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0807c500 LY |
1 | /* |
2 | * Copyright (C) 2007,2008 Freescale semiconductor, Inc. | |
3 | * | |
4 | * Author: Li Yang <LeoLi@freescale.com> | |
5 | * Jerry Huang <Chang-Ming.Huang@freescale.com> | |
6 | * | |
7 | * Initialization based on code from Shlomi Gridish. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, write to the Free Software Foundation, Inc., | |
21 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/proc_fs.h> | |
29 | #include <linux/errno.h> | |
0807c500 LY |
30 | #include <linux/interrupt.h> |
31 | #include <linux/io.h> | |
32 | #include <linux/timer.h> | |
33 | #include <linux/usb.h> | |
34 | #include <linux/device.h> | |
35 | #include <linux/usb/ch9.h> | |
36 | #include <linux/usb/gadget.h> | |
37 | #include <linux/workqueue.h> | |
38 | #include <linux/time.h> | |
39 | #include <linux/fsl_devices.h> | |
40 | #include <linux/platform_device.h> | |
41 | #include <linux/uaccess.h> | |
42 | ||
43 | #include <asm/unaligned.h> | |
44 | ||
94ae9843 | 45 | #include "phy-fsl-usb.h" |
0807c500 LY |
46 | |
47 | #define DRIVER_VERSION "Rev. 1.55" | |
48 | #define DRIVER_AUTHOR "Jerry Huang/Li Yang" | |
49 | #define DRIVER_DESC "Freescale USB OTG Transceiver Driver" | |
50 | #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION | |
51 | ||
52 | static const char driver_name[] = "fsl-usb2-otg"; | |
53 | ||
54 | const pm_message_t otg_suspend_state = { | |
55 | .event = 1, | |
56 | }; | |
57 | ||
58 | #define HA_DATA_PULSE | |
59 | ||
60 | static struct usb_dr_mmap *usb_dr_regs; | |
61 | static struct fsl_otg *fsl_otg_dev; | |
62 | static int srp_wait_done; | |
63 | ||
64 | /* FSM timers */ | |
65 | struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr, | |
66 | *b_ase0_brst_tmr, *b_se0_srp_tmr; | |
67 | ||
68 | /* Driver specific timers */ | |
69 | struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr, | |
70 | *b_srp_wait_tmr, *a_wait_enum_tmr; | |
71 | ||
72 | static struct list_head active_timers; | |
73 | ||
74 | static struct fsl_otg_config fsl_otg_initdata = { | |
75 | .otg_port = 1, | |
76 | }; | |
77 | ||
78 | #ifdef CONFIG_PPC32 | |
79 | static u32 _fsl_readl_be(const unsigned __iomem *p) | |
80 | { | |
81 | return in_be32(p); | |
82 | } | |
83 | ||
84 | static u32 _fsl_readl_le(const unsigned __iomem *p) | |
85 | { | |
86 | return in_le32(p); | |
87 | } | |
88 | ||
89 | static void _fsl_writel_be(u32 v, unsigned __iomem *p) | |
90 | { | |
91 | out_be32(p, v); | |
92 | } | |
93 | ||
94 | static void _fsl_writel_le(u32 v, unsigned __iomem *p) | |
95 | { | |
96 | out_le32(p, v); | |
97 | } | |
98 | ||
99 | static u32 (*_fsl_readl)(const unsigned __iomem *p); | |
100 | static void (*_fsl_writel)(u32 v, unsigned __iomem *p); | |
101 | ||
102 | #define fsl_readl(p) (*_fsl_readl)((p)) | |
103 | #define fsl_writel(v, p) (*_fsl_writel)((v), (p)) | |
104 | ||
105 | #else | |
106 | #define fsl_readl(addr) readl(addr) | |
107 | #define fsl_writel(val, addr) writel(val, addr) | |
108 | #endif /* CONFIG_PPC32 */ | |
109 | ||
110 | /* Routines to access transceiver ULPI registers */ | |
111 | u8 view_ulpi(u8 addr) | |
112 | { | |
113 | u32 temp; | |
114 | ||
115 | temp = 0x40000000 | (addr << 16); | |
116 | fsl_writel(temp, &usb_dr_regs->ulpiview); | |
117 | udelay(1000); | |
118 | while (temp & 0x40) | |
119 | temp = fsl_readl(&usb_dr_regs->ulpiview); | |
120 | return (le32_to_cpu(temp) & 0x0000ff00) >> 8; | |
121 | } | |
122 | ||
123 | int write_ulpi(u8 addr, u8 data) | |
124 | { | |
125 | u32 temp; | |
126 | ||
127 | temp = 0x60000000 | (addr << 16) | data; | |
128 | fsl_writel(temp, &usb_dr_regs->ulpiview); | |
129 | return 0; | |
130 | } | |
131 | ||
132 | /* -------------------------------------------------------------*/ | |
133 | /* Operations that will be called from OTG Finite State Machine */ | |
134 | ||
135 | /* Charge vbus for vbus pulsing in SRP */ | |
da8cc167 | 136 | void fsl_otg_chrg_vbus(struct otg_fsm *fsm, int on) |
0807c500 LY |
137 | { |
138 | u32 tmp; | |
139 | ||
140 | tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; | |
141 | ||
142 | if (on) | |
143 | /* stop discharging, start charging */ | |
144 | tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) | | |
145 | OTGSC_CTRL_VBUS_CHARGE; | |
146 | else | |
147 | /* stop charging */ | |
148 | tmp &= ~OTGSC_CTRL_VBUS_CHARGE; | |
149 | ||
150 | fsl_writel(tmp, &usb_dr_regs->otgsc); | |
151 | } | |
152 | ||
153 | /* Discharge vbus through a resistor to ground */ | |
154 | void fsl_otg_dischrg_vbus(int on) | |
155 | { | |
156 | u32 tmp; | |
157 | ||
158 | tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; | |
159 | ||
160 | if (on) | |
161 | /* stop charging, start discharging */ | |
162 | tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) | | |
163 | OTGSC_CTRL_VBUS_DISCHARGE; | |
164 | else | |
165 | /* stop discharging */ | |
166 | tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE; | |
167 | ||
168 | fsl_writel(tmp, &usb_dr_regs->otgsc); | |
169 | } | |
170 | ||
171 | /* A-device driver vbus, controlled through PP bit in PORTSC */ | |
da8cc167 | 172 | void fsl_otg_drv_vbus(struct otg_fsm *fsm, int on) |
0807c500 LY |
173 | { |
174 | u32 tmp; | |
175 | ||
176 | if (on) { | |
177 | tmp = fsl_readl(&usb_dr_regs->portsc) & ~PORTSC_W1C_BITS; | |
178 | fsl_writel(tmp | PORTSC_PORT_POWER, &usb_dr_regs->portsc); | |
179 | } else { | |
180 | tmp = fsl_readl(&usb_dr_regs->portsc) & | |
181 | ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER; | |
182 | fsl_writel(tmp, &usb_dr_regs->portsc); | |
183 | } | |
184 | } | |
185 | ||
186 | /* | |
187 | * Pull-up D+, signalling connect by periperal. Also used in | |
188 | * data-line pulsing in SRP | |
189 | */ | |
da8cc167 | 190 | void fsl_otg_loc_conn(struct otg_fsm *fsm, int on) |
0807c500 LY |
191 | { |
192 | u32 tmp; | |
193 | ||
194 | tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; | |
195 | ||
196 | if (on) | |
197 | tmp |= OTGSC_CTRL_DATA_PULSING; | |
198 | else | |
199 | tmp &= ~OTGSC_CTRL_DATA_PULSING; | |
200 | ||
201 | fsl_writel(tmp, &usb_dr_regs->otgsc); | |
202 | } | |
203 | ||
204 | /* | |
205 | * Generate SOF by host. This is controlled through suspend/resume the | |
206 | * port. In host mode, controller will automatically send SOF. | |
207 | * Suspend will block the data on the port. | |
208 | */ | |
da8cc167 | 209 | void fsl_otg_loc_sof(struct otg_fsm *fsm, int on) |
0807c500 LY |
210 | { |
211 | u32 tmp; | |
212 | ||
213 | tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS; | |
214 | if (on) | |
215 | tmp |= PORTSC_PORT_FORCE_RESUME; | |
216 | else | |
217 | tmp |= PORTSC_PORT_SUSPEND; | |
218 | ||
219 | fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc); | |
220 | ||
221 | } | |
222 | ||
223 | /* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */ | |
da8cc167 | 224 | void fsl_otg_start_pulse(struct otg_fsm *fsm) |
0807c500 LY |
225 | { |
226 | u32 tmp; | |
227 | ||
228 | srp_wait_done = 0; | |
229 | #ifdef HA_DATA_PULSE | |
230 | tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; | |
231 | tmp |= OTGSC_HA_DATA_PULSE; | |
232 | fsl_writel(tmp, &usb_dr_regs->otgsc); | |
233 | #else | |
234 | fsl_otg_loc_conn(1); | |
235 | #endif | |
236 | ||
da8cc167 | 237 | fsl_otg_add_timer(fsm, b_data_pulse_tmr); |
0807c500 LY |
238 | } |
239 | ||
240 | void b_data_pulse_end(unsigned long foo) | |
241 | { | |
242 | #ifdef HA_DATA_PULSE | |
243 | #else | |
244 | fsl_otg_loc_conn(0); | |
245 | #endif | |
246 | ||
247 | /* Do VBUS pulse after data pulse */ | |
248 | fsl_otg_pulse_vbus(); | |
249 | } | |
250 | ||
251 | void fsl_otg_pulse_vbus(void) | |
252 | { | |
253 | srp_wait_done = 0; | |
da8cc167 | 254 | fsl_otg_chrg_vbus(&fsl_otg_dev->fsm, 1); |
0807c500 | 255 | /* start the timer to end vbus charge */ |
da8cc167 | 256 | fsl_otg_add_timer(&fsl_otg_dev->fsm, b_vbus_pulse_tmr); |
0807c500 LY |
257 | } |
258 | ||
259 | void b_vbus_pulse_end(unsigned long foo) | |
260 | { | |
da8cc167 | 261 | fsl_otg_chrg_vbus(&fsl_otg_dev->fsm, 0); |
0807c500 LY |
262 | |
263 | /* | |
264 | * As USB3300 using the same a_sess_vld and b_sess_vld voltage | |
265 | * we need to discharge the bus for a while to distinguish | |
266 | * residual voltage of vbus pulsing and A device pull up | |
267 | */ | |
268 | fsl_otg_dischrg_vbus(1); | |
da8cc167 | 269 | fsl_otg_add_timer(&fsl_otg_dev->fsm, b_srp_wait_tmr); |
0807c500 LY |
270 | } |
271 | ||
272 | void b_srp_end(unsigned long foo) | |
273 | { | |
274 | fsl_otg_dischrg_vbus(0); | |
275 | srp_wait_done = 1; | |
276 | ||
e5ba1c02 | 277 | if ((fsl_otg_dev->phy.otg->state == OTG_STATE_B_SRP_INIT) && |
0807c500 LY |
278 | fsl_otg_dev->fsm.b_sess_vld) |
279 | fsl_otg_dev->fsm.b_srp_done = 1; | |
280 | } | |
281 | ||
282 | /* | |
283 | * Workaround for a_host suspending too fast. When a_bus_req=0, | |
284 | * a_host will start by SRP. It needs to set b_hnp_enable before | |
285 | * actually suspending to start HNP | |
286 | */ | |
287 | void a_wait_enum(unsigned long foo) | |
288 | { | |
289 | VDBG("a_wait_enum timeout\n"); | |
7e062c0f | 290 | if (!fsl_otg_dev->phy.otg->host->b_hnp_enable) |
da8cc167 | 291 | fsl_otg_add_timer(&fsl_otg_dev->fsm, a_wait_enum_tmr); |
0807c500 LY |
292 | else |
293 | otg_statemachine(&fsl_otg_dev->fsm); | |
294 | } | |
295 | ||
296 | /* The timeout callback function to set time out bit */ | |
297 | void set_tmout(unsigned long indicator) | |
298 | { | |
299 | *(int *)indicator = 1; | |
300 | } | |
301 | ||
302 | /* Initialize timers */ | |
303 | int fsl_otg_init_timers(struct otg_fsm *fsm) | |
304 | { | |
305 | /* FSM used timers */ | |
306 | a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE, | |
307 | (unsigned long)&fsm->a_wait_vrise_tmout); | |
308 | if (!a_wait_vrise_tmr) | |
309 | return -ENOMEM; | |
310 | ||
311 | a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON, | |
312 | (unsigned long)&fsm->a_wait_bcon_tmout); | |
313 | if (!a_wait_bcon_tmr) | |
314 | return -ENOMEM; | |
315 | ||
316 | a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS, | |
317 | (unsigned long)&fsm->a_aidl_bdis_tmout); | |
318 | if (!a_aidl_bdis_tmr) | |
319 | return -ENOMEM; | |
320 | ||
321 | b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST, | |
322 | (unsigned long)&fsm->b_ase0_brst_tmout); | |
323 | if (!b_ase0_brst_tmr) | |
324 | return -ENOMEM; | |
325 | ||
326 | b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP, | |
327 | (unsigned long)&fsm->b_se0_srp); | |
328 | if (!b_se0_srp_tmr) | |
329 | return -ENOMEM; | |
330 | ||
331 | b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL, | |
332 | (unsigned long)&fsm->b_srp_done); | |
333 | if (!b_srp_fail_tmr) | |
334 | return -ENOMEM; | |
335 | ||
336 | a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10, | |
337 | (unsigned long)&fsm); | |
338 | if (!a_wait_enum_tmr) | |
339 | return -ENOMEM; | |
340 | ||
341 | /* device driver used timers */ | |
342 | b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0); | |
343 | if (!b_srp_wait_tmr) | |
344 | return -ENOMEM; | |
345 | ||
346 | b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end, | |
347 | TB_DATA_PLS, 0); | |
348 | if (!b_data_pulse_tmr) | |
349 | return -ENOMEM; | |
350 | ||
351 | b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end, | |
352 | TB_VBUS_PLS, 0); | |
353 | if (!b_vbus_pulse_tmr) | |
354 | return -ENOMEM; | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | /* Uninitialize timers */ | |
360 | void fsl_otg_uninit_timers(void) | |
361 | { | |
362 | /* FSM used timers */ | |
5f717919 SS |
363 | kfree(a_wait_vrise_tmr); |
364 | kfree(a_wait_bcon_tmr); | |
365 | kfree(a_aidl_bdis_tmr); | |
366 | kfree(b_ase0_brst_tmr); | |
367 | kfree(b_se0_srp_tmr); | |
368 | kfree(b_srp_fail_tmr); | |
369 | kfree(a_wait_enum_tmr); | |
0807c500 LY |
370 | |
371 | /* device driver used timers */ | |
5f717919 SS |
372 | kfree(b_srp_wait_tmr); |
373 | kfree(b_data_pulse_tmr); | |
374 | kfree(b_vbus_pulse_tmr); | |
0807c500 LY |
375 | } |
376 | ||
f6de27ee AT |
377 | static struct fsl_otg_timer *fsl_otg_get_timer(enum otg_fsm_timer t) |
378 | { | |
379 | struct fsl_otg_timer *timer; | |
380 | ||
381 | /* REVISIT: use array of pointers to timers instead */ | |
382 | switch (t) { | |
383 | case A_WAIT_VRISE: | |
384 | timer = a_wait_vrise_tmr; | |
385 | break; | |
386 | case A_WAIT_BCON: | |
387 | timer = a_wait_vrise_tmr; | |
388 | break; | |
389 | case A_AIDL_BDIS: | |
390 | timer = a_wait_vrise_tmr; | |
391 | break; | |
392 | case B_ASE0_BRST: | |
393 | timer = a_wait_vrise_tmr; | |
394 | break; | |
395 | case B_SE0_SRP: | |
396 | timer = a_wait_vrise_tmr; | |
397 | break; | |
398 | case B_SRP_FAIL: | |
399 | timer = a_wait_vrise_tmr; | |
400 | break; | |
401 | case A_WAIT_ENUM: | |
402 | timer = a_wait_vrise_tmr; | |
403 | break; | |
404 | default: | |
405 | timer = NULL; | |
406 | } | |
407 | ||
408 | return timer; | |
409 | } | |
410 | ||
0807c500 | 411 | /* Add timer to timer list */ |
da8cc167 | 412 | void fsl_otg_add_timer(struct otg_fsm *fsm, void *gtimer) |
0807c500 LY |
413 | { |
414 | struct fsl_otg_timer *timer = gtimer; | |
415 | struct fsl_otg_timer *tmp_timer; | |
416 | ||
417 | /* | |
418 | * Check if the timer is already in the active list, | |
419 | * if so update timer count | |
420 | */ | |
421 | list_for_each_entry(tmp_timer, &active_timers, list) | |
422 | if (tmp_timer == timer) { | |
423 | timer->count = timer->expires; | |
424 | return; | |
425 | } | |
426 | timer->count = timer->expires; | |
427 | list_add_tail(&timer->list, &active_timers); | |
428 | } | |
429 | ||
f6de27ee AT |
430 | static void fsl_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t) |
431 | { | |
432 | struct fsl_otg_timer *timer; | |
433 | ||
434 | timer = fsl_otg_get_timer(t); | |
435 | if (!timer) | |
436 | return; | |
437 | ||
438 | fsl_otg_add_timer(fsm, timer); | |
439 | } | |
440 | ||
0807c500 | 441 | /* Remove timer from the timer list; clear timeout status */ |
da8cc167 | 442 | void fsl_otg_del_timer(struct otg_fsm *fsm, void *gtimer) |
0807c500 LY |
443 | { |
444 | struct fsl_otg_timer *timer = gtimer; | |
445 | struct fsl_otg_timer *tmp_timer, *del_tmp; | |
446 | ||
447 | list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) | |
448 | if (tmp_timer == timer) | |
449 | list_del(&timer->list); | |
450 | } | |
451 | ||
f6de27ee AT |
452 | static void fsl_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t) |
453 | { | |
454 | struct fsl_otg_timer *timer; | |
455 | ||
456 | timer = fsl_otg_get_timer(t); | |
457 | if (!timer) | |
458 | return; | |
459 | ||
460 | fsl_otg_del_timer(fsm, timer); | |
461 | } | |
462 | ||
0807c500 LY |
463 | /* |
464 | * Reduce timer count by 1, and find timeout conditions. | |
465 | * Called by fsl_otg 1ms timer interrupt | |
466 | */ | |
467 | int fsl_otg_tick_timer(void) | |
468 | { | |
469 | struct fsl_otg_timer *tmp_timer, *del_tmp; | |
470 | int expired = 0; | |
471 | ||
472 | list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) { | |
473 | tmp_timer->count--; | |
474 | /* check if timer expires */ | |
475 | if (!tmp_timer->count) { | |
476 | list_del(&tmp_timer->list); | |
477 | tmp_timer->function(tmp_timer->data); | |
478 | expired = 1; | |
479 | } | |
480 | } | |
481 | ||
482 | return expired; | |
483 | } | |
484 | ||
485 | /* Reset controller, not reset the bus */ | |
486 | void otg_reset_controller(void) | |
487 | { | |
488 | u32 command; | |
489 | ||
490 | command = fsl_readl(&usb_dr_regs->usbcmd); | |
491 | command |= (1 << 1); | |
492 | fsl_writel(command, &usb_dr_regs->usbcmd); | |
493 | while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1)) | |
494 | ; | |
495 | } | |
496 | ||
497 | /* Call suspend/resume routines in host driver */ | |
498 | int fsl_otg_start_host(struct otg_fsm *fsm, int on) | |
499 | { | |
7e062c0f | 500 | struct usb_otg *otg = fsm->otg; |
0807c500 | 501 | struct device *dev; |
19c1eac2 AT |
502 | struct fsl_otg *otg_dev = |
503 | container_of(otg->usb_phy, struct fsl_otg, phy); | |
0807c500 LY |
504 | u32 retval = 0; |
505 | ||
7e062c0f | 506 | if (!otg->host) |
0807c500 | 507 | return -ENODEV; |
7e062c0f | 508 | dev = otg->host->controller; |
0807c500 LY |
509 | |
510 | /* | |
511 | * Update a_vbus_vld state as a_vbus_vld int is disabled | |
512 | * in device mode | |
513 | */ | |
514 | fsm->a_vbus_vld = | |
515 | !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID); | |
516 | if (on) { | |
517 | /* start fsl usb host controller */ | |
518 | if (otg_dev->host_working) | |
519 | goto end; | |
520 | else { | |
521 | otg_reset_controller(); | |
522 | VDBG("host on......\n"); | |
523 | if (dev->driver->pm && dev->driver->pm->resume) { | |
524 | retval = dev->driver->pm->resume(dev); | |
525 | if (fsm->id) { | |
526 | /* default-b */ | |
da8cc167 | 527 | fsl_otg_drv_vbus(fsm, 1); |
0807c500 LY |
528 | /* |
529 | * Workaround: b_host can't driver | |
530 | * vbus, but PP in PORTSC needs to | |
531 | * be 1 for host to work. | |
532 | * So we set drv_vbus bit in | |
533 | * transceiver to 0 thru ULPI. | |
534 | */ | |
535 | write_ulpi(0x0c, 0x20); | |
536 | } | |
537 | } | |
538 | ||
539 | otg_dev->host_working = 1; | |
540 | } | |
541 | } else { | |
542 | /* stop fsl usb host controller */ | |
543 | if (!otg_dev->host_working) | |
544 | goto end; | |
545 | else { | |
546 | VDBG("host off......\n"); | |
547 | if (dev && dev->driver) { | |
548 | if (dev->driver->pm && dev->driver->pm->suspend) | |
549 | retval = dev->driver->pm->suspend(dev); | |
550 | if (fsm->id) | |
551 | /* default-b */ | |
da8cc167 | 552 | fsl_otg_drv_vbus(fsm, 0); |
0807c500 LY |
553 | } |
554 | otg_dev->host_working = 0; | |
555 | } | |
556 | } | |
557 | end: | |
558 | return retval; | |
559 | } | |
560 | ||
561 | /* | |
562 | * Call suspend and resume function in udc driver | |
563 | * to stop and start udc driver. | |
564 | */ | |
565 | int fsl_otg_start_gadget(struct otg_fsm *fsm, int on) | |
566 | { | |
7e062c0f | 567 | struct usb_otg *otg = fsm->otg; |
0807c500 LY |
568 | struct device *dev; |
569 | ||
7e062c0f | 570 | if (!otg->gadget || !otg->gadget->dev.parent) |
0807c500 LY |
571 | return -ENODEV; |
572 | ||
573 | VDBG("gadget %s\n", on ? "on" : "off"); | |
7e062c0f | 574 | dev = otg->gadget->dev.parent; |
0807c500 LY |
575 | |
576 | if (on) { | |
577 | if (dev->driver->resume) | |
578 | dev->driver->resume(dev); | |
579 | } else { | |
580 | if (dev->driver->suspend) | |
581 | dev->driver->suspend(dev, otg_suspend_state); | |
582 | } | |
583 | ||
584 | return 0; | |
585 | } | |
586 | ||
587 | /* | |
588 | * Called by initialization code of host driver. Register host controller | |
589 | * to the OTG. Suspend host for OTG role detection. | |
590 | */ | |
7e062c0f | 591 | static int fsl_otg_set_host(struct usb_otg *otg, struct usb_bus *host) |
0807c500 | 592 | { |
58add6ca WY |
593 | struct fsl_otg *otg_dev; |
594 | ||
595 | if (!otg) | |
596 | return -ENODEV; | |
0807c500 | 597 | |
19c1eac2 | 598 | otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy); |
58add6ca | 599 | if (otg_dev != fsl_otg_dev) |
0807c500 LY |
600 | return -ENODEV; |
601 | ||
7e062c0f | 602 | otg->host = host; |
0807c500 LY |
603 | |
604 | otg_dev->fsm.a_bus_drop = 0; | |
605 | otg_dev->fsm.a_bus_req = 1; | |
606 | ||
607 | if (host) { | |
608 | VDBG("host off......\n"); | |
609 | ||
7e062c0f HK |
610 | otg->host->otg_port = fsl_otg_initdata.otg_port; |
611 | otg->host->is_b_host = otg_dev->fsm.id; | |
0807c500 | 612 | /* |
37ebb549 | 613 | * must leave time for hub_wq to finish its thing |
0807c500 LY |
614 | * before yanking the host driver out from under it, |
615 | * so suspend the host after a short delay. | |
616 | */ | |
617 | otg_dev->host_working = 1; | |
618 | schedule_delayed_work(&otg_dev->otg_event, 100); | |
619 | return 0; | |
620 | } else { | |
621 | /* host driver going away */ | |
622 | if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) & | |
623 | OTGSC_STS_USB_ID)) { | |
624 | /* Mini-A cable connected */ | |
625 | struct otg_fsm *fsm = &otg_dev->fsm; | |
626 | ||
e5ba1c02 | 627 | otg->state = OTG_STATE_UNDEFINED; |
0807c500 LY |
628 | fsm->protocol = PROTO_UNDEF; |
629 | } | |
630 | } | |
631 | ||
632 | otg_dev->host_working = 0; | |
633 | ||
634 | otg_statemachine(&otg_dev->fsm); | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
639 | /* Called by initialization code of udc. Register udc to OTG. */ | |
7e062c0f HK |
640 | static int fsl_otg_set_peripheral(struct usb_otg *otg, |
641 | struct usb_gadget *gadget) | |
0807c500 | 642 | { |
58add6ca | 643 | struct fsl_otg *otg_dev; |
0807c500 | 644 | |
58add6ca WY |
645 | if (!otg) |
646 | return -ENODEV; | |
647 | ||
19c1eac2 | 648 | otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy); |
0807c500 LY |
649 | VDBG("otg_dev 0x%x\n", (int)otg_dev); |
650 | VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev); | |
58add6ca | 651 | if (otg_dev != fsl_otg_dev) |
0807c500 LY |
652 | return -ENODEV; |
653 | ||
654 | if (!gadget) { | |
7e062c0f HK |
655 | if (!otg->default_a) |
656 | otg->gadget->ops->vbus_draw(otg->gadget, 0); | |
657 | usb_gadget_vbus_disconnect(otg->gadget); | |
658 | otg->gadget = 0; | |
0807c500 LY |
659 | otg_dev->fsm.b_bus_req = 0; |
660 | otg_statemachine(&otg_dev->fsm); | |
661 | return 0; | |
662 | } | |
663 | ||
7e062c0f HK |
664 | otg->gadget = gadget; |
665 | otg->gadget->is_a_peripheral = !otg_dev->fsm.id; | |
0807c500 LY |
666 | |
667 | otg_dev->fsm.b_bus_req = 1; | |
668 | ||
669 | /* start the gadget right away if the ID pin says Mini-B */ | |
523e531e | 670 | pr_debug("ID pin=%d\n", otg_dev->fsm.id); |
0807c500 LY |
671 | if (otg_dev->fsm.id == 1) { |
672 | fsl_otg_start_host(&otg_dev->fsm, 0); | |
673 | otg_drv_vbus(&otg_dev->fsm, 0); | |
674 | fsl_otg_start_gadget(&otg_dev->fsm, 1); | |
675 | } | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | /* Set OTG port power, only for B-device */ | |
7e062c0f | 681 | static int fsl_otg_set_power(struct usb_phy *phy, unsigned mA) |
0807c500 LY |
682 | { |
683 | if (!fsl_otg_dev) | |
684 | return -ENODEV; | |
e5ba1c02 | 685 | if (phy->otg->state == OTG_STATE_B_PERIPHERAL) |
0807c500 LY |
686 | pr_info("FSL OTG: Draw %d mA\n", mA); |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | /* | |
692 | * Delayed pin detect interrupt processing. | |
693 | * | |
694 | * When the Mini-A cable is disconnected from the board, | |
42b2aa86 | 695 | * the pin-detect interrupt happens before the disconnect |
0807c500 LY |
696 | * interrupts for the connected device(s). In order to |
697 | * process the disconnect interrupt(s) prior to switching | |
698 | * roles, the pin-detect interrupts are delayed, and handled | |
699 | * by this routine. | |
700 | */ | |
701 | static void fsl_otg_event(struct work_struct *work) | |
702 | { | |
703 | struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work); | |
704 | struct otg_fsm *fsm = &og->fsm; | |
705 | ||
706 | if (fsm->id) { /* switch to gadget */ | |
707 | fsl_otg_start_host(fsm, 0); | |
708 | otg_drv_vbus(fsm, 0); | |
709 | fsl_otg_start_gadget(fsm, 1); | |
710 | } | |
711 | } | |
712 | ||
713 | /* B-device start SRP */ | |
7e062c0f | 714 | static int fsl_otg_start_srp(struct usb_otg *otg) |
0807c500 | 715 | { |
58add6ca WY |
716 | struct fsl_otg *otg_dev; |
717 | ||
e5ba1c02 | 718 | if (!otg || otg->state != OTG_STATE_B_IDLE) |
58add6ca | 719 | return -ENODEV; |
0807c500 | 720 | |
19c1eac2 | 721 | otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy); |
58add6ca | 722 | if (otg_dev != fsl_otg_dev) |
0807c500 LY |
723 | return -ENODEV; |
724 | ||
725 | otg_dev->fsm.b_bus_req = 1; | |
726 | otg_statemachine(&otg_dev->fsm); | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
731 | /* A_host suspend will call this function to start hnp */ | |
7e062c0f | 732 | static int fsl_otg_start_hnp(struct usb_otg *otg) |
0807c500 | 733 | { |
58add6ca WY |
734 | struct fsl_otg *otg_dev; |
735 | ||
736 | if (!otg) | |
737 | return -ENODEV; | |
0807c500 | 738 | |
19c1eac2 | 739 | otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy); |
58add6ca | 740 | if (otg_dev != fsl_otg_dev) |
0807c500 LY |
741 | return -ENODEV; |
742 | ||
523e531e | 743 | pr_debug("start_hnp...\n"); |
0807c500 LY |
744 | |
745 | /* clear a_bus_req to enter a_suspend state */ | |
746 | otg_dev->fsm.a_bus_req = 0; | |
747 | otg_statemachine(&otg_dev->fsm); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | /* | |
753 | * Interrupt handler. OTG/host/peripheral share the same int line. | |
754 | * OTG driver clears OTGSC interrupts and leaves USB interrupts | |
755 | * intact. It needs to have knowledge of some USB interrupts | |
756 | * such as port change. | |
757 | */ | |
758 | irqreturn_t fsl_otg_isr(int irq, void *dev_id) | |
759 | { | |
760 | struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm; | |
7e062c0f | 761 | struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg; |
0807c500 LY |
762 | u32 otg_int_src, otg_sc; |
763 | ||
764 | otg_sc = fsl_readl(&usb_dr_regs->otgsc); | |
765 | otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8); | |
766 | ||
767 | /* Only clear otg interrupts */ | |
768 | fsl_writel(otg_sc, &usb_dr_regs->otgsc); | |
769 | ||
770 | /*FIXME: ID change not generate when init to 0 */ | |
771 | fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0; | |
772 | otg->default_a = (fsm->id == 0); | |
773 | ||
774 | /* process OTG interrupts */ | |
775 | if (otg_int_src) { | |
776 | if (otg_int_src & OTGSC_INTSTS_USB_ID) { | |
777 | fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0; | |
778 | otg->default_a = (fsm->id == 0); | |
779 | /* clear conn information */ | |
780 | if (fsm->id) | |
781 | fsm->b_conn = 0; | |
782 | else | |
783 | fsm->a_conn = 0; | |
784 | ||
785 | if (otg->host) | |
786 | otg->host->is_b_host = fsm->id; | |
787 | if (otg->gadget) | |
788 | otg->gadget->is_a_peripheral = !fsm->id; | |
789 | VDBG("ID int (ID is %d)\n", fsm->id); | |
790 | ||
791 | if (fsm->id) { /* switch to gadget */ | |
792 | schedule_delayed_work( | |
793 | &((struct fsl_otg *)dev_id)->otg_event, | |
794 | 100); | |
795 | } else { /* switch to host */ | |
796 | cancel_delayed_work(& | |
797 | ((struct fsl_otg *)dev_id)-> | |
798 | otg_event); | |
799 | fsl_otg_start_gadget(fsm, 0); | |
800 | otg_drv_vbus(fsm, 1); | |
801 | fsl_otg_start_host(fsm, 1); | |
802 | } | |
803 | return IRQ_HANDLED; | |
804 | } | |
805 | } | |
806 | return IRQ_NONE; | |
807 | } | |
808 | ||
809 | static struct otg_fsm_ops fsl_otg_ops = { | |
810 | .chrg_vbus = fsl_otg_chrg_vbus, | |
811 | .drv_vbus = fsl_otg_drv_vbus, | |
812 | .loc_conn = fsl_otg_loc_conn, | |
813 | .loc_sof = fsl_otg_loc_sof, | |
814 | .start_pulse = fsl_otg_start_pulse, | |
815 | ||
f6de27ee AT |
816 | .add_timer = fsl_otg_fsm_add_timer, |
817 | .del_timer = fsl_otg_fsm_del_timer, | |
0807c500 LY |
818 | |
819 | .start_host = fsl_otg_start_host, | |
820 | .start_gadget = fsl_otg_start_gadget, | |
821 | }; | |
822 | ||
823 | /* Initialize the global variable fsl_otg_dev and request IRQ for OTG */ | |
824 | static int fsl_otg_conf(struct platform_device *pdev) | |
825 | { | |
826 | struct fsl_otg *fsl_otg_tc; | |
827 | int status; | |
828 | ||
829 | if (fsl_otg_dev) | |
830 | return 0; | |
831 | ||
832 | /* allocate space to fsl otg device */ | |
833 | fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL); | |
834 | if (!fsl_otg_tc) | |
835 | return -ENOMEM; | |
836 | ||
7e062c0f HK |
837 | fsl_otg_tc->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL); |
838 | if (!fsl_otg_tc->phy.otg) { | |
839 | kfree(fsl_otg_tc); | |
840 | return -ENOMEM; | |
841 | } | |
842 | ||
0807c500 LY |
843 | INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event); |
844 | ||
845 | INIT_LIST_HEAD(&active_timers); | |
846 | status = fsl_otg_init_timers(&fsl_otg_tc->fsm); | |
847 | if (status) { | |
848 | pr_info("Couldn't init OTG timers\n"); | |
849 | goto err; | |
850 | } | |
16e569e9 | 851 | mutex_init(&fsl_otg_tc->fsm.lock); |
0807c500 LY |
852 | |
853 | /* Set OTG state machine operations */ | |
854 | fsl_otg_tc->fsm.ops = &fsl_otg_ops; | |
855 | ||
856 | /* initialize the otg structure */ | |
7e062c0f | 857 | fsl_otg_tc->phy.label = DRIVER_DESC; |
1abd8b31 | 858 | fsl_otg_tc->phy.dev = &pdev->dev; |
7e062c0f HK |
859 | fsl_otg_tc->phy.set_power = fsl_otg_set_power; |
860 | ||
19c1eac2 | 861 | fsl_otg_tc->phy.otg->usb_phy = &fsl_otg_tc->phy; |
7e062c0f HK |
862 | fsl_otg_tc->phy.otg->set_host = fsl_otg_set_host; |
863 | fsl_otg_tc->phy.otg->set_peripheral = fsl_otg_set_peripheral; | |
864 | fsl_otg_tc->phy.otg->start_hnp = fsl_otg_start_hnp; | |
865 | fsl_otg_tc->phy.otg->start_srp = fsl_otg_start_srp; | |
0807c500 LY |
866 | |
867 | fsl_otg_dev = fsl_otg_tc; | |
868 | ||
869 | /* Store the otg transceiver */ | |
662dca54 | 870 | status = usb_add_phy(&fsl_otg_tc->phy, USB_PHY_TYPE_USB2); |
0807c500 LY |
871 | if (status) { |
872 | pr_warn(FSL_OTG_NAME ": unable to register OTG transceiver.\n"); | |
873 | goto err; | |
874 | } | |
875 | ||
876 | return 0; | |
877 | err: | |
878 | fsl_otg_uninit_timers(); | |
7e062c0f | 879 | kfree(fsl_otg_tc->phy.otg); |
0807c500 LY |
880 | kfree(fsl_otg_tc); |
881 | return status; | |
882 | } | |
883 | ||
884 | /* OTG Initialization */ | |
885 | int usb_otg_start(struct platform_device *pdev) | |
886 | { | |
887 | struct fsl_otg *p_otg; | |
662dca54 | 888 | struct usb_phy *otg_trans = usb_get_phy(USB_PHY_TYPE_USB2); |
0807c500 LY |
889 | struct otg_fsm *fsm; |
890 | int status; | |
891 | struct resource *res; | |
892 | u32 temp; | |
19f9e188 | 893 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0807c500 | 894 | |
7e062c0f | 895 | p_otg = container_of(otg_trans, struct fsl_otg, phy); |
0807c500 LY |
896 | fsm = &p_otg->fsm; |
897 | ||
898 | /* Initialize the state machine structure with default values */ | |
899 | SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED); | |
7e062c0f | 900 | fsm->otg = p_otg->phy.otg; |
0807c500 LY |
901 | |
902 | /* We don't require predefined MEM/IRQ resource index */ | |
903 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
904 | if (!res) | |
905 | return -ENXIO; | |
906 | ||
907 | /* We don't request_mem_region here to enable resource sharing | |
908 | * with host/device */ | |
909 | ||
910 | usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap)); | |
911 | p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs; | |
912 | pdata->regs = (void *)usb_dr_regs; | |
913 | ||
914 | if (pdata->init && pdata->init(pdev) != 0) | |
915 | return -EINVAL; | |
916 | ||
917 | if (pdata->big_endian_mmio) { | |
918 | _fsl_readl = _fsl_readl_be; | |
919 | _fsl_writel = _fsl_writel_be; | |
920 | } else { | |
921 | _fsl_readl = _fsl_readl_le; | |
922 | _fsl_writel = _fsl_writel_le; | |
923 | } | |
924 | ||
925 | /* request irq */ | |
926 | p_otg->irq = platform_get_irq(pdev, 0); | |
927 | status = request_irq(p_otg->irq, fsl_otg_isr, | |
928 | IRQF_SHARED, driver_name, p_otg); | |
929 | if (status) { | |
7e062c0f | 930 | dev_dbg(p_otg->phy.dev, "can't get IRQ %d, error %d\n", |
0807c500 LY |
931 | p_otg->irq, status); |
932 | iounmap(p_otg->dr_mem_map); | |
7e062c0f | 933 | kfree(p_otg->phy.otg); |
0807c500 LY |
934 | kfree(p_otg); |
935 | return status; | |
936 | } | |
937 | ||
938 | /* stop the controller */ | |
939 | temp = fsl_readl(&p_otg->dr_mem_map->usbcmd); | |
940 | temp &= ~USB_CMD_RUN_STOP; | |
941 | fsl_writel(temp, &p_otg->dr_mem_map->usbcmd); | |
942 | ||
943 | /* reset the controller */ | |
944 | temp = fsl_readl(&p_otg->dr_mem_map->usbcmd); | |
945 | temp |= USB_CMD_CTRL_RESET; | |
946 | fsl_writel(temp, &p_otg->dr_mem_map->usbcmd); | |
947 | ||
948 | /* wait reset completed */ | |
949 | while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET) | |
950 | ; | |
951 | ||
952 | /* configure the VBUSHS as IDLE(both host and device) */ | |
953 | temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0); | |
954 | fsl_writel(temp, &p_otg->dr_mem_map->usbmode); | |
955 | ||
956 | /* configure PHY interface */ | |
957 | temp = fsl_readl(&p_otg->dr_mem_map->portsc); | |
958 | temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW); | |
959 | switch (pdata->phy_mode) { | |
960 | case FSL_USB2_PHY_ULPI: | |
961 | temp |= PORTSC_PTS_ULPI; | |
962 | break; | |
963 | case FSL_USB2_PHY_UTMI_WIDE: | |
964 | temp |= PORTSC_PTW_16BIT; | |
965 | /* fall through */ | |
966 | case FSL_USB2_PHY_UTMI: | |
967 | temp |= PORTSC_PTS_UTMI; | |
968 | /* fall through */ | |
969 | default: | |
970 | break; | |
971 | } | |
972 | fsl_writel(temp, &p_otg->dr_mem_map->portsc); | |
973 | ||
974 | if (pdata->have_sysif_regs) { | |
975 | /* configure control enable IO output, big endian register */ | |
976 | temp = __raw_readl(&p_otg->dr_mem_map->control); | |
977 | temp |= USB_CTRL_IOENB; | |
978 | __raw_writel(temp, &p_otg->dr_mem_map->control); | |
979 | } | |
980 | ||
981 | /* disable all interrupt and clear all OTGSC status */ | |
982 | temp = fsl_readl(&p_otg->dr_mem_map->otgsc); | |
983 | temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK; | |
984 | temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE; | |
985 | fsl_writel(temp, &p_otg->dr_mem_map->otgsc); | |
986 | ||
987 | /* | |
988 | * The identification (id) input is FALSE when a Mini-A plug is inserted | |
989 | * in the devices Mini-AB receptacle. Otherwise, this input is TRUE. | |
990 | * Also: record initial state of ID pin | |
991 | */ | |
992 | if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) { | |
e5ba1c02 | 993 | p_otg->phy.otg->state = OTG_STATE_UNDEFINED; |
0807c500 LY |
994 | p_otg->fsm.id = 1; |
995 | } else { | |
e5ba1c02 | 996 | p_otg->phy.otg->state = OTG_STATE_A_IDLE; |
0807c500 LY |
997 | p_otg->fsm.id = 0; |
998 | } | |
999 | ||
523e531e | 1000 | pr_debug("initial ID pin=%d\n", p_otg->fsm.id); |
0807c500 LY |
1001 | |
1002 | /* enable OTG ID pin interrupt */ | |
1003 | temp = fsl_readl(&p_otg->dr_mem_map->otgsc); | |
1004 | temp |= OTGSC_INTR_USB_ID_EN; | |
1005 | temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN); | |
1006 | fsl_writel(temp, &p_otg->dr_mem_map->otgsc); | |
1007 | ||
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | * state file in sysfs | |
1013 | */ | |
1014 | static int show_fsl_usb2_otg_state(struct device *dev, | |
1015 | struct device_attribute *attr, char *buf) | |
1016 | { | |
1017 | struct otg_fsm *fsm = &fsl_otg_dev->fsm; | |
1018 | char *next = buf; | |
1019 | unsigned size = PAGE_SIZE; | |
0807c500 LY |
1020 | int t; |
1021 | ||
16e569e9 | 1022 | mutex_lock(&fsm->lock); |
0807c500 LY |
1023 | |
1024 | /* basic driver infomation */ | |
1025 | t = scnprintf(next, size, | |
1026 | DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n", | |
1027 | DRIVER_VERSION); | |
1028 | size -= t; | |
1029 | next += t; | |
1030 | ||
1031 | /* Registers */ | |
1032 | t = scnprintf(next, size, | |
1033 | "OTGSC: 0x%08x\n" | |
1034 | "PORTSC: 0x%08x\n" | |
1035 | "USBMODE: 0x%08x\n" | |
1036 | "USBCMD: 0x%08x\n" | |
1037 | "USBSTS: 0x%08x\n" | |
1038 | "USBINTR: 0x%08x\n", | |
1039 | fsl_readl(&usb_dr_regs->otgsc), | |
1040 | fsl_readl(&usb_dr_regs->portsc), | |
1041 | fsl_readl(&usb_dr_regs->usbmode), | |
1042 | fsl_readl(&usb_dr_regs->usbcmd), | |
1043 | fsl_readl(&usb_dr_regs->usbsts), | |
1044 | fsl_readl(&usb_dr_regs->usbintr)); | |
1045 | size -= t; | |
1046 | next += t; | |
1047 | ||
1048 | /* State */ | |
1049 | t = scnprintf(next, size, | |
1050 | "OTG state: %s\n\n", | |
e5ba1c02 | 1051 | usb_otg_state_string(fsl_otg_dev->phy.otg->state)); |
0807c500 LY |
1052 | size -= t; |
1053 | next += t; | |
1054 | ||
1055 | /* State Machine Variables */ | |
1056 | t = scnprintf(next, size, | |
1057 | "a_bus_req: %d\n" | |
1058 | "b_bus_req: %d\n" | |
1059 | "a_bus_resume: %d\n" | |
1060 | "a_bus_suspend: %d\n" | |
1061 | "a_conn: %d\n" | |
1062 | "a_sess_vld: %d\n" | |
1063 | "a_srp_det: %d\n" | |
1064 | "a_vbus_vld: %d\n" | |
1065 | "b_bus_resume: %d\n" | |
1066 | "b_bus_suspend: %d\n" | |
1067 | "b_conn: %d\n" | |
1068 | "b_se0_srp: %d\n" | |
68041785 | 1069 | "b_ssend_srp: %d\n" |
0807c500 LY |
1070 | "b_sess_vld: %d\n" |
1071 | "id: %d\n", | |
1072 | fsm->a_bus_req, | |
1073 | fsm->b_bus_req, | |
1074 | fsm->a_bus_resume, | |
1075 | fsm->a_bus_suspend, | |
1076 | fsm->a_conn, | |
1077 | fsm->a_sess_vld, | |
1078 | fsm->a_srp_det, | |
1079 | fsm->a_vbus_vld, | |
1080 | fsm->b_bus_resume, | |
1081 | fsm->b_bus_suspend, | |
1082 | fsm->b_conn, | |
1083 | fsm->b_se0_srp, | |
68041785 | 1084 | fsm->b_ssend_srp, |
0807c500 LY |
1085 | fsm->b_sess_vld, |
1086 | fsm->id); | |
1087 | size -= t; | |
1088 | next += t; | |
1089 | ||
16e569e9 | 1090 | mutex_unlock(&fsm->lock); |
0807c500 LY |
1091 | |
1092 | return PAGE_SIZE - size; | |
1093 | } | |
1094 | ||
1095 | static DEVICE_ATTR(fsl_usb2_otg_state, S_IRUGO, show_fsl_usb2_otg_state, NULL); | |
1096 | ||
1097 | ||
1098 | /* Char driver interface to control some OTG input */ | |
1099 | ||
1100 | /* | |
1101 | * Handle some ioctl command, such as get otg | |
1102 | * status and set host suspend | |
1103 | */ | |
1104 | static long fsl_otg_ioctl(struct file *file, unsigned int cmd, | |
1105 | unsigned long arg) | |
1106 | { | |
1107 | u32 retval = 0; | |
1108 | ||
1109 | switch (cmd) { | |
1110 | case GET_OTG_STATUS: | |
1111 | retval = fsl_otg_dev->host_working; | |
1112 | break; | |
1113 | ||
1114 | case SET_A_SUSPEND_REQ: | |
cff4dab4 | 1115 | fsl_otg_dev->fsm.a_suspend_req_inf = arg; |
0807c500 LY |
1116 | break; |
1117 | ||
1118 | case SET_A_BUS_DROP: | |
1119 | fsl_otg_dev->fsm.a_bus_drop = arg; | |
1120 | break; | |
1121 | ||
1122 | case SET_A_BUS_REQ: | |
1123 | fsl_otg_dev->fsm.a_bus_req = arg; | |
1124 | break; | |
1125 | ||
1126 | case SET_B_BUS_REQ: | |
1127 | fsl_otg_dev->fsm.b_bus_req = arg; | |
1128 | break; | |
1129 | ||
1130 | default: | |
1131 | break; | |
1132 | } | |
1133 | ||
1134 | otg_statemachine(&fsl_otg_dev->fsm); | |
1135 | ||
1136 | return retval; | |
1137 | } | |
1138 | ||
1139 | static int fsl_otg_open(struct inode *inode, struct file *file) | |
1140 | { | |
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | static int fsl_otg_release(struct inode *inode, struct file *file) | |
1145 | { | |
1146 | return 0; | |
1147 | } | |
1148 | ||
1149 | static const struct file_operations otg_fops = { | |
1150 | .owner = THIS_MODULE, | |
1151 | .llseek = NULL, | |
1152 | .read = NULL, | |
1153 | .write = NULL, | |
1154 | .unlocked_ioctl = fsl_otg_ioctl, | |
1155 | .open = fsl_otg_open, | |
1156 | .release = fsl_otg_release, | |
1157 | }; | |
1158 | ||
41ac7b3a | 1159 | static int fsl_otg_probe(struct platform_device *pdev) |
0807c500 LY |
1160 | { |
1161 | int ret; | |
1162 | ||
19f9e188 | 1163 | if (!dev_get_platdata(&pdev->dev)) |
0807c500 LY |
1164 | return -ENODEV; |
1165 | ||
1166 | /* configure the OTG */ | |
1167 | ret = fsl_otg_conf(pdev); | |
1168 | if (ret) { | |
1169 | dev_err(&pdev->dev, "Couldn't configure OTG module\n"); | |
1170 | return ret; | |
1171 | } | |
1172 | ||
1173 | /* start OTG */ | |
1174 | ret = usb_otg_start(pdev); | |
1175 | if (ret) { | |
1176 | dev_err(&pdev->dev, "Can't init FSL OTG device\n"); | |
1177 | return ret; | |
1178 | } | |
1179 | ||
1180 | ret = register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops); | |
1181 | if (ret) { | |
1182 | dev_err(&pdev->dev, "unable to register FSL OTG device\n"); | |
1183 | return ret; | |
1184 | } | |
1185 | ||
1186 | ret = device_create_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state); | |
1187 | if (ret) | |
1188 | dev_warn(&pdev->dev, "Can't register sysfs attribute\n"); | |
1189 | ||
1190 | return ret; | |
1191 | } | |
1192 | ||
fb4e98ab | 1193 | static int fsl_otg_remove(struct platform_device *pdev) |
0807c500 | 1194 | { |
19f9e188 | 1195 | struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0807c500 | 1196 | |
662dca54 | 1197 | usb_remove_phy(&fsl_otg_dev->phy); |
0807c500 LY |
1198 | free_irq(fsl_otg_dev->irq, fsl_otg_dev); |
1199 | ||
1200 | iounmap((void *)usb_dr_regs); | |
1201 | ||
1202 | fsl_otg_uninit_timers(); | |
7e062c0f | 1203 | kfree(fsl_otg_dev->phy.otg); |
0807c500 LY |
1204 | kfree(fsl_otg_dev); |
1205 | ||
1206 | device_remove_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state); | |
1207 | ||
1208 | unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME); | |
1209 | ||
1210 | if (pdata->exit) | |
1211 | pdata->exit(pdev); | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | struct platform_driver fsl_otg_driver = { | |
1217 | .probe = fsl_otg_probe, | |
7690417d | 1218 | .remove = fsl_otg_remove, |
0807c500 LY |
1219 | .driver = { |
1220 | .name = driver_name, | |
1221 | .owner = THIS_MODULE, | |
1222 | }, | |
1223 | }; | |
1224 | ||
cc27c96c | 1225 | module_platform_driver(fsl_otg_driver); |
0807c500 LY |
1226 | |
1227 | MODULE_DESCRIPTION(DRIVER_INFO); | |
1228 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
1229 | MODULE_LICENSE("GPL"); |