Commit | Line | Data |
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d860852e | 1 | /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. |
e0c201f3 PK |
2 | * |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/ioport.h> | |
29 | #include <linux/uaccess.h> | |
30 | #include <linux/debugfs.h> | |
31 | #include <linux/seq_file.h> | |
87c0104a | 32 | #include <linux/pm_runtime.h> |
8364f9af II |
33 | #include <linux/of.h> |
34 | #include <linux/of_device.h> | |
a2734543 | 35 | #include <linux/reset.h> |
e0c201f3 PK |
36 | |
37 | #include <linux/usb.h> | |
38 | #include <linux/usb/otg.h> | |
8364f9af | 39 | #include <linux/usb/of.h> |
e0c201f3 PK |
40 | #include <linux/usb/ulpi.h> |
41 | #include <linux/usb/gadget.h> | |
42 | #include <linux/usb/hcd.h> | |
43 | #include <linux/usb/msm_hsusb.h> | |
44 | #include <linux/usb/msm_hsusb_hw.h> | |
11aa5c47 | 45 | #include <linux/regulator/consumer.h> |
e0c201f3 | 46 | |
e0c201f3 PK |
47 | #define MSM_USB_BASE (motg->regs) |
48 | #define DRIVER_NAME "msm_otg" | |
49 | ||
50 | #define ULPI_IO_TIMEOUT_USEC (10 * 1000) | |
d69c6f5d | 51 | #define LINK_RESET_TIMEOUT_USEC (250 * 1000) |
11aa5c47 A |
52 | |
53 | #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */ | |
54 | #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */ | |
55 | #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */ | |
56 | #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */ | |
57 | ||
58 | #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */ | |
59 | #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */ | |
60 | #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */ | |
61 | #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */ | |
62 | ||
63 | #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */ | |
64 | #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */ | |
01799b62 II |
65 | #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */ |
66 | ||
67 | enum vdd_levels { | |
68 | VDD_LEVEL_NONE = 0, | |
69 | VDD_LEVEL_MIN, | |
70 | VDD_LEVEL_MAX, | |
71 | }; | |
11aa5c47 | 72 | |
11aa5c47 A |
73 | static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init) |
74 | { | |
75 | int ret = 0; | |
76 | ||
77 | if (init) { | |
37cfdaf7 | 78 | ret = regulator_set_voltage(motg->vddcx, |
01799b62 II |
79 | motg->vdd_levels[VDD_LEVEL_MIN], |
80 | motg->vdd_levels[VDD_LEVEL_MAX]); | |
11aa5c47 | 81 | if (ret) { |
3aca0fa9 | 82 | dev_err(motg->phy.dev, "Cannot set vddcx voltage\n"); |
11aa5c47 A |
83 | return ret; |
84 | } | |
85 | ||
37cfdaf7 | 86 | ret = regulator_enable(motg->vddcx); |
6b99c68e | 87 | if (ret) |
1d4c9293 | 88 | dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n"); |
11aa5c47 | 89 | } else { |
37cfdaf7 | 90 | ret = regulator_set_voltage(motg->vddcx, 0, |
01799b62 | 91 | motg->vdd_levels[VDD_LEVEL_MAX]); |
e99c4309 | 92 | if (ret) |
3aca0fa9 | 93 | dev_err(motg->phy.dev, "Cannot set vddcx voltage\n"); |
37cfdaf7 | 94 | ret = regulator_disable(motg->vddcx); |
11aa5c47 | 95 | if (ret) |
1d4c9293 | 96 | dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n"); |
11aa5c47 A |
97 | } |
98 | ||
99 | return ret; | |
100 | } | |
101 | ||
102 | static int msm_hsusb_ldo_init(struct msm_otg *motg, int init) | |
103 | { | |
104 | int rc = 0; | |
105 | ||
106 | if (init) { | |
37cfdaf7 | 107 | rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN, |
11aa5c47 A |
108 | USB_PHY_3P3_VOL_MAX); |
109 | if (rc) { | |
3aca0fa9 | 110 | dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n"); |
6b99c68e | 111 | goto exit; |
11aa5c47 | 112 | } |
37cfdaf7 | 113 | rc = regulator_enable(motg->v3p3); |
11aa5c47 | 114 | if (rc) { |
1d4c9293 | 115 | dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n"); |
6b99c68e | 116 | goto exit; |
11aa5c47 | 117 | } |
37cfdaf7 | 118 | rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN, |
11aa5c47 A |
119 | USB_PHY_1P8_VOL_MAX); |
120 | if (rc) { | |
3aca0fa9 | 121 | dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n"); |
6b99c68e | 122 | goto disable_3p3; |
11aa5c47 | 123 | } |
37cfdaf7 | 124 | rc = regulator_enable(motg->v1p8); |
11aa5c47 | 125 | if (rc) { |
1d4c9293 | 126 | dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n"); |
6b99c68e | 127 | goto disable_3p3; |
11aa5c47 A |
128 | } |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
37cfdaf7 | 133 | regulator_disable(motg->v1p8); |
11aa5c47 | 134 | disable_3p3: |
37cfdaf7 | 135 | regulator_disable(motg->v3p3); |
6b99c68e | 136 | exit: |
11aa5c47 A |
137 | return rc; |
138 | } | |
139 | ||
37cfdaf7 | 140 | static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on) |
11aa5c47 A |
141 | { |
142 | int ret = 0; | |
143 | ||
11aa5c47 | 144 | if (on) { |
37cfdaf7 | 145 | ret = regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
146 | USB_PHY_1P8_HPM_LOAD); |
147 | if (ret < 0) { | |
3aca0fa9 | 148 | pr_err("Could not set HPM for v1p8\n"); |
11aa5c47 A |
149 | return ret; |
150 | } | |
37cfdaf7 | 151 | ret = regulator_set_optimum_mode(motg->v3p3, |
11aa5c47 A |
152 | USB_PHY_3P3_HPM_LOAD); |
153 | if (ret < 0) { | |
3aca0fa9 | 154 | pr_err("Could not set HPM for v3p3\n"); |
37cfdaf7 | 155 | regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
156 | USB_PHY_1P8_LPM_LOAD); |
157 | return ret; | |
158 | } | |
159 | } else { | |
37cfdaf7 | 160 | ret = regulator_set_optimum_mode(motg->v1p8, |
11aa5c47 A |
161 | USB_PHY_1P8_LPM_LOAD); |
162 | if (ret < 0) | |
3aca0fa9 | 163 | pr_err("Could not set LPM for v1p8\n"); |
37cfdaf7 | 164 | ret = regulator_set_optimum_mode(motg->v3p3, |
11aa5c47 A |
165 | USB_PHY_3P3_LPM_LOAD); |
166 | if (ret < 0) | |
3aca0fa9 | 167 | pr_err("Could not set LPM for v3p3\n"); |
11aa5c47 A |
168 | } |
169 | ||
170 | pr_debug("reg (%s)\n", on ? "HPM" : "LPM"); | |
171 | return ret < 0 ? ret : 0; | |
172 | } | |
173 | ||
1d4c9293 | 174 | static int ulpi_read(struct usb_phy *phy, u32 reg) |
e0c201f3 | 175 | { |
1d4c9293 | 176 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
177 | int cnt = 0; |
178 | ||
179 | /* initiate read operation */ | |
180 | writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg), | |
181 | USB_ULPI_VIEWPORT); | |
182 | ||
183 | /* wait for completion */ | |
184 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
185 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
186 | break; | |
187 | udelay(1); | |
188 | cnt++; | |
189 | } | |
190 | ||
191 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 192 | dev_err(phy->dev, "ulpi_read: timeout %08x\n", |
e0c201f3 PK |
193 | readl(USB_ULPI_VIEWPORT)); |
194 | return -ETIMEDOUT; | |
195 | } | |
196 | return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT)); | |
197 | } | |
198 | ||
1d4c9293 | 199 | static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg) |
e0c201f3 | 200 | { |
1d4c9293 | 201 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
202 | int cnt = 0; |
203 | ||
204 | /* initiate write operation */ | |
205 | writel(ULPI_RUN | ULPI_WRITE | | |
206 | ULPI_ADDR(reg) | ULPI_DATA(val), | |
207 | USB_ULPI_VIEWPORT); | |
208 | ||
209 | /* wait for completion */ | |
210 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
211 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
212 | break; | |
213 | udelay(1); | |
214 | cnt++; | |
215 | } | |
216 | ||
217 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 218 | dev_err(phy->dev, "ulpi_write: timeout\n"); |
e0c201f3 PK |
219 | return -ETIMEDOUT; |
220 | } | |
221 | return 0; | |
222 | } | |
223 | ||
1d4c9293 | 224 | static struct usb_phy_io_ops msm_otg_io_ops = { |
e0c201f3 PK |
225 | .read = ulpi_read, |
226 | .write = ulpi_write, | |
227 | }; | |
228 | ||
229 | static void ulpi_init(struct msm_otg *motg) | |
230 | { | |
231 | struct msm_otg_platform_data *pdata = motg->pdata; | |
8364f9af II |
232 | int *seq = pdata->phy_init_seq, idx; |
233 | u32 addr = ULPI_EXT_VENDOR_SPECIFIC; | |
e0c201f3 | 234 | |
8364f9af II |
235 | for (idx = 0; idx < pdata->phy_init_sz; idx++) { |
236 | if (seq[idx] == -1) | |
237 | continue; | |
e0c201f3 | 238 | |
1d4c9293 | 239 | dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n", |
8364f9af II |
240 | seq[idx], addr + idx); |
241 | ulpi_write(&motg->phy, seq[idx], addr + idx); | |
e0c201f3 PK |
242 | } |
243 | } | |
244 | ||
349907c2 II |
245 | static int msm_phy_notify_disconnect(struct usb_phy *phy, |
246 | enum usb_device_speed speed) | |
247 | { | |
248 | int val; | |
249 | ||
250 | /* | |
251 | * Put the transceiver in non-driving mode. Otherwise host | |
252 | * may not detect soft-disconnection. | |
253 | */ | |
254 | val = ulpi_read(phy, ULPI_FUNC_CTRL); | |
255 | val &= ~ULPI_FUNC_CTRL_OPMODE_MASK; | |
256 | val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; | |
257 | ulpi_write(phy, val, ULPI_FUNC_CTRL); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
e0c201f3 PK |
262 | static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert) |
263 | { | |
a2734543 | 264 | int ret; |
5146d771 | 265 | |
32fc9eb5 | 266 | if (assert) |
a2734543 II |
267 | ret = reset_control_assert(motg->link_rst); |
268 | else | |
269 | ret = reset_control_deassert(motg->link_rst); | |
5146d771 | 270 | |
5146d771 II |
271 | if (ret) |
272 | dev_err(motg->phy.dev, "usb link clk reset %s failed\n", | |
273 | assert ? "assert" : "deassert"); | |
e0c201f3 | 274 | |
e0c201f3 PK |
275 | return ret; |
276 | } | |
277 | ||
278 | static int msm_otg_phy_clk_reset(struct msm_otg *motg) | |
279 | { | |
e44f1f4c | 280 | int ret = 0; |
e0c201f3 | 281 | |
32fc9eb5 | 282 | if (motg->phy_rst) |
a2734543 | 283 | ret = reset_control_reset(motg->phy_rst); |
5146d771 | 284 | |
e0c201f3 | 285 | if (ret) |
5146d771 II |
286 | dev_err(motg->phy.dev, "usb phy clk reset failed\n"); |
287 | ||
e0c201f3 PK |
288 | return ret; |
289 | } | |
290 | ||
d69c6f5d | 291 | static int msm_link_reset(struct msm_otg *motg) |
e0c201f3 PK |
292 | { |
293 | u32 val; | |
294 | int ret; | |
e0c201f3 PK |
295 | |
296 | ret = msm_otg_link_clk_reset(motg, 1); | |
e0c201f3 PK |
297 | if (ret) |
298 | return ret; | |
299 | ||
d69c6f5d II |
300 | /* wait for 1ms delay as suggested in HPG. */ |
301 | usleep_range(1000, 1200); | |
e0c201f3 | 302 | |
d69c6f5d | 303 | ret = msm_otg_link_clk_reset(motg, 0); |
e0c201f3 PK |
304 | if (ret) |
305 | return ret; | |
306 | ||
cfa3ff5d II |
307 | if (motg->phy_number) |
308 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
309 | ||
9f27984b | 310 | /* put transceiver in serial mode as part of reset */ |
d69c6f5d | 311 | val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK; |
9f27984b | 312 | writel(val | PORTSC_PTS_SERIAL, USB_PORTSC); |
d69c6f5d | 313 | |
e0c201f3 PK |
314 | return 0; |
315 | } | |
316 | ||
1d4c9293 | 317 | static int msm_otg_reset(struct usb_phy *phy) |
e0c201f3 | 318 | { |
1d4c9293 | 319 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 | 320 | int cnt = 0; |
e0c201f3 PK |
321 | |
322 | writel(USBCMD_RESET, USB_USBCMD); | |
323 | while (cnt < LINK_RESET_TIMEOUT_USEC) { | |
324 | if (!(readl(USB_USBCMD) & USBCMD_RESET)) | |
325 | break; | |
326 | udelay(1); | |
327 | cnt++; | |
328 | } | |
329 | if (cnt >= LINK_RESET_TIMEOUT_USEC) | |
330 | return -ETIMEDOUT; | |
331 | ||
9f27984b TB |
332 | /* select ULPI phy and clear other status/control bits in PORTSC */ |
333 | writel(PORTSC_PTS_ULPI, USB_PORTSC); | |
334 | ||
d69c6f5d II |
335 | writel(0x0, USB_AHBBURST); |
336 | writel(0x08, USB_AHBMODE); | |
337 | ||
338 | if (motg->phy_number) | |
339 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
340 | return 0; | |
341 | } | |
342 | ||
343 | static void msm_phy_reset(struct msm_otg *motg) | |
344 | { | |
345 | void __iomem *addr; | |
346 | ||
347 | if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) { | |
348 | msm_otg_phy_clk_reset(motg); | |
349 | return; | |
350 | } | |
351 | ||
352 | addr = USB_PHY_CTRL; | |
353 | if (motg->phy_number) | |
354 | addr = USB_PHY_CTRL2; | |
355 | ||
356 | /* Assert USB PHY_POR */ | |
357 | writel(readl(addr) | PHY_POR_ASSERT, addr); | |
358 | ||
359 | /* | |
360 | * wait for minimum 10 microseconds as suggested in HPG. | |
361 | * Use a slightly larger value since the exact value didn't | |
362 | * work 100% of the time. | |
363 | */ | |
364 | udelay(12); | |
365 | ||
366 | /* Deassert USB PHY_POR */ | |
367 | writel(readl(addr) & ~PHY_POR_ASSERT, addr); | |
368 | } | |
369 | ||
370 | static int msm_usb_reset(struct usb_phy *phy) | |
371 | { | |
372 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); | |
373 | int ret; | |
374 | ||
375 | if (!IS_ERR(motg->core_clk)) | |
376 | clk_prepare_enable(motg->core_clk); | |
377 | ||
378 | ret = msm_link_reset(motg); | |
379 | if (ret) { | |
380 | dev_err(phy->dev, "phy_reset failed\n"); | |
381 | return ret; | |
382 | } | |
383 | ||
384 | ret = msm_otg_reset(&motg->phy); | |
385 | if (ret) { | |
386 | dev_err(phy->dev, "link reset failed\n"); | |
387 | return ret; | |
388 | } | |
e0c201f3 PK |
389 | |
390 | msleep(100); | |
391 | ||
d69c6f5d II |
392 | /* Reset USB PHY after performing USB Link RESET */ |
393 | msm_phy_reset(motg); | |
394 | ||
395 | if (!IS_ERR(motg->core_clk)) | |
396 | clk_disable_unprepare(motg->core_clk); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int msm_phy_init(struct usb_phy *phy) | |
402 | { | |
403 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); | |
404 | struct msm_otg_platform_data *pdata = motg->pdata; | |
405 | u32 val, ulpi_val = 0; | |
406 | ||
407 | /* Program USB PHY Override registers. */ | |
408 | ulpi_init(motg); | |
409 | ||
410 | /* | |
411 | * It is recommended in HPG to reset USB PHY after programming | |
412 | * USB PHY Override registers. | |
413 | */ | |
414 | msm_phy_reset(motg); | |
e0c201f3 PK |
415 | |
416 | if (pdata->otg_control == OTG_PHY_CONTROL) { | |
417 | val = readl(USB_OTGSC); | |
971232cf | 418 | if (pdata->mode == USB_DR_MODE_OTG) { |
e0c201f3 PK |
419 | ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID; |
420 | val |= OTGSC_IDIE | OTGSC_BSVIE; | |
971232cf | 421 | } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) { |
e0c201f3 PK |
422 | ulpi_val = ULPI_INT_SESS_VALID; |
423 | val |= OTGSC_BSVIE; | |
424 | } | |
425 | writel(val, USB_OTGSC); | |
1d4c9293 HK |
426 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE); |
427 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL); | |
e0c201f3 PK |
428 | } |
429 | ||
cfa3ff5d II |
430 | if (motg->phy_number) |
431 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
432 | ||
e0c201f3 PK |
433 | return 0; |
434 | } | |
435 | ||
87c0104a | 436 | #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000) |
7018773a PK |
437 | #define PHY_RESUME_TIMEOUT_USEC (100 * 1000) |
438 | ||
e7d613d1 JC |
439 | #ifdef CONFIG_PM |
440 | ||
37cfdaf7 | 441 | static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high) |
e7d613d1 | 442 | { |
01799b62 | 443 | int max_vol = motg->vdd_levels[VDD_LEVEL_MAX]; |
e7d613d1 JC |
444 | int min_vol; |
445 | int ret; | |
446 | ||
447 | if (high) | |
01799b62 | 448 | min_vol = motg->vdd_levels[VDD_LEVEL_MIN]; |
e7d613d1 | 449 | else |
01799b62 | 450 | min_vol = motg->vdd_levels[VDD_LEVEL_NONE]; |
e7d613d1 | 451 | |
37cfdaf7 | 452 | ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol); |
e7d613d1 | 453 | if (ret) { |
3aca0fa9 | 454 | pr_err("Cannot set vddcx voltage\n"); |
e7d613d1 JC |
455 | return ret; |
456 | } | |
457 | ||
458 | pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol); | |
459 | ||
460 | return ret; | |
461 | } | |
462 | ||
87c0104a PK |
463 | static int msm_otg_suspend(struct msm_otg *motg) |
464 | { | |
1d4c9293 HK |
465 | struct usb_phy *phy = &motg->phy; |
466 | struct usb_bus *bus = phy->otg->host; | |
87c0104a | 467 | struct msm_otg_platform_data *pdata = motg->pdata; |
cfa3ff5d | 468 | void __iomem *addr; |
87c0104a PK |
469 | int cnt = 0; |
470 | ||
471 | if (atomic_read(&motg->in_lpm)) | |
472 | return 0; | |
473 | ||
474 | disable_irq(motg->irq); | |
475 | /* | |
04aebcbb PK |
476 | * Chipidea 45-nm PHY suspend sequence: |
477 | * | |
87c0104a PK |
478 | * Interrupt Latch Register auto-clear feature is not present |
479 | * in all PHY versions. Latch register is clear on read type. | |
480 | * Clear latch register to avoid spurious wakeup from | |
481 | * low power mode (LPM). | |
04aebcbb | 482 | * |
87c0104a PK |
483 | * PHY comparators are disabled when PHY enters into low power |
484 | * mode (LPM). Keep PHY comparators ON in LPM only when we expect | |
485 | * VBUS/Id notifications from USB PHY. Otherwise turn off USB | |
486 | * PHY comparators. This save significant amount of power. | |
04aebcbb | 487 | * |
87c0104a PK |
488 | * PLL is not turned off when PHY enters into low power mode (LPM). |
489 | * Disable PLL for maximum power savings. | |
490 | */ | |
04aebcbb PK |
491 | |
492 | if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) { | |
1d4c9293 | 493 | ulpi_read(phy, 0x14); |
04aebcbb | 494 | if (pdata->otg_control == OTG_PHY_CONTROL) |
1d4c9293 HK |
495 | ulpi_write(phy, 0x01, 0x30); |
496 | ulpi_write(phy, 0x08, 0x09); | |
04aebcbb | 497 | } |
87c0104a PK |
498 | |
499 | /* | |
500 | * PHY may take some time or even fail to enter into low power | |
501 | * mode (LPM). Hence poll for 500 msec and reset the PHY and link | |
502 | * in failure case. | |
503 | */ | |
504 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
505 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
506 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
507 | break; | |
508 | udelay(1); | |
509 | cnt++; | |
510 | } | |
511 | ||
512 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) { | |
1d4c9293 HK |
513 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
514 | msm_otg_reset(phy); | |
87c0104a PK |
515 | enable_irq(motg->irq); |
516 | return -ETIMEDOUT; | |
517 | } | |
518 | ||
519 | /* | |
520 | * PHY has capability to generate interrupt asynchronously in low | |
521 | * power mode (LPM). This interrupt is level triggered. So USB IRQ | |
522 | * line must be disabled till async interrupt enable bit is cleared | |
523 | * in USBCMD register. Assert STP (ULPI interface STOP signal) to | |
524 | * block data communication from PHY. | |
525 | */ | |
526 | writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD); | |
527 | ||
cfa3ff5d II |
528 | addr = USB_PHY_CTRL; |
529 | if (motg->phy_number) | |
530 | addr = USB_PHY_CTRL2; | |
531 | ||
04aebcbb PK |
532 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
533 | motg->pdata->otg_control == OTG_PMIC_CONTROL) | |
cfa3ff5d | 534 | writel(readl(addr) | PHY_RETEN, addr); |
04aebcbb | 535 | |
b99a8f62 SB |
536 | clk_disable_unprepare(motg->pclk); |
537 | clk_disable_unprepare(motg->clk); | |
6b99c68e | 538 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 539 | clk_disable_unprepare(motg->core_clk); |
87c0104a | 540 | |
04aebcbb PK |
541 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
542 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
37cfdaf7 II |
543 | msm_hsusb_ldo_set_mode(motg, 0); |
544 | msm_hsusb_config_vddcx(motg, 0); | |
04aebcbb PK |
545 | } |
546 | ||
1d4c9293 | 547 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
548 | enable_irq_wake(motg->irq); |
549 | if (bus) | |
550 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
551 | ||
552 | atomic_set(&motg->in_lpm, 1); | |
553 | enable_irq(motg->irq); | |
554 | ||
1d4c9293 | 555 | dev_info(phy->dev, "USB in low power mode\n"); |
87c0104a PK |
556 | |
557 | return 0; | |
558 | } | |
559 | ||
87c0104a PK |
560 | static int msm_otg_resume(struct msm_otg *motg) |
561 | { | |
1d4c9293 HK |
562 | struct usb_phy *phy = &motg->phy; |
563 | struct usb_bus *bus = phy->otg->host; | |
cfa3ff5d | 564 | void __iomem *addr; |
87c0104a PK |
565 | int cnt = 0; |
566 | unsigned temp; | |
567 | ||
568 | if (!atomic_read(&motg->in_lpm)) | |
569 | return 0; | |
570 | ||
b99a8f62 SB |
571 | clk_prepare_enable(motg->pclk); |
572 | clk_prepare_enable(motg->clk); | |
6b99c68e | 573 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 574 | clk_prepare_enable(motg->core_clk); |
87c0104a | 575 | |
04aebcbb PK |
576 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
577 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
cfa3ff5d II |
578 | |
579 | addr = USB_PHY_CTRL; | |
580 | if (motg->phy_number) | |
581 | addr = USB_PHY_CTRL2; | |
582 | ||
37cfdaf7 II |
583 | msm_hsusb_ldo_set_mode(motg, 1); |
584 | msm_hsusb_config_vddcx(motg, 1); | |
cfa3ff5d | 585 | writel(readl(addr) & ~PHY_RETEN, addr); |
04aebcbb PK |
586 | } |
587 | ||
87c0104a PK |
588 | temp = readl(USB_USBCMD); |
589 | temp &= ~ASYNC_INTR_CTRL; | |
590 | temp &= ~ULPI_STP_CTRL; | |
591 | writel(temp, USB_USBCMD); | |
592 | ||
593 | /* | |
594 | * PHY comes out of low power mode (LPM) in case of wakeup | |
595 | * from asynchronous interrupt. | |
596 | */ | |
597 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
598 | goto skip_phy_resume; | |
599 | ||
600 | writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC); | |
601 | while (cnt < PHY_RESUME_TIMEOUT_USEC) { | |
602 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
603 | break; | |
604 | udelay(1); | |
605 | cnt++; | |
606 | } | |
607 | ||
608 | if (cnt >= PHY_RESUME_TIMEOUT_USEC) { | |
609 | /* | |
610 | * This is a fatal error. Reset the link and | |
611 | * PHY. USB state can not be restored. Re-insertion | |
612 | * of USB cable is the only way to get USB working. | |
613 | */ | |
3aca0fa9 | 614 | dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n"); |
1d4c9293 | 615 | msm_otg_reset(phy); |
87c0104a PK |
616 | } |
617 | ||
618 | skip_phy_resume: | |
1d4c9293 | 619 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
620 | disable_irq_wake(motg->irq); |
621 | if (bus) | |
622 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
623 | ||
2ce2c3ac PK |
624 | atomic_set(&motg->in_lpm, 0); |
625 | ||
87c0104a PK |
626 | if (motg->async_int) { |
627 | motg->async_int = 0; | |
1d4c9293 | 628 | pm_runtime_put(phy->dev); |
87c0104a PK |
629 | enable_irq(motg->irq); |
630 | } | |
631 | ||
1d4c9293 | 632 | dev_info(phy->dev, "USB exited from low power mode\n"); |
87c0104a PK |
633 | |
634 | return 0; | |
635 | } | |
7018773a | 636 | #endif |
87c0104a | 637 | |
d860852e PK |
638 | static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA) |
639 | { | |
640 | if (motg->cur_power == mA) | |
641 | return; | |
642 | ||
643 | /* TODO: Notify PMIC about available current */ | |
1d4c9293 | 644 | dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA); |
d860852e PK |
645 | motg->cur_power = mA; |
646 | } | |
647 | ||
1d4c9293 | 648 | static int msm_otg_set_power(struct usb_phy *phy, unsigned mA) |
d860852e | 649 | { |
1d4c9293 | 650 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
d860852e PK |
651 | |
652 | /* | |
653 | * Gadget driver uses set_power method to notify about the | |
654 | * available current based on suspend/configured states. | |
655 | * | |
656 | * IDEV_CHG can be drawn irrespective of suspend/un-configured | |
657 | * states when CDP/ACA is connected. | |
658 | */ | |
659 | if (motg->chg_type == USB_SDP_CHARGER) | |
660 | msm_otg_notify_charger(motg, mA); | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
1d4c9293 | 665 | static void msm_otg_start_host(struct usb_phy *phy, int on) |
e0c201f3 | 666 | { |
1d4c9293 | 667 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
668 | struct msm_otg_platform_data *pdata = motg->pdata; |
669 | struct usb_hcd *hcd; | |
670 | ||
1d4c9293 | 671 | if (!phy->otg->host) |
e0c201f3 PK |
672 | return; |
673 | ||
1d4c9293 | 674 | hcd = bus_to_hcd(phy->otg->host); |
e0c201f3 PK |
675 | |
676 | if (on) { | |
1d4c9293 | 677 | dev_dbg(phy->dev, "host on\n"); |
e0c201f3 PK |
678 | |
679 | if (pdata->vbus_power) | |
680 | pdata->vbus_power(1); | |
681 | /* | |
682 | * Some boards have a switch cotrolled by gpio | |
683 | * to enable/disable internal HUB. Enable internal | |
684 | * HUB before kicking the host. | |
685 | */ | |
686 | if (pdata->setup_gpio) | |
687 | pdata->setup_gpio(OTG_STATE_A_HOST); | |
688 | #ifdef CONFIG_USB | |
689 | usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); | |
3c9740a1 | 690 | device_wakeup_enable(hcd->self.controller); |
e0c201f3 PK |
691 | #endif |
692 | } else { | |
1d4c9293 | 693 | dev_dbg(phy->dev, "host off\n"); |
e0c201f3 PK |
694 | |
695 | #ifdef CONFIG_USB | |
696 | usb_remove_hcd(hcd); | |
697 | #endif | |
698 | if (pdata->setup_gpio) | |
699 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
700 | if (pdata->vbus_power) | |
701 | pdata->vbus_power(0); | |
702 | } | |
703 | } | |
704 | ||
1d4c9293 | 705 | static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host) |
e0c201f3 | 706 | { |
19c1eac2 | 707 | struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy); |
e0c201f3 PK |
708 | struct usb_hcd *hcd; |
709 | ||
710 | /* | |
711 | * Fail host registration if this board can support | |
712 | * only peripheral configuration. | |
713 | */ | |
971232cf | 714 | if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) { |
19c1eac2 | 715 | dev_info(otg->usb_phy->dev, "Host mode is not supported\n"); |
e0c201f3 PK |
716 | return -ENODEV; |
717 | } | |
718 | ||
719 | if (!host) { | |
e47d9254 | 720 | if (otg->state == OTG_STATE_A_HOST) { |
19c1eac2 AT |
721 | pm_runtime_get_sync(otg->usb_phy->dev); |
722 | msm_otg_start_host(otg->usb_phy, 0); | |
e0c201f3 | 723 | otg->host = NULL; |
e47d9254 | 724 | otg->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
725 | schedule_work(&motg->sm_work); |
726 | } else { | |
727 | otg->host = NULL; | |
728 | } | |
729 | ||
730 | return 0; | |
731 | } | |
732 | ||
733 | hcd = bus_to_hcd(host); | |
734 | hcd->power_budget = motg->pdata->power_budget; | |
735 | ||
736 | otg->host = host; | |
19c1eac2 | 737 | dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n"); |
e0c201f3 PK |
738 | |
739 | /* | |
740 | * Kick the state machine work, if peripheral is not supported | |
741 | * or peripheral is already registered with us. | |
742 | */ | |
971232cf | 743 | if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) { |
19c1eac2 | 744 | pm_runtime_get_sync(otg->usb_phy->dev); |
e0c201f3 | 745 | schedule_work(&motg->sm_work); |
87c0104a | 746 | } |
e0c201f3 PK |
747 | |
748 | return 0; | |
749 | } | |
750 | ||
1d4c9293 | 751 | static void msm_otg_start_peripheral(struct usb_phy *phy, int on) |
e0c201f3 | 752 | { |
1d4c9293 | 753 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
754 | struct msm_otg_platform_data *pdata = motg->pdata; |
755 | ||
1d4c9293 | 756 | if (!phy->otg->gadget) |
e0c201f3 PK |
757 | return; |
758 | ||
759 | if (on) { | |
1d4c9293 | 760 | dev_dbg(phy->dev, "gadget on\n"); |
e0c201f3 PK |
761 | /* |
762 | * Some boards have a switch cotrolled by gpio | |
763 | * to enable/disable internal HUB. Disable internal | |
764 | * HUB before kicking the gadget. | |
765 | */ | |
766 | if (pdata->setup_gpio) | |
767 | pdata->setup_gpio(OTG_STATE_B_PERIPHERAL); | |
1d4c9293 | 768 | usb_gadget_vbus_connect(phy->otg->gadget); |
e0c201f3 | 769 | } else { |
1d4c9293 HK |
770 | dev_dbg(phy->dev, "gadget off\n"); |
771 | usb_gadget_vbus_disconnect(phy->otg->gadget); | |
e0c201f3 PK |
772 | if (pdata->setup_gpio) |
773 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
774 | } | |
775 | ||
776 | } | |
777 | ||
1d4c9293 HK |
778 | static int msm_otg_set_peripheral(struct usb_otg *otg, |
779 | struct usb_gadget *gadget) | |
e0c201f3 | 780 | { |
19c1eac2 | 781 | struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy); |
e0c201f3 PK |
782 | |
783 | /* | |
784 | * Fail peripheral registration if this board can support | |
785 | * only host configuration. | |
786 | */ | |
971232cf | 787 | if (motg->pdata->mode == USB_DR_MODE_HOST) { |
19c1eac2 | 788 | dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n"); |
e0c201f3 PK |
789 | return -ENODEV; |
790 | } | |
791 | ||
792 | if (!gadget) { | |
e47d9254 | 793 | if (otg->state == OTG_STATE_B_PERIPHERAL) { |
19c1eac2 AT |
794 | pm_runtime_get_sync(otg->usb_phy->dev); |
795 | msm_otg_start_peripheral(otg->usb_phy, 0); | |
e0c201f3 | 796 | otg->gadget = NULL; |
e47d9254 | 797 | otg->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
798 | schedule_work(&motg->sm_work); |
799 | } else { | |
800 | otg->gadget = NULL; | |
801 | } | |
802 | ||
803 | return 0; | |
804 | } | |
805 | otg->gadget = gadget; | |
19c1eac2 AT |
806 | dev_dbg(otg->usb_phy->dev, |
807 | "peripheral driver registered w/ tranceiver\n"); | |
e0c201f3 PK |
808 | |
809 | /* | |
810 | * Kick the state machine work, if host is not supported | |
811 | * or host is already registered with us. | |
812 | */ | |
971232cf | 813 | if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) { |
19c1eac2 | 814 | pm_runtime_get_sync(otg->usb_phy->dev); |
e0c201f3 | 815 | schedule_work(&motg->sm_work); |
87c0104a | 816 | } |
e0c201f3 PK |
817 | |
818 | return 0; | |
819 | } | |
820 | ||
d860852e PK |
821 | static bool msm_chg_check_secondary_det(struct msm_otg *motg) |
822 | { | |
1d4c9293 | 823 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
824 | u32 chg_det; |
825 | bool ret = false; | |
826 | ||
827 | switch (motg->pdata->phy_type) { | |
828 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 829 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
830 | ret = chg_det & (1 << 4); |
831 | break; | |
832 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 833 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
834 | ret = chg_det & 1; |
835 | break; | |
836 | default: | |
837 | break; | |
838 | } | |
839 | return ret; | |
840 | } | |
841 | ||
842 | static void msm_chg_enable_secondary_det(struct msm_otg *motg) | |
843 | { | |
1d4c9293 | 844 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
845 | u32 chg_det; |
846 | ||
847 | switch (motg->pdata->phy_type) { | |
848 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 849 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
850 | /* Turn off charger block */ |
851 | chg_det |= ~(1 << 1); | |
1d4c9293 | 852 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
853 | udelay(20); |
854 | /* control chg block via ULPI */ | |
855 | chg_det &= ~(1 << 3); | |
1d4c9293 | 856 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
857 | /* put it in host mode for enabling D- source */ |
858 | chg_det &= ~(1 << 2); | |
1d4c9293 | 859 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
860 | /* Turn on chg detect block */ |
861 | chg_det &= ~(1 << 1); | |
1d4c9293 | 862 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
863 | udelay(20); |
864 | /* enable chg detection */ | |
865 | chg_det &= ~(1 << 0); | |
1d4c9293 | 866 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
867 | break; |
868 | case SNPS_28NM_INTEGRATED_PHY: | |
869 | /* | |
870 | * Configure DM as current source, DP as current sink | |
871 | * and enable battery charging comparators. | |
872 | */ | |
1d4c9293 HK |
873 | ulpi_write(phy, 0x8, 0x85); |
874 | ulpi_write(phy, 0x2, 0x85); | |
875 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
876 | break; |
877 | default: | |
878 | break; | |
879 | } | |
880 | } | |
881 | ||
882 | static bool msm_chg_check_primary_det(struct msm_otg *motg) | |
883 | { | |
1d4c9293 | 884 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
885 | u32 chg_det; |
886 | bool ret = false; | |
887 | ||
888 | switch (motg->pdata->phy_type) { | |
889 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 890 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
891 | ret = chg_det & (1 << 4); |
892 | break; | |
893 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 894 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
895 | ret = chg_det & 1; |
896 | break; | |
897 | default: | |
898 | break; | |
899 | } | |
900 | return ret; | |
901 | } | |
902 | ||
903 | static void msm_chg_enable_primary_det(struct msm_otg *motg) | |
904 | { | |
1d4c9293 | 905 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
906 | u32 chg_det; |
907 | ||
908 | switch (motg->pdata->phy_type) { | |
909 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 910 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
911 | /* enable chg detection */ |
912 | chg_det &= ~(1 << 0); | |
1d4c9293 | 913 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
914 | break; |
915 | case SNPS_28NM_INTEGRATED_PHY: | |
916 | /* | |
917 | * Configure DP as current source, DM as current sink | |
918 | * and enable battery charging comparators. | |
919 | */ | |
1d4c9293 HK |
920 | ulpi_write(phy, 0x2, 0x85); |
921 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
922 | break; |
923 | default: | |
924 | break; | |
925 | } | |
926 | } | |
927 | ||
928 | static bool msm_chg_check_dcd(struct msm_otg *motg) | |
929 | { | |
1d4c9293 | 930 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
931 | u32 line_state; |
932 | bool ret = false; | |
933 | ||
934 | switch (motg->pdata->phy_type) { | |
935 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 936 | line_state = ulpi_read(phy, 0x15); |
d860852e PK |
937 | ret = !(line_state & 1); |
938 | break; | |
939 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 940 | line_state = ulpi_read(phy, 0x87); |
d860852e PK |
941 | ret = line_state & 2; |
942 | break; | |
943 | default: | |
944 | break; | |
945 | } | |
946 | return ret; | |
947 | } | |
948 | ||
949 | static void msm_chg_disable_dcd(struct msm_otg *motg) | |
950 | { | |
1d4c9293 | 951 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
952 | u32 chg_det; |
953 | ||
954 | switch (motg->pdata->phy_type) { | |
955 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 956 | chg_det = ulpi_read(phy, 0x34); |
d860852e | 957 | chg_det &= ~(1 << 5); |
1d4c9293 | 958 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
959 | break; |
960 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 961 | ulpi_write(phy, 0x10, 0x86); |
d860852e PK |
962 | break; |
963 | default: | |
964 | break; | |
965 | } | |
966 | } | |
967 | ||
968 | static void msm_chg_enable_dcd(struct msm_otg *motg) | |
969 | { | |
1d4c9293 | 970 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
971 | u32 chg_det; |
972 | ||
973 | switch (motg->pdata->phy_type) { | |
974 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 975 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
976 | /* Turn on D+ current source */ |
977 | chg_det |= (1 << 5); | |
1d4c9293 | 978 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
979 | break; |
980 | case SNPS_28NM_INTEGRATED_PHY: | |
981 | /* Data contact detection enable */ | |
1d4c9293 | 982 | ulpi_write(phy, 0x10, 0x85); |
d860852e PK |
983 | break; |
984 | default: | |
985 | break; | |
986 | } | |
987 | } | |
988 | ||
989 | static void msm_chg_block_on(struct msm_otg *motg) | |
990 | { | |
1d4c9293 | 991 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
992 | u32 func_ctrl, chg_det; |
993 | ||
994 | /* put the controller in non-driving mode */ | |
1d4c9293 | 995 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
996 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
997 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; | |
1d4c9293 | 998 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
999 | |
1000 | switch (motg->pdata->phy_type) { | |
1001 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1002 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1003 | /* control chg block via ULPI */ |
1004 | chg_det &= ~(1 << 3); | |
1d4c9293 | 1005 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1006 | /* Turn on chg detect block */ |
1007 | chg_det &= ~(1 << 1); | |
1d4c9293 | 1008 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1009 | udelay(20); |
1010 | break; | |
1011 | case SNPS_28NM_INTEGRATED_PHY: | |
1012 | /* Clear charger detecting control bits */ | |
1d4c9293 | 1013 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 1014 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
1015 | ulpi_write(phy, 0x1F, 0x92); |
1016 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
1017 | udelay(100); |
1018 | break; | |
1019 | default: | |
1020 | break; | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | static void msm_chg_block_off(struct msm_otg *motg) | |
1025 | { | |
1d4c9293 | 1026 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1027 | u32 func_ctrl, chg_det; |
1028 | ||
1029 | switch (motg->pdata->phy_type) { | |
1030 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1031 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1032 | /* Turn off charger block */ |
1033 | chg_det |= ~(1 << 1); | |
1d4c9293 | 1034 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1035 | break; |
1036 | case SNPS_28NM_INTEGRATED_PHY: | |
1037 | /* Clear charger detecting control bits */ | |
1d4c9293 | 1038 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 1039 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
1040 | ulpi_write(phy, 0x1F, 0x92); |
1041 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
1042 | break; |
1043 | default: | |
1044 | break; | |
1045 | } | |
1046 | ||
1047 | /* put the controller in normal mode */ | |
1d4c9293 | 1048 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
1049 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
1050 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL; | |
1d4c9293 | 1051 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
1052 | } |
1053 | ||
1054 | #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */ | |
1055 | #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */ | |
1056 | #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */ | |
1057 | #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */ | |
1058 | static void msm_chg_detect_work(struct work_struct *w) | |
1059 | { | |
1060 | struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work); | |
1d4c9293 | 1061 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1062 | bool is_dcd, tmout, vout; |
1063 | unsigned long delay; | |
1064 | ||
1d4c9293 | 1065 | dev_dbg(phy->dev, "chg detection work\n"); |
d860852e PK |
1066 | switch (motg->chg_state) { |
1067 | case USB_CHG_STATE_UNDEFINED: | |
1d4c9293 | 1068 | pm_runtime_get_sync(phy->dev); |
d860852e PK |
1069 | msm_chg_block_on(motg); |
1070 | msm_chg_enable_dcd(motg); | |
1071 | motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; | |
1072 | motg->dcd_retries = 0; | |
1073 | delay = MSM_CHG_DCD_POLL_TIME; | |
1074 | break; | |
1075 | case USB_CHG_STATE_WAIT_FOR_DCD: | |
1076 | is_dcd = msm_chg_check_dcd(motg); | |
1077 | tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES; | |
1078 | if (is_dcd || tmout) { | |
1079 | msm_chg_disable_dcd(motg); | |
1080 | msm_chg_enable_primary_det(motg); | |
1081 | delay = MSM_CHG_PRIMARY_DET_TIME; | |
1082 | motg->chg_state = USB_CHG_STATE_DCD_DONE; | |
1083 | } else { | |
1084 | delay = MSM_CHG_DCD_POLL_TIME; | |
1085 | } | |
1086 | break; | |
1087 | case USB_CHG_STATE_DCD_DONE: | |
1088 | vout = msm_chg_check_primary_det(motg); | |
1089 | if (vout) { | |
1090 | msm_chg_enable_secondary_det(motg); | |
1091 | delay = MSM_CHG_SECONDARY_DET_TIME; | |
1092 | motg->chg_state = USB_CHG_STATE_PRIMARY_DONE; | |
1093 | } else { | |
1094 | motg->chg_type = USB_SDP_CHARGER; | |
1095 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1096 | delay = 0; | |
1097 | } | |
1098 | break; | |
1099 | case USB_CHG_STATE_PRIMARY_DONE: | |
1100 | vout = msm_chg_check_secondary_det(motg); | |
1101 | if (vout) | |
1102 | motg->chg_type = USB_DCP_CHARGER; | |
1103 | else | |
1104 | motg->chg_type = USB_CDP_CHARGER; | |
1105 | motg->chg_state = USB_CHG_STATE_SECONDARY_DONE; | |
1106 | /* fall through */ | |
1107 | case USB_CHG_STATE_SECONDARY_DONE: | |
1108 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1109 | case USB_CHG_STATE_DETECTED: | |
1110 | msm_chg_block_off(motg); | |
1d4c9293 | 1111 | dev_dbg(phy->dev, "charger = %d\n", motg->chg_type); |
d860852e PK |
1112 | schedule_work(&motg->sm_work); |
1113 | return; | |
1114 | default: | |
1115 | return; | |
1116 | } | |
1117 | ||
1118 | schedule_delayed_work(&motg->chg_work, delay); | |
1119 | } | |
1120 | ||
e0c201f3 PK |
1121 | /* |
1122 | * We support OTG, Peripheral only and Host only configurations. In case | |
1123 | * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen | |
1124 | * via Id pin status or user request (debugfs). Id/BSV interrupts are not | |
1125 | * enabled when switch is controlled by user and default mode is supplied | |
1126 | * by board file, which can be changed by userspace later. | |
1127 | */ | |
1128 | static void msm_otg_init_sm(struct msm_otg *motg) | |
1129 | { | |
1130 | struct msm_otg_platform_data *pdata = motg->pdata; | |
1131 | u32 otgsc = readl(USB_OTGSC); | |
1132 | ||
1133 | switch (pdata->mode) { | |
971232cf | 1134 | case USB_DR_MODE_OTG: |
e0c201f3 PK |
1135 | if (pdata->otg_control == OTG_PHY_CONTROL) { |
1136 | if (otgsc & OTGSC_ID) | |
1137 | set_bit(ID, &motg->inputs); | |
1138 | else | |
1139 | clear_bit(ID, &motg->inputs); | |
1140 | ||
1141 | if (otgsc & OTGSC_BSV) | |
1142 | set_bit(B_SESS_VLD, &motg->inputs); | |
1143 | else | |
1144 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1145 | } else if (pdata->otg_control == OTG_USER_CONTROL) { | |
e0c201f3 PK |
1146 | set_bit(ID, &motg->inputs); |
1147 | clear_bit(B_SESS_VLD, &motg->inputs); | |
e0c201f3 PK |
1148 | } |
1149 | break; | |
971232cf | 1150 | case USB_DR_MODE_HOST: |
e0c201f3 PK |
1151 | clear_bit(ID, &motg->inputs); |
1152 | break; | |
971232cf | 1153 | case USB_DR_MODE_PERIPHERAL: |
e0c201f3 PK |
1154 | set_bit(ID, &motg->inputs); |
1155 | if (otgsc & OTGSC_BSV) | |
1156 | set_bit(B_SESS_VLD, &motg->inputs); | |
1157 | else | |
1158 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1159 | break; | |
1160 | default: | |
1161 | break; | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | static void msm_otg_sm_work(struct work_struct *w) | |
1166 | { | |
1167 | struct msm_otg *motg = container_of(w, struct msm_otg, sm_work); | |
1d4c9293 | 1168 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1169 | |
e47d9254 | 1170 | switch (otg->state) { |
e0c201f3 | 1171 | case OTG_STATE_UNDEFINED: |
19c1eac2 AT |
1172 | dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n"); |
1173 | msm_otg_reset(otg->usb_phy); | |
e0c201f3 | 1174 | msm_otg_init_sm(motg); |
e47d9254 | 1175 | otg->state = OTG_STATE_B_IDLE; |
e0c201f3 PK |
1176 | /* FALL THROUGH */ |
1177 | case OTG_STATE_B_IDLE: | |
19c1eac2 | 1178 | dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n"); |
e0c201f3 PK |
1179 | if (!test_bit(ID, &motg->inputs) && otg->host) { |
1180 | /* disable BSV bit */ | |
1181 | writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC); | |
19c1eac2 | 1182 | msm_otg_start_host(otg->usb_phy, 1); |
e47d9254 | 1183 | otg->state = OTG_STATE_A_HOST; |
d860852e PK |
1184 | } else if (test_bit(B_SESS_VLD, &motg->inputs)) { |
1185 | switch (motg->chg_state) { | |
1186 | case USB_CHG_STATE_UNDEFINED: | |
1187 | msm_chg_detect_work(&motg->chg_work.work); | |
1188 | break; | |
1189 | case USB_CHG_STATE_DETECTED: | |
1190 | switch (motg->chg_type) { | |
1191 | case USB_DCP_CHARGER: | |
1192 | msm_otg_notify_charger(motg, | |
1193 | IDEV_CHG_MAX); | |
1194 | break; | |
1195 | case USB_CDP_CHARGER: | |
1196 | msm_otg_notify_charger(motg, | |
1197 | IDEV_CHG_MAX); | |
19c1eac2 AT |
1198 | msm_otg_start_peripheral(otg->usb_phy, |
1199 | 1); | |
e47d9254 | 1200 | otg->state |
1d4c9293 | 1201 | = OTG_STATE_B_PERIPHERAL; |
d860852e PK |
1202 | break; |
1203 | case USB_SDP_CHARGER: | |
1204 | msm_otg_notify_charger(motg, IUNIT); | |
19c1eac2 AT |
1205 | msm_otg_start_peripheral(otg->usb_phy, |
1206 | 1); | |
e47d9254 | 1207 | otg->state |
1d4c9293 | 1208 | = OTG_STATE_B_PERIPHERAL; |
d860852e PK |
1209 | break; |
1210 | default: | |
1211 | break; | |
1212 | } | |
1213 | break; | |
1214 | default: | |
1215 | break; | |
1216 | } | |
1217 | } else { | |
1218 | /* | |
1219 | * If charger detection work is pending, decrement | |
1220 | * the pm usage counter to balance with the one that | |
1221 | * is incremented in charger detection work. | |
1222 | */ | |
1223 | if (cancel_delayed_work_sync(&motg->chg_work)) { | |
19c1eac2 AT |
1224 | pm_runtime_put_sync(otg->usb_phy->dev); |
1225 | msm_otg_reset(otg->usb_phy); | |
d860852e PK |
1226 | } |
1227 | msm_otg_notify_charger(motg, 0); | |
1228 | motg->chg_state = USB_CHG_STATE_UNDEFINED; | |
1229 | motg->chg_type = USB_INVALID_CHARGER; | |
e0c201f3 | 1230 | } |
508ccea1 | 1231 | |
e47d9254 | 1232 | if (otg->state == OTG_STATE_B_IDLE) |
19c1eac2 | 1233 | pm_runtime_put_sync(otg->usb_phy->dev); |
e0c201f3 PK |
1234 | break; |
1235 | case OTG_STATE_B_PERIPHERAL: | |
19c1eac2 | 1236 | dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n"); |
e0c201f3 PK |
1237 | if (!test_bit(B_SESS_VLD, &motg->inputs) || |
1238 | !test_bit(ID, &motg->inputs)) { | |
d860852e | 1239 | msm_otg_notify_charger(motg, 0); |
19c1eac2 | 1240 | msm_otg_start_peripheral(otg->usb_phy, 0); |
d860852e PK |
1241 | motg->chg_state = USB_CHG_STATE_UNDEFINED; |
1242 | motg->chg_type = USB_INVALID_CHARGER; | |
e47d9254 | 1243 | otg->state = OTG_STATE_B_IDLE; |
19c1eac2 | 1244 | msm_otg_reset(otg->usb_phy); |
e0c201f3 PK |
1245 | schedule_work(w); |
1246 | } | |
1247 | break; | |
1248 | case OTG_STATE_A_HOST: | |
19c1eac2 | 1249 | dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n"); |
e0c201f3 | 1250 | if (test_bit(ID, &motg->inputs)) { |
19c1eac2 | 1251 | msm_otg_start_host(otg->usb_phy, 0); |
e47d9254 | 1252 | otg->state = OTG_STATE_B_IDLE; |
19c1eac2 | 1253 | msm_otg_reset(otg->usb_phy); |
e0c201f3 PK |
1254 | schedule_work(w); |
1255 | } | |
1256 | break; | |
1257 | default: | |
1258 | break; | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | static irqreturn_t msm_otg_irq(int irq, void *data) | |
1263 | { | |
1264 | struct msm_otg *motg = data; | |
1d4c9293 | 1265 | struct usb_phy *phy = &motg->phy; |
e0c201f3 PK |
1266 | u32 otgsc = 0; |
1267 | ||
87c0104a PK |
1268 | if (atomic_read(&motg->in_lpm)) { |
1269 | disable_irq_nosync(irq); | |
1270 | motg->async_int = 1; | |
1d4c9293 | 1271 | pm_runtime_get(phy->dev); |
87c0104a PK |
1272 | return IRQ_HANDLED; |
1273 | } | |
1274 | ||
e0c201f3 PK |
1275 | otgsc = readl(USB_OTGSC); |
1276 | if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS))) | |
1277 | return IRQ_NONE; | |
1278 | ||
1279 | if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) { | |
1280 | if (otgsc & OTGSC_ID) | |
1281 | set_bit(ID, &motg->inputs); | |
1282 | else | |
1283 | clear_bit(ID, &motg->inputs); | |
1d4c9293 HK |
1284 | dev_dbg(phy->dev, "ID set/clear\n"); |
1285 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1286 | } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) { |
1287 | if (otgsc & OTGSC_BSV) | |
1288 | set_bit(B_SESS_VLD, &motg->inputs); | |
1289 | else | |
1290 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1d4c9293 HK |
1291 | dev_dbg(phy->dev, "BSV set/clear\n"); |
1292 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1293 | } |
1294 | ||
1295 | writel(otgsc, USB_OTGSC); | |
1296 | schedule_work(&motg->sm_work); | |
1297 | return IRQ_HANDLED; | |
1298 | } | |
1299 | ||
1300 | static int msm_otg_mode_show(struct seq_file *s, void *unused) | |
1301 | { | |
1302 | struct msm_otg *motg = s->private; | |
1d4c9293 | 1303 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1304 | |
e47d9254 | 1305 | switch (otg->state) { |
e0c201f3 | 1306 | case OTG_STATE_A_HOST: |
3aca0fa9 | 1307 | seq_puts(s, "host\n"); |
e0c201f3 PK |
1308 | break; |
1309 | case OTG_STATE_B_PERIPHERAL: | |
3aca0fa9 | 1310 | seq_puts(s, "peripheral\n"); |
e0c201f3 PK |
1311 | break; |
1312 | default: | |
3aca0fa9 | 1313 | seq_puts(s, "none\n"); |
e0c201f3 PK |
1314 | break; |
1315 | } | |
1316 | ||
1317 | return 0; | |
1318 | } | |
1319 | ||
1320 | static int msm_otg_mode_open(struct inode *inode, struct file *file) | |
1321 | { | |
1322 | return single_open(file, msm_otg_mode_show, inode->i_private); | |
1323 | } | |
1324 | ||
1325 | static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, | |
1326 | size_t count, loff_t *ppos) | |
1327 | { | |
e2904ee4 PK |
1328 | struct seq_file *s = file->private_data; |
1329 | struct msm_otg *motg = s->private; | |
e0c201f3 | 1330 | char buf[16]; |
1d4c9293 | 1331 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1332 | int status = count; |
971232cf | 1333 | enum usb_dr_mode req_mode; |
e0c201f3 PK |
1334 | |
1335 | memset(buf, 0x00, sizeof(buf)); | |
1336 | ||
1337 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) { | |
1338 | status = -EFAULT; | |
1339 | goto out; | |
1340 | } | |
1341 | ||
1342 | if (!strncmp(buf, "host", 4)) { | |
971232cf | 1343 | req_mode = USB_DR_MODE_HOST; |
e0c201f3 | 1344 | } else if (!strncmp(buf, "peripheral", 10)) { |
971232cf | 1345 | req_mode = USB_DR_MODE_PERIPHERAL; |
e0c201f3 | 1346 | } else if (!strncmp(buf, "none", 4)) { |
971232cf | 1347 | req_mode = USB_DR_MODE_UNKNOWN; |
e0c201f3 PK |
1348 | } else { |
1349 | status = -EINVAL; | |
1350 | goto out; | |
1351 | } | |
1352 | ||
1353 | switch (req_mode) { | |
971232cf | 1354 | case USB_DR_MODE_UNKNOWN: |
e47d9254 | 1355 | switch (otg->state) { |
e0c201f3 PK |
1356 | case OTG_STATE_A_HOST: |
1357 | case OTG_STATE_B_PERIPHERAL: | |
1358 | set_bit(ID, &motg->inputs); | |
1359 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1360 | break; | |
1361 | default: | |
1362 | goto out; | |
1363 | } | |
1364 | break; | |
971232cf | 1365 | case USB_DR_MODE_PERIPHERAL: |
e47d9254 | 1366 | switch (otg->state) { |
e0c201f3 PK |
1367 | case OTG_STATE_B_IDLE: |
1368 | case OTG_STATE_A_HOST: | |
1369 | set_bit(ID, &motg->inputs); | |
1370 | set_bit(B_SESS_VLD, &motg->inputs); | |
1371 | break; | |
1372 | default: | |
1373 | goto out; | |
1374 | } | |
1375 | break; | |
971232cf | 1376 | case USB_DR_MODE_HOST: |
e47d9254 | 1377 | switch (otg->state) { |
e0c201f3 PK |
1378 | case OTG_STATE_B_IDLE: |
1379 | case OTG_STATE_B_PERIPHERAL: | |
1380 | clear_bit(ID, &motg->inputs); | |
1381 | break; | |
1382 | default: | |
1383 | goto out; | |
1384 | } | |
1385 | break; | |
1386 | default: | |
1387 | goto out; | |
1388 | } | |
1389 | ||
19c1eac2 | 1390 | pm_runtime_get_sync(otg->usb_phy->dev); |
e0c201f3 PK |
1391 | schedule_work(&motg->sm_work); |
1392 | out: | |
1393 | return status; | |
1394 | } | |
1395 | ||
8f90afd9 | 1396 | static const struct file_operations msm_otg_mode_fops = { |
e0c201f3 PK |
1397 | .open = msm_otg_mode_open, |
1398 | .read = seq_read, | |
1399 | .write = msm_otg_mode_write, | |
1400 | .llseek = seq_lseek, | |
1401 | .release = single_release, | |
1402 | }; | |
1403 | ||
1404 | static struct dentry *msm_otg_dbg_root; | |
1405 | static struct dentry *msm_otg_dbg_mode; | |
1406 | ||
1407 | static int msm_otg_debugfs_init(struct msm_otg *motg) | |
1408 | { | |
1409 | msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL); | |
1410 | ||
1411 | if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root)) | |
1412 | return -ENODEV; | |
1413 | ||
1414 | msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR, | |
1415 | msm_otg_dbg_root, motg, &msm_otg_mode_fops); | |
1416 | if (!msm_otg_dbg_mode) { | |
1417 | debugfs_remove(msm_otg_dbg_root); | |
1418 | msm_otg_dbg_root = NULL; | |
1419 | return -ENODEV; | |
1420 | } | |
1421 | ||
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | static void msm_otg_debugfs_cleanup(void) | |
1426 | { | |
1427 | debugfs_remove(msm_otg_dbg_mode); | |
1428 | debugfs_remove(msm_otg_dbg_root); | |
1429 | } | |
1430 | ||
492240b0 | 1431 | static const struct of_device_id msm_otg_dt_match[] = { |
8364f9af II |
1432 | { |
1433 | .compatible = "qcom,usb-otg-ci", | |
1434 | .data = (void *) CI_45NM_INTEGRATED_PHY | |
1435 | }, | |
1436 | { | |
1437 | .compatible = "qcom,usb-otg-snps", | |
1438 | .data = (void *) SNPS_28NM_INTEGRATED_PHY | |
1439 | }, | |
1440 | { } | |
1441 | }; | |
1442 | MODULE_DEVICE_TABLE(of, msm_otg_dt_match); | |
1443 | ||
1444 | static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) | |
1445 | { | |
1446 | struct msm_otg_platform_data *pdata; | |
1447 | const struct of_device_id *id; | |
1448 | struct device_node *node = pdev->dev.of_node; | |
1449 | struct property *prop; | |
1450 | int len, ret, words; | |
01799b62 | 1451 | u32 val, tmp[3]; |
8364f9af II |
1452 | |
1453 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1454 | if (!pdata) | |
1455 | return -ENOMEM; | |
1456 | ||
1457 | motg->pdata = pdata; | |
1458 | ||
1459 | id = of_match_device(msm_otg_dt_match, &pdev->dev); | |
b3025e6a | 1460 | pdata->phy_type = (enum msm_usb_phy_type) id->data; |
8364f9af | 1461 | |
a2734543 II |
1462 | motg->link_rst = devm_reset_control_get(&pdev->dev, "link"); |
1463 | if (IS_ERR(motg->link_rst)) | |
1464 | return PTR_ERR(motg->link_rst); | |
1465 | ||
1466 | motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy"); | |
1467 | if (IS_ERR(motg->phy_rst)) | |
e44f1f4c | 1468 | motg->phy_rst = NULL; |
a2734543 | 1469 | |
8364f9af II |
1470 | pdata->mode = of_usb_get_dr_mode(node); |
1471 | if (pdata->mode == USB_DR_MODE_UNKNOWN) | |
1472 | pdata->mode = USB_DR_MODE_OTG; | |
1473 | ||
1474 | pdata->otg_control = OTG_PHY_CONTROL; | |
1475 | if (!of_property_read_u32(node, "qcom,otg-control", &val)) | |
1476 | if (val == OTG_PMIC_CONTROL) | |
1477 | pdata->otg_control = val; | |
1478 | ||
cfa3ff5d II |
1479 | if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2) |
1480 | motg->phy_number = val; | |
1481 | ||
01799b62 II |
1482 | motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL; |
1483 | motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN; | |
1484 | motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX; | |
1485 | ||
1486 | if (of_get_property(node, "qcom,vdd-levels", &len) && | |
1487 | len == sizeof(tmp)) { | |
1488 | of_property_read_u32_array(node, "qcom,vdd-levels", | |
1489 | tmp, len / sizeof(*tmp)); | |
1490 | motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE]; | |
1491 | motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN]; | |
1492 | motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX]; | |
1493 | } | |
1494 | ||
8364f9af II |
1495 | prop = of_find_property(node, "qcom,phy-init-sequence", &len); |
1496 | if (!prop || !len) | |
1497 | return 0; | |
1498 | ||
1499 | words = len / sizeof(u32); | |
1500 | ||
1501 | if (words >= ULPI_EXT_VENDOR_SPECIFIC) { | |
1502 | dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words); | |
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); | |
9da22206 | 1507 | if (!pdata->phy_init_seq) |
8364f9af | 1508 | return 0; |
8364f9af II |
1509 | |
1510 | ret = of_property_read_u32_array(node, "qcom,phy-init-sequence", | |
1511 | pdata->phy_init_seq, words); | |
1512 | if (!ret) | |
1513 | pdata->phy_init_sz = words; | |
1514 | ||
1515 | return 0; | |
1516 | } | |
1517 | ||
06a6ec44 | 1518 | static int msm_otg_probe(struct platform_device *pdev) |
e0c201f3 | 1519 | { |
6b99c68e | 1520 | struct regulator_bulk_data regs[3]; |
e0c201f3 | 1521 | int ret = 0; |
8364f9af II |
1522 | struct device_node *np = pdev->dev.of_node; |
1523 | struct msm_otg_platform_data *pdata; | |
e0c201f3 PK |
1524 | struct resource *res; |
1525 | struct msm_otg *motg; | |
1d4c9293 | 1526 | struct usb_phy *phy; |
30bf8667 | 1527 | void __iomem *phy_select; |
e0c201f3 | 1528 | |
6b99c68e | 1529 | motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL); |
9da22206 | 1530 | if (!motg) |
e0c201f3 | 1531 | return -ENOMEM; |
e0c201f3 | 1532 | |
8364f9af II |
1533 | pdata = dev_get_platdata(&pdev->dev); |
1534 | if (!pdata) { | |
1535 | if (!np) | |
1536 | return -ENXIO; | |
1537 | ret = msm_otg_read_dt(pdev, motg); | |
1538 | if (ret) | |
1539 | return ret; | |
1540 | } | |
1541 | ||
6b99c68e II |
1542 | motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
1543 | GFP_KERNEL); | |
9da22206 | 1544 | if (!motg->phy.otg) |
6b99c68e | 1545 | return -ENOMEM; |
1d4c9293 | 1546 | |
1d4c9293 HK |
1547 | phy = &motg->phy; |
1548 | phy->dev = &pdev->dev; | |
e0c201f3 | 1549 | |
8364f9af | 1550 | motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk"); |
e0c201f3 PK |
1551 | if (IS_ERR(motg->clk)) { |
1552 | dev_err(&pdev->dev, "failed to get usb_hs_clk\n"); | |
6b99c68e | 1553 | return PTR_ERR(motg->clk); |
e0c201f3 | 1554 | } |
0f73cac8 A |
1555 | |
1556 | /* | |
1557 | * If USB Core is running its protocol engine based on CORE CLK, | |
1558 | * CORE CLK must be running at >55Mhz for correct HSUSB | |
1559 | * operation and USB core cannot tolerate frequency changes on | |
ff0e4a68 | 1560 | * CORE CLK. |
0f73cac8 | 1561 | */ |
8364f9af | 1562 | motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk"); |
e0c201f3 PK |
1563 | if (IS_ERR(motg->pclk)) { |
1564 | dev_err(&pdev->dev, "failed to get usb_hs_pclk\n"); | |
6b99c68e | 1565 | return PTR_ERR(motg->pclk); |
e0c201f3 PK |
1566 | } |
1567 | ||
1568 | /* | |
1569 | * USB core clock is not present on all MSM chips. This | |
1570 | * clock is introduced to remove the dependency on AXI | |
1571 | * bus frequency. | |
1572 | */ | |
8364f9af II |
1573 | motg->core_clk = devm_clk_get(&pdev->dev, |
1574 | np ? "alt_core" : "usb_hs_core_clk"); | |
e0c201f3 PK |
1575 | |
1576 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2ea7b148 DC |
1577 | if (!res) |
1578 | return -EINVAL; | |
1579 | motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | |
1580 | if (!motg->regs) | |
1581 | return -ENOMEM; | |
e0c201f3 | 1582 | |
30bf8667 TB |
1583 | /* |
1584 | * NOTE: The PHYs can be multiplexed between the chipidea controller | |
1585 | * and the dwc3 controller, using a single bit. It is important that | |
1586 | * the dwc3 driver does not set this bit in an incompatible way. | |
1587 | */ | |
1588 | if (motg->phy_number) { | |
1589 | phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4); | |
716d28e2 WY |
1590 | if (!phy_select) |
1591 | return -ENOMEM; | |
30bf8667 | 1592 | /* Enable second PHY with the OTG port */ |
24597490 | 1593 | writel(0x1, phy_select); |
30bf8667 TB |
1594 | } |
1595 | ||
e0c201f3 PK |
1596 | dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs); |
1597 | ||
1598 | motg->irq = platform_get_irq(pdev, 0); | |
f60c114a | 1599 | if (motg->irq < 0) { |
e0c201f3 | 1600 | dev_err(&pdev->dev, "platform_get_irq failed\n"); |
6b99c68e II |
1601 | return motg->irq; |
1602 | } | |
1603 | ||
f5ef2372 II |
1604 | regs[0].supply = "vddcx"; |
1605 | regs[1].supply = "v3p3"; | |
1606 | regs[2].supply = "v1p8"; | |
6b99c68e II |
1607 | |
1608 | ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs); | |
1609 | if (ret) | |
1610 | return ret; | |
1611 | ||
1612 | motg->vddcx = regs[0].consumer; | |
1613 | motg->v3p3 = regs[1].consumer; | |
1614 | motg->v1p8 = regs[2].consumer; | |
1615 | ||
1616 | clk_set_rate(motg->clk, 60000000); | |
e0c201f3 | 1617 | |
b99a8f62 SB |
1618 | clk_prepare_enable(motg->clk); |
1619 | clk_prepare_enable(motg->pclk); | |
11aa5c47 | 1620 | |
6b99c68e II |
1621 | if (!IS_ERR(motg->core_clk)) |
1622 | clk_prepare_enable(motg->core_clk); | |
1623 | ||
11aa5c47 A |
1624 | ret = msm_hsusb_init_vddcx(motg, 1); |
1625 | if (ret) { | |
1626 | dev_err(&pdev->dev, "hsusb vddcx configuration failed\n"); | |
6b99c68e | 1627 | goto disable_clks; |
11aa5c47 A |
1628 | } |
1629 | ||
1630 | ret = msm_hsusb_ldo_init(motg, 1); | |
1631 | if (ret) { | |
1632 | dev_err(&pdev->dev, "hsusb vreg configuration failed\n"); | |
6b99c68e | 1633 | goto disable_vddcx; |
11aa5c47 | 1634 | } |
37cfdaf7 | 1635 | ret = msm_hsusb_ldo_set_mode(motg, 1); |
11aa5c47 A |
1636 | if (ret) { |
1637 | dev_err(&pdev->dev, "hsusb vreg enable failed\n"); | |
6b99c68e | 1638 | goto disable_ldo; |
11aa5c47 A |
1639 | } |
1640 | ||
e0c201f3 PK |
1641 | writel(0, USB_USBINTR); |
1642 | writel(0, USB_OTGSC); | |
1643 | ||
1644 | INIT_WORK(&motg->sm_work, msm_otg_sm_work); | |
d860852e | 1645 | INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work); |
6b99c68e | 1646 | ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED, |
e0c201f3 PK |
1647 | "msm_otg", motg); |
1648 | if (ret) { | |
1649 | dev_err(&pdev->dev, "request irq failed\n"); | |
6b99c68e | 1650 | goto disable_ldo; |
e0c201f3 PK |
1651 | } |
1652 | ||
d69c6f5d | 1653 | phy->init = msm_phy_init; |
1d4c9293 | 1654 | phy->set_power = msm_otg_set_power; |
349907c2 | 1655 | phy->notify_disconnect = msm_phy_notify_disconnect; |
e695abb3 | 1656 | phy->type = USB_PHY_TYPE_USB2; |
1d4c9293 HK |
1657 | |
1658 | phy->io_ops = &msm_otg_io_ops; | |
e0c201f3 | 1659 | |
19c1eac2 | 1660 | phy->otg->usb_phy = &motg->phy; |
1d4c9293 HK |
1661 | phy->otg->set_host = msm_otg_set_host; |
1662 | phy->otg->set_peripheral = msm_otg_set_peripheral; | |
e0c201f3 | 1663 | |
d69c6f5d II |
1664 | msm_usb_reset(phy); |
1665 | ||
e695abb3 | 1666 | ret = usb_add_phy_dev(&motg->phy); |
e0c201f3 | 1667 | if (ret) { |
721002ec | 1668 | dev_err(&pdev->dev, "usb_add_phy failed\n"); |
6b99c68e | 1669 | goto disable_ldo; |
e0c201f3 PK |
1670 | } |
1671 | ||
1672 | platform_set_drvdata(pdev, motg); | |
1673 | device_init_wakeup(&pdev->dev, 1); | |
1674 | ||
971232cf | 1675 | if (motg->pdata->mode == USB_DR_MODE_OTG && |
8364f9af | 1676 | motg->pdata->otg_control == OTG_USER_CONTROL) { |
e0c201f3 PK |
1677 | ret = msm_otg_debugfs_init(motg); |
1678 | if (ret) | |
3aca0fa9 | 1679 | dev_dbg(&pdev->dev, "Can not create mode change file\n"); |
e0c201f3 PK |
1680 | } |
1681 | ||
87c0104a PK |
1682 | pm_runtime_set_active(&pdev->dev); |
1683 | pm_runtime_enable(&pdev->dev); | |
e0c201f3 | 1684 | |
87c0104a | 1685 | return 0; |
6b99c68e II |
1686 | |
1687 | disable_ldo: | |
1688 | msm_hsusb_ldo_init(motg, 0); | |
1689 | disable_vddcx: | |
1690 | msm_hsusb_init_vddcx(motg, 0); | |
e0c201f3 | 1691 | disable_clks: |
b99a8f62 SB |
1692 | clk_disable_unprepare(motg->pclk); |
1693 | clk_disable_unprepare(motg->clk); | |
6b99c68e II |
1694 | if (!IS_ERR(motg->core_clk)) |
1695 | clk_disable_unprepare(motg->core_clk); | |
e0c201f3 PK |
1696 | return ret; |
1697 | } | |
1698 | ||
fb4e98ab | 1699 | static int msm_otg_remove(struct platform_device *pdev) |
e0c201f3 PK |
1700 | { |
1701 | struct msm_otg *motg = platform_get_drvdata(pdev); | |
1d4c9293 | 1702 | struct usb_phy *phy = &motg->phy; |
87c0104a | 1703 | int cnt = 0; |
e0c201f3 | 1704 | |
1d4c9293 | 1705 | if (phy->otg->host || phy->otg->gadget) |
e0c201f3 PK |
1706 | return -EBUSY; |
1707 | ||
1708 | msm_otg_debugfs_cleanup(); | |
d860852e | 1709 | cancel_delayed_work_sync(&motg->chg_work); |
e0c201f3 | 1710 | cancel_work_sync(&motg->sm_work); |
87c0104a | 1711 | |
7018773a | 1712 | pm_runtime_resume(&pdev->dev); |
87c0104a | 1713 | |
e0c201f3 | 1714 | device_init_wakeup(&pdev->dev, 0); |
87c0104a | 1715 | pm_runtime_disable(&pdev->dev); |
e0c201f3 | 1716 | |
662dca54 | 1717 | usb_remove_phy(phy); |
6b99c68e | 1718 | disable_irq(motg->irq); |
e0c201f3 | 1719 | |
87c0104a PK |
1720 | /* |
1721 | * Put PHY in low power mode. | |
1722 | */ | |
1d4c9293 HK |
1723 | ulpi_read(phy, 0x14); |
1724 | ulpi_write(phy, 0x08, 0x09); | |
87c0104a PK |
1725 | |
1726 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
1727 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
1728 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
1729 | break; | |
1730 | udelay(1); | |
1731 | cnt++; | |
1732 | } | |
1733 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) | |
1d4c9293 | 1734 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
87c0104a | 1735 | |
b99a8f62 SB |
1736 | clk_disable_unprepare(motg->pclk); |
1737 | clk_disable_unprepare(motg->clk); | |
6b99c68e | 1738 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 1739 | clk_disable_unprepare(motg->core_clk); |
11aa5c47 | 1740 | msm_hsusb_ldo_init(motg, 0); |
e0c201f3 | 1741 | |
87c0104a | 1742 | pm_runtime_set_suspended(&pdev->dev); |
e0c201f3 | 1743 | |
e0c201f3 PK |
1744 | return 0; |
1745 | } | |
1746 | ||
ceb6c9c8 | 1747 | #ifdef CONFIG_PM |
87c0104a PK |
1748 | static int msm_otg_runtime_idle(struct device *dev) |
1749 | { | |
1750 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1d4c9293 | 1751 | struct usb_otg *otg = motg->phy.otg; |
87c0104a PK |
1752 | |
1753 | dev_dbg(dev, "OTG runtime idle\n"); | |
1754 | ||
1755 | /* | |
1756 | * It is observed some times that a spurious interrupt | |
1757 | * comes when PHY is put into LPM immediately after PHY reset. | |
1758 | * This 1 sec delay also prevents entering into LPM immediately | |
1759 | * after asynchronous interrupt. | |
1760 | */ | |
e47d9254 | 1761 | if (otg->state != OTG_STATE_UNDEFINED) |
87c0104a PK |
1762 | pm_schedule_suspend(dev, 1000); |
1763 | ||
1764 | return -EAGAIN; | |
1765 | } | |
1766 | ||
1767 | static int msm_otg_runtime_suspend(struct device *dev) | |
1768 | { | |
1769 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1770 | ||
1771 | dev_dbg(dev, "OTG runtime suspend\n"); | |
1772 | return msm_otg_suspend(motg); | |
1773 | } | |
1774 | ||
1775 | static int msm_otg_runtime_resume(struct device *dev) | |
1776 | { | |
1777 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1778 | ||
1779 | dev_dbg(dev, "OTG runtime resume\n"); | |
1780 | return msm_otg_resume(motg); | |
1781 | } | |
87c0104a PK |
1782 | #endif |
1783 | ||
7018773a | 1784 | #ifdef CONFIG_PM_SLEEP |
87c0104a PK |
1785 | static int msm_otg_pm_suspend(struct device *dev) |
1786 | { | |
1787 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1788 | ||
1789 | dev_dbg(dev, "OTG PM suspend\n"); | |
1790 | return msm_otg_suspend(motg); | |
1791 | } | |
1792 | ||
1793 | static int msm_otg_pm_resume(struct device *dev) | |
1794 | { | |
1795 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1796 | int ret; | |
1797 | ||
1798 | dev_dbg(dev, "OTG PM resume\n"); | |
1799 | ||
1800 | ret = msm_otg_resume(motg); | |
1801 | if (ret) | |
1802 | return ret; | |
1803 | ||
1804 | /* | |
1805 | * Runtime PM Documentation recommends bringing the | |
1806 | * device to full powered state upon resume. | |
1807 | */ | |
1808 | pm_runtime_disable(dev); | |
1809 | pm_runtime_set_active(dev); | |
1810 | pm_runtime_enable(dev); | |
1811 | ||
1812 | return 0; | |
1813 | } | |
87c0104a PK |
1814 | #endif |
1815 | ||
1816 | static const struct dev_pm_ops msm_otg_dev_pm_ops = { | |
7018773a PK |
1817 | SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume) |
1818 | SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume, | |
1819 | msm_otg_runtime_idle) | |
87c0104a PK |
1820 | }; |
1821 | ||
e0c201f3 | 1822 | static struct platform_driver msm_otg_driver = { |
06a6ec44 | 1823 | .probe = msm_otg_probe, |
7690417d | 1824 | .remove = msm_otg_remove, |
e0c201f3 PK |
1825 | .driver = { |
1826 | .name = DRIVER_NAME, | |
87c0104a | 1827 | .pm = &msm_otg_dev_pm_ops, |
8364f9af | 1828 | .of_match_table = msm_otg_dt_match, |
e0c201f3 PK |
1829 | }, |
1830 | }; | |
1831 | ||
06a6ec44 | 1832 | module_platform_driver(msm_otg_driver); |
e0c201f3 PK |
1833 | |
1834 | MODULE_LICENSE("GPL v2"); | |
1835 | MODULE_DESCRIPTION("MSM USB transceiver driver"); |