projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'usb-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi...
[deliverable/linux.git] / drivers / usb / phy / phy-msm-usb.c
CommitLineData
d860852e 1/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
e0c201f3
PK		 2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23#include <linux/slab.h>
24#include <linux/interrupt.h>
25#include <linux/err.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/ioport.h>
29#include <linux/uaccess.h>
30#include <linux/debugfs.h>
31#include <linux/seq_file.h>
87c0104a 32#include <linux/pm_runtime.h>
8364f9af
II		 33#include <linux/of.h>
34#include <linux/of_device.h>
a2734543 35#include <linux/reset.h>
e0c201f3
PK		 36
37#include <linux/usb.h>
38#include <linux/usb/otg.h>
8364f9af 39#include <linux/usb/of.h>
e0c201f3
PK		 40#include <linux/usb/ulpi.h>
41#include <linux/usb/gadget.h>
42#include <linux/usb/hcd.h>
43#include <linux/usb/msm_hsusb.h>
44#include <linux/usb/msm_hsusb_hw.h>
11aa5c47 45#include <linux/regulator/consumer.h>
e0c201f3 46
e0c201f3
PK		 47#define MSM_USB_BASE (motg->regs)
48#define DRIVER_NAME "msm_otg"
49
50#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
d69c6f5d 51#define LINK_RESET_TIMEOUT_USEC (250 * 1000)
11aa5c47
A		 52
53#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
54#define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
55#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
56#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
57
58#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
59#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
60#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
61#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
62
63#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
64#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
01799b62
II		 65#define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
66
67enum vdd_levels {
68 VDD_LEVEL_NONE = 0,
69 VDD_LEVEL_MIN,
70 VDD_LEVEL_MAX,
71};
11aa5c47 72
11aa5c47
A		 73static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
74{
75 int ret = 0;
76
77 if (init) {
37cfdaf7 78 ret = regulator_set_voltage(motg->vddcx,
01799b62
II		 79 motg->vdd_levels[VDD_LEVEL_MIN],
80 motg->vdd_levels[VDD_LEVEL_MAX]);
11aa5c47 81 if (ret) {
3aca0fa9 82 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
11aa5c47
A		 83 return ret;
84 }
85
37cfdaf7 86 ret = regulator_enable(motg->vddcx);
6b99c68e 87 if (ret)
1d4c9293 88 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
11aa5c47 89 } else {
37cfdaf7 90 ret = regulator_set_voltage(motg->vddcx, 0,
01799b62 91 motg->vdd_levels[VDD_LEVEL_MAX]);
e99c4309 92 if (ret)
3aca0fa9 93 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
37cfdaf7 94 ret = regulator_disable(motg->vddcx);
11aa5c47 95 if (ret)
1d4c9293 96 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
11aa5c47
A		 97 }
98
99 return ret;
100}
101
102static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
103{
104 int rc = 0;
105
106 if (init) {
37cfdaf7 107 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
11aa5c47
A		 108 USB_PHY_3P3_VOL_MAX);
109 if (rc) {
3aca0fa9 110 dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
6b99c68e 111 goto exit;
11aa5c47 112 }
37cfdaf7 113 rc = regulator_enable(motg->v3p3);
11aa5c47 114 if (rc) {
1d4c9293 115 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
6b99c68e 116 goto exit;
11aa5c47 117 }
37cfdaf7 118 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
11aa5c47
A		 119 USB_PHY_1P8_VOL_MAX);
120 if (rc) {
3aca0fa9 121 dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
6b99c68e 122 goto disable_3p3;
11aa5c47 123 }
37cfdaf7 124 rc = regulator_enable(motg->v1p8);
11aa5c47 125 if (rc) {
1d4c9293 126 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
6b99c68e 127 goto disable_3p3;
11aa5c47
A		 128 }
129
130 return 0;
131 }
132
37cfdaf7 133 regulator_disable(motg->v1p8);
11aa5c47 134disable_3p3:
37cfdaf7 135 regulator_disable(motg->v3p3);
6b99c68e 136exit:
11aa5c47
A		 137 return rc;
138}
139
37cfdaf7 140static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
11aa5c47
A		 141{
142 int ret = 0;
143
11aa5c47 144 if (on) {
37cfdaf7 145 ret = regulator_set_optimum_mode(motg->v1p8,
11aa5c47
A		 146 USB_PHY_1P8_HPM_LOAD);
147 if (ret < 0) {
3aca0fa9 148 pr_err("Could not set HPM for v1p8\n");
11aa5c47
A		 149 return ret;
150 }
37cfdaf7 151 ret = regulator_set_optimum_mode(motg->v3p3,
11aa5c47
A		 152 USB_PHY_3P3_HPM_LOAD);
153 if (ret < 0) {
3aca0fa9 154 pr_err("Could not set HPM for v3p3\n");
37cfdaf7 155 regulator_set_optimum_mode(motg->v1p8,
11aa5c47
A		 156 USB_PHY_1P8_LPM_LOAD);
157 return ret;
158 }
159 } else {
37cfdaf7 160 ret = regulator_set_optimum_mode(motg->v1p8,
11aa5c47
A		 161 USB_PHY_1P8_LPM_LOAD);
162 if (ret < 0)
3aca0fa9 163 pr_err("Could not set LPM for v1p8\n");
37cfdaf7 164 ret = regulator_set_optimum_mode(motg->v3p3,
11aa5c47
A		 165 USB_PHY_3P3_LPM_LOAD);
166 if (ret < 0)
3aca0fa9 167 pr_err("Could not set LPM for v3p3\n");
11aa5c47
A		 168 }
169
170 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
171 return ret < 0 ? ret : 0;
172}
173
1d4c9293 174static int ulpi_read(struct usb_phy *phy, u32 reg)
e0c201f3 175{
1d4c9293 176 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
e0c201f3
PK		 177 int cnt = 0;
178
179 /* initiate read operation */
180 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
181 USB_ULPI_VIEWPORT);
182
183 /* wait for completion */
184 while (cnt < ULPI_IO_TIMEOUT_USEC) {
185 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
186 break;
187 udelay(1);
188 cnt++;
189 }
190
191 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
1d4c9293 192 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
e0c201f3
PK		 193 readl(USB_ULPI_VIEWPORT));
194 return -ETIMEDOUT;
195 }
196 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
197}
198
1d4c9293 199static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
e0c201f3 200{
1d4c9293 201 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
e0c201f3
PK		 202 int cnt = 0;
203
204 /* initiate write operation */
205 writel(ULPI_RUN | ULPI_WRITE |
206 ULPI_ADDR(reg) | ULPI_DATA(val),
207 USB_ULPI_VIEWPORT);
208
209 /* wait for completion */
210 while (cnt < ULPI_IO_TIMEOUT_USEC) {
211 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
212 break;
213 udelay(1);
214 cnt++;
215 }
216
217 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
1d4c9293 218 dev_err(phy->dev, "ulpi_write: timeout\n");
e0c201f3
PK		 219 return -ETIMEDOUT;
220 }
221 return 0;
222}
223
1d4c9293 224static struct usb_phy_io_ops msm_otg_io_ops = {
e0c201f3
PK		 225 .read = ulpi_read,
226 .write = ulpi_write,
227};
228
229static void ulpi_init(struct msm_otg *motg)
230{
231 struct msm_otg_platform_data *pdata = motg->pdata;
8364f9af
II		 232 int *seq = pdata->phy_init_seq, idx;
233 u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
e0c201f3 234
8364f9af
II		 235 for (idx = 0; idx < pdata->phy_init_sz; idx++) {
236 if (seq[idx] == -1)
237 continue;
e0c201f3 238
1d4c9293 239 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
8364f9af
II		 240 seq[idx], addr + idx);
241 ulpi_write(&motg->phy, seq[idx], addr + idx);
e0c201f3
PK		 242 }
243}
244
349907c2
II		 245static int msm_phy_notify_disconnect(struct usb_phy *phy,
246 enum usb_device_speed speed)
247{
248 int val;
249
250 /*
251 * Put the transceiver in non-driving mode. Otherwise host
252 * may not detect soft-disconnection.
253 */
254 val = ulpi_read(phy, ULPI_FUNC_CTRL);
255 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
256 val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
257 ulpi_write(phy, val, ULPI_FUNC_CTRL);
258
259 return 0;
260}
261
e0c201f3
PK		 262static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
263{
a2734543 264 int ret;
5146d771 265
a2734543
II		 266 if (motg->pdata->link_clk_reset)
267 ret = motg->pdata->link_clk_reset(motg->clk, assert);
268 else if (assert)
269 ret = reset_control_assert(motg->link_rst);
270 else
271 ret = reset_control_deassert(motg->link_rst);
5146d771 272
5146d771
II		 273 if (ret)
274 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
275 assert ? "assert" : "deassert");
e0c201f3 276
e0c201f3
PK		 277 return ret;
278}
279
280static int msm_otg_phy_clk_reset(struct msm_otg *motg)
281{
e44f1f4c 282 int ret = 0;
e0c201f3 283
a1a4caf4 284 if (motg->pdata->phy_clk_reset)
a2734543 285 ret = motg->pdata->phy_clk_reset(motg->phy_reset_clk);
e44f1f4c 286 else if (motg->phy_rst)
a2734543 287 ret = reset_control_reset(motg->phy_rst);
5146d771 288
e0c201f3 289 if (ret)
5146d771
II		 290 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
291
e0c201f3
PK		 292 return ret;
293}
294
d69c6f5d 295static int msm_link_reset(struct msm_otg *motg)
e0c201f3
PK		 296{
297 u32 val;
298 int ret;
e0c201f3
PK		 299
300 ret = msm_otg_link_clk_reset(motg, 1);
e0c201f3
PK		 301 if (ret)
302 return ret;
303
d69c6f5d
II		 304 /* wait for 1ms delay as suggested in HPG. */
305 usleep_range(1000, 1200);
e0c201f3 306
d69c6f5d 307 ret = msm_otg_link_clk_reset(motg, 0);
e0c201f3
PK		 308 if (ret)
309 return ret;
310
cfa3ff5d
II		 311 if (motg->phy_number)
312 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
313
9f27984b 314 /* put transceiver in serial mode as part of reset */
d69c6f5d 315 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
9f27984b 316 writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
d69c6f5d 317
e0c201f3
PK		 318 return 0;
319}
320
1d4c9293 321static int msm_otg_reset(struct usb_phy *phy)
e0c201f3 322{
1d4c9293 323 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
e0c201f3 324 int cnt = 0;
e0c201f3
PK		 325
326 writel(USBCMD_RESET, USB_USBCMD);
327 while (cnt < LINK_RESET_TIMEOUT_USEC) {
328 if (!(readl(USB_USBCMD) & USBCMD_RESET))
329 break;
330 udelay(1);
331 cnt++;
332 }
333 if (cnt >= LINK_RESET_TIMEOUT_USEC)
334 return -ETIMEDOUT;
335
9f27984b
TB		 336 /* select ULPI phy and clear other status/control bits in PORTSC */
337 writel(PORTSC_PTS_ULPI, USB_PORTSC);
338
d69c6f5d
II		 339 writel(0x0, USB_AHBBURST);
340 writel(0x08, USB_AHBMODE);
341
342 if (motg->phy_number)
343 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
344 return 0;
345}
346
347static void msm_phy_reset(struct msm_otg *motg)
348{
349 void __iomem *addr;
350
351 if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
352 msm_otg_phy_clk_reset(motg);
353 return;
354 }
355
356 addr = USB_PHY_CTRL;
357 if (motg->phy_number)
358 addr = USB_PHY_CTRL2;
359
360 /* Assert USB PHY_POR */
361 writel(readl(addr) | PHY_POR_ASSERT, addr);
362
363 /*
364 * wait for minimum 10 microseconds as suggested in HPG.
365 * Use a slightly larger value since the exact value didn't
366 * work 100% of the time.
367 */
368 udelay(12);
369
370 /* Deassert USB PHY_POR */
371 writel(readl(addr) & ~PHY_POR_ASSERT, addr);
372}
373
374static int msm_usb_reset(struct usb_phy *phy)
375{
376 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
377 int ret;
378
379 if (!IS_ERR(motg->core_clk))
380 clk_prepare_enable(motg->core_clk);
381
382 ret = msm_link_reset(motg);
383 if (ret) {
384 dev_err(phy->dev, "phy_reset failed\n");
385 return ret;
386 }
387
388 ret = msm_otg_reset(&motg->phy);
389 if (ret) {
390 dev_err(phy->dev, "link reset failed\n");
391 return ret;
392 }
e0c201f3
PK		 393
394 msleep(100);
395
d69c6f5d
II		 396 /* Reset USB PHY after performing USB Link RESET */
397 msm_phy_reset(motg);
398
399 if (!IS_ERR(motg->core_clk))
400 clk_disable_unprepare(motg->core_clk);
401
402 return 0;
403}
404
405static int msm_phy_init(struct usb_phy *phy)
406{
407 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
408 struct msm_otg_platform_data *pdata = motg->pdata;
409 u32 val, ulpi_val = 0;
410
411 /* Program USB PHY Override registers. */
412 ulpi_init(motg);
413
414 /*
415 * It is recommended in HPG to reset USB PHY after programming
416 * USB PHY Override registers.
417 */
418 msm_phy_reset(motg);
e0c201f3
PK		 419
420 if (pdata->otg_control == OTG_PHY_CONTROL) {
421 val = readl(USB_OTGSC);
971232cf 422 if (pdata->mode == USB_DR_MODE_OTG) {
e0c201f3
PK		 423 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
424 val |= OTGSC_IDIE | OTGSC_BSVIE;
971232cf 425 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
e0c201f3
PK		 426 ulpi_val = ULPI_INT_SESS_VALID;
427 val |= OTGSC_BSVIE;
428 }
429 writel(val, USB_OTGSC);
1d4c9293
HK		 430 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
431 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
e0c201f3
PK		 432 }
433
cfa3ff5d
II		 434 if (motg->phy_number)
435 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
436
e0c201f3
PK		 437 return 0;
438}
439
87c0104a 440#define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
7018773a
PK		 441#define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
442
e7d613d1
JC		 443#ifdef CONFIG_PM
444
37cfdaf7 445static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
e7d613d1 446{
01799b62 447 int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
e7d613d1
JC		 448 int min_vol;
449 int ret;
450
451 if (high)
01799b62 452 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
e7d613d1 453 else
01799b62 454 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
e7d613d1 455
37cfdaf7 456 ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
e7d613d1 457 if (ret) {
3aca0fa9 458 pr_err("Cannot set vddcx voltage\n");
e7d613d1
JC		 459 return ret;
460 }
461
462 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
463
464 return ret;
465}
466
87c0104a
PK		 467static int msm_otg_suspend(struct msm_otg *motg)
468{
1d4c9293
HK		 469 struct usb_phy *phy = &motg->phy;
470 struct usb_bus *bus = phy->otg->host;
87c0104a 471 struct msm_otg_platform_data *pdata = motg->pdata;
cfa3ff5d 472 void __iomem *addr;
87c0104a
PK		 473 int cnt = 0;
474
475 if (atomic_read(&motg->in_lpm))
476 return 0;
477
478 disable_irq(motg->irq);
479 /*
04aebcbb
PK		 480 * Chipidea 45-nm PHY suspend sequence:
481 *
87c0104a
PK		 482 * Interrupt Latch Register auto-clear feature is not present
483 * in all PHY versions. Latch register is clear on read type.
484 * Clear latch register to avoid spurious wakeup from
485 * low power mode (LPM).
04aebcbb 486 *
87c0104a
PK		 487 * PHY comparators are disabled when PHY enters into low power
488 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
489 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
490 * PHY comparators. This save significant amount of power.
04aebcbb 491 *
87c0104a
PK		 492 * PLL is not turned off when PHY enters into low power mode (LPM).
493 * Disable PLL for maximum power savings.
494 */
04aebcbb
PK		 495
496 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
1d4c9293 497 ulpi_read(phy, 0x14);
04aebcbb 498 if (pdata->otg_control == OTG_PHY_CONTROL)
1d4c9293
HK		 499 ulpi_write(phy, 0x01, 0x30);
500 ulpi_write(phy, 0x08, 0x09);
04aebcbb 501 }
87c0104a
PK		 502
503 /*
504 * PHY may take some time or even fail to enter into low power
505 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
506 * in failure case.
507 */
508 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
509 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
510 if (readl(USB_PORTSC) & PORTSC_PHCD)
511 break;
512 udelay(1);
513 cnt++;
514 }
515
516 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
1d4c9293
HK		 517 dev_err(phy->dev, "Unable to suspend PHY\n");
518 msm_otg_reset(phy);
87c0104a
PK		 519 enable_irq(motg->irq);
520 return -ETIMEDOUT;
521 }
522
523 /*
524 * PHY has capability to generate interrupt asynchronously in low
525 * power mode (LPM). This interrupt is level triggered. So USB IRQ
526 * line must be disabled till async interrupt enable bit is cleared
527 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
528 * block data communication from PHY.
529 */
530 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
531
cfa3ff5d
II		 532 addr = USB_PHY_CTRL;
533 if (motg->phy_number)
534 addr = USB_PHY_CTRL2;
535
04aebcbb
PK		 536 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
537 motg->pdata->otg_control == OTG_PMIC_CONTROL)
cfa3ff5d 538 writel(readl(addr) | PHY_RETEN, addr);
04aebcbb 539
b99a8f62
SB		 540 clk_disable_unprepare(motg->pclk);
541 clk_disable_unprepare(motg->clk);
6b99c68e 542 if (!IS_ERR(motg->core_clk))
b99a8f62 543 clk_disable_unprepare(motg->core_clk);
87c0104a 544
04aebcbb
PK		 545 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
546 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
37cfdaf7
II		 547 msm_hsusb_ldo_set_mode(motg, 0);
548 msm_hsusb_config_vddcx(motg, 0);
04aebcbb
PK		 549 }
550
1d4c9293 551 if (device_may_wakeup(phy->dev))
87c0104a
PK		 552 enable_irq_wake(motg->irq);
553 if (bus)
554 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
555
556 atomic_set(&motg->in_lpm, 1);
557 enable_irq(motg->irq);
558
1d4c9293 559 dev_info(phy->dev, "USB in low power mode\n");
87c0104a
PK		 560
561 return 0;
562}
563
87c0104a
PK		 564static int msm_otg_resume(struct msm_otg *motg)
565{
1d4c9293
HK		 566 struct usb_phy *phy = &motg->phy;
567 struct usb_bus *bus = phy->otg->host;
cfa3ff5d 568 void __iomem *addr;
87c0104a
PK		 569 int cnt = 0;
570 unsigned temp;
571
572 if (!atomic_read(&motg->in_lpm))
573 return 0;
574
b99a8f62
SB		 575 clk_prepare_enable(motg->pclk);
576 clk_prepare_enable(motg->clk);
6b99c68e 577 if (!IS_ERR(motg->core_clk))
b99a8f62 578 clk_prepare_enable(motg->core_clk);
87c0104a 579
04aebcbb
PK		 580 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
581 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
cfa3ff5d
II		 582
583 addr = USB_PHY_CTRL;
584 if (motg->phy_number)
585 addr = USB_PHY_CTRL2;
586
37cfdaf7
II		 587 msm_hsusb_ldo_set_mode(motg, 1);
588 msm_hsusb_config_vddcx(motg, 1);
cfa3ff5d 589 writel(readl(addr) & ~PHY_RETEN, addr);
04aebcbb
PK		 590 }
591
87c0104a
PK		 592 temp = readl(USB_USBCMD);
593 temp &= ~ASYNC_INTR_CTRL;
594 temp &= ~ULPI_STP_CTRL;
595 writel(temp, USB_USBCMD);
596
597 /*
598 * PHY comes out of low power mode (LPM) in case of wakeup
599 * from asynchronous interrupt.
600 */
601 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
602 goto skip_phy_resume;
603
604 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
605 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
606 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
607 break;
608 udelay(1);
609 cnt++;
610 }
611
612 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
613 /*
614 * This is a fatal error. Reset the link and
615 * PHY. USB state can not be restored. Re-insertion
616 * of USB cable is the only way to get USB working.
617 */
3aca0fa9 618 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
1d4c9293 619 msm_otg_reset(phy);
87c0104a
PK		 620 }
621
622skip_phy_resume:
1d4c9293 623 if (device_may_wakeup(phy->dev))
87c0104a
PK		 624 disable_irq_wake(motg->irq);
625 if (bus)
626 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
627
2ce2c3ac
PK		 628 atomic_set(&motg->in_lpm, 0);
629
87c0104a
PK		 630 if (motg->async_int) {
631 motg->async_int = 0;
1d4c9293 632 pm_runtime_put(phy->dev);
87c0104a
PK		 633 enable_irq(motg->irq);
634 }
635
1d4c9293 636 dev_info(phy->dev, "USB exited from low power mode\n");
87c0104a
PK		 637
638 return 0;
639}
7018773a 640#endif
87c0104a 641
d860852e
PK		 642static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
643{
644 if (motg->cur_power == mA)
645 return;
646
647 /* TODO: Notify PMIC about available current */
1d4c9293 648 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
d860852e
PK		 649 motg->cur_power = mA;
650}
651
1d4c9293 652static int msm_otg_set_power(struct usb_phy *phy, unsigned mA)
d860852e 653{
1d4c9293 654 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
d860852e
PK		 655
656 /*
657 * Gadget driver uses set_power method to notify about the
658 * available current based on suspend/configured states.
659 *
660 * IDEV_CHG can be drawn irrespective of suspend/un-configured
661 * states when CDP/ACA is connected.
662 */
663 if (motg->chg_type == USB_SDP_CHARGER)
664 msm_otg_notify_charger(motg, mA);
665
666 return 0;
667}
668
1d4c9293 669static void msm_otg_start_host(struct usb_phy *phy, int on)
e0c201f3 670{
1d4c9293 671 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
e0c201f3
PK		 672 struct msm_otg_platform_data *pdata = motg->pdata;
673 struct usb_hcd *hcd;
674
1d4c9293 675 if (!phy->otg->host)
e0c201f3
PK		 676 return;
677
1d4c9293 678 hcd = bus_to_hcd(phy->otg->host);
e0c201f3
PK		 679
680 if (on) {
1d4c9293 681 dev_dbg(phy->dev, "host on\n");
e0c201f3
PK		 682
683 if (pdata->vbus_power)
684 pdata->vbus_power(1);
685 /*
686 * Some boards have a switch cotrolled by gpio
687 * to enable/disable internal HUB. Enable internal
688 * HUB before kicking the host.
689 */
690 if (pdata->setup_gpio)
691 pdata->setup_gpio(OTG_STATE_A_HOST);
692#ifdef CONFIG_USB
693 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
3c9740a1 694 device_wakeup_enable(hcd->self.controller);
e0c201f3
PK		 695#endif
696 } else {
1d4c9293 697 dev_dbg(phy->dev, "host off\n");
e0c201f3
PK		 698
699#ifdef CONFIG_USB
700 usb_remove_hcd(hcd);
701#endif
702 if (pdata->setup_gpio)
703 pdata->setup_gpio(OTG_STATE_UNDEFINED);
704 if (pdata->vbus_power)
705 pdata->vbus_power(0);
706 }
707}
708
1d4c9293 709static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
e0c201f3 710{
19c1eac2 711 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
e0c201f3
PK		 712 struct usb_hcd *hcd;
713
714 /*
715 * Fail host registration if this board can support
716 * only peripheral configuration.
717 */
971232cf 718 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
19c1eac2 719 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
e0c201f3
PK		 720 return -ENODEV;
721 }
722
723 if (!host) {
e47d9254 724 if (otg->state == OTG_STATE_A_HOST) {
19c1eac2
AT		 725 pm_runtime_get_sync(otg->usb_phy->dev);
726 msm_otg_start_host(otg->usb_phy, 0);
e0c201f3 727 otg->host = NULL;
e47d9254 728 otg->state = OTG_STATE_UNDEFINED;
e0c201f3
PK		 729 schedule_work(&motg->sm_work);
730 } else {
731 otg->host = NULL;
732 }
733
734 return 0;
735 }
736
737 hcd = bus_to_hcd(host);
738 hcd->power_budget = motg->pdata->power_budget;
739
740 otg->host = host;
19c1eac2 741 dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
e0c201f3
PK		 742
743 /*
744 * Kick the state machine work, if peripheral is not supported
745 * or peripheral is already registered with us.
746 */
971232cf 747 if (motg->pdata->mode == USB_DR_MODE_HOST || otg->gadget) {
19c1eac2 748 pm_runtime_get_sync(otg->usb_phy->dev);
e0c201f3 749 schedule_work(&motg->sm_work);
87c0104a 750 }
e0c201f3
PK		 751
752 return 0;
753}
754
1d4c9293 755static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
e0c201f3 756{
1d4c9293 757 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
e0c201f3
PK		 758 struct msm_otg_platform_data *pdata = motg->pdata;
759
1d4c9293 760 if (!phy->otg->gadget)
e0c201f3
PK		 761 return;
762
763 if (on) {
1d4c9293 764 dev_dbg(phy->dev, "gadget on\n");
e0c201f3
PK		 765 /*
766 * Some boards have a switch cotrolled by gpio
767 * to enable/disable internal HUB. Disable internal
768 * HUB before kicking the gadget.
769 */
770 if (pdata->setup_gpio)
771 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
1d4c9293 772 usb_gadget_vbus_connect(phy->otg->gadget);
e0c201f3 773 } else {
1d4c9293
HK		 774 dev_dbg(phy->dev, "gadget off\n");
775 usb_gadget_vbus_disconnect(phy->otg->gadget);
e0c201f3
PK		 776 if (pdata->setup_gpio)
777 pdata->setup_gpio(OTG_STATE_UNDEFINED);
778 }
779
780}
781
1d4c9293
HK		 782static int msm_otg_set_peripheral(struct usb_otg *otg,
783 struct usb_gadget *gadget)
e0c201f3 784{
19c1eac2 785 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
e0c201f3
PK		 786
787 /*
788 * Fail peripheral registration if this board can support
789 * only host configuration.
790 */
971232cf 791 if (motg->pdata->mode == USB_DR_MODE_HOST) {
19c1eac2 792 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
e0c201f3
PK		 793 return -ENODEV;
794 }
795
796 if (!gadget) {
e47d9254 797 if (otg->state == OTG_STATE_B_PERIPHERAL) {
19c1eac2
AT		 798 pm_runtime_get_sync(otg->usb_phy->dev);
799 msm_otg_start_peripheral(otg->usb_phy, 0);
e0c201f3 800 otg->gadget = NULL;
e47d9254 801 otg->state = OTG_STATE_UNDEFINED;
e0c201f3
PK		 802 schedule_work(&motg->sm_work);
803 } else {
804 otg->gadget = NULL;
805 }
806
807 return 0;
808 }
809 otg->gadget = gadget;
19c1eac2
AT		 810 dev_dbg(otg->usb_phy->dev,
811 "peripheral driver registered w/ tranceiver\n");
e0c201f3
PK		 812
813 /*
814 * Kick the state machine work, if host is not supported
815 * or host is already registered with us.
816 */
971232cf 817 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL || otg->host) {
19c1eac2 818 pm_runtime_get_sync(otg->usb_phy->dev);
e0c201f3 819 schedule_work(&motg->sm_work);
87c0104a 820 }
e0c201f3
PK		 821
822 return 0;
823}
824
d860852e
PK		 825static bool msm_chg_check_secondary_det(struct msm_otg *motg)
826{
1d4c9293 827 struct usb_phy *phy = &motg->phy;
d860852e
PK		 828 u32 chg_det;
829 bool ret = false;
830
831 switch (motg->pdata->phy_type) {
832 case CI_45NM_INTEGRATED_PHY:
1d4c9293 833 chg_det = ulpi_read(phy, 0x34);
d860852e
PK		 834 ret = chg_det & (1 << 4);
835 break;
836 case SNPS_28NM_INTEGRATED_PHY:
1d4c9293 837 chg_det = ulpi_read(phy, 0x87);
d860852e
PK		 838 ret = chg_det & 1;
839 break;
840 default:
841 break;
842 }
843 return ret;
844}
845
846static void msm_chg_enable_secondary_det(struct msm_otg *motg)
847{
1d4c9293 848 struct usb_phy *phy = &motg->phy;
d860852e
PK		 849 u32 chg_det;
850
851 switch (motg->pdata->phy_type) {
852 case CI_45NM_INTEGRATED_PHY:
1d4c9293 853 chg_det = ulpi_read(phy, 0x34);
d860852e
PK		 854 /* Turn off charger block */
855 chg_det |= ~(1 << 1);
1d4c9293 856 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 857 udelay(20);
858 /* control chg block via ULPI */
859 chg_det &= ~(1 << 3);
1d4c9293 860 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 861 /* put it in host mode for enabling D- source */
862 chg_det &= ~(1 << 2);
1d4c9293 863 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 864 /* Turn on chg detect block */
865 chg_det &= ~(1 << 1);
1d4c9293 866 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 867 udelay(20);
868 /* enable chg detection */
869 chg_det &= ~(1 << 0);
1d4c9293 870 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 871 break;
872 case SNPS_28NM_INTEGRATED_PHY:
873 /*
874 * Configure DM as current source, DP as current sink
875 * and enable battery charging comparators.
876 */
1d4c9293
HK		 877 ulpi_write(phy, 0x8, 0x85);
878 ulpi_write(phy, 0x2, 0x85);
879 ulpi_write(phy, 0x1, 0x85);
d860852e
PK		 880 break;
881 default:
882 break;
883 }
884}
885
886static bool msm_chg_check_primary_det(struct msm_otg *motg)
887{
1d4c9293 888 struct usb_phy *phy = &motg->phy;
d860852e
PK		 889 u32 chg_det;
890 bool ret = false;
891
892 switch (motg->pdata->phy_type) {
893 case CI_45NM_INTEGRATED_PHY:
1d4c9293 894 chg_det = ulpi_read(phy, 0x34);
d860852e
PK		 895 ret = chg_det & (1 << 4);
896 break;
897 case SNPS_28NM_INTEGRATED_PHY:
1d4c9293 898 chg_det = ulpi_read(phy, 0x87);
d860852e
PK		 899 ret = chg_det & 1;
900 break;
901 default:
902 break;
903 }
904 return ret;
905}
906
907static void msm_chg_enable_primary_det(struct msm_otg *motg)
908{
1d4c9293 909 struct usb_phy *phy = &motg->phy;
d860852e
PK		 910 u32 chg_det;
911
912 switch (motg->pdata->phy_type) {
913 case CI_45NM_INTEGRATED_PHY:
1d4c9293 914 chg_det = ulpi_read(phy, 0x34);
d860852e
PK		 915 /* enable chg detection */
916 chg_det &= ~(1 << 0);
1d4c9293 917 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 918 break;
919 case SNPS_28NM_INTEGRATED_PHY:
920 /*
921 * Configure DP as current source, DM as current sink
922 * and enable battery charging comparators.
923 */
1d4c9293
HK		 924 ulpi_write(phy, 0x2, 0x85);
925 ulpi_write(phy, 0x1, 0x85);
d860852e
PK		 926 break;
927 default:
928 break;
929 }
930}
931
932static bool msm_chg_check_dcd(struct msm_otg *motg)
933{
1d4c9293 934 struct usb_phy *phy = &motg->phy;
d860852e
PK		 935 u32 line_state;
936 bool ret = false;
937
938 switch (motg->pdata->phy_type) {
939 case CI_45NM_INTEGRATED_PHY:
1d4c9293 940 line_state = ulpi_read(phy, 0x15);
d860852e
PK		 941 ret = !(line_state & 1);
942 break;
943 case SNPS_28NM_INTEGRATED_PHY:
1d4c9293 944 line_state = ulpi_read(phy, 0x87);
d860852e
PK		 945 ret = line_state & 2;
946 break;
947 default:
948 break;
949 }
950 return ret;
951}
952
953static void msm_chg_disable_dcd(struct msm_otg *motg)
954{
1d4c9293 955 struct usb_phy *phy = &motg->phy;
d860852e
PK		 956 u32 chg_det;
957
958 switch (motg->pdata->phy_type) {
959 case CI_45NM_INTEGRATED_PHY:
1d4c9293 960 chg_det = ulpi_read(phy, 0x34);
d860852e 961 chg_det &= ~(1 << 5);
1d4c9293 962 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 963 break;
964 case SNPS_28NM_INTEGRATED_PHY:
1d4c9293 965 ulpi_write(phy, 0x10, 0x86);
d860852e
PK		 966 break;
967 default:
968 break;
969 }
970}
971
972static void msm_chg_enable_dcd(struct msm_otg *motg)
973{
1d4c9293 974 struct usb_phy *phy = &motg->phy;
d860852e
PK		 975 u32 chg_det;
976
977 switch (motg->pdata->phy_type) {
978 case CI_45NM_INTEGRATED_PHY:
1d4c9293 979 chg_det = ulpi_read(phy, 0x34);
d860852e
PK		 980 /* Turn on D+ current source */
981 chg_det |= (1 << 5);
1d4c9293 982 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 983 break;
984 case SNPS_28NM_INTEGRATED_PHY:
985 /* Data contact detection enable */
1d4c9293 986 ulpi_write(phy, 0x10, 0x85);
d860852e
PK		 987 break;
988 default:
989 break;
990 }
991}
992
993static void msm_chg_block_on(struct msm_otg *motg)
994{
1d4c9293 995 struct usb_phy *phy = &motg->phy;
d860852e
PK		 996 u32 func_ctrl, chg_det;
997
998 /* put the controller in non-driving mode */
1d4c9293 999 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
d860852e
PK		 1000 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1001 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1d4c9293 1002 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
d860852e
PK		 1003
1004 switch (motg->pdata->phy_type) {
1005 case CI_45NM_INTEGRATED_PHY:
1d4c9293 1006 chg_det = ulpi_read(phy, 0x34);
d860852e
PK		 1007 /* control chg block via ULPI */
1008 chg_det &= ~(1 << 3);
1d4c9293 1009 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 1010 /* Turn on chg detect block */
1011 chg_det &= ~(1 << 1);
1d4c9293 1012 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 1013 udelay(20);
1014 break;
1015 case SNPS_28NM_INTEGRATED_PHY:
1016 /* Clear charger detecting control bits */
1d4c9293 1017 ulpi_write(phy, 0x3F, 0x86);
d860852e 1018 /* Clear alt interrupt latch and enable bits */
1d4c9293
HK		 1019 ulpi_write(phy, 0x1F, 0x92);
1020 ulpi_write(phy, 0x1F, 0x95);
d860852e
PK		 1021 udelay(100);
1022 break;
1023 default:
1024 break;
1025 }
1026}
1027
1028static void msm_chg_block_off(struct msm_otg *motg)
1029{
1d4c9293 1030 struct usb_phy *phy = &motg->phy;
d860852e
PK		 1031 u32 func_ctrl, chg_det;
1032
1033 switch (motg->pdata->phy_type) {
1034 case CI_45NM_INTEGRATED_PHY:
1d4c9293 1035 chg_det = ulpi_read(phy, 0x34);
d860852e
PK		 1036 /* Turn off charger block */
1037 chg_det |= ~(1 << 1);
1d4c9293 1038 ulpi_write(phy, chg_det, 0x34);
d860852e
PK		 1039 break;
1040 case SNPS_28NM_INTEGRATED_PHY:
1041 /* Clear charger detecting control bits */
1d4c9293 1042 ulpi_write(phy, 0x3F, 0x86);
d860852e 1043 /* Clear alt interrupt latch and enable bits */
1d4c9293
HK		 1044 ulpi_write(phy, 0x1F, 0x92);
1045 ulpi_write(phy, 0x1F, 0x95);
d860852e
PK		 1046 break;
1047 default:
1048 break;
1049 }
1050
1051 /* put the controller in normal mode */
1d4c9293 1052 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
d860852e
PK		 1053 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1054 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1d4c9293 1055 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
d860852e
PK		 1056}
1057
1058#define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1059#define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1060#define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1061#define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1062static void msm_chg_detect_work(struct work_struct *w)
1063{
1064 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1d4c9293 1065 struct usb_phy *phy = &motg->phy;
d860852e
PK		 1066 bool is_dcd, tmout, vout;
1067 unsigned long delay;
1068
1d4c9293 1069 dev_dbg(phy->dev, "chg detection work\n");
d860852e
PK		 1070 switch (motg->chg_state) {
1071 case USB_CHG_STATE_UNDEFINED:
1d4c9293 1072 pm_runtime_get_sync(phy->dev);
d860852e
PK		 1073 msm_chg_block_on(motg);
1074 msm_chg_enable_dcd(motg);
1075 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1076 motg->dcd_retries = 0;
1077 delay = MSM_CHG_DCD_POLL_TIME;
1078 break;
1079 case USB_CHG_STATE_WAIT_FOR_DCD:
1080 is_dcd = msm_chg_check_dcd(motg);
1081 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1082 if (is_dcd || tmout) {
1083 msm_chg_disable_dcd(motg);
1084 msm_chg_enable_primary_det(motg);
1085 delay = MSM_CHG_PRIMARY_DET_TIME;
1086 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1087 } else {
1088 delay = MSM_CHG_DCD_POLL_TIME;
1089 }
1090 break;
1091 case USB_CHG_STATE_DCD_DONE:
1092 vout = msm_chg_check_primary_det(motg);
1093 if (vout) {
1094 msm_chg_enable_secondary_det(motg);
1095 delay = MSM_CHG_SECONDARY_DET_TIME;
1096 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1097 } else {
1098 motg->chg_type = USB_SDP_CHARGER;
1099 motg->chg_state = USB_CHG_STATE_DETECTED;
1100 delay = 0;
1101 }
1102 break;
1103 case USB_CHG_STATE_PRIMARY_DONE:
1104 vout = msm_chg_check_secondary_det(motg);
1105 if (vout)
1106 motg->chg_type = USB_DCP_CHARGER;
1107 else
1108 motg->chg_type = USB_CDP_CHARGER;
1109 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1110 /* fall through */
1111 case USB_CHG_STATE_SECONDARY_DONE:
1112 motg->chg_state = USB_CHG_STATE_DETECTED;
1113 case USB_CHG_STATE_DETECTED:
1114 msm_chg_block_off(motg);
1d4c9293 1115 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
d860852e
PK		 1116 schedule_work(&motg->sm_work);
1117 return;
1118 default:
1119 return;
1120 }
1121
1122 schedule_delayed_work(&motg->chg_work, delay);
1123}
1124
e0c201f3
PK		 1125/*
1126 * We support OTG, Peripheral only and Host only configurations. In case
1127 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1128 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1129 * enabled when switch is controlled by user and default mode is supplied
1130 * by board file, which can be changed by userspace later.
1131 */
1132static void msm_otg_init_sm(struct msm_otg *motg)
1133{
1134 struct msm_otg_platform_data *pdata = motg->pdata;
1135 u32 otgsc = readl(USB_OTGSC);
1136
1137 switch (pdata->mode) {
971232cf 1138 case USB_DR_MODE_OTG:
e0c201f3
PK		 1139 if (pdata->otg_control == OTG_PHY_CONTROL) {
1140 if (otgsc & OTGSC_ID)
1141 set_bit(ID, &motg->inputs);
1142 else
1143 clear_bit(ID, &motg->inputs);
1144
1145 if (otgsc & OTGSC_BSV)
1146 set_bit(B_SESS_VLD, &motg->inputs);
1147 else
1148 clear_bit(B_SESS_VLD, &motg->inputs);
1149 } else if (pdata->otg_control == OTG_USER_CONTROL) {
e0c201f3
PK		 1150 set_bit(ID, &motg->inputs);
1151 clear_bit(B_SESS_VLD, &motg->inputs);
e0c201f3
PK		 1152 }
1153 break;
971232cf 1154 case USB_DR_MODE_HOST:
e0c201f3
PK		 1155 clear_bit(ID, &motg->inputs);
1156 break;
971232cf 1157 case USB_DR_MODE_PERIPHERAL:
e0c201f3
PK		 1158 set_bit(ID, &motg->inputs);
1159 if (otgsc & OTGSC_BSV)
1160 set_bit(B_SESS_VLD, &motg->inputs);
1161 else
1162 clear_bit(B_SESS_VLD, &motg->inputs);
1163 break;
1164 default:
1165 break;
1166 }
1167}
1168
1169static void msm_otg_sm_work(struct work_struct *w)
1170{
1171 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1d4c9293 1172 struct usb_otg *otg = motg->phy.otg;
e0c201f3 1173
e47d9254 1174 switch (otg->state) {
e0c201f3 1175 case OTG_STATE_UNDEFINED:
19c1eac2
AT		 1176 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1177 msm_otg_reset(otg->usb_phy);
e0c201f3 1178 msm_otg_init_sm(motg);
e47d9254 1179 otg->state = OTG_STATE_B_IDLE;
e0c201f3
PK		 1180 /* FALL THROUGH */
1181 case OTG_STATE_B_IDLE:
19c1eac2 1182 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
e0c201f3
PK		 1183 if (!test_bit(ID, &motg->inputs) && otg->host) {
1184 /* disable BSV bit */
1185 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
19c1eac2 1186 msm_otg_start_host(otg->usb_phy, 1);
e47d9254 1187 otg->state = OTG_STATE_A_HOST;
d860852e
PK		 1188 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1189 switch (motg->chg_state) {
1190 case USB_CHG_STATE_UNDEFINED:
1191 msm_chg_detect_work(&motg->chg_work.work);
1192 break;
1193 case USB_CHG_STATE_DETECTED:
1194 switch (motg->chg_type) {
1195 case USB_DCP_CHARGER:
1196 msm_otg_notify_charger(motg,
1197 IDEV_CHG_MAX);
1198 break;
1199 case USB_CDP_CHARGER:
1200 msm_otg_notify_charger(motg,
1201 IDEV_CHG_MAX);
19c1eac2
AT		 1202 msm_otg_start_peripheral(otg->usb_phy,
1203 1);
e47d9254 1204 otg->state
1d4c9293 1205 = OTG_STATE_B_PERIPHERAL;
d860852e
PK		 1206 break;
1207 case USB_SDP_CHARGER:
1208 msm_otg_notify_charger(motg, IUNIT);
19c1eac2
AT		 1209 msm_otg_start_peripheral(otg->usb_phy,
1210 1);
e47d9254 1211 otg->state
1d4c9293 1212 = OTG_STATE_B_PERIPHERAL;
d860852e
PK		 1213 break;
1214 default:
1215 break;
1216 }
1217 break;
1218 default:
1219 break;
1220 }
1221 } else {
1222 /*
1223 * If charger detection work is pending, decrement
1224 * the pm usage counter to balance with the one that
1225 * is incremented in charger detection work.
1226 */
1227 if (cancel_delayed_work_sync(&motg->chg_work)) {
19c1eac2
AT		 1228 pm_runtime_put_sync(otg->usb_phy->dev);
1229 msm_otg_reset(otg->usb_phy);
d860852e
PK		 1230 }
1231 msm_otg_notify_charger(motg, 0);
1232 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1233 motg->chg_type = USB_INVALID_CHARGER;
e0c201f3 1234 }
508ccea1 1235
e47d9254 1236 if (otg->state == OTG_STATE_B_IDLE)
19c1eac2 1237 pm_runtime_put_sync(otg->usb_phy->dev);
e0c201f3
PK		 1238 break;
1239 case OTG_STATE_B_PERIPHERAL:
19c1eac2 1240 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
e0c201f3
PK		 1241 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1242 !test_bit(ID, &motg->inputs)) {
d860852e 1243 msm_otg_notify_charger(motg, 0);
19c1eac2 1244 msm_otg_start_peripheral(otg->usb_phy, 0);
d860852e
PK		 1245 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1246 motg->chg_type = USB_INVALID_CHARGER;
e47d9254 1247 otg->state = OTG_STATE_B_IDLE;
19c1eac2 1248 msm_otg_reset(otg->usb_phy);
e0c201f3
PK		 1249 schedule_work(w);
1250 }
1251 break;
1252 case OTG_STATE_A_HOST:
19c1eac2 1253 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
e0c201f3 1254 if (test_bit(ID, &motg->inputs)) {
19c1eac2 1255 msm_otg_start_host(otg->usb_phy, 0);
e47d9254 1256 otg->state = OTG_STATE_B_IDLE;
19c1eac2 1257 msm_otg_reset(otg->usb_phy);
e0c201f3
PK		 1258 schedule_work(w);
1259 }
1260 break;
1261 default:
1262 break;
1263 }
1264}
1265
1266static irqreturn_t msm_otg_irq(int irq, void *data)
1267{
1268 struct msm_otg *motg = data;
1d4c9293 1269 struct usb_phy *phy = &motg->phy;
e0c201f3
PK		 1270 u32 otgsc = 0;
1271
87c0104a
PK		 1272 if (atomic_read(&motg->in_lpm)) {
1273 disable_irq_nosync(irq);
1274 motg->async_int = 1;
1d4c9293 1275 pm_runtime_get(phy->dev);
87c0104a
PK		 1276 return IRQ_HANDLED;
1277 }
1278
e0c201f3
PK		 1279 otgsc = readl(USB_OTGSC);
1280 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1281 return IRQ_NONE;
1282
1283 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1284 if (otgsc & OTGSC_ID)
1285 set_bit(ID, &motg->inputs);
1286 else
1287 clear_bit(ID, &motg->inputs);
1d4c9293
HK		 1288 dev_dbg(phy->dev, "ID set/clear\n");
1289 pm_runtime_get_noresume(phy->dev);
e0c201f3
PK		 1290 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1291 if (otgsc & OTGSC_BSV)
1292 set_bit(B_SESS_VLD, &motg->inputs);
1293 else
1294 clear_bit(B_SESS_VLD, &motg->inputs);
1d4c9293
HK		 1295 dev_dbg(phy->dev, "BSV set/clear\n");
1296 pm_runtime_get_noresume(phy->dev);
e0c201f3
PK		 1297 }
1298
1299 writel(otgsc, USB_OTGSC);
1300 schedule_work(&motg->sm_work);
1301 return IRQ_HANDLED;
1302}
1303
1304static int msm_otg_mode_show(struct seq_file *s, void *unused)
1305{
1306 struct msm_otg *motg = s->private;
1d4c9293 1307 struct usb_otg *otg = motg->phy.otg;
e0c201f3 1308
e47d9254 1309 switch (otg->state) {
e0c201f3 1310 case OTG_STATE_A_HOST:
3aca0fa9 1311 seq_puts(s, "host\n");
e0c201f3
PK		 1312 break;
1313 case OTG_STATE_B_PERIPHERAL:
3aca0fa9 1314 seq_puts(s, "peripheral\n");
e0c201f3
PK		 1315 break;
1316 default:
3aca0fa9 1317 seq_puts(s, "none\n");
e0c201f3
PK		 1318 break;
1319 }
1320
1321 return 0;
1322}
1323
1324static int msm_otg_mode_open(struct inode *inode, struct file *file)
1325{
1326 return single_open(file, msm_otg_mode_show, inode->i_private);
1327}
1328
1329static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1330 size_t count, loff_t *ppos)
1331{
e2904ee4
PK		 1332 struct seq_file *s = file->private_data;
1333 struct msm_otg *motg = s->private;
e0c201f3 1334 char buf[16];
1d4c9293 1335 struct usb_otg *otg = motg->phy.otg;
e0c201f3 1336 int status = count;
971232cf 1337 enum usb_dr_mode req_mode;
e0c201f3
PK		 1338
1339 memset(buf, 0x00, sizeof(buf));
1340
1341 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1342 status = -EFAULT;
1343 goto out;
1344 }
1345
1346 if (!strncmp(buf, "host", 4)) {
971232cf 1347 req_mode = USB_DR_MODE_HOST;
e0c201f3 1348 } else if (!strncmp(buf, "peripheral", 10)) {
971232cf 1349 req_mode = USB_DR_MODE_PERIPHERAL;
e0c201f3 1350 } else if (!strncmp(buf, "none", 4)) {
971232cf 1351 req_mode = USB_DR_MODE_UNKNOWN;
e0c201f3
PK		 1352 } else {
1353 status = -EINVAL;
1354 goto out;
1355 }
1356
1357 switch (req_mode) {
971232cf 1358 case USB_DR_MODE_UNKNOWN:
e47d9254 1359 switch (otg->state) {
e0c201f3
PK		 1360 case OTG_STATE_A_HOST:
1361 case OTG_STATE_B_PERIPHERAL:
1362 set_bit(ID, &motg->inputs);
1363 clear_bit(B_SESS_VLD, &motg->inputs);
1364 break;
1365 default:
1366 goto out;
1367 }
1368 break;
971232cf 1369 case USB_DR_MODE_PERIPHERAL:
e47d9254 1370 switch (otg->state) {
e0c201f3
PK		 1371 case OTG_STATE_B_IDLE:
1372 case OTG_STATE_A_HOST:
1373 set_bit(ID, &motg->inputs);
1374 set_bit(B_SESS_VLD, &motg->inputs);
1375 break;
1376 default:
1377 goto out;
1378 }
1379 break;
971232cf 1380 case USB_DR_MODE_HOST:
e47d9254 1381 switch (otg->state) {
e0c201f3
PK		 1382 case OTG_STATE_B_IDLE:
1383 case OTG_STATE_B_PERIPHERAL:
1384 clear_bit(ID, &motg->inputs);
1385 break;
1386 default:
1387 goto out;
1388 }
1389 break;
1390 default:
1391 goto out;
1392 }
1393
19c1eac2 1394 pm_runtime_get_sync(otg->usb_phy->dev);
e0c201f3
PK		 1395 schedule_work(&motg->sm_work);
1396out:
1397 return status;
1398}
1399
8f90afd9 1400static const struct file_operations msm_otg_mode_fops = {
e0c201f3
PK		 1401 .open = msm_otg_mode_open,
1402 .read = seq_read,
1403 .write = msm_otg_mode_write,
1404 .llseek = seq_lseek,
1405 .release = single_release,
1406};
1407
1408static struct dentry *msm_otg_dbg_root;
1409static struct dentry *msm_otg_dbg_mode;
1410
1411static int msm_otg_debugfs_init(struct msm_otg *motg)
1412{
1413 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1414
1415 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1416 return -ENODEV;
1417
1418 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1419 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1420 if (!msm_otg_dbg_mode) {
1421 debugfs_remove(msm_otg_dbg_root);
1422 msm_otg_dbg_root = NULL;
1423 return -ENODEV;
1424 }
1425
1426 return 0;
1427}
1428
1429static void msm_otg_debugfs_cleanup(void)
1430{
1431 debugfs_remove(msm_otg_dbg_mode);
1432 debugfs_remove(msm_otg_dbg_root);
1433}
1434
492240b0 1435static const struct of_device_id msm_otg_dt_match[] = {
8364f9af
II		 1436 {
1437 .compatible = "qcom,usb-otg-ci",
1438 .data = (void *) CI_45NM_INTEGRATED_PHY
1439 },
1440 {
1441 .compatible = "qcom,usb-otg-snps",
1442 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1443 },
1444 { }
1445};
1446MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1447
1448static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1449{
1450 struct msm_otg_platform_data *pdata;
1451 const struct of_device_id *id;
1452 struct device_node *node = pdev->dev.of_node;
1453 struct property *prop;
1454 int len, ret, words;
01799b62 1455 u32 val, tmp[3];
8364f9af
II		 1456
1457 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1458 if (!pdata)
1459 return -ENOMEM;
1460
1461 motg->pdata = pdata;
1462
1463 id = of_match_device(msm_otg_dt_match, &pdev->dev);
b3025e6a 1464 pdata->phy_type = (enum msm_usb_phy_type) id->data;
8364f9af 1465
a2734543
II		 1466 motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1467 if (IS_ERR(motg->link_rst))
1468 return PTR_ERR(motg->link_rst);
1469
1470 motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1471 if (IS_ERR(motg->phy_rst))
e44f1f4c 1472 motg->phy_rst = NULL;
a2734543 1473
8364f9af
II		 1474 pdata->mode = of_usb_get_dr_mode(node);
1475 if (pdata->mode == USB_DR_MODE_UNKNOWN)
1476 pdata->mode = USB_DR_MODE_OTG;
1477
1478 pdata->otg_control = OTG_PHY_CONTROL;
1479 if (!of_property_read_u32(node, "qcom,otg-control", &val))
1480 if (val == OTG_PMIC_CONTROL)
1481 pdata->otg_control = val;
1482
cfa3ff5d
II		 1483 if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1484 motg->phy_number = val;
1485
01799b62
II		 1486 motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1487 motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1488 motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1489
1490 if (of_get_property(node, "qcom,vdd-levels", &len) &&
1491 len == sizeof(tmp)) {
1492 of_property_read_u32_array(node, "qcom,vdd-levels",
1493 tmp, len / sizeof(*tmp));
1494 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1495 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1496 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1497 }
1498
8364f9af
II		 1499 prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1500 if (!prop || !len)
1501 return 0;
1502
1503 words = len / sizeof(u32);
1504
1505 if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1506 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1507 return 0;
1508 }
1509
1510 pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
9da22206 1511 if (!pdata->phy_init_seq)
8364f9af 1512 return 0;
8364f9af
II		 1513
1514 ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1515 pdata->phy_init_seq, words);
1516 if (!ret)
1517 pdata->phy_init_sz = words;
1518
1519 return 0;
1520}
1521
06a6ec44 1522static int msm_otg_probe(struct platform_device *pdev)
e0c201f3 1523{
6b99c68e 1524 struct regulator_bulk_data regs[3];
e0c201f3 1525 int ret = 0;
8364f9af
II		 1526 struct device_node *np = pdev->dev.of_node;
1527 struct msm_otg_platform_data *pdata;
e0c201f3
PK		 1528 struct resource *res;
1529 struct msm_otg *motg;
1d4c9293 1530 struct usb_phy *phy;
30bf8667 1531 void __iomem *phy_select;
e0c201f3 1532
6b99c68e 1533 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
9da22206 1534 if (!motg)
e0c201f3 1535 return -ENOMEM;
e0c201f3 1536
8364f9af
II		 1537 pdata = dev_get_platdata(&pdev->dev);
1538 if (!pdata) {
1539 if (!np)
1540 return -ENXIO;
1541 ret = msm_otg_read_dt(pdev, motg);
1542 if (ret)
1543 return ret;
1544 }
1545
6b99c68e
II		 1546 motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1547 GFP_KERNEL);
9da22206 1548 if (!motg->phy.otg)
6b99c68e 1549 return -ENOMEM;
1d4c9293 1550
1d4c9293
HK		 1551 phy = &motg->phy;
1552 phy->dev = &pdev->dev;
e0c201f3 1553
a1a4caf4
SK		 1554 if (motg->pdata->phy_clk_reset) {
1555 motg->phy_reset_clk = devm_clk_get(&pdev->dev,
8364f9af 1556 np ? "phy" : "usb_phy_clk");
a1a4caf4
SK		 1557
1558 if (IS_ERR(motg->phy_reset_clk)) {
1559 dev_err(&pdev->dev, "failed to get usb_phy_clk\n");
1560 return PTR_ERR(motg->phy_reset_clk);
1561 }
e0c201f3
PK		 1562 }
1563
8364f9af 1564 motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
e0c201f3
PK		 1565 if (IS_ERR(motg->clk)) {
1566 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
6b99c68e 1567 return PTR_ERR(motg->clk);
e0c201f3 1568 }
0f73cac8
A		 1569
1570 /*
1571 * If USB Core is running its protocol engine based on CORE CLK,
1572 * CORE CLK must be running at >55Mhz for correct HSUSB
1573 * operation and USB core cannot tolerate frequency changes on
ff0e4a68 1574 * CORE CLK.
0f73cac8 1575 */
8364f9af 1576 motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
e0c201f3
PK		 1577 if (IS_ERR(motg->pclk)) {
1578 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
6b99c68e 1579 return PTR_ERR(motg->pclk);
e0c201f3
PK		 1580 }
1581
1582 /*
1583 * USB core clock is not present on all MSM chips. This
1584 * clock is introduced to remove the dependency on AXI
1585 * bus frequency.
1586 */
8364f9af
II		 1587 motg->core_clk = devm_clk_get(&pdev->dev,
1588 np ? "alt_core" : "usb_hs_core_clk");
e0c201f3
PK		 1589
1590 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2ea7b148
DC		 1591 if (!res)
1592 return -EINVAL;
1593 motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1594 if (!motg->regs)
1595 return -ENOMEM;
e0c201f3 1596
30bf8667
TB		 1597 /*
1598 * NOTE: The PHYs can be multiplexed between the chipidea controller
1599 * and the dwc3 controller, using a single bit. It is important that
1600 * the dwc3 driver does not set this bit in an incompatible way.
1601 */
1602 if (motg->phy_number) {
1603 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
716d28e2
WY		 1604 if (!phy_select)
1605 return -ENOMEM;
30bf8667 1606 /* Enable second PHY with the OTG port */
24597490 1607 writel(0x1, phy_select);
30bf8667
TB		 1608 }
1609
e0c201f3
PK		 1610 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1611
1612 motg->irq = platform_get_irq(pdev, 0);
f60c114a 1613 if (motg->irq < 0) {
e0c201f3 1614 dev_err(&pdev->dev, "platform_get_irq failed\n");
6b99c68e
II		 1615 return motg->irq;
1616 }
1617
f5ef2372
II		 1618 regs[0].supply = "vddcx";
1619 regs[1].supply = "v3p3";
1620 regs[2].supply = "v1p8";
6b99c68e
II		 1621
1622 ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1623 if (ret)
1624 return ret;
1625
1626 motg->vddcx = regs[0].consumer;
1627 motg->v3p3 = regs[1].consumer;
1628 motg->v1p8 = regs[2].consumer;
1629
1630 clk_set_rate(motg->clk, 60000000);
e0c201f3 1631
b99a8f62
SB		 1632 clk_prepare_enable(motg->clk);
1633 clk_prepare_enable(motg->pclk);
11aa5c47 1634
6b99c68e
II		 1635 if (!IS_ERR(motg->core_clk))
1636 clk_prepare_enable(motg->core_clk);
1637
11aa5c47
A		 1638 ret = msm_hsusb_init_vddcx(motg, 1);
1639 if (ret) {
1640 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
6b99c68e 1641 goto disable_clks;
11aa5c47
A		 1642 }
1643
1644 ret = msm_hsusb_ldo_init(motg, 1);
1645 if (ret) {
1646 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
6b99c68e 1647 goto disable_vddcx;
11aa5c47 1648 }
37cfdaf7 1649 ret = msm_hsusb_ldo_set_mode(motg, 1);
11aa5c47
A		 1650 if (ret) {
1651 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
6b99c68e 1652 goto disable_ldo;
11aa5c47
A		 1653 }
1654
e0c201f3
PK		 1655 writel(0, USB_USBINTR);
1656 writel(0, USB_OTGSC);
1657
1658 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
d860852e 1659 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
6b99c68e 1660 ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
e0c201f3
PK		 1661 "msm_otg", motg);
1662 if (ret) {
1663 dev_err(&pdev->dev, "request irq failed\n");
6b99c68e 1664 goto disable_ldo;
e0c201f3
PK		 1665 }
1666
d69c6f5d 1667 phy->init = msm_phy_init;
1d4c9293 1668 phy->set_power = msm_otg_set_power;
349907c2 1669 phy->notify_disconnect = msm_phy_notify_disconnect;
e695abb3 1670 phy->type = USB_PHY_TYPE_USB2;
1d4c9293
HK		 1671
1672 phy->io_ops = &msm_otg_io_ops;
e0c201f3 1673
19c1eac2 1674 phy->otg->usb_phy = &motg->phy;
1d4c9293
HK		 1675 phy->otg->set_host = msm_otg_set_host;
1676 phy->otg->set_peripheral = msm_otg_set_peripheral;
e0c201f3 1677
d69c6f5d
II		 1678 msm_usb_reset(phy);
1679
e695abb3 1680 ret = usb_add_phy_dev(&motg->phy);
e0c201f3 1681 if (ret) {
721002ec 1682 dev_err(&pdev->dev, "usb_add_phy failed\n");
6b99c68e 1683 goto disable_ldo;
e0c201f3
PK		 1684 }
1685
1686 platform_set_drvdata(pdev, motg);
1687 device_init_wakeup(&pdev->dev, 1);
1688
971232cf 1689 if (motg->pdata->mode == USB_DR_MODE_OTG &&
8364f9af 1690 motg->pdata->otg_control == OTG_USER_CONTROL) {
e0c201f3
PK		 1691 ret = msm_otg_debugfs_init(motg);
1692 if (ret)
3aca0fa9 1693 dev_dbg(&pdev->dev, "Can not create mode change file\n");
e0c201f3
PK		 1694 }
1695
87c0104a
PK		 1696 pm_runtime_set_active(&pdev->dev);
1697 pm_runtime_enable(&pdev->dev);
e0c201f3 1698
87c0104a 1699 return 0;
6b99c68e
II		 1700
1701disable_ldo:
1702 msm_hsusb_ldo_init(motg, 0);
1703disable_vddcx:
1704 msm_hsusb_init_vddcx(motg, 0);
e0c201f3 1705disable_clks:
b99a8f62
SB		 1706 clk_disable_unprepare(motg->pclk);
1707 clk_disable_unprepare(motg->clk);
6b99c68e
II		 1708 if (!IS_ERR(motg->core_clk))
1709 clk_disable_unprepare(motg->core_clk);
e0c201f3
PK		 1710 return ret;
1711}
1712
fb4e98ab 1713static int msm_otg_remove(struct platform_device *pdev)
e0c201f3
PK		 1714{
1715 struct msm_otg *motg = platform_get_drvdata(pdev);
1d4c9293 1716 struct usb_phy *phy = &motg->phy;
87c0104a 1717 int cnt = 0;
e0c201f3 1718
1d4c9293 1719 if (phy->otg->host || phy->otg->gadget)
e0c201f3
PK		 1720 return -EBUSY;
1721
1722 msm_otg_debugfs_cleanup();
d860852e 1723 cancel_delayed_work_sync(&motg->chg_work);
e0c201f3 1724 cancel_work_sync(&motg->sm_work);
87c0104a 1725
7018773a 1726 pm_runtime_resume(&pdev->dev);
87c0104a 1727
e0c201f3 1728 device_init_wakeup(&pdev->dev, 0);
87c0104a 1729 pm_runtime_disable(&pdev->dev);
e0c201f3 1730
662dca54 1731 usb_remove_phy(phy);
6b99c68e 1732 disable_irq(motg->irq);
e0c201f3 1733
87c0104a
PK		 1734 /*
1735 * Put PHY in low power mode.
1736 */
1d4c9293
HK		 1737 ulpi_read(phy, 0x14);
1738 ulpi_write(phy, 0x08, 0x09);
87c0104a
PK		 1739
1740 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1741 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1742 if (readl(USB_PORTSC) & PORTSC_PHCD)
1743 break;
1744 udelay(1);
1745 cnt++;
1746 }
1747 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1d4c9293 1748 dev_err(phy->dev, "Unable to suspend PHY\n");
87c0104a 1749
b99a8f62
SB		 1750 clk_disable_unprepare(motg->pclk);
1751 clk_disable_unprepare(motg->clk);
6b99c68e 1752 if (!IS_ERR(motg->core_clk))
b99a8f62 1753 clk_disable_unprepare(motg->core_clk);
11aa5c47 1754 msm_hsusb_ldo_init(motg, 0);
e0c201f3 1755
87c0104a 1756 pm_runtime_set_suspended(&pdev->dev);
e0c201f3 1757
e0c201f3
PK		 1758 return 0;
1759}
1760
87c0104a
PK		 1761#ifdef CONFIG_PM_RUNTIME
1762static int msm_otg_runtime_idle(struct device *dev)
1763{
1764 struct msm_otg *motg = dev_get_drvdata(dev);
1d4c9293 1765 struct usb_otg *otg = motg->phy.otg;
87c0104a
PK		 1766
1767 dev_dbg(dev, "OTG runtime idle\n");
1768
1769 /*
1770 * It is observed some times that a spurious interrupt
1771 * comes when PHY is put into LPM immediately after PHY reset.
1772 * This 1 sec delay also prevents entering into LPM immediately
1773 * after asynchronous interrupt.
1774 */
e47d9254 1775 if (otg->state != OTG_STATE_UNDEFINED)
87c0104a
PK		 1776 pm_schedule_suspend(dev, 1000);
1777
1778 return -EAGAIN;
1779}
1780
1781static int msm_otg_runtime_suspend(struct device *dev)
1782{
1783 struct msm_otg *motg = dev_get_drvdata(dev);
1784
1785 dev_dbg(dev, "OTG runtime suspend\n");
1786 return msm_otg_suspend(motg);
1787}
1788
1789static int msm_otg_runtime_resume(struct device *dev)
1790{
1791 struct msm_otg *motg = dev_get_drvdata(dev);
1792
1793 dev_dbg(dev, "OTG runtime resume\n");
1794 return msm_otg_resume(motg);
1795}
87c0104a
PK		 1796#endif
1797
7018773a 1798#ifdef CONFIG_PM_SLEEP
87c0104a
PK		 1799static int msm_otg_pm_suspend(struct device *dev)
1800{
1801 struct msm_otg *motg = dev_get_drvdata(dev);
1802
1803 dev_dbg(dev, "OTG PM suspend\n");
1804 return msm_otg_suspend(motg);
1805}
1806
1807static int msm_otg_pm_resume(struct device *dev)
1808{
1809 struct msm_otg *motg = dev_get_drvdata(dev);
1810 int ret;
1811
1812 dev_dbg(dev, "OTG PM resume\n");
1813
1814 ret = msm_otg_resume(motg);
1815 if (ret)
1816 return ret;
1817
1818 /*
1819 * Runtime PM Documentation recommends bringing the
1820 * device to full powered state upon resume.
1821 */
1822 pm_runtime_disable(dev);
1823 pm_runtime_set_active(dev);
1824 pm_runtime_enable(dev);
1825
1826 return 0;
1827}
87c0104a
PK		 1828#endif
1829
1830static const struct dev_pm_ops msm_otg_dev_pm_ops = {
7018773a
PK		 1831 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
1832 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
1833 msm_otg_runtime_idle)
87c0104a
PK		 1834};
1835
e0c201f3 1836static struct platform_driver msm_otg_driver = {
06a6ec44 1837 .probe = msm_otg_probe,
7690417d 1838 .remove = msm_otg_remove,
e0c201f3
PK		 1839 .driver = {
1840 .name = DRIVER_NAME,
87c0104a 1841 .pm = &msm_otg_dev_pm_ops,
8364f9af 1842 .of_match_table = msm_otg_dt_match,
e0c201f3
PK		 1843 },
1844};
1845
06a6ec44 1846module_platform_driver(msm_otg_driver);
e0c201f3
PK		 1847
1848MODULE_LICENSE("GPL v2");
1849MODULE_DESCRIPTION("MSM USB transceiver driver");
Linux kernel - Deliverables
This page took 0.338824 seconds and 5 git commands to generate.