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91525d08 | 1 | /* |
91525d08 | 2 | * Copyright (C) 2010 Google, Inc. |
2d22b42d | 3 | * Copyright (C) 2013 NVIDIA Corporation |
91525d08 BG |
4 | * |
5 | * Author: | |
6 | * Erik Gilling <konkers@google.com> | |
7 | * Benoit Goby <benoit@android.com> | |
2d22b42d | 8 | * Venu Byravarasu <vbyravarasu@nvidia.com> |
91525d08 BG |
9 | * |
10 | * This software is licensed under the terms of the GNU General Public | |
11 | * License version 2, as published by the Free Software Foundation, and | |
12 | * may be copied, distributed, and modified under those terms. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/resource.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/err.h> | |
4265cbfd | 25 | #include <linux/export.h> |
587376a1 | 26 | #include <linux/module.h> |
91525d08 BG |
27 | #include <linux/platform_device.h> |
28 | #include <linux/io.h> | |
29 | #include <linux/gpio.h> | |
3a55c6a8 | 30 | #include <linux/of.h> |
aa607ebf | 31 | #include <linux/of_gpio.h> |
91525d08 BG |
32 | #include <linux/usb/otg.h> |
33 | #include <linux/usb/ulpi.h> | |
34 | #include <asm/mach-types.h> | |
91a687d8 | 35 | #include <linux/usb/ehci_def.h> |
1ba8216f | 36 | #include <linux/usb/tegra_usb_phy.h> |
2d22b42d | 37 | #include <linux/module.h> |
91525d08 BG |
38 | |
39 | #define ULPI_VIEWPORT 0x170 | |
40 | ||
91a687d8 SW |
41 | /* PORTSC registers */ |
42 | #define TEGRA_USB_PORTSC1 0x184 | |
43 | #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) | |
44 | #define TEGRA_USB_PORTSC1_PHCD (1 << 23) | |
45 | ||
46 | /* Bits of PORTSC1, which will get cleared by writing 1 into them */ | |
47 | #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) | |
48 | ||
91525d08 BG |
49 | #define USB_SUSP_CTRL 0x400 |
50 | #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) | |
51 | #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) | |
52 | #define USB_SUSP_CLR (1 << 5) | |
53 | #define USB_PHY_CLK_VALID (1 << 7) | |
54 | #define UTMIP_RESET (1 << 11) | |
55 | #define UHSIC_RESET (1 << 11) | |
56 | #define UTMIP_PHY_ENABLE (1 << 12) | |
57 | #define ULPI_PHY_ENABLE (1 << 13) | |
58 | #define USB_SUSP_SET (1 << 14) | |
59 | #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) | |
60 | ||
61 | #define USB1_LEGACY_CTRL 0x410 | |
62 | #define USB1_NO_LEGACY_MODE (1 << 0) | |
63 | #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) | |
64 | #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) | |
65 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ | |
66 | (1 << 1) | |
67 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) | |
68 | #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) | |
69 | ||
70 | #define ULPI_TIMING_CTRL_0 0x424 | |
71 | #define ULPI_OUTPUT_PINMUX_BYP (1 << 10) | |
72 | #define ULPI_CLKOUT_PINMUX_BYP (1 << 11) | |
73 | ||
74 | #define ULPI_TIMING_CTRL_1 0x428 | |
75 | #define ULPI_DATA_TRIMMER_LOAD (1 << 0) | |
76 | #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) | |
77 | #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) | |
78 | #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) | |
79 | #define ULPI_DIR_TRIMMER_LOAD (1 << 24) | |
80 | #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) | |
81 | ||
82 | #define UTMIP_PLL_CFG1 0x804 | |
83 | #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
84 | #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
85 | ||
86 | #define UTMIP_XCVR_CFG0 0x808 | |
87 | #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) | |
88 | #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) | |
89 | #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) | |
90 | #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) | |
91 | #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) | |
92 | #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) | |
93 | #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) | |
94 | ||
95 | #define UTMIP_BIAS_CFG0 0x80c | |
96 | #define UTMIP_OTGPD (1 << 11) | |
97 | #define UTMIP_BIASPD (1 << 10) | |
98 | ||
99 | #define UTMIP_HSRX_CFG0 0x810 | |
100 | #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) | |
101 | #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) | |
102 | ||
103 | #define UTMIP_HSRX_CFG1 0x814 | |
104 | #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) | |
105 | ||
106 | #define UTMIP_TX_CFG0 0x820 | |
107 | #define UTMIP_FS_PREABMLE_J (1 << 19) | |
108 | #define UTMIP_HS_DISCON_DISABLE (1 << 8) | |
109 | ||
110 | #define UTMIP_MISC_CFG0 0x824 | |
111 | #define UTMIP_DPDM_OBSERVE (1 << 26) | |
112 | #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) | |
113 | #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) | |
114 | #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) | |
115 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) | |
116 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) | |
117 | #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) | |
118 | ||
119 | #define UTMIP_MISC_CFG1 0x828 | |
120 | #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) | |
121 | #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
122 | ||
123 | #define UTMIP_DEBOUNCE_CFG0 0x82c | |
124 | #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) | |
125 | ||
126 | #define UTMIP_BAT_CHRG_CFG0 0x830 | |
127 | #define UTMIP_PD_CHRG (1 << 0) | |
128 | ||
129 | #define UTMIP_SPARE_CFG0 0x834 | |
130 | #define FUSE_SETUP_SEL (1 << 3) | |
131 | ||
132 | #define UTMIP_XCVR_CFG1 0x838 | |
133 | #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) | |
134 | #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) | |
135 | #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) | |
136 | #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) | |
137 | ||
138 | #define UTMIP_BIAS_CFG1 0x83c | |
139 | #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) | |
140 | ||
141 | static DEFINE_SPINLOCK(utmip_pad_lock); | |
142 | static int utmip_pad_count; | |
143 | ||
144 | struct tegra_xtal_freq { | |
145 | int freq; | |
146 | u8 enable_delay; | |
147 | u8 stable_count; | |
148 | u8 active_delay; | |
149 | u8 xtal_freq_count; | |
150 | u16 debounce; | |
151 | }; | |
152 | ||
153 | static const struct tegra_xtal_freq tegra_freq_table[] = { | |
154 | { | |
155 | .freq = 12000000, | |
156 | .enable_delay = 0x02, | |
157 | .stable_count = 0x2F, | |
158 | .active_delay = 0x04, | |
159 | .xtal_freq_count = 0x76, | |
160 | .debounce = 0x7530, | |
161 | }, | |
162 | { | |
163 | .freq = 13000000, | |
164 | .enable_delay = 0x02, | |
165 | .stable_count = 0x33, | |
166 | .active_delay = 0x05, | |
167 | .xtal_freq_count = 0x7F, | |
168 | .debounce = 0x7EF4, | |
169 | }, | |
170 | { | |
171 | .freq = 19200000, | |
172 | .enable_delay = 0x03, | |
173 | .stable_count = 0x4B, | |
174 | .active_delay = 0x06, | |
175 | .xtal_freq_count = 0xBB, | |
176 | .debounce = 0xBB80, | |
177 | }, | |
178 | { | |
179 | .freq = 26000000, | |
180 | .enable_delay = 0x04, | |
181 | .stable_count = 0x66, | |
182 | .active_delay = 0x09, | |
183 | .xtal_freq_count = 0xFE, | |
184 | .debounce = 0xFDE8, | |
185 | }, | |
186 | }; | |
187 | ||
188 | static struct tegra_utmip_config utmip_default[] = { | |
189 | [0] = { | |
190 | .hssync_start_delay = 9, | |
191 | .idle_wait_delay = 17, | |
192 | .elastic_limit = 16, | |
193 | .term_range_adj = 6, | |
194 | .xcvr_setup = 9, | |
195 | .xcvr_lsfslew = 1, | |
196 | .xcvr_lsrslew = 1, | |
197 | }, | |
198 | [2] = { | |
199 | .hssync_start_delay = 9, | |
200 | .idle_wait_delay = 17, | |
201 | .elastic_limit = 16, | |
202 | .term_range_adj = 6, | |
203 | .xcvr_setup = 9, | |
204 | .xcvr_lsfslew = 2, | |
205 | .xcvr_lsrslew = 2, | |
206 | }, | |
207 | }; | |
208 | ||
91a687d8 SW |
209 | static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) |
210 | { | |
211 | void __iomem *base = phy->regs; | |
212 | unsigned long val; | |
213 | ||
214 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
215 | val &= ~TEGRA_USB_PORTSC1_PTS(3); | |
216 | val |= TEGRA_USB_PORTSC1_PTS(pts_val & 3); | |
217 | writel(val, base + TEGRA_USB_PORTSC1); | |
218 | } | |
219 | ||
220 | static void set_phcd(struct tegra_usb_phy *phy, bool enable) | |
221 | { | |
222 | void __iomem *base = phy->regs; | |
223 | unsigned long val; | |
224 | ||
225 | val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; | |
226 | if (enable) | |
227 | val |= TEGRA_USB_PORTSC1_PHCD; | |
228 | else | |
229 | val &= ~TEGRA_USB_PORTSC1_PHCD; | |
230 | writel(val, base + TEGRA_USB_PORTSC1); | |
231 | } | |
232 | ||
91525d08 BG |
233 | static int utmip_pad_open(struct tegra_usb_phy *phy) |
234 | { | |
2d22b42d | 235 | phy->pad_clk = devm_clk_get(phy->dev, "utmi-pads"); |
91525d08 BG |
236 | if (IS_ERR(phy->pad_clk)) { |
237 | pr_err("%s: can't get utmip pad clock\n", __func__); | |
238 | return PTR_ERR(phy->pad_clk); | |
239 | } | |
240 | ||
91525d08 BG |
241 | return 0; |
242 | } | |
243 | ||
91525d08 BG |
244 | static void utmip_pad_power_on(struct tegra_usb_phy *phy) |
245 | { | |
246 | unsigned long val, flags; | |
247 | void __iomem *base = phy->pad_regs; | |
248 | ||
6a5278d0 | 249 | clk_prepare_enable(phy->pad_clk); |
91525d08 BG |
250 | |
251 | spin_lock_irqsave(&utmip_pad_lock, flags); | |
252 | ||
253 | if (utmip_pad_count++ == 0) { | |
254 | val = readl(base + UTMIP_BIAS_CFG0); | |
255 | val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); | |
256 | writel(val, base + UTMIP_BIAS_CFG0); | |
257 | } | |
258 | ||
259 | spin_unlock_irqrestore(&utmip_pad_lock, flags); | |
260 | ||
6a5278d0 | 261 | clk_disable_unprepare(phy->pad_clk); |
91525d08 BG |
262 | } |
263 | ||
264 | static int utmip_pad_power_off(struct tegra_usb_phy *phy) | |
265 | { | |
266 | unsigned long val, flags; | |
267 | void __iomem *base = phy->pad_regs; | |
268 | ||
269 | if (!utmip_pad_count) { | |
270 | pr_err("%s: utmip pad already powered off\n", __func__); | |
271 | return -EINVAL; | |
272 | } | |
273 | ||
6a5278d0 | 274 | clk_prepare_enable(phy->pad_clk); |
91525d08 BG |
275 | |
276 | spin_lock_irqsave(&utmip_pad_lock, flags); | |
277 | ||
278 | if (--utmip_pad_count == 0) { | |
279 | val = readl(base + UTMIP_BIAS_CFG0); | |
280 | val |= UTMIP_OTGPD | UTMIP_BIASPD; | |
281 | writel(val, base + UTMIP_BIAS_CFG0); | |
282 | } | |
283 | ||
284 | spin_unlock_irqrestore(&utmip_pad_lock, flags); | |
285 | ||
6a5278d0 | 286 | clk_disable_unprepare(phy->pad_clk); |
91525d08 BG |
287 | |
288 | return 0; | |
289 | } | |
290 | ||
291 | static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) | |
292 | { | |
293 | unsigned long timeout = 2000; | |
294 | do { | |
295 | if ((readl(reg) & mask) == result) | |
296 | return 0; | |
297 | udelay(1); | |
298 | timeout--; | |
299 | } while (timeout); | |
300 | return -1; | |
301 | } | |
302 | ||
303 | static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) | |
304 | { | |
305 | unsigned long val; | |
306 | void __iomem *base = phy->regs; | |
307 | ||
3a55c6a8 | 308 | if (phy->is_legacy_phy) { |
91525d08 BG |
309 | val = readl(base + USB_SUSP_CTRL); |
310 | val |= USB_SUSP_SET; | |
311 | writel(val, base + USB_SUSP_CTRL); | |
312 | ||
313 | udelay(10); | |
314 | ||
315 | val = readl(base + USB_SUSP_CTRL); | |
316 | val &= ~USB_SUSP_SET; | |
317 | writel(val, base + USB_SUSP_CTRL); | |
bbdabdb6 | 318 | } else |
91a687d8 | 319 | set_phcd(phy, true); |
91525d08 BG |
320 | |
321 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) | |
322 | pr_err("%s: timeout waiting for phy to stabilize\n", __func__); | |
323 | } | |
324 | ||
325 | static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) | |
326 | { | |
327 | unsigned long val; | |
328 | void __iomem *base = phy->regs; | |
329 | ||
3a55c6a8 | 330 | if (phy->is_legacy_phy) { |
91525d08 BG |
331 | val = readl(base + USB_SUSP_CTRL); |
332 | val |= USB_SUSP_CLR; | |
333 | writel(val, base + USB_SUSP_CTRL); | |
334 | ||
335 | udelay(10); | |
336 | ||
337 | val = readl(base + USB_SUSP_CTRL); | |
338 | val &= ~USB_SUSP_CLR; | |
339 | writel(val, base + USB_SUSP_CTRL); | |
bbdabdb6 | 340 | } else |
91a687d8 | 341 | set_phcd(phy, false); |
91525d08 BG |
342 | |
343 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, | |
344 | USB_PHY_CLK_VALID)) | |
345 | pr_err("%s: timeout waiting for phy to stabilize\n", __func__); | |
346 | } | |
347 | ||
348 | static int utmi_phy_power_on(struct tegra_usb_phy *phy) | |
349 | { | |
350 | unsigned long val; | |
351 | void __iomem *base = phy->regs; | |
352 | struct tegra_utmip_config *config = phy->config; | |
353 | ||
354 | val = readl(base + USB_SUSP_CTRL); | |
355 | val |= UTMIP_RESET; | |
356 | writel(val, base + USB_SUSP_CTRL); | |
357 | ||
3a55c6a8 | 358 | if (phy->is_legacy_phy) { |
91525d08 BG |
359 | val = readl(base + USB1_LEGACY_CTRL); |
360 | val |= USB1_NO_LEGACY_MODE; | |
361 | writel(val, base + USB1_LEGACY_CTRL); | |
362 | } | |
363 | ||
364 | val = readl(base + UTMIP_TX_CFG0); | |
365 | val &= ~UTMIP_FS_PREABMLE_J; | |
366 | writel(val, base + UTMIP_TX_CFG0); | |
367 | ||
368 | val = readl(base + UTMIP_HSRX_CFG0); | |
369 | val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); | |
370 | val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); | |
371 | val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); | |
372 | writel(val, base + UTMIP_HSRX_CFG0); | |
373 | ||
374 | val = readl(base + UTMIP_HSRX_CFG1); | |
375 | val &= ~UTMIP_HS_SYNC_START_DLY(~0); | |
376 | val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); | |
377 | writel(val, base + UTMIP_HSRX_CFG1); | |
378 | ||
379 | val = readl(base + UTMIP_DEBOUNCE_CFG0); | |
380 | val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); | |
381 | val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); | |
382 | writel(val, base + UTMIP_DEBOUNCE_CFG0); | |
383 | ||
384 | val = readl(base + UTMIP_MISC_CFG0); | |
385 | val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; | |
386 | writel(val, base + UTMIP_MISC_CFG0); | |
387 | ||
388 | val = readl(base + UTMIP_MISC_CFG1); | |
389 | val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0)); | |
390 | val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | | |
391 | UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); | |
392 | writel(val, base + UTMIP_MISC_CFG1); | |
393 | ||
394 | val = readl(base + UTMIP_PLL_CFG1); | |
395 | val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); | |
396 | val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | | |
397 | UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); | |
398 | writel(val, base + UTMIP_PLL_CFG1); | |
399 | ||
400 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { | |
401 | val = readl(base + USB_SUSP_CTRL); | |
402 | val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); | |
403 | writel(val, base + USB_SUSP_CTRL); | |
404 | } | |
405 | ||
406 | utmip_pad_power_on(phy); | |
407 | ||
408 | val = readl(base + UTMIP_XCVR_CFG0); | |
409 | val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
410 | UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) | | |
411 | UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | | |
412 | UTMIP_XCVR_HSSLEW_MSB(~0)); | |
413 | val |= UTMIP_XCVR_SETUP(config->xcvr_setup); | |
414 | val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); | |
415 | val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); | |
416 | writel(val, base + UTMIP_XCVR_CFG0); | |
417 | ||
418 | val = readl(base + UTMIP_XCVR_CFG1); | |
419 | val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | | |
420 | UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); | |
421 | val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); | |
422 | writel(val, base + UTMIP_XCVR_CFG1); | |
423 | ||
424 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
425 | val &= ~UTMIP_PD_CHRG; | |
426 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
427 | ||
428 | val = readl(base + UTMIP_BIAS_CFG1); | |
429 | val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); | |
430 | val |= UTMIP_BIAS_PDTRK_COUNT(0x5); | |
431 | writel(val, base + UTMIP_BIAS_CFG1); | |
432 | ||
3a55c6a8 | 433 | if (phy->is_legacy_phy) { |
91525d08 BG |
434 | val = readl(base + UTMIP_SPARE_CFG0); |
435 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) | |
436 | val &= ~FUSE_SETUP_SEL; | |
437 | else | |
438 | val |= FUSE_SETUP_SEL; | |
439 | writel(val, base + UTMIP_SPARE_CFG0); | |
3a55c6a8 | 440 | } else { |
91525d08 BG |
441 | val = readl(base + USB_SUSP_CTRL); |
442 | val |= UTMIP_PHY_ENABLE; | |
443 | writel(val, base + USB_SUSP_CTRL); | |
444 | } | |
445 | ||
446 | val = readl(base + USB_SUSP_CTRL); | |
447 | val &= ~UTMIP_RESET; | |
448 | writel(val, base + USB_SUSP_CTRL); | |
449 | ||
3a55c6a8 | 450 | if (phy->is_legacy_phy) { |
91525d08 BG |
451 | val = readl(base + USB1_LEGACY_CTRL); |
452 | val &= ~USB1_VBUS_SENSE_CTL_MASK; | |
453 | val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; | |
454 | writel(val, base + USB1_LEGACY_CTRL); | |
455 | ||
456 | val = readl(base + USB_SUSP_CTRL); | |
457 | val &= ~USB_SUSP_SET; | |
458 | writel(val, base + USB_SUSP_CTRL); | |
459 | } | |
460 | ||
461 | utmi_phy_clk_enable(phy); | |
462 | ||
bbdabdb6 | 463 | if (!phy->is_legacy_phy) |
91a687d8 | 464 | set_pts(phy, 0); |
91525d08 BG |
465 | |
466 | return 0; | |
467 | } | |
468 | ||
1ba8216f | 469 | static int utmi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 BG |
470 | { |
471 | unsigned long val; | |
472 | void __iomem *base = phy->regs; | |
473 | ||
474 | utmi_phy_clk_disable(phy); | |
475 | ||
476 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { | |
477 | val = readl(base + USB_SUSP_CTRL); | |
478 | val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); | |
479 | val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); | |
480 | writel(val, base + USB_SUSP_CTRL); | |
481 | } | |
482 | ||
483 | val = readl(base + USB_SUSP_CTRL); | |
484 | val |= UTMIP_RESET; | |
485 | writel(val, base + USB_SUSP_CTRL); | |
486 | ||
487 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
488 | val |= UTMIP_PD_CHRG; | |
489 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
490 | ||
491 | val = readl(base + UTMIP_XCVR_CFG0); | |
492 | val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
493 | UTMIP_FORCE_PDZI_POWERDOWN; | |
494 | writel(val, base + UTMIP_XCVR_CFG0); | |
495 | ||
496 | val = readl(base + UTMIP_XCVR_CFG1); | |
497 | val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | | |
498 | UTMIP_FORCE_PDDR_POWERDOWN; | |
499 | writel(val, base + UTMIP_XCVR_CFG1); | |
500 | ||
1ba8216f | 501 | return utmip_pad_power_off(phy); |
91525d08 BG |
502 | } |
503 | ||
504 | static void utmi_phy_preresume(struct tegra_usb_phy *phy) | |
505 | { | |
506 | unsigned long val; | |
507 | void __iomem *base = phy->regs; | |
508 | ||
509 | val = readl(base + UTMIP_TX_CFG0); | |
510 | val |= UTMIP_HS_DISCON_DISABLE; | |
511 | writel(val, base + UTMIP_TX_CFG0); | |
512 | } | |
513 | ||
514 | static void utmi_phy_postresume(struct tegra_usb_phy *phy) | |
515 | { | |
516 | unsigned long val; | |
517 | void __iomem *base = phy->regs; | |
518 | ||
519 | val = readl(base + UTMIP_TX_CFG0); | |
520 | val &= ~UTMIP_HS_DISCON_DISABLE; | |
521 | writel(val, base + UTMIP_TX_CFG0); | |
522 | } | |
523 | ||
524 | static void utmi_phy_restore_start(struct tegra_usb_phy *phy, | |
525 | enum tegra_usb_phy_port_speed port_speed) | |
526 | { | |
527 | unsigned long val; | |
528 | void __iomem *base = phy->regs; | |
529 | ||
530 | val = readl(base + UTMIP_MISC_CFG0); | |
531 | val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); | |
532 | if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | |
533 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; | |
534 | else | |
535 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; | |
536 | writel(val, base + UTMIP_MISC_CFG0); | |
537 | udelay(1); | |
538 | ||
539 | val = readl(base + UTMIP_MISC_CFG0); | |
540 | val |= UTMIP_DPDM_OBSERVE; | |
541 | writel(val, base + UTMIP_MISC_CFG0); | |
542 | udelay(10); | |
543 | } | |
544 | ||
545 | static void utmi_phy_restore_end(struct tegra_usb_phy *phy) | |
546 | { | |
547 | unsigned long val; | |
548 | void __iomem *base = phy->regs; | |
549 | ||
550 | val = readl(base + UTMIP_MISC_CFG0); | |
551 | val &= ~UTMIP_DPDM_OBSERVE; | |
552 | writel(val, base + UTMIP_MISC_CFG0); | |
553 | udelay(10); | |
554 | } | |
555 | ||
556 | static int ulpi_phy_power_on(struct tegra_usb_phy *phy) | |
557 | { | |
558 | int ret; | |
559 | unsigned long val; | |
560 | void __iomem *base = phy->regs; | |
91525d08 | 561 | |
6829f92f VB |
562 | ret = gpio_direction_output(phy->reset_gpio, 0); |
563 | if (ret < 0) { | |
564 | dev_err(phy->dev, "gpio %d not set to 0\n", phy->reset_gpio); | |
565 | return ret; | |
566 | } | |
91525d08 | 567 | msleep(5); |
6829f92f VB |
568 | ret = gpio_direction_output(phy->reset_gpio, 1); |
569 | if (ret < 0) { | |
570 | dev_err(phy->dev, "gpio %d not set to 1\n", phy->reset_gpio); | |
571 | return ret; | |
572 | } | |
91525d08 | 573 | |
6a5278d0 | 574 | clk_prepare_enable(phy->clk); |
91525d08 BG |
575 | msleep(1); |
576 | ||
577 | val = readl(base + USB_SUSP_CTRL); | |
578 | val |= UHSIC_RESET; | |
579 | writel(val, base + USB_SUSP_CTRL); | |
580 | ||
581 | val = readl(base + ULPI_TIMING_CTRL_0); | |
582 | val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; | |
583 | writel(val, base + ULPI_TIMING_CTRL_0); | |
584 | ||
585 | val = readl(base + USB_SUSP_CTRL); | |
586 | val |= ULPI_PHY_ENABLE; | |
587 | writel(val, base + USB_SUSP_CTRL); | |
588 | ||
589 | val = 0; | |
590 | writel(val, base + ULPI_TIMING_CTRL_1); | |
591 | ||
592 | val |= ULPI_DATA_TRIMMER_SEL(4); | |
593 | val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); | |
594 | val |= ULPI_DIR_TRIMMER_SEL(4); | |
595 | writel(val, base + ULPI_TIMING_CTRL_1); | |
596 | udelay(10); | |
597 | ||
598 | val |= ULPI_DATA_TRIMMER_LOAD; | |
599 | val |= ULPI_STPDIRNXT_TRIMMER_LOAD; | |
600 | val |= ULPI_DIR_TRIMMER_LOAD; | |
601 | writel(val, base + ULPI_TIMING_CTRL_1); | |
602 | ||
603 | /* Fix VbusInvalid due to floating VBUS */ | |
b96d3b08 | 604 | ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08); |
91525d08 BG |
605 | if (ret) { |
606 | pr_err("%s: ulpi write failed\n", __func__); | |
607 | return ret; | |
608 | } | |
609 | ||
b96d3b08 | 610 | ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); |
91525d08 BG |
611 | if (ret) { |
612 | pr_err("%s: ulpi write failed\n", __func__); | |
613 | return ret; | |
614 | } | |
615 | ||
91525d08 BG |
616 | val = readl(base + USB_SUSP_CTRL); |
617 | val |= USB_SUSP_CLR; | |
618 | writel(val, base + USB_SUSP_CTRL); | |
619 | udelay(100); | |
620 | ||
621 | val = readl(base + USB_SUSP_CTRL); | |
622 | val &= ~USB_SUSP_CLR; | |
623 | writel(val, base + USB_SUSP_CTRL); | |
624 | ||
625 | return 0; | |
626 | } | |
627 | ||
1ba8216f | 628 | static int ulpi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 | 629 | { |
91525d08 | 630 | clk_disable(phy->clk); |
12ea18e4 | 631 | return gpio_direction_output(phy->reset_gpio, 0); |
1ba8216f VB |
632 | } |
633 | ||
1ba8216f VB |
634 | static void tegra_usb_phy_close(struct usb_phy *x) |
635 | { | |
636 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); | |
637 | ||
1ba8216f | 638 | clk_disable_unprepare(phy->pll_u); |
1ba8216f VB |
639 | } |
640 | ||
641 | static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) | |
642 | { | |
3f9db1a1 | 643 | if (phy->is_ulpi_phy) |
1ba8216f VB |
644 | return ulpi_phy_power_on(phy); |
645 | else | |
646 | return utmi_phy_power_on(phy); | |
647 | } | |
648 | ||
649 | static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) | |
650 | { | |
3f9db1a1 | 651 | if (phy->is_ulpi_phy) |
1ba8216f VB |
652 | return ulpi_phy_power_off(phy); |
653 | else | |
654 | return utmi_phy_power_off(phy); | |
655 | } | |
656 | ||
657 | static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend) | |
658 | { | |
659 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); | |
660 | if (suspend) | |
661 | return tegra_usb_phy_power_off(phy); | |
662 | else | |
663 | return tegra_usb_phy_power_on(phy); | |
91525d08 BG |
664 | } |
665 | ||
2d22b42d | 666 | static int ulpi_open(struct tegra_usb_phy *phy) |
91525d08 | 667 | { |
91525d08 BG |
668 | int err; |
669 | ||
2d22b42d VB |
670 | phy->clk = devm_clk_get(phy->dev, "ulpi-link"); |
671 | if (IS_ERR(phy->clk)) { | |
672 | pr_err("%s: can't get ulpi clock\n", __func__); | |
673 | return PTR_ERR(phy->clk); | |
674 | } | |
91525d08 | 675 | |
2d22b42d VB |
676 | err = devm_gpio_request(phy->dev, phy->reset_gpio, "ulpi_phy_reset_b"); |
677 | if (err < 0) { | |
678 | dev_err(phy->dev, "request failed for gpio: %d\n", | |
679 | phy->reset_gpio); | |
680 | return err; | |
681 | } | |
91525d08 | 682 | |
2d22b42d | 683 | err = gpio_direction_output(phy->reset_gpio, 0); |
9cd9384c | 684 | if (err < 0) { |
2d22b42d VB |
685 | dev_err(phy->dev, "gpio %d direction not set to output\n", |
686 | phy->reset_gpio); | |
687 | return err; | |
688 | } | |
689 | ||
690 | phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); | |
691 | if (!phy->ulpi) { | |
692 | dev_err(phy->dev, "otg_ulpi_create returned NULL\n"); | |
693 | err = -ENOMEM; | |
694 | return err; | |
695 | } | |
696 | ||
697 | phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT; | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static int tegra_usb_phy_init(struct tegra_usb_phy *phy) | |
702 | { | |
703 | unsigned long parent_rate; | |
704 | int i; | |
705 | int err; | |
706 | ||
707 | if (!phy->is_ulpi_phy) { | |
708 | if (phy->is_legacy_phy) | |
709 | phy->config = &utmip_default[0]; | |
9cd9384c | 710 | else |
2d22b42d | 711 | phy->config = &utmip_default[2]; |
91525d08 BG |
712 | } |
713 | ||
2d22b42d | 714 | phy->pll_u = devm_clk_get(phy->dev, "pll_u"); |
91525d08 BG |
715 | if (IS_ERR(phy->pll_u)) { |
716 | pr_err("Can't get pll_u clock\n"); | |
2d22b42d | 717 | return PTR_ERR(phy->pll_u); |
91525d08 | 718 | } |
2d22b42d VB |
719 | |
720 | err = clk_prepare_enable(phy->pll_u); | |
721 | if (err) | |
722 | return err; | |
91525d08 BG |
723 | |
724 | parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); | |
725 | for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { | |
726 | if (tegra_freq_table[i].freq == parent_rate) { | |
727 | phy->freq = &tegra_freq_table[i]; | |
728 | break; | |
729 | } | |
730 | } | |
731 | if (!phy->freq) { | |
732 | pr_err("invalid pll_u parent rate %ld\n", parent_rate); | |
733 | err = -EINVAL; | |
2d22b42d | 734 | goto fail; |
91525d08 BG |
735 | } |
736 | ||
2d22b42d VB |
737 | if (phy->is_ulpi_phy) |
738 | err = ulpi_open(phy); | |
739 | else | |
740 | err = utmip_pad_open(phy); | |
741 | if (err < 0) | |
742 | goto fail; | |
91525d08 | 743 | |
2d22b42d | 744 | return 0; |
91525d08 | 745 | |
2d22b42d | 746 | fail: |
6a5278d0 | 747 | clk_disable_unprepare(phy->pll_u); |
2d22b42d | 748 | return err; |
91525d08 BG |
749 | } |
750 | ||
ab137d04 | 751 | void tegra_usb_phy_preresume(struct usb_phy *x) |
91525d08 | 752 | { |
ab137d04 VB |
753 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
754 | ||
3f9db1a1 | 755 | if (!phy->is_ulpi_phy) |
91525d08 BG |
756 | utmi_phy_preresume(phy); |
757 | } | |
4265cbfd | 758 | EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); |
91525d08 | 759 | |
ab137d04 | 760 | void tegra_usb_phy_postresume(struct usb_phy *x) |
91525d08 | 761 | { |
ab137d04 VB |
762 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
763 | ||
3f9db1a1 | 764 | if (!phy->is_ulpi_phy) |
91525d08 BG |
765 | utmi_phy_postresume(phy); |
766 | } | |
4265cbfd | 767 | EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); |
91525d08 | 768 | |
ab137d04 | 769 | void tegra_ehci_phy_restore_start(struct usb_phy *x, |
91525d08 BG |
770 | enum tegra_usb_phy_port_speed port_speed) |
771 | { | |
ab137d04 VB |
772 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
773 | ||
3f9db1a1 | 774 | if (!phy->is_ulpi_phy) |
91525d08 BG |
775 | utmi_phy_restore_start(phy, port_speed); |
776 | } | |
4265cbfd | 777 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); |
91525d08 | 778 | |
ab137d04 | 779 | void tegra_ehci_phy_restore_end(struct usb_phy *x) |
91525d08 | 780 | { |
ab137d04 VB |
781 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); |
782 | ||
3f9db1a1 | 783 | if (!phy->is_ulpi_phy) |
91525d08 BG |
784 | utmi_phy_restore_end(phy); |
785 | } | |
4265cbfd | 786 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); |
91525d08 | 787 | |
2d22b42d VB |
788 | static int tegra_usb_phy_probe(struct platform_device *pdev) |
789 | { | |
790 | struct resource *res; | |
791 | struct tegra_usb_phy *tegra_phy = NULL; | |
792 | struct device_node *np = pdev->dev.of_node; | |
793 | int err; | |
794 | ||
795 | tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL); | |
796 | if (!tegra_phy) { | |
797 | dev_err(&pdev->dev, "unable to allocate memory for USB2 PHY\n"); | |
798 | return -ENOMEM; | |
799 | } | |
800 | ||
801 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
802 | if (!res) { | |
803 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
804 | return -ENXIO; | |
805 | } | |
806 | ||
807 | tegra_phy->regs = devm_ioremap(&pdev->dev, res->start, | |
808 | resource_size(res)); | |
809 | if (!tegra_phy->regs) { | |
810 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
811 | return -ENOMEM; | |
812 | } | |
813 | ||
814 | tegra_phy->is_legacy_phy = | |
815 | of_property_read_bool(np, "nvidia,has-legacy-mode"); | |
816 | ||
817 | err = of_property_match_string(np, "phy_type", "ulpi"); | |
818 | if (err < 0) { | |
819 | tegra_phy->is_ulpi_phy = false; | |
820 | ||
821 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
822 | if (!res) { | |
823 | dev_err(&pdev->dev, "Failed to get UTMI Pad regs\n"); | |
824 | return -ENXIO; | |
825 | } | |
826 | ||
827 | tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start, | |
828 | resource_size(res)); | |
829 | if (!tegra_phy->regs) { | |
830 | dev_err(&pdev->dev, "Failed to remap UTMI Pad regs\n"); | |
831 | return -ENOMEM; | |
832 | } | |
833 | } else { | |
834 | tegra_phy->is_ulpi_phy = true; | |
835 | ||
836 | tegra_phy->reset_gpio = | |
837 | of_get_named_gpio(np, "nvidia,phy-reset-gpio", 0); | |
838 | if (!gpio_is_valid(tegra_phy->reset_gpio)) { | |
839 | dev_err(&pdev->dev, "invalid gpio: %d\n", | |
840 | tegra_phy->reset_gpio); | |
841 | return tegra_phy->reset_gpio; | |
842 | } | |
843 | } | |
844 | ||
845 | err = of_property_match_string(np, "dr_mode", "otg"); | |
846 | if (err < 0) { | |
847 | err = of_property_match_string(np, "dr_mode", "peripheral"); | |
848 | if (err < 0) | |
849 | tegra_phy->mode = TEGRA_USB_PHY_MODE_HOST; | |
850 | else | |
851 | tegra_phy->mode = TEGRA_USB_PHY_MODE_DEVICE; | |
852 | } else | |
853 | tegra_phy->mode = TEGRA_USB_PHY_MODE_OTG; | |
854 | ||
855 | tegra_phy->dev = &pdev->dev; | |
856 | err = tegra_usb_phy_init(tegra_phy); | |
857 | if (err < 0) | |
858 | return err; | |
859 | ||
860 | tegra_phy->u_phy.shutdown = tegra_usb_phy_close; | |
861 | tegra_phy->u_phy.set_suspend = tegra_usb_phy_suspend; | |
862 | ||
863 | dev_set_drvdata(&pdev->dev, tegra_phy); | |
864 | return 0; | |
865 | } | |
866 | ||
867 | static struct of_device_id tegra_usb_phy_id_table[] = { | |
868 | { .compatible = "nvidia,tegra20-usb-phy", }, | |
869 | { }, | |
870 | }; | |
871 | MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table); | |
872 | ||
873 | static struct platform_driver tegra_usb_phy_driver = { | |
874 | .probe = tegra_usb_phy_probe, | |
875 | .driver = { | |
876 | .name = "tegra-phy", | |
877 | .owner = THIS_MODULE, | |
878 | .of_match_table = of_match_ptr(tegra_usb_phy_id_table), | |
879 | }, | |
880 | }; | |
881 | module_platform_driver(tegra_usb_phy_driver); | |
882 | ||
883 | static int tegra_usb_phy_match(struct device *dev, void *data) | |
884 | { | |
885 | struct tegra_usb_phy *tegra_phy = dev_get_drvdata(dev); | |
886 | struct device_node *dn = data; | |
887 | ||
888 | return (tegra_phy->dev->of_node == dn) ? 1 : 0; | |
889 | } | |
890 | ||
891 | struct usb_phy *tegra_usb_get_phy(struct device_node *dn) | |
892 | { | |
893 | struct device *dev; | |
894 | struct tegra_usb_phy *tegra_phy; | |
895 | ||
896 | dev = driver_find_device(&tegra_usb_phy_driver.driver, NULL, dn, | |
897 | tegra_usb_phy_match); | |
898 | if (!dev) | |
899 | return ERR_PTR(-EPROBE_DEFER); | |
900 | ||
901 | tegra_phy = dev_get_drvdata(dev); | |
902 | ||
903 | return &tegra_phy->u_phy; | |
904 | } | |
905 | EXPORT_SYMBOL_GPL(tegra_usb_get_phy); | |
587376a1 SW |
906 | |
907 | MODULE_DESCRIPTION("Tegra USB PHY driver"); | |
908 | MODULE_LICENSE("GPL v2"); |