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blacklight: remove redundant spi driver bus initialization
[deliverable/linux.git] / drivers / video / atmel_lcdfb.c
CommitLineData
14340586
NF		 1/*
2 * Driver for AT91/AT32 LCD Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/dma-mapping.h>
14#include <linux/interrupt.h>
15#include <linux/clk.h>
16#include <linux/fb.h>
17#include <linux/init.h>
18#include <linux/delay.h>
a9a84c37 19#include <linux/backlight.h>
5a0e3ad6 20#include <linux/gfp.h>
355b200b 21#include <linux/module.h>
14340586 22
a09e64fb
RK		 23#include <mach/board.h>
24#include <mach/cpu.h>
60e8972d 25#include <asm/gpio.h>
14340586
NF		 26
27#include <video/atmel_lcdc.h>
28
29#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
30#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
31
32/* configurable parameters */
33#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
53b7479b
NF		 34#define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */
35#define ATMEL_LCDC_FIFO_SIZE 512 /* words */
14340586
NF		 36
37#if defined(CONFIG_ARCH_AT91)
e730d8b0
HS		 38#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
39 | FBINFO_PARTIAL_PAN_OK \
40 | FBINFO_HWACCEL_YPAN)
14340586
NF		 41
42static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
b3e9c129
LP		 43 struct fb_var_screeninfo *var,
44 struct fb_info *info)
14340586
NF		 45{
46
47}
48#elif defined(CONFIG_AVR32)
49#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
50 | FBINFO_PARTIAL_PAN_OK \
51 | FBINFO_HWACCEL_XPAN \
52 | FBINFO_HWACCEL_YPAN)
53
54static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
b3e9c129
LP		 55 struct fb_var_screeninfo *var,
56 struct fb_info *info)
14340586
NF		 57{
58 u32 dma2dcfg;
59 u32 pixeloff;
60
b3e9c129 61 pixeloff = (var->xoffset * info->var.bits_per_pixel) & 0x1f;
14340586 62
b3e9c129
LP		 63 dma2dcfg = (info->var.xres_virtual - info->var.xres)
64 * info->var.bits_per_pixel / 8;
14340586
NF		 65 dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
66 lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
67
68 /* Update configuration */
69 lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
70 lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
71 | ATMEL_LCDC_DMAUPDT);
72}
73#endif
74
7cdcdb69 75static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
a9a84c37
DB		 76 | ATMEL_LCDC_POL_POSITIVE
77 | ATMEL_LCDC_ENA_PWMENABLE;
78
79#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
80
81/* some bl->props field just changed */
82static int atmel_bl_update_status(struct backlight_device *bl)
83{
84 struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
85 int power = sinfo->bl_power;
86 int brightness = bl->props.brightness;
87
88 /* REVISIT there may be a meaningful difference between
89 * fb_blank and power ... there seem to be some cases
90 * this doesn't handle correctly.
91 */
92 if (bl->props.fb_blank != sinfo->bl_power)
93 power = bl->props.fb_blank;
94 else if (bl->props.power != sinfo->bl_power)
95 power = bl->props.power;
96
97 if (brightness < 0 && power == FB_BLANK_UNBLANK)
98 brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
99 else if (power != FB_BLANK_UNBLANK)
100 brightness = 0;
101
102 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
acfdc2e1
AS		 103 if (contrast_ctr & ATMEL_LCDC_POL_POSITIVE)
104 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
a9a84c37 105 brightness ? contrast_ctr : 0);
acfdc2e1
AS		 106 else
107 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
a9a84c37
DB		 108
109 bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
110
111 return 0;
112}
113
114static int atmel_bl_get_brightness(struct backlight_device *bl)
115{
116 struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
117
118 return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
119}
120
acc2472e 121static const struct backlight_ops atmel_lcdc_bl_ops = {
a9a84c37
DB		 122 .update_status = atmel_bl_update_status,
123 .get_brightness = atmel_bl_get_brightness,
124};
125
126static void init_backlight(struct atmel_lcdfb_info *sinfo)
127{
a19a6ee6 128 struct backlight_properties props;
a9a84c37
DB		 129 struct backlight_device *bl;
130
131 sinfo->bl_power = FB_BLANK_UNBLANK;
132
133 if (sinfo->backlight)
134 return;
135
a19a6ee6 136 memset(&props, 0, sizeof(struct backlight_properties));
bb7ca747 137 props.type = BACKLIGHT_RAW;
a19a6ee6
MG		 138 props.max_brightness = 0xff;
139 bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
140 &atmel_lcdc_bl_ops, &props);
cf7b9a1e 141 if (IS_ERR(bl)) {
a9a84c37
DB		 142 dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
143 PTR_ERR(bl));
144 return;
145 }
146 sinfo->backlight = bl;
147
148 bl->props.power = FB_BLANK_UNBLANK;
149 bl->props.fb_blank = FB_BLANK_UNBLANK;
a9a84c37
DB		 150 bl->props.brightness = atmel_bl_get_brightness(bl);
151}
152
153static void exit_backlight(struct atmel_lcdfb_info *sinfo)
154{
155 if (sinfo->backlight)
156 backlight_device_unregister(sinfo->backlight);
157}
158
159#else
160
161static void init_backlight(struct atmel_lcdfb_info *sinfo)
162{
163 dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
164}
165
166static void exit_backlight(struct atmel_lcdfb_info *sinfo)
167{
168}
169
170#endif
171
172static void init_contrast(struct atmel_lcdfb_info *sinfo)
173{
7cdcdb69
AB		 174 /* contrast pwm can be 'inverted' */
175 if (sinfo->lcdcon_pol_negative)
176 contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
177
a9a84c37
DB		 178 /* have some default contrast/backlight settings */
179 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
180 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
181
182 if (sinfo->lcdcon_is_backlight)
183 init_backlight(sinfo);
184}
185
14340586
NF		 186
187static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
188 .type = FB_TYPE_PACKED_PIXELS,
189 .visual = FB_VISUAL_TRUECOLOR,
190 .xpanstep = 0,
e730d8b0 191 .ypanstep = 1,
14340586
NF		 192 .ywrapstep = 0,
193 .accel = FB_ACCEL_NONE,
194};
195
250a269d
NF		 196static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
197{
198 unsigned long value;
199
915190f7
NF		 200 if (!(cpu_is_at91sam9261() || cpu_is_at91sam9g10()
201 || cpu_is_at32ap7000()))
250a269d
NF		 202 return xres;
203
204 value = xres;
205 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
206 /* STN display */
207 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
208 value *= 3;
209 }
210 if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
211 || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
212 && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
213 value = DIV_ROUND_UP(value, 4);
214 else
215 value = DIV_ROUND_UP(value, 8);
216 }
217
218 return value;
219}
14340586 220
3aa04f1b
HS		 221static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
222{
223 /* Turn off the LCD controller and the DMA controller */
224 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
225 sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
226
227 /* Wait for the LCDC core to become idle */
228 while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
229 msleep(10);
230
231 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
232}
233
234static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
235{
236 atmel_lcdfb_stop_nowait(sinfo);
237
238 /* Wait for DMA engine to become idle... */
239 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
240 msleep(10);
241}
242
243static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
244{
245 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
246 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
247 (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
248 | ATMEL_LCDC_PWR);
249}
250
14340586
NF		 251static void atmel_lcdfb_update_dma(struct fb_info *info,
252 struct fb_var_screeninfo *var)
253{
254 struct atmel_lcdfb_info *sinfo = info->par;
255 struct fb_fix_screeninfo *fix = &info->fix;
256 unsigned long dma_addr;
257
258 dma_addr = (fix->smem_start + var->yoffset * fix->line_length
b3e9c129 259 + var->xoffset * info->var.bits_per_pixel / 8);
14340586
NF		 260
261 dma_addr &= ~3UL;
262
263 /* Set framebuffer DMA base address and pixel offset */
264 lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
265
b3e9c129 266 atmel_lcdfb_update_dma2d(sinfo, var, info);
14340586
NF		 267}
268
269static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
270{
271 struct fb_info *info = sinfo->info;
272
273 dma_free_writecombine(info->device, info->fix.smem_len,
274 info->screen_base, info->fix.smem_start);
275}
276
277/**
278 * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
279 * @sinfo: the frame buffer to allocate memory for
1d01e835
KH		 280 *
281 * This function is called only from the atmel_lcdfb_probe()
282 * so no locking by fb_info->mm_lock around smem_len setting is needed.
14340586
NF		 283 */
284static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
285{
286 struct fb_info *info = sinfo->info;
287 struct fb_var_screeninfo *var = &info->var;
ea757aca 288 unsigned int smem_len;
14340586 289
ea757aca
HS		 290 smem_len = (var->xres_virtual * var->yres_virtual
291 * ((var->bits_per_pixel + 7) / 8));
292 info->fix.smem_len = max(smem_len, sinfo->smem_len);
14340586
NF		 293
294 info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
295 (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
296
297 if (!info->screen_base) {
298 return -ENOMEM;
299 }
300
01d3a5e7
HS		 301 memset(info->screen_base, 0, info->fix.smem_len);
302
14340586
NF		 303 return 0;
304}
305
968910bd
NF		 306static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
307 struct fb_info *info)
308{
309 struct fb_videomode varfbmode;
310 const struct fb_videomode *fbmode = NULL;
311
312 fb_var_to_videomode(&varfbmode, var);
313 fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
314 if (fbmode)
315 fb_videomode_to_var(var, fbmode);
316 return fbmode;
317}
318
319
14340586
NF		 320/**
321 * atmel_lcdfb_check_var - Validates a var passed in.
322 * @var: frame buffer variable screen structure
323 * @info: frame buffer structure that represents a single frame buffer
324 *
325 * Checks to see if the hardware supports the state requested by
326 * var passed in. This function does not alter the hardware
327 * state!!! This means the data stored in struct fb_info and
328 * struct atmel_lcdfb_info do not change. This includes the var
329 * inside of struct fb_info. Do NOT change these. This function
330 * can be called on its own if we intent to only test a mode and
331 * not actually set it. The stuff in modedb.c is a example of
332 * this. If the var passed in is slightly off by what the
333 * hardware can support then we alter the var PASSED in to what
334 * we can do. If the hardware doesn't support mode change a
335 * -EINVAL will be returned by the upper layers. You don't need
336 * to implement this function then. If you hardware doesn't
337 * support changing the resolution then this function is not
338 * needed. In this case the driver would just provide a var that
339 * represents the static state the screen is in.
340 *
341 * Returns negative errno on error, or zero on success.
342 */
343static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
344 struct fb_info *info)
345{
346 struct device *dev = info->device;
347 struct atmel_lcdfb_info *sinfo = info->par;
348 unsigned long clk_value_khz;
349
350 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
351
352 dev_dbg(dev, "%s:\n", __func__);
968910bd
NF		 353
354 if (!(var->pixclock && var->bits_per_pixel)) {
355 /* choose a suitable mode if possible */
356 if (!atmel_lcdfb_choose_mode(var, info)) {
357 dev_err(dev, "needed value not specified\n");
358 return -EINVAL;
359 }
360 }
361
14340586
NF		 362 dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
363 dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
364 dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
365 dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
366
97b9a5a2 367 if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
14340586
NF		 368 dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
369 return -EINVAL;
370 }
371
968910bd
NF		 372 /* Do not allow to have real resoulution larger than virtual */
373 if (var->xres > var->xres_virtual)
374 var->xres_virtual = var->xres;
375
376 if (var->yres > var->yres_virtual)
377 var->yres_virtual = var->yres;
378
14340586
NF		 379 /* Force same alignment for each line */
380 var->xres = (var->xres + 3) & ~3UL;
381 var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
382
383 var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
384 var->transp.msb_right = 0;
385 var->transp.offset = var->transp.length = 0;
386 var->xoffset = var->yoffset = 0;
387
f928ac0a
SG		 388 if (info->fix.smem_len) {
389 unsigned int smem_len = (var->xres_virtual * var->yres_virtual
390 * ((var->bits_per_pixel + 7) / 8));
391 if (smem_len > info->fix.smem_len)
392 return -EINVAL;
393 }
394
162b3a08
HS		 395 /* Saturate vertical and horizontal timings at maximum values */
396 var->vsync_len = min_t(u32, var->vsync_len,
397 (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
398 var->upper_margin = min_t(u32, var->upper_margin,
399 ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
400 var->lower_margin = min_t(u32, var->lower_margin,
401 ATMEL_LCDC_VFP);
402 var->right_margin = min_t(u32, var->right_margin,
6b3cbe40 403 (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
162b3a08
HS		 404 var->hsync_len = min_t(u32, var->hsync_len,
405 (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
406 var->left_margin = min_t(u32, var->left_margin,
407 ATMEL_LCDC_HBP + 1);
408
409 /* Some parameters can't be zero */
410 var->vsync_len = max_t(u32, var->vsync_len, 1);
411 var->right_margin = max_t(u32, var->right_margin, 1);
412 var->hsync_len = max_t(u32, var->hsync_len, 1);
413 var->left_margin = max_t(u32, var->left_margin, 1);
414
14340586 415 switch (var->bits_per_pixel) {
250a269d 416 case 1:
14340586
NF		 417 case 2:
418 case 4:
419 case 8:
420 var->red.offset = var->green.offset = var->blue.offset = 0;
421 var->red.length = var->green.length = var->blue.length
422 = var->bits_per_pixel;
423 break;
14340586 424 case 16:
fd085801
NF		 425 if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
426 /* RGB:565 mode */
427 var->red.offset = 11;
428 var->blue.offset = 0;
fd085801 429 } else {
787f9fd2 430 /* BGR:565 mode */
fd085801 431 var->red.offset = 0;
787f9fd2 432 var->blue.offset = 11;
fd085801 433 }
14340586 434 var->green.offset = 5;
787f9fd2 435 var->green.length = 6;
fd085801 436 var->red.length = var->blue.length = 5;
14340586 437 break;
14340586 438 case 32:
4440e0e1
HS		 439 var->transp.offset = 24;
440 var->transp.length = 8;
441 /* fall through */
442 case 24:
fd085801
NF		 443 if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
444 /* RGB:888 mode */
445 var->red.offset = 16;
446 var->blue.offset = 0;
447 } else {
448 /* BGR:888 mode */
449 var->red.offset = 0;
450 var->blue.offset = 16;
451 }
14340586 452 var->green.offset = 8;
14340586
NF		 453 var->red.length = var->green.length = var->blue.length = 8;
454 break;
455 default:
456 dev_err(dev, "color depth %d not supported\n",
457 var->bits_per_pixel);
458 return -EINVAL;
459 }
460
461 return 0;
462}
463
d22579b8
NF		 464/*
465 * LCD reset sequence
466 */
467static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
468{
469 might_sleep();
470
3aa04f1b
HS		 471 atmel_lcdfb_stop(sinfo);
472 atmel_lcdfb_start(sinfo);
d22579b8
NF		 473}
474
14340586
NF		 475/**
476 * atmel_lcdfb_set_par - Alters the hardware state.
477 * @info: frame buffer structure that represents a single frame buffer
478 *
479 * Using the fb_var_screeninfo in fb_info we set the resolution
480 * of the this particular framebuffer. This function alters the
481 * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
482 * not alter var in fb_info since we are using that data. This
483 * means we depend on the data in var inside fb_info to be
484 * supported by the hardware. atmel_lcdfb_check_var is always called
485 * before atmel_lcdfb_set_par to ensure this. Again if you can't
486 * change the resolution you don't need this function.
487 *
488 */
489static int atmel_lcdfb_set_par(struct fb_info *info)
490{
491 struct atmel_lcdfb_info *sinfo = info->par;
250a269d 492 unsigned long hozval_linesz;
14340586
NF		 493 unsigned long value;
494 unsigned long clk_value_khz;
250a269d 495 unsigned long bits_per_line;
431861cf 496 unsigned long pix_factor = 2;
14340586 497
d22579b8
NF		 498 might_sleep();
499
14340586
NF		 500 dev_dbg(info->device, "%s:\n", __func__);
501 dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
502 info->var.xres, info->var.yres,
503 info->var.xres_virtual, info->var.yres_virtual);
504
3aa04f1b 505 atmel_lcdfb_stop_nowait(sinfo);
14340586 506
250a269d
NF		 507 if (info->var.bits_per_pixel == 1)
508 info->fix.visual = FB_VISUAL_MONO01;
509 else if (info->var.bits_per_pixel <= 8)
14340586
NF		 510 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
511 else
512 info->fix.visual = FB_VISUAL_TRUECOLOR;
513
250a269d
NF		 514 bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
515 info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
14340586
NF		 516
517 /* Re-initialize the DMA engine... */
518 dev_dbg(info->device, " * update DMA engine\n");
519 atmel_lcdfb_update_dma(info, &info->var);
520
521 /* ...set frame size and burst length = 8 words (?) */
522 value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
523 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
524 lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
525
526 /* Now, the LCDC core... */
527
528 /* Set pixel clock */
431861cf
NF		 529 if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es())
530 pix_factor = 1;
531
14340586
NF		 532 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
533
250a269d 534 value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
14340586 535
431861cf 536 if (value < pix_factor) {
14340586
NF		 537 dev_notice(info->device, "Bypassing pixel clock divider\n");
538 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
250a269d 539 } else {
431861cf 540 value = (value / pix_factor) - 1;
baf6332a
NF		 541 dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n",
542 value);
543 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
544 value << ATMEL_LCDC_CLKVAL_OFFSET);
431861cf
NF		 545 info->var.pixclock =
546 KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
250a269d
NF		 547 dev_dbg(info->device, " updated pixclk: %lu KHz\n",
548 PICOS2KHZ(info->var.pixclock));
549 }
550
14340586
NF		 551
552 /* Initialize control register 2 */
553 value = sinfo->default_lcdcon2;
554
555 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
556 value |= ATMEL_LCDC_INVLINE_INVERTED;
557 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
558 value |= ATMEL_LCDC_INVFRAME_INVERTED;
559
560 switch (info->var.bits_per_pixel) {
561 case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
562 case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
563 case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
564 case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
565 case 15: /* fall through */
566 case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
567 case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
568 case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
569 default: BUG(); break;
570 }
571 dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
572 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
573
574 /* Vertical timing */
575 value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
576 value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
577 value |= info->var.lower_margin;
578 dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
579 lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
580
581 /* Horizontal timing */
6b3cbe40 582 value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
14340586
NF		 583 value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
584 value |= (info->var.left_margin - 1);
585 dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
586 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
587
250a269d
NF		 588 /* Horizontal value (aka line size) */
589 hozval_linesz = compute_hozval(info->var.xres,
590 lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
591
14340586 592 /* Display size */
250a269d 593 value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
14340586 594 value |= info->var.yres - 1;
250a269d 595 dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
14340586
NF		 596 lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
597
598 /* FIFO Threshold: Use formula from data sheet */
599 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
600 lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
601
602 /* Toggle LCD_MODE every frame */
603 lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
604
605 /* Disable all interrupts */
606 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
d22579b8
NF		 607 /* Enable FIFO & DMA errors */
608 lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
14340586 609
14340586
NF		 610 /* ...wait for DMA engine to become idle... */
611 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
612 msleep(10);
613
3aa04f1b 614 atmel_lcdfb_start(sinfo);
14340586
NF		 615
616 dev_dbg(info->device, " * DONE\n");
617
618 return 0;
619}
620
621static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
622{
623 chan &= 0xffff;
624 chan >>= 16 - bf->length;
625 return chan << bf->offset;
626}
627
628/**
629 * atmel_lcdfb_setcolreg - Optional function. Sets a color register.
630 * @regno: Which register in the CLUT we are programming
631 * @red: The red value which can be up to 16 bits wide
632 * @green: The green value which can be up to 16 bits wide
633 * @blue: The blue value which can be up to 16 bits wide.
634 * @transp: If supported the alpha value which can be up to 16 bits wide.
635 * @info: frame buffer info structure
636 *
637 * Set a single color register. The values supplied have a 16 bit
638 * magnitude which needs to be scaled in this function for the hardware.
639 * Things to take into consideration are how many color registers, if
640 * any, are supported with the current color visual. With truecolor mode
25985edc 641 * no color palettes are supported. Here a pseudo palette is created
14340586
NF		 642 * which we store the value in pseudo_palette in struct fb_info. For
643 * pseudocolor mode we have a limited color palette. To deal with this
644 * we can program what color is displayed for a particular pixel value.
645 * DirectColor is similar in that we can program each color field. If
646 * we have a static colormap we don't need to implement this function.
647 *
648 * Returns negative errno on error, or zero on success. In an
649 * ideal world, this would have been the case, but as it turns
650 * out, the other drivers return 1 on failure, so that's what
651 * we're going to do.
652 */
653static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
654 unsigned int green, unsigned int blue,
655 unsigned int transp, struct fb_info *info)
656{
657 struct atmel_lcdfb_info *sinfo = info->par;
658 unsigned int val;
659 u32 *pal;
660 int ret = 1;
661
662 if (info->var.grayscale)
663 red = green = blue = (19595 * red + 38470 * green
664 + 7471 * blue) >> 16;
665
666 switch (info->fix.visual) {
667 case FB_VISUAL_TRUECOLOR:
668 if (regno < 16) {
669 pal = info->pseudo_palette;
670
671 val = chan_to_field(red, &info->var.red);
672 val |= chan_to_field(green, &info->var.green);
673 val |= chan_to_field(blue, &info->var.blue);
674
675 pal[regno] = val;
676 ret = 0;
677 }
678 break;
679
680 case FB_VISUAL_PSEUDOCOLOR:
681 if (regno < 256) {
5d67b89c
PK		 682 if (cpu_is_at91sam9261() || cpu_is_at91sam9263()
683 || cpu_is_at91sam9rl()) {
684 /* old style I+BGR:555 */
685 val = ((red >> 11) & 0x001f);
686 val |= ((green >> 6) & 0x03e0);
687 val |= ((blue >> 1) & 0x7c00);
688
689 /*
690 * TODO: intensity bit. Maybe something like
691 * ~(red[10] ^ green[10] ^ blue[10]) & 1
692 */
693 } else {
694 /* new style BGR:565 / RGB:565 */
695 if (sinfo->lcd_wiring_mode ==
696 ATMEL_LCDC_WIRING_RGB) {
697 val = ((blue >> 11) & 0x001f);
698 val |= ((red >> 0) & 0xf800);
699 } else {
700 val = ((red >> 11) & 0x001f);
701 val |= ((blue >> 0) & 0xf800);
702 }
703
704 val |= ((green >> 5) & 0x07e0);
705 }
14340586
NF		 706
707 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
708 ret = 0;
709 }
710 break;
250a269d
NF		 711
712 case FB_VISUAL_MONO01:
713 if (regno < 2) {
714 val = (regno == 0) ? 0x00 : 0x1F;
715 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
716 ret = 0;
717 }
718 break;
719
14340586
NF		 720 }
721
722 return ret;
723}
724
725static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
726 struct fb_info *info)
727{
728 dev_dbg(info->device, "%s\n", __func__);
729
730 atmel_lcdfb_update_dma(info, var);
731
732 return 0;
733}
734
bed7bddb
AB		 735static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
736{
737 struct atmel_lcdfb_info *sinfo = info->par;
738
739 switch (blank_mode) {
740 case FB_BLANK_UNBLANK:
741 case FB_BLANK_NORMAL:
742 atmel_lcdfb_start(sinfo);
743 break;
744 case FB_BLANK_VSYNC_SUSPEND:
745 case FB_BLANK_HSYNC_SUSPEND:
746 break;
747 case FB_BLANK_POWERDOWN:
748 atmel_lcdfb_stop(sinfo);
749 break;
750 default:
751 return -EINVAL;
752 }
753
754 /* let fbcon do a soft blank for us */
755 return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
756}
757
14340586
NF		 758static struct fb_ops atmel_lcdfb_ops = {
759 .owner = THIS_MODULE,
760 .fb_check_var = atmel_lcdfb_check_var,
761 .fb_set_par = atmel_lcdfb_set_par,
762 .fb_setcolreg = atmel_lcdfb_setcolreg,
bed7bddb 763 .fb_blank = atmel_lcdfb_blank,
14340586
NF		 764 .fb_pan_display = atmel_lcdfb_pan_display,
765 .fb_fillrect = cfb_fillrect,
766 .fb_copyarea = cfb_copyarea,
767 .fb_imageblit = cfb_imageblit,
768};
769
770static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
771{
772 struct fb_info *info = dev_id;
773 struct atmel_lcdfb_info *sinfo = info->par;
774 u32 status;
775
776 status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
d22579b8
NF		 777 if (status & ATMEL_LCDC_UFLWI) {
778 dev_warn(info->device, "FIFO underflow %#x\n", status);
779 /* reset DMA and FIFO to avoid screen shifting */
780 schedule_work(&sinfo->task);
781 }
782 lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
14340586
NF		 783 return IRQ_HANDLED;
784}
785
d22579b8
NF		 786/*
787 * LCD controller task (to reset the LCD)
788 */
789static void atmel_lcdfb_task(struct work_struct *work)
790{
791 struct atmel_lcdfb_info *sinfo =
792 container_of(work, struct atmel_lcdfb_info, task);
793
794 atmel_lcdfb_reset(sinfo);
795}
796
14340586
NF		 797static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
798{
799 struct fb_info *info = sinfo->info;
800 int ret = 0;
801
14340586
NF		 802 info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
803
804 dev_info(info->device,
805 "%luKiB frame buffer at %08lx (mapped at %p)\n",
806 (unsigned long)info->fix.smem_len / 1024,
807 (unsigned long)info->fix.smem_start,
808 info->screen_base);
809
810 /* Allocate colormap */
811 ret = fb_alloc_cmap(&info->cmap, 256, 0);
812 if (ret < 0)
813 dev_err(info->device, "Alloc color map failed\n");
814
815 return ret;
816}
817
818static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
819{
820 if (sinfo->bus_clk)
821 clk_enable(sinfo->bus_clk);
822 clk_enable(sinfo->lcdc_clk);
823}
824
825static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
826{
827 if (sinfo->bus_clk)
828 clk_disable(sinfo->bus_clk);
829 clk_disable(sinfo->lcdc_clk);
830}
831
832
833static int __init atmel_lcdfb_probe(struct platform_device *pdev)
834{
835 struct device *dev = &pdev->dev;
836 struct fb_info *info;
837 struct atmel_lcdfb_info *sinfo;
838 struct atmel_lcdfb_info *pdata_sinfo;
968910bd 839 struct fb_videomode fbmode;
14340586
NF		 840 struct resource *regs = NULL;
841 struct resource *map = NULL;
842 int ret;
843
844 dev_dbg(dev, "%s BEGIN\n", __func__);
845
846 ret = -ENOMEM;
847 info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
848 if (!info) {
849 dev_err(dev, "cannot allocate memory\n");
850 goto out;
851 }
852
853 sinfo = info->par;
854
855 if (dev->platform_data) {
856 pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
857 sinfo->default_bpp = pdata_sinfo->default_bpp;
858 sinfo->default_dmacon = pdata_sinfo->default_dmacon;
859 sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
860 sinfo->default_monspecs = pdata_sinfo->default_monspecs;
861 sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
862 sinfo->guard_time = pdata_sinfo->guard_time;
ea757aca 863 sinfo->smem_len = pdata_sinfo->smem_len;
a9a84c37 864 sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
7cdcdb69 865 sinfo->lcdcon_pol_negative = pdata_sinfo->lcdcon_pol_negative;
fd085801 866 sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
14340586
NF		 867 } else {
868 dev_err(dev, "cannot get default configuration\n");
869 goto free_info;
870 }
871 sinfo->info = info;
872 sinfo->pdev = pdev;
873
874 strcpy(info->fix.id, sinfo->pdev->name);
875 info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
876 info->pseudo_palette = sinfo->pseudo_palette;
877 info->fbops = &atmel_lcdfb_ops;
878
879 memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
880 info->fix = atmel_lcdfb_fix;
881
882 /* Enable LCDC Clocks */
915190f7
NF		 883 if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()
884 || cpu_is_at32ap7000()) {
14340586
NF		 885 sinfo->bus_clk = clk_get(dev, "hck1");
886 if (IS_ERR(sinfo->bus_clk)) {
887 ret = PTR_ERR(sinfo->bus_clk);
888 goto free_info;
889 }
890 }
891 sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
892 if (IS_ERR(sinfo->lcdc_clk)) {
893 ret = PTR_ERR(sinfo->lcdc_clk);
894 goto put_bus_clk;
895 }
896 atmel_lcdfb_start_clock(sinfo);
897
898 ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
899 info->monspecs.modedb_len, info->monspecs.modedb,
900 sinfo->default_bpp);
901 if (!ret) {
902 dev_err(dev, "no suitable video mode found\n");
903 goto stop_clk;
904 }
905
906
907 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
908 if (!regs) {
909 dev_err(dev, "resources unusable\n");
910 ret = -ENXIO;
911 goto stop_clk;
912 }
913
914 sinfo->irq_base = platform_get_irq(pdev, 0);
915 if (sinfo->irq_base < 0) {
916 dev_err(dev, "unable to get irq\n");
917 ret = sinfo->irq_base;
918 goto stop_clk;
919 }
920
921 /* Initialize video memory */
922 map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
923 if (map) {
924 /* use a pre-allocated memory buffer */
925 info->fix.smem_start = map->start;
28f65c11 926 info->fix.smem_len = resource_size(map);
14340586
NF		 927 if (!request_mem_region(info->fix.smem_start,
928 info->fix.smem_len, pdev->name)) {
929 ret = -EBUSY;
930 goto stop_clk;
931 }
932
933 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
934 if (!info->screen_base)
935 goto release_intmem;
01d3a5e7
HS		 936
937 /*
938 * Don't clear the framebuffer -- someone may have set
939 * up a splash image.
940 */
14340586
NF		 941 } else {
942 /* alocate memory buffer */
943 ret = atmel_lcdfb_alloc_video_memory(sinfo);
944 if (ret < 0) {
945 dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
946 goto stop_clk;
947 }
948 }
949
950 /* LCDC registers */
951 info->fix.mmio_start = regs->start;
28f65c11 952 info->fix.mmio_len = resource_size(regs);
14340586
NF		 953
954 if (!request_mem_region(info->fix.mmio_start,
955 info->fix.mmio_len, pdev->name)) {
956 ret = -EBUSY;
957 goto free_fb;
958 }
959
960 sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
961 if (!sinfo->mmio) {
962 dev_err(dev, "cannot map LCDC registers\n");
963 goto release_mem;
964 }
965
a9a84c37
DB		 966 /* Initialize PWM for contrast or backlight ("off") */
967 init_contrast(sinfo);
968
14340586
NF		 969 /* interrupt */
970 ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
971 if (ret) {
972 dev_err(dev, "request_irq failed: %d\n", ret);
973 goto unmap_mmio;
974 }
975
d22579b8
NF		 976 /* Some operations on the LCDC might sleep and
977 * require a preemptible task context */
978 INIT_WORK(&sinfo->task, atmel_lcdfb_task);
979
14340586
NF		 980 ret = atmel_lcdfb_init_fbinfo(sinfo);
981 if (ret < 0) {
982 dev_err(dev, "init fbinfo failed: %d\n", ret);
983 goto unregister_irqs;
984 }
985
986 /*
987 * This makes sure that our colour bitfield
988 * descriptors are correctly initialised.
989 */
990 atmel_lcdfb_check_var(&info->var, info);
991
992 ret = fb_set_var(info, &info->var);
993 if (ret) {
994 dev_warn(dev, "unable to set display parameters\n");
995 goto free_cmap;
996 }
997
998 dev_set_drvdata(dev, info);
999
1000 /*
1001 * Tell the world that we're ready to go
1002 */
1003 ret = register_framebuffer(info);
1004 if (ret < 0) {
1005 dev_err(dev, "failed to register framebuffer device: %d\n", ret);
34a35bdd 1006 goto reset_drvdata;
14340586
NF		 1007 }
1008
968910bd
NF		 1009 /* add selected videomode to modelist */
1010 fb_var_to_videomode(&fbmode, &info->var);
1011 fb_add_videomode(&fbmode, &info->modelist);
1012
14340586
NF		 1013 /* Power up the LCDC screen */
1014 if (sinfo->atmel_lcdfb_power_control)
1015 sinfo->atmel_lcdfb_power_control(1);
1016
93f6ced9 1017 dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n",
14340586
NF		 1018 info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
1019
1020 return 0;
1021
34a35bdd
SG		 1022reset_drvdata:
1023 dev_set_drvdata(dev, NULL);
14340586
NF		 1024free_cmap:
1025 fb_dealloc_cmap(&info->cmap);
1026unregister_irqs:
d22579b8 1027 cancel_work_sync(&sinfo->task);
14340586
NF		 1028 free_irq(sinfo->irq_base, info);
1029unmap_mmio:
a9a84c37 1030 exit_backlight(sinfo);
14340586
NF		 1031 iounmap(sinfo->mmio);
1032release_mem:
1033 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1034free_fb:
1035 if (map)
1036 iounmap(info->screen_base);
1037 else
1038 atmel_lcdfb_free_video_memory(sinfo);
1039
1040release_intmem:
1041 if (map)
1042 release_mem_region(info->fix.smem_start, info->fix.smem_len);
1043stop_clk:
1044 atmel_lcdfb_stop_clock(sinfo);
1045 clk_put(sinfo->lcdc_clk);
1046put_bus_clk:
1047 if (sinfo->bus_clk)
1048 clk_put(sinfo->bus_clk);
1049free_info:
1050 framebuffer_release(info);
1051out:
1052 dev_dbg(dev, "%s FAILED\n", __func__);
1053 return ret;
1054}
1055
1056static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
1057{
1058 struct device *dev = &pdev->dev;
1059 struct fb_info *info = dev_get_drvdata(dev);
34a35bdd 1060 struct atmel_lcdfb_info *sinfo;
14340586 1061
34a35bdd 1062 if (!info || !info->par)
14340586 1063 return 0;
34a35bdd 1064 sinfo = info->par;
14340586 1065
d22579b8 1066 cancel_work_sync(&sinfo->task);
a9a84c37 1067 exit_backlight(sinfo);
14340586
NF		 1068 if (sinfo->atmel_lcdfb_power_control)
1069 sinfo->atmel_lcdfb_power_control(0);
1070 unregister_framebuffer(info);
1071 atmel_lcdfb_stop_clock(sinfo);
1072 clk_put(sinfo->lcdc_clk);
1073 if (sinfo->bus_clk)
1074 clk_put(sinfo->bus_clk);
1075 fb_dealloc_cmap(&info->cmap);
1076 free_irq(sinfo->irq_base, info);
1077 iounmap(sinfo->mmio);
1078 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1079 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
1080 iounmap(info->screen_base);
1081 release_mem_region(info->fix.smem_start, info->fix.smem_len);
1082 } else {
1083 atmel_lcdfb_free_video_memory(sinfo);
1084 }
1085
1086 dev_set_drvdata(dev, NULL);
1087 framebuffer_release(info);
1088
1089 return 0;
1090}
1091
cf19a37e
DB		 1092#ifdef CONFIG_PM
1093
1094static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
1095{
1096 struct fb_info *info = platform_get_drvdata(pdev);
1097 struct atmel_lcdfb_info *sinfo = info->par;
1098
3aa04f1b
HS		 1099 /*
1100 * We don't want to handle interrupts while the clock is
1101 * stopped. It may take forever.
1102 */
1103 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
1104
9f106503 1105 sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_CTR);
cf19a37e
DB		 1106 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
1107 if (sinfo->atmel_lcdfb_power_control)
1108 sinfo->atmel_lcdfb_power_control(0);
3aa04f1b
HS		 1109
1110 atmel_lcdfb_stop(sinfo);
cf19a37e 1111 atmel_lcdfb_stop_clock(sinfo);
3aa04f1b 1112
cf19a37e
DB		 1113 return 0;
1114}
1115
1116static int atmel_lcdfb_resume(struct platform_device *pdev)
1117{
1118 struct fb_info *info = platform_get_drvdata(pdev);
1119 struct atmel_lcdfb_info *sinfo = info->par;
1120
1121 atmel_lcdfb_start_clock(sinfo);
3aa04f1b 1122 atmel_lcdfb_start(sinfo);
cf19a37e
DB		 1123 if (sinfo->atmel_lcdfb_power_control)
1124 sinfo->atmel_lcdfb_power_control(1);
1125 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
3aa04f1b
HS		 1126
1127 /* Enable FIFO & DMA errors */
1128 lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
1129 | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
1130
cf19a37e
DB		 1131 return 0;
1132}
1133
1134#else
1135#define atmel_lcdfb_suspend NULL
1136#define atmel_lcdfb_resume NULL
1137#endif
1138
14340586
NF		 1139static struct platform_driver atmel_lcdfb_driver = {
1140 .remove = __exit_p(atmel_lcdfb_remove),
cf19a37e
DB		 1141 .suspend = atmel_lcdfb_suspend,
1142 .resume = atmel_lcdfb_resume,
a9a84c37 1143
14340586
NF		 1144 .driver = {
1145 .name = "atmel_lcdfb",
1146 .owner = THIS_MODULE,
1147 },
1148};
1149
1150static int __init atmel_lcdfb_init(void)
1151{
1152 return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe);
1153}
1154
1155static void __exit atmel_lcdfb_exit(void)
1156{
1157 platform_driver_unregister(&atmel_lcdfb_driver);
1158}
1159
1160module_init(atmel_lcdfb_init);
1161module_exit(atmel_lcdfb_exit);
1162
1163MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
8f4c79ce 1164MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
14340586 1165MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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