[ARM] 5228/1: Add the RGB555 wiring for the atmel LCD
[deliverable/linux.git] / drivers / video / atmel_lcdfb.c
CommitLineData
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1/*
2 * Driver for AT91/AT32 LCD Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/dma-mapping.h>
14#include <linux/interrupt.h>
15#include <linux/clk.h>
16#include <linux/fb.h>
17#include <linux/init.h>
18#include <linux/delay.h>
a9a84c37 19#include <linux/backlight.h>
14340586 20
a09e64fb
RK
21#include <mach/board.h>
22#include <mach/cpu.h>
23#include <mach/gpio.h>
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24
25#include <video/atmel_lcdc.h>
26
27#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
28#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
29
30/* configurable parameters */
31#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
32#define ATMEL_LCDC_DMA_BURST_LEN 8
33
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34#if defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9) || \
35 defined(CONFIG_ARCH_AT91SAM9RL)
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36#define ATMEL_LCDC_FIFO_SIZE 2048
37#else
38#define ATMEL_LCDC_FIFO_SIZE 512
39#endif
40
41#if defined(CONFIG_ARCH_AT91)
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42#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
43 | FBINFO_PARTIAL_PAN_OK \
44 | FBINFO_HWACCEL_YPAN)
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45
46static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
47 struct fb_var_screeninfo *var)
48{
49
50}
51#elif defined(CONFIG_AVR32)
52#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
53 | FBINFO_PARTIAL_PAN_OK \
54 | FBINFO_HWACCEL_XPAN \
55 | FBINFO_HWACCEL_YPAN)
56
57static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
58 struct fb_var_screeninfo *var)
59{
60 u32 dma2dcfg;
61 u32 pixeloff;
62
63 pixeloff = (var->xoffset * var->bits_per_pixel) & 0x1f;
64
65 dma2dcfg = ((var->xres_virtual - var->xres) * var->bits_per_pixel) / 8;
66 dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
67 lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
68
69 /* Update configuration */
70 lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
71 lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
72 | ATMEL_LCDC_DMAUPDT);
73}
74#endif
75
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DB
76static const u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
77 | ATMEL_LCDC_POL_POSITIVE
78 | ATMEL_LCDC_ENA_PWMENABLE;
79
80#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
81
82/* some bl->props field just changed */
83static int atmel_bl_update_status(struct backlight_device *bl)
84{
85 struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
86 int power = sinfo->bl_power;
87 int brightness = bl->props.brightness;
88
89 /* REVISIT there may be a meaningful difference between
90 * fb_blank and power ... there seem to be some cases
91 * this doesn't handle correctly.
92 */
93 if (bl->props.fb_blank != sinfo->bl_power)
94 power = bl->props.fb_blank;
95 else if (bl->props.power != sinfo->bl_power)
96 power = bl->props.power;
97
98 if (brightness < 0 && power == FB_BLANK_UNBLANK)
99 brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
100 else if (power != FB_BLANK_UNBLANK)
101 brightness = 0;
102
103 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
104 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
105 brightness ? contrast_ctr : 0);
106
107 bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
108
109 return 0;
110}
111
112static int atmel_bl_get_brightness(struct backlight_device *bl)
113{
114 struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
115
116 return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
117}
118
119static struct backlight_ops atmel_lcdc_bl_ops = {
120 .update_status = atmel_bl_update_status,
121 .get_brightness = atmel_bl_get_brightness,
122};
123
124static void init_backlight(struct atmel_lcdfb_info *sinfo)
125{
126 struct backlight_device *bl;
127
128 sinfo->bl_power = FB_BLANK_UNBLANK;
129
130 if (sinfo->backlight)
131 return;
132
133 bl = backlight_device_register("backlight", &sinfo->pdev->dev,
134 sinfo, &atmel_lcdc_bl_ops);
135 if (IS_ERR(sinfo->backlight)) {
136 dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
137 PTR_ERR(bl));
138 return;
139 }
140 sinfo->backlight = bl;
141
142 bl->props.power = FB_BLANK_UNBLANK;
143 bl->props.fb_blank = FB_BLANK_UNBLANK;
144 bl->props.max_brightness = 0xff;
145 bl->props.brightness = atmel_bl_get_brightness(bl);
146}
147
148static void exit_backlight(struct atmel_lcdfb_info *sinfo)
149{
150 if (sinfo->backlight)
151 backlight_device_unregister(sinfo->backlight);
152}
153
154#else
155
156static void init_backlight(struct atmel_lcdfb_info *sinfo)
157{
158 dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
159}
160
161static void exit_backlight(struct atmel_lcdfb_info *sinfo)
162{
163}
164
165#endif
166
167static void init_contrast(struct atmel_lcdfb_info *sinfo)
168{
169 /* have some default contrast/backlight settings */
170 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
171 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
172
173 if (sinfo->lcdcon_is_backlight)
174 init_backlight(sinfo);
175}
176
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177
178static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
179 .type = FB_TYPE_PACKED_PIXELS,
180 .visual = FB_VISUAL_TRUECOLOR,
181 .xpanstep = 0,
e730d8b0 182 .ypanstep = 1,
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183 .ywrapstep = 0,
184 .accel = FB_ACCEL_NONE,
185};
186
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187static unsigned long compute_hozval(unsigned long xres, unsigned long lcdcon2)
188{
189 unsigned long value;
190
191 if (!(cpu_is_at91sam9261() || cpu_is_at32ap7000()))
192 return xres;
193
194 value = xres;
195 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
196 /* STN display */
197 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
198 value *= 3;
199 }
200 if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
201 || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
202 && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
203 value = DIV_ROUND_UP(value, 4);
204 else
205 value = DIV_ROUND_UP(value, 8);
206 }
207
208 return value;
209}
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210
211static void atmel_lcdfb_update_dma(struct fb_info *info,
212 struct fb_var_screeninfo *var)
213{
214 struct atmel_lcdfb_info *sinfo = info->par;
215 struct fb_fix_screeninfo *fix = &info->fix;
216 unsigned long dma_addr;
217
218 dma_addr = (fix->smem_start + var->yoffset * fix->line_length
219 + var->xoffset * var->bits_per_pixel / 8);
220
221 dma_addr &= ~3UL;
222
223 /* Set framebuffer DMA base address and pixel offset */
224 lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
225
226 atmel_lcdfb_update_dma2d(sinfo, var);
227}
228
229static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
230{
231 struct fb_info *info = sinfo->info;
232
233 dma_free_writecombine(info->device, info->fix.smem_len,
234 info->screen_base, info->fix.smem_start);
235}
236
237/**
238 * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
239 * @sinfo: the frame buffer to allocate memory for
240 */
241static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
242{
243 struct fb_info *info = sinfo->info;
244 struct fb_var_screeninfo *var = &info->var;
ea757aca 245 unsigned int smem_len;
14340586 246
ea757aca
HS
247 smem_len = (var->xres_virtual * var->yres_virtual
248 * ((var->bits_per_pixel + 7) / 8));
249 info->fix.smem_len = max(smem_len, sinfo->smem_len);
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250
251 info->screen_base = dma_alloc_writecombine(info->device, info->fix.smem_len,
252 (dma_addr_t *)&info->fix.smem_start, GFP_KERNEL);
253
254 if (!info->screen_base) {
255 return -ENOMEM;
256 }
257
01d3a5e7
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258 memset(info->screen_base, 0, info->fix.smem_len);
259
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260 return 0;
261}
262
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263static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
264 struct fb_info *info)
265{
266 struct fb_videomode varfbmode;
267 const struct fb_videomode *fbmode = NULL;
268
269 fb_var_to_videomode(&varfbmode, var);
270 fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
271 if (fbmode)
272 fb_videomode_to_var(var, fbmode);
273 return fbmode;
274}
275
276
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277/**
278 * atmel_lcdfb_check_var - Validates a var passed in.
279 * @var: frame buffer variable screen structure
280 * @info: frame buffer structure that represents a single frame buffer
281 *
282 * Checks to see if the hardware supports the state requested by
283 * var passed in. This function does not alter the hardware
284 * state!!! This means the data stored in struct fb_info and
285 * struct atmel_lcdfb_info do not change. This includes the var
286 * inside of struct fb_info. Do NOT change these. This function
287 * can be called on its own if we intent to only test a mode and
288 * not actually set it. The stuff in modedb.c is a example of
289 * this. If the var passed in is slightly off by what the
290 * hardware can support then we alter the var PASSED in to what
291 * we can do. If the hardware doesn't support mode change a
292 * -EINVAL will be returned by the upper layers. You don't need
293 * to implement this function then. If you hardware doesn't
294 * support changing the resolution then this function is not
295 * needed. In this case the driver would just provide a var that
296 * represents the static state the screen is in.
297 *
298 * Returns negative errno on error, or zero on success.
299 */
300static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
301 struct fb_info *info)
302{
303 struct device *dev = info->device;
304 struct atmel_lcdfb_info *sinfo = info->par;
305 unsigned long clk_value_khz;
306
307 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
308
309 dev_dbg(dev, "%s:\n", __func__);
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310
311 if (!(var->pixclock && var->bits_per_pixel)) {
312 /* choose a suitable mode if possible */
313 if (!atmel_lcdfb_choose_mode(var, info)) {
314 dev_err(dev, "needed value not specified\n");
315 return -EINVAL;
316 }
317 }
318
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319 dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
320 dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
321 dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
322 dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
323
324 if ((PICOS2KHZ(var->pixclock) * var->bits_per_pixel / 8) > clk_value_khz) {
325 dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
326 return -EINVAL;
327 }
328
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NF
329 /* Do not allow to have real resoulution larger than virtual */
330 if (var->xres > var->xres_virtual)
331 var->xres_virtual = var->xres;
332
333 if (var->yres > var->yres_virtual)
334 var->yres_virtual = var->yres;
335
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336 /* Force same alignment for each line */
337 var->xres = (var->xres + 3) & ~3UL;
338 var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
339
340 var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
341 var->transp.msb_right = 0;
342 var->transp.offset = var->transp.length = 0;
343 var->xoffset = var->yoffset = 0;
344
162b3a08
HS
345 /* Saturate vertical and horizontal timings at maximum values */
346 var->vsync_len = min_t(u32, var->vsync_len,
347 (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
348 var->upper_margin = min_t(u32, var->upper_margin,
349 ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
350 var->lower_margin = min_t(u32, var->lower_margin,
351 ATMEL_LCDC_VFP);
352 var->right_margin = min_t(u32, var->right_margin,
353 (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
354 var->hsync_len = min_t(u32, var->hsync_len,
355 (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
356 var->left_margin = min_t(u32, var->left_margin,
357 ATMEL_LCDC_HBP + 1);
358
359 /* Some parameters can't be zero */
360 var->vsync_len = max_t(u32, var->vsync_len, 1);
361 var->right_margin = max_t(u32, var->right_margin, 1);
362 var->hsync_len = max_t(u32, var->hsync_len, 1);
363 var->left_margin = max_t(u32, var->left_margin, 1);
364
14340586 365 switch (var->bits_per_pixel) {
250a269d 366 case 1:
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367 case 2:
368 case 4:
369 case 8:
370 var->red.offset = var->green.offset = var->blue.offset = 0;
371 var->red.length = var->green.length = var->blue.length
372 = var->bits_per_pixel;
373 break;
374 case 15:
375 case 16:
fd085801
NF
376 if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
377 /* RGB:565 mode */
378 var->red.offset = 11;
379 var->blue.offset = 0;
380 var->green.length = 6;
fbd03a1c
GG
381 } else if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB555) {
382 var->red.offset = 10;
383 var->blue.offset = 0;
384 var->green.length = 5;
fd085801
NF
385 } else {
386 /* BGR:555 mode */
387 var->red.offset = 0;
388 var->blue.offset = 10;
389 var->green.length = 5;
390 }
14340586 391 var->green.offset = 5;
fd085801 392 var->red.length = var->blue.length = 5;
14340586 393 break;
14340586 394 case 32:
4440e0e1
HS
395 var->transp.offset = 24;
396 var->transp.length = 8;
397 /* fall through */
398 case 24:
fd085801
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399 if (sinfo->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
400 /* RGB:888 mode */
401 var->red.offset = 16;
402 var->blue.offset = 0;
403 } else {
404 /* BGR:888 mode */
405 var->red.offset = 0;
406 var->blue.offset = 16;
407 }
14340586 408 var->green.offset = 8;
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NF
409 var->red.length = var->green.length = var->blue.length = 8;
410 break;
411 default:
412 dev_err(dev, "color depth %d not supported\n",
413 var->bits_per_pixel);
414 return -EINVAL;
415 }
416
417 return 0;
418}
419
d22579b8
NF
420/*
421 * LCD reset sequence
422 */
423static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
424{
425 might_sleep();
426
427 /* LCD power off */
428 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
429
430 /* wait for the LCDC core to become idle */
431 while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
432 msleep(10);
433
434 /* DMA disable */
435 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
436
437 /* wait for DMA engine to become idle */
438 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
439 msleep(10);
440
441 /* LCD power on */
442 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
443 (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
444
445 /* DMA enable */
446 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
447}
448
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449/**
450 * atmel_lcdfb_set_par - Alters the hardware state.
451 * @info: frame buffer structure that represents a single frame buffer
452 *
453 * Using the fb_var_screeninfo in fb_info we set the resolution
454 * of the this particular framebuffer. This function alters the
455 * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
456 * not alter var in fb_info since we are using that data. This
457 * means we depend on the data in var inside fb_info to be
458 * supported by the hardware. atmel_lcdfb_check_var is always called
459 * before atmel_lcdfb_set_par to ensure this. Again if you can't
460 * change the resolution you don't need this function.
461 *
462 */
463static int atmel_lcdfb_set_par(struct fb_info *info)
464{
465 struct atmel_lcdfb_info *sinfo = info->par;
250a269d 466 unsigned long hozval_linesz;
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467 unsigned long value;
468 unsigned long clk_value_khz;
250a269d 469 unsigned long bits_per_line;
14340586 470
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NF
471 might_sleep();
472
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473 dev_dbg(info->device, "%s:\n", __func__);
474 dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
475 info->var.xres, info->var.yres,
476 info->var.xres_virtual, info->var.yres_virtual);
477
478 /* Turn off the LCD controller and the DMA controller */
479 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON, sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
480
e593f070
AS
481 /* Wait for the LCDC core to become idle */
482 while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
483 msleep(10);
484
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485 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
486
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NF
487 if (info->var.bits_per_pixel == 1)
488 info->fix.visual = FB_VISUAL_MONO01;
489 else if (info->var.bits_per_pixel <= 8)
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NF
490 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
491 else
492 info->fix.visual = FB_VISUAL_TRUECOLOR;
493
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NF
494 bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
495 info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
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496
497 /* Re-initialize the DMA engine... */
498 dev_dbg(info->device, " * update DMA engine\n");
499 atmel_lcdfb_update_dma(info, &info->var);
500
501 /* ...set frame size and burst length = 8 words (?) */
502 value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
503 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
504 lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
505
506 /* Now, the LCDC core... */
507
508 /* Set pixel clock */
509 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
510
250a269d 511 value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
14340586 512
baf6332a 513 if (value < 2) {
14340586
NF
514 dev_notice(info->device, "Bypassing pixel clock divider\n");
515 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
250a269d 516 } else {
baf6332a
NF
517 value = (value / 2) - 1;
518 dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n",
519 value);
520 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
521 value << ATMEL_LCDC_CLKVAL_OFFSET);
250a269d
NF
522 info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1)));
523 dev_dbg(info->device, " updated pixclk: %lu KHz\n",
524 PICOS2KHZ(info->var.pixclock));
525 }
526
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527
528 /* Initialize control register 2 */
529 value = sinfo->default_lcdcon2;
530
531 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
532 value |= ATMEL_LCDC_INVLINE_INVERTED;
533 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
534 value |= ATMEL_LCDC_INVFRAME_INVERTED;
535
536 switch (info->var.bits_per_pixel) {
537 case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
538 case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
539 case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
540 case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
541 case 15: /* fall through */
542 case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
543 case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
544 case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
545 default: BUG(); break;
546 }
547 dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
548 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
549
550 /* Vertical timing */
551 value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
552 value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
553 value |= info->var.lower_margin;
554 dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
555 lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
556
557 /* Horizontal timing */
558 value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
559 value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
560 value |= (info->var.left_margin - 1);
561 dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
562 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
563
250a269d
NF
564 /* Horizontal value (aka line size) */
565 hozval_linesz = compute_hozval(info->var.xres,
566 lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2));
567
14340586 568 /* Display size */
250a269d 569 value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
14340586 570 value |= info->var.yres - 1;
250a269d 571 dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
14340586
NF
572 lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
573
574 /* FIFO Threshold: Use formula from data sheet */
575 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
576 lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
577
578 /* Toggle LCD_MODE every frame */
579 lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
580
581 /* Disable all interrupts */
582 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
d22579b8
NF
583 /* Enable FIFO & DMA errors */
584 lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
14340586 585
14340586
NF
586 /* ...wait for DMA engine to become idle... */
587 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
588 msleep(10);
589
590 dev_dbg(info->device, " * re-enable DMA engine\n");
591 /* ...and enable it with updated configuration */
592 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, sinfo->default_dmacon);
593
594 dev_dbg(info->device, " * re-enable LCDC core\n");
595 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
596 (sinfo->guard_time << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
597
598 dev_dbg(info->device, " * DONE\n");
599
600 return 0;
601}
602
603static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
604{
605 chan &= 0xffff;
606 chan >>= 16 - bf->length;
607 return chan << bf->offset;
608}
609
610/**
611 * atmel_lcdfb_setcolreg - Optional function. Sets a color register.
612 * @regno: Which register in the CLUT we are programming
613 * @red: The red value which can be up to 16 bits wide
614 * @green: The green value which can be up to 16 bits wide
615 * @blue: The blue value which can be up to 16 bits wide.
616 * @transp: If supported the alpha value which can be up to 16 bits wide.
617 * @info: frame buffer info structure
618 *
619 * Set a single color register. The values supplied have a 16 bit
620 * magnitude which needs to be scaled in this function for the hardware.
621 * Things to take into consideration are how many color registers, if
622 * any, are supported with the current color visual. With truecolor mode
623 * no color palettes are supported. Here a psuedo palette is created
624 * which we store the value in pseudo_palette in struct fb_info. For
625 * pseudocolor mode we have a limited color palette. To deal with this
626 * we can program what color is displayed for a particular pixel value.
627 * DirectColor is similar in that we can program each color field. If
628 * we have a static colormap we don't need to implement this function.
629 *
630 * Returns negative errno on error, or zero on success. In an
631 * ideal world, this would have been the case, but as it turns
632 * out, the other drivers return 1 on failure, so that's what
633 * we're going to do.
634 */
635static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
636 unsigned int green, unsigned int blue,
637 unsigned int transp, struct fb_info *info)
638{
639 struct atmel_lcdfb_info *sinfo = info->par;
640 unsigned int val;
641 u32 *pal;
642 int ret = 1;
643
644 if (info->var.grayscale)
645 red = green = blue = (19595 * red + 38470 * green
646 + 7471 * blue) >> 16;
647
648 switch (info->fix.visual) {
649 case FB_VISUAL_TRUECOLOR:
650 if (regno < 16) {
651 pal = info->pseudo_palette;
652
653 val = chan_to_field(red, &info->var.red);
654 val |= chan_to_field(green, &info->var.green);
655 val |= chan_to_field(blue, &info->var.blue);
656
657 pal[regno] = val;
658 ret = 0;
659 }
660 break;
661
662 case FB_VISUAL_PSEUDOCOLOR:
663 if (regno < 256) {
664 val = ((red >> 11) & 0x001f);
665 val |= ((green >> 6) & 0x03e0);
666 val |= ((blue >> 1) & 0x7c00);
667
668 /*
669 * TODO: intensity bit. Maybe something like
670 * ~(red[10] ^ green[10] ^ blue[10]) & 1
671 */
672
673 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
674 ret = 0;
675 }
676 break;
250a269d
NF
677
678 case FB_VISUAL_MONO01:
679 if (regno < 2) {
680 val = (regno == 0) ? 0x00 : 0x1F;
681 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
682 ret = 0;
683 }
684 break;
685
14340586
NF
686 }
687
688 return ret;
689}
690
691static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
692 struct fb_info *info)
693{
694 dev_dbg(info->device, "%s\n", __func__);
695
696 atmel_lcdfb_update_dma(info, var);
697
698 return 0;
699}
700
701static struct fb_ops atmel_lcdfb_ops = {
702 .owner = THIS_MODULE,
703 .fb_check_var = atmel_lcdfb_check_var,
704 .fb_set_par = atmel_lcdfb_set_par,
705 .fb_setcolreg = atmel_lcdfb_setcolreg,
706 .fb_pan_display = atmel_lcdfb_pan_display,
707 .fb_fillrect = cfb_fillrect,
708 .fb_copyarea = cfb_copyarea,
709 .fb_imageblit = cfb_imageblit,
710};
711
712static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
713{
714 struct fb_info *info = dev_id;
715 struct atmel_lcdfb_info *sinfo = info->par;
716 u32 status;
717
718 status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
d22579b8
NF
719 if (status & ATMEL_LCDC_UFLWI) {
720 dev_warn(info->device, "FIFO underflow %#x\n", status);
721 /* reset DMA and FIFO to avoid screen shifting */
722 schedule_work(&sinfo->task);
723 }
724 lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
14340586
NF
725 return IRQ_HANDLED;
726}
727
d22579b8
NF
728/*
729 * LCD controller task (to reset the LCD)
730 */
731static void atmel_lcdfb_task(struct work_struct *work)
732{
733 struct atmel_lcdfb_info *sinfo =
734 container_of(work, struct atmel_lcdfb_info, task);
735
736 atmel_lcdfb_reset(sinfo);
737}
738
14340586
NF
739static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
740{
741 struct fb_info *info = sinfo->info;
742 int ret = 0;
743
14340586
NF
744 info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
745
746 dev_info(info->device,
747 "%luKiB frame buffer at %08lx (mapped at %p)\n",
748 (unsigned long)info->fix.smem_len / 1024,
749 (unsigned long)info->fix.smem_start,
750 info->screen_base);
751
752 /* Allocate colormap */
753 ret = fb_alloc_cmap(&info->cmap, 256, 0);
754 if (ret < 0)
755 dev_err(info->device, "Alloc color map failed\n");
756
757 return ret;
758}
759
760static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
761{
762 if (sinfo->bus_clk)
763 clk_enable(sinfo->bus_clk);
764 clk_enable(sinfo->lcdc_clk);
765}
766
767static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
768{
769 if (sinfo->bus_clk)
770 clk_disable(sinfo->bus_clk);
771 clk_disable(sinfo->lcdc_clk);
772}
773
774
775static int __init atmel_lcdfb_probe(struct platform_device *pdev)
776{
777 struct device *dev = &pdev->dev;
778 struct fb_info *info;
779 struct atmel_lcdfb_info *sinfo;
780 struct atmel_lcdfb_info *pdata_sinfo;
968910bd 781 struct fb_videomode fbmode;
14340586
NF
782 struct resource *regs = NULL;
783 struct resource *map = NULL;
784 int ret;
785
786 dev_dbg(dev, "%s BEGIN\n", __func__);
787
788 ret = -ENOMEM;
789 info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
790 if (!info) {
791 dev_err(dev, "cannot allocate memory\n");
792 goto out;
793 }
794
795 sinfo = info->par;
796
797 if (dev->platform_data) {
798 pdata_sinfo = (struct atmel_lcdfb_info *)dev->platform_data;
799 sinfo->default_bpp = pdata_sinfo->default_bpp;
800 sinfo->default_dmacon = pdata_sinfo->default_dmacon;
801 sinfo->default_lcdcon2 = pdata_sinfo->default_lcdcon2;
802 sinfo->default_monspecs = pdata_sinfo->default_monspecs;
803 sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
804 sinfo->guard_time = pdata_sinfo->guard_time;
ea757aca 805 sinfo->smem_len = pdata_sinfo->smem_len;
a9a84c37 806 sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
fd085801 807 sinfo->lcd_wiring_mode = pdata_sinfo->lcd_wiring_mode;
14340586
NF
808 } else {
809 dev_err(dev, "cannot get default configuration\n");
810 goto free_info;
811 }
812 sinfo->info = info;
813 sinfo->pdev = pdev;
814
815 strcpy(info->fix.id, sinfo->pdev->name);
816 info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
817 info->pseudo_palette = sinfo->pseudo_palette;
818 info->fbops = &atmel_lcdfb_ops;
819
820 memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
821 info->fix = atmel_lcdfb_fix;
822
823 /* Enable LCDC Clocks */
824 if (cpu_is_at91sam9261() || cpu_is_at32ap7000()) {
825 sinfo->bus_clk = clk_get(dev, "hck1");
826 if (IS_ERR(sinfo->bus_clk)) {
827 ret = PTR_ERR(sinfo->bus_clk);
828 goto free_info;
829 }
830 }
831 sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
832 if (IS_ERR(sinfo->lcdc_clk)) {
833 ret = PTR_ERR(sinfo->lcdc_clk);
834 goto put_bus_clk;
835 }
836 atmel_lcdfb_start_clock(sinfo);
837
838 ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
839 info->monspecs.modedb_len, info->monspecs.modedb,
840 sinfo->default_bpp);
841 if (!ret) {
842 dev_err(dev, "no suitable video mode found\n");
843 goto stop_clk;
844 }
845
846
847 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
848 if (!regs) {
849 dev_err(dev, "resources unusable\n");
850 ret = -ENXIO;
851 goto stop_clk;
852 }
853
854 sinfo->irq_base = platform_get_irq(pdev, 0);
855 if (sinfo->irq_base < 0) {
856 dev_err(dev, "unable to get irq\n");
857 ret = sinfo->irq_base;
858 goto stop_clk;
859 }
860
861 /* Initialize video memory */
862 map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
863 if (map) {
864 /* use a pre-allocated memory buffer */
865 info->fix.smem_start = map->start;
866 info->fix.smem_len = map->end - map->start + 1;
867 if (!request_mem_region(info->fix.smem_start,
868 info->fix.smem_len, pdev->name)) {
869 ret = -EBUSY;
870 goto stop_clk;
871 }
872
873 info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
874 if (!info->screen_base)
875 goto release_intmem;
01d3a5e7
HS
876
877 /*
878 * Don't clear the framebuffer -- someone may have set
879 * up a splash image.
880 */
14340586
NF
881 } else {
882 /* alocate memory buffer */
883 ret = atmel_lcdfb_alloc_video_memory(sinfo);
884 if (ret < 0) {
885 dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
886 goto stop_clk;
887 }
888 }
889
890 /* LCDC registers */
891 info->fix.mmio_start = regs->start;
892 info->fix.mmio_len = regs->end - regs->start + 1;
893
894 if (!request_mem_region(info->fix.mmio_start,
895 info->fix.mmio_len, pdev->name)) {
896 ret = -EBUSY;
897 goto free_fb;
898 }
899
900 sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
901 if (!sinfo->mmio) {
902 dev_err(dev, "cannot map LCDC registers\n");
903 goto release_mem;
904 }
905
a9a84c37
DB
906 /* Initialize PWM for contrast or backlight ("off") */
907 init_contrast(sinfo);
908
14340586
NF
909 /* interrupt */
910 ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
911 if (ret) {
912 dev_err(dev, "request_irq failed: %d\n", ret);
913 goto unmap_mmio;
914 }
915
d22579b8
NF
916 /* Some operations on the LCDC might sleep and
917 * require a preemptible task context */
918 INIT_WORK(&sinfo->task, atmel_lcdfb_task);
919
14340586
NF
920 ret = atmel_lcdfb_init_fbinfo(sinfo);
921 if (ret < 0) {
922 dev_err(dev, "init fbinfo failed: %d\n", ret);
923 goto unregister_irqs;
924 }
925
926 /*
927 * This makes sure that our colour bitfield
928 * descriptors are correctly initialised.
929 */
930 atmel_lcdfb_check_var(&info->var, info);
931
932 ret = fb_set_var(info, &info->var);
933 if (ret) {
934 dev_warn(dev, "unable to set display parameters\n");
935 goto free_cmap;
936 }
937
938 dev_set_drvdata(dev, info);
939
940 /*
941 * Tell the world that we're ready to go
942 */
943 ret = register_framebuffer(info);
944 if (ret < 0) {
945 dev_err(dev, "failed to register framebuffer device: %d\n", ret);
34a35bdd 946 goto reset_drvdata;
14340586
NF
947 }
948
968910bd
NF
949 /* add selected videomode to modelist */
950 fb_var_to_videomode(&fbmode, &info->var);
951 fb_add_videomode(&fbmode, &info->modelist);
952
14340586
NF
953 /* Power up the LCDC screen */
954 if (sinfo->atmel_lcdfb_power_control)
955 sinfo->atmel_lcdfb_power_control(1);
956
957 dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %lu\n",
958 info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
959
960 return 0;
961
34a35bdd
SG
962reset_drvdata:
963 dev_set_drvdata(dev, NULL);
14340586
NF
964free_cmap:
965 fb_dealloc_cmap(&info->cmap);
966unregister_irqs:
d22579b8 967 cancel_work_sync(&sinfo->task);
14340586
NF
968 free_irq(sinfo->irq_base, info);
969unmap_mmio:
a9a84c37 970 exit_backlight(sinfo);
14340586
NF
971 iounmap(sinfo->mmio);
972release_mem:
973 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
974free_fb:
975 if (map)
976 iounmap(info->screen_base);
977 else
978 atmel_lcdfb_free_video_memory(sinfo);
979
980release_intmem:
981 if (map)
982 release_mem_region(info->fix.smem_start, info->fix.smem_len);
983stop_clk:
984 atmel_lcdfb_stop_clock(sinfo);
985 clk_put(sinfo->lcdc_clk);
986put_bus_clk:
987 if (sinfo->bus_clk)
988 clk_put(sinfo->bus_clk);
989free_info:
990 framebuffer_release(info);
991out:
992 dev_dbg(dev, "%s FAILED\n", __func__);
993 return ret;
994}
995
996static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
997{
998 struct device *dev = &pdev->dev;
999 struct fb_info *info = dev_get_drvdata(dev);
34a35bdd 1000 struct atmel_lcdfb_info *sinfo;
14340586 1001
34a35bdd 1002 if (!info || !info->par)
14340586 1003 return 0;
34a35bdd 1004 sinfo = info->par;
14340586 1005
d22579b8 1006 cancel_work_sync(&sinfo->task);
a9a84c37 1007 exit_backlight(sinfo);
14340586
NF
1008 if (sinfo->atmel_lcdfb_power_control)
1009 sinfo->atmel_lcdfb_power_control(0);
1010 unregister_framebuffer(info);
1011 atmel_lcdfb_stop_clock(sinfo);
1012 clk_put(sinfo->lcdc_clk);
1013 if (sinfo->bus_clk)
1014 clk_put(sinfo->bus_clk);
1015 fb_dealloc_cmap(&info->cmap);
1016 free_irq(sinfo->irq_base, info);
1017 iounmap(sinfo->mmio);
1018 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1019 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
1020 iounmap(info->screen_base);
1021 release_mem_region(info->fix.smem_start, info->fix.smem_len);
1022 } else {
1023 atmel_lcdfb_free_video_memory(sinfo);
1024 }
1025
1026 dev_set_drvdata(dev, NULL);
1027 framebuffer_release(info);
1028
1029 return 0;
1030}
1031
cf19a37e
DB
1032#ifdef CONFIG_PM
1033
1034static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
1035{
1036 struct fb_info *info = platform_get_drvdata(pdev);
1037 struct atmel_lcdfb_info *sinfo = info->par;
1038
1039 sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
1040 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
1041 if (sinfo->atmel_lcdfb_power_control)
1042 sinfo->atmel_lcdfb_power_control(0);
1043 atmel_lcdfb_stop_clock(sinfo);
1044 return 0;
1045}
1046
1047static int atmel_lcdfb_resume(struct platform_device *pdev)
1048{
1049 struct fb_info *info = platform_get_drvdata(pdev);
1050 struct atmel_lcdfb_info *sinfo = info->par;
1051
1052 atmel_lcdfb_start_clock(sinfo);
1053 if (sinfo->atmel_lcdfb_power_control)
1054 sinfo->atmel_lcdfb_power_control(1);
1055 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
1056 return 0;
1057}
1058
1059#else
1060#define atmel_lcdfb_suspend NULL
1061#define atmel_lcdfb_resume NULL
1062#endif
1063
14340586
NF
1064static struct platform_driver atmel_lcdfb_driver = {
1065 .remove = __exit_p(atmel_lcdfb_remove),
cf19a37e
DB
1066 .suspend = atmel_lcdfb_suspend,
1067 .resume = atmel_lcdfb_resume,
a9a84c37 1068
14340586
NF
1069 .driver = {
1070 .name = "atmel_lcdfb",
1071 .owner = THIS_MODULE,
1072 },
1073};
1074
1075static int __init atmel_lcdfb_init(void)
1076{
1077 return platform_driver_probe(&atmel_lcdfb_driver, atmel_lcdfb_probe);
1078}
1079
1080static void __exit atmel_lcdfb_exit(void)
1081{
1082 platform_driver_unregister(&atmel_lcdfb_driver);
1083}
1084
1085module_init(atmel_lcdfb_init);
1086module_exit(atmel_lcdfb_exit);
1087
1088MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
8f4c79ce 1089MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
14340586 1090MODULE_LICENSE("GPL");
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