[deliverable/linux.git] / drivers / video / aty / radeonfb.h

#ifndef __RADEONFB_H__
#define __RADEONFB_H__

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/fb.h>


#ifdef CONFIG_FB_RADEON_I2C
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#endif

#include <asm/io.h>

#ifdef CONFIG_PPC_OF
#include <asm/prom.h>
#endif

#include <video/radeon.h>

/***************************************************************
 * Most of the definitions here are adapted right from XFree86 *
 ***************************************************************/


/*
 * Chip families. Must fit in the low 16 bits of a long word
 */
enum radeon_family {
	CHIP_FAMILY_UNKNOW,
	CHIP_FAMILY_LEGACY,
	CHIP_FAMILY_RADEON,
	CHIP_FAMILY_RV100,
	CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
	CHIP_FAMILY_RV200,
	CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
				 RS250 (IGP 7000) */
	CHIP_FAMILY_R200,
	CHIP_FAMILY_RV250,
	CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
	CHIP_FAMILY_RV280,
	CHIP_FAMILY_R300,
	CHIP_FAMILY_R350,
	CHIP_FAMILY_RV350,
	CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
	CHIP_FAMILY_R420,     /* R420/R423/M18 */
	CHIP_FAMILY_LAST,
};

#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
				 ((rinfo)->family == CHIP_FAMILY_RV200)  || \
				 ((rinfo)->family == CHIP_FAMILY_RS100)  || \
				 ((rinfo)->family == CHIP_FAMILY_RS200)  || \
				 ((rinfo)->family == CHIP_FAMILY_RV250)  || \
				 ((rinfo)->family == CHIP_FAMILY_RV280)  || \
				 ((rinfo)->family == CHIP_FAMILY_RS300))


#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
				((rinfo)->family == CHIP_FAMILY_RV350) || \
				((rinfo)->family == CHIP_FAMILY_R350)  || \
				((rinfo)->family == CHIP_FAMILY_RV380) || \
				((rinfo)->family == CHIP_FAMILY_R420))

/*
 * Chip flags
 */
enum radeon_chip_flags {
	CHIP_FAMILY_MASK	= 0x0000ffffUL,
	CHIP_FLAGS_MASK		= 0xffff0000UL,
	CHIP_IS_MOBILITY	= 0x00010000UL,
	CHIP_IS_IGP		= 0x00020000UL,
	CHIP_HAS_CRTC2		= 0x00040000UL,	
};

/*
 * Errata workarounds
 */
enum radeon_errata {
	CHIP_ERRATA_R300_CG		= 0x00000001,
	CHIP_ERRATA_PLL_DUMMYREADS	= 0x00000002,
	CHIP_ERRATA_PLL_DELAY		= 0x00000004,
};


/*
 * Monitor types
 */
enum radeon_montype {
	MT_NONE = 0,
	MT_CRT,		/* CRT */
	MT_LCD,		/* LCD */
	MT_DFP,		/* DVI */
	MT_CTV,		/* composite TV */
	MT_STV		/* S-Video out */
};

/*
 * DDC i2c ports
 */
enum ddc_type {
	ddc_none,
	ddc_monid,
	ddc_dvi,
	ddc_vga,
	ddc_crt2,
};

/*
 * Connector types
 */
enum conn_type {
	conn_none,
	conn_proprietary,
	conn_crt,
	conn_DVI_I,
	conn_DVI_D,
};


/*
 * PLL infos
 */
struct pll_info {
	int ppll_max;
	int ppll_min;
	int sclk, mclk;
	int ref_div;
	int ref_clk;
};


/*
 * This structure contains the various registers manipulated by this
 * driver for setting or restoring a mode. It's mostly copied from
 * XFree's RADEONSaveRec structure. A few chip settings might still be
 * tweaked without beeing reflected or saved in these registers though
 */
struct radeon_regs {
	/* Common registers */
	u32		ovr_clr;
	u32		ovr_wid_left_right;
	u32		ovr_wid_top_bottom;
	u32		ov0_scale_cntl;
	u32		mpp_tb_config;
	u32		mpp_gp_config;
	u32		subpic_cntl;
	u32		viph_control;
	u32		i2c_cntl_1;
	u32		gen_int_cntl;
	u32		cap0_trig_cntl;
	u32		cap1_trig_cntl;
	u32		bus_cntl;
	u32		surface_cntl;
	u32		bios_5_scratch;

	/* Other registers to save for VT switches or driver load/unload */
	u32		dp_datatype;
	u32		rbbm_soft_reset;
	u32		clock_cntl_index;
	u32		amcgpio_en_reg;
	u32		amcgpio_mask;

	/* Surface/tiling registers */
	u32		surf_lower_bound[8];
	u32		surf_upper_bound[8];
	u32		surf_info[8];

	/* CRTC registers */
	u32		crtc_gen_cntl;
	u32		crtc_ext_cntl;
	u32		dac_cntl;
	u32		crtc_h_total_disp;
	u32		crtc_h_sync_strt_wid;
	u32		crtc_v_total_disp;
	u32		crtc_v_sync_strt_wid;
	u32		crtc_offset;
	u32		crtc_offset_cntl;
	u32		crtc_pitch;
	u32		disp_merge_cntl;
	u32		grph_buffer_cntl;
	u32		crtc_more_cntl;

	/* CRTC2 registers */
	u32		crtc2_gen_cntl;
	u32		dac2_cntl;
	u32		disp_output_cntl;
	u32		disp_hw_debug;
	u32		disp2_merge_cntl;
	u32		grph2_buffer_cntl;
	u32		crtc2_h_total_disp;
	u32		crtc2_h_sync_strt_wid;
	u32		crtc2_v_total_disp;
	u32		crtc2_v_sync_strt_wid;
	u32		crtc2_offset;
	u32		crtc2_offset_cntl;
	u32		crtc2_pitch;

	/* Flat panel regs */
	u32 		fp_crtc_h_total_disp;
	u32		fp_crtc_v_total_disp;
	u32		fp_gen_cntl;
	u32		fp2_gen_cntl;
	u32		fp_h_sync_strt_wid;
	u32		fp2_h_sync_strt_wid;
	u32		fp_horz_stretch;
	u32		fp_panel_cntl;
	u32		fp_v_sync_strt_wid;
	u32		fp2_v_sync_strt_wid;
	u32		fp_vert_stretch;
	u32		lvds_gen_cntl;
	u32		lvds_pll_cntl;
	u32		tmds_crc;
	u32		tmds_transmitter_cntl;

	/* Computed values for PLL */
	u32		dot_clock_freq;
	int		feedback_div;
	int		post_div;	

	/* PLL registers */
	u32		ppll_div_3;
	u32		ppll_ref_div;
	u32		vclk_ecp_cntl;
	u32		clk_cntl_index;

	/* Computed values for PLL2 */
	u32		dot_clock_freq_2;
	int		feedback_div_2;
	int		post_div_2;

	/* PLL2 registers */
	u32		p2pll_ref_div;
	u32		p2pll_div_0;
	u32		htotal_cntl2;

       	/* Palette */
	int		palette_valid;
};

struct panel_info {
	int xres, yres;
	int valid;
	int clock;
	int hOver_plus, hSync_width, hblank;
	int vOver_plus, vSync_width, vblank;
	int hAct_high, vAct_high, interlaced;
	int pwr_delay;
	int use_bios_dividers;
	int ref_divider;
	int post_divider;
	int fbk_divider;
};

struct radeonfb_info;

#ifdef CONFIG_FB_RADEON_I2C
struct radeon_i2c_chan {
	struct radeonfb_info		*rinfo;
	u32		 		ddc_reg;
	struct i2c_adapter		adapter;
	struct i2c_algo_bit_data	algo;
};
#endif

enum radeon_pm_mode {
	radeon_pm_none	= 0,		/* Nothing supported */
	radeon_pm_d2	= 0x00000001,	/* Can do D2 state */
	radeon_pm_off	= 0x00000002,	/* Can resume from D3 cold */
};

typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);

struct radeonfb_info {
	struct fb_info		*info;

	struct radeon_regs 	state;
	struct radeon_regs	init_state;

	char			name[DEVICE_NAME_SIZE];

	unsigned long		mmio_base_phys;
	unsigned long		fb_base_phys;

	void __iomem		*mmio_base;
	void __iomem		*fb_base;

	unsigned long		fb_local_base;

	struct pci_dev		*pdev;
#ifdef CONFIG_PPC_OF
	struct device_node	*of_node;
#endif

	void __iomem		*bios_seg;
	int			fp_bios_start;

	u32			pseudo_palette[17];
	struct { u8 red, green, blue, pad; }
				palette[256];

	int			chipset;
	u8			family;
	u8			rev;
	unsigned int		errata;
	unsigned long		video_ram;
	unsigned long		mapped_vram;
	int			vram_width;
	int			vram_ddr;

	int			pitch, bpp, depth;

	int			has_CRTC2;
	int			is_mobility;
	int			is_IGP;
	int			reversed_DAC;
	int			reversed_TMDS;
	struct panel_info	panel_info;
	int			mon1_type;
	u8			*mon1_EDID;
	struct fb_videomode	*mon1_modedb;
	int			mon1_dbsize;
	int			mon2_type;
	u8		        *mon2_EDID;

	u32			dp_gui_master_cntl;

	struct pll_info		pll;

	int			mtrr_hdl;

	int			pm_reg;
	u32			save_regs[100];
	int			asleep;
	int			lock_blank;
	int			dynclk;
	int			no_schedule;
	enum radeon_pm_mode	pm_mode;
	reinit_function_ptr     reinit_func;

	/* Lock on register access */
	spinlock_t		reg_lock;

	/* Timer used for delayed LVDS operations */
	struct timer_list	lvds_timer;
	u32			pending_lvds_gen_cntl;

#ifdef CONFIG_FB_RADEON_I2C
	struct radeon_i2c_chan 	i2c[4];
#endif

	u32			cfg_save[64];
};


#define PRIMARY_MONITOR(rinfo)	(rinfo->mon1_type)


/*
 * Debugging stuffs
 */
#ifdef CONFIG_FB_RADEON_DEBUG
#define DEBUG		1
#else
#define DEBUG		0
#endif

#if DEBUG
#define RTRACE		printk
#else
#define RTRACE		if(0) printk
#endif


/*
 * IO macros
 */

/* Note about this function: we have some rare cases where we must not schedule,
 * this typically happen with our special "wake up early" hook which allows us to
 * wake up the graphic chip (and thus get the console back) before everything else
 * on some machines that support that mechanism. At this point, interrupts are off
 * and scheduling is not permitted
 */
static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
{
	if (rinfo->no_schedule || oops_in_progress)
		mdelay(ms);
	else
		msleep(ms);
}


#define INREG8(addr)		readb((rinfo->mmio_base)+addr)
#define OUTREG8(addr,val)	writeb(val, (rinfo->mmio_base)+addr)
#define INREG16(addr)		readw((rinfo->mmio_base)+addr)
#define OUTREG16(addr,val)	writew(val, (rinfo->mmio_base)+addr)
#define INREG(addr)		readl((rinfo->mmio_base)+addr)
#define OUTREG(addr,val)	writel(val, (rinfo->mmio_base)+addr)

static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
		       u32 val, u32 mask)
{
	unsigned long flags;
	unsigned int tmp;

	spin_lock_irqsave(&rinfo->reg_lock, flags);
	tmp = INREG(addr);
	tmp &= (mask);
	tmp |= (val);
	OUTREG(addr, tmp);
	spin_unlock_irqrestore(&rinfo->reg_lock, flags);
}

#define OUTREGP(addr,val,mask)	_OUTREGP(rinfo, addr, val,mask)

/*
 * Note about PLL register accesses:
 *
 * I have removed the spinlock on them on purpose. The driver now
 * expects that it will only manipulate the PLL registers in normal
 * task environment, where radeon_msleep() will be called, protected
 * by a semaphore (currently the console semaphore) so that no conflict
 * will happen on the PLL register index.
 *
 * With the latest changes to the VT layer, this is guaranteed for all
 * calls except the actual drawing/blits which aren't supposed to use
 * the PLL registers anyway
 *
 * This is very important for the workarounds to work properly. The only
 * possible exception to this rule is the call to unblank(), which may
 * be done at irq time if an oops is in progress.
 */
static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
{
	if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
		return;

	(void)INREG(CLOCK_CNTL_DATA);
	(void)INREG(CRTC_GEN_CNTL);
}

static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
{
	if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
		/* we can't deal with posted writes here ... */
		_radeon_msleep(rinfo, 5);
	}
	if (rinfo->errata & CHIP_ERRATA_R300_CG) {
		u32 save, tmp;
		save = INREG(CLOCK_CNTL_INDEX);
		tmp = save & ~(0x3f | PLL_WR_EN);
		OUTREG(CLOCK_CNTL_INDEX, tmp);
		tmp = INREG(CLOCK_CNTL_DATA);
		OUTREG(CLOCK_CNTL_INDEX, save);
	}
}

static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
{
	u32 data;

	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
	radeon_pll_errata_after_index(rinfo);
	data = INREG(CLOCK_CNTL_DATA);
	radeon_pll_errata_after_data(rinfo);
	return data;
}

static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
			    u32 val)
{

	OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
	radeon_pll_errata_after_index(rinfo);
	OUTREG(CLOCK_CNTL_DATA, val);
	radeon_pll_errata_after_data(rinfo);
}


static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
			     u32 val, u32 mask)
{
	unsigned int tmp;

	tmp  = __INPLL(rinfo, index);
	tmp &= (mask);
	tmp |= (val);
	__OUTPLL(rinfo, index, tmp);
}


#define INPLL(addr)			__INPLL(rinfo, addr)
#define OUTPLL(index, val)		__OUTPLL(rinfo, index, val)
#define OUTPLLP(index, val, mask)	__OUTPLLP(rinfo, index, val, mask)


#define BIOS_IN8(v)  	(readb(rinfo->bios_seg + (v)))
#define BIOS_IN16(v) 	(readb(rinfo->bios_seg + (v)) | \
			  (readb(rinfo->bios_seg + (v) + 1) << 8))
#define BIOS_IN32(v) 	(readb(rinfo->bios_seg + (v)) | \
			  (readb(rinfo->bios_seg + (v) + 1) << 8) | \
			  (readb(rinfo->bios_seg + (v) + 2) << 16) | \
			  (readb(rinfo->bios_seg + (v) + 3) << 24))

/*
 * Inline utilities
 */
static inline int round_div(int num, int den)
{
        return (num + (den / 2)) / den;
}

static inline int var_to_depth(const struct fb_var_screeninfo *var)
{
	if (var->bits_per_pixel != 16)
		return var->bits_per_pixel;
	return (var->green.length == 5) ? 15 : 16;
}

static inline u32 radeon_get_dstbpp(u16 depth)
{
	switch (depth) {
       	case 8:
       		return DST_8BPP;
       	case 15:
       		return DST_15BPP;
       	case 16:
       		return DST_16BPP;
       	case 32:
       		return DST_32BPP;
       	default:
       		return 0;
	}
}

/*
 * 2D Engine helper routines
 */
static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
{
	int i;

	/* initiate flush */
	OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
	        ~RB2D_DC_FLUSH_ALL);

	for (i=0; i < 2000000; i++) {
		if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
			return;
		udelay(1);
	}
	printk(KERN_ERR "radeonfb: Flush Timeout !\n");
}


static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{
	int i;

	for (i=0; i<2000000; i++) {
		if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
			return;
		udelay(1);
	}
	printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
}


static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
{
	int i;

	/* ensure FIFO is empty before waiting for idle */
	_radeon_fifo_wait (rinfo, 64);

	for (i=0; i<2000000; i++) {
		if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
			radeon_engine_flush (rinfo);
			return;
		}
		udelay(1);
	}
	printk(KERN_ERR "radeonfb: Idle Timeout !\n");
}


#define radeon_engine_idle()		_radeon_engine_idle(rinfo)
#define radeon_fifo_wait(entries)	_radeon_fifo_wait(rinfo,entries)
#define radeon_msleep(ms)		_radeon_msleep(rinfo,ms)


/* I2C Functions */
extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);

/* PM Functions */
extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
extern int radeonfb_pci_resume(struct pci_dev *pdev);
extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);

/* Monitor probe functions */
extern void radeon_probe_screens(struct radeonfb_info *rinfo,
				 const char *monitor_layout, int ignore_edid);
extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
extern int radeon_match_mode(struct radeonfb_info *rinfo,
			     struct fb_var_screeninfo *dest,
			     const struct fb_var_screeninfo *src);

/* Accel functions */
extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
extern int radeonfb_sync(struct fb_info *info);
extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);

/* Other functions */
extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
			       int reg_only);

/* Backlight functions */
#ifdef CONFIG_FB_RADEON_BACKLIGHT
extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
#else
static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
#endif

#endif /* __RADEONFB_H__ */
Commit	Line	Data
1da177e4 LT	1	#ifndef __RADEONFB_H__
	2	#define __RADEONFB_H__
	3
1da177e4 LT	4	#include <linux/module.h>
	5	#include <linux/kernel.h>
	6	#include <linux/sched.h>
	7	#include <linux/delay.h>
	8	#include <linux/pci.h>
	9	#include <linux/fb.h>
	10
	11
e764a201	12	#ifdef CONFIG_FB_RADEON_I2C
1da177e4	13	#include <linux/i2c.h>
1da177e4	14	#include <linux/i2c-algo-bit.h>
e764a201	15	#endif
1da177e4 LT	16
	17	#include <asm/io.h>
	18
	19	#ifdef CONFIG_PPC_OF
	20	#include <asm/prom.h>
	21	#endif
	22
	23	#include <video/radeon.h>
	24
	25	/***************************************************************
	26	* Most of the definitions here are adapted right from XFree86 *
	27	***************************************************************/
	28
	29
	30	/*
	31	* Chip families. Must fit in the low 16 bits of a long word
	32	*/
	33	enum radeon_family {
	34	CHIP_FAMILY_UNKNOW,
	35	CHIP_FAMILY_LEGACY,
	36	CHIP_FAMILY_RADEON,
	37	CHIP_FAMILY_RV100,
	38	CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
	39	CHIP_FAMILY_RV200,
	40	CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
	41	RS250 (IGP 7000) */
	42	CHIP_FAMILY_R200,
	43	CHIP_FAMILY_RV250,
	44	CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
	45	CHIP_FAMILY_RV280,
	46	CHIP_FAMILY_R300,
	47	CHIP_FAMILY_R350,
	48	CHIP_FAMILY_RV350,
	49	CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
	50	CHIP_FAMILY_R420, /* R420/R423/M18 */
	51	CHIP_FAMILY_LAST,
	52	};
	53
	54	#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) \|\| \
	55	((rinfo)->family == CHIP_FAMILY_RV200) \|\| \
	56	((rinfo)->family == CHIP_FAMILY_RS100) \|\| \
	57	((rinfo)->family == CHIP_FAMILY_RS200) \|\| \
	58	((rinfo)->family == CHIP_FAMILY_RV250) \|\| \
	59	((rinfo)->family == CHIP_FAMILY_RV280) \|\| \
	60	((rinfo)->family == CHIP_FAMILY_RS300))
	61
	62
	63	#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) \|\| \
	64	((rinfo)->family == CHIP_FAMILY_RV350) \|\| \
	65	((rinfo)->family == CHIP_FAMILY_R350) \|\| \
	66	((rinfo)->family == CHIP_FAMILY_RV380) \|\| \
	67	((rinfo)->family == CHIP_FAMILY_R420))
	68
	69	/*
	70	* Chip flags
	71	*/
	72	enum radeon_chip_flags {
	73	CHIP_FAMILY_MASK = 0x0000ffffUL,
	74	CHIP_FLAGS_MASK = 0xffff0000UL,
	75	CHIP_IS_MOBILITY = 0x00010000UL,
	76	CHIP_IS_IGP = 0x00020000UL,
	77	CHIP_HAS_CRTC2 = 0x00040000UL,
	78	};
	79
80	/*
81	* Errata workarounds
82	*/
83	enum radeon_errata {
84	CHIP_ERRATA_R300_CG = 0x00000001,
85	CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
86	CHIP_ERRATA_PLL_DELAY = 0x00000004,
87	};
88
89
90	/*
91	* Monitor types
92	*/
93	enum radeon_montype {
94	MT_NONE = 0,
95	MT_CRT, /* CRT */
96	MT_LCD, /* LCD */
97	MT_DFP, /* DVI */
98	MT_CTV, /* composite TV */
99	MT_STV /* S-Video out */
100	};
101
102	/*
103	* DDC i2c ports
104	*/
105	enum ddc_type {
106	ddc_none,
107	ddc_monid,
108	ddc_dvi,
109	ddc_vga,
110	ddc_crt2,
111	};
112
113	/*
114	* Connector types
115	*/
116	enum conn_type {
117	conn_none,
118	conn_proprietary,
119	conn_crt,
120	conn_DVI_I,
121	conn_DVI_D,
122	};
123
124
125	/*
126	* PLL infos
127	*/
128	struct pll_info {
129	int ppll_max;
130	int ppll_min;
131	int sclk, mclk;
132	int ref_div;
133	int ref_clk;
134	};
135
136
137	/*
138	* This structure contains the various registers manipulated by this
139	* driver for setting or restoring a mode. It's mostly copied from
140	* XFree's RADEONSaveRec structure. A few chip settings might still be
141	* tweaked without beeing reflected or saved in these registers though
142	*/
143	struct radeon_regs {
144	/* Common registers */
145	u32 ovr_clr;
146	u32 ovr_wid_left_right;
147	u32 ovr_wid_top_bottom;
148	u32 ov0_scale_cntl;
149	u32 mpp_tb_config;
150	u32 mpp_gp_config;
151	u32 subpic_cntl;
152	u32 viph_control;
153	u32 i2c_cntl_1;
154	u32 gen_int_cntl;
155	u32 cap0_trig_cntl;
156	u32 cap1_trig_cntl;
157	u32 bus_cntl;
158	u32 surface_cntl;
159	u32 bios_5_scratch;
160
161	/* Other registers to save for VT switches or driver load/unload */
162	u32 dp_datatype;
163	u32 rbbm_soft_reset;
164	u32 clock_cntl_index;
165	u32 amcgpio_en_reg;
166	u32 amcgpio_mask;
167
168	/* Surface/tiling registers */
169	u32 surf_lower_bound[8];
170	u32 surf_upper_bound[8];
171	u32 surf_info[8];
172
173	/* CRTC registers */
174	u32 crtc_gen_cntl;
175	u32 crtc_ext_cntl;
176	u32 dac_cntl;
177	u32 crtc_h_total_disp;
178	u32 crtc_h_sync_strt_wid;
179	u32 crtc_v_total_disp;
180	u32 crtc_v_sync_strt_wid;
181	u32 crtc_offset;
182	u32 crtc_offset_cntl;
183	u32 crtc_pitch;
184	u32 disp_merge_cntl;
185	u32 grph_buffer_cntl;
186	u32 crtc_more_cntl;
187
188	/* CRTC2 registers */
189	u32 crtc2_gen_cntl;
190	u32 dac2_cntl;
191	u32 disp_output_cntl;
192	u32 disp_hw_debug;
193	u32 disp2_merge_cntl;
194	u32 grph2_buffer_cntl;
195	u32 crtc2_h_total_disp;
196	u32 crtc2_h_sync_strt_wid;
197	u32 crtc2_v_total_disp;
198	u32 crtc2_v_sync_strt_wid;
199	u32 crtc2_offset;
200	u32 crtc2_offset_cntl;
201	u32 crtc2_pitch;
202
203	/* Flat panel regs */
204	u32 fp_crtc_h_total_disp;
205	u32 fp_crtc_v_total_disp;
206	u32 fp_gen_cntl;
207	u32 fp2_gen_cntl;
208	u32 fp_h_sync_strt_wid;
209	u32 fp2_h_sync_strt_wid;
210	u32 fp_horz_stretch;
211	u32 fp_panel_cntl;
212	u32 fp_v_sync_strt_wid;
213	u32 fp2_v_sync_strt_wid;
214	u32 fp_vert_stretch;
215	u32 lvds_gen_cntl;
216	u32 lvds_pll_cntl;
217	u32 tmds_crc;
218	u32 tmds_transmitter_cntl;
219
220	/* Computed values for PLL */
221	u32 dot_clock_freq;
222	int feedback_div;
223	int post_div;
224
225	/* PLL registers */
226	u32 ppll_div_3;
227	u32 ppll_ref_div;
228	u32 vclk_ecp_cntl;
229	u32 clk_cntl_index;
230
231	/* Computed values for PLL2 */
232	u32 dot_clock_freq_2;
233	int feedback_div_2;
234	int post_div_2;
235
236	/* PLL2 registers */
237	u32 p2pll_ref_div;
238	u32 p2pll_div_0;
239	u32 htotal_cntl2;
240
241	/* Palette */
242	int palette_valid;
243	};
244
245	struct panel_info {
246	int xres, yres;
247	int valid;
248	int clock;
249	int hOver_plus, hSync_width, hblank;
250	int vOver_plus, vSync_width, vblank;
251	int hAct_high, vAct_high, interlaced;
252	int pwr_delay;
253	int use_bios_dividers;
254	int ref_divider;
255	int post_divider;
256	int fbk_divider;
257	};
258
259	struct radeonfb_info;
260
261	#ifdef CONFIG_FB_RADEON_I2C
262	struct radeon_i2c_chan {
263	struct radeonfb_info *rinfo;
264	u32 ddc_reg;
265	struct i2c_adapter adapter;
266	struct i2c_algo_bit_data algo;
267	};
268	#endif
269
270	enum radeon_pm_mode {
271	radeon_pm_none = 0, /* Nothing supported */
272	radeon_pm_d2 = 0x00000001, /* Can do D2 state */
273	radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
274	};
275
994aad25 VB	276	typedef void (reinit_function_ptr)(struct radeonfb_info rinfo);
994aad25 VB	277
1da177e4 LT	278	struct radeonfb_info {
	279	struct fb_info *info;
	280
	281	struct radeon_regs state;
	282	struct radeon_regs init_state;
	283
	284	char name[DEVICE_NAME_SIZE];
	285
	286	unsigned long mmio_base_phys;
	287	unsigned long fb_base_phys;
	288
	289	void __iomem *mmio_base;
	290	void __iomem *fb_base;
	291
	292	unsigned long fb_local_base;
	293
	294	struct pci_dev *pdev;
	295	#ifdef CONFIG_PPC_OF
	296	struct device_node *of_node;
	297	#endif
	298
	299	void __iomem *bios_seg;
	300	int fp_bios_start;
	301
	302	u32 pseudo_palette[17];
	303	struct { u8 red, green, blue, pad; }
	304	palette[256];
	305
	306	int chipset;
	307	u8 family;
	308	u8 rev;
	309	unsigned int errata;
	310	unsigned long video_ram;
	311	unsigned long mapped_vram;
	312	int vram_width;
	313	int vram_ddr;
	314
	315	int pitch, bpp, depth;
	316
	317	int has_CRTC2;
	318	int is_mobility;
	319	int is_IGP;
	320	int reversed_DAC;
	321	int reversed_TMDS;
	322	struct panel_info panel_info;
	323	int mon1_type;
	324	u8 *mon1_EDID;
	325	struct fb_videomode *mon1_modedb;
	326	int mon1_dbsize;
	327	int mon2_type;
	328	u8 *mon2_EDID;
	329
	330	u32 dp_gui_master_cntl;
	331
	332	struct pll_info pll;
	333
	334	int mtrr_hdl;
	335
	336	int pm_reg;
	337	u32 save_regs[100];
	338	int asleep;
	339	int lock_blank;
	340	int dynclk;
	341	int no_schedule;
342	enum radeon_pm_mode pm_mode;
994aad25	343	reinit_function_ptr reinit_func;
1da177e4 LT	344
	345	/* Lock on register access */
	346	spinlock_t reg_lock;
	347
	348	/* Timer used for delayed LVDS operations */
	349	struct timer_list lvds_timer;
	350	u32 pending_lvds_gen_cntl;
	351
	352	#ifdef CONFIG_FB_RADEON_I2C
	353	struct radeon_i2c_chan i2c[4];
	354	#endif
	355
	356	u32 cfg_save[64];
	357	};
	358
	359
	360	#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
	361
	362
	363	/*
	364	* Debugging stuffs
	365	*/
	366	#ifdef CONFIG_FB_RADEON_DEBUG
	367	#define DEBUG 1
	368	#else
	369	#define DEBUG 0
	370	#endif
	371
	372	#if DEBUG
	373	#define RTRACE printk
	374	#else
	375	#define RTRACE if(0) printk
	376	#endif
	377
	378
	379	/*
	380	* IO macros
	381	*/
	382
	383	/* Note about this function: we have some rare cases where we must not schedule,
	384	* this typically happen with our special "wake up early" hook which allows us to
	385	* wake up the graphic chip (and thus get the console back) before everything else
b3c2ffd5	386	* on some machines that support that mechanism. At this point, interrupts are off
1da177e4 LT	387	* and scheduling is not permitted
	388	*/
	389	static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
	390	{
	391	if (rinfo->no_schedule \|\| oops_in_progress)
	392	mdelay(ms);
	393	else
	394	msleep(ms);
	395	}
	396
	397
	398	#define INREG8(addr) readb((rinfo->mmio_base)+addr)
	399	#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
017fb98e DM	400	#define INREG16(addr) readw((rinfo->mmio_base)+addr)
017fb98e DM	401	#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
1da177e4 LT	402	#define INREG(addr) readl((rinfo->mmio_base)+addr)
	403	#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
	404
	405	static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
	406	u32 val, u32 mask)
	407	{
	408	unsigned long flags;
	409	unsigned int tmp;
	410
	411	spin_lock_irqsave(&rinfo->reg_lock, flags);
	412	tmp = INREG(addr);
	413	tmp &= (mask);
	414	tmp \|= (val);
	415	OUTREG(addr, tmp);
	416	spin_unlock_irqrestore(&rinfo->reg_lock, flags);
	417	}
	418
	419	#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
	420
	421	/*
	422	* Note about PLL register accesses:
	423	*
	424	* I have removed the spinlock on them on purpose. The driver now
	425	* expects that it will only manipulate the PLL registers in normal
	426	* task environment, where radeon_msleep() will be called, protected
	427	* by a semaphore (currently the console semaphore) so that no conflict
	428	* will happen on the PLL register index.
	429	*
	430	* With the latest changes to the VT layer, this is guaranteed for all
	431	* calls except the actual drawing/blits which aren't supposed to use
	432	* the PLL registers anyway
	433	*
	434	* This is very important for the workarounds to work properly. The only
	435	* possible exception to this rule is the call to unblank(), which may
	436	* be done at irq time if an oops is in progress.
	437	*/
	438	static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
	439	{
	440	if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
	441	return;
	442
	443	(void)INREG(CLOCK_CNTL_DATA);
	444	(void)INREG(CRTC_GEN_CNTL);
	445	}
	446
	447	static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
	448	{
	449	if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
	450	/* we can't deal with posted writes here ... */
	451	_radeon_msleep(rinfo, 5);
	452	}
	453	if (rinfo->errata & CHIP_ERRATA_R300_CG) {
	454	u32 save, tmp;
	455	save = INREG(CLOCK_CNTL_INDEX);
	456	tmp = save & ~(0x3f \| PLL_WR_EN);
	457	OUTREG(CLOCK_CNTL_INDEX, tmp);
	458	tmp = INREG(CLOCK_CNTL_DATA);
	459	OUTREG(CLOCK_CNTL_INDEX, save);
	460	}
	461	}
	462
	463	static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
	464	{
	465	u32 data;
466
467	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
468	radeon_pll_errata_after_index(rinfo);
469	data = INREG(CLOCK_CNTL_DATA);
470	radeon_pll_errata_after_data(rinfo);
471	return data;
472	}
473
474	static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
475	u32 val)
476	{
477
478	OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) \| 0x00000080);
479	radeon_pll_errata_after_index(rinfo);
480	OUTREG(CLOCK_CNTL_DATA, val);
481	radeon_pll_errata_after_data(rinfo);
482	}
483
484
485	static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
486	u32 val, u32 mask)
487	{
488	unsigned int tmp;
489
490	tmp = __INPLL(rinfo, index);
491	tmp &= (mask);
492	tmp \|= (val);
493	__OUTPLL(rinfo, index, tmp);
494	}
495
496
497	#define INPLL(addr) __INPLL(rinfo, addr)
498	#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
499	#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
500
501
502	#define BIOS_IN8(v) (readb(rinfo->bios_seg + (v)))
503	#define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) \| \
504	(readb(rinfo->bios_seg + (v) + 1) << 8))
505	#define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) \| \
506	(readb(rinfo->bios_seg + (v) + 1) << 8) \| \
507	(readb(rinfo->bios_seg + (v) + 2) << 16) \| \
508	(readb(rinfo->bios_seg + (v) + 3) << 24))
509
510	/*
511	* Inline utilities
512	*/
513	static inline int round_div(int num, int den)
514	{
515	return (num + (den / 2)) / den;
516	}
517
518	static inline int var_to_depth(const struct fb_var_screeninfo *var)
519	{
520	if (var->bits_per_pixel != 16)
521	return var->bits_per_pixel;
522	return (var->green.length == 5) ? 15 : 16;
523	}
524
525	static inline u32 radeon_get_dstbpp(u16 depth)
526	{
527	switch (depth) {
528	case 8:
529	return DST_8BPP;
530	case 15:
531	return DST_15BPP;
532	case 16:
533	return DST_16BPP;
534	case 32:
535	return DST_32BPP;
536	default:
537	return 0;
538	}
539	}
540
541	/*
542	* 2D Engine helper routines
543	*/
544	static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
545	{
546	int i;
547
548	/* initiate flush */
549	OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
550	~RB2D_DC_FLUSH_ALL);
551
552	for (i=0; i < 2000000; i++) {
553	if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
554	return;
555	udelay(1);
556	}
557	printk(KERN_ERR "radeonfb: Flush Timeout !\n");
558	}
559
560
561	static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
562	{
563	int i;
564
565	for (i=0; i<2000000; i++) {
566	if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
567	return;
568	udelay(1);
569	}
570	printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
571	}
572
573
574	static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
575	{
576	int i;
577
578	/* ensure FIFO is empty before waiting for idle */
579	_radeon_fifo_wait (rinfo, 64);
580
581	for (i=0; i<2000000; i++) {
582	if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
583	radeon_engine_flush (rinfo);
584	return;
585	}
586	udelay(1);
587	}
588	printk(KERN_ERR "radeonfb: Idle Timeout !\n");
589	}
590
591
592	#define radeon_engine_idle() _radeon_engine_idle(rinfo)
593	#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
594	#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
595
596
597	/* I2C Functions */
598	extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
599	extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
600	extern int radeon_probe_i2c_connector(struct radeonfb_info rinfo, int conn, u8 *out_edid);
601
602	/* PM Functions */
603	extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
604	extern int radeonfb_pci_resume(struct pci_dev *pdev);
994aad25	605	extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
1da177e4 LT	606	extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
	607
	608	/* Monitor probe functions */
	609	extern void radeon_probe_screens(struct radeonfb_info *rinfo,
	610	const char *monitor_layout, int ignore_edid);
	611	extern void radeon_check_modes(struct radeonfb_info rinfo, const char mode_option);
	612	extern int radeon_match_mode(struct radeonfb_info *rinfo,
	613	struct fb_var_screeninfo *dest,
	614	const struct fb_var_screeninfo *src);
	615
	616	/* Accel functions */
	617	extern void radeonfb_fillrect(struct fb_info info, const struct fb_fillrect region);
	618	extern void radeonfb_copyarea(struct fb_info info, const struct fb_copyarea area);
	619	extern void radeonfb_imageblit(struct fb_info p, const struct fb_image image);
	620	extern int radeonfb_sync(struct fb_info *info);
	621	extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
	622	extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
	623
	624	/* Other functions */
	625	extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
	626	extern void radeon_write_mode (struct radeonfb_info rinfo, struct radeon_regs mode,
	627	int reg_only);
	628
5474c120 MH	629	/* Backlight functions */
	630	#ifdef CONFIG_FB_RADEON_BACKLIGHT
	631	extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
	632	extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
	633	#else
	634	static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
	635	static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
	636	#endif
	637
1da177e4	638	#endif /* __RADEONFB_H__ */