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davinci: fb: update the driver in preparation for addition of power management features
[deliverable/linux.git] / drivers / video / da8xx-fb.c
CommitLineData
4ed824d9
SR		 1/*
2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
4 *
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/fb.h>
25#include <linux/dma-mapping.h>
26#include <linux/device.h>
27#include <linux/platform_device.h>
28#include <linux/uaccess.h>
4ed824d9
SR		 29#include <linux/interrupt.h>
30#include <linux/clk.h>
e04e5483 31#include <linux/cpufreq.h>
4ed824d9
SR		 32#include <video/da8xx-fb.h>
33
34#define DRIVER_NAME "da8xx_lcdc"
35
36/* LCD Status Register */
37#define LCD_END_OF_FRAME0 BIT(8)
38#define LCD_FIFO_UNDERFLOW BIT(5)
39#define LCD_SYNC_LOST BIT(2)
40
41/* LCD DMA Control Register */
42#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
43#define LCD_DMA_BURST_1 0x0
44#define LCD_DMA_BURST_2 0x1
45#define LCD_DMA_BURST_4 0x2
46#define LCD_DMA_BURST_8 0x3
47#define LCD_DMA_BURST_16 0x4
48#define LCD_END_OF_FRAME_INT_ENA BIT(2)
49#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
50
51/* LCD Control Register */
52#define LCD_CLK_DIVISOR(x) ((x) << 8)
53#define LCD_RASTER_MODE 0x01
54
55/* LCD Raster Control Register */
56#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
57#define PALETTE_AND_DATA 0x00
58#define PALETTE_ONLY 0x01
59
60#define LCD_MONO_8BIT_MODE BIT(9)
61#define LCD_RASTER_ORDER BIT(8)
62#define LCD_TFT_MODE BIT(7)
63#define LCD_UNDERFLOW_INT_ENA BIT(6)
64#define LCD_MONOCHROME_MODE BIT(1)
65#define LCD_RASTER_ENABLE BIT(0)
66#define LCD_TFT_ALT_ENABLE BIT(23)
67#define LCD_STN_565_ENABLE BIT(24)
68
69/* LCD Raster Timing 2 Register */
70#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
71#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
72#define LCD_SYNC_CTRL BIT(25)
73#define LCD_SYNC_EDGE BIT(24)
74#define LCD_INVERT_PIXEL_CLOCK BIT(22)
75#define LCD_INVERT_LINE_CLOCK BIT(21)
76#define LCD_INVERT_FRAME_CLOCK BIT(20)
77
78/* LCD Block */
79#define LCD_CTRL_REG 0x4
80#define LCD_STAT_REG 0x8
81#define LCD_RASTER_CTRL_REG 0x28
82#define LCD_RASTER_TIMING_0_REG 0x2C
83#define LCD_RASTER_TIMING_1_REG 0x30
84#define LCD_RASTER_TIMING_2_REG 0x34
85#define LCD_DMA_CTRL_REG 0x40
86#define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
87#define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
88
89#define WSI_TIMEOUT 50
90#define PALETTE_SIZE 256
91#define LEFT_MARGIN 64
92#define RIGHT_MARGIN 64
93#define UPPER_MARGIN 32
94#define LOWER_MARGIN 32
95
96static resource_size_t da8xx_fb_reg_base;
97static struct resource *lcdc_regs;
98
99static inline unsigned int lcdc_read(unsigned int addr)
100{
101 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
102}
103
104static inline void lcdc_write(unsigned int val, unsigned int addr)
105{
106 __raw_writel(val, da8xx_fb_reg_base + (addr));
107}
108
109struct da8xx_fb_par {
4ed824d9
SR		 110 resource_size_t p_palette_base;
111 unsigned char *v_palette_base;
112 struct clk *lcdc_clk;
113 int irq;
114 unsigned short pseudo_palette[16];
115 unsigned int databuf_sz;
116 unsigned int palette_sz;
8097b174 117 unsigned int pxl_clk;
36113804 118 int blank;
e04e5483
C		 119#ifdef CONFIG_CPU_FREQ
120 struct notifier_block freq_transition;
121#endif
36113804 122 void (*panel_power_ctrl)(int);
4ed824d9
SR		 123};
124
125/* Variable Screen Information */
126static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
127 .xoffset = 0,
128 .yoffset = 0,
129 .transp = {0, 0, 0},
130 .nonstd = 0,
131 .activate = 0,
132 .height = -1,
133 .width = -1,
134 .pixclock = 46666, /* 46us - AUO display */
135 .accel_flags = 0,
136 .left_margin = LEFT_MARGIN,
137 .right_margin = RIGHT_MARGIN,
138 .upper_margin = UPPER_MARGIN,
139 .lower_margin = LOWER_MARGIN,
140 .sync = 0,
141 .vmode = FB_VMODE_NONINTERLACED
142};
143
144static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
145 .id = "DA8xx FB Drv",
146 .type = FB_TYPE_PACKED_PIXELS,
147 .type_aux = 0,
148 .visual = FB_VISUAL_PSEUDOCOLOR,
149 .xpanstep = 1,
150 .ypanstep = 1,
151 .ywrapstep = 1,
152 .accel = FB_ACCEL_NONE
153};
154
155struct da8xx_panel {
156 const char name[25]; /* Full name <vendor>_<model> */
157 unsigned short width;
158 unsigned short height;
159 int hfp; /* Horizontal front porch */
160 int hbp; /* Horizontal back porch */
161 int hsw; /* Horizontal Sync Pulse Width */
162 int vfp; /* Vertical front porch */
163 int vbp; /* Vertical back porch */
164 int vsw; /* Vertical Sync Pulse Width */
8097b174 165 unsigned int pxl_clk; /* Pixel clock */
2f93e8f4 166 unsigned char invert_pxl_clk; /* Invert Pixel clock */
4ed824d9
SR		 167};
168
169static struct da8xx_panel known_lcd_panels[] = {
170 /* Sharp LCD035Q3DG01 */
171 [0] = {
172 .name = "Sharp_LCD035Q3DG01",
173 .width = 320,
174 .height = 240,
175 .hfp = 8,
176 .hbp = 6,
177 .hsw = 0,
178 .vfp = 2,
179 .vbp = 2,
180 .vsw = 0,
8097b174 181 .pxl_clk = 4608000,
2f93e8f4 182 .invert_pxl_clk = 1,
4ed824d9
SR		 183 },
184 /* Sharp LK043T1DG01 */
185 [1] = {
186 .name = "Sharp_LK043T1DG01",
187 .width = 480,
188 .height = 272,
189 .hfp = 2,
190 .hbp = 2,
191 .hsw = 41,
192 .vfp = 2,
193 .vbp = 2,
194 .vsw = 10,
8097b174 195 .pxl_clk = 7833600,
2f93e8f4 196 .invert_pxl_clk = 0,
4ed824d9
SR		 197 },
198};
199
36113804
C		 200/* Enable the Raster Engine of the LCD Controller */
201static inline void lcd_enable_raster(void)
202{
203 u32 reg;
204
205 reg = lcdc_read(LCD_RASTER_CTRL_REG);
206 if (!(reg & LCD_RASTER_ENABLE))
207 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
208}
209
4ed824d9 210/* Disable the Raster Engine of the LCD Controller */
36113804 211static inline void lcd_disable_raster(void)
4ed824d9 212{
4ed824d9
SR		 213 u32 reg;
214
215 reg = lcdc_read(LCD_RASTER_CTRL_REG);
2f93e8f4 216 if (reg & LCD_RASTER_ENABLE)
4ed824d9 217 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
4ed824d9
SR		 218}
219
220static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
221{
222 u32 tmp = par->p_palette_base + par->databuf_sz - 4;
223 u32 reg;
224
225 /* Update the databuf in the hw. */
226 lcdc_write(par->p_palette_base, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
227 lcdc_write(tmp, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
228
229 /* Start the DMA. */
230 reg = lcdc_read(LCD_RASTER_CTRL_REG);
231 reg &= ~(3 << 20);
232 if (load_mode == LOAD_DATA)
233 reg |= LCD_PALETTE_LOAD_MODE(PALETTE_AND_DATA);
234 else if (load_mode == LOAD_PALETTE)
235 reg |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
236
237 lcdc_write(reg, LCD_RASTER_CTRL_REG);
238}
239
240/* Configure the Burst Size of DMA */
241static int lcd_cfg_dma(int burst_size)
242{
243 u32 reg;
244
245 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
246 switch (burst_size) {
247 case 1:
248 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
249 break;
250 case 2:
251 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
252 break;
253 case 4:
254 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
255 break;
256 case 8:
257 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
258 break;
259 case 16:
260 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
261 break;
262 default:
263 return -EINVAL;
264 }
2f93e8f4 265 lcdc_write(reg, LCD_DMA_CTRL_REG);
4ed824d9
SR		 266
267 return 0;
268}
269
270static void lcd_cfg_ac_bias(int period, int transitions_per_int)
271{
272 u32 reg;
273
274 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
275 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
276 reg |= LCD_AC_BIAS_FREQUENCY(period) |
277 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
278 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
279}
280
281static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
282 int front_porch)
283{
284 u32 reg;
285
286 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
287 reg |= ((back_porch & 0xff) << 24)
288 | ((front_porch & 0xff) << 16)
289 | ((pulse_width & 0x3f) << 10);
290 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
291}
292
293static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
294 int front_porch)
295{
296 u32 reg;
297
298 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
299 reg |= ((back_porch & 0xff) << 24)
300 | ((front_porch & 0xff) << 16)
301 | ((pulse_width & 0x3f) << 10);
302 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
303}
304
305static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
306{
307 u32 reg;
308
309 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
310 LCD_MONO_8BIT_MODE |
311 LCD_MONOCHROME_MODE);
312
313 switch (cfg->p_disp_panel->panel_shade) {
314 case MONOCHROME:
315 reg |= LCD_MONOCHROME_MODE;
316 if (cfg->mono_8bit_mode)
317 reg |= LCD_MONO_8BIT_MODE;
318 break;
319 case COLOR_ACTIVE:
320 reg |= LCD_TFT_MODE;
321 if (cfg->tft_alt_mode)
322 reg |= LCD_TFT_ALT_ENABLE;
323 break;
324
325 case COLOR_PASSIVE:
326 if (cfg->stn_565_mode)
327 reg |= LCD_STN_565_ENABLE;
328 break;
329
330 default:
331 return -EINVAL;
332 }
333
334 /* enable additional interrupts here */
335 reg |= LCD_UNDERFLOW_INT_ENA;
336
337 lcdc_write(reg, LCD_RASTER_CTRL_REG);
338
339 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
340
341 if (cfg->sync_ctrl)
342 reg |= LCD_SYNC_CTRL;
343 else
344 reg &= ~LCD_SYNC_CTRL;
345
346 if (cfg->sync_edge)
347 reg |= LCD_SYNC_EDGE;
348 else
349 reg &= ~LCD_SYNC_EDGE;
350
4ed824d9
SR		 351 if (cfg->invert_line_clock)
352 reg |= LCD_INVERT_LINE_CLOCK;
353 else
354 reg &= ~LCD_INVERT_LINE_CLOCK;
355
356 if (cfg->invert_frm_clock)
357 reg |= LCD_INVERT_FRAME_CLOCK;
358 else
359 reg &= ~LCD_INVERT_FRAME_CLOCK;
360
361 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
362
363 return 0;
364}
365
366static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
367 u32 bpp, u32 raster_order)
368{
369 u32 bpl, reg;
370
371 /* Disable Dual Frame Buffer. */
372 reg = lcdc_read(LCD_DMA_CTRL_REG);
373 lcdc_write(reg & ~LCD_DUAL_FRAME_BUFFER_ENABLE,
374 LCD_DMA_CTRL_REG);
375 /* Set the Panel Width */
376 /* Pixels per line = (PPL + 1)*16 */
377 /*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
378 width &= 0x3f0;
379 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
380 reg &= 0xfffffc00;
381 reg |= ((width >> 4) - 1) << 4;
382 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
383
384 /* Set the Panel Height */
385 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
386 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
387 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
388
389 /* Set the Raster Order of the Frame Buffer */
390 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
391 if (raster_order)
392 reg |= LCD_RASTER_ORDER;
393 lcdc_write(reg, LCD_RASTER_CTRL_REG);
394
395 switch (bpp) {
396 case 1:
397 case 2:
398 case 4:
399 case 16:
400 par->palette_sz = 16 * 2;
401 break;
402
403 case 8:
404 par->palette_sz = 256 * 2;
405 break;
406
407 default:
408 return -EINVAL;
409 }
410
411 bpl = width * bpp / 8;
412 par->databuf_sz = height * bpl + par->palette_sz;
413
414 return 0;
415}
416
417static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
418 unsigned blue, unsigned transp,
419 struct fb_info *info)
420{
421 struct da8xx_fb_par *par = info->par;
422 unsigned short *palette = (unsigned short *)par->v_palette_base;
423 u_short pal;
424
425 if (regno > 255)
426 return 1;
427
428 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
429 return 1;
430
431 if (info->var.bits_per_pixel == 8) {
432 red >>= 4;
433 green >>= 8;
434 blue >>= 12;
435
436 pal = (red & 0x0f00);
437 pal |= (green & 0x00f0);
438 pal |= (blue & 0x000f);
439
440 palette[regno] = pal;
441
442 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
443 red >>= (16 - info->var.red.length);
444 red <<= info->var.red.offset;
445
446 green >>= (16 - info->var.green.length);
447 green <<= info->var.green.offset;
448
449 blue >>= (16 - info->var.blue.length);
450 blue <<= info->var.blue.offset;
451
452 par->pseudo_palette[regno] = red | green | blue;
453
454 palette[0] = 0x4000;
455 }
456
457 return 0;
458}
459
2f93e8f4 460static void lcd_reset(struct da8xx_fb_par *par)
4ed824d9 461{
4ed824d9 462 /* Disable the Raster if previously Enabled */
36113804 463 lcd_disable_raster();
4ed824d9
SR		 464
465 /* DMA has to be disabled */
466 lcdc_write(0, LCD_DMA_CTRL_REG);
467 lcdc_write(0, LCD_RASTER_CTRL_REG);
4ed824d9
SR		 468}
469
8097b174
C		 470static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
471{
472 unsigned int lcd_clk, div;
473
474 lcd_clk = clk_get_rate(par->lcdc_clk);
475 div = lcd_clk / par->pxl_clk;
476
477 /* Configure the LCD clock divisor. */
478 lcdc_write(LCD_CLK_DIVISOR(div) |
479 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
480}
481
4ed824d9
SR		 482static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
483 struct da8xx_panel *panel)
484{
485 u32 bpp;
486 int ret = 0;
487
2f93e8f4 488 lcd_reset(par);
4ed824d9 489
8097b174
C		 490 /* Calculate the divider */
491 lcd_calc_clk_divider(par);
4ed824d9 492
2f93e8f4
SR		 493 if (panel->invert_pxl_clk)
494 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
495 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
496 else
497 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
498 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
499
4ed824d9
SR		 500 /* Configure the DMA burst size. */
501 ret = lcd_cfg_dma(cfg->dma_burst_sz);
502 if (ret < 0)
503 return ret;
504
505 /* Configure the AC bias properties. */
506 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
507
508 /* Configure the vertical and horizontal sync properties. */
509 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
510 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
511
512 /* Configure for disply */
513 ret = lcd_cfg_display(cfg);
514 if (ret < 0)
515 return ret;
516
517 if (QVGA != cfg->p_disp_panel->panel_type)
518 return -EINVAL;
519
520 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
521 cfg->bpp >= cfg->p_disp_panel->min_bpp)
522 bpp = cfg->bpp;
523 else
524 bpp = cfg->p_disp_panel->max_bpp;
525 if (bpp == 12)
526 bpp = 16;
527 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
528 (unsigned int)panel->height, bpp,
529 cfg->raster_order);
530 if (ret < 0)
531 return ret;
532
533 /* Configure FDD */
534 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
535 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
536
537 return 0;
538}
539
540static irqreturn_t lcdc_irq_handler(int irq, void *arg)
541{
542 u32 stat = lcdc_read(LCD_STAT_REG);
4ed824d9
SR		 543
544 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
36113804 545 lcd_disable_raster();
4ed824d9 546 lcdc_write(stat, LCD_STAT_REG);
36113804 547 lcd_enable_raster();
4ed824d9
SR		 548 } else
549 lcdc_write(stat, LCD_STAT_REG);
550
4ed824d9
SR		 551 return IRQ_HANDLED;
552}
553
554static int fb_check_var(struct fb_var_screeninfo *var,
555 struct fb_info *info)
556{
557 int err = 0;
558
559 switch (var->bits_per_pixel) {
560 case 1:
561 case 8:
562 var->red.offset = 0;
563 var->red.length = 8;
564 var->green.offset = 0;
565 var->green.length = 8;
566 var->blue.offset = 0;
567 var->blue.length = 8;
568 var->transp.offset = 0;
569 var->transp.length = 0;
570 break;
571 case 4:
572 var->red.offset = 0;
573 var->red.length = 4;
574 var->green.offset = 0;
575 var->green.length = 4;
576 var->blue.offset = 0;
577 var->blue.length = 4;
578 var->transp.offset = 0;
579 var->transp.length = 0;
580 break;
581 case 16: /* RGB 565 */
3510b8f7 582 var->red.offset = 11;
4ed824d9
SR		 583 var->red.length = 5;
584 var->green.offset = 5;
585 var->green.length = 6;
3510b8f7 586 var->blue.offset = 0;
4ed824d9
SR		 587 var->blue.length = 5;
588 var->transp.offset = 0;
589 var->transp.length = 0;
590 break;
591 default:
592 err = -EINVAL;
593 }
594
595 var->red.msb_right = 0;
596 var->green.msb_right = 0;
597 var->blue.msb_right = 0;
598 var->transp.msb_right = 0;
599 return err;
600}
601
e04e5483
C		 602#ifdef CONFIG_CPU_FREQ
603static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
604 unsigned long val, void *data)
605{
606 struct da8xx_fb_par *par;
e04e5483
C		 607
608 par = container_of(nb, struct da8xx_fb_par, freq_transition);
609 if (val == CPUFREQ_PRECHANGE) {
36113804 610 lcd_disable_raster();
e04e5483
C		 611 } else if (val == CPUFREQ_POSTCHANGE) {
612 lcd_calc_clk_divider(par);
36113804 613 lcd_enable_raster();
e04e5483
C		 614 }
615
616 return 0;
617}
618
619static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
620{
621 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
622
623 return cpufreq_register_notifier(&par->freq_transition,
624 CPUFREQ_TRANSITION_NOTIFIER);
625}
626
627static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
628{
629 cpufreq_unregister_notifier(&par->freq_transition,
630 CPUFREQ_TRANSITION_NOTIFIER);
631}
632#endif
633
4ed824d9
SR		 634static int __devexit fb_remove(struct platform_device *dev)
635{
636 struct fb_info *info = dev_get_drvdata(&dev->dev);
4ed824d9
SR		 637
638 if (info) {
639 struct da8xx_fb_par *par = info->par;
640
e04e5483
C		 641#ifdef CONFIG_CPU_FREQ
642 lcd_da8xx_cpufreq_deregister(par);
643#endif
36113804
C		 644 if (par->panel_power_ctrl)
645 par->panel_power_ctrl(0);
646
647 lcd_disable_raster();
4ed824d9
SR		 648 lcdc_write(0, LCD_RASTER_CTRL_REG);
649
650 /* disable DMA */
651 lcdc_write(0, LCD_DMA_CTRL_REG);
652
653 unregister_framebuffer(info);
654 fb_dealloc_cmap(&info->cmap);
655 dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
3510b8f7 656 info->screen_base - PAGE_SIZE,
4ed824d9
SR		 657 info->fix.smem_start);
658 free_irq(par->irq, par);
659 clk_disable(par->lcdc_clk);
660 clk_put(par->lcdc_clk);
661 framebuffer_release(info);
662 iounmap((void __iomem *)da8xx_fb_reg_base);
663 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
664
665 }
2f93e8f4 666 return 0;
4ed824d9
SR		 667}
668
669static int fb_ioctl(struct fb_info *info, unsigned int cmd,
670 unsigned long arg)
671{
672 struct lcd_sync_arg sync_arg;
673
674 switch (cmd) {
675 case FBIOGET_CONTRAST:
676 case FBIOPUT_CONTRAST:
677 case FBIGET_BRIGHTNESS:
678 case FBIPUT_BRIGHTNESS:
679 case FBIGET_COLOR:
680 case FBIPUT_COLOR:
2f93e8f4 681 return -ENOTTY;
4ed824d9
SR		 682 case FBIPUT_HSYNC:
683 if (copy_from_user(&sync_arg, (char *)arg,
684 sizeof(struct lcd_sync_arg)))
2f93e8f4 685 return -EFAULT;
4ed824d9
SR		 686 lcd_cfg_horizontal_sync(sync_arg.back_porch,
687 sync_arg.pulse_width,
688 sync_arg.front_porch);
689 break;
690 case FBIPUT_VSYNC:
691 if (copy_from_user(&sync_arg, (char *)arg,
692 sizeof(struct lcd_sync_arg)))
2f93e8f4 693 return -EFAULT;
4ed824d9
SR		 694 lcd_cfg_vertical_sync(sync_arg.back_porch,
695 sync_arg.pulse_width,
696 sync_arg.front_porch);
697 break;
698 default:
699 return -EINVAL;
700 }
701 return 0;
702}
703
704static struct fb_ops da8xx_fb_ops = {
705 .owner = THIS_MODULE,
706 .fb_check_var = fb_check_var,
707 .fb_setcolreg = fb_setcolreg,
708 .fb_ioctl = fb_ioctl,
709 .fb_fillrect = cfb_fillrect,
710 .fb_copyarea = cfb_copyarea,
711 .fb_imageblit = cfb_imageblit,
712};
713
714static int __init fb_probe(struct platform_device *device)
715{
716 struct da8xx_lcdc_platform_data *fb_pdata =
717 device->dev.platform_data;
718 struct lcd_ctrl_config *lcd_cfg;
719 struct da8xx_panel *lcdc_info;
720 struct fb_info *da8xx_fb_info;
721 struct clk *fb_clk = NULL;
722 struct da8xx_fb_par *par;
723 resource_size_t len;
724 int ret, i;
725
726 if (fb_pdata == NULL) {
727 dev_err(&device->dev, "Can not get platform data\n");
728 return -ENOENT;
729 }
730
731 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
732 if (!lcdc_regs) {
733 dev_err(&device->dev,
734 "Can not get memory resource for LCD controller\n");
735 return -ENOENT;
736 }
737
738 len = resource_size(lcdc_regs);
739
740 lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
741 if (!lcdc_regs)
742 return -EBUSY;
743
744 da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
745 if (!da8xx_fb_reg_base) {
746 ret = -EBUSY;
747 goto err_request_mem;
748 }
749
750 fb_clk = clk_get(&device->dev, NULL);
751 if (IS_ERR(fb_clk)) {
752 dev_err(&device->dev, "Can not get device clock\n");
753 ret = -ENODEV;
754 goto err_ioremap;
755 }
756 ret = clk_enable(fb_clk);
757 if (ret)
758 goto err_clk_put;
759
760 for (i = 0, lcdc_info = known_lcd_panels;
761 i < ARRAY_SIZE(known_lcd_panels);
762 i++, lcdc_info++) {
763 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
764 break;
765 }
766
767 if (i == ARRAY_SIZE(known_lcd_panels)) {
768 dev_err(&device->dev, "GLCD: No valid panel found\n");
dd04a6b3 769 ret = -ENODEV;
4ed824d9
SR		 770 goto err_clk_disable;
771 } else
772 dev_info(&device->dev, "GLCD: Found %s panel\n",
773 fb_pdata->type);
774
775 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
776
777 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
778 &device->dev);
779 if (!da8xx_fb_info) {
780 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
781 ret = -ENOMEM;
782 goto err_clk_disable;
783 }
784
785 par = da8xx_fb_info->par;
8097b174
C		 786 par->lcdc_clk = fb_clk;
787 par->pxl_clk = lcdc_info->pxl_clk;
36113804
C		 788 if (fb_pdata->panel_power_ctrl) {
789 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
790 par->panel_power_ctrl(1);
791 }
4ed824d9
SR		 792
793 if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
794 dev_err(&device->dev, "lcd_init failed\n");
795 ret = -EFAULT;
796 goto err_release_fb;
797 }
798
799 /* allocate frame buffer */
800 da8xx_fb_info->screen_base = dma_alloc_coherent(NULL,
801 par->databuf_sz + PAGE_SIZE,
802 (resource_size_t *)
803 &da8xx_fb_info->fix.smem_start,
804 GFP_KERNEL | GFP_DMA);
805
806 if (!da8xx_fb_info->screen_base) {
807 dev_err(&device->dev,
808 "GLCD: kmalloc for frame buffer failed\n");
809 ret = -EINVAL;
810 goto err_release_fb;
811 }
812
813 /* move palette base pointer by (PAGE_SIZE - palette_sz) bytes */
814 par->v_palette_base = da8xx_fb_info->screen_base +
815 (PAGE_SIZE - par->palette_sz);
816 par->p_palette_base = da8xx_fb_info->fix.smem_start +
817 (PAGE_SIZE - par->palette_sz);
818
819 /* the rest of the frame buffer is pixel data */
3510b8f7 820 da8xx_fb_info->screen_base = par->v_palette_base + par->palette_sz;
4ed824d9
SR		 821 da8xx_fb_fix.smem_start = par->p_palette_base + par->palette_sz;
822 da8xx_fb_fix.smem_len = par->databuf_sz - par->palette_sz;
823 da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
824
4ed824d9
SR		 825 par->irq = platform_get_irq(device, 0);
826 if (par->irq < 0) {
827 ret = -ENOENT;
828 goto err_release_fb_mem;
829 }
830
831 ret = request_irq(par->irq, lcdc_irq_handler, 0, DRIVER_NAME, par);
832 if (ret)
833 goto err_release_fb_mem;
834
835 /* Initialize par */
836 da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
837
838 da8xx_fb_var.xres = lcdc_info->width;
839 da8xx_fb_var.xres_virtual = lcdc_info->width;
840
841 da8xx_fb_var.yres = lcdc_info->height;
842 da8xx_fb_var.yres_virtual = lcdc_info->height;
843
844 da8xx_fb_var.grayscale =
845 lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
846 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
847
848 da8xx_fb_var.hsync_len = lcdc_info->hsw;
849 da8xx_fb_var.vsync_len = lcdc_info->vsw;
850
851 /* Initialize fbinfo */
852 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
853 da8xx_fb_info->fix = da8xx_fb_fix;
854 da8xx_fb_info->var = da8xx_fb_var;
855 da8xx_fb_info->fbops = &da8xx_fb_ops;
856 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
3510b8f7
SR		 857 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
858 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
4ed824d9
SR		 859
860 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
861 if (ret)
862 goto err_free_irq;
863
864 /* First palette_sz byte of the frame buffer is the palette */
865 da8xx_fb_info->cmap.len = par->palette_sz;
866
867 /* Flush the buffer to the screen. */
868 lcd_blit(LOAD_DATA, par);
869
870 /* initialize var_screeninfo */
871 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
872 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
873
874 dev_set_drvdata(&device->dev, da8xx_fb_info);
875 /* Register the Frame Buffer */
876 if (register_framebuffer(da8xx_fb_info) < 0) {
877 dev_err(&device->dev,
878 "GLCD: Frame Buffer Registration Failed!\n");
879 ret = -EINVAL;
880 goto err_dealloc_cmap;
881 }
882
e04e5483
C		 883#ifdef CONFIG_CPU_FREQ
884 ret = lcd_da8xx_cpufreq_register(par);
885 if (ret) {
886 dev_err(&device->dev, "failed to register cpufreq\n");
887 goto err_cpu_freq;
888 }
889#endif
890
4ed824d9 891 /* enable raster engine */
36113804 892 lcd_enable_raster();
4ed824d9
SR		 893
894 return 0;
895
e04e5483
C		 896#ifdef CONFIG_CPU_FREQ
897err_cpu_freq:
898 unregister_framebuffer(da8xx_fb_info);
899#endif
900
4ed824d9
SR		 901err_dealloc_cmap:
902 fb_dealloc_cmap(&da8xx_fb_info->cmap);
903
904err_free_irq:
905 free_irq(par->irq, par);
906
907err_release_fb_mem:
908 dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
3510b8f7 909 da8xx_fb_info->screen_base - PAGE_SIZE,
4ed824d9
SR		 910 da8xx_fb_info->fix.smem_start);
911
912err_release_fb:
913 framebuffer_release(da8xx_fb_info);
914
915err_clk_disable:
916 clk_disable(fb_clk);
917
918err_clk_put:
919 clk_put(fb_clk);
920
921err_ioremap:
922 iounmap((void __iomem *)da8xx_fb_reg_base);
923
924err_request_mem:
925 release_mem_region(lcdc_regs->start, len);
926
927 return ret;
928}
929
930#ifdef CONFIG_PM
931static int fb_suspend(struct platform_device *dev, pm_message_t state)
932{
933 return -EBUSY;
934}
935static int fb_resume(struct platform_device *dev)
936{
937 return -EBUSY;
938}
939#else
940#define fb_suspend NULL
941#define fb_resume NULL
942#endif
943
944static struct platform_driver da8xx_fb_driver = {
945 .probe = fb_probe,
946 .remove = fb_remove,
947 .suspend = fb_suspend,
948 .resume = fb_resume,
949 .driver = {
950 .name = DRIVER_NAME,
951 .owner = THIS_MODULE,
952 },
953};
954
955static int __init da8xx_fb_init(void)
956{
957 return platform_driver_register(&da8xx_fb_driver);
958}
959
960static void __exit da8xx_fb_cleanup(void)
961{
962 platform_driver_unregister(&da8xx_fb_driver);
963}
964
965module_init(da8xx_fb_init);
966module_exit(da8xx_fb_cleanup);
967
968MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
969MODULE_AUTHOR("Texas Instruments");
970MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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