projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e9474be4 JH |
1 | /* |
| 2 | * Register definition file for Samsung DP driver | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. | |
| 5 | * Author: Jingoo Han <jg1.han@samsung.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef _EXYNOS_DP_REG_H | |
| 13 | #define _EXYNOS_DP_REG_H | |
| 14 | ||
| 15 | #define EXYNOS_DP_TX_SW_RESET 0x14 | |
| 16 | #define EXYNOS_DP_FUNC_EN_1 0x18 | |
| 17 | #define EXYNOS_DP_FUNC_EN_2 0x1C | |
| 18 | #define EXYNOS_DP_VIDEO_CTL_1 0x20 | |
| 19 | #define EXYNOS_DP_VIDEO_CTL_2 0x24 | |
| 20 | #define EXYNOS_DP_VIDEO_CTL_3 0x28 | |
| 21 | ||
| 22 | #define EXYNOS_DP_VIDEO_CTL_8 0x3C | |
| 23 | #define EXYNOS_DP_VIDEO_CTL_10 0x44 | |
| 24 | ||
| 25 | #define EXYNOS_DP_LANE_MAP 0x35C | |
| 26 | ||
| 27 | #define EXYNOS_DP_AUX_HW_RETRY_CTL 0x390 | |
| 28 | ||
| 29 | #define EXYNOS_DP_COMMON_INT_STA_1 0x3C4 | |
| 30 | #define EXYNOS_DP_COMMON_INT_STA_2 0x3C8 | |
| 31 | #define EXYNOS_DP_COMMON_INT_STA_3 0x3CC | |
| 32 | #define EXYNOS_DP_COMMON_INT_STA_4 0x3D0 | |
| 33 | #define EXYNOS_DP_INT_STA 0x3DC | |
| 34 | #define EXYNOS_DP_COMMON_INT_MASK_1 0x3E0 | |
| 35 | #define EXYNOS_DP_COMMON_INT_MASK_2 0x3E4 | |
| 36 | #define EXYNOS_DP_COMMON_INT_MASK_3 0x3E8 | |
| 37 | #define EXYNOS_DP_COMMON_INT_MASK_4 0x3EC | |
| 38 | #define EXYNOS_DP_INT_STA_MASK 0x3F8 | |
| 39 | #define EXYNOS_DP_INT_CTL 0x3FC | |
| 40 | ||
| 41 | #define EXYNOS_DP_SYS_CTL_1 0x600 | |
| 42 | #define EXYNOS_DP_SYS_CTL_2 0x604 | |
| 43 | #define EXYNOS_DP_SYS_CTL_3 0x608 | |
| 44 | #define EXYNOS_DP_SYS_CTL_4 0x60C | |
| 45 | ||
| 46 | #define EXYNOS_DP_PKT_SEND_CTL 0x640 | |
| 47 | #define EXYNOS_DP_HDCP_CTL 0x648 | |
| 48 | ||
| 49 | #define EXYNOS_DP_LINK_BW_SET 0x680 | |
| 50 | #define EXYNOS_DP_LANE_COUNT_SET 0x684 | |
| 51 | #define EXYNOS_DP_TRAINING_PTN_SET 0x688 | |
| 52 | #define EXYNOS_DP_LN0_LINK_TRAINING_CTL 0x68C | |
| 53 | #define EXYNOS_DP_LN1_LINK_TRAINING_CTL 0x690 | |
| 54 | #define EXYNOS_DP_LN2_LINK_TRAINING_CTL 0x694 | |
| 55 | #define EXYNOS_DP_LN3_LINK_TRAINING_CTL 0x698 | |
| 56 | ||
| 57 | #define EXYNOS_DP_DEBUG_CTL 0x6C0 | |
| 58 | #define EXYNOS_DP_HPD_DEGLITCH_L 0x6C4 | |
| 59 | #define EXYNOS_DP_HPD_DEGLITCH_H 0x6C8 | |
| 60 | #define EXYNOS_DP_LINK_DEBUG_CTL 0x6E0 | |
| 61 | ||
| 62 | #define EXYNOS_DP_M_VID_0 0x700 | |
| 63 | #define EXYNOS_DP_M_VID_1 0x704 | |
| 64 | #define EXYNOS_DP_M_VID_2 0x708 | |
| 65 | #define EXYNOS_DP_N_VID_0 0x70C | |
| 66 | #define EXYNOS_DP_N_VID_1 0x710 | |
| 67 | #define EXYNOS_DP_N_VID_2 0x714 | |
| 68 | ||
| 69 | #define EXYNOS_DP_PLL_CTL 0x71C | |
| 70 | #define EXYNOS_DP_PHY_PD 0x720 | |
| 71 | #define EXYNOS_DP_PHY_TEST 0x724 | |
| 72 | ||
| 73 | #define EXYNOS_DP_VIDEO_FIFO_THRD 0x730 | |
| 74 | #define EXYNOS_DP_AUDIO_MARGIN 0x73C | |
| 75 | ||
| 76 | #define EXYNOS_DP_M_VID_GEN_FILTER_TH 0x764 | |
| 77 | #define EXYNOS_DP_M_AUD_GEN_FILTER_TH 0x778 | |
| 78 | #define EXYNOS_DP_AUX_CH_STA 0x780 | |
| 79 | #define EXYNOS_DP_AUX_CH_DEFER_CTL 0x788 | |
| 80 | #define EXYNOS_DP_AUX_RX_COMM 0x78C | |
| 81 | #define EXYNOS_DP_BUFFER_DATA_CTL 0x790 | |
| 82 | #define EXYNOS_DP_AUX_CH_CTL_1 0x794 | |
| 83 | #define EXYNOS_DP_AUX_ADDR_7_0 0x798 | |
| 84 | #define EXYNOS_DP_AUX_ADDR_15_8 0x79C | |
| 85 | #define EXYNOS_DP_AUX_ADDR_19_16 0x7A0 | |
| 86 | #define EXYNOS_DP_AUX_CH_CTL_2 0x7A4 | |
| 87 | ||
| 88 | #define EXYNOS_DP_BUF_DATA_0 0x7C0 | |
| 89 | ||
| 90 | #define EXYNOS_DP_SOC_GENERAL_CTL 0x800 | |
| 91 | ||
| 92 | /* EXYNOS_DP_TX_SW_RESET */ | |
| 93 | #define RESET_DP_TX (0x1 << 0) | |
| 94 | ||
| 95 | /* EXYNOS_DP_FUNC_EN_1 */ | |
| 96 | #define MASTER_VID_FUNC_EN_N (0x1 << 7) | |
| 97 | #define SLAVE_VID_FUNC_EN_N (0x1 << 5) | |
| 98 | #define AUD_FIFO_FUNC_EN_N (0x1 << 4) | |
| 99 | #define AUD_FUNC_EN_N (0x1 << 3) | |
| 100 | #define HDCP_FUNC_EN_N (0x1 << 2) | |
| 101 | #define CRC_FUNC_EN_N (0x1 << 1) | |
| 102 | #define SW_FUNC_EN_N (0x1 << 0) | |
| 103 | ||
| 104 | /* EXYNOS_DP_FUNC_EN_2 */ | |
| 105 | #define SSC_FUNC_EN_N (0x1 << 7) | |
| 106 | #define AUX_FUNC_EN_N (0x1 << 2) | |
| 107 | #define SERDES_FIFO_FUNC_EN_N (0x1 << 1) | |
| 108 | #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) | |
| 109 | ||
| 110 | /* EXYNOS_DP_VIDEO_CTL_1 */ | |
| 111 | #define VIDEO_EN (0x1 << 7) | |
| 112 | #define HDCP_VIDEO_MUTE (0x1 << 6) | |
| 113 | ||
| 114 | /* EXYNOS_DP_VIDEO_CTL_1 */ | |
| 115 | #define IN_D_RANGE_MASK (0x1 << 7) | |
| 116 | #define IN_D_RANGE_SHIFT (7) | |
| 117 | #define IN_D_RANGE_CEA (0x1 << 7) | |
| 118 | #define IN_D_RANGE_VESA (0x0 << 7) | |
| 119 | #define IN_BPC_MASK (0x7 << 4) | |
| 120 | #define IN_BPC_SHIFT (4) | |
| 121 | #define IN_BPC_12_BITS (0x3 << 4) | |
| 122 | #define IN_BPC_10_BITS (0x2 << 4) | |
| 123 | #define IN_BPC_8_BITS (0x1 << 4) | |
| 124 | #define IN_BPC_6_BITS (0x0 << 4) | |
| 125 | #define IN_COLOR_F_MASK (0x3 << 0) | |
| 126 | #define IN_COLOR_F_SHIFT (0) | |
| 127 | #define IN_COLOR_F_YCBCR444 (0x2 << 0) | |
| 128 | #define IN_COLOR_F_YCBCR422 (0x1 << 0) | |
| 129 | #define IN_COLOR_F_RGB (0x0 << 0) | |
| 130 | ||
| 131 | /* EXYNOS_DP_VIDEO_CTL_3 */ | |
| 132 | #define IN_YC_COEFFI_MASK (0x1 << 7) | |
| 133 | #define IN_YC_COEFFI_SHIFT (7) | |
| 134 | #define IN_YC_COEFFI_ITU709 (0x1 << 7) | |
| 135 | #define IN_YC_COEFFI_ITU601 (0x0 << 7) | |
| 136 | #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) | |
| 137 | #define VID_CHK_UPDATE_TYPE_SHIFT (4) | |
| 138 | #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) | |
| 139 | #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) | |
| 140 | ||
| 141 | /* EXYNOS_DP_VIDEO_CTL_8 */ | |
| 142 | #define VID_HRES_TH(x) (((x) & 0xf) << 4) | |
| 143 | #define VID_VRES_TH(x) (((x) & 0xf) << 0) | |
| 144 | ||
| 145 | /* EXYNOS_DP_VIDEO_CTL_10 */ | |
| 146 | #define FORMAT_SEL (0x1 << 4) | |
| 147 | #define INTERACE_SCAN_CFG (0x1 << 2) | |
| 148 | #define VSYNC_POLARITY_CFG (0x1 << 1) | |
| 149 | #define HSYNC_POLARITY_CFG (0x1 << 0) | |
| 150 | ||
| 151 | /* EXYNOS_DP_LANE_MAP */ | |
| 152 | #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) | |
| 153 | #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) | |
| 154 | #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) | |
| 155 | #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) | |
| 156 | #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) | |
| 157 | #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) | |
| 158 | #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) | |
| 159 | #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) | |
| 160 | #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) | |
| 161 | #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) | |
| 162 | #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) | |
| 163 | #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) | |
| 164 | #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) | |
| 165 | #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) | |
| 166 | #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) | |
| 167 | #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) | |
| 168 | ||
| 169 | /* EXYNOS_DP_AUX_HW_RETRY_CTL */ | |
| 170 | #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) | |
| 171 | #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) | |
| 172 | #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) | |
| 173 | #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) | |
| 174 | #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) | |
| 175 | #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) | |
| 176 | #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) | |
| 177 | ||
| 178 | /* EXYNOS_DP_COMMON_INT_STA_1 */ | |
| 179 | #define VSYNC_DET (0x1 << 7) | |
| 180 | #define PLL_LOCK_CHG (0x1 << 6) | |
| 181 | #define SPDIF_ERR (0x1 << 5) | |
| 182 | #define SPDIF_UNSTBL (0x1 << 4) | |
| 183 | #define VID_FORMAT_CHG (0x1 << 3) | |
| 184 | #define AUD_CLK_CHG (0x1 << 2) | |
| 185 | #define VID_CLK_CHG (0x1 << 1) | |
| 186 | #define SW_INT (0x1 << 0) | |
| 187 | ||
| 188 | /* EXYNOS_DP_COMMON_INT_STA_2 */ | |
| 189 | #define ENC_EN_CHG (0x1 << 6) | |
| 190 | #define HW_BKSV_RDY (0x1 << 3) | |
| 191 | #define HW_SHA_DONE (0x1 << 2) | |
| 192 | #define HW_AUTH_STATE_CHG (0x1 << 1) | |
| 193 | #define HW_AUTH_DONE (0x1 << 0) | |
| 194 | ||
| 195 | /* EXYNOS_DP_COMMON_INT_STA_3 */ | |
| 196 | #define AFIFO_UNDER (0x1 << 7) | |
| 197 | #define AFIFO_OVER (0x1 << 6) | |
| 198 | #define R0_CHK_FLAG (0x1 << 5) | |
| 199 | ||
| 200 | /* EXYNOS_DP_COMMON_INT_STA_4 */ | |
| 201 | #define PSR_ACTIVE (0x1 << 7) | |
| 202 | #define PSR_INACTIVE (0x1 << 6) | |
| 203 | #define SPDIF_BI_PHASE_ERR (0x1 << 5) | |
| 204 | #define HOTPLUG_CHG (0x1 << 2) | |
| 205 | #define HPD_LOST (0x1 << 1) | |
| 206 | #define PLUG (0x1 << 0) | |
| 207 | ||
| 208 | /* EXYNOS_DP_INT_STA */ | |
| 209 | #define INT_HPD (0x1 << 6) | |
| 210 | #define HW_TRAINING_FINISH (0x1 << 5) | |
| 211 | #define RPLY_RECEIV (0x1 << 1) | |
| 212 | #define AUX_ERR (0x1 << 0) | |
| 213 | ||
| 214 | /* EXYNOS_DP_INT_CTL */ | |
| 215 | #define SOFT_INT_CTRL (0x1 << 2) | |
| 216 | #define INT_POL (0x1 << 0) | |
| 217 | ||
| 218 | /* EXYNOS_DP_SYS_CTL_1 */ | |
| 219 | #define DET_STA (0x1 << 2) | |
| 220 | #define FORCE_DET (0x1 << 1) | |
| 221 | #define DET_CTRL (0x1 << 0) | |
| 222 | ||
| 223 | /* EXYNOS_DP_SYS_CTL_2 */ | |
| 224 | #define CHA_CRI(x) (((x) & 0xf) << 4) | |
| 225 | #define CHA_STA (0x1 << 2) | |
| 226 | #define FORCE_CHA (0x1 << 1) | |
| 227 | #define CHA_CTRL (0x1 << 0) | |
| 228 | ||
| 229 | /* EXYNOS_DP_SYS_CTL_3 */ | |
| 230 | #define HPD_STATUS (0x1 << 6) | |
| 231 | #define F_HPD (0x1 << 5) | |
| 232 | #define HPD_CTRL (0x1 << 4) | |
| 233 | #define HDCP_RDY (0x1 << 3) | |
| 234 | #define STRM_VALID (0x1 << 2) | |
| 235 | #define F_VALID (0x1 << 1) | |
| 236 | #define VALID_CTRL (0x1 << 0) | |
| 237 | ||
| 238 | /* EXYNOS_DP_SYS_CTL_4 */ | |
| 239 | #define FIX_M_AUD (0x1 << 4) | |
| 240 | #define ENHANCED (0x1 << 3) | |
| 241 | #define FIX_M_VID (0x1 << 2) | |
| 242 | #define M_VID_UPDATE_CTRL (0x3 << 0) | |
| 243 | ||
| 244 | /* EXYNOS_DP_TRAINING_PTN_SET */ | |
| 245 | #define SCRAMBLER_TYPE (0x1 << 9) | |
| 246 | #define HW_LINK_TRAINING_PATTERN (0x1 << 8) | |
| 247 | #define SCRAMBLING_DISABLE (0x1 << 5) | |
| 248 | #define SCRAMBLING_ENABLE (0x0 << 5) | |
| 249 | #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) | |
| 250 | #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) | |
| 251 | #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) | |
| 252 | #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) | |
| 253 | #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) | |
| 254 | #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) | |
| 255 | #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) | |
| 256 | #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) | |
| 257 | ||
| 258 | /* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ | |
| 259 | #define PRE_EMPHASIS_SET_SHIFT (3) | |
| 260 | ||
| 261 | /* EXYNOS_DP_DEBUG_CTL */ | |
| 262 | #define PLL_LOCK (0x1 << 4) | |
| 263 | #define F_PLL_LOCK (0x1 << 3) | |
| 264 | #define PLL_LOCK_CTRL (0x1 << 2) | |
| 265 | #define PN_INV (0x1 << 0) | |
| 266 | ||
| 267 | /* EXYNOS_DP_PLL_CTL */ | |
| 268 | #define DP_PLL_PD (0x1 << 7) | |
| 269 | #define DP_PLL_RESET (0x1 << 6) | |
| 270 | #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) | |
| 271 | #define DP_PLL_REF_BIT_1_1250V (0x5 << 0) | |
| 272 | #define DP_PLL_REF_BIT_1_2500V (0x7 << 0) | |
| 273 | ||
| 274 | /* EXYNOS_DP_PHY_PD */ | |
| 275 | #define DP_PHY_PD (0x1 << 5) | |
| 276 | #define AUX_PD (0x1 << 4) | |
| 277 | #define CH3_PD (0x1 << 3) | |
| 278 | #define CH2_PD (0x1 << 2) | |
| 279 | #define CH1_PD (0x1 << 1) | |
| 280 | #define CH0_PD (0x1 << 0) | |
| 281 | ||
| 282 | /* EXYNOS_DP_PHY_TEST */ | |
| 283 | #define MACRO_RST (0x1 << 5) | |
| 284 | #define CH1_TEST (0x1 << 1) | |
| 285 | #define CH0_TEST (0x1 << 0) | |
| 286 | ||
| 287 | /* EXYNOS_DP_AUX_CH_STA */ | |
| 288 | #define AUX_BUSY (0x1 << 4) | |
| 289 | #define AUX_STATUS_MASK (0xf << 0) | |
| 290 | ||
| 291 | /* EXYNOS_DP_AUX_CH_DEFER_CTL */ | |
| 292 | #define DEFER_CTRL_EN (0x1 << 7) | |
| 293 | #define DEFER_COUNT(x) (((x) & 0x7f) << 0) | |
| 294 | ||
| 295 | /* EXYNOS_DP_AUX_RX_COMM */ | |
| 296 | #define AUX_RX_COMM_I2C_DEFER (0x2 << 2) | |
| 297 | #define AUX_RX_COMM_AUX_DEFER (0x2 << 0) | |
| 298 | ||
| 299 | /* EXYNOS_DP_BUFFER_DATA_CTL */ | |
| 300 | #define BUF_CLR (0x1 << 7) | |
| 301 | #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) | |
| 302 | ||
| 303 | /* EXYNOS_DP_AUX_CH_CTL_1 */ | |
| 304 | #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) | |
| 305 | #define AUX_TX_COMM_MASK (0xf << 0) | |
| 306 | #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) | |
| 307 | #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) | |
| 308 | #define AUX_TX_COMM_MOT (0x1 << 2) | |
| 309 | #define AUX_TX_COMM_WRITE (0x0 << 0) | |
| 310 | #define AUX_TX_COMM_READ (0x1 << 0) | |
| 311 | ||
| 312 | /* EXYNOS_DP_AUX_ADDR_7_0 */ | |
| 313 | #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) | |
| 314 | ||
| 315 | /* EXYNOS_DP_AUX_ADDR_15_8 */ | |
| 316 | #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) | |
| 317 | ||
| 318 | /* EXYNOS_DP_AUX_ADDR_19_16 */ | |
| 319 | #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) | |
| 320 | ||
| 321 | /* EXYNOS_DP_AUX_CH_CTL_2 */ | |
| 322 | #define ADDR_ONLY (0x1 << 1) | |
| 323 | #define AUX_EN (0x1 << 0) | |
| 324 | ||
| 325 | /* EXYNOS_DP_SOC_GENERAL_CTL */ | |
| 326 | #define AUDIO_MODE_SPDIF_MODE (0x1 << 8) | |
| 327 | #define AUDIO_MODE_MASTER_MODE (0x0 << 8) | |
| 328 | #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) | |
| 329 | #define VIDEO_MASTER_CLK_SEL (0x1 << 2) | |
| 330 | #define VIDEO_MASTER_MODE_EN (0x1 << 1) | |
| 331 | #define VIDEO_MODE_MASK (0x1 << 0) | |
| 332 | #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) | |
| 333 | #define VIDEO_MODE_MASTER_MODE (0x0 << 0) | |
| 334 | ||
| 335 | #endif /* _EXYNOS_DP_REG_H */ |