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OMAPDSS: DISPC: fix div by zero issue in overlay scaling
[deliverable/linux.git] / drivers / video / fbdev / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
0006fd63
TV		 39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
80c39712 42
a0b38cc4 43#include <video/omapdss.h>
80c39712
TV		 44
45#include "dss.h"
a0acb557 46#include "dss_features.h"
9b372c2d 47#include "dispc.h"
80c39712
TV		 48
49/* DISPC */
8613b000 50#define DISPC_SZ_REGS SZ_4K
80c39712 51
5ed8cf5b
TV		 52enum omap_burst_size {
53 BURST_SIZE_X2 = 0,
54 BURST_SIZE_X4 = 1,
55 BURST_SIZE_X8 = 2,
56};
57
80c39712
TV		 58#define REG_GET(idx, start, end) \
59 FLD_GET(dispc_read_reg(idx), start, end)
60
61#define REG_FLD_MOD(idx, val, start, end) \
62 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
63
dcbe765b
CM		 64struct dispc_features {
65 u8 sw_start;
66 u8 fp_start;
67 u8 bp_start;
68 u16 sw_max;
69 u16 vp_max;
70 u16 hp_max;
33b89928
AT		 71 u8 mgr_width_start;
72 u8 mgr_height_start;
73 u16 mgr_width_max;
74 u16 mgr_height_max;
ca5ca69c
AT		 75 unsigned long max_lcd_pclk;
76 unsigned long max_tv_pclk;
0c6921de 77 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 78 const struct omap_video_timings *mgr_timings,
79 u16 width, u16 height, u16 out_width, u16 out_height,
80 enum omap_color_mode color_mode, bool *five_taps,
81 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 82 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 83 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 84 u16 width, u16 height, u16 out_width, u16 out_height,
85 bool mem_to_mem);
42a6961c 86 u8 num_fifos;
66a0f9e4
TV		 87
88 /* swap GFX & WB fifos */
89 bool gfx_fifo_workaround:1;
cffa947d
TV		 90
91 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
92 bool no_framedone_tv:1;
d0df9a2c
AT		 93
94 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
95 bool mstandby_workaround:1;
8bc65552
AT		 96
97 bool set_max_preload:1;
dcbe765b
CM		 98};
99
42a6961c
TV		 100#define DISPC_MAX_NR_FIFOS 5
101
80c39712 102static struct {
060b6d9c 103 struct platform_device *pdev;
80c39712 104 void __iomem *base;
4fbafaf3 105
affe360d 106 int irq;
0925afc9
TV		 107 irq_handler_t user_handler;
108 void *user_data;
80c39712 109
7b3926b3 110 unsigned long core_clk_rate;
5391e87d 111 unsigned long tv_pclk_rate;
7b3926b3 112
42a6961c
TV		 113 u32 fifo_size[DISPC_MAX_NR_FIFOS];
114 /* maps which plane is using a fifo. fifo-id -> plane-id */
115 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 116
49ea86f3 117 bool ctx_valid;
80c39712 118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 119
dcbe765b 120 const struct dispc_features *feat;
0925afc9
TV		 121
122 bool is_enabled;
0006fd63
TV		 123
124 struct regmap *syscon_pol;
125 u32 syscon_pol_offset;
80c39712
TV		 126} dispc;
127
0d66cbb5
AJ		 128enum omap_color_component {
129 /* used for all color formats for OMAP3 and earlier
130 * and for RGB and Y color component on OMAP4
131 */
132 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
133 /* used for UV component for
134 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
135 * color formats on OMAP4
136 */
137 DISPC_COLOR_COMPONENT_UV = 1 << 1,
138};
139
efa70b3b
CM		 140enum mgr_reg_fields {
141 DISPC_MGR_FLD_ENABLE,
142 DISPC_MGR_FLD_STNTFT,
143 DISPC_MGR_FLD_GO,
144 DISPC_MGR_FLD_TFTDATALINES,
145 DISPC_MGR_FLD_STALLMODE,
146 DISPC_MGR_FLD_TCKENABLE,
147 DISPC_MGR_FLD_TCKSELECTION,
148 DISPC_MGR_FLD_CPR,
149 DISPC_MGR_FLD_FIFOHANDCHECK,
150 /* used to maintain a count of the above fields */
151 DISPC_MGR_FLD_NUM,
152};
153
5c348ba9
JS		 154struct dispc_reg_field {
155 u16 reg;
156 u8 high;
157 u8 low;
158};
159
efa70b3b
CM		 160static const struct {
161 const char *name;
162 u32 vsync_irq;
163 u32 framedone_irq;
164 u32 sync_lost_irq;
5c348ba9 165 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
efa70b3b
CM		 166} mgr_desc[] = {
167 [OMAP_DSS_CHANNEL_LCD] = {
168 .name = "LCD",
169 .vsync_irq = DISPC_IRQ_VSYNC,
170 .framedone_irq = DISPC_IRQ_FRAMEDONE,
171 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
172 .reg_desc = {
173 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
174 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
175 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
176 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
177 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
178 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
179 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
180 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
181 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
182 },
183 },
184 [OMAP_DSS_CHANNEL_DIGIT] = {
185 .name = "DIGIT",
186 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 187 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 188 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
189 .reg_desc = {
190 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
191 [DISPC_MGR_FLD_STNTFT] = { },
192 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
193 [DISPC_MGR_FLD_TFTDATALINES] = { },
194 [DISPC_MGR_FLD_STALLMODE] = { },
195 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
196 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
197 [DISPC_MGR_FLD_CPR] = { },
198 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
199 },
200 },
201 [OMAP_DSS_CHANNEL_LCD2] = {
202 .name = "LCD2",
203 .vsync_irq = DISPC_IRQ_VSYNC2,
204 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
205 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
206 .reg_desc = {
207 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
208 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
209 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
210 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
211 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
212 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
213 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
214 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
215 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
216 },
217 },
e86d456a
CM		 218 [OMAP_DSS_CHANNEL_LCD3] = {
219 .name = "LCD3",
220 .vsync_irq = DISPC_IRQ_VSYNC3,
221 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
222 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
223 .reg_desc = {
224 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
225 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
226 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
227 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
228 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
229 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
230 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
231 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
232 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
233 },
234 },
efa70b3b
CM		 235};
236
6e5264b0
AT		 237struct color_conv_coef {
238 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
239 int full_range;
240};
241
3e8a6ff2
AT		 242static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
243static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 244
55978cc2 245static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 246{
55978cc2 247 __raw_writel(val, dispc.base + idx);
80c39712
TV		 248}
249
55978cc2 250static inline u32 dispc_read_reg(const u16 idx)
80c39712 251{
55978cc2 252 return __raw_readl(dispc.base + idx);
80c39712
TV		 253}
254
efa70b3b
CM		 255static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
256{
5c348ba9 257 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 258 return REG_GET(rfld.reg, rfld.high, rfld.low);
259}
260
261static void mgr_fld_write(enum omap_channel channel,
262 enum mgr_reg_fields regfld, int val) {
5c348ba9 263 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
efa70b3b
CM		 264 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
265}
266
80c39712 267#define SR(reg) \
55978cc2 268 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 269#define RR(reg) \
55978cc2 270 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 271
4fbafaf3 272static void dispc_save_context(void)
80c39712 273{
c6104b8e 274 int i, j;
80c39712 275
4fbafaf3
TV		 276 DSSDBG("dispc_save_context\n");
277
80c39712
TV		 278 SR(IRQENABLE);
279 SR(CONTROL);
280 SR(CONFIG);
80c39712 281 SR(LINE_NUMBER);
11354dd5
AT		 282 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
283 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 284 SR(GLOBAL_ALPHA);
2a205f34
SS		 285 if (dss_has_feature(FEAT_MGR_LCD2)) {
286 SR(CONTROL2);
2a205f34
SS		 287 SR(CONFIG2);
288 }
e86d456a
CM		 289 if (dss_has_feature(FEAT_MGR_LCD3)) {
290 SR(CONTROL3);
291 SR(CONFIG3);
292 }
80c39712 293
c6104b8e
AT		 294 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
295 SR(DEFAULT_COLOR(i));
296 SR(TRANS_COLOR(i));
297 SR(SIZE_MGR(i));
298 if (i == OMAP_DSS_CHANNEL_DIGIT)
299 continue;
300 SR(TIMING_H(i));
301 SR(TIMING_V(i));
302 SR(POL_FREQ(i));
303 SR(DIVISORo(i));
304
305 SR(DATA_CYCLE1(i));
306 SR(DATA_CYCLE2(i));
307 SR(DATA_CYCLE3(i));
308
332e9d70 309 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 310 SR(CPR_COEF_R(i));
311 SR(CPR_COEF_G(i));
312 SR(CPR_COEF_B(i));
332e9d70 313 }
2a205f34 314 }
80c39712 315
c6104b8e
AT		 316 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
317 SR(OVL_BA0(i));
318 SR(OVL_BA1(i));
319 SR(OVL_POSITION(i));
320 SR(OVL_SIZE(i));
321 SR(OVL_ATTRIBUTES(i));
322 SR(OVL_FIFO_THRESHOLD(i));
323 SR(OVL_ROW_INC(i));
324 SR(OVL_PIXEL_INC(i));
325 if (dss_has_feature(FEAT_PRELOAD))
326 SR(OVL_PRELOAD(i));
327 if (i == OMAP_DSS_GFX) {
328 SR(OVL_WINDOW_SKIP(i));
329 SR(OVL_TABLE_BA(i));
330 continue;
331 }
332 SR(OVL_FIR(i));
333 SR(OVL_PICTURE_SIZE(i));
334 SR(OVL_ACCU0(i));
335 SR(OVL_ACCU1(i));
9b372c2d 336
c6104b8e
AT		 337 for (j = 0; j < 8; j++)
338 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 339
c6104b8e
AT		 340 for (j = 0; j < 8; j++)
341 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 342
c6104b8e
AT		 343 for (j = 0; j < 5; j++)
344 SR(OVL_CONV_COEF(i, j));
ab5ca071 345
c6104b8e
AT		 346 if (dss_has_feature(FEAT_FIR_COEF_V)) {
347 for (j = 0; j < 8; j++)
348 SR(OVL_FIR_COEF_V(i, j));
349 }
9b372c2d 350
c6104b8e
AT		 351 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
352 SR(OVL_BA0_UV(i));
353 SR(OVL_BA1_UV(i));
354 SR(OVL_FIR2(i));
355 SR(OVL_ACCU2_0(i));
356 SR(OVL_ACCU2_1(i));
ab5ca071 357
c6104b8e
AT		 358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 360
c6104b8e
AT		 361 for (j = 0; j < 8; j++)
362 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 363
c6104b8e
AT		 364 for (j = 0; j < 8; j++)
365 SR(OVL_FIR_COEF_V2(i, j));
366 }
367 if (dss_has_feature(FEAT_ATTR2))
368 SR(OVL_ATTRIBUTES2(i));
ab5ca071 369 }
0cf35df3
MR		 370
371 if (dss_has_feature(FEAT_CORE_CLK_DIV))
372 SR(DIVISOR);
49ea86f3 373
49ea86f3
TV		 374 dispc.ctx_valid = true;
375
9229b516 376 DSSDBG("context saved\n");
80c39712
TV		 377}
378
4fbafaf3 379static void dispc_restore_context(void)
80c39712 380{
9229b516 381 int i, j;
4fbafaf3
TV		 382
383 DSSDBG("dispc_restore_context\n");
384
49ea86f3
TV		 385 if (!dispc.ctx_valid)
386 return;
387
75c7d59d 388 /*RR(IRQENABLE);*/
80c39712
TV		 389 /*RR(CONTROL);*/
390 RR(CONFIG);
80c39712 391 RR(LINE_NUMBER);
11354dd5
AT		 392 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
393 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 394 RR(GLOBAL_ALPHA);
c6104b8e 395 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 396 RR(CONFIG2);
e86d456a
CM		 397 if (dss_has_feature(FEAT_MGR_LCD3))
398 RR(CONFIG3);
80c39712 399
c6104b8e
AT		 400 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
401 RR(DEFAULT_COLOR(i));
402 RR(TRANS_COLOR(i));
403 RR(SIZE_MGR(i));
404 if (i == OMAP_DSS_CHANNEL_DIGIT)
405 continue;
406 RR(TIMING_H(i));
407 RR(TIMING_V(i));
408 RR(POL_FREQ(i));
409 RR(DIVISORo(i));
410
411 RR(DATA_CYCLE1(i));
412 RR(DATA_CYCLE2(i));
413 RR(DATA_CYCLE3(i));
2a205f34 414
332e9d70 415 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 416 RR(CPR_COEF_R(i));
417 RR(CPR_COEF_G(i));
418 RR(CPR_COEF_B(i));
332e9d70 419 }
2a205f34 420 }
80c39712 421
c6104b8e
AT		 422 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
423 RR(OVL_BA0(i));
424 RR(OVL_BA1(i));
425 RR(OVL_POSITION(i));
426 RR(OVL_SIZE(i));
427 RR(OVL_ATTRIBUTES(i));
428 RR(OVL_FIFO_THRESHOLD(i));
429 RR(OVL_ROW_INC(i));
430 RR(OVL_PIXEL_INC(i));
431 if (dss_has_feature(FEAT_PRELOAD))
432 RR(OVL_PRELOAD(i));
433 if (i == OMAP_DSS_GFX) {
434 RR(OVL_WINDOW_SKIP(i));
435 RR(OVL_TABLE_BA(i));
436 continue;
437 }
438 RR(OVL_FIR(i));
439 RR(OVL_PICTURE_SIZE(i));
440 RR(OVL_ACCU0(i));
441 RR(OVL_ACCU1(i));
9b372c2d 442
c6104b8e
AT		 443 for (j = 0; j < 8; j++)
444 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 445
c6104b8e
AT		 446 for (j = 0; j < 8; j++)
447 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 448
c6104b8e
AT		 449 for (j = 0; j < 5; j++)
450 RR(OVL_CONV_COEF(i, j));
ab5ca071 451
c6104b8e
AT		 452 if (dss_has_feature(FEAT_FIR_COEF_V)) {
453 for (j = 0; j < 8; j++)
454 RR(OVL_FIR_COEF_V(i, j));
455 }
9b372c2d 456
c6104b8e
AT		 457 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
458 RR(OVL_BA0_UV(i));
459 RR(OVL_BA1_UV(i));
460 RR(OVL_FIR2(i));
461 RR(OVL_ACCU2_0(i));
462 RR(OVL_ACCU2_1(i));
ab5ca071 463
c6104b8e
AT		 464 for (j = 0; j < 8; j++)
465 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 466
c6104b8e
AT		 467 for (j = 0; j < 8; j++)
468 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 469
c6104b8e
AT		 470 for (j = 0; j < 8; j++)
471 RR(OVL_FIR_COEF_V2(i, j));
472 }
473 if (dss_has_feature(FEAT_ATTR2))
474 RR(OVL_ATTRIBUTES2(i));
ab5ca071 475 }
80c39712 476
0cf35df3
MR		 477 if (dss_has_feature(FEAT_CORE_CLK_DIV))
478 RR(DIVISOR);
479
80c39712
TV		 480 /* enable last, because LCD & DIGIT enable are here */
481 RR(CONTROL);
2a205f34
SS		 482 if (dss_has_feature(FEAT_MGR_LCD2))
483 RR(CONTROL2);
e86d456a
CM		 484 if (dss_has_feature(FEAT_MGR_LCD3))
485 RR(CONTROL3);
75c7d59d 486 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 487 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 488
489 /*
490 * enable last so IRQs won't trigger before
491 * the context is fully restored
492 */
493 RR(IRQENABLE);
49ea86f3
TV		 494
495 DSSDBG("context restored\n");
80c39712
TV		 496}
497
498#undef SR
499#undef RR
500
4fbafaf3
TV		 501int dispc_runtime_get(void)
502{
503 int r;
504
505 DSSDBG("dispc_runtime_get\n");
506
507 r = pm_runtime_get_sync(&dispc.pdev->dev);
508 WARN_ON(r < 0);
509 return r < 0 ? r : 0;
510}
348be69d 511EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 512
513void dispc_runtime_put(void)
514{
515 int r;
516
517 DSSDBG("dispc_runtime_put\n");
518
0eaf9f52 519 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 520 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 521}
348be69d 522EXPORT_SYMBOL(dispc_runtime_put);
80c39712 523
3dcec4d6
TV		 524u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
525{
efa70b3b 526 return mgr_desc[channel].vsync_irq;
3dcec4d6 527}
348be69d 528EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 529
7d1365c9
TV		 530u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
531{
cffa947d
TV		 532 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
533 return 0;
534
efa70b3b 535 return mgr_desc[channel].framedone_irq;
7d1365c9 536}
348be69d 537EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 538
cb699200
TV		 539u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
540{
541 return mgr_desc[channel].sync_lost_irq;
542}
348be69d 543EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 544
0b23e5b8
AT		 545u32 dispc_wb_get_framedone_irq(void)
546{
547 return DISPC_IRQ_FRAMEDONEWB;
548}
549
26d9dd0d 550bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 551{
efa70b3b 552 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 553}
348be69d 554EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 555
26d9dd0d 556void dispc_mgr_go(enum omap_channel channel)
80c39712 557{
3c91ee8c
TV		 558 WARN_ON(dispc_mgr_is_enabled(channel) == false);
559 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 560
efa70b3b 561 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 562
efa70b3b 563 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 564}
348be69d 565EXPORT_SYMBOL(dispc_mgr_go);
80c39712 566
0b23e5b8
AT		 567bool dispc_wb_go_busy(void)
568{
569 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
570}
571
572void dispc_wb_go(void)
573{
574 enum omap_plane plane = OMAP_DSS_WB;
575 bool enable, go;
576
577 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
578
579 if (!enable)
580 return;
581
582 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
583 if (go) {
584 DSSERR("GO bit not down for WB\n");
585 return;
586 }
587
588 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
589}
590
f0e5caab 591static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 592{
9b372c2d 593 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 594}
595
f0e5caab 596static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 597{
9b372c2d 598 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 599}
600
f0e5caab 601static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 602{
9b372c2d 603 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 604}
605
f0e5caab 606static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 607{
608 BUG_ON(plane == OMAP_DSS_GFX);
609
610 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
611}
612
f0e5caab
TV		 613static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
614 u32 value)
ab5ca071
AJ		 615{
616 BUG_ON(plane == OMAP_DSS_GFX);
617
618 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
619}
620
f0e5caab 621static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 622{
623 BUG_ON(plane == OMAP_DSS_GFX);
624
625 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
626}
627
debd9074
CM		 628static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
629 int fir_vinc, int five_taps,
630 enum omap_color_component color_comp)
80c39712 631{
debd9074 632 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 633 int i;
634
debd9074
CM		 635 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
636 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 637
638 for (i = 0; i < 8; i++) {
639 u32 h, hv;
640
debd9074
CM		 641 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
642 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
643 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
644 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
645 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
646 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
647 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
648 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 649
0d66cbb5 650 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 651 dispc_ovl_write_firh_reg(plane, i, h);
652 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 653 } else {
f0e5caab
TV		 654 dispc_ovl_write_firh2_reg(plane, i, h);
655 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 656 }
657
80c39712
TV		 658 }
659
66be8f6c
GI		 660 if (five_taps) {
661 for (i = 0; i < 8; i++) {
662 u32 v;
debd9074
CM		 663 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
664 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 665 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 666 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 667 else
f0e5caab 668 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 669 }
80c39712
TV		 670 }
671}
672
80c39712 673
6e5264b0
AT		 674static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
675 const struct color_conv_coef *ct)
676{
80c39712
TV		 677#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
678
6e5264b0
AT		 679 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
680 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
681 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
682 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
683 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 684
6e5264b0 685 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 686
687#undef CVAL
80c39712
TV		 688}
689
6e5264b0
AT		 690static void dispc_setup_color_conv_coef(void)
691{
692 int i;
693 int num_ovl = dss_feat_get_num_ovls();
694 int num_wb = dss_feat_get_num_wbs();
695 const struct color_conv_coef ctbl_bt601_5_ovl = {
696 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
697 };
698 const struct color_conv_coef ctbl_bt601_5_wb = {
699 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
700 };
701
702 for (i = 1; i < num_ovl; i++)
703 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
704
705 for (; i < num_wb; i++)
706 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
707}
80c39712 708
f0e5caab 709static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 710{
9b372c2d 711 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 712}
713
f0e5caab 714static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 715{
9b372c2d 716 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 717}
718
f0e5caab 719static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 720{
721 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
722}
723
f0e5caab 724static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 725{
726 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
727}
728
d79db853
AT		 729static void dispc_ovl_set_pos(enum omap_plane plane,
730 enum omap_overlay_caps caps, int x, int y)
80c39712 731{
d79db853
AT		 732 u32 val;
733
734 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
735 return;
736
737 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 738
739 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 740}
741
78b687fc
AT		 742static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
743 int height)
80c39712 744{
80c39712 745 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 746
36d87d95 747 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 748 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
749 else
750 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 751}
752
78b687fc
AT		 753static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
754 int height)
80c39712
TV		 755{
756 u32 val;
80c39712
TV		 757
758 BUG_ON(plane == OMAP_DSS_GFX);
759
760 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 761
36d87d95
AT		 762 if (plane == OMAP_DSS_WB)
763 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
764 else
765 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 766}
767
5b54ed3e
AT		 768static void dispc_ovl_set_zorder(enum omap_plane plane,
769 enum omap_overlay_caps caps, u8 zorder)
54128701 770{
5b54ed3e 771 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 772 return;
773
774 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
775}
776
777static void dispc_ovl_enable_zorder_planes(void)
778{
779 int i;
780
781 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
782 return;
783
784 for (i = 0; i < dss_feat_get_num_ovls(); i++)
785 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
786}
787
5b54ed3e
AT		 788static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
789 enum omap_overlay_caps caps, bool enable)
fd28a390 790{
5b54ed3e 791 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 792 return;
793
9b372c2d 794 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 795}
796
5b54ed3e
AT		 797static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
798 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 799{
b8c095b4 800 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 801 int shift;
802
5b54ed3e 803 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 804 return;
a0acb557 805
fe3cc9d6
TV		 806 shift = shifts[plane];
807 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 808}
809
f0e5caab 810static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 811{
9b372c2d 812 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 813}
814
f0e5caab 815static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 816{
9b372c2d 817 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 818}
819
f0e5caab 820static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 821 enum omap_color_mode color_mode)
822{
823 u32 m = 0;
f20e4220
AJ		 824 if (plane != OMAP_DSS_GFX) {
825 switch (color_mode) {
826 case OMAP_DSS_COLOR_NV12:
827 m = 0x0; break;
08f3267e 828 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 829 m = 0x1; break;
830 case OMAP_DSS_COLOR_RGBA16:
831 m = 0x2; break;
08f3267e 832 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 833 m = 0x4; break;
834 case OMAP_DSS_COLOR_ARGB16:
835 m = 0x5; break;
836 case OMAP_DSS_COLOR_RGB16:
837 m = 0x6; break;
838 case OMAP_DSS_COLOR_ARGB16_1555:
839 m = 0x7; break;
840 case OMAP_DSS_COLOR_RGB24U:
841 m = 0x8; break;
842 case OMAP_DSS_COLOR_RGB24P:
843 m = 0x9; break;
844 case OMAP_DSS_COLOR_YUV2:
845 m = 0xa; break;
846 case OMAP_DSS_COLOR_UYVY:
847 m = 0xb; break;
848 case OMAP_DSS_COLOR_ARGB32:
849 m = 0xc; break;
850 case OMAP_DSS_COLOR_RGBA32:
851 m = 0xd; break;
852 case OMAP_DSS_COLOR_RGBX32:
853 m = 0xe; break;
854 case OMAP_DSS_COLOR_XRGB16_1555:
855 m = 0xf; break;
856 default:
c6eee968 857 BUG(); return;
f20e4220
AJ		 858 }
859 } else {
860 switch (color_mode) {
861 case OMAP_DSS_COLOR_CLUT1:
862 m = 0x0; break;
863 case OMAP_DSS_COLOR_CLUT2:
864 m = 0x1; break;
865 case OMAP_DSS_COLOR_CLUT4:
866 m = 0x2; break;
867 case OMAP_DSS_COLOR_CLUT8:
868 m = 0x3; break;
869 case OMAP_DSS_COLOR_RGB12U:
870 m = 0x4; break;
871 case OMAP_DSS_COLOR_ARGB16:
872 m = 0x5; break;
873 case OMAP_DSS_COLOR_RGB16:
874 m = 0x6; break;
875 case OMAP_DSS_COLOR_ARGB16_1555:
876 m = 0x7; break;
877 case OMAP_DSS_COLOR_RGB24U:
878 m = 0x8; break;
879 case OMAP_DSS_COLOR_RGB24P:
880 m = 0x9; break;
08f3267e 881 case OMAP_DSS_COLOR_RGBX16:
f20e4220 882 m = 0xa; break;
08f3267e 883 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 884 m = 0xb; break;
885 case OMAP_DSS_COLOR_ARGB32:
886 m = 0xc; break;
887 case OMAP_DSS_COLOR_RGBA32:
888 m = 0xd; break;
889 case OMAP_DSS_COLOR_RGBX32:
890 m = 0xe; break;
891 case OMAP_DSS_COLOR_XRGB16_1555:
892 m = 0xf; break;
893 default:
c6eee968 894 BUG(); return;
f20e4220 895 }
80c39712
TV		 896 }
897
9b372c2d 898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 899}
900
65e006ff
CM		 901static void dispc_ovl_configure_burst_type(enum omap_plane plane,
902 enum omap_dss_rotation_type rotation_type)
903{
904 if (dss_has_feature(FEAT_BURST_2D) == 0)
905 return;
906
907 if (rotation_type == OMAP_DSS_ROT_TILER)
908 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
909 else
910 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
911}
912
f427984e 913void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 914{
915 int shift;
916 u32 val;
2a205f34 917 int chan = 0, chan2 = 0;
80c39712
TV		 918
919 switch (plane) {
920 case OMAP_DSS_GFX:
921 shift = 8;
922 break;
923 case OMAP_DSS_VIDEO1:
924 case OMAP_DSS_VIDEO2:
b8c095b4 925 case OMAP_DSS_VIDEO3:
80c39712
TV		 926 shift = 16;
927 break;
928 default:
929 BUG();
930 return;
931 }
932
9b372c2d 933 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 934 if (dss_has_feature(FEAT_MGR_LCD2)) {
935 switch (channel) {
936 case OMAP_DSS_CHANNEL_LCD:
937 chan = 0;
938 chan2 = 0;
939 break;
940 case OMAP_DSS_CHANNEL_DIGIT:
941 chan = 1;
942 chan2 = 0;
943 break;
944 case OMAP_DSS_CHANNEL_LCD2:
945 chan = 0;
946 chan2 = 1;
947 break;
e86d456a
CM		 948 case OMAP_DSS_CHANNEL_LCD3:
949 if (dss_has_feature(FEAT_MGR_LCD3)) {
950 chan = 0;
951 chan2 = 2;
952 } else {
953 BUG();
954 return;
955 }
956 break;
2a205f34
SS		 957 default:
958 BUG();
c6eee968 959 return;
2a205f34
SS		 960 }
961
962 val = FLD_MOD(val, chan, shift, shift);
963 val = FLD_MOD(val, chan2, 31, 30);
964 } else {
965 val = FLD_MOD(val, channel, shift, shift);
966 }
9b372c2d 967 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 968}
348be69d 969EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 970
2cc5d1af
TV		 971static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
972{
973 int shift;
974 u32 val;
975 enum omap_channel channel;
976
977 switch (plane) {
978 case OMAP_DSS_GFX:
979 shift = 8;
980 break;
981 case OMAP_DSS_VIDEO1:
982 case OMAP_DSS_VIDEO2:
983 case OMAP_DSS_VIDEO3:
984 shift = 16;
985 break;
986 default:
987 BUG();
c6eee968 988 return 0;
2cc5d1af
TV		 989 }
990
991 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
992
e86d456a
CM		 993 if (dss_has_feature(FEAT_MGR_LCD3)) {
994 if (FLD_GET(val, 31, 30) == 0)
995 channel = FLD_GET(val, shift, shift);
996 else if (FLD_GET(val, 31, 30) == 1)
997 channel = OMAP_DSS_CHANNEL_LCD2;
998 else
999 channel = OMAP_DSS_CHANNEL_LCD3;
1000 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 1001 if (FLD_GET(val, 31, 30) == 0)
1002 channel = FLD_GET(val, shift, shift);
1003 else
1004 channel = OMAP_DSS_CHANNEL_LCD2;
1005 } else {
1006 channel = FLD_GET(val, shift, shift);
1007 }
1008
1009 return channel;
1010}
1011
d9ac773c
AT		 1012void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1013{
1014 enum omap_plane plane = OMAP_DSS_WB;
1015
1016 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1017}
1018
f0e5caab 1019static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1020 enum omap_burst_size burst_size)
1021{
8bbe09ee 1022 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1023 int shift;
80c39712 1024
fe3cc9d6 1025 shift = shifts[plane];
5ed8cf5b 1026 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1027}
1028
5ed8cf5b
TV		 1029static void dispc_configure_burst_sizes(void)
1030{
1031 int i;
1032 const int burst_size = BURST_SIZE_X8;
1033
1034 /* Configure burst size always to maximum size */
392faa0e 1035 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1036 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1037}
1038
83fa2f2e 1039static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1040{
1041 unsigned unit = dss_feat_get_burst_size_unit();
1042 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1043 return unit * 8;
1044}
1045
d3862610
M		 1046void dispc_enable_gamma_table(bool enable)
1047{
1048 /*
1049 * This is partially implemented to support only disabling of
1050 * the gamma table.
1051 */
1052 if (enable) {
1053 DSSWARN("Gamma table enabling for TV not yet supported");
1054 return;
1055 }
1056
1057 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1058}
1059
c64dca40 1060static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1061{
efa70b3b 1062 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1063 return;
1064
efa70b3b 1065 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1066}
1067
c64dca40 1068static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1069 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1070{
1071 u32 coef_r, coef_g, coef_b;
1072
dd88b7a6 1073 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1074 return;
1075
1076 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1077 FLD_VAL(coefs->rb, 9, 0);
1078 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1079 FLD_VAL(coefs->gb, 9, 0);
1080 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1081 FLD_VAL(coefs->bb, 9, 0);
1082
1083 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1084 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1085 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1086}
1087
f0e5caab 1088static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1089{
1090 u32 val;
1091
1092 BUG_ON(plane == OMAP_DSS_GFX);
1093
9b372c2d 1094 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1095 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1096 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1097}
1098
d79db853
AT		 1099static void dispc_ovl_enable_replication(enum omap_plane plane,
1100 enum omap_overlay_caps caps, bool enable)
80c39712 1101{
b8c095b4 1102 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1103 int shift;
80c39712 1104
d79db853
AT		 1105 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1106 return;
1107
fe3cc9d6
TV		 1108 shift = shifts[plane];
1109 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1110}
1111
8f366162 1112static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1113 u16 height)
80c39712
TV		 1114{
1115 u32 val;
80c39712 1116
33b89928
AT		 1117 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1118 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1119
8f366162 1120 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1121}
1122
42a6961c 1123static void dispc_init_fifos(void)
80c39712 1124{
80c39712 1125 u32 size;
42a6961c 1126 int fifo;
a0acb557 1127 u8 start, end;
5ed8cf5b
TV		 1128 u32 unit;
1129
1130 unit = dss_feat_get_buffer_size_unit();
80c39712 1131
a0acb557 1132 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1133
42a6961c
TV		 1134 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1135 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1136 size *= unit;
42a6961c
TV		 1137 dispc.fifo_size[fifo] = size;
1138
1139 /*
1140 * By default fifos are mapped directly to overlays, fifo 0 to
1141 * ovl 0, fifo 1 to ovl 1, etc.
1142 */
1143 dispc.fifo_assignment[fifo] = fifo;
80c39712 1144 }
66a0f9e4
TV		 1145
1146 /*
1147 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1148 * causes problems with certain use cases, like using the tiler in 2D
1149 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1150 * giving GFX plane a larger fifo. WB but should work fine with a
1151 * smaller fifo.
1152 */
1153 if (dispc.feat->gfx_fifo_workaround) {
1154 u32 v;
1155
1156 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1157
1158 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1159 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1160 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1161 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1162
1163 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1164
1165 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1166 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1167 }
80c39712
TV		 1168}
1169
83fa2f2e 1170static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1171{
42a6961c
TV		 1172 int fifo;
1173 u32 size = 0;
1174
1175 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1176 if (dispc.fifo_assignment[fifo] == plane)
1177 size += dispc.fifo_size[fifo];
1178 }
1179
1180 return size;
80c39712
TV		 1181}
1182
6f04e1bf 1183void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1184{
a0acb557 1185 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1186 u32 unit;
1187
1188 unit = dss_feat_get_buffer_size_unit();
1189
1190 WARN_ON(low % unit != 0);
1191 WARN_ON(high % unit != 0);
1192
1193 low /= unit;
1194 high /= unit;
a0acb557 1195
9b372c2d
AT		 1196 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1197 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1198
3cb5d966 1199 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1200 plane,
9b372c2d 1201 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1202 lo_start, lo_end) * unit,
9b372c2d 1203 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1204 hi_start, hi_end) * unit,
1205 low * unit, high * unit);
80c39712 1206
9b372c2d 1207 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1208 FLD_VAL(high, hi_start, hi_end) |
1209 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1210
1211 /*
1212 * configure the preload to the pipeline's high threhold, if HT it's too
1213 * large for the preload field, set the threshold to the maximum value
1214 * that can be held by the preload register
1215 */
1216 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1217 plane != OMAP_DSS_WB)
1218 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712 1219}
8ee5c842 1220EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
80c39712
TV		 1221
1222void dispc_enable_fifomerge(bool enable)
1223{
e6b0f884
TV		 1224 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1225 WARN_ON(enable);
1226 return;
1227 }
1228
80c39712
TV		 1229 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1230 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1231}
1232
83fa2f2e 1233void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1234 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1235 bool manual_update)
83fa2f2e
TV		 1236{
1237 /*
1238 * All sizes are in bytes. Both the buffer and burst are made of
1239 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1240 */
1241
1242 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1243 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1244 int i;
83fa2f2e
TV		 1245
1246 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1247 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1248
e0e405b9
TV		 1249 if (use_fifomerge) {
1250 total_fifo_size = 0;
392faa0e 1251 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1252 total_fifo_size += dispc_ovl_get_fifo_size(i);
1253 } else {
1254 total_fifo_size = ovl_fifo_size;
1255 }
1256
1257 /*
1258 * We use the same low threshold for both fifomerge and non-fifomerge
1259 * cases, but for fifomerge we calculate the high threshold using the
1260 * combined fifo size
1261 */
1262
3568f2a4 1263 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1264 *fifo_low = ovl_fifo_size - burst_size * 2;
1265 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1266 } else if (plane == OMAP_DSS_WB) {
1267 /*
1268 * Most optimal configuration for writeback is to push out data
1269 * to the interconnect the moment writeback pushes enough pixels
1270 * in the FIFO to form a burst
1271 */
1272 *fifo_low = 0;
1273 *fifo_high = burst_size;
e0e405b9
TV		 1274 } else {
1275 *fifo_low = ovl_fifo_size - burst_size;
1276 *fifo_high = total_fifo_size - buf_unit;
1277 }
83fa2f2e 1278}
8ee5c842 1279EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
83fa2f2e 1280
f0e5caab 1281static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1282 int hinc, int vinc,
1283 enum omap_color_component color_comp)
80c39712
TV		 1284{
1285 u32 val;
80c39712 1286
0d66cbb5
AJ		 1287 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1288 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1289
0d66cbb5
AJ		 1290 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1291 &hinc_start, &hinc_end);
1292 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1293 &vinc_start, &vinc_end);
1294 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1295 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1296
0d66cbb5
AJ		 1297 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1298 } else {
1299 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1300 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1301 }
80c39712
TV		 1302}
1303
f0e5caab 1304static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1305{
1306 u32 val;
87a7484b 1307 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1308
87a7484b
AT		 1309 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1310 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1311
1312 val = FLD_VAL(vaccu, vert_start, vert_end) |
1313 FLD_VAL(haccu, hor_start, hor_end);
1314
9b372c2d 1315 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1316}
1317
f0e5caab 1318static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1319{
1320 u32 val;
87a7484b 1321 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1322
87a7484b
AT		 1323 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1324 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1325
1326 val = FLD_VAL(vaccu, vert_start, vert_end) |
1327 FLD_VAL(haccu, hor_start, hor_end);
1328
9b372c2d 1329 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1330}
1331
f0e5caab
TV		 1332static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1333 int vaccu)
ab5ca071
AJ		 1334{
1335 u32 val;
1336
1337 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1338 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1339}
1340
f0e5caab
TV		 1341static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1342 int vaccu)
ab5ca071
AJ		 1343{
1344 u32 val;
1345
1346 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1347 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1348}
80c39712 1349
f0e5caab 1350static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1351 u16 orig_width, u16 orig_height,
1352 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1353 bool five_taps, u8 rotation,
1354 enum omap_color_component color_comp)
80c39712 1355{
0d66cbb5 1356 int fir_hinc, fir_vinc;
80c39712 1357
ed14a3ce
AJ		 1358 fir_hinc = 1024 * orig_width / out_width;
1359 fir_vinc = 1024 * orig_height / out_height;
80c39712 1360
debd9074
CM		 1361 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1362 color_comp);
f0e5caab 1363 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1364}
1365
05dd0f53
CM		 1366static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1367 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1368 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1369{
1370 int h_accu2_0, h_accu2_1;
1371 int v_accu2_0, v_accu2_1;
1372 int chroma_hinc, chroma_vinc;
1373 int idx;
1374
1375 struct accu {
1376 s8 h0_m, h0_n;
1377 s8 h1_m, h1_n;
1378 s8 v0_m, v0_n;
1379 s8 v1_m, v1_n;
1380 };
1381
1382 const struct accu *accu_table;
1383 const struct accu *accu_val;
1384
1385 static const struct accu accu_nv12[4] = {
1386 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1387 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1388 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1389 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1390 };
1391
1392 static const struct accu accu_nv12_ilace[4] = {
1393 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1394 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1395 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1396 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1397 };
1398
1399 static const struct accu accu_yuv[4] = {
1400 { 0, 1, 0, 1, 0, 1, 0, 1 },
1401 { 0, 1, 0, 1, 0, 1, 0, 1 },
1402 { -1, 1, 0, 1, 0, 1, 0, 1 },
1403 { 0, 1, 0, 1, -1, 1, 0, 1 },
1404 };
1405
1406 switch (rotation) {
1407 case OMAP_DSS_ROT_0:
1408 idx = 0;
1409 break;
1410 case OMAP_DSS_ROT_90:
1411 idx = 1;
1412 break;
1413 case OMAP_DSS_ROT_180:
1414 idx = 2;
1415 break;
1416 case OMAP_DSS_ROT_270:
1417 idx = 3;
1418 break;
1419 default:
1420 BUG();
c6eee968 1421 return;
05dd0f53
CM		 1422 }
1423
1424 switch (color_mode) {
1425 case OMAP_DSS_COLOR_NV12:
1426 if (ilace)
1427 accu_table = accu_nv12_ilace;
1428 else
1429 accu_table = accu_nv12;
1430 break;
1431 case OMAP_DSS_COLOR_YUV2:
1432 case OMAP_DSS_COLOR_UYVY:
1433 accu_table = accu_yuv;
1434 break;
1435 default:
1436 BUG();
c6eee968 1437 return;
05dd0f53
CM		 1438 }
1439
1440 accu_val = &accu_table[idx];
1441
1442 chroma_hinc = 1024 * orig_width / out_width;
1443 chroma_vinc = 1024 * orig_height / out_height;
1444
1445 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1446 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1447 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1448 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1449
1450 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1451 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1452}
1453
f0e5caab 1454static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1455 u16 orig_width, u16 orig_height,
1456 u16 out_width, u16 out_height,
1457 bool ilace, bool five_taps,
1458 bool fieldmode, enum omap_color_mode color_mode,
1459 u8 rotation)
1460{
1461 int accu0 = 0;
1462 int accu1 = 0;
1463 u32 l;
80c39712 1464
f0e5caab 1465 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1466 out_width, out_height, five_taps,
1467 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1468 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1469
87a7484b
AT		 1470 /* RESIZEENABLE and VERTICALTAPS */
1471 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1472 l |= (orig_width != out_width) ? (1 << 5) : 0;
1473 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1474 l |= five_taps ? (1 << 21) : 0;
80c39712 1475
87a7484b
AT		 1476 /* VRESIZECONF and HRESIZECONF */
1477 if (dss_has_feature(FEAT_RESIZECONF)) {
1478 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1479 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1480 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1481 }
80c39712 1482
87a7484b
AT		 1483 /* LINEBUFFERSPLIT */
1484 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1485 l &= ~(0x1 << 22);
1486 l |= five_taps ? (1 << 22) : 0;
1487 }
80c39712 1488
9b372c2d 1489 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1490
1491 /*
1492 * field 0 = even field = bottom field
1493 * field 1 = odd field = top field
1494 */
1495 if (ilace && !fieldmode) {
1496 accu1 = 0;
0d66cbb5 1497 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1498 if (accu0 >= 1024/2) {
1499 accu1 = 1024/2;
1500 accu0 -= accu1;
1501 }
1502 }
1503
f0e5caab
TV		 1504 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1505 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1506}
1507
f0e5caab 1508static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1509 u16 orig_width, u16 orig_height,
1510 u16 out_width, u16 out_height,
1511 bool ilace, bool five_taps,
1512 bool fieldmode, enum omap_color_mode color_mode,
1513 u8 rotation)
1514{
1515 int scale_x = out_width != orig_width;
1516 int scale_y = out_height != orig_height;
f92afae2 1517 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1518
1519 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1520 return;
1521 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1522 color_mode != OMAP_DSS_COLOR_UYVY &&
1523 color_mode != OMAP_DSS_COLOR_NV12)) {
1524 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1525 if (plane != OMAP_DSS_WB)
1526 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1527 return;
1528 }
36377357
TV		 1529
1530 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1531 out_height, ilace, color_mode, rotation);
1532
0d66cbb5
AJ		 1533 switch (color_mode) {
1534 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1535 if (chroma_upscale) {
1536 /* UV is subsampled by 2 horizontally and vertically */
1537 orig_height >>= 1;
1538 orig_width >>= 1;
1539 } else {
1540 /* UV is downsampled by 2 horizontally and vertically */
1541 orig_height <<= 1;
1542 orig_width <<= 1;
1543 }
1544
0d66cbb5
AJ		 1545 break;
1546 case OMAP_DSS_COLOR_YUV2:
1547 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1548 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1549 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1550 rotation == OMAP_DSS_ROT_180) {
1551 if (chroma_upscale)
1552 /* UV is subsampled by 2 horizontally */
1553 orig_width >>= 1;
1554 else
1555 /* UV is downsampled by 2 horizontally */
1556 orig_width <<= 1;
1557 }
1558
0d66cbb5
AJ		 1559 /* must use FIR for YUV422 if rotated */
1560 if (rotation != OMAP_DSS_ROT_0)
1561 scale_x = scale_y = true;
20fbb50b 1562
0d66cbb5
AJ		 1563 break;
1564 default:
1565 BUG();
c6eee968 1566 return;
0d66cbb5
AJ		 1567 }
1568
1569 if (out_width != orig_width)
1570 scale_x = true;
1571 if (out_height != orig_height)
1572 scale_y = true;
1573
f0e5caab 1574 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1575 out_width, out_height, five_taps,
1576 rotation, DISPC_COLOR_COMPONENT_UV);
1577
2a5561b1
AT		 1578 if (plane != OMAP_DSS_WB)
1579 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1580 (scale_x || scale_y) ? 1 : 0, 8, 8);
1581
0d66cbb5
AJ		 1582 /* set H scaling */
1583 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1584 /* set V scaling */
1585 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1586}
1587
f0e5caab 1588static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1589 u16 orig_width, u16 orig_height,
1590 u16 out_width, u16 out_height,
1591 bool ilace, bool five_taps,
1592 bool fieldmode, enum omap_color_mode color_mode,
1593 u8 rotation)
1594{
1595 BUG_ON(plane == OMAP_DSS_GFX);
1596
f0e5caab 1597 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1598 orig_width, orig_height,
1599 out_width, out_height,
1600 ilace, five_taps,
1601 fieldmode, color_mode,
1602 rotation);
1603
f0e5caab 1604 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1605 orig_width, orig_height,
1606 out_width, out_height,
1607 ilace, five_taps,
1608 fieldmode, color_mode,
1609 rotation);
1610}
1611
f0e5caab 1612static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1613 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1614 bool mirroring, enum omap_color_mode color_mode)
1615{
87a7484b
AT		 1616 bool row_repeat = false;
1617 int vidrot = 0;
1618
80c39712
TV		 1619 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1621
1622 if (mirroring) {
1623 switch (rotation) {
1624 case OMAP_DSS_ROT_0:
1625 vidrot = 2;
1626 break;
1627 case OMAP_DSS_ROT_90:
1628 vidrot = 1;
1629 break;
1630 case OMAP_DSS_ROT_180:
1631 vidrot = 0;
1632 break;
1633 case OMAP_DSS_ROT_270:
1634 vidrot = 3;
1635 break;
1636 }
1637 } else {
1638 switch (rotation) {
1639 case OMAP_DSS_ROT_0:
1640 vidrot = 0;
1641 break;
1642 case OMAP_DSS_ROT_90:
1643 vidrot = 1;
1644 break;
1645 case OMAP_DSS_ROT_180:
1646 vidrot = 2;
1647 break;
1648 case OMAP_DSS_ROT_270:
1649 vidrot = 3;
1650 break;
1651 }
1652 }
1653
80c39712 1654 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1655 row_repeat = true;
80c39712 1656 else
87a7484b 1657 row_repeat = false;
80c39712 1658 }
87a7484b 1659
9b372c2d 1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1661 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1662 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1663 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1664
1665 if (color_mode == OMAP_DSS_COLOR_NV12) {
1666 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1667 (rotation == OMAP_DSS_ROT_0 ||
1668 rotation == OMAP_DSS_ROT_180);
1669 /* DOUBLESTRIDE */
1670 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1671 }
1672
80c39712
TV		 1673}
1674
1675static int color_mode_to_bpp(enum omap_color_mode color_mode)
1676{
1677 switch (color_mode) {
1678 case OMAP_DSS_COLOR_CLUT1:
1679 return 1;
1680 case OMAP_DSS_COLOR_CLUT2:
1681 return 2;
1682 case OMAP_DSS_COLOR_CLUT4:
1683 return 4;
1684 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1685 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1686 return 8;
1687 case OMAP_DSS_COLOR_RGB12U:
1688 case OMAP_DSS_COLOR_RGB16:
1689 case OMAP_DSS_COLOR_ARGB16:
1690 case OMAP_DSS_COLOR_YUV2:
1691 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1692 case OMAP_DSS_COLOR_RGBA16:
1693 case OMAP_DSS_COLOR_RGBX16:
1694 case OMAP_DSS_COLOR_ARGB16_1555:
1695 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1696 return 16;
1697 case OMAP_DSS_COLOR_RGB24P:
1698 return 24;
1699 case OMAP_DSS_COLOR_RGB24U:
1700 case OMAP_DSS_COLOR_ARGB32:
1701 case OMAP_DSS_COLOR_RGBA32:
1702 case OMAP_DSS_COLOR_RGBX32:
1703 return 32;
1704 default:
1705 BUG();
c6eee968 1706 return 0;
80c39712
TV		 1707 }
1708}
1709
1710static s32 pixinc(int pixels, u8 ps)
1711{
1712 if (pixels == 1)
1713 return 1;
1714 else if (pixels > 1)
1715 return 1 + (pixels - 1) * ps;
1716 else if (pixels < 0)
1717 return 1 - (-pixels + 1) * ps;
1718 else
1719 BUG();
c6eee968 1720 return 0;
80c39712
TV		 1721}
1722
1723static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1724 u16 screen_width,
1725 u16 width, u16 height,
1726 enum omap_color_mode color_mode, bool fieldmode,
1727 unsigned int field_offset,
1728 unsigned *offset0, unsigned *offset1,
aed74b55 1729 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1730{
1731 u8 ps;
1732
1733 /* FIXME CLUT formats */
1734 switch (color_mode) {
1735 case OMAP_DSS_COLOR_CLUT1:
1736 case OMAP_DSS_COLOR_CLUT2:
1737 case OMAP_DSS_COLOR_CLUT4:
1738 case OMAP_DSS_COLOR_CLUT8:
1739 BUG();
1740 return;
1741 case OMAP_DSS_COLOR_YUV2:
1742 case OMAP_DSS_COLOR_UYVY:
1743 ps = 4;
1744 break;
1745 default:
1746 ps = color_mode_to_bpp(color_mode) / 8;
1747 break;
1748 }
1749
1750 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1751 width, height);
1752
1753 /*
1754 * field 0 = even field = bottom field
1755 * field 1 = odd field = top field
1756 */
1757 switch (rotation + mirror * 4) {
1758 case OMAP_DSS_ROT_0:
1759 case OMAP_DSS_ROT_180:
1760 /*
1761 * If the pixel format is YUV or UYVY divide the width
1762 * of the image by 2 for 0 and 180 degree rotation.
1763 */
1764 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1765 color_mode == OMAP_DSS_COLOR_UYVY)
1766 width = width >> 1;
1767 case OMAP_DSS_ROT_90:
1768 case OMAP_DSS_ROT_270:
1769 *offset1 = 0;
1770 if (field_offset)
1771 *offset0 = field_offset * screen_width * ps;
1772 else
1773 *offset0 = 0;
1774
aed74b55
CM		 1775 *row_inc = pixinc(1 +
1776 (y_predecim * screen_width - x_predecim * width) +
1777 (fieldmode ? screen_width : 0), ps);
1778 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1779 break;
1780
1781 case OMAP_DSS_ROT_0 + 4:
1782 case OMAP_DSS_ROT_180 + 4:
1783 /* If the pixel format is YUV or UYVY divide the width
1784 * of the image by 2 for 0 degree and 180 degree
1785 */
1786 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1787 color_mode == OMAP_DSS_COLOR_UYVY)
1788 width = width >> 1;
1789 case OMAP_DSS_ROT_90 + 4:
1790 case OMAP_DSS_ROT_270 + 4:
1791 *offset1 = 0;
1792 if (field_offset)
1793 *offset0 = field_offset * screen_width * ps;
1794 else
1795 *offset0 = 0;
aed74b55
CM		 1796 *row_inc = pixinc(1 -
1797 (y_predecim * screen_width + x_predecim * width) -
1798 (fieldmode ? screen_width : 0), ps);
1799 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1800 break;
1801
1802 default:
1803 BUG();
c6eee968 1804 return;
80c39712
TV		 1805 }
1806}
1807
1808static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1809 u16 screen_width,
1810 u16 width, u16 height,
1811 enum omap_color_mode color_mode, bool fieldmode,
1812 unsigned int field_offset,
1813 unsigned *offset0, unsigned *offset1,
aed74b55 1814 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1815{
1816 u8 ps;
1817 u16 fbw, fbh;
1818
1819 /* FIXME CLUT formats */
1820 switch (color_mode) {
1821 case OMAP_DSS_COLOR_CLUT1:
1822 case OMAP_DSS_COLOR_CLUT2:
1823 case OMAP_DSS_COLOR_CLUT4:
1824 case OMAP_DSS_COLOR_CLUT8:
1825 BUG();
1826 return;
1827 default:
1828 ps = color_mode_to_bpp(color_mode) / 8;
1829 break;
1830 }
1831
1832 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1833 width, height);
1834
1835 /* width & height are overlay sizes, convert to fb sizes */
1836
1837 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1838 fbw = width;
1839 fbh = height;
1840 } else {
1841 fbw = height;
1842 fbh = width;
1843 }
1844
1845 /*
1846 * field 0 = even field = bottom field
1847 * field 1 = odd field = top field
1848 */
1849 switch (rotation + mirror * 4) {
1850 case OMAP_DSS_ROT_0:
1851 *offset1 = 0;
1852 if (field_offset)
1853 *offset0 = *offset1 + field_offset * screen_width * ps;
1854 else
1855 *offset0 = *offset1;
aed74b55
CM		 1856 *row_inc = pixinc(1 +
1857 (y_predecim * screen_width - fbw * x_predecim) +
1858 (fieldmode ? screen_width : 0), ps);
1859 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1860 color_mode == OMAP_DSS_COLOR_UYVY)
1861 *pix_inc = pixinc(x_predecim, 2 * ps);
1862 else
1863 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1864 break;
1865 case OMAP_DSS_ROT_90:
1866 *offset1 = screen_width * (fbh - 1) * ps;
1867 if (field_offset)
1868 *offset0 = *offset1 + field_offset * ps;
1869 else
1870 *offset0 = *offset1;
aed74b55
CM		 1871 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1872 y_predecim + (fieldmode ? 1 : 0), ps);
1873 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1874 break;
1875 case OMAP_DSS_ROT_180:
1876 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1877 if (field_offset)
1878 *offset0 = *offset1 - field_offset * screen_width * ps;
1879 else
1880 *offset0 = *offset1;
1881 *row_inc = pixinc(-1 -
aed74b55
CM		 1882 (y_predecim * screen_width - fbw * x_predecim) -
1883 (fieldmode ? screen_width : 0), ps);
1884 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1885 color_mode == OMAP_DSS_COLOR_UYVY)
1886 *pix_inc = pixinc(-x_predecim, 2 * ps);
1887 else
1888 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1889 break;
1890 case OMAP_DSS_ROT_270:
1891 *offset1 = (fbw - 1) * ps;
1892 if (field_offset)
1893 *offset0 = *offset1 - field_offset * ps;
1894 else
1895 *offset0 = *offset1;
aed74b55
CM		 1896 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1897 y_predecim - (fieldmode ? 1 : 0), ps);
1898 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1899 break;
1900
1901 /* mirroring */
1902 case OMAP_DSS_ROT_0 + 4:
1903 *offset1 = (fbw - 1) * ps;
1904 if (field_offset)
1905 *offset0 = *offset1 + field_offset * screen_width * ps;
1906 else
1907 *offset0 = *offset1;
aed74b55 1908 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1909 (fieldmode ? screen_width : 0),
1910 ps);
aed74b55
CM		 1911 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1912 color_mode == OMAP_DSS_COLOR_UYVY)
1913 *pix_inc = pixinc(-x_predecim, 2 * ps);
1914 else
1915 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1916 break;
1917
1918 case OMAP_DSS_ROT_90 + 4:
1919 *offset1 = 0;
1920 if (field_offset)
1921 *offset0 = *offset1 + field_offset * ps;
1922 else
1923 *offset0 = *offset1;
aed74b55
CM		 1924 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1925 y_predecim + (fieldmode ? 1 : 0),
80c39712 1926 ps);
aed74b55 1927 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1928 break;
1929
1930 case OMAP_DSS_ROT_180 + 4:
1931 *offset1 = screen_width * (fbh - 1) * ps;
1932 if (field_offset)
1933 *offset0 = *offset1 - field_offset * screen_width * ps;
1934 else
1935 *offset0 = *offset1;
aed74b55 1936 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1937 (fieldmode ? screen_width : 0),
1938 ps);
aed74b55
CM		 1939 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1940 color_mode == OMAP_DSS_COLOR_UYVY)
1941 *pix_inc = pixinc(x_predecim, 2 * ps);
1942 else
1943 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1944 break;
1945
1946 case OMAP_DSS_ROT_270 + 4:
1947 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1948 if (field_offset)
1949 *offset0 = *offset1 - field_offset * ps;
1950 else
1951 *offset0 = *offset1;
aed74b55
CM		 1952 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1953 y_predecim - (fieldmode ? 1 : 0),
80c39712 1954 ps);
aed74b55 1955 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1956 break;
1957
1958 default:
1959 BUG();
c6eee968 1960 return;
80c39712
TV		 1961 }
1962}
1963
65e006ff
CM		 1964static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1965 enum omap_color_mode color_mode, bool fieldmode,
1966 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1967 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1968{
1969 u8 ps;
1970
1971 switch (color_mode) {
1972 case OMAP_DSS_COLOR_CLUT1:
1973 case OMAP_DSS_COLOR_CLUT2:
1974 case OMAP_DSS_COLOR_CLUT4:
1975 case OMAP_DSS_COLOR_CLUT8:
1976 BUG();
1977 return;
1978 default:
1979 ps = color_mode_to_bpp(color_mode) / 8;
1980 break;
1981 }
1982
1983 DSSDBG("scrw %d, width %d\n", screen_width, width);
1984
1985 /*
1986 * field 0 = even field = bottom field
1987 * field 1 = odd field = top field
1988 */
1989 *offset1 = 0;
1990 if (field_offset)
1991 *offset0 = *offset1 + field_offset * screen_width * ps;
1992 else
1993 *offset0 = *offset1;
1994 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1995 (fieldmode ? screen_width : 0), ps);
1996 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1997 color_mode == OMAP_DSS_COLOR_UYVY)
1998 *pix_inc = pixinc(x_predecim, 2 * ps);
1999 else
2000 *pix_inc = pixinc(x_predecim, ps);
2001}
2002
7faa9233
CM		 2003/*
2004 * This function is used to avoid synclosts in OMAP3, because of some
2005 * undocumented horizontal position and timing related limitations.
2006 */
465ec13f 2007static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 2008 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 2009 u16 width, u16 height, u16 out_width, u16 out_height,
2010 bool five_taps)
7faa9233 2011{
230edc03 2012 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2013 unsigned long nonactive;
7faa9233
CM		 2014 static const u8 limits[3] = { 8, 10, 20 };
2015 u64 val, blank;
2016 int i;
2017
81ab95b7 2018 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2019
2020 i = 0;
2021 if (out_height < height)
2022 i++;
2023 if (out_width < width)
2024 i++;
81ab95b7 2025 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2026 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2027 if (blank <= limits[i])
2028 return -EINVAL;
2029
e4998634
ID		 2030 /* FIXME add checks for 3-tap filter once the limitations are known */
2031 if (!five_taps)
2032 return 0;
2033
7faa9233
CM		 2034 /*
2035 * Pixel data should be prepared before visible display point starts.
2036 * So, atleast DS-2 lines must have already been fetched by DISPC
2037 * during nonactive - pos_x period.
2038 */
2039 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2040 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2041 val, max(0, ds - 2) * width);
2042 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2043 return -EINVAL;
2044
2045 /*
2046 * All lines need to be refilled during the nonactive period of which
2047 * only one line can be loaded during the active period. So, atleast
2048 * DS - 1 lines should be loaded during nonactive period.
2049 */
2050 val = div_u64((u64)nonactive * lclk, pclk);
2051 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2052 val, max(0, ds - 1) * width);
2053 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2054 return -EINVAL;
2055
2056 return 0;
2057}
2058
8702ee50 2059static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2060 const struct omap_video_timings *mgr_timings, u16 width,
2061 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2062 enum omap_color_mode color_mode)
80c39712 2063{
8b53d991 2064 u32 core_clk = 0;
3e8a6ff2 2065 u64 tmp;
80c39712 2066
7282f1b7
CM		 2067 if (height <= out_height && width <= out_width)
2068 return (unsigned long) pclk;
2069
80c39712 2070 if (height > out_height) {
81ab95b7 2071 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2072
2073 tmp = pclk * height * out_width;
2074 do_div(tmp, 2 * out_height * ppl);
8b53d991 2075 core_clk = tmp;
80c39712 2076
2d9c5597
VS		 2077 if (height > 2 * out_height) {
2078 if (ppl == out_width)
2079 return 0;
2080
80c39712
TV		 2081 tmp = pclk * (height - 2 * out_height) * out_width;
2082 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2083 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2084 }
2085 }
2086
2087 if (width > out_width) {
2088 tmp = pclk * width;
2089 do_div(tmp, out_width);
8b53d991 2090 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2091
2092 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2093 core_clk <<= 1;
80c39712
TV		 2094 }
2095
8b53d991 2096 return core_clk;
80c39712
TV		 2097}
2098
8702ee50 2099static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2100 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2101{
dcbe765b
CM		 2102 if (height > out_height && width > out_width)
2103 return pclk * 4;
2104 else
2105 return pclk * 2;
2106}
2107
8702ee50 2108static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2109 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2110{
2111 unsigned int hf, vf;
2112
2113 /*
2114 * FIXME how to determine the 'A' factor
2115 * for the no downscaling case ?
2116 */
2117
2118 if (width > 3 * out_width)
2119 hf = 4;
2120 else if (width > 2 * out_width)
2121 hf = 3;
2122 else if (width > out_width)
2123 hf = 2;
2124 else
2125 hf = 1;
80c39712
TV		 2126 if (height > out_height)
2127 vf = 2;
2128 else
2129 vf = 1;
2130
dcbe765b
CM		 2131 return pclk * vf * hf;
2132}
2133
8702ee50 2134static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2135 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2136{
8ba85306
AT		 2137 /*
2138 * If the overlay/writeback is in mem to mem mode, there are no
2139 * downscaling limitations with respect to pixel clock, return 1 as
2140 * required core clock to represent that we have sufficient enough
2141 * core clock to do maximum downscaling
2142 */
2143 if (mem_to_mem)
2144 return 1;
2145
dcbe765b
CM		 2146 if (width > out_width)
2147 return DIV_ROUND_UP(pclk, out_width) * width;
2148 else
2149 return pclk;
2150}
2151
0c6921de 2152static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2153 const struct omap_video_timings *mgr_timings,
2154 u16 width, u16 height, u16 out_width, u16 out_height,
2155 enum omap_color_mode color_mode, bool *five_taps,
2156 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2157 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2158{
2159 int error;
2160 u16 in_width, in_height;
2161 int min_factor = min(*decim_x, *decim_y);
2162 const int maxsinglelinewidth =
2163 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2164
dcbe765b
CM		 2165 *five_taps = false;
2166
2167 do {
eec77da2
TV		 2168 in_height = height / *decim_y;
2169 in_width = width / *decim_x;
8702ee50 2170 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2171 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2172 error = (in_width > maxsinglelinewidth || !*core_clk ||
2173 *core_clk > dispc_core_clk_rate());
2174 if (error) {
2175 if (*decim_x == *decim_y) {
2176 *decim_x = min_factor;
2177 ++*decim_y;
2178 } else {
2179 swap(*decim_x, *decim_y);
2180 if (*decim_x < *decim_y)
2181 ++*decim_x;
2182 }
2183 }
2184 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2185
2186 if (in_width > maxsinglelinewidth) {
2187 DSSERR("Cannot scale max input width exceeded");
2188 return -EINVAL;
2189 }
2190 return 0;
2191}
2192
0c6921de 2193static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2194 const struct omap_video_timings *mgr_timings,
2195 u16 width, u16 height, u16 out_width, u16 out_height,
2196 enum omap_color_mode color_mode, bool *five_taps,
2197 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2198 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2199{
2200 int error;
2201 u16 in_width, in_height;
2202 int min_factor = min(*decim_x, *decim_y);
2203 const int maxsinglelinewidth =
2204 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2205
2206 do {
eec77da2
TV		 2207 in_height = height / *decim_y;
2208 in_width = width / *decim_x;
e4998634 2209 *five_taps = in_height > out_height;
dcbe765b
CM		 2210
2211 if (in_width > maxsinglelinewidth)
2212 if (in_height > out_height &&
2213 in_height < out_height * 2)
2214 *five_taps = false;
e4998634
ID		 2215again:
2216 if (*five_taps)
2217 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2218 in_width, in_height, out_width,
2219 out_height, color_mode);
2220 else
8702ee50 2221 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2222 in_height, out_width, out_height,
2223 mem_to_mem);
dcbe765b 2224
e4998634
ID		 2225 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2226 pos_x, in_width, in_height, out_width,
2227 out_height, *five_taps);
2228 if (error && *five_taps) {
2229 *five_taps = false;
2230 goto again;
2231 }
2232
dcbe765b
CM		 2233 error = (error || in_width > maxsinglelinewidth * 2 ||
2234 (in_width > maxsinglelinewidth && *five_taps) ||
2235 !*core_clk || *core_clk > dispc_core_clk_rate());
2236 if (error) {
2237 if (*decim_x == *decim_y) {
2238 *decim_x = min_factor;
2239 ++*decim_y;
2240 } else {
2241 swap(*decim_x, *decim_y);
2242 if (*decim_x < *decim_y)
2243 ++*decim_x;
2244 }
2245 }
2246 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2247
465ec13f 2248 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
e4998634 2249 height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2250 DSSERR("horizontal timing too tight\n");
2251 return -EINVAL;
7282f1b7 2252 }
dcbe765b
CM		 2253
2254 if (in_width > (maxsinglelinewidth * 2)) {
2255 DSSERR("Cannot setup scaling");
2256 DSSERR("width exceeds maximum width possible");
2257 return -EINVAL;
2258 }
2259
2260 if (in_width > maxsinglelinewidth && *five_taps) {
2261 DSSERR("cannot setup scaling with five taps");
2262 return -EINVAL;
2263 }
2264 return 0;
2265}
2266
0c6921de 2267static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2268 const struct omap_video_timings *mgr_timings,
2269 u16 width, u16 height, u16 out_width, u16 out_height,
2270 enum omap_color_mode color_mode, bool *five_taps,
2271 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2272 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2273{
2274 u16 in_width, in_width_max;
2275 int decim_x_min = *decim_x;
eec77da2 2276 u16 in_height = height / *decim_y;
dcbe765b
CM		 2277 const int maxsinglelinewidth =
2278 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2279 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2280
5d501085
AT		 2281 if (mem_to_mem) {
2282 in_width_max = out_width * maxdownscale;
2283 } else {
8ba85306
AT		 2284 in_width_max = dispc_core_clk_rate() /
2285 DIV_ROUND_UP(pclk, out_width);
5d501085 2286 }
dcbe765b 2287
dcbe765b
CM		 2288 *decim_x = DIV_ROUND_UP(width, in_width_max);
2289
2290 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2291 if (*decim_x > *x_predecim)
2292 return -EINVAL;
2293
2294 do {
eec77da2 2295 in_width = width / *decim_x;
dcbe765b
CM		 2296 } while (*decim_x <= *x_predecim &&
2297 in_width > maxsinglelinewidth && ++*decim_x);
2298
2299 if (in_width > maxsinglelinewidth) {
2300 DSSERR("Cannot scale width exceeds max line width");
2301 return -EINVAL;
2302 }
2303
8702ee50 2304 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2305 out_width, out_height, mem_to_mem);
dcbe765b 2306 return 0;
80c39712
TV		 2307}
2308
74e16458 2309static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2310 enum omap_overlay_caps caps,
81ab95b7
AT		 2311 const struct omap_video_timings *mgr_timings,
2312 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2313 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2314 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2315 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2316{
0373cac6 2317 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2318 const int max_decim_limit = 16;
8b53d991 2319 unsigned long core_clk = 0;
dcbe765b 2320 int decim_x, decim_y, ret;
79ad75f2 2321
f95cb5eb
TV		 2322 if (width == out_width && height == out_height)
2323 return 0;
2324
4e1d3ca0
TV		 2325 if (pclk == 0 || mgr_timings->pixelclock == 0) {
2326 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2327 return -EINVAL;
2328 }
2329
5b54ed3e 2330 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2331 return -EINVAL;
79ad75f2 2332
74e16458 2333 if (mem_to_mem) {
1c031441
AT		 2334 *x_predecim = *y_predecim = 1;
2335 } else {
2336 *x_predecim = max_decim_limit;
2337 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2338 dss_has_feature(FEAT_BURST_2D)) ?
2339 2 : max_decim_limit;
2340 }
aed74b55
CM		 2341
2342 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2343 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2344 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2345 color_mode == OMAP_DSS_COLOR_CLUT8) {
2346 *x_predecim = 1;
2347 *y_predecim = 1;
2348 *five_taps = false;
2349 return 0;
2350 }
2351
2352 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2353 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2354
aed74b55 2355 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2356 return -EINVAL;
2357
aed74b55 2358 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2359 return -EINVAL;
2360
0c6921de 2361 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2362 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2363 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2364 mem_to_mem);
dcbe765b
CM		 2365 if (ret)
2366 return ret;
79ad75f2 2367
8b53d991
CM		 2368 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2369 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2370
8b53d991 2371 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2372 DSSERR("failed to set up scaling, "
8b53d991
CM		 2373 "required core clk rate = %lu Hz, "
2374 "current core clk rate = %lu Hz\n",
2375 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2376 return -EINVAL;
2377 }
2378
aed74b55
CM		 2379 *x_predecim = decim_x;
2380 *y_predecim = decim_y;
79ad75f2
AT		 2381 return 0;
2382}
2383
f9b719b6
TV		 2384int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2385 const struct omap_overlay_info *oi,
2386 const struct omap_video_timings *timings,
2387 int *x_predecim, int *y_predecim)
2388{
2389 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2390 bool five_taps = true;
62a83183 2391 bool fieldmode = false;
f9b719b6
TV		 2392 u16 in_height = oi->height;
2393 u16 in_width = oi->width;
2394 bool ilace = timings->interlace;
2395 u16 out_width, out_height;
2396 int pos_x = oi->pos_x;
2397 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2398 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2399
2400 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2401 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2402
2403 if (ilace && oi->height == out_height)
62a83183 2404 fieldmode = true;
f9b719b6
TV		 2405
2406 if (ilace) {
2407 if (fieldmode)
2408 in_height /= 2;
2409 out_height /= 2;
2410
2411 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2412 in_height, out_height);
2413 }
2414
2415 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2416 return -EINVAL;
2417
2418 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2419 in_height, out_width, out_height, oi->color_mode,
2420 &five_taps, x_predecim, y_predecim, pos_x,
2421 oi->rotation_type, false);
2422}
348be69d 2423EXPORT_SYMBOL(dispc_ovl_check);
f9b719b6 2424
84a880fd 2425static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2426 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2427 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2428 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2429 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2430 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2431 bool replication, const struct omap_video_timings *mgr_timings,
2432 bool mem_to_mem)
80c39712 2433{
7282f1b7 2434 bool five_taps = true;
62a83183 2435 bool fieldmode = false;
79ad75f2 2436 int r, cconv = 0;
80c39712
TV		 2437 unsigned offset0, offset1;
2438 s32 row_inc;
2439 s32 pix_inc;
6be0d73e 2440 u16 frame_width, frame_height;
80c39712 2441 unsigned int field_offset = 0;
84a880fd
AT		 2442 u16 in_height = height;
2443 u16 in_width = width;
aed74b55 2444 int x_predecim = 1, y_predecim = 1;
8050cbe4 2445 bool ilace = mgr_timings->interlace;
74e16458
TV		 2446 unsigned long pclk = dispc_plane_pclk_rate(plane);
2447 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2448
e566658f 2449 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
80c39712
TV		 2450 return -EINVAL;
2451
84a880fd
AT		 2452 out_width = out_width == 0 ? width : out_width;
2453 out_height = out_height == 0 ? height : out_height;
cf073668 2454
84a880fd 2455 if (ilace && height == out_height)
62a83183 2456 fieldmode = true;
80c39712
TV		 2457
2458 if (ilace) {
2459 if (fieldmode)
aed74b55 2460 in_height /= 2;
8eeb7019 2461 pos_y /= 2;
aed74b55 2462 out_height /= 2;
80c39712
TV		 2463
2464 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2465 "out_height %d\n", in_height, pos_y,
2466 out_height);
80c39712
TV		 2467 }
2468
84a880fd 2469 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2470 return -EINVAL;
2471
74e16458 2472 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2473 in_height, out_width, out_height, color_mode,
2474 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2475 rotation_type, mem_to_mem);
79ad75f2
AT		 2476 if (r)
2477 return r;
80c39712 2478
eec77da2
TV		 2479 in_width = in_width / x_predecim;
2480 in_height = in_height / y_predecim;
aed74b55 2481
84a880fd
AT		 2482 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2483 color_mode == OMAP_DSS_COLOR_UYVY ||
2484 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2485 cconv = 1;
80c39712
TV		 2486
2487 if (ilace && !fieldmode) {
2488 /*
2489 * when downscaling the bottom field may have to start several
2490 * source lines below the top field. Unfortunately ACCUI
2491 * registers will only hold the fractional part of the offset
2492 * so the integer part must be added to the base address of the
2493 * bottom field.
2494 */
aed74b55 2495 if (!in_height || in_height == out_height)
80c39712
TV		 2496 field_offset = 0;
2497 else
aed74b55 2498 field_offset = in_height / out_height / 2;
80c39712
TV		 2499 }
2500
2501 /* Fields are independent but interleaved in memory. */
2502 if (fieldmode)
2503 field_offset = 1;
2504
c6eee968
TV		 2505 offset0 = 0;
2506 offset1 = 0;
2507 row_inc = 0;
2508 pix_inc = 0;
2509
6be0d73e
AT		 2510 if (plane == OMAP_DSS_WB) {
2511 frame_width = out_width;
2512 frame_height = out_height;
2513 } else {
2514 frame_width = in_width;
2515 frame_height = height;
2516 }
2517
84a880fd 2518 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2519 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2520 color_mode, fieldmode, field_offset,
65e006ff
CM		 2521 &offset0, &offset1, &row_inc, &pix_inc,
2522 x_predecim, y_predecim);
84a880fd 2523 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2524 calc_dma_rotation_offset(rotation, mirror, screen_width,
2525 frame_width, frame_height,
84a880fd 2526 color_mode, fieldmode, field_offset,
aed74b55
CM		 2527 &offset0, &offset1, &row_inc, &pix_inc,
2528 x_predecim, y_predecim);
80c39712 2529 else
84a880fd 2530 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2531 screen_width, frame_width, frame_height,
84a880fd 2532 color_mode, fieldmode, field_offset,
aed74b55
CM		 2533 &offset0, &offset1, &row_inc, &pix_inc,
2534 x_predecim, y_predecim);
80c39712
TV		 2535
2536 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2537 offset0, offset1, row_inc, pix_inc);
2538
84a880fd 2539 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2540
84a880fd 2541 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2542
84a880fd
AT		 2543 dispc_ovl_set_ba0(plane, paddr + offset0);
2544 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2545
84a880fd
AT		 2546 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2547 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2548 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2549 }
2550
f0e5caab
TV		 2551 dispc_ovl_set_row_inc(plane, row_inc);
2552 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2553
84a880fd 2554 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2555 in_height, out_width, out_height);
80c39712 2556
84a880fd 2557 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2558
78b687fc 2559 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2560
5b54ed3e 2561 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2562 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2563 out_height, ilace, five_taps, fieldmode,
84a880fd 2564 color_mode, rotation);
78b687fc 2565 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2566 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2567 }
2568
c35eeb2e
AT		 2569 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2570 color_mode);
80c39712 2571
84a880fd
AT		 2572 dispc_ovl_set_zorder(plane, caps, zorder);
2573 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2574 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2575
d79db853 2576 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2577
80c39712
TV		 2578 return 0;
2579}
2580
84a880fd 2581int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2582 bool replication, const struct omap_video_timings *mgr_timings,
2583 bool mem_to_mem)
84a880fd
AT		 2584{
2585 int r;
16bf20c7 2586 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2587 enum omap_channel channel;
2588
2589 channel = dispc_ovl_get_channel_out(plane);
2590
24f13a66
AB		 2591 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2592 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2593 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
84a880fd
AT		 2594 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2595 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2596
16bf20c7 2597 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2598 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2599 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2600 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2601 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2602
2603 return r;
2604}
348be69d 2605EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2606
749feffa 2607int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2608 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2609{
2610 int r;
9e4a0fc7 2611 u32 l;
749feffa
AT		 2612 enum omap_plane plane = OMAP_DSS_WB;
2613 const int pos_x = 0, pos_y = 0;
2614 const u8 zorder = 0, global_alpha = 0;
2615 const bool replication = false;
9e4a0fc7 2616 bool truncation;
749feffa
AT		 2617 int in_width = mgr_timings->x_res;
2618 int in_height = mgr_timings->y_res;
2619 enum omap_overlay_caps caps =
2620 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2621
2622 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2623 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2624 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2625 wi->mirror);
2626
2627 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2628 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2629 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2630 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2631 replication, mgr_timings, mem_to_mem);
2632
2633 switch (wi->color_mode) {
2634 case OMAP_DSS_COLOR_RGB16:
2635 case OMAP_DSS_COLOR_RGB24P:
2636 case OMAP_DSS_COLOR_ARGB16:
2637 case OMAP_DSS_COLOR_RGBA16:
2638 case OMAP_DSS_COLOR_RGB12U:
2639 case OMAP_DSS_COLOR_ARGB16_1555:
2640 case OMAP_DSS_COLOR_XRGB16_1555:
2641 case OMAP_DSS_COLOR_RGBX16:
2642 truncation = true;
2643 break;
2644 default:
2645 truncation = false;
2646 break;
2647 }
2648
2649 /* setup extra DISPC_WB_ATTRIBUTES */
2650 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2651 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2652 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2653 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2654
2655 return r;
2656}
2657
f0e5caab 2658int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2659{
e6d80f95
TV		 2660 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2661
9b372c2d 2662 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2663
2664 return 0;
80c39712 2665}
348be69d 2666EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2667
04bd8ac1
TV		 2668bool dispc_ovl_enabled(enum omap_plane plane)
2669{
2670 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2671}
348be69d 2672EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2673
f1a813d3 2674void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2675{
efa70b3b
CM		 2676 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2677 /* flush posted write */
2678 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2679}
348be69d 2680EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2681
65398511
TV		 2682bool dispc_mgr_is_enabled(enum omap_channel channel)
2683{
2684 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2685}
348be69d 2686EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2687
0b23e5b8
AT		 2688void dispc_wb_enable(bool enable)
2689{
916188a4 2690 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2691}
2692
2693bool dispc_wb_is_enabled(void)
2694{
916188a4 2695 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2696}
2697
fb2cec1f 2698static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2699{
6ced40bf
AT		 2700 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2701 return;
2702
80c39712 2703 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2704}
2705
2706void dispc_lcd_enable_signal(bool enable)
2707{
6ced40bf
AT		 2708 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2709 return;
2710
80c39712 2711 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2712}
2713
2714void dispc_pck_free_enable(bool enable)
2715{
6ced40bf
AT		 2716 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2717 return;
2718
80c39712 2719 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2720}
2721
fb2cec1f 2722static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2723{
efa70b3b 2724 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2725}
2726
2727
fb2cec1f 2728static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2729{
d21f43bc 2730 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2731}
2732
2733void dispc_set_loadmode(enum omap_dss_load_mode mode)
2734{
80c39712 2735 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2736}
2737
2738
c64dca40 2739static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2740{
8613b000 2741 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2742}
2743
c64dca40 2744static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2745 enum omap_dss_trans_key_type type,
2746 u32 trans_key)
2747{
efa70b3b 2748 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2749
8613b000 2750 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2751}
2752
c64dca40 2753static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2754{
efa70b3b 2755 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2756}
11354dd5 2757
c64dca40
TV		 2758static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2759 bool enable)
80c39712 2760{
11354dd5 2761 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2762 return;
2763
80c39712
TV		 2764 if (ch == OMAP_DSS_CHANNEL_LCD)
2765 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2766 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2767 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2768}
11354dd5 2769
c64dca40 2770void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2771 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2772{
2773 dispc_mgr_set_default_color(channel, info->default_color);
2774 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2775 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2776 dispc_mgr_enable_alpha_fixed_zorder(channel,
2777 info->partial_alpha_enabled);
2778 if (dss_has_feature(FEAT_CPR)) {
2779 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2780 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2781 }
2782}
348be69d 2783EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 2784
fb2cec1f 2785static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2786{
2787 int code;
2788
2789 switch (data_lines) {
2790 case 12:
2791 code = 0;
2792 break;
2793 case 16:
2794 code = 1;
2795 break;
2796 case 18:
2797 code = 2;
2798 break;
2799 case 24:
2800 code = 3;
2801 break;
2802 default:
2803 BUG();
2804 return;
2805 }
2806
efa70b3b 2807 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2808}
2809
fb2cec1f 2810static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2811{
2812 u32 l;
569969d6 2813 int gpout0, gpout1;
80c39712
TV		 2814
2815 switch (mode) {
569969d6
AT		 2816 case DSS_IO_PAD_MODE_RESET:
2817 gpout0 = 0;
2818 gpout1 = 0;
80c39712 2819 break;
569969d6
AT		 2820 case DSS_IO_PAD_MODE_RFBI:
2821 gpout0 = 1;
80c39712
TV		 2822 gpout1 = 0;
2823 break;
569969d6
AT		 2824 case DSS_IO_PAD_MODE_BYPASS:
2825 gpout0 = 1;
80c39712
TV		 2826 gpout1 = 1;
2827 break;
80c39712
TV		 2828 default:
2829 BUG();
2830 return;
2831 }
2832
569969d6
AT		 2833 l = dispc_read_reg(DISPC_CONTROL);
2834 l = FLD_MOD(l, gpout0, 15, 15);
2835 l = FLD_MOD(l, gpout1, 16, 16);
2836 dispc_write_reg(DISPC_CONTROL, l);
2837}
2838
fb2cec1f 2839static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2840{
efa70b3b 2841 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2842}
2843
fb2cec1f
TV		 2844void dispc_mgr_set_lcd_config(enum omap_channel channel,
2845 const struct dss_lcd_mgr_config *config)
2846{
2847 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2848
2849 dispc_mgr_enable_stallmode(channel, config->stallmode);
2850 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2851
2852 dispc_mgr_set_clock_div(channel, &config->clock_info);
2853
2854 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2855
2856 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2857
2858 dispc_mgr_set_lcd_type_tft(channel);
2859}
348be69d 2860EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 2861
8f366162
AT		 2862static bool _dispc_mgr_size_ok(u16 width, u16 height)
2863{
33b89928
AT		 2864 return width <= dispc.feat->mgr_width_max &&
2865 height <= dispc.feat->mgr_height_max;
8f366162
AT		 2866}
2867
80c39712
TV		 2868static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2869 int vsw, int vfp, int vbp)
2870{
dcbe765b
CM		 2871 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2872 hfp < 1 || hfp > dispc.feat->hp_max ||
2873 hbp < 1 || hbp > dispc.feat->hp_max ||
2874 vsw < 1 || vsw > dispc.feat->sw_max ||
2875 vfp < 0 || vfp > dispc.feat->vp_max ||
2876 vbp < 0 || vbp > dispc.feat->vp_max)
2877 return false;
80c39712
TV		 2878 return true;
2879}
2880
ca5ca69c
AT		 2881static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2882 unsigned long pclk)
2883{
2884 if (dss_mgr_is_lcd(channel))
2885 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2886 else
2887 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2888}
2889
8f366162 2890bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2891 const struct omap_video_timings *timings)
80c39712 2892{
eadd33bb
TV		 2893 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
2894 return false;
8f366162 2895
eadd33bb
TV		 2896 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
2897 return false;
ca5ca69c
AT		 2898
2899 if (dss_mgr_is_lcd(channel)) {
beb8384d 2900 /* TODO: OMAP4+ supports interlace for LCD outputs */
eadd33bb
TV		 2901 if (timings->interlace)
2902 return false;
beb8384d 2903
eadd33bb 2904 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
ca5ca69c 2905 timings->hbp, timings->vsw, timings->vfp,
eadd33bb
TV		 2906 timings->vbp))
2907 return false;
ca5ca69c 2908 }
8f366162 2909
eadd33bb 2910 return true;
80c39712
TV		 2911}
2912
26d9dd0d 2913static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2914 int hfp, int hbp, int vsw, int vfp, int vbp,
2915 enum omap_dss_signal_level vsync_level,
2916 enum omap_dss_signal_level hsync_level,
2917 enum omap_dss_signal_edge data_pclk_edge,
2918 enum omap_dss_signal_level de_level,
2919 enum omap_dss_signal_edge sync_pclk_edge)
2920
80c39712 2921{
655e2941 2922 u32 timing_h, timing_v, l;
ed351881 2923 bool onoff, rf, ipc, vs, hs, de;
80c39712 2924
dcbe765b
CM		 2925 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2926 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2927 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2928 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2929 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2930 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 2931
64ba4f74
SS		 2932 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2933 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941 2934
ed351881
TV		 2935 switch (vsync_level) {
2936 case OMAPDSS_SIG_ACTIVE_LOW:
2937 vs = true;
2938 break;
2939 case OMAPDSS_SIG_ACTIVE_HIGH:
2940 vs = false;
2941 break;
2942 default:
2943 BUG();
2944 }
2945
2946 switch (hsync_level) {
2947 case OMAPDSS_SIG_ACTIVE_LOW:
2948 hs = true;
2949 break;
2950 case OMAPDSS_SIG_ACTIVE_HIGH:
2951 hs = false;
2952 break;
2953 default:
2954 BUG();
2955 }
2956
2957 switch (de_level) {
2958 case OMAPDSS_SIG_ACTIVE_LOW:
2959 de = true;
2960 break;
2961 case OMAPDSS_SIG_ACTIVE_HIGH:
2962 de = false;
2963 break;
2964 default:
2965 BUG();
2966 }
2967
655e2941
AT		 2968 switch (data_pclk_edge) {
2969 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2970 ipc = false;
2971 break;
2972 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2973 ipc = true;
2974 break;
655e2941
AT		 2975 default:
2976 BUG();
2977 }
2978
7a16360d
TV		 2979 /* always use the 'rf' setting */
2980 onoff = true;
2981
655e2941 2982 switch (sync_pclk_edge) {
655e2941 2983 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
655e2941
AT		 2984 rf = false;
2985 break;
2986 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
655e2941
AT		 2987 rf = true;
2988 break;
2989 default:
2990 BUG();
cf6ac4ce 2991 }
655e2941 2992
d80e02ef
TV		 2993 l = FLD_VAL(onoff, 17, 17) |
2994 FLD_VAL(rf, 16, 16) |
ed351881 2995 FLD_VAL(de, 15, 15) |
d80e02ef 2996 FLD_VAL(ipc, 14, 14) |
ed351881
TV		 2997 FLD_VAL(hs, 13, 13) |
2998 FLD_VAL(vs, 12, 12);
d80e02ef 2999
655e2941 3000 dispc_write_reg(DISPC_POL_FREQ(channel), l);
0006fd63
TV		 3001
3002 if (dispc.syscon_pol) {
3003 const int shifts[] = {
3004 [OMAP_DSS_CHANNEL_LCD] = 0,
3005 [OMAP_DSS_CHANNEL_LCD2] = 1,
3006 [OMAP_DSS_CHANNEL_LCD3] = 2,
3007 };
3008
3009 u32 mask, val;
3010
3011 mask = (1 << 0) | (1 << 3) | (1 << 6);
3012 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3013
3014 mask <<= 16 + shifts[channel];
3015 val <<= 16 + shifts[channel];
3016
3017 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3018 mask, val);
3019 }
80c39712
TV		 3020}
3021
3022/* change name to mode? */
c51d921a 3023void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3024 const struct omap_video_timings *timings)
80c39712
TV		 3025{
3026 unsigned xtot, ytot;
3027 unsigned long ht, vt;
2aefad49 3028 struct omap_video_timings t = *timings;
80c39712 3029
2aefad49 3030 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3031
2aefad49 3032 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3033 BUG();
c6eee968
TV		 3034 return;
3035 }
80c39712 3036
dd88b7a6 3037 if (dss_mgr_is_lcd(channel)) {
2aefad49 3038 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3039 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3040 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3041
2aefad49
AT		 3042 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3043 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3044
d8d78941
TV		 3045 ht = timings->pixelclock / xtot;
3046 vt = timings->pixelclock / xtot / ytot;
c51d921a 3047
d8d78941 3048 DSSDBG("pck %u\n", timings->pixelclock);
c51d921a 3049 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3050 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3051 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3052 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3053 t.de_level, t.sync_pclk_edge);
80c39712 3054
c51d921a 3055 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3056 } else {
23c8f88e 3057 if (t.interlace == true)
2aefad49 3058 t.y_res /= 2;
c51d921a 3059 }
8f366162 3060
2aefad49 3061 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 3062}
348be69d 3063EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 3064
26d9dd0d 3065static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3066 u16 pck_div)
80c39712
TV		 3067{
3068 BUG_ON(lck_div < 1);
9eaaf207 3069 BUG_ON(pck_div < 1);
80c39712 3070
ce7fa5eb 3071 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3072 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3
TV		 3073
3074 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3075 channel == OMAP_DSS_CHANNEL_LCD)
3076 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3077}
3078
26d9dd0d 3079static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3080 int *pck_div)
80c39712
TV		 3081{
3082 u32 l;
ce7fa5eb 3083 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3084 *lck_div = FLD_GET(l, 23, 16);
3085 *pck_div = FLD_GET(l, 7, 0);
3086}
3087
3088unsigned long dispc_fclk_rate(void)
3089{
2daea7af 3090 struct dss_pll *pll;
80c39712
TV		 3091 unsigned long r = 0;
3092
66534e8e 3093 switch (dss_get_dispc_clk_source()) {
89a35e51 3094 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3095 r = dss_get_dispc_clk_rate();
66534e8e 3096 break;
89a35e51 3097 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3098 pll = dss_pll_find("dsi0");
93550927
TV		 3099 if (!pll)
3100 pll = dss_pll_find("video0");
3101
2daea7af 3102 r = pll->cinfo.clkout[0];
66534e8e 3103 break;
5a8b572d 3104 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3105 pll = dss_pll_find("dsi1");
93550927
TV		 3106 if (!pll)
3107 pll = dss_pll_find("video1");
3108
2daea7af 3109 r = pll->cinfo.clkout[0];
5a8b572d 3110 break;
66534e8e
TA		 3111 default:
3112 BUG();
c6eee968 3113 return 0;
66534e8e
TA		 3114 }
3115
80c39712
TV		 3116 return r;
3117}
3118
26d9dd0d 3119unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3120{
2daea7af 3121 struct dss_pll *pll;
80c39712
TV		 3122 int lcd;
3123 unsigned long r;
3124 u32 l;
3125
c31cba8a
TV		 3126 if (dss_mgr_is_lcd(channel)) {
3127 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3128
c31cba8a 3129 lcd = FLD_GET(l, 23, 16);
80c39712 3130
c31cba8a
TV		 3131 switch (dss_get_lcd_clk_source(channel)) {
3132 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3133 r = dss_get_dispc_clk_rate();
c31cba8a
TV		 3134 break;
3135 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2daea7af 3136 pll = dss_pll_find("dsi0");
93550927
TV		 3137 if (!pll)
3138 pll = dss_pll_find("video0");
3139
2daea7af 3140 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3141 break;
3142 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2daea7af 3143 pll = dss_pll_find("dsi1");
93550927
TV		 3144 if (!pll)
3145 pll = dss_pll_find("video1");
3146
2daea7af 3147 r = pll->cinfo.clkout[0];
c31cba8a
TV		 3148 break;
3149 default:
3150 BUG();
3151 return 0;
3152 }
80c39712 3153
c31cba8a
TV		 3154 return r / lcd;
3155 } else {
3156 return dispc_fclk_rate();
3157 }
80c39712
TV		 3158}
3159
26d9dd0d 3160unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3161{
80c39712 3162 unsigned long r;
80c39712 3163
dd88b7a6 3164 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3165 int pcd;
3166 u32 l;
80c39712 3167
c3dc6a7a 3168 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3169
c3dc6a7a 3170 pcd = FLD_GET(l, 7, 0);
80c39712 3171
c3dc6a7a
AT		 3172 r = dispc_mgr_lclk_rate(channel);
3173
3174 return r / pcd;
3175 } else {
5391e87d 3176 return dispc.tv_pclk_rate;
c3dc6a7a 3177 }
80c39712
TV		 3178}
3179
5391e87d
TV		 3180void dispc_set_tv_pclk(unsigned long pclk)
3181{
3182 dispc.tv_pclk_rate = pclk;
3183}
3184
8b53d991
CM		 3185unsigned long dispc_core_clk_rate(void)
3186{
7b3926b3 3187 return dispc.core_clk_rate;
8b53d991
CM		 3188}
3189
3e8a6ff2
AT		 3190static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3191{
251886d8
TV		 3192 enum omap_channel channel;
3193
3194 if (plane == OMAP_DSS_WB)
3195 return 0;
3196
3197 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3198
3199 return dispc_mgr_pclk_rate(channel);
3200}
3201
3202static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3203{
251886d8
TV		 3204 enum omap_channel channel;
3205
3206 if (plane == OMAP_DSS_WB)
3207 return 0;
3208
3209 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3210
c31cba8a 3211 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3212}
c31cba8a 3213
6f1891fc 3214static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3215{
3216 int lcd, pcd;
6f1891fc
CM		 3217 enum omap_dss_clk_source lcd_clk_src;
3218
3219 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3220
3221 lcd_clk_src = dss_get_lcd_clk_source(channel);
3222
3223 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3224 dss_get_generic_clk_source_name(lcd_clk_src),
3225 dss_feat_get_clk_source_name(lcd_clk_src));
3226
3227 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3228
3229 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3230 dispc_mgr_lclk_rate(channel), lcd);
3231 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3232 dispc_mgr_pclk_rate(channel), pcd);
3233}
3234
3235void dispc_dump_clocks(struct seq_file *s)
3236{
3237 int lcd;
0cf35df3 3238 u32 l;
89a35e51 3239 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3240
4fbafaf3
TV		 3241 if (dispc_runtime_get())
3242 return;
80c39712 3243
80c39712
TV		 3244 seq_printf(s, "- DISPC -\n");
3245
067a57e4
AT		 3246 seq_printf(s, "dispc fclk source = %s (%s)\n",
3247 dss_get_generic_clk_source_name(dispc_clk_src),
3248 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3249
3250 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3251
0cf35df3
MR		 3252 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3253 seq_printf(s, "- DISPC-CORE-CLK -\n");
3254 l = dispc_read_reg(DISPC_DIVISOR);
3255 lcd = FLD_GET(l, 23, 16);
3256
3257 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3258 (dispc_fclk_rate()/lcd), lcd);
3259 }
2a205f34 3260
6f1891fc 3261 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3262
6f1891fc
CM		 3263 if (dss_has_feature(FEAT_MGR_LCD2))
3264 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3265 if (dss_has_feature(FEAT_MGR_LCD3))
3266 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3267
3268 dispc_runtime_put();
80c39712
TV		 3269}
3270
e40402cf 3271static void dispc_dump_regs(struct seq_file *s)
80c39712 3272{
4dd2da15
AT		 3273 int i, j;
3274 const char *mgr_names[] = {
3275 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3276 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3277 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3278 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3279 };
3280 const char *ovl_names[] = {
3281 [OMAP_DSS_GFX] = "GFX",
3282 [OMAP_DSS_VIDEO1] = "VID1",
3283 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3284 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3285 };
3286 const char **p_names;
3287
9b372c2d 3288#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3289
4fbafaf3
TV		 3290 if (dispc_runtime_get())
3291 return;
80c39712 3292
5010be80 3293 /* DISPC common registers */
80c39712
TV		 3294 DUMPREG(DISPC_REVISION);
3295 DUMPREG(DISPC_SYSCONFIG);
3296 DUMPREG(DISPC_SYSSTATUS);
3297 DUMPREG(DISPC_IRQSTATUS);
3298 DUMPREG(DISPC_IRQENABLE);
3299 DUMPREG(DISPC_CONTROL);
3300 DUMPREG(DISPC_CONFIG);
3301 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3302 DUMPREG(DISPC_LINE_STATUS);
3303 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3304 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3305 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3306 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3307 if (dss_has_feature(FEAT_MGR_LCD2)) {
3308 DUMPREG(DISPC_CONTROL2);
3309 DUMPREG(DISPC_CONFIG2);
5010be80 3310 }
6f1891fc
CM		 3311 if (dss_has_feature(FEAT_MGR_LCD3)) {
3312 DUMPREG(DISPC_CONTROL3);
3313 DUMPREG(DISPC_CONFIG3);
3314 }
29fceeeb
TV		 3315 if (dss_has_feature(FEAT_MFLAG))
3316 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3317
3318#undef DUMPREG
3319
3320#define DISPC_REG(i, name) name(i)
4dd2da15 3321#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3322 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3323 dispc_read_reg(DISPC_REG(i, r)))
3324
4dd2da15 3325 p_names = mgr_names;
5010be80 3326
4dd2da15
AT		 3327 /* DISPC channel specific registers */
3328 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3329 DUMPREG(i, DISPC_DEFAULT_COLOR);
3330 DUMPREG(i, DISPC_TRANS_COLOR);
3331 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3332
4dd2da15
AT		 3333 if (i == OMAP_DSS_CHANNEL_DIGIT)
3334 continue;
5010be80 3335
4dd2da15
AT		 3336 DUMPREG(i, DISPC_TIMING_H);
3337 DUMPREG(i, DISPC_TIMING_V);
3338 DUMPREG(i, DISPC_POL_FREQ);
3339 DUMPREG(i, DISPC_DIVISORo);
5010be80 3340
4dd2da15
AT		 3341 DUMPREG(i, DISPC_DATA_CYCLE1);
3342 DUMPREG(i, DISPC_DATA_CYCLE2);
3343 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3344
332e9d70 3345 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3346 DUMPREG(i, DISPC_CPR_COEF_R);
3347 DUMPREG(i, DISPC_CPR_COEF_G);
3348 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3349 }
2a205f34 3350 }
80c39712 3351
4dd2da15
AT		 3352 p_names = ovl_names;
3353
3354 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3355 DUMPREG(i, DISPC_OVL_BA0);
3356 DUMPREG(i, DISPC_OVL_BA1);
3357 DUMPREG(i, DISPC_OVL_POSITION);
3358 DUMPREG(i, DISPC_OVL_SIZE);
3359 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3360 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3361 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3362 DUMPREG(i, DISPC_OVL_ROW_INC);
3363 DUMPREG(i, DISPC_OVL_PIXEL_INC);
aba837a2 3364
4dd2da15
AT		 3365 if (dss_has_feature(FEAT_PRELOAD))
3366 DUMPREG(i, DISPC_OVL_PRELOAD);
aba837a2
TV		 3367 if (dss_has_feature(FEAT_MFLAG))
3368 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
4dd2da15
AT		 3369
3370 if (i == OMAP_DSS_GFX) {
3371 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3372 DUMPREG(i, DISPC_OVL_TABLE_BA);
3373 continue;
3374 }
3375
3376 DUMPREG(i, DISPC_OVL_FIR);
3377 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3378 DUMPREG(i, DISPC_OVL_ACCU0);
3379 DUMPREG(i, DISPC_OVL_ACCU1);
3380 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3381 DUMPREG(i, DISPC_OVL_BA0_UV);
3382 DUMPREG(i, DISPC_OVL_BA1_UV);
3383 DUMPREG(i, DISPC_OVL_FIR2);
3384 DUMPREG(i, DISPC_OVL_ACCU2_0);
3385 DUMPREG(i, DISPC_OVL_ACCU2_1);
3386 }
3387 if (dss_has_feature(FEAT_ATTR2))
3388 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
ab5ca071 3389 }
5010be80
AT		 3390
3391#undef DISPC_REG
3392#undef DUMPREG
3393
3394#define DISPC_REG(plane, name, i) name(plane, i)
3395#define DUMPREG(plane, name, i) \
4dd2da15 3396 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3397 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3398 dispc_read_reg(DISPC_REG(plane, name, i)))
3399
4dd2da15 3400 /* Video pipeline coefficient registers */
332e9d70 3401
4dd2da15
AT		 3402 /* start from OMAP_DSS_VIDEO1 */
3403 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3404 for (j = 0; j < 8; j++)
3405 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3406
4dd2da15
AT		 3407 for (j = 0; j < 8; j++)
3408 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3409
4dd2da15
AT		 3410 for (j = 0; j < 5; j++)
3411 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3412
4dd2da15
AT		 3413 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3414 for (j = 0; j < 8; j++)
3415 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3416 }
3417
3418 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3419 for (j = 0; j < 8; j++)
3420 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3421
3422 for (j = 0; j < 8; j++)
3423 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3424
3425 for (j = 0; j < 8; j++)
3426 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3427 }
332e9d70 3428 }
80c39712 3429
4fbafaf3 3430 dispc_runtime_put();
5010be80
AT		 3431
3432#undef DISPC_REG
80c39712
TV		 3433#undef DUMPREG
3434}
3435
80c39712
TV		 3436/* calculate clock rates using dividers in cinfo */
3437int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3438 struct dispc_clock_info *cinfo)
3439{
80c39712
TV		 3440 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3441 return -EINVAL;
9eaaf207 3442 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3443 return -EINVAL;
80c39712 3444
80c39712
TV		 3445 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3446 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3447
80c39712
TV		 3448 return 0;
3449}
80c39712 3450
7c284e6e
TV		 3451bool dispc_div_calc(unsigned long dispc,
3452 unsigned long pck_min, unsigned long pck_max,
3453 dispc_div_calc_func func, void *data)
3454{
3455 int lckd, lckd_start, lckd_stop;
3456 int pckd, pckd_start, pckd_stop;
3457 unsigned long pck, lck;
3458 unsigned long lck_max;
3459 unsigned long pckd_hw_min, pckd_hw_max;
3460 unsigned min_fck_per_pck;
3461 unsigned long fck;
80c39712 3462
7c284e6e
TV		 3463#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3464 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3465#else
3466 min_fck_per_pck = 0;
3467#endif
80c39712 3468
7c284e6e
TV		 3469 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3470 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3471
7c284e6e 3472 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3473
7c284e6e
TV		 3474 pck_min = pck_min ? pck_min : 1;
3475 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3476
7c284e6e
TV		 3477 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3478 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3479
7c284e6e
TV		 3480 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3481 lck = dispc / lckd;
80c39712 3482
7c284e6e
TV		 3483 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3484 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3485
7c284e6e
TV		 3486 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3487 pck = lck / pckd;
80c39712 3488
7c284e6e
TV		 3489 /*
3490 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3491 * clock, which means we're configuring DISPC fclk here
3492 * also. Thus we need to use the calculated lck. For
3493 * OMAP4+ the DISPC fclk is a separate clock.
3494 */
3495 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3496 fck = dispc_core_clk_rate();
3497 else
3498 fck = lck;
3499
3500 if (fck < pck * min_fck_per_pck)
3501 continue;
3502
3503 if (func(lckd, pckd, lck, pck, data))
3504 return true;
3505 }
3506 }
3507
3508 return false;
80c39712
TV		 3509}
3510
f0d08f89 3511void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3512 const struct dispc_clock_info *cinfo)
80c39712
TV		 3513{
3514 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3515 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3516
26d9dd0d 3517 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3518}
3519
26d9dd0d 3520int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3521 struct dispc_clock_info *cinfo)
80c39712
TV		 3522{
3523 unsigned long fck;
3524
3525 fck = dispc_fclk_rate();
3526
ce7fa5eb
MR		 3527 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3528 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3529
3530 cinfo->lck = fck / cinfo->lck_div;
3531 cinfo->pck = cinfo->lck / cinfo->pck_div;
3532
3533 return 0;
3534}
3535
4e0397cf
TV		 3536u32 dispc_read_irqstatus(void)
3537{
3538 return dispc_read_reg(DISPC_IRQSTATUS);
3539}
348be69d 3540EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3541
3542void dispc_clear_irqstatus(u32 mask)
3543{
3544 dispc_write_reg(DISPC_IRQSTATUS, mask);
3545}
348be69d 3546EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3547
3548u32 dispc_read_irqenable(void)
3549{
3550 return dispc_read_reg(DISPC_IRQENABLE);
3551}
348be69d 3552EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3553
3554void dispc_write_irqenable(u32 mask)
3555{
3556 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3557
3558 /* clear the irqstatus for newly enabled irqs */
3559 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3560
3561 dispc_write_reg(DISPC_IRQENABLE, mask);
3562}
348be69d 3563EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3564
80c39712
TV		 3565void dispc_enable_sidle(void)
3566{
3567 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3568}
3569
3570void dispc_disable_sidle(void)
3571{
3572 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3573}
3574
3575static void _omap_dispc_initial_config(void)
3576{
3577 u32 l;
3578
0cf35df3
MR		 3579 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3580 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3581 l = dispc_read_reg(DISPC_DIVISOR);
3582 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3583 l = FLD_MOD(l, 1, 0, 0);
3584 l = FLD_MOD(l, 1, 23, 16);
3585 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3586
3587 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3588 }
3589
80c39712 3590 /* FUNCGATED */
6ced40bf
AT		 3591 if (dss_has_feature(FEAT_FUNCGATED))
3592 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3593
6e5264b0 3594 dispc_setup_color_conv_coef();
80c39712
TV		 3595
3596 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3597
42a6961c 3598 dispc_init_fifos();
5ed8cf5b
TV		 3599
3600 dispc_configure_burst_sizes();
54128701
AT		 3601
3602 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3603
3604 if (dispc.feat->mstandby_workaround)
3605 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
80c39712
TV		 3606}
3607
dcbe765b
CM		 3608static const struct dispc_features omap24xx_dispc_feats __initconst = {
3609 .sw_start = 5,
3610 .fp_start = 15,
3611 .bp_start = 27,
3612 .sw_max = 64,
3613 .vp_max = 255,
3614 .hp_max = 256,
33b89928
AT		 3615 .mgr_width_start = 10,
3616 .mgr_height_start = 26,
3617 .mgr_width_max = 2048,
3618 .mgr_height_max = 2048,
ca5ca69c 3619 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3620 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3621 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3622 .num_fifos = 3,
cffa947d 3623 .no_framedone_tv = true,
8bc65552 3624 .set_max_preload = false,
dcbe765b
CM		 3625};
3626
3627static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3628 .sw_start = 5,
3629 .fp_start = 15,
3630 .bp_start = 27,
3631 .sw_max = 64,
3632 .vp_max = 255,
3633 .hp_max = 256,
33b89928
AT		 3634 .mgr_width_start = 10,
3635 .mgr_height_start = 26,
3636 .mgr_width_max = 2048,
3637 .mgr_height_max = 2048,
ca5ca69c
AT		 3638 .max_lcd_pclk = 173000000,
3639 .max_tv_pclk = 59000000,
dcbe765b
CM		 3640 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3641 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3642 .num_fifos = 3,
cffa947d 3643 .no_framedone_tv = true,
8bc65552 3644 .set_max_preload = false,
dcbe765b
CM		 3645};
3646
3647static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3648 .sw_start = 7,
3649 .fp_start = 19,
3650 .bp_start = 31,
3651 .sw_max = 256,
3652 .vp_max = 4095,
3653 .hp_max = 4096,
33b89928
AT		 3654 .mgr_width_start = 10,
3655 .mgr_height_start = 26,
3656 .mgr_width_max = 2048,
3657 .mgr_height_max = 2048,
ca5ca69c
AT		 3658 .max_lcd_pclk = 173000000,
3659 .max_tv_pclk = 59000000,
dcbe765b
CM		 3660 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3661 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3662 .num_fifos = 3,
cffa947d 3663 .no_framedone_tv = true,
8bc65552 3664 .set_max_preload = false,
dcbe765b
CM		 3665};
3666
3667static const struct dispc_features omap44xx_dispc_feats __initconst = {
3668 .sw_start = 7,
3669 .fp_start = 19,
3670 .bp_start = 31,
3671 .sw_max = 256,
3672 .vp_max = 4095,
3673 .hp_max = 4096,
33b89928
AT		 3674 .mgr_width_start = 10,
3675 .mgr_height_start = 26,
3676 .mgr_width_max = 2048,
3677 .mgr_height_max = 2048,
ca5ca69c
AT		 3678 .max_lcd_pclk = 170000000,
3679 .max_tv_pclk = 185625000,
dcbe765b
CM		 3680 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3681 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3682 .num_fifos = 5,
66a0f9e4 3683 .gfx_fifo_workaround = true,
8bc65552 3684 .set_max_preload = true,
dcbe765b
CM		 3685};
3686
264236f8
AT		 3687static const struct dispc_features omap54xx_dispc_feats __initconst = {
3688 .sw_start = 7,
3689 .fp_start = 19,
3690 .bp_start = 31,
3691 .sw_max = 256,
3692 .vp_max = 4095,
3693 .hp_max = 4096,
3694 .mgr_width_start = 11,
3695 .mgr_height_start = 27,
3696 .mgr_width_max = 4096,
3697 .mgr_height_max = 4096,
ca5ca69c
AT		 3698 .max_lcd_pclk = 170000000,
3699 .max_tv_pclk = 186000000,
264236f8
AT		 3700 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3701 .calc_core_clk = calc_core_clk_44xx,
3702 .num_fifos = 5,
3703 .gfx_fifo_workaround = true,
d0df9a2c 3704 .mstandby_workaround = true,
8bc65552 3705 .set_max_preload = true,
264236f8
AT		 3706};
3707
84b47623 3708static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3709{
3710 const struct dispc_features *src;
3711 struct dispc_features *dst;
3712
84b47623 3713 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3714 if (!dst) {
84b47623 3715 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3716 return -ENOMEM;
3717 }
3718
b2c7d54f 3719 switch (omapdss_get_version()) {
84b47623 3720 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3721 src = &omap24xx_dispc_feats;
84b47623
TV		 3722 break;
3723
3724 case OMAPDSS_VER_OMAP34xx_ES1:
3725 src = &omap34xx_rev1_0_dispc_feats;
3726 break;
3727
3728 case OMAPDSS_VER_OMAP34xx_ES3:
3729 case OMAPDSS_VER_OMAP3630:
3730 case OMAPDSS_VER_AM35xx:
d6279d4a 3731 case OMAPDSS_VER_AM43xx:
84b47623
TV		 3732 src = &omap34xx_rev3_0_dispc_feats;
3733 break;
3734
3735 case OMAPDSS_VER_OMAP4430_ES1:
3736 case OMAPDSS_VER_OMAP4430_ES2:
3737 case OMAPDSS_VER_OMAP4:
dcbe765b 3738 src = &omap44xx_dispc_feats;
84b47623
TV		 3739 break;
3740
3741 case OMAPDSS_VER_OMAP5:
93550927 3742 case OMAPDSS_VER_DRA7xx:
264236f8 3743 src = &omap54xx_dispc_feats;
84b47623
TV		 3744 break;
3745
3746 default:
dcbe765b
CM		 3747 return -ENODEV;
3748 }
3749
3750 memcpy(dst, src, sizeof(*dst));
3751 dispc.feat = dst;
3752
3753 return 0;
3754}
3755
0925afc9
TV		 3756static irqreturn_t dispc_irq_handler(int irq, void *arg)
3757{
3758 if (!dispc.is_enabled)
3759 return IRQ_NONE;
3760
3761 return dispc.user_handler(irq, dispc.user_data);
3762}
3763
96e2e637
TV		 3764int dispc_request_irq(irq_handler_t handler, void *dev_id)
3765{
0925afc9
TV		 3766 int r;
3767
3768 if (dispc.user_handler != NULL)
3769 return -EBUSY;
3770
3771 dispc.user_handler = handler;
3772 dispc.user_data = dev_id;
3773
3774 /* ensure the dispc_irq_handler sees the values above */
3775 smp_wmb();
3776
3777 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3778 IRQF_SHARED, "OMAP DISPC", &dispc);
3779 if (r) {
3780 dispc.user_handler = NULL;
3781 dispc.user_data = NULL;
3782 }
3783
3784 return r;
96e2e637 3785}
348be69d 3786EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 3787
3788void dispc_free_irq(void *dev_id)
3789{
0925afc9
TV		 3790 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3791
3792 dispc.user_handler = NULL;
3793 dispc.user_data = NULL;
96e2e637 3794}
348be69d 3795EXPORT_SYMBOL(dispc_free_irq);
96e2e637 3796
060b6d9c 3797/* DISPC HW IP initialisation */
6e7e8f06 3798static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3799{
3800 u32 rev;
affe360d 3801 int r = 0;
ea9da36a 3802 struct resource *dispc_mem;
0006fd63 3803 struct device_node *np = pdev->dev.of_node;
ea9da36a 3804
060b6d9c
SG		 3805 dispc.pdev = pdev;
3806
84b47623 3807 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 3808 if (r)
3809 return r;
3810
ea9da36a
SG		 3811 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3812 if (!dispc_mem) {
3813 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3814 return -EINVAL;
ea9da36a 3815 }
cd3b3449 3816
6e2a14d2
JL		 3817 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3818 resource_size(dispc_mem));
060b6d9c
SG		 3819 if (!dispc.base) {
3820 DSSERR("can't ioremap DISPC\n");
cd3b3449 3821 return -ENOMEM;
affe360d 3822 }
cd3b3449 3823
affe360d 3824 dispc.irq = platform_get_irq(dispc.pdev, 0);
3825 if (dispc.irq < 0) {
3826 DSSERR("platform_get_irq failed\n");
cd3b3449 3827 return -ENODEV;
affe360d 3828 }
3829
0006fd63
TV		 3830 if (np && of_property_read_bool(np, "syscon-pol")) {
3831 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
3832 if (IS_ERR(dispc.syscon_pol)) {
3833 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
3834 return PTR_ERR(dispc.syscon_pol);
3835 }
3836
3837 if (of_property_read_u32_index(np, "syscon-pol", 1,
3838 &dispc.syscon_pol_offset)) {
3839 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
3840 return -EINVAL;
3841 }
3842 }
3843
4fbafaf3
TV		 3844 pm_runtime_enable(&pdev->dev);
3845
3846 r = dispc_runtime_get();
3847 if (r)
3848 goto err_runtime_get;
060b6d9c
SG		 3849
3850 _omap_dispc_initial_config();
3851
060b6d9c 3852 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3853 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3854 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3855
4fbafaf3 3856 dispc_runtime_put();
060b6d9c 3857
04b1fc02
TV		 3858 dss_init_overlay_managers();
3859
e40402cf
TV		 3860 dss_debugfs_create_file("dispc", dispc_dump_regs);
3861
060b6d9c 3862 return 0;
4fbafaf3
TV		 3863
3864err_runtime_get:
3865 pm_runtime_disable(&pdev->dev);
affe360d 3866 return r;
060b6d9c
SG		 3867}
3868
6e7e8f06 3869static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3870{
4fbafaf3
TV		 3871 pm_runtime_disable(&pdev->dev);
3872
04b1fc02
TV		 3873 dss_uninit_overlay_managers();
3874
060b6d9c
SG		 3875 return 0;
3876}
3877
4fbafaf3
TV		 3878static int dispc_runtime_suspend(struct device *dev)
3879{
0925afc9
TV		 3880 dispc.is_enabled = false;
3881 /* ensure the dispc_irq_handler sees the is_enabled value */
3882 smp_wmb();
3883 /* wait for current handler to finish before turning the DISPC off */
3884 synchronize_irq(dispc.irq);
3885
4fbafaf3 3886 dispc_save_context();
4fbafaf3
TV		 3887
3888 return 0;
3889}
3890
3891static int dispc_runtime_resume(struct device *dev)
3892{
9229b516
TV		 3893 /*
3894 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
3895 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
3896 * _omap_dispc_initial_config(). We can thus use it to detect if
3897 * we have lost register context.
3898 */
0925afc9
TV		 3899 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
3900 _omap_dispc_initial_config();
9229b516 3901
0925afc9
TV		 3902 dispc_restore_context();
3903 }
be07dcd7 3904
0925afc9
TV		 3905 dispc.is_enabled = true;
3906 /* ensure the dispc_irq_handler sees the is_enabled value */
3907 smp_wmb();
4fbafaf3
TV		 3908
3909 return 0;
3910}
3911
3912static const struct dev_pm_ops dispc_pm_ops = {
3913 .runtime_suspend = dispc_runtime_suspend,
3914 .runtime_resume = dispc_runtime_resume,
3915};
3916
d7977f88
TV		 3917static const struct of_device_id dispc_of_match[] = {
3918 { .compatible = "ti,omap2-dispc", },
3919 { .compatible = "ti,omap3-dispc", },
3920 { .compatible = "ti,omap4-dispc", },
2e7e6b68 3921 { .compatible = "ti,omap5-dispc", },
93550927 3922 { .compatible = "ti,dra7-dispc", },
d7977f88
TV		 3923 {},
3924};
3925
060b6d9c 3926static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3927 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3928 .driver = {
3929 .name = "omapdss_dispc",
4fbafaf3 3930 .pm = &dispc_pm_ops,
d7977f88 3931 .of_match_table = dispc_of_match,
422ccbd5 3932 .suppress_bind_attrs = true,
060b6d9c
SG		 3933 },
3934};
3935
6e7e8f06 3936int __init dispc_init_platform_driver(void)
060b6d9c 3937{
11436e1d 3938 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3939}
3940
6e7e8f06 3941void __exit dispc_uninit_platform_driver(void)
060b6d9c 3942{
04c742c3 3943 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3944}
Linux kernel - Deliverables
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