Commit | Line | Data |
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80c39712 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dispc.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DISPC" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/vmalloc.h> | |
a8a35931 | 28 | #include <linux/export.h> |
80c39712 TV |
29 | #include <linux/clk.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/jiffies.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/workqueue.h> | |
ab83b14c | 35 | #include <linux/hardirq.h> |
24e6289c | 36 | #include <linux/platform_device.h> |
4fbafaf3 | 37 | #include <linux/pm_runtime.h> |
33366d0e | 38 | #include <linux/sizes.h> |
80c39712 | 39 | |
a0b38cc4 | 40 | #include <video/omapdss.h> |
80c39712 TV |
41 | |
42 | #include "dss.h" | |
a0acb557 | 43 | #include "dss_features.h" |
9b372c2d | 44 | #include "dispc.h" |
80c39712 TV |
45 | |
46 | /* DISPC */ | |
8613b000 | 47 | #define DISPC_SZ_REGS SZ_4K |
80c39712 | 48 | |
5ed8cf5b TV |
49 | enum omap_burst_size { |
50 | BURST_SIZE_X2 = 0, | |
51 | BURST_SIZE_X4 = 1, | |
52 | BURST_SIZE_X8 = 2, | |
53 | }; | |
54 | ||
80c39712 TV |
55 | #define REG_GET(idx, start, end) \ |
56 | FLD_GET(dispc_read_reg(idx), start, end) | |
57 | ||
58 | #define REG_FLD_MOD(idx, val, start, end) \ | |
59 | dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) | |
60 | ||
dcbe765b CM |
61 | struct dispc_features { |
62 | u8 sw_start; | |
63 | u8 fp_start; | |
64 | u8 bp_start; | |
65 | u16 sw_max; | |
66 | u16 vp_max; | |
67 | u16 hp_max; | |
33b89928 AT |
68 | u8 mgr_width_start; |
69 | u8 mgr_height_start; | |
70 | u16 mgr_width_max; | |
71 | u16 mgr_height_max; | |
ca5ca69c AT |
72 | unsigned long max_lcd_pclk; |
73 | unsigned long max_tv_pclk; | |
0c6921de | 74 | int (*calc_scaling) (unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
75 | const struct omap_video_timings *mgr_timings, |
76 | u16 width, u16 height, u16 out_width, u16 out_height, | |
77 | enum omap_color_mode color_mode, bool *five_taps, | |
78 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 79 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem); |
8702ee50 | 80 | unsigned long (*calc_core_clk) (unsigned long pclk, |
8ba85306 AT |
81 | u16 width, u16 height, u16 out_width, u16 out_height, |
82 | bool mem_to_mem); | |
42a6961c | 83 | u8 num_fifos; |
66a0f9e4 TV |
84 | |
85 | /* swap GFX & WB fifos */ | |
86 | bool gfx_fifo_workaround:1; | |
cffa947d TV |
87 | |
88 | /* no DISPC_IRQ_FRAMEDONETV on this SoC */ | |
89 | bool no_framedone_tv:1; | |
d0df9a2c AT |
90 | |
91 | /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ | |
92 | bool mstandby_workaround:1; | |
8bc65552 AT |
93 | |
94 | bool set_max_preload:1; | |
dcbe765b CM |
95 | }; |
96 | ||
42a6961c TV |
97 | #define DISPC_MAX_NR_FIFOS 5 |
98 | ||
80c39712 | 99 | static struct { |
060b6d9c | 100 | struct platform_device *pdev; |
80c39712 | 101 | void __iomem *base; |
4fbafaf3 | 102 | |
affe360d | 103 | int irq; |
0925afc9 TV |
104 | irq_handler_t user_handler; |
105 | void *user_data; | |
80c39712 | 106 | |
7b3926b3 | 107 | unsigned long core_clk_rate; |
5391e87d | 108 | unsigned long tv_pclk_rate; |
7b3926b3 | 109 | |
42a6961c TV |
110 | u32 fifo_size[DISPC_MAX_NR_FIFOS]; |
111 | /* maps which plane is using a fifo. fifo-id -> plane-id */ | |
112 | int fifo_assignment[DISPC_MAX_NR_FIFOS]; | |
80c39712 | 113 | |
49ea86f3 | 114 | bool ctx_valid; |
80c39712 | 115 | u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; |
dfc0fd8d | 116 | |
dcbe765b | 117 | const struct dispc_features *feat; |
0925afc9 TV |
118 | |
119 | bool is_enabled; | |
80c39712 TV |
120 | } dispc; |
121 | ||
0d66cbb5 AJ |
122 | enum omap_color_component { |
123 | /* used for all color formats for OMAP3 and earlier | |
124 | * and for RGB and Y color component on OMAP4 | |
125 | */ | |
126 | DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, | |
127 | /* used for UV component for | |
128 | * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 | |
129 | * color formats on OMAP4 | |
130 | */ | |
131 | DISPC_COLOR_COMPONENT_UV = 1 << 1, | |
132 | }; | |
133 | ||
efa70b3b CM |
134 | enum mgr_reg_fields { |
135 | DISPC_MGR_FLD_ENABLE, | |
136 | DISPC_MGR_FLD_STNTFT, | |
137 | DISPC_MGR_FLD_GO, | |
138 | DISPC_MGR_FLD_TFTDATALINES, | |
139 | DISPC_MGR_FLD_STALLMODE, | |
140 | DISPC_MGR_FLD_TCKENABLE, | |
141 | DISPC_MGR_FLD_TCKSELECTION, | |
142 | DISPC_MGR_FLD_CPR, | |
143 | DISPC_MGR_FLD_FIFOHANDCHECK, | |
144 | /* used to maintain a count of the above fields */ | |
145 | DISPC_MGR_FLD_NUM, | |
146 | }; | |
147 | ||
5c348ba9 JS |
148 | struct dispc_reg_field { |
149 | u16 reg; | |
150 | u8 high; | |
151 | u8 low; | |
152 | }; | |
153 | ||
efa70b3b CM |
154 | static const struct { |
155 | const char *name; | |
156 | u32 vsync_irq; | |
157 | u32 framedone_irq; | |
158 | u32 sync_lost_irq; | |
5c348ba9 | 159 | struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM]; |
efa70b3b CM |
160 | } mgr_desc[] = { |
161 | [OMAP_DSS_CHANNEL_LCD] = { | |
162 | .name = "LCD", | |
163 | .vsync_irq = DISPC_IRQ_VSYNC, | |
164 | .framedone_irq = DISPC_IRQ_FRAMEDONE, | |
165 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST, | |
166 | .reg_desc = { | |
167 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, | |
168 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, | |
169 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, | |
170 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, | |
171 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, | |
172 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, | |
173 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, | |
174 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, | |
175 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, | |
176 | }, | |
177 | }, | |
178 | [OMAP_DSS_CHANNEL_DIGIT] = { | |
179 | .name = "DIGIT", | |
180 | .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, | |
cffa947d | 181 | .framedone_irq = DISPC_IRQ_FRAMEDONETV, |
efa70b3b CM |
182 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, |
183 | .reg_desc = { | |
184 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, | |
185 | [DISPC_MGR_FLD_STNTFT] = { }, | |
186 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, | |
187 | [DISPC_MGR_FLD_TFTDATALINES] = { }, | |
188 | [DISPC_MGR_FLD_STALLMODE] = { }, | |
189 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, | |
190 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, | |
191 | [DISPC_MGR_FLD_CPR] = { }, | |
192 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, | |
193 | }, | |
194 | }, | |
195 | [OMAP_DSS_CHANNEL_LCD2] = { | |
196 | .name = "LCD2", | |
197 | .vsync_irq = DISPC_IRQ_VSYNC2, | |
198 | .framedone_irq = DISPC_IRQ_FRAMEDONE2, | |
199 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, | |
200 | .reg_desc = { | |
201 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, | |
202 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, | |
203 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, | |
204 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, | |
205 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, | |
206 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, | |
207 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, | |
208 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, | |
209 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, | |
210 | }, | |
211 | }, | |
e86d456a CM |
212 | [OMAP_DSS_CHANNEL_LCD3] = { |
213 | .name = "LCD3", | |
214 | .vsync_irq = DISPC_IRQ_VSYNC3, | |
215 | .framedone_irq = DISPC_IRQ_FRAMEDONE3, | |
216 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, | |
217 | .reg_desc = { | |
218 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, | |
219 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, | |
220 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, | |
221 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, | |
222 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, | |
223 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, | |
224 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, | |
225 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, | |
226 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, | |
227 | }, | |
228 | }, | |
efa70b3b CM |
229 | }; |
230 | ||
6e5264b0 AT |
231 | struct color_conv_coef { |
232 | int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; | |
233 | int full_range; | |
234 | }; | |
235 | ||
3e8a6ff2 AT |
236 | static unsigned long dispc_plane_pclk_rate(enum omap_plane plane); |
237 | static unsigned long dispc_plane_lclk_rate(enum omap_plane plane); | |
80c39712 | 238 | |
55978cc2 | 239 | static inline void dispc_write_reg(const u16 idx, u32 val) |
80c39712 | 240 | { |
55978cc2 | 241 | __raw_writel(val, dispc.base + idx); |
80c39712 TV |
242 | } |
243 | ||
55978cc2 | 244 | static inline u32 dispc_read_reg(const u16 idx) |
80c39712 | 245 | { |
55978cc2 | 246 | return __raw_readl(dispc.base + idx); |
80c39712 TV |
247 | } |
248 | ||
efa70b3b CM |
249 | static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) |
250 | { | |
5c348ba9 | 251 | const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; |
efa70b3b CM |
252 | return REG_GET(rfld.reg, rfld.high, rfld.low); |
253 | } | |
254 | ||
255 | static void mgr_fld_write(enum omap_channel channel, | |
256 | enum mgr_reg_fields regfld, int val) { | |
5c348ba9 | 257 | const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; |
efa70b3b CM |
258 | REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); |
259 | } | |
260 | ||
80c39712 | 261 | #define SR(reg) \ |
55978cc2 | 262 | dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) |
80c39712 | 263 | #define RR(reg) \ |
55978cc2 | 264 | dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) |
80c39712 | 265 | |
4fbafaf3 | 266 | static void dispc_save_context(void) |
80c39712 | 267 | { |
c6104b8e | 268 | int i, j; |
80c39712 | 269 | |
4fbafaf3 TV |
270 | DSSDBG("dispc_save_context\n"); |
271 | ||
80c39712 TV |
272 | SR(IRQENABLE); |
273 | SR(CONTROL); | |
274 | SR(CONFIG); | |
80c39712 | 275 | SR(LINE_NUMBER); |
11354dd5 AT |
276 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
277 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 278 | SR(GLOBAL_ALPHA); |
2a205f34 SS |
279 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
280 | SR(CONTROL2); | |
2a205f34 SS |
281 | SR(CONFIG2); |
282 | } | |
e86d456a CM |
283 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
284 | SR(CONTROL3); | |
285 | SR(CONFIG3); | |
286 | } | |
80c39712 | 287 | |
c6104b8e AT |
288 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
289 | SR(DEFAULT_COLOR(i)); | |
290 | SR(TRANS_COLOR(i)); | |
291 | SR(SIZE_MGR(i)); | |
292 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
293 | continue; | |
294 | SR(TIMING_H(i)); | |
295 | SR(TIMING_V(i)); | |
296 | SR(POL_FREQ(i)); | |
297 | SR(DIVISORo(i)); | |
298 | ||
299 | SR(DATA_CYCLE1(i)); | |
300 | SR(DATA_CYCLE2(i)); | |
301 | SR(DATA_CYCLE3(i)); | |
302 | ||
332e9d70 | 303 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
304 | SR(CPR_COEF_R(i)); |
305 | SR(CPR_COEF_G(i)); | |
306 | SR(CPR_COEF_B(i)); | |
332e9d70 | 307 | } |
2a205f34 | 308 | } |
80c39712 | 309 | |
c6104b8e AT |
310 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
311 | SR(OVL_BA0(i)); | |
312 | SR(OVL_BA1(i)); | |
313 | SR(OVL_POSITION(i)); | |
314 | SR(OVL_SIZE(i)); | |
315 | SR(OVL_ATTRIBUTES(i)); | |
316 | SR(OVL_FIFO_THRESHOLD(i)); | |
317 | SR(OVL_ROW_INC(i)); | |
318 | SR(OVL_PIXEL_INC(i)); | |
319 | if (dss_has_feature(FEAT_PRELOAD)) | |
320 | SR(OVL_PRELOAD(i)); | |
321 | if (i == OMAP_DSS_GFX) { | |
322 | SR(OVL_WINDOW_SKIP(i)); | |
323 | SR(OVL_TABLE_BA(i)); | |
324 | continue; | |
325 | } | |
326 | SR(OVL_FIR(i)); | |
327 | SR(OVL_PICTURE_SIZE(i)); | |
328 | SR(OVL_ACCU0(i)); | |
329 | SR(OVL_ACCU1(i)); | |
9b372c2d | 330 | |
c6104b8e AT |
331 | for (j = 0; j < 8; j++) |
332 | SR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 333 | |
c6104b8e AT |
334 | for (j = 0; j < 8; j++) |
335 | SR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 336 | |
c6104b8e AT |
337 | for (j = 0; j < 5; j++) |
338 | SR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 339 | |
c6104b8e AT |
340 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
341 | for (j = 0; j < 8; j++) | |
342 | SR(OVL_FIR_COEF_V(i, j)); | |
343 | } | |
9b372c2d | 344 | |
c6104b8e AT |
345 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
346 | SR(OVL_BA0_UV(i)); | |
347 | SR(OVL_BA1_UV(i)); | |
348 | SR(OVL_FIR2(i)); | |
349 | SR(OVL_ACCU2_0(i)); | |
350 | SR(OVL_ACCU2_1(i)); | |
ab5ca071 | 351 | |
c6104b8e AT |
352 | for (j = 0; j < 8; j++) |
353 | SR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 354 | |
c6104b8e AT |
355 | for (j = 0; j < 8; j++) |
356 | SR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 357 | |
c6104b8e AT |
358 | for (j = 0; j < 8; j++) |
359 | SR(OVL_FIR_COEF_V2(i, j)); | |
360 | } | |
361 | if (dss_has_feature(FEAT_ATTR2)) | |
362 | SR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 363 | } |
0cf35df3 MR |
364 | |
365 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
366 | SR(DIVISOR); | |
49ea86f3 | 367 | |
49ea86f3 TV |
368 | dispc.ctx_valid = true; |
369 | ||
9229b516 | 370 | DSSDBG("context saved\n"); |
80c39712 TV |
371 | } |
372 | ||
4fbafaf3 | 373 | static void dispc_restore_context(void) |
80c39712 | 374 | { |
9229b516 | 375 | int i, j; |
4fbafaf3 TV |
376 | |
377 | DSSDBG("dispc_restore_context\n"); | |
378 | ||
49ea86f3 TV |
379 | if (!dispc.ctx_valid) |
380 | return; | |
381 | ||
75c7d59d | 382 | /*RR(IRQENABLE);*/ |
80c39712 TV |
383 | /*RR(CONTROL);*/ |
384 | RR(CONFIG); | |
80c39712 | 385 | RR(LINE_NUMBER); |
11354dd5 AT |
386 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
387 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 388 | RR(GLOBAL_ALPHA); |
c6104b8e | 389 | if (dss_has_feature(FEAT_MGR_LCD2)) |
2a205f34 | 390 | RR(CONFIG2); |
e86d456a CM |
391 | if (dss_has_feature(FEAT_MGR_LCD3)) |
392 | RR(CONFIG3); | |
80c39712 | 393 | |
c6104b8e AT |
394 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
395 | RR(DEFAULT_COLOR(i)); | |
396 | RR(TRANS_COLOR(i)); | |
397 | RR(SIZE_MGR(i)); | |
398 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
399 | continue; | |
400 | RR(TIMING_H(i)); | |
401 | RR(TIMING_V(i)); | |
402 | RR(POL_FREQ(i)); | |
403 | RR(DIVISORo(i)); | |
404 | ||
405 | RR(DATA_CYCLE1(i)); | |
406 | RR(DATA_CYCLE2(i)); | |
407 | RR(DATA_CYCLE3(i)); | |
2a205f34 | 408 | |
332e9d70 | 409 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
410 | RR(CPR_COEF_R(i)); |
411 | RR(CPR_COEF_G(i)); | |
412 | RR(CPR_COEF_B(i)); | |
332e9d70 | 413 | } |
2a205f34 | 414 | } |
80c39712 | 415 | |
c6104b8e AT |
416 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
417 | RR(OVL_BA0(i)); | |
418 | RR(OVL_BA1(i)); | |
419 | RR(OVL_POSITION(i)); | |
420 | RR(OVL_SIZE(i)); | |
421 | RR(OVL_ATTRIBUTES(i)); | |
422 | RR(OVL_FIFO_THRESHOLD(i)); | |
423 | RR(OVL_ROW_INC(i)); | |
424 | RR(OVL_PIXEL_INC(i)); | |
425 | if (dss_has_feature(FEAT_PRELOAD)) | |
426 | RR(OVL_PRELOAD(i)); | |
427 | if (i == OMAP_DSS_GFX) { | |
428 | RR(OVL_WINDOW_SKIP(i)); | |
429 | RR(OVL_TABLE_BA(i)); | |
430 | continue; | |
431 | } | |
432 | RR(OVL_FIR(i)); | |
433 | RR(OVL_PICTURE_SIZE(i)); | |
434 | RR(OVL_ACCU0(i)); | |
435 | RR(OVL_ACCU1(i)); | |
9b372c2d | 436 | |
c6104b8e AT |
437 | for (j = 0; j < 8; j++) |
438 | RR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 439 | |
c6104b8e AT |
440 | for (j = 0; j < 8; j++) |
441 | RR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 442 | |
c6104b8e AT |
443 | for (j = 0; j < 5; j++) |
444 | RR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 445 | |
c6104b8e AT |
446 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
447 | for (j = 0; j < 8; j++) | |
448 | RR(OVL_FIR_COEF_V(i, j)); | |
449 | } | |
9b372c2d | 450 | |
c6104b8e AT |
451 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
452 | RR(OVL_BA0_UV(i)); | |
453 | RR(OVL_BA1_UV(i)); | |
454 | RR(OVL_FIR2(i)); | |
455 | RR(OVL_ACCU2_0(i)); | |
456 | RR(OVL_ACCU2_1(i)); | |
ab5ca071 | 457 | |
c6104b8e AT |
458 | for (j = 0; j < 8; j++) |
459 | RR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 460 | |
c6104b8e AT |
461 | for (j = 0; j < 8; j++) |
462 | RR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 463 | |
c6104b8e AT |
464 | for (j = 0; j < 8; j++) |
465 | RR(OVL_FIR_COEF_V2(i, j)); | |
466 | } | |
467 | if (dss_has_feature(FEAT_ATTR2)) | |
468 | RR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 469 | } |
80c39712 | 470 | |
0cf35df3 MR |
471 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) |
472 | RR(DIVISOR); | |
473 | ||
80c39712 TV |
474 | /* enable last, because LCD & DIGIT enable are here */ |
475 | RR(CONTROL); | |
2a205f34 SS |
476 | if (dss_has_feature(FEAT_MGR_LCD2)) |
477 | RR(CONTROL2); | |
e86d456a CM |
478 | if (dss_has_feature(FEAT_MGR_LCD3)) |
479 | RR(CONTROL3); | |
75c7d59d | 480 | /* clear spurious SYNC_LOST_DIGIT interrupts */ |
4e0397cf | 481 | dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); |
75c7d59d VS |
482 | |
483 | /* | |
484 | * enable last so IRQs won't trigger before | |
485 | * the context is fully restored | |
486 | */ | |
487 | RR(IRQENABLE); | |
49ea86f3 TV |
488 | |
489 | DSSDBG("context restored\n"); | |
80c39712 TV |
490 | } |
491 | ||
492 | #undef SR | |
493 | #undef RR | |
494 | ||
4fbafaf3 TV |
495 | int dispc_runtime_get(void) |
496 | { | |
497 | int r; | |
498 | ||
499 | DSSDBG("dispc_runtime_get\n"); | |
500 | ||
501 | r = pm_runtime_get_sync(&dispc.pdev->dev); | |
502 | WARN_ON(r < 0); | |
503 | return r < 0 ? r : 0; | |
504 | } | |
348be69d | 505 | EXPORT_SYMBOL(dispc_runtime_get); |
4fbafaf3 TV |
506 | |
507 | void dispc_runtime_put(void) | |
508 | { | |
509 | int r; | |
510 | ||
511 | DSSDBG("dispc_runtime_put\n"); | |
512 | ||
0eaf9f52 | 513 | r = pm_runtime_put_sync(&dispc.pdev->dev); |
5be3aebd | 514 | WARN_ON(r < 0 && r != -ENOSYS); |
80c39712 | 515 | } |
348be69d | 516 | EXPORT_SYMBOL(dispc_runtime_put); |
80c39712 | 517 | |
3dcec4d6 TV |
518 | u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) |
519 | { | |
efa70b3b | 520 | return mgr_desc[channel].vsync_irq; |
3dcec4d6 | 521 | } |
348be69d | 522 | EXPORT_SYMBOL(dispc_mgr_get_vsync_irq); |
3dcec4d6 | 523 | |
7d1365c9 TV |
524 | u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) |
525 | { | |
cffa947d TV |
526 | if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) |
527 | return 0; | |
528 | ||
efa70b3b | 529 | return mgr_desc[channel].framedone_irq; |
7d1365c9 | 530 | } |
348be69d | 531 | EXPORT_SYMBOL(dispc_mgr_get_framedone_irq); |
7d1365c9 | 532 | |
cb699200 TV |
533 | u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) |
534 | { | |
535 | return mgr_desc[channel].sync_lost_irq; | |
536 | } | |
348be69d | 537 | EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq); |
cb699200 | 538 | |
0b23e5b8 AT |
539 | u32 dispc_wb_get_framedone_irq(void) |
540 | { | |
541 | return DISPC_IRQ_FRAMEDONEWB; | |
542 | } | |
543 | ||
26d9dd0d | 544 | bool dispc_mgr_go_busy(enum omap_channel channel) |
80c39712 | 545 | { |
efa70b3b | 546 | return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; |
80c39712 | 547 | } |
348be69d | 548 | EXPORT_SYMBOL(dispc_mgr_go_busy); |
80c39712 | 549 | |
26d9dd0d | 550 | void dispc_mgr_go(enum omap_channel channel) |
80c39712 | 551 | { |
3c91ee8c TV |
552 | WARN_ON(dispc_mgr_is_enabled(channel) == false); |
553 | WARN_ON(dispc_mgr_go_busy(channel)); | |
80c39712 | 554 | |
efa70b3b | 555 | DSSDBG("GO %s\n", mgr_desc[channel].name); |
80c39712 | 556 | |
efa70b3b | 557 | mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); |
80c39712 | 558 | } |
348be69d | 559 | EXPORT_SYMBOL(dispc_mgr_go); |
80c39712 | 560 | |
0b23e5b8 AT |
561 | bool dispc_wb_go_busy(void) |
562 | { | |
563 | return REG_GET(DISPC_CONTROL2, 6, 6) == 1; | |
564 | } | |
565 | ||
566 | void dispc_wb_go(void) | |
567 | { | |
568 | enum omap_plane plane = OMAP_DSS_WB; | |
569 | bool enable, go; | |
570 | ||
571 | enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; | |
572 | ||
573 | if (!enable) | |
574 | return; | |
575 | ||
576 | go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; | |
577 | if (go) { | |
578 | DSSERR("GO bit not down for WB\n"); | |
579 | return; | |
580 | } | |
581 | ||
582 | REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); | |
583 | } | |
584 | ||
f0e5caab | 585 | static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 586 | { |
9b372c2d | 587 | dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); |
80c39712 TV |
588 | } |
589 | ||
f0e5caab | 590 | static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 591 | { |
9b372c2d | 592 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); |
80c39712 TV |
593 | } |
594 | ||
f0e5caab | 595 | static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 596 | { |
9b372c2d | 597 | dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); |
80c39712 TV |
598 | } |
599 | ||
f0e5caab | 600 | static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
601 | { |
602 | BUG_ON(plane == OMAP_DSS_GFX); | |
603 | ||
604 | dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); | |
605 | } | |
606 | ||
f0e5caab TV |
607 | static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, |
608 | u32 value) | |
ab5ca071 AJ |
609 | { |
610 | BUG_ON(plane == OMAP_DSS_GFX); | |
611 | ||
612 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); | |
613 | } | |
614 | ||
f0e5caab | 615 | static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
616 | { |
617 | BUG_ON(plane == OMAP_DSS_GFX); | |
618 | ||
619 | dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); | |
620 | } | |
621 | ||
debd9074 CM |
622 | static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, |
623 | int fir_vinc, int five_taps, | |
624 | enum omap_color_component color_comp) | |
80c39712 | 625 | { |
debd9074 | 626 | const struct dispc_coef *h_coef, *v_coef; |
80c39712 TV |
627 | int i; |
628 | ||
debd9074 CM |
629 | h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); |
630 | v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); | |
80c39712 TV |
631 | |
632 | for (i = 0; i < 8; i++) { | |
633 | u32 h, hv; | |
634 | ||
debd9074 CM |
635 | h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) |
636 | | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) | |
637 | | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) | |
638 | | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); | |
639 | hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) | |
640 | | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) | |
641 | | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) | |
642 | | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); | |
80c39712 | 643 | |
0d66cbb5 | 644 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
f0e5caab TV |
645 | dispc_ovl_write_firh_reg(plane, i, h); |
646 | dispc_ovl_write_firhv_reg(plane, i, hv); | |
0d66cbb5 | 647 | } else { |
f0e5caab TV |
648 | dispc_ovl_write_firh2_reg(plane, i, h); |
649 | dispc_ovl_write_firhv2_reg(plane, i, hv); | |
0d66cbb5 AJ |
650 | } |
651 | ||
80c39712 TV |
652 | } |
653 | ||
66be8f6c GI |
654 | if (five_taps) { |
655 | for (i = 0; i < 8; i++) { | |
656 | u32 v; | |
debd9074 CM |
657 | v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) |
658 | | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); | |
0d66cbb5 | 659 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) |
f0e5caab | 660 | dispc_ovl_write_firv_reg(plane, i, v); |
0d66cbb5 | 661 | else |
f0e5caab | 662 | dispc_ovl_write_firv2_reg(plane, i, v); |
66be8f6c | 663 | } |
80c39712 TV |
664 | } |
665 | } | |
666 | ||
80c39712 | 667 | |
6e5264b0 AT |
668 | static void dispc_ovl_write_color_conv_coef(enum omap_plane plane, |
669 | const struct color_conv_coef *ct) | |
670 | { | |
80c39712 TV |
671 | #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) |
672 | ||
6e5264b0 AT |
673 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); |
674 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); | |
675 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); | |
676 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); | |
677 | dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); | |
80c39712 | 678 | |
6e5264b0 | 679 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); |
80c39712 TV |
680 | |
681 | #undef CVAL | |
80c39712 TV |
682 | } |
683 | ||
6e5264b0 AT |
684 | static void dispc_setup_color_conv_coef(void) |
685 | { | |
686 | int i; | |
687 | int num_ovl = dss_feat_get_num_ovls(); | |
688 | int num_wb = dss_feat_get_num_wbs(); | |
689 | const struct color_conv_coef ctbl_bt601_5_ovl = { | |
690 | 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, | |
691 | }; | |
692 | const struct color_conv_coef ctbl_bt601_5_wb = { | |
693 | 66, 112, -38, 129, -94, -74, 25, -18, 112, 0, | |
694 | }; | |
695 | ||
696 | for (i = 1; i < num_ovl; i++) | |
697 | dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); | |
698 | ||
699 | for (; i < num_wb; i++) | |
700 | dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb); | |
701 | } | |
80c39712 | 702 | |
f0e5caab | 703 | static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) |
80c39712 | 704 | { |
9b372c2d | 705 | dispc_write_reg(DISPC_OVL_BA0(plane), paddr); |
80c39712 TV |
706 | } |
707 | ||
f0e5caab | 708 | static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) |
80c39712 | 709 | { |
9b372c2d | 710 | dispc_write_reg(DISPC_OVL_BA1(plane), paddr); |
80c39712 TV |
711 | } |
712 | ||
f0e5caab | 713 | static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
714 | { |
715 | dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); | |
716 | } | |
717 | ||
f0e5caab | 718 | static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
719 | { |
720 | dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); | |
721 | } | |
722 | ||
d79db853 AT |
723 | static void dispc_ovl_set_pos(enum omap_plane plane, |
724 | enum omap_overlay_caps caps, int x, int y) | |
80c39712 | 725 | { |
d79db853 AT |
726 | u32 val; |
727 | ||
728 | if ((caps & OMAP_DSS_OVL_CAP_POS) == 0) | |
729 | return; | |
730 | ||
731 | val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); | |
9b372c2d AT |
732 | |
733 | dispc_write_reg(DISPC_OVL_POSITION(plane), val); | |
80c39712 TV |
734 | } |
735 | ||
78b687fc AT |
736 | static void dispc_ovl_set_input_size(enum omap_plane plane, int width, |
737 | int height) | |
80c39712 | 738 | { |
80c39712 | 739 | u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
9b372c2d | 740 | |
36d87d95 | 741 | if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) |
9b372c2d AT |
742 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); |
743 | else | |
744 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); | |
80c39712 TV |
745 | } |
746 | ||
78b687fc AT |
747 | static void dispc_ovl_set_output_size(enum omap_plane plane, int width, |
748 | int height) | |
80c39712 TV |
749 | { |
750 | u32 val; | |
80c39712 TV |
751 | |
752 | BUG_ON(plane == OMAP_DSS_GFX); | |
753 | ||
754 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); | |
9b372c2d | 755 | |
36d87d95 AT |
756 | if (plane == OMAP_DSS_WB) |
757 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); | |
758 | else | |
759 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); | |
80c39712 TV |
760 | } |
761 | ||
5b54ed3e AT |
762 | static void dispc_ovl_set_zorder(enum omap_plane plane, |
763 | enum omap_overlay_caps caps, u8 zorder) | |
54128701 | 764 | { |
5b54ed3e | 765 | if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) |
54128701 AT |
766 | return; |
767 | ||
768 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); | |
769 | } | |
770 | ||
771 | static void dispc_ovl_enable_zorder_planes(void) | |
772 | { | |
773 | int i; | |
774 | ||
775 | if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
776 | return; | |
777 | ||
778 | for (i = 0; i < dss_feat_get_num_ovls(); i++) | |
779 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); | |
780 | } | |
781 | ||
5b54ed3e AT |
782 | static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, |
783 | enum omap_overlay_caps caps, bool enable) | |
fd28a390 | 784 | { |
5b54ed3e | 785 | if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) |
fd28a390 R |
786 | return; |
787 | ||
9b372c2d | 788 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); |
fd28a390 R |
789 | } |
790 | ||
5b54ed3e AT |
791 | static void dispc_ovl_setup_global_alpha(enum omap_plane plane, |
792 | enum omap_overlay_caps caps, u8 global_alpha) | |
80c39712 | 793 | { |
b8c095b4 | 794 | static const unsigned shifts[] = { 0, 8, 16, 24, }; |
fe3cc9d6 TV |
795 | int shift; |
796 | ||
5b54ed3e | 797 | if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) |
fd28a390 | 798 | return; |
a0acb557 | 799 | |
fe3cc9d6 TV |
800 | shift = shifts[plane]; |
801 | REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); | |
80c39712 TV |
802 | } |
803 | ||
f0e5caab | 804 | static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) |
80c39712 | 805 | { |
9b372c2d | 806 | dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); |
80c39712 TV |
807 | } |
808 | ||
f0e5caab | 809 | static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) |
80c39712 | 810 | { |
9b372c2d | 811 | dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); |
80c39712 TV |
812 | } |
813 | ||
f0e5caab | 814 | static void dispc_ovl_set_color_mode(enum omap_plane plane, |
80c39712 TV |
815 | enum omap_color_mode color_mode) |
816 | { | |
817 | u32 m = 0; | |
f20e4220 AJ |
818 | if (plane != OMAP_DSS_GFX) { |
819 | switch (color_mode) { | |
820 | case OMAP_DSS_COLOR_NV12: | |
821 | m = 0x0; break; | |
08f3267e | 822 | case OMAP_DSS_COLOR_RGBX16: |
f20e4220 AJ |
823 | m = 0x1; break; |
824 | case OMAP_DSS_COLOR_RGBA16: | |
825 | m = 0x2; break; | |
08f3267e | 826 | case OMAP_DSS_COLOR_RGB12U: |
f20e4220 AJ |
827 | m = 0x4; break; |
828 | case OMAP_DSS_COLOR_ARGB16: | |
829 | m = 0x5; break; | |
830 | case OMAP_DSS_COLOR_RGB16: | |
831 | m = 0x6; break; | |
832 | case OMAP_DSS_COLOR_ARGB16_1555: | |
833 | m = 0x7; break; | |
834 | case OMAP_DSS_COLOR_RGB24U: | |
835 | m = 0x8; break; | |
836 | case OMAP_DSS_COLOR_RGB24P: | |
837 | m = 0x9; break; | |
838 | case OMAP_DSS_COLOR_YUV2: | |
839 | m = 0xa; break; | |
840 | case OMAP_DSS_COLOR_UYVY: | |
841 | m = 0xb; break; | |
842 | case OMAP_DSS_COLOR_ARGB32: | |
843 | m = 0xc; break; | |
844 | case OMAP_DSS_COLOR_RGBA32: | |
845 | m = 0xd; break; | |
846 | case OMAP_DSS_COLOR_RGBX32: | |
847 | m = 0xe; break; | |
848 | case OMAP_DSS_COLOR_XRGB16_1555: | |
849 | m = 0xf; break; | |
850 | default: | |
c6eee968 | 851 | BUG(); return; |
f20e4220 AJ |
852 | } |
853 | } else { | |
854 | switch (color_mode) { | |
855 | case OMAP_DSS_COLOR_CLUT1: | |
856 | m = 0x0; break; | |
857 | case OMAP_DSS_COLOR_CLUT2: | |
858 | m = 0x1; break; | |
859 | case OMAP_DSS_COLOR_CLUT4: | |
860 | m = 0x2; break; | |
861 | case OMAP_DSS_COLOR_CLUT8: | |
862 | m = 0x3; break; | |
863 | case OMAP_DSS_COLOR_RGB12U: | |
864 | m = 0x4; break; | |
865 | case OMAP_DSS_COLOR_ARGB16: | |
866 | m = 0x5; break; | |
867 | case OMAP_DSS_COLOR_RGB16: | |
868 | m = 0x6; break; | |
869 | case OMAP_DSS_COLOR_ARGB16_1555: | |
870 | m = 0x7; break; | |
871 | case OMAP_DSS_COLOR_RGB24U: | |
872 | m = 0x8; break; | |
873 | case OMAP_DSS_COLOR_RGB24P: | |
874 | m = 0x9; break; | |
08f3267e | 875 | case OMAP_DSS_COLOR_RGBX16: |
f20e4220 | 876 | m = 0xa; break; |
08f3267e | 877 | case OMAP_DSS_COLOR_RGBA16: |
f20e4220 AJ |
878 | m = 0xb; break; |
879 | case OMAP_DSS_COLOR_ARGB32: | |
880 | m = 0xc; break; | |
881 | case OMAP_DSS_COLOR_RGBA32: | |
882 | m = 0xd; break; | |
883 | case OMAP_DSS_COLOR_RGBX32: | |
884 | m = 0xe; break; | |
885 | case OMAP_DSS_COLOR_XRGB16_1555: | |
886 | m = 0xf; break; | |
887 | default: | |
c6eee968 | 888 | BUG(); return; |
f20e4220 | 889 | } |
80c39712 TV |
890 | } |
891 | ||
9b372c2d | 892 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); |
80c39712 TV |
893 | } |
894 | ||
65e006ff CM |
895 | static void dispc_ovl_configure_burst_type(enum omap_plane plane, |
896 | enum omap_dss_rotation_type rotation_type) | |
897 | { | |
898 | if (dss_has_feature(FEAT_BURST_2D) == 0) | |
899 | return; | |
900 | ||
901 | if (rotation_type == OMAP_DSS_ROT_TILER) | |
902 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); | |
903 | else | |
904 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); | |
905 | } | |
906 | ||
f427984e | 907 | void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) |
80c39712 TV |
908 | { |
909 | int shift; | |
910 | u32 val; | |
2a205f34 | 911 | int chan = 0, chan2 = 0; |
80c39712 TV |
912 | |
913 | switch (plane) { | |
914 | case OMAP_DSS_GFX: | |
915 | shift = 8; | |
916 | break; | |
917 | case OMAP_DSS_VIDEO1: | |
918 | case OMAP_DSS_VIDEO2: | |
b8c095b4 | 919 | case OMAP_DSS_VIDEO3: |
80c39712 TV |
920 | shift = 16; |
921 | break; | |
922 | default: | |
923 | BUG(); | |
924 | return; | |
925 | } | |
926 | ||
9b372c2d | 927 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
2a205f34 SS |
928 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
929 | switch (channel) { | |
930 | case OMAP_DSS_CHANNEL_LCD: | |
931 | chan = 0; | |
932 | chan2 = 0; | |
933 | break; | |
934 | case OMAP_DSS_CHANNEL_DIGIT: | |
935 | chan = 1; | |
936 | chan2 = 0; | |
937 | break; | |
938 | case OMAP_DSS_CHANNEL_LCD2: | |
939 | chan = 0; | |
940 | chan2 = 1; | |
941 | break; | |
e86d456a CM |
942 | case OMAP_DSS_CHANNEL_LCD3: |
943 | if (dss_has_feature(FEAT_MGR_LCD3)) { | |
944 | chan = 0; | |
945 | chan2 = 2; | |
946 | } else { | |
947 | BUG(); | |
948 | return; | |
949 | } | |
950 | break; | |
2a205f34 SS |
951 | default: |
952 | BUG(); | |
c6eee968 | 953 | return; |
2a205f34 SS |
954 | } |
955 | ||
956 | val = FLD_MOD(val, chan, shift, shift); | |
957 | val = FLD_MOD(val, chan2, 31, 30); | |
958 | } else { | |
959 | val = FLD_MOD(val, channel, shift, shift); | |
960 | } | |
9b372c2d | 961 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 | 962 | } |
348be69d | 963 | EXPORT_SYMBOL(dispc_ovl_set_channel_out); |
80c39712 | 964 | |
2cc5d1af TV |
965 | static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) |
966 | { | |
967 | int shift; | |
968 | u32 val; | |
969 | enum omap_channel channel; | |
970 | ||
971 | switch (plane) { | |
972 | case OMAP_DSS_GFX: | |
973 | shift = 8; | |
974 | break; | |
975 | case OMAP_DSS_VIDEO1: | |
976 | case OMAP_DSS_VIDEO2: | |
977 | case OMAP_DSS_VIDEO3: | |
978 | shift = 16; | |
979 | break; | |
980 | default: | |
981 | BUG(); | |
c6eee968 | 982 | return 0; |
2cc5d1af TV |
983 | } |
984 | ||
985 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); | |
986 | ||
e86d456a CM |
987 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
988 | if (FLD_GET(val, 31, 30) == 0) | |
989 | channel = FLD_GET(val, shift, shift); | |
990 | else if (FLD_GET(val, 31, 30) == 1) | |
991 | channel = OMAP_DSS_CHANNEL_LCD2; | |
992 | else | |
993 | channel = OMAP_DSS_CHANNEL_LCD3; | |
994 | } else if (dss_has_feature(FEAT_MGR_LCD2)) { | |
2cc5d1af TV |
995 | if (FLD_GET(val, 31, 30) == 0) |
996 | channel = FLD_GET(val, shift, shift); | |
997 | else | |
998 | channel = OMAP_DSS_CHANNEL_LCD2; | |
999 | } else { | |
1000 | channel = FLD_GET(val, shift, shift); | |
1001 | } | |
1002 | ||
1003 | return channel; | |
1004 | } | |
1005 | ||
d9ac773c AT |
1006 | void dispc_wb_set_channel_in(enum dss_writeback_channel channel) |
1007 | { | |
1008 | enum omap_plane plane = OMAP_DSS_WB; | |
1009 | ||
1010 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16); | |
1011 | } | |
1012 | ||
f0e5caab | 1013 | static void dispc_ovl_set_burst_size(enum omap_plane plane, |
80c39712 TV |
1014 | enum omap_burst_size burst_size) |
1015 | { | |
8bbe09ee | 1016 | static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; |
80c39712 | 1017 | int shift; |
80c39712 | 1018 | |
fe3cc9d6 | 1019 | shift = shifts[plane]; |
5ed8cf5b | 1020 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); |
80c39712 TV |
1021 | } |
1022 | ||
5ed8cf5b TV |
1023 | static void dispc_configure_burst_sizes(void) |
1024 | { | |
1025 | int i; | |
1026 | const int burst_size = BURST_SIZE_X8; | |
1027 | ||
1028 | /* Configure burst size always to maximum size */ | |
392faa0e | 1029 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) |
f0e5caab | 1030 | dispc_ovl_set_burst_size(i, burst_size); |
5ed8cf5b TV |
1031 | } |
1032 | ||
83fa2f2e | 1033 | static u32 dispc_ovl_get_burst_size(enum omap_plane plane) |
5ed8cf5b TV |
1034 | { |
1035 | unsigned unit = dss_feat_get_burst_size_unit(); | |
1036 | /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ | |
1037 | return unit * 8; | |
1038 | } | |
1039 | ||
d3862610 M |
1040 | void dispc_enable_gamma_table(bool enable) |
1041 | { | |
1042 | /* | |
1043 | * This is partially implemented to support only disabling of | |
1044 | * the gamma table. | |
1045 | */ | |
1046 | if (enable) { | |
1047 | DSSWARN("Gamma table enabling for TV not yet supported"); | |
1048 | return; | |
1049 | } | |
1050 | ||
1051 | REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); | |
1052 | } | |
1053 | ||
c64dca40 | 1054 | static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) |
3c07cae2 | 1055 | { |
efa70b3b | 1056 | if (channel == OMAP_DSS_CHANNEL_DIGIT) |
3c07cae2 TV |
1057 | return; |
1058 | ||
efa70b3b | 1059 | mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); |
3c07cae2 TV |
1060 | } |
1061 | ||
c64dca40 | 1062 | static void dispc_mgr_set_cpr_coef(enum omap_channel channel, |
a8f3fcd1 | 1063 | const struct omap_dss_cpr_coefs *coefs) |
3c07cae2 TV |
1064 | { |
1065 | u32 coef_r, coef_g, coef_b; | |
1066 | ||
dd88b7a6 | 1067 | if (!dss_mgr_is_lcd(channel)) |
3c07cae2 TV |
1068 | return; |
1069 | ||
1070 | coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | | |
1071 | FLD_VAL(coefs->rb, 9, 0); | |
1072 | coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | | |
1073 | FLD_VAL(coefs->gb, 9, 0); | |
1074 | coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | | |
1075 | FLD_VAL(coefs->bb, 9, 0); | |
1076 | ||
1077 | dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); | |
1078 | dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); | |
1079 | dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); | |
1080 | } | |
1081 | ||
f0e5caab | 1082 | static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) |
80c39712 TV |
1083 | { |
1084 | u32 val; | |
1085 | ||
1086 | BUG_ON(plane == OMAP_DSS_GFX); | |
1087 | ||
9b372c2d | 1088 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1089 | val = FLD_MOD(val, enable, 9, 9); |
9b372c2d | 1090 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 TV |
1091 | } |
1092 | ||
d79db853 AT |
1093 | static void dispc_ovl_enable_replication(enum omap_plane plane, |
1094 | enum omap_overlay_caps caps, bool enable) | |
80c39712 | 1095 | { |
b8c095b4 | 1096 | static const unsigned shifts[] = { 5, 10, 10, 10 }; |
fe3cc9d6 | 1097 | int shift; |
80c39712 | 1098 | |
d79db853 AT |
1099 | if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) |
1100 | return; | |
1101 | ||
fe3cc9d6 TV |
1102 | shift = shifts[plane]; |
1103 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); | |
80c39712 TV |
1104 | } |
1105 | ||
8f366162 | 1106 | static void dispc_mgr_set_size(enum omap_channel channel, u16 width, |
e5c09e06 | 1107 | u16 height) |
80c39712 TV |
1108 | { |
1109 | u32 val; | |
80c39712 | 1110 | |
33b89928 AT |
1111 | val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | |
1112 | FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); | |
1113 | ||
8f366162 | 1114 | dispc_write_reg(DISPC_SIZE_MGR(channel), val); |
80c39712 TV |
1115 | } |
1116 | ||
42a6961c | 1117 | static void dispc_init_fifos(void) |
80c39712 | 1118 | { |
80c39712 | 1119 | u32 size; |
42a6961c | 1120 | int fifo; |
a0acb557 | 1121 | u8 start, end; |
5ed8cf5b TV |
1122 | u32 unit; |
1123 | ||
1124 | unit = dss_feat_get_buffer_size_unit(); | |
80c39712 | 1125 | |
a0acb557 | 1126 | dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); |
80c39712 | 1127 | |
42a6961c TV |
1128 | for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { |
1129 | size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); | |
5ed8cf5b | 1130 | size *= unit; |
42a6961c TV |
1131 | dispc.fifo_size[fifo] = size; |
1132 | ||
1133 | /* | |
1134 | * By default fifos are mapped directly to overlays, fifo 0 to | |
1135 | * ovl 0, fifo 1 to ovl 1, etc. | |
1136 | */ | |
1137 | dispc.fifo_assignment[fifo] = fifo; | |
80c39712 | 1138 | } |
66a0f9e4 TV |
1139 | |
1140 | /* | |
1141 | * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo | |
1142 | * causes problems with certain use cases, like using the tiler in 2D | |
1143 | * mode. The below hack swaps the fifos of GFX and WB planes, thus | |
1144 | * giving GFX plane a larger fifo. WB but should work fine with a | |
1145 | * smaller fifo. | |
1146 | */ | |
1147 | if (dispc.feat->gfx_fifo_workaround) { | |
1148 | u32 v; | |
1149 | ||
1150 | v = dispc_read_reg(DISPC_GLOBAL_BUFFER); | |
1151 | ||
1152 | v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ | |
1153 | v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ | |
1154 | v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ | |
1155 | v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ | |
1156 | ||
1157 | dispc_write_reg(DISPC_GLOBAL_BUFFER, v); | |
1158 | ||
1159 | dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; | |
1160 | dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; | |
1161 | } | |
80c39712 TV |
1162 | } |
1163 | ||
83fa2f2e | 1164 | static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) |
80c39712 | 1165 | { |
42a6961c TV |
1166 | int fifo; |
1167 | u32 size = 0; | |
1168 | ||
1169 | for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { | |
1170 | if (dispc.fifo_assignment[fifo] == plane) | |
1171 | size += dispc.fifo_size[fifo]; | |
1172 | } | |
1173 | ||
1174 | return size; | |
80c39712 TV |
1175 | } |
1176 | ||
6f04e1bf | 1177 | void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) |
80c39712 | 1178 | { |
a0acb557 | 1179 | u8 hi_start, hi_end, lo_start, lo_end; |
5ed8cf5b TV |
1180 | u32 unit; |
1181 | ||
1182 | unit = dss_feat_get_buffer_size_unit(); | |
1183 | ||
1184 | WARN_ON(low % unit != 0); | |
1185 | WARN_ON(high % unit != 0); | |
1186 | ||
1187 | low /= unit; | |
1188 | high /= unit; | |
a0acb557 | 1189 | |
9b372c2d AT |
1190 | dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); |
1191 | dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); | |
1192 | ||
3cb5d966 | 1193 | DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", |
80c39712 | 1194 | plane, |
9b372c2d | 1195 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 | 1196 | lo_start, lo_end) * unit, |
9b372c2d | 1197 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 TV |
1198 | hi_start, hi_end) * unit, |
1199 | low * unit, high * unit); | |
80c39712 | 1200 | |
9b372c2d | 1201 | dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), |
a0acb557 AT |
1202 | FLD_VAL(high, hi_start, hi_end) | |
1203 | FLD_VAL(low, lo_start, lo_end)); | |
8bc65552 AT |
1204 | |
1205 | /* | |
1206 | * configure the preload to the pipeline's high threhold, if HT it's too | |
1207 | * large for the preload field, set the threshold to the maximum value | |
1208 | * that can be held by the preload register | |
1209 | */ | |
1210 | if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && | |
1211 | plane != OMAP_DSS_WB) | |
1212 | dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); | |
80c39712 | 1213 | } |
8ee5c842 | 1214 | EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold); |
80c39712 TV |
1215 | |
1216 | void dispc_enable_fifomerge(bool enable) | |
1217 | { | |
e6b0f884 TV |
1218 | if (!dss_has_feature(FEAT_FIFO_MERGE)) { |
1219 | WARN_ON(enable); | |
1220 | return; | |
1221 | } | |
1222 | ||
80c39712 TV |
1223 | DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); |
1224 | REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); | |
80c39712 TV |
1225 | } |
1226 | ||
83fa2f2e | 1227 | void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, |
3568f2a4 TV |
1228 | u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, |
1229 | bool manual_update) | |
83fa2f2e TV |
1230 | { |
1231 | /* | |
1232 | * All sizes are in bytes. Both the buffer and burst are made of | |
1233 | * buffer_units, and the fifo thresholds must be buffer_unit aligned. | |
1234 | */ | |
1235 | ||
1236 | unsigned buf_unit = dss_feat_get_buffer_size_unit(); | |
e0e405b9 TV |
1237 | unsigned ovl_fifo_size, total_fifo_size, burst_size; |
1238 | int i; | |
83fa2f2e TV |
1239 | |
1240 | burst_size = dispc_ovl_get_burst_size(plane); | |
e0e405b9 | 1241 | ovl_fifo_size = dispc_ovl_get_fifo_size(plane); |
83fa2f2e | 1242 | |
e0e405b9 TV |
1243 | if (use_fifomerge) { |
1244 | total_fifo_size = 0; | |
392faa0e | 1245 | for (i = 0; i < dss_feat_get_num_ovls(); ++i) |
e0e405b9 TV |
1246 | total_fifo_size += dispc_ovl_get_fifo_size(i); |
1247 | } else { | |
1248 | total_fifo_size = ovl_fifo_size; | |
1249 | } | |
1250 | ||
1251 | /* | |
1252 | * We use the same low threshold for both fifomerge and non-fifomerge | |
1253 | * cases, but for fifomerge we calculate the high threshold using the | |
1254 | * combined fifo size | |
1255 | */ | |
1256 | ||
3568f2a4 | 1257 | if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { |
e0e405b9 TV |
1258 | *fifo_low = ovl_fifo_size - burst_size * 2; |
1259 | *fifo_high = total_fifo_size - burst_size; | |
8bbe09ee AT |
1260 | } else if (plane == OMAP_DSS_WB) { |
1261 | /* | |
1262 | * Most optimal configuration for writeback is to push out data | |
1263 | * to the interconnect the moment writeback pushes enough pixels | |
1264 | * in the FIFO to form a burst | |
1265 | */ | |
1266 | *fifo_low = 0; | |
1267 | *fifo_high = burst_size; | |
e0e405b9 TV |
1268 | } else { |
1269 | *fifo_low = ovl_fifo_size - burst_size; | |
1270 | *fifo_high = total_fifo_size - buf_unit; | |
1271 | } | |
83fa2f2e | 1272 | } |
8ee5c842 | 1273 | EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds); |
83fa2f2e | 1274 | |
f0e5caab | 1275 | static void dispc_ovl_set_fir(enum omap_plane plane, |
0d66cbb5 AJ |
1276 | int hinc, int vinc, |
1277 | enum omap_color_component color_comp) | |
80c39712 TV |
1278 | { |
1279 | u32 val; | |
80c39712 | 1280 | |
0d66cbb5 AJ |
1281 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
1282 | u8 hinc_start, hinc_end, vinc_start, vinc_end; | |
a0acb557 | 1283 | |
0d66cbb5 AJ |
1284 | dss_feat_get_reg_field(FEAT_REG_FIRHINC, |
1285 | &hinc_start, &hinc_end); | |
1286 | dss_feat_get_reg_field(FEAT_REG_FIRVINC, | |
1287 | &vinc_start, &vinc_end); | |
1288 | val = FLD_VAL(vinc, vinc_start, vinc_end) | | |
1289 | FLD_VAL(hinc, hinc_start, hinc_end); | |
a0acb557 | 1290 | |
0d66cbb5 AJ |
1291 | dispc_write_reg(DISPC_OVL_FIR(plane), val); |
1292 | } else { | |
1293 | val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); | |
1294 | dispc_write_reg(DISPC_OVL_FIR2(plane), val); | |
1295 | } | |
80c39712 TV |
1296 | } |
1297 | ||
f0e5caab | 1298 | static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1299 | { |
1300 | u32 val; | |
87a7484b | 1301 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1302 | |
87a7484b AT |
1303 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1304 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1305 | ||
1306 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1307 | FLD_VAL(haccu, hor_start, hor_end); | |
1308 | ||
9b372c2d | 1309 | dispc_write_reg(DISPC_OVL_ACCU0(plane), val); |
80c39712 TV |
1310 | } |
1311 | ||
f0e5caab | 1312 | static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1313 | { |
1314 | u32 val; | |
87a7484b | 1315 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1316 | |
87a7484b AT |
1317 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1318 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1319 | ||
1320 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1321 | FLD_VAL(haccu, hor_start, hor_end); | |
1322 | ||
9b372c2d | 1323 | dispc_write_reg(DISPC_OVL_ACCU1(plane), val); |
80c39712 TV |
1324 | } |
1325 | ||
f0e5caab TV |
1326 | static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, |
1327 | int vaccu) | |
ab5ca071 AJ |
1328 | { |
1329 | u32 val; | |
1330 | ||
1331 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1332 | dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); | |
1333 | } | |
1334 | ||
f0e5caab TV |
1335 | static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, |
1336 | int vaccu) | |
ab5ca071 AJ |
1337 | { |
1338 | u32 val; | |
1339 | ||
1340 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1341 | dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); | |
1342 | } | |
80c39712 | 1343 | |
f0e5caab | 1344 | static void dispc_ovl_set_scale_param(enum omap_plane plane, |
80c39712 TV |
1345 | u16 orig_width, u16 orig_height, |
1346 | u16 out_width, u16 out_height, | |
0d66cbb5 AJ |
1347 | bool five_taps, u8 rotation, |
1348 | enum omap_color_component color_comp) | |
80c39712 | 1349 | { |
0d66cbb5 | 1350 | int fir_hinc, fir_vinc; |
80c39712 | 1351 | |
ed14a3ce AJ |
1352 | fir_hinc = 1024 * orig_width / out_width; |
1353 | fir_vinc = 1024 * orig_height / out_height; | |
80c39712 | 1354 | |
debd9074 CM |
1355 | dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, |
1356 | color_comp); | |
f0e5caab | 1357 | dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); |
0d66cbb5 AJ |
1358 | } |
1359 | ||
05dd0f53 CM |
1360 | static void dispc_ovl_set_accu_uv(enum omap_plane plane, |
1361 | u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, | |
1362 | bool ilace, enum omap_color_mode color_mode, u8 rotation) | |
1363 | { | |
1364 | int h_accu2_0, h_accu2_1; | |
1365 | int v_accu2_0, v_accu2_1; | |
1366 | int chroma_hinc, chroma_vinc; | |
1367 | int idx; | |
1368 | ||
1369 | struct accu { | |
1370 | s8 h0_m, h0_n; | |
1371 | s8 h1_m, h1_n; | |
1372 | s8 v0_m, v0_n; | |
1373 | s8 v1_m, v1_n; | |
1374 | }; | |
1375 | ||
1376 | const struct accu *accu_table; | |
1377 | const struct accu *accu_val; | |
1378 | ||
1379 | static const struct accu accu_nv12[4] = { | |
1380 | { 0, 1, 0, 1 , -1, 2, 0, 1 }, | |
1381 | { 1, 2, -3, 4 , 0, 1, 0, 1 }, | |
1382 | { -1, 1, 0, 1 , -1, 2, 0, 1 }, | |
1383 | { -1, 2, -1, 2 , -1, 1, 0, 1 }, | |
1384 | }; | |
1385 | ||
1386 | static const struct accu accu_nv12_ilace[4] = { | |
1387 | { 0, 1, 0, 1 , -3, 4, -1, 4 }, | |
1388 | { -1, 4, -3, 4 , 0, 1, 0, 1 }, | |
1389 | { -1, 1, 0, 1 , -1, 4, -3, 4 }, | |
1390 | { -3, 4, -3, 4 , -1, 1, 0, 1 }, | |
1391 | }; | |
1392 | ||
1393 | static const struct accu accu_yuv[4] = { | |
1394 | { 0, 1, 0, 1, 0, 1, 0, 1 }, | |
1395 | { 0, 1, 0, 1, 0, 1, 0, 1 }, | |
1396 | { -1, 1, 0, 1, 0, 1, 0, 1 }, | |
1397 | { 0, 1, 0, 1, -1, 1, 0, 1 }, | |
1398 | }; | |
1399 | ||
1400 | switch (rotation) { | |
1401 | case OMAP_DSS_ROT_0: | |
1402 | idx = 0; | |
1403 | break; | |
1404 | case OMAP_DSS_ROT_90: | |
1405 | idx = 1; | |
1406 | break; | |
1407 | case OMAP_DSS_ROT_180: | |
1408 | idx = 2; | |
1409 | break; | |
1410 | case OMAP_DSS_ROT_270: | |
1411 | idx = 3; | |
1412 | break; | |
1413 | default: | |
1414 | BUG(); | |
c6eee968 | 1415 | return; |
05dd0f53 CM |
1416 | } |
1417 | ||
1418 | switch (color_mode) { | |
1419 | case OMAP_DSS_COLOR_NV12: | |
1420 | if (ilace) | |
1421 | accu_table = accu_nv12_ilace; | |
1422 | else | |
1423 | accu_table = accu_nv12; | |
1424 | break; | |
1425 | case OMAP_DSS_COLOR_YUV2: | |
1426 | case OMAP_DSS_COLOR_UYVY: | |
1427 | accu_table = accu_yuv; | |
1428 | break; | |
1429 | default: | |
1430 | BUG(); | |
c6eee968 | 1431 | return; |
05dd0f53 CM |
1432 | } |
1433 | ||
1434 | accu_val = &accu_table[idx]; | |
1435 | ||
1436 | chroma_hinc = 1024 * orig_width / out_width; | |
1437 | chroma_vinc = 1024 * orig_height / out_height; | |
1438 | ||
1439 | h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; | |
1440 | h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; | |
1441 | v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; | |
1442 | v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; | |
1443 | ||
1444 | dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); | |
1445 | dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); | |
1446 | } | |
1447 | ||
f0e5caab | 1448 | static void dispc_ovl_set_scaling_common(enum omap_plane plane, |
0d66cbb5 AJ |
1449 | u16 orig_width, u16 orig_height, |
1450 | u16 out_width, u16 out_height, | |
1451 | bool ilace, bool five_taps, | |
1452 | bool fieldmode, enum omap_color_mode color_mode, | |
1453 | u8 rotation) | |
1454 | { | |
1455 | int accu0 = 0; | |
1456 | int accu1 = 0; | |
1457 | u32 l; | |
80c39712 | 1458 | |
f0e5caab | 1459 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1460 | out_width, out_height, five_taps, |
1461 | rotation, DISPC_COLOR_COMPONENT_RGB_Y); | |
9b372c2d | 1462 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1463 | |
87a7484b AT |
1464 | /* RESIZEENABLE and VERTICALTAPS */ |
1465 | l &= ~((0x3 << 5) | (0x1 << 21)); | |
ed14a3ce AJ |
1466 | l |= (orig_width != out_width) ? (1 << 5) : 0; |
1467 | l |= (orig_height != out_height) ? (1 << 6) : 0; | |
87a7484b | 1468 | l |= five_taps ? (1 << 21) : 0; |
80c39712 | 1469 | |
87a7484b AT |
1470 | /* VRESIZECONF and HRESIZECONF */ |
1471 | if (dss_has_feature(FEAT_RESIZECONF)) { | |
1472 | l &= ~(0x3 << 7); | |
0d66cbb5 AJ |
1473 | l |= (orig_width <= out_width) ? 0 : (1 << 7); |
1474 | l |= (orig_height <= out_height) ? 0 : (1 << 8); | |
87a7484b | 1475 | } |
80c39712 | 1476 | |
87a7484b AT |
1477 | /* LINEBUFFERSPLIT */ |
1478 | if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { | |
1479 | l &= ~(0x1 << 22); | |
1480 | l |= five_taps ? (1 << 22) : 0; | |
1481 | } | |
80c39712 | 1482 | |
9b372c2d | 1483 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); |
80c39712 TV |
1484 | |
1485 | /* | |
1486 | * field 0 = even field = bottom field | |
1487 | * field 1 = odd field = top field | |
1488 | */ | |
1489 | if (ilace && !fieldmode) { | |
1490 | accu1 = 0; | |
0d66cbb5 | 1491 | accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; |
80c39712 TV |
1492 | if (accu0 >= 1024/2) { |
1493 | accu1 = 1024/2; | |
1494 | accu0 -= accu1; | |
1495 | } | |
1496 | } | |
1497 | ||
f0e5caab TV |
1498 | dispc_ovl_set_vid_accu0(plane, 0, accu0); |
1499 | dispc_ovl_set_vid_accu1(plane, 0, accu1); | |
80c39712 TV |
1500 | } |
1501 | ||
f0e5caab | 1502 | static void dispc_ovl_set_scaling_uv(enum omap_plane plane, |
0d66cbb5 AJ |
1503 | u16 orig_width, u16 orig_height, |
1504 | u16 out_width, u16 out_height, | |
1505 | bool ilace, bool five_taps, | |
1506 | bool fieldmode, enum omap_color_mode color_mode, | |
1507 | u8 rotation) | |
1508 | { | |
1509 | int scale_x = out_width != orig_width; | |
1510 | int scale_y = out_height != orig_height; | |
f92afae2 | 1511 | bool chroma_upscale = plane != OMAP_DSS_WB ? true : false; |
0d66cbb5 AJ |
1512 | |
1513 | if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) | |
1514 | return; | |
1515 | if ((color_mode != OMAP_DSS_COLOR_YUV2 && | |
1516 | color_mode != OMAP_DSS_COLOR_UYVY && | |
1517 | color_mode != OMAP_DSS_COLOR_NV12)) { | |
1518 | /* reset chroma resampling for RGB formats */ | |
2a5561b1 AT |
1519 | if (plane != OMAP_DSS_WB) |
1520 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); | |
0d66cbb5 AJ |
1521 | return; |
1522 | } | |
36377357 TV |
1523 | |
1524 | dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, | |
1525 | out_height, ilace, color_mode, rotation); | |
1526 | ||
0d66cbb5 AJ |
1527 | switch (color_mode) { |
1528 | case OMAP_DSS_COLOR_NV12: | |
20fbb50b AT |
1529 | if (chroma_upscale) { |
1530 | /* UV is subsampled by 2 horizontally and vertically */ | |
1531 | orig_height >>= 1; | |
1532 | orig_width >>= 1; | |
1533 | } else { | |
1534 | /* UV is downsampled by 2 horizontally and vertically */ | |
1535 | orig_height <<= 1; | |
1536 | orig_width <<= 1; | |
1537 | } | |
1538 | ||
0d66cbb5 AJ |
1539 | break; |
1540 | case OMAP_DSS_COLOR_YUV2: | |
1541 | case OMAP_DSS_COLOR_UYVY: | |
20fbb50b | 1542 | /* For YUV422 with 90/270 rotation, we don't upsample chroma */ |
0d66cbb5 | 1543 | if (rotation == OMAP_DSS_ROT_0 || |
20fbb50b AT |
1544 | rotation == OMAP_DSS_ROT_180) { |
1545 | if (chroma_upscale) | |
1546 | /* UV is subsampled by 2 horizontally */ | |
1547 | orig_width >>= 1; | |
1548 | else | |
1549 | /* UV is downsampled by 2 horizontally */ | |
1550 | orig_width <<= 1; | |
1551 | } | |
1552 | ||
0d66cbb5 AJ |
1553 | /* must use FIR for YUV422 if rotated */ |
1554 | if (rotation != OMAP_DSS_ROT_0) | |
1555 | scale_x = scale_y = true; | |
20fbb50b | 1556 | |
0d66cbb5 AJ |
1557 | break; |
1558 | default: | |
1559 | BUG(); | |
c6eee968 | 1560 | return; |
0d66cbb5 AJ |
1561 | } |
1562 | ||
1563 | if (out_width != orig_width) | |
1564 | scale_x = true; | |
1565 | if (out_height != orig_height) | |
1566 | scale_y = true; | |
1567 | ||
f0e5caab | 1568 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1569 | out_width, out_height, five_taps, |
1570 | rotation, DISPC_COLOR_COMPONENT_UV); | |
1571 | ||
2a5561b1 AT |
1572 | if (plane != OMAP_DSS_WB) |
1573 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), | |
1574 | (scale_x || scale_y) ? 1 : 0, 8, 8); | |
1575 | ||
0d66cbb5 AJ |
1576 | /* set H scaling */ |
1577 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); | |
1578 | /* set V scaling */ | |
1579 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); | |
0d66cbb5 AJ |
1580 | } |
1581 | ||
f0e5caab | 1582 | static void dispc_ovl_set_scaling(enum omap_plane plane, |
0d66cbb5 AJ |
1583 | u16 orig_width, u16 orig_height, |
1584 | u16 out_width, u16 out_height, | |
1585 | bool ilace, bool five_taps, | |
1586 | bool fieldmode, enum omap_color_mode color_mode, | |
1587 | u8 rotation) | |
1588 | { | |
1589 | BUG_ON(plane == OMAP_DSS_GFX); | |
1590 | ||
f0e5caab | 1591 | dispc_ovl_set_scaling_common(plane, |
0d66cbb5 AJ |
1592 | orig_width, orig_height, |
1593 | out_width, out_height, | |
1594 | ilace, five_taps, | |
1595 | fieldmode, color_mode, | |
1596 | rotation); | |
1597 | ||
f0e5caab | 1598 | dispc_ovl_set_scaling_uv(plane, |
0d66cbb5 AJ |
1599 | orig_width, orig_height, |
1600 | out_width, out_height, | |
1601 | ilace, five_taps, | |
1602 | fieldmode, color_mode, | |
1603 | rotation); | |
1604 | } | |
1605 | ||
f0e5caab | 1606 | static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, |
c35eeb2e | 1607 | enum omap_dss_rotation_type rotation_type, |
80c39712 TV |
1608 | bool mirroring, enum omap_color_mode color_mode) |
1609 | { | |
87a7484b AT |
1610 | bool row_repeat = false; |
1611 | int vidrot = 0; | |
1612 | ||
80c39712 TV |
1613 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1614 | color_mode == OMAP_DSS_COLOR_UYVY) { | |
80c39712 TV |
1615 | |
1616 | if (mirroring) { | |
1617 | switch (rotation) { | |
1618 | case OMAP_DSS_ROT_0: | |
1619 | vidrot = 2; | |
1620 | break; | |
1621 | case OMAP_DSS_ROT_90: | |
1622 | vidrot = 1; | |
1623 | break; | |
1624 | case OMAP_DSS_ROT_180: | |
1625 | vidrot = 0; | |
1626 | break; | |
1627 | case OMAP_DSS_ROT_270: | |
1628 | vidrot = 3; | |
1629 | break; | |
1630 | } | |
1631 | } else { | |
1632 | switch (rotation) { | |
1633 | case OMAP_DSS_ROT_0: | |
1634 | vidrot = 0; | |
1635 | break; | |
1636 | case OMAP_DSS_ROT_90: | |
1637 | vidrot = 1; | |
1638 | break; | |
1639 | case OMAP_DSS_ROT_180: | |
1640 | vidrot = 2; | |
1641 | break; | |
1642 | case OMAP_DSS_ROT_270: | |
1643 | vidrot = 3; | |
1644 | break; | |
1645 | } | |
1646 | } | |
1647 | ||
80c39712 | 1648 | if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) |
87a7484b | 1649 | row_repeat = true; |
80c39712 | 1650 | else |
87a7484b | 1651 | row_repeat = false; |
80c39712 | 1652 | } |
87a7484b | 1653 | |
9b372c2d | 1654 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); |
87a7484b | 1655 | if (dss_has_feature(FEAT_ROWREPEATENABLE)) |
9b372c2d AT |
1656 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), |
1657 | row_repeat ? 1 : 0, 18, 18); | |
c35eeb2e AT |
1658 | |
1659 | if (color_mode == OMAP_DSS_COLOR_NV12) { | |
1660 | bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) && | |
1661 | (rotation == OMAP_DSS_ROT_0 || | |
1662 | rotation == OMAP_DSS_ROT_180); | |
1663 | /* DOUBLESTRIDE */ | |
1664 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); | |
1665 | } | |
1666 | ||
80c39712 TV |
1667 | } |
1668 | ||
1669 | static int color_mode_to_bpp(enum omap_color_mode color_mode) | |
1670 | { | |
1671 | switch (color_mode) { | |
1672 | case OMAP_DSS_COLOR_CLUT1: | |
1673 | return 1; | |
1674 | case OMAP_DSS_COLOR_CLUT2: | |
1675 | return 2; | |
1676 | case OMAP_DSS_COLOR_CLUT4: | |
1677 | return 4; | |
1678 | case OMAP_DSS_COLOR_CLUT8: | |
f20e4220 | 1679 | case OMAP_DSS_COLOR_NV12: |
80c39712 TV |
1680 | return 8; |
1681 | case OMAP_DSS_COLOR_RGB12U: | |
1682 | case OMAP_DSS_COLOR_RGB16: | |
1683 | case OMAP_DSS_COLOR_ARGB16: | |
1684 | case OMAP_DSS_COLOR_YUV2: | |
1685 | case OMAP_DSS_COLOR_UYVY: | |
f20e4220 AJ |
1686 | case OMAP_DSS_COLOR_RGBA16: |
1687 | case OMAP_DSS_COLOR_RGBX16: | |
1688 | case OMAP_DSS_COLOR_ARGB16_1555: | |
1689 | case OMAP_DSS_COLOR_XRGB16_1555: | |
80c39712 TV |
1690 | return 16; |
1691 | case OMAP_DSS_COLOR_RGB24P: | |
1692 | return 24; | |
1693 | case OMAP_DSS_COLOR_RGB24U: | |
1694 | case OMAP_DSS_COLOR_ARGB32: | |
1695 | case OMAP_DSS_COLOR_RGBA32: | |
1696 | case OMAP_DSS_COLOR_RGBX32: | |
1697 | return 32; | |
1698 | default: | |
1699 | BUG(); | |
c6eee968 | 1700 | return 0; |
80c39712 TV |
1701 | } |
1702 | } | |
1703 | ||
1704 | static s32 pixinc(int pixels, u8 ps) | |
1705 | { | |
1706 | if (pixels == 1) | |
1707 | return 1; | |
1708 | else if (pixels > 1) | |
1709 | return 1 + (pixels - 1) * ps; | |
1710 | else if (pixels < 0) | |
1711 | return 1 - (-pixels + 1) * ps; | |
1712 | else | |
1713 | BUG(); | |
c6eee968 | 1714 | return 0; |
80c39712 TV |
1715 | } |
1716 | ||
1717 | static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, | |
1718 | u16 screen_width, | |
1719 | u16 width, u16 height, | |
1720 | enum omap_color_mode color_mode, bool fieldmode, | |
1721 | unsigned int field_offset, | |
1722 | unsigned *offset0, unsigned *offset1, | |
aed74b55 | 1723 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) |
80c39712 TV |
1724 | { |
1725 | u8 ps; | |
1726 | ||
1727 | /* FIXME CLUT formats */ | |
1728 | switch (color_mode) { | |
1729 | case OMAP_DSS_COLOR_CLUT1: | |
1730 | case OMAP_DSS_COLOR_CLUT2: | |
1731 | case OMAP_DSS_COLOR_CLUT4: | |
1732 | case OMAP_DSS_COLOR_CLUT8: | |
1733 | BUG(); | |
1734 | return; | |
1735 | case OMAP_DSS_COLOR_YUV2: | |
1736 | case OMAP_DSS_COLOR_UYVY: | |
1737 | ps = 4; | |
1738 | break; | |
1739 | default: | |
1740 | ps = color_mode_to_bpp(color_mode) / 8; | |
1741 | break; | |
1742 | } | |
1743 | ||
1744 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1745 | width, height); | |
1746 | ||
1747 | /* | |
1748 | * field 0 = even field = bottom field | |
1749 | * field 1 = odd field = top field | |
1750 | */ | |
1751 | switch (rotation + mirror * 4) { | |
1752 | case OMAP_DSS_ROT_0: | |
1753 | case OMAP_DSS_ROT_180: | |
1754 | /* | |
1755 | * If the pixel format is YUV or UYVY divide the width | |
1756 | * of the image by 2 for 0 and 180 degree rotation. | |
1757 | */ | |
1758 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1759 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1760 | width = width >> 1; | |
1761 | case OMAP_DSS_ROT_90: | |
1762 | case OMAP_DSS_ROT_270: | |
1763 | *offset1 = 0; | |
1764 | if (field_offset) | |
1765 | *offset0 = field_offset * screen_width * ps; | |
1766 | else | |
1767 | *offset0 = 0; | |
1768 | ||
aed74b55 CM |
1769 | *row_inc = pixinc(1 + |
1770 | (y_predecim * screen_width - x_predecim * width) + | |
1771 | (fieldmode ? screen_width : 0), ps); | |
1772 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1773 | break; |
1774 | ||
1775 | case OMAP_DSS_ROT_0 + 4: | |
1776 | case OMAP_DSS_ROT_180 + 4: | |
1777 | /* If the pixel format is YUV or UYVY divide the width | |
1778 | * of the image by 2 for 0 degree and 180 degree | |
1779 | */ | |
1780 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1781 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1782 | width = width >> 1; | |
1783 | case OMAP_DSS_ROT_90 + 4: | |
1784 | case OMAP_DSS_ROT_270 + 4: | |
1785 | *offset1 = 0; | |
1786 | if (field_offset) | |
1787 | *offset0 = field_offset * screen_width * ps; | |
1788 | else | |
1789 | *offset0 = 0; | |
aed74b55 CM |
1790 | *row_inc = pixinc(1 - |
1791 | (y_predecim * screen_width + x_predecim * width) - | |
1792 | (fieldmode ? screen_width : 0), ps); | |
1793 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1794 | break; |
1795 | ||
1796 | default: | |
1797 | BUG(); | |
c6eee968 | 1798 | return; |
80c39712 TV |
1799 | } |
1800 | } | |
1801 | ||
1802 | static void calc_dma_rotation_offset(u8 rotation, bool mirror, | |
1803 | u16 screen_width, | |
1804 | u16 width, u16 height, | |
1805 | enum omap_color_mode color_mode, bool fieldmode, | |
1806 | unsigned int field_offset, | |
1807 | unsigned *offset0, unsigned *offset1, | |
aed74b55 | 1808 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) |
80c39712 TV |
1809 | { |
1810 | u8 ps; | |
1811 | u16 fbw, fbh; | |
1812 | ||
1813 | /* FIXME CLUT formats */ | |
1814 | switch (color_mode) { | |
1815 | case OMAP_DSS_COLOR_CLUT1: | |
1816 | case OMAP_DSS_COLOR_CLUT2: | |
1817 | case OMAP_DSS_COLOR_CLUT4: | |
1818 | case OMAP_DSS_COLOR_CLUT8: | |
1819 | BUG(); | |
1820 | return; | |
1821 | default: | |
1822 | ps = color_mode_to_bpp(color_mode) / 8; | |
1823 | break; | |
1824 | } | |
1825 | ||
1826 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1827 | width, height); | |
1828 | ||
1829 | /* width & height are overlay sizes, convert to fb sizes */ | |
1830 | ||
1831 | if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { | |
1832 | fbw = width; | |
1833 | fbh = height; | |
1834 | } else { | |
1835 | fbw = height; | |
1836 | fbh = width; | |
1837 | } | |
1838 | ||
1839 | /* | |
1840 | * field 0 = even field = bottom field | |
1841 | * field 1 = odd field = top field | |
1842 | */ | |
1843 | switch (rotation + mirror * 4) { | |
1844 | case OMAP_DSS_ROT_0: | |
1845 | *offset1 = 0; | |
1846 | if (field_offset) | |
1847 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1848 | else | |
1849 | *offset0 = *offset1; | |
aed74b55 CM |
1850 | *row_inc = pixinc(1 + |
1851 | (y_predecim * screen_width - fbw * x_predecim) + | |
1852 | (fieldmode ? screen_width : 0), ps); | |
1853 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1854 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1855 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
1856 | else | |
1857 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1858 | break; |
1859 | case OMAP_DSS_ROT_90: | |
1860 | *offset1 = screen_width * (fbh - 1) * ps; | |
1861 | if (field_offset) | |
1862 | *offset0 = *offset1 + field_offset * ps; | |
1863 | else | |
1864 | *offset0 = *offset1; | |
aed74b55 CM |
1865 | *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + |
1866 | y_predecim + (fieldmode ? 1 : 0), ps); | |
1867 | *pix_inc = pixinc(-x_predecim * screen_width, ps); | |
80c39712 TV |
1868 | break; |
1869 | case OMAP_DSS_ROT_180: | |
1870 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
1871 | if (field_offset) | |
1872 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
1873 | else | |
1874 | *offset0 = *offset1; | |
1875 | *row_inc = pixinc(-1 - | |
aed74b55 CM |
1876 | (y_predecim * screen_width - fbw * x_predecim) - |
1877 | (fieldmode ? screen_width : 0), ps); | |
1878 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1879 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1880 | *pix_inc = pixinc(-x_predecim, 2 * ps); | |
1881 | else | |
1882 | *pix_inc = pixinc(-x_predecim, ps); | |
80c39712 TV |
1883 | break; |
1884 | case OMAP_DSS_ROT_270: | |
1885 | *offset1 = (fbw - 1) * ps; | |
1886 | if (field_offset) | |
1887 | *offset0 = *offset1 - field_offset * ps; | |
1888 | else | |
1889 | *offset0 = *offset1; | |
aed74b55 CM |
1890 | *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - |
1891 | y_predecim - (fieldmode ? 1 : 0), ps); | |
1892 | *pix_inc = pixinc(x_predecim * screen_width, ps); | |
80c39712 TV |
1893 | break; |
1894 | ||
1895 | /* mirroring */ | |
1896 | case OMAP_DSS_ROT_0 + 4: | |
1897 | *offset1 = (fbw - 1) * ps; | |
1898 | if (field_offset) | |
1899 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1900 | else | |
1901 | *offset0 = *offset1; | |
aed74b55 | 1902 | *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + |
80c39712 TV |
1903 | (fieldmode ? screen_width : 0), |
1904 | ps); | |
aed74b55 CM |
1905 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1906 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1907 | *pix_inc = pixinc(-x_predecim, 2 * ps); | |
1908 | else | |
1909 | *pix_inc = pixinc(-x_predecim, ps); | |
80c39712 TV |
1910 | break; |
1911 | ||
1912 | case OMAP_DSS_ROT_90 + 4: | |
1913 | *offset1 = 0; | |
1914 | if (field_offset) | |
1915 | *offset0 = *offset1 + field_offset * ps; | |
1916 | else | |
1917 | *offset0 = *offset1; | |
aed74b55 CM |
1918 | *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + |
1919 | y_predecim + (fieldmode ? 1 : 0), | |
80c39712 | 1920 | ps); |
aed74b55 | 1921 | *pix_inc = pixinc(x_predecim * screen_width, ps); |
80c39712 TV |
1922 | break; |
1923 | ||
1924 | case OMAP_DSS_ROT_180 + 4: | |
1925 | *offset1 = screen_width * (fbh - 1) * ps; | |
1926 | if (field_offset) | |
1927 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
1928 | else | |
1929 | *offset0 = *offset1; | |
aed74b55 | 1930 | *row_inc = pixinc(1 - y_predecim * screen_width * 2 - |
80c39712 TV |
1931 | (fieldmode ? screen_width : 0), |
1932 | ps); | |
aed74b55 CM |
1933 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1934 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1935 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
1936 | else | |
1937 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1938 | break; |
1939 | ||
1940 | case OMAP_DSS_ROT_270 + 4: | |
1941 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
1942 | if (field_offset) | |
1943 | *offset0 = *offset1 - field_offset * ps; | |
1944 | else | |
1945 | *offset0 = *offset1; | |
aed74b55 CM |
1946 | *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - |
1947 | y_predecim - (fieldmode ? 1 : 0), | |
80c39712 | 1948 | ps); |
aed74b55 | 1949 | *pix_inc = pixinc(-x_predecim * screen_width, ps); |
80c39712 TV |
1950 | break; |
1951 | ||
1952 | default: | |
1953 | BUG(); | |
c6eee968 | 1954 | return; |
80c39712 TV |
1955 | } |
1956 | } | |
1957 | ||
65e006ff CM |
1958 | static void calc_tiler_rotation_offset(u16 screen_width, u16 width, |
1959 | enum omap_color_mode color_mode, bool fieldmode, | |
1960 | unsigned int field_offset, unsigned *offset0, unsigned *offset1, | |
1961 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) | |
1962 | { | |
1963 | u8 ps; | |
1964 | ||
1965 | switch (color_mode) { | |
1966 | case OMAP_DSS_COLOR_CLUT1: | |
1967 | case OMAP_DSS_COLOR_CLUT2: | |
1968 | case OMAP_DSS_COLOR_CLUT4: | |
1969 | case OMAP_DSS_COLOR_CLUT8: | |
1970 | BUG(); | |
1971 | return; | |
1972 | default: | |
1973 | ps = color_mode_to_bpp(color_mode) / 8; | |
1974 | break; | |
1975 | } | |
1976 | ||
1977 | DSSDBG("scrw %d, width %d\n", screen_width, width); | |
1978 | ||
1979 | /* | |
1980 | * field 0 = even field = bottom field | |
1981 | * field 1 = odd field = top field | |
1982 | */ | |
1983 | *offset1 = 0; | |
1984 | if (field_offset) | |
1985 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1986 | else | |
1987 | *offset0 = *offset1; | |
1988 | *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + | |
1989 | (fieldmode ? screen_width : 0), ps); | |
1990 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1991 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1992 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
1993 | else | |
1994 | *pix_inc = pixinc(x_predecim, ps); | |
1995 | } | |
1996 | ||
7faa9233 CM |
1997 | /* |
1998 | * This function is used to avoid synclosts in OMAP3, because of some | |
1999 | * undocumented horizontal position and timing related limitations. | |
2000 | */ | |
465ec13f | 2001 | static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk, |
81ab95b7 | 2002 | const struct omap_video_timings *t, u16 pos_x, |
e4998634 ID |
2003 | u16 width, u16 height, u16 out_width, u16 out_height, |
2004 | bool five_taps) | |
7faa9233 | 2005 | { |
230edc03 | 2006 | const int ds = DIV_ROUND_UP(height, out_height); |
3e8a6ff2 | 2007 | unsigned long nonactive; |
7faa9233 CM |
2008 | static const u8 limits[3] = { 8, 10, 20 }; |
2009 | u64 val, blank; | |
2010 | int i; | |
2011 | ||
81ab95b7 | 2012 | nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; |
7faa9233 CM |
2013 | |
2014 | i = 0; | |
2015 | if (out_height < height) | |
2016 | i++; | |
2017 | if (out_width < width) | |
2018 | i++; | |
81ab95b7 | 2019 | blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); |
7faa9233 CM |
2020 | DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); |
2021 | if (blank <= limits[i]) | |
2022 | return -EINVAL; | |
2023 | ||
e4998634 ID |
2024 | /* FIXME add checks for 3-tap filter once the limitations are known */ |
2025 | if (!five_taps) | |
2026 | return 0; | |
2027 | ||
7faa9233 CM |
2028 | /* |
2029 | * Pixel data should be prepared before visible display point starts. | |
2030 | * So, atleast DS-2 lines must have already been fetched by DISPC | |
2031 | * during nonactive - pos_x period. | |
2032 | */ | |
2033 | val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); | |
2034 | DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", | |
230edc03 TV |
2035 | val, max(0, ds - 2) * width); |
2036 | if (val < max(0, ds - 2) * width) | |
7faa9233 CM |
2037 | return -EINVAL; |
2038 | ||
2039 | /* | |
2040 | * All lines need to be refilled during the nonactive period of which | |
2041 | * only one line can be loaded during the active period. So, atleast | |
2042 | * DS - 1 lines should be loaded during nonactive period. | |
2043 | */ | |
2044 | val = div_u64((u64)nonactive * lclk, pclk); | |
2045 | DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", | |
230edc03 TV |
2046 | val, max(0, ds - 1) * width); |
2047 | if (val < max(0, ds - 1) * width) | |
7faa9233 CM |
2048 | return -EINVAL; |
2049 | ||
2050 | return 0; | |
2051 | } | |
2052 | ||
8702ee50 | 2053 | static unsigned long calc_core_clk_five_taps(unsigned long pclk, |
81ab95b7 AT |
2054 | const struct omap_video_timings *mgr_timings, u16 width, |
2055 | u16 height, u16 out_width, u16 out_height, | |
ff1b2cde | 2056 | enum omap_color_mode color_mode) |
80c39712 | 2057 | { |
8b53d991 | 2058 | u32 core_clk = 0; |
3e8a6ff2 | 2059 | u64 tmp; |
80c39712 | 2060 | |
7282f1b7 CM |
2061 | if (height <= out_height && width <= out_width) |
2062 | return (unsigned long) pclk; | |
2063 | ||
80c39712 | 2064 | if (height > out_height) { |
81ab95b7 | 2065 | unsigned int ppl = mgr_timings->x_res; |
80c39712 TV |
2066 | |
2067 | tmp = pclk * height * out_width; | |
2068 | do_div(tmp, 2 * out_height * ppl); | |
8b53d991 | 2069 | core_clk = tmp; |
80c39712 | 2070 | |
2d9c5597 VS |
2071 | if (height > 2 * out_height) { |
2072 | if (ppl == out_width) | |
2073 | return 0; | |
2074 | ||
80c39712 TV |
2075 | tmp = pclk * (height - 2 * out_height) * out_width; |
2076 | do_div(tmp, 2 * out_height * (ppl - out_width)); | |
8b53d991 | 2077 | core_clk = max_t(u32, core_clk, tmp); |
80c39712 TV |
2078 | } |
2079 | } | |
2080 | ||
2081 | if (width > out_width) { | |
2082 | tmp = pclk * width; | |
2083 | do_div(tmp, out_width); | |
8b53d991 | 2084 | core_clk = max_t(u32, core_clk, tmp); |
80c39712 TV |
2085 | |
2086 | if (color_mode == OMAP_DSS_COLOR_RGB24U) | |
8b53d991 | 2087 | core_clk <<= 1; |
80c39712 TV |
2088 | } |
2089 | ||
8b53d991 | 2090 | return core_clk; |
80c39712 TV |
2091 | } |
2092 | ||
8702ee50 | 2093 | static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, |
8ba85306 | 2094 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
dcbe765b | 2095 | { |
dcbe765b CM |
2096 | if (height > out_height && width > out_width) |
2097 | return pclk * 4; | |
2098 | else | |
2099 | return pclk * 2; | |
2100 | } | |
2101 | ||
8702ee50 | 2102 | static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, |
8ba85306 | 2103 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
80c39712 TV |
2104 | { |
2105 | unsigned int hf, vf; | |
2106 | ||
2107 | /* | |
2108 | * FIXME how to determine the 'A' factor | |
2109 | * for the no downscaling case ? | |
2110 | */ | |
2111 | ||
2112 | if (width > 3 * out_width) | |
2113 | hf = 4; | |
2114 | else if (width > 2 * out_width) | |
2115 | hf = 3; | |
2116 | else if (width > out_width) | |
2117 | hf = 2; | |
2118 | else | |
2119 | hf = 1; | |
80c39712 TV |
2120 | if (height > out_height) |
2121 | vf = 2; | |
2122 | else | |
2123 | vf = 1; | |
2124 | ||
dcbe765b CM |
2125 | return pclk * vf * hf; |
2126 | } | |
2127 | ||
8702ee50 | 2128 | static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, |
8ba85306 | 2129 | u16 height, u16 out_width, u16 out_height, bool mem_to_mem) |
dcbe765b | 2130 | { |
8ba85306 AT |
2131 | /* |
2132 | * If the overlay/writeback is in mem to mem mode, there are no | |
2133 | * downscaling limitations with respect to pixel clock, return 1 as | |
2134 | * required core clock to represent that we have sufficient enough | |
2135 | * core clock to do maximum downscaling | |
2136 | */ | |
2137 | if (mem_to_mem) | |
2138 | return 1; | |
2139 | ||
dcbe765b CM |
2140 | if (width > out_width) |
2141 | return DIV_ROUND_UP(pclk, out_width) * width; | |
2142 | else | |
2143 | return pclk; | |
2144 | } | |
2145 | ||
0c6921de | 2146 | static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2147 | const struct omap_video_timings *mgr_timings, |
2148 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2149 | enum omap_color_mode color_mode, bool *five_taps, | |
2150 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2151 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2152 | { |
2153 | int error; | |
2154 | u16 in_width, in_height; | |
2155 | int min_factor = min(*decim_x, *decim_y); | |
2156 | const int maxsinglelinewidth = | |
2157 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
3e8a6ff2 | 2158 | |
dcbe765b CM |
2159 | *five_taps = false; |
2160 | ||
2161 | do { | |
eec77da2 TV |
2162 | in_height = height / *decim_y; |
2163 | in_width = width / *decim_x; | |
8702ee50 | 2164 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, |
8ba85306 | 2165 | in_height, out_width, out_height, mem_to_mem); |
dcbe765b CM |
2166 | error = (in_width > maxsinglelinewidth || !*core_clk || |
2167 | *core_clk > dispc_core_clk_rate()); | |
2168 | if (error) { | |
2169 | if (*decim_x == *decim_y) { | |
2170 | *decim_x = min_factor; | |
2171 | ++*decim_y; | |
2172 | } else { | |
2173 | swap(*decim_x, *decim_y); | |
2174 | if (*decim_x < *decim_y) | |
2175 | ++*decim_x; | |
2176 | } | |
2177 | } | |
2178 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | |
2179 | ||
2180 | if (in_width > maxsinglelinewidth) { | |
2181 | DSSERR("Cannot scale max input width exceeded"); | |
2182 | return -EINVAL; | |
2183 | } | |
2184 | return 0; | |
2185 | } | |
2186 | ||
0c6921de | 2187 | static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2188 | const struct omap_video_timings *mgr_timings, |
2189 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2190 | enum omap_color_mode color_mode, bool *five_taps, | |
2191 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2192 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2193 | { |
2194 | int error; | |
2195 | u16 in_width, in_height; | |
2196 | int min_factor = min(*decim_x, *decim_y); | |
2197 | const int maxsinglelinewidth = | |
2198 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
2199 | ||
2200 | do { | |
eec77da2 TV |
2201 | in_height = height / *decim_y; |
2202 | in_width = width / *decim_x; | |
e4998634 | 2203 | *five_taps = in_height > out_height; |
dcbe765b CM |
2204 | |
2205 | if (in_width > maxsinglelinewidth) | |
2206 | if (in_height > out_height && | |
2207 | in_height < out_height * 2) | |
2208 | *five_taps = false; | |
e4998634 ID |
2209 | again: |
2210 | if (*five_taps) | |
2211 | *core_clk = calc_core_clk_five_taps(pclk, mgr_timings, | |
2212 | in_width, in_height, out_width, | |
2213 | out_height, color_mode); | |
2214 | else | |
8702ee50 | 2215 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, |
8ba85306 AT |
2216 | in_height, out_width, out_height, |
2217 | mem_to_mem); | |
dcbe765b | 2218 | |
e4998634 ID |
2219 | error = check_horiz_timing_omap3(pclk, lclk, mgr_timings, |
2220 | pos_x, in_width, in_height, out_width, | |
2221 | out_height, *five_taps); | |
2222 | if (error && *five_taps) { | |
2223 | *five_taps = false; | |
2224 | goto again; | |
2225 | } | |
2226 | ||
dcbe765b CM |
2227 | error = (error || in_width > maxsinglelinewidth * 2 || |
2228 | (in_width > maxsinglelinewidth && *five_taps) || | |
2229 | !*core_clk || *core_clk > dispc_core_clk_rate()); | |
2230 | if (error) { | |
2231 | if (*decim_x == *decim_y) { | |
2232 | *decim_x = min_factor; | |
2233 | ++*decim_y; | |
2234 | } else { | |
2235 | swap(*decim_x, *decim_y); | |
2236 | if (*decim_x < *decim_y) | |
2237 | ++*decim_x; | |
2238 | } | |
2239 | } | |
2240 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | |
2241 | ||
465ec13f | 2242 | if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width, |
e4998634 | 2243 | height, out_width, out_height, *five_taps)) { |
dcbe765b CM |
2244 | DSSERR("horizontal timing too tight\n"); |
2245 | return -EINVAL; | |
7282f1b7 | 2246 | } |
dcbe765b CM |
2247 | |
2248 | if (in_width > (maxsinglelinewidth * 2)) { | |
2249 | DSSERR("Cannot setup scaling"); | |
2250 | DSSERR("width exceeds maximum width possible"); | |
2251 | return -EINVAL; | |
2252 | } | |
2253 | ||
2254 | if (in_width > maxsinglelinewidth && *five_taps) { | |
2255 | DSSERR("cannot setup scaling with five taps"); | |
2256 | return -EINVAL; | |
2257 | } | |
2258 | return 0; | |
2259 | } | |
2260 | ||
0c6921de | 2261 | static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, |
dcbe765b CM |
2262 | const struct omap_video_timings *mgr_timings, |
2263 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2264 | enum omap_color_mode color_mode, bool *five_taps, | |
2265 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
8ba85306 | 2266 | u16 pos_x, unsigned long *core_clk, bool mem_to_mem) |
dcbe765b CM |
2267 | { |
2268 | u16 in_width, in_width_max; | |
2269 | int decim_x_min = *decim_x; | |
eec77da2 | 2270 | u16 in_height = height / *decim_y; |
dcbe765b CM |
2271 | const int maxsinglelinewidth = |
2272 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
8ba85306 | 2273 | const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); |
3e8a6ff2 | 2274 | |
5d501085 AT |
2275 | if (mem_to_mem) { |
2276 | in_width_max = out_width * maxdownscale; | |
2277 | } else { | |
8ba85306 AT |
2278 | in_width_max = dispc_core_clk_rate() / |
2279 | DIV_ROUND_UP(pclk, out_width); | |
5d501085 | 2280 | } |
dcbe765b | 2281 | |
dcbe765b CM |
2282 | *decim_x = DIV_ROUND_UP(width, in_width_max); |
2283 | ||
2284 | *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; | |
2285 | if (*decim_x > *x_predecim) | |
2286 | return -EINVAL; | |
2287 | ||
2288 | do { | |
eec77da2 | 2289 | in_width = width / *decim_x; |
dcbe765b CM |
2290 | } while (*decim_x <= *x_predecim && |
2291 | in_width > maxsinglelinewidth && ++*decim_x); | |
2292 | ||
2293 | if (in_width > maxsinglelinewidth) { | |
2294 | DSSERR("Cannot scale width exceeds max line width"); | |
2295 | return -EINVAL; | |
2296 | } | |
2297 | ||
8702ee50 | 2298 | *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, |
8ba85306 | 2299 | out_width, out_height, mem_to_mem); |
dcbe765b | 2300 | return 0; |
80c39712 TV |
2301 | } |
2302 | ||
74e16458 | 2303 | static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, |
3e8a6ff2 | 2304 | enum omap_overlay_caps caps, |
81ab95b7 AT |
2305 | const struct omap_video_timings *mgr_timings, |
2306 | u16 width, u16 height, u16 out_width, u16 out_height, | |
aed74b55 | 2307 | enum omap_color_mode color_mode, bool *five_taps, |
d557a9cf | 2308 | int *x_predecim, int *y_predecim, u16 pos_x, |
8ba85306 | 2309 | enum omap_dss_rotation_type rotation_type, bool mem_to_mem) |
79ad75f2 | 2310 | { |
0373cac6 | 2311 | const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); |
aed74b55 | 2312 | const int max_decim_limit = 16; |
8b53d991 | 2313 | unsigned long core_clk = 0; |
dcbe765b | 2314 | int decim_x, decim_y, ret; |
79ad75f2 | 2315 | |
f95cb5eb TV |
2316 | if (width == out_width && height == out_height) |
2317 | return 0; | |
2318 | ||
5b54ed3e | 2319 | if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0) |
f95cb5eb | 2320 | return -EINVAL; |
79ad75f2 | 2321 | |
74e16458 | 2322 | if (mem_to_mem) { |
1c031441 AT |
2323 | *x_predecim = *y_predecim = 1; |
2324 | } else { | |
2325 | *x_predecim = max_decim_limit; | |
2326 | *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && | |
2327 | dss_has_feature(FEAT_BURST_2D)) ? | |
2328 | 2 : max_decim_limit; | |
2329 | } | |
aed74b55 CM |
2330 | |
2331 | if (color_mode == OMAP_DSS_COLOR_CLUT1 || | |
2332 | color_mode == OMAP_DSS_COLOR_CLUT2 || | |
2333 | color_mode == OMAP_DSS_COLOR_CLUT4 || | |
2334 | color_mode == OMAP_DSS_COLOR_CLUT8) { | |
2335 | *x_predecim = 1; | |
2336 | *y_predecim = 1; | |
2337 | *five_taps = false; | |
2338 | return 0; | |
2339 | } | |
2340 | ||
2341 | decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); | |
2342 | decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); | |
2343 | ||
aed74b55 | 2344 | if (decim_x > *x_predecim || out_width > width * 8) |
79ad75f2 AT |
2345 | return -EINVAL; |
2346 | ||
aed74b55 | 2347 | if (decim_y > *y_predecim || out_height > height * 8) |
79ad75f2 AT |
2348 | return -EINVAL; |
2349 | ||
0c6921de | 2350 | ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height, |
3e8a6ff2 | 2351 | out_width, out_height, color_mode, five_taps, |
8ba85306 AT |
2352 | x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, |
2353 | mem_to_mem); | |
dcbe765b CM |
2354 | if (ret) |
2355 | return ret; | |
79ad75f2 | 2356 | |
8b53d991 CM |
2357 | DSSDBG("required core clk rate = %lu Hz\n", core_clk); |
2358 | DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate()); | |
79ad75f2 | 2359 | |
8b53d991 | 2360 | if (!core_clk || core_clk > dispc_core_clk_rate()) { |
79ad75f2 | 2361 | DSSERR("failed to set up scaling, " |
8b53d991 CM |
2362 | "required core clk rate = %lu Hz, " |
2363 | "current core clk rate = %lu Hz\n", | |
2364 | core_clk, dispc_core_clk_rate()); | |
79ad75f2 AT |
2365 | return -EINVAL; |
2366 | } | |
2367 | ||
aed74b55 CM |
2368 | *x_predecim = decim_x; |
2369 | *y_predecim = decim_y; | |
79ad75f2 AT |
2370 | return 0; |
2371 | } | |
2372 | ||
f9b719b6 TV |
2373 | int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, |
2374 | const struct omap_overlay_info *oi, | |
2375 | const struct omap_video_timings *timings, | |
2376 | int *x_predecim, int *y_predecim) | |
2377 | { | |
2378 | enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); | |
2379 | bool five_taps = true; | |
62a83183 | 2380 | bool fieldmode = false; |
f9b719b6 TV |
2381 | u16 in_height = oi->height; |
2382 | u16 in_width = oi->width; | |
2383 | bool ilace = timings->interlace; | |
2384 | u16 out_width, out_height; | |
2385 | int pos_x = oi->pos_x; | |
2386 | unsigned long pclk = dispc_mgr_pclk_rate(channel); | |
2387 | unsigned long lclk = dispc_mgr_lclk_rate(channel); | |
2388 | ||
2389 | out_width = oi->out_width == 0 ? oi->width : oi->out_width; | |
2390 | out_height = oi->out_height == 0 ? oi->height : oi->out_height; | |
2391 | ||
2392 | if (ilace && oi->height == out_height) | |
62a83183 | 2393 | fieldmode = true; |
f9b719b6 TV |
2394 | |
2395 | if (ilace) { | |
2396 | if (fieldmode) | |
2397 | in_height /= 2; | |
2398 | out_height /= 2; | |
2399 | ||
2400 | DSSDBG("adjusting for ilace: height %d, out_height %d\n", | |
2401 | in_height, out_height); | |
2402 | } | |
2403 | ||
2404 | if (!dss_feat_color_mode_supported(plane, oi->color_mode)) | |
2405 | return -EINVAL; | |
2406 | ||
2407 | return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width, | |
2408 | in_height, out_width, out_height, oi->color_mode, | |
2409 | &five_taps, x_predecim, y_predecim, pos_x, | |
2410 | oi->rotation_type, false); | |
2411 | } | |
348be69d | 2412 | EXPORT_SYMBOL(dispc_ovl_check); |
f9b719b6 | 2413 | |
84a880fd | 2414 | static int dispc_ovl_setup_common(enum omap_plane plane, |
3e8a6ff2 AT |
2415 | enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, |
2416 | u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, | |
2417 | u16 out_width, u16 out_height, enum omap_color_mode color_mode, | |
2418 | u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha, | |
2419 | u8 global_alpha, enum omap_dss_rotation_type rotation_type, | |
8ba85306 AT |
2420 | bool replication, const struct omap_video_timings *mgr_timings, |
2421 | bool mem_to_mem) | |
80c39712 | 2422 | { |
7282f1b7 | 2423 | bool five_taps = true; |
62a83183 | 2424 | bool fieldmode = false; |
79ad75f2 | 2425 | int r, cconv = 0; |
80c39712 TV |
2426 | unsigned offset0, offset1; |
2427 | s32 row_inc; | |
2428 | s32 pix_inc; | |
6be0d73e | 2429 | u16 frame_width, frame_height; |
80c39712 | 2430 | unsigned int field_offset = 0; |
84a880fd AT |
2431 | u16 in_height = height; |
2432 | u16 in_width = width; | |
aed74b55 | 2433 | int x_predecim = 1, y_predecim = 1; |
8050cbe4 | 2434 | bool ilace = mgr_timings->interlace; |
74e16458 TV |
2435 | unsigned long pclk = dispc_plane_pclk_rate(plane); |
2436 | unsigned long lclk = dispc_plane_lclk_rate(plane); | |
e6d80f95 | 2437 | |
84a880fd | 2438 | if (paddr == 0) |
80c39712 TV |
2439 | return -EINVAL; |
2440 | ||
84a880fd AT |
2441 | out_width = out_width == 0 ? width : out_width; |
2442 | out_height = out_height == 0 ? height : out_height; | |
cf073668 | 2443 | |
84a880fd | 2444 | if (ilace && height == out_height) |
62a83183 | 2445 | fieldmode = true; |
80c39712 TV |
2446 | |
2447 | if (ilace) { | |
2448 | if (fieldmode) | |
aed74b55 | 2449 | in_height /= 2; |
8eeb7019 | 2450 | pos_y /= 2; |
aed74b55 | 2451 | out_height /= 2; |
80c39712 TV |
2452 | |
2453 | DSSDBG("adjusting for ilace: height %d, pos_y %d, " | |
84a880fd AT |
2454 | "out_height %d\n", in_height, pos_y, |
2455 | out_height); | |
80c39712 TV |
2456 | } |
2457 | ||
84a880fd | 2458 | if (!dss_feat_color_mode_supported(plane, color_mode)) |
8dad2ab6 AT |
2459 | return -EINVAL; |
2460 | ||
74e16458 | 2461 | r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width, |
84a880fd AT |
2462 | in_height, out_width, out_height, color_mode, |
2463 | &five_taps, &x_predecim, &y_predecim, pos_x, | |
8ba85306 | 2464 | rotation_type, mem_to_mem); |
79ad75f2 AT |
2465 | if (r) |
2466 | return r; | |
80c39712 | 2467 | |
eec77da2 TV |
2468 | in_width = in_width / x_predecim; |
2469 | in_height = in_height / y_predecim; | |
aed74b55 | 2470 | |
84a880fd AT |
2471 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
2472 | color_mode == OMAP_DSS_COLOR_UYVY || | |
2473 | color_mode == OMAP_DSS_COLOR_NV12) | |
79ad75f2 | 2474 | cconv = 1; |
80c39712 TV |
2475 | |
2476 | if (ilace && !fieldmode) { | |
2477 | /* | |
2478 | * when downscaling the bottom field may have to start several | |
2479 | * source lines below the top field. Unfortunately ACCUI | |
2480 | * registers will only hold the fractional part of the offset | |
2481 | * so the integer part must be added to the base address of the | |
2482 | * bottom field. | |
2483 | */ | |
aed74b55 | 2484 | if (!in_height || in_height == out_height) |
80c39712 TV |
2485 | field_offset = 0; |
2486 | else | |
aed74b55 | 2487 | field_offset = in_height / out_height / 2; |
80c39712 TV |
2488 | } |
2489 | ||
2490 | /* Fields are independent but interleaved in memory. */ | |
2491 | if (fieldmode) | |
2492 | field_offset = 1; | |
2493 | ||
c6eee968 TV |
2494 | offset0 = 0; |
2495 | offset1 = 0; | |
2496 | row_inc = 0; | |
2497 | pix_inc = 0; | |
2498 | ||
6be0d73e AT |
2499 | if (plane == OMAP_DSS_WB) { |
2500 | frame_width = out_width; | |
2501 | frame_height = out_height; | |
2502 | } else { | |
2503 | frame_width = in_width; | |
2504 | frame_height = height; | |
2505 | } | |
2506 | ||
84a880fd | 2507 | if (rotation_type == OMAP_DSS_ROT_TILER) |
6be0d73e | 2508 | calc_tiler_rotation_offset(screen_width, frame_width, |
84a880fd | 2509 | color_mode, fieldmode, field_offset, |
65e006ff CM |
2510 | &offset0, &offset1, &row_inc, &pix_inc, |
2511 | x_predecim, y_predecim); | |
84a880fd | 2512 | else if (rotation_type == OMAP_DSS_ROT_DMA) |
6be0d73e AT |
2513 | calc_dma_rotation_offset(rotation, mirror, screen_width, |
2514 | frame_width, frame_height, | |
84a880fd | 2515 | color_mode, fieldmode, field_offset, |
aed74b55 CM |
2516 | &offset0, &offset1, &row_inc, &pix_inc, |
2517 | x_predecim, y_predecim); | |
80c39712 | 2518 | else |
84a880fd | 2519 | calc_vrfb_rotation_offset(rotation, mirror, |
6be0d73e | 2520 | screen_width, frame_width, frame_height, |
84a880fd | 2521 | color_mode, fieldmode, field_offset, |
aed74b55 CM |
2522 | &offset0, &offset1, &row_inc, &pix_inc, |
2523 | x_predecim, y_predecim); | |
80c39712 TV |
2524 | |
2525 | DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", | |
2526 | offset0, offset1, row_inc, pix_inc); | |
2527 | ||
84a880fd | 2528 | dispc_ovl_set_color_mode(plane, color_mode); |
80c39712 | 2529 | |
84a880fd | 2530 | dispc_ovl_configure_burst_type(plane, rotation_type); |
65e006ff | 2531 | |
84a880fd AT |
2532 | dispc_ovl_set_ba0(plane, paddr + offset0); |
2533 | dispc_ovl_set_ba1(plane, paddr + offset1); | |
80c39712 | 2534 | |
84a880fd AT |
2535 | if (OMAP_DSS_COLOR_NV12 == color_mode) { |
2536 | dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); | |
2537 | dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); | |
0d66cbb5 AJ |
2538 | } |
2539 | ||
f0e5caab TV |
2540 | dispc_ovl_set_row_inc(plane, row_inc); |
2541 | dispc_ovl_set_pix_inc(plane, pix_inc); | |
80c39712 | 2542 | |
84a880fd | 2543 | DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, |
aed74b55 | 2544 | in_height, out_width, out_height); |
80c39712 | 2545 | |
84a880fd | 2546 | dispc_ovl_set_pos(plane, caps, pos_x, pos_y); |
80c39712 | 2547 | |
78b687fc | 2548 | dispc_ovl_set_input_size(plane, in_width, in_height); |
80c39712 | 2549 | |
5b54ed3e | 2550 | if (caps & OMAP_DSS_OVL_CAP_SCALE) { |
aed74b55 CM |
2551 | dispc_ovl_set_scaling(plane, in_width, in_height, out_width, |
2552 | out_height, ilace, five_taps, fieldmode, | |
84a880fd | 2553 | color_mode, rotation); |
78b687fc | 2554 | dispc_ovl_set_output_size(plane, out_width, out_height); |
f0e5caab | 2555 | dispc_ovl_set_vid_color_conv(plane, cconv); |
80c39712 TV |
2556 | } |
2557 | ||
c35eeb2e AT |
2558 | dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror, |
2559 | color_mode); | |
80c39712 | 2560 | |
84a880fd AT |
2561 | dispc_ovl_set_zorder(plane, caps, zorder); |
2562 | dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); | |
2563 | dispc_ovl_setup_global_alpha(plane, caps, global_alpha); | |
80c39712 | 2564 | |
d79db853 | 2565 | dispc_ovl_enable_replication(plane, caps, replication); |
c3d92529 | 2566 | |
80c39712 TV |
2567 | return 0; |
2568 | } | |
2569 | ||
84a880fd | 2570 | int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, |
8ba85306 AT |
2571 | bool replication, const struct omap_video_timings *mgr_timings, |
2572 | bool mem_to_mem) | |
84a880fd AT |
2573 | { |
2574 | int r; | |
16bf20c7 | 2575 | enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); |
84a880fd AT |
2576 | enum omap_channel channel; |
2577 | ||
2578 | channel = dispc_ovl_get_channel_out(plane); | |
2579 | ||
2580 | DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> " | |
2581 | "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n", | |
2582 | plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x, | |
2583 | oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, | |
2584 | oi->color_mode, oi->rotation, oi->mirror, channel, replication); | |
2585 | ||
16bf20c7 | 2586 | r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, |
3e8a6ff2 AT |
2587 | oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, |
2588 | oi->out_width, oi->out_height, oi->color_mode, oi->rotation, | |
2589 | oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha, | |
8ba85306 | 2590 | oi->rotation_type, replication, mgr_timings, mem_to_mem); |
84a880fd AT |
2591 | |
2592 | return r; | |
2593 | } | |
348be69d | 2594 | EXPORT_SYMBOL(dispc_ovl_setup); |
84a880fd | 2595 | |
749feffa | 2596 | int dispc_wb_setup(const struct omap_dss_writeback_info *wi, |
9e4a0fc7 | 2597 | bool mem_to_mem, const struct omap_video_timings *mgr_timings) |
749feffa AT |
2598 | { |
2599 | int r; | |
9e4a0fc7 | 2600 | u32 l; |
749feffa AT |
2601 | enum omap_plane plane = OMAP_DSS_WB; |
2602 | const int pos_x = 0, pos_y = 0; | |
2603 | const u8 zorder = 0, global_alpha = 0; | |
2604 | const bool replication = false; | |
9e4a0fc7 | 2605 | bool truncation; |
749feffa AT |
2606 | int in_width = mgr_timings->x_res; |
2607 | int in_height = mgr_timings->y_res; | |
2608 | enum omap_overlay_caps caps = | |
2609 | OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; | |
2610 | ||
2611 | DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " | |
2612 | "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width, | |
2613 | in_height, wi->width, wi->height, wi->color_mode, wi->rotation, | |
2614 | wi->mirror); | |
2615 | ||
2616 | r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr, | |
2617 | wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, | |
2618 | wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder, | |
2619 | wi->pre_mult_alpha, global_alpha, wi->rotation_type, | |
9e4a0fc7 AT |
2620 | replication, mgr_timings, mem_to_mem); |
2621 | ||
2622 | switch (wi->color_mode) { | |
2623 | case OMAP_DSS_COLOR_RGB16: | |
2624 | case OMAP_DSS_COLOR_RGB24P: | |
2625 | case OMAP_DSS_COLOR_ARGB16: | |
2626 | case OMAP_DSS_COLOR_RGBA16: | |
2627 | case OMAP_DSS_COLOR_RGB12U: | |
2628 | case OMAP_DSS_COLOR_ARGB16_1555: | |
2629 | case OMAP_DSS_COLOR_XRGB16_1555: | |
2630 | case OMAP_DSS_COLOR_RGBX16: | |
2631 | truncation = true; | |
2632 | break; | |
2633 | default: | |
2634 | truncation = false; | |
2635 | break; | |
2636 | } | |
2637 | ||
2638 | /* setup extra DISPC_WB_ATTRIBUTES */ | |
2639 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); | |
2640 | l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ | |
2641 | l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ | |
2642 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); | |
749feffa AT |
2643 | |
2644 | return r; | |
2645 | } | |
2646 | ||
f0e5caab | 2647 | int dispc_ovl_enable(enum omap_plane plane, bool enable) |
80c39712 | 2648 | { |
e6d80f95 TV |
2649 | DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); |
2650 | ||
9b372c2d | 2651 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); |
e6d80f95 TV |
2652 | |
2653 | return 0; | |
80c39712 | 2654 | } |
348be69d | 2655 | EXPORT_SYMBOL(dispc_ovl_enable); |
80c39712 | 2656 | |
04bd8ac1 TV |
2657 | bool dispc_ovl_enabled(enum omap_plane plane) |
2658 | { | |
2659 | return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); | |
2660 | } | |
348be69d | 2661 | EXPORT_SYMBOL(dispc_ovl_enabled); |
04bd8ac1 | 2662 | |
f1a813d3 | 2663 | void dispc_mgr_enable(enum omap_channel channel, bool enable) |
80c39712 | 2664 | { |
efa70b3b CM |
2665 | mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); |
2666 | /* flush posted write */ | |
2667 | mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); | |
80c39712 | 2668 | } |
348be69d | 2669 | EXPORT_SYMBOL(dispc_mgr_enable); |
80c39712 | 2670 | |
65398511 TV |
2671 | bool dispc_mgr_is_enabled(enum omap_channel channel) |
2672 | { | |
2673 | return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); | |
2674 | } | |
348be69d | 2675 | EXPORT_SYMBOL(dispc_mgr_is_enabled); |
65398511 | 2676 | |
0b23e5b8 AT |
2677 | void dispc_wb_enable(bool enable) |
2678 | { | |
916188a4 | 2679 | dispc_ovl_enable(OMAP_DSS_WB, enable); |
0b23e5b8 AT |
2680 | } |
2681 | ||
2682 | bool dispc_wb_is_enabled(void) | |
2683 | { | |
916188a4 | 2684 | return dispc_ovl_enabled(OMAP_DSS_WB); |
0b23e5b8 AT |
2685 | } |
2686 | ||
fb2cec1f | 2687 | static void dispc_lcd_enable_signal_polarity(bool act_high) |
80c39712 | 2688 | { |
6ced40bf AT |
2689 | if (!dss_has_feature(FEAT_LCDENABLEPOL)) |
2690 | return; | |
2691 | ||
80c39712 | 2692 | REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); |
80c39712 TV |
2693 | } |
2694 | ||
2695 | void dispc_lcd_enable_signal(bool enable) | |
2696 | { | |
6ced40bf AT |
2697 | if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) |
2698 | return; | |
2699 | ||
80c39712 | 2700 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); |
80c39712 TV |
2701 | } |
2702 | ||
2703 | void dispc_pck_free_enable(bool enable) | |
2704 | { | |
6ced40bf AT |
2705 | if (!dss_has_feature(FEAT_PCKFREEENABLE)) |
2706 | return; | |
2707 | ||
80c39712 | 2708 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); |
80c39712 TV |
2709 | } |
2710 | ||
fb2cec1f | 2711 | static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) |
80c39712 | 2712 | { |
efa70b3b | 2713 | mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); |
80c39712 TV |
2714 | } |
2715 | ||
2716 | ||
fb2cec1f | 2717 | static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) |
80c39712 | 2718 | { |
d21f43bc | 2719 | mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); |
80c39712 TV |
2720 | } |
2721 | ||
2722 | void dispc_set_loadmode(enum omap_dss_load_mode mode) | |
2723 | { | |
80c39712 | 2724 | REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); |
80c39712 TV |
2725 | } |
2726 | ||
2727 | ||
c64dca40 | 2728 | static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) |
80c39712 | 2729 | { |
8613b000 | 2730 | dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); |
80c39712 TV |
2731 | } |
2732 | ||
c64dca40 | 2733 | static void dispc_mgr_set_trans_key(enum omap_channel ch, |
80c39712 TV |
2734 | enum omap_dss_trans_key_type type, |
2735 | u32 trans_key) | |
2736 | { | |
efa70b3b | 2737 | mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); |
80c39712 | 2738 | |
8613b000 | 2739 | dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); |
80c39712 TV |
2740 | } |
2741 | ||
c64dca40 | 2742 | static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) |
80c39712 | 2743 | { |
efa70b3b | 2744 | mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); |
80c39712 | 2745 | } |
11354dd5 | 2746 | |
c64dca40 TV |
2747 | static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, |
2748 | bool enable) | |
80c39712 | 2749 | { |
11354dd5 | 2750 | if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) |
80c39712 TV |
2751 | return; |
2752 | ||
80c39712 TV |
2753 | if (ch == OMAP_DSS_CHANNEL_LCD) |
2754 | REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); | |
2a205f34 | 2755 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
80c39712 | 2756 | REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); |
80c39712 | 2757 | } |
11354dd5 | 2758 | |
c64dca40 | 2759 | void dispc_mgr_setup(enum omap_channel channel, |
a8f3fcd1 | 2760 | const struct omap_overlay_manager_info *info) |
c64dca40 TV |
2761 | { |
2762 | dispc_mgr_set_default_color(channel, info->default_color); | |
2763 | dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); | |
2764 | dispc_mgr_enable_trans_key(channel, info->trans_enabled); | |
2765 | dispc_mgr_enable_alpha_fixed_zorder(channel, | |
2766 | info->partial_alpha_enabled); | |
2767 | if (dss_has_feature(FEAT_CPR)) { | |
2768 | dispc_mgr_enable_cpr(channel, info->cpr_enable); | |
2769 | dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); | |
2770 | } | |
2771 | } | |
348be69d | 2772 | EXPORT_SYMBOL(dispc_mgr_setup); |
80c39712 | 2773 | |
fb2cec1f | 2774 | static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) |
80c39712 TV |
2775 | { |
2776 | int code; | |
2777 | ||
2778 | switch (data_lines) { | |
2779 | case 12: | |
2780 | code = 0; | |
2781 | break; | |
2782 | case 16: | |
2783 | code = 1; | |
2784 | break; | |
2785 | case 18: | |
2786 | code = 2; | |
2787 | break; | |
2788 | case 24: | |
2789 | code = 3; | |
2790 | break; | |
2791 | default: | |
2792 | BUG(); | |
2793 | return; | |
2794 | } | |
2795 | ||
efa70b3b | 2796 | mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); |
80c39712 TV |
2797 | } |
2798 | ||
fb2cec1f | 2799 | static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) |
80c39712 TV |
2800 | { |
2801 | u32 l; | |
569969d6 | 2802 | int gpout0, gpout1; |
80c39712 TV |
2803 | |
2804 | switch (mode) { | |
569969d6 AT |
2805 | case DSS_IO_PAD_MODE_RESET: |
2806 | gpout0 = 0; | |
2807 | gpout1 = 0; | |
80c39712 | 2808 | break; |
569969d6 AT |
2809 | case DSS_IO_PAD_MODE_RFBI: |
2810 | gpout0 = 1; | |
80c39712 TV |
2811 | gpout1 = 0; |
2812 | break; | |
569969d6 AT |
2813 | case DSS_IO_PAD_MODE_BYPASS: |
2814 | gpout0 = 1; | |
80c39712 TV |
2815 | gpout1 = 1; |
2816 | break; | |
80c39712 TV |
2817 | default: |
2818 | BUG(); | |
2819 | return; | |
2820 | } | |
2821 | ||
569969d6 AT |
2822 | l = dispc_read_reg(DISPC_CONTROL); |
2823 | l = FLD_MOD(l, gpout0, 15, 15); | |
2824 | l = FLD_MOD(l, gpout1, 16, 16); | |
2825 | dispc_write_reg(DISPC_CONTROL, l); | |
2826 | } | |
2827 | ||
fb2cec1f | 2828 | static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) |
569969d6 | 2829 | { |
efa70b3b | 2830 | mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); |
80c39712 TV |
2831 | } |
2832 | ||
fb2cec1f TV |
2833 | void dispc_mgr_set_lcd_config(enum omap_channel channel, |
2834 | const struct dss_lcd_mgr_config *config) | |
2835 | { | |
2836 | dispc_mgr_set_io_pad_mode(config->io_pad_mode); | |
2837 | ||
2838 | dispc_mgr_enable_stallmode(channel, config->stallmode); | |
2839 | dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); | |
2840 | ||
2841 | dispc_mgr_set_clock_div(channel, &config->clock_info); | |
2842 | ||
2843 | dispc_mgr_set_tft_data_lines(channel, config->video_port_width); | |
2844 | ||
2845 | dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); | |
2846 | ||
2847 | dispc_mgr_set_lcd_type_tft(channel); | |
2848 | } | |
348be69d | 2849 | EXPORT_SYMBOL(dispc_mgr_set_lcd_config); |
fb2cec1f | 2850 | |
8f366162 AT |
2851 | static bool _dispc_mgr_size_ok(u16 width, u16 height) |
2852 | { | |
33b89928 AT |
2853 | return width <= dispc.feat->mgr_width_max && |
2854 | height <= dispc.feat->mgr_height_max; | |
8f366162 AT |
2855 | } |
2856 | ||
80c39712 TV |
2857 | static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, |
2858 | int vsw, int vfp, int vbp) | |
2859 | { | |
dcbe765b CM |
2860 | if (hsw < 1 || hsw > dispc.feat->sw_max || |
2861 | hfp < 1 || hfp > dispc.feat->hp_max || | |
2862 | hbp < 1 || hbp > dispc.feat->hp_max || | |
2863 | vsw < 1 || vsw > dispc.feat->sw_max || | |
2864 | vfp < 0 || vfp > dispc.feat->vp_max || | |
2865 | vbp < 0 || vbp > dispc.feat->vp_max) | |
2866 | return false; | |
80c39712 TV |
2867 | return true; |
2868 | } | |
2869 | ||
ca5ca69c AT |
2870 | static bool _dispc_mgr_pclk_ok(enum omap_channel channel, |
2871 | unsigned long pclk) | |
2872 | { | |
2873 | if (dss_mgr_is_lcd(channel)) | |
2874 | return pclk <= dispc.feat->max_lcd_pclk ? true : false; | |
2875 | else | |
2876 | return pclk <= dispc.feat->max_tv_pclk ? true : false; | |
2877 | } | |
2878 | ||
8f366162 | 2879 | bool dispc_mgr_timings_ok(enum omap_channel channel, |
b917fa39 | 2880 | const struct omap_video_timings *timings) |
80c39712 | 2881 | { |
8f366162 AT |
2882 | bool timings_ok; |
2883 | ||
2884 | timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res); | |
2885 | ||
d8d78941 | 2886 | timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixelclock); |
ca5ca69c AT |
2887 | |
2888 | if (dss_mgr_is_lcd(channel)) { | |
2889 | timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp, | |
2890 | timings->hbp, timings->vsw, timings->vfp, | |
2891 | timings->vbp); | |
2892 | } | |
8f366162 AT |
2893 | |
2894 | return timings_ok; | |
80c39712 TV |
2895 | } |
2896 | ||
26d9dd0d | 2897 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, |
655e2941 AT |
2898 | int hfp, int hbp, int vsw, int vfp, int vbp, |
2899 | enum omap_dss_signal_level vsync_level, | |
2900 | enum omap_dss_signal_level hsync_level, | |
2901 | enum omap_dss_signal_edge data_pclk_edge, | |
2902 | enum omap_dss_signal_level de_level, | |
2903 | enum omap_dss_signal_edge sync_pclk_edge) | |
2904 | ||
80c39712 | 2905 | { |
655e2941 AT |
2906 | u32 timing_h, timing_v, l; |
2907 | bool onoff, rf, ipc; | |
80c39712 | 2908 | |
dcbe765b CM |
2909 | timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | |
2910 | FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | | |
2911 | FLD_VAL(hbp-1, dispc.feat->bp_start, 20); | |
2912 | timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | | |
2913 | FLD_VAL(vfp, dispc.feat->fp_start, 8) | | |
2914 | FLD_VAL(vbp, dispc.feat->bp_start, 20); | |
80c39712 | 2915 | |
64ba4f74 SS |
2916 | dispc_write_reg(DISPC_TIMING_H(channel), timing_h); |
2917 | dispc_write_reg(DISPC_TIMING_V(channel), timing_v); | |
655e2941 AT |
2918 | |
2919 | switch (data_pclk_edge) { | |
2920 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | |
2921 | ipc = false; | |
2922 | break; | |
2923 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: | |
2924 | ipc = true; | |
2925 | break; | |
2926 | case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES: | |
2927 | default: | |
2928 | BUG(); | |
2929 | } | |
2930 | ||
2931 | switch (sync_pclk_edge) { | |
2932 | case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES: | |
2933 | onoff = false; | |
2934 | rf = false; | |
2935 | break; | |
2936 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: | |
2937 | onoff = true; | |
2938 | rf = false; | |
2939 | break; | |
2940 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | |
2941 | onoff = true; | |
2942 | rf = true; | |
2943 | break; | |
2944 | default: | |
2945 | BUG(); | |
cf6ac4ce | 2946 | } |
655e2941 AT |
2947 | |
2948 | l = dispc_read_reg(DISPC_POL_FREQ(channel)); | |
2949 | l |= FLD_VAL(onoff, 17, 17); | |
2950 | l |= FLD_VAL(rf, 16, 16); | |
2951 | l |= FLD_VAL(de_level, 15, 15); | |
2952 | l |= FLD_VAL(ipc, 14, 14); | |
2953 | l |= FLD_VAL(hsync_level, 13, 13); | |
2954 | l |= FLD_VAL(vsync_level, 12, 12); | |
2955 | dispc_write_reg(DISPC_POL_FREQ(channel), l); | |
80c39712 TV |
2956 | } |
2957 | ||
2958 | /* change name to mode? */ | |
c51d921a | 2959 | void dispc_mgr_set_timings(enum omap_channel channel, |
a8f3fcd1 | 2960 | const struct omap_video_timings *timings) |
80c39712 TV |
2961 | { |
2962 | unsigned xtot, ytot; | |
2963 | unsigned long ht, vt; | |
2aefad49 | 2964 | struct omap_video_timings t = *timings; |
80c39712 | 2965 | |
2aefad49 | 2966 | DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res); |
80c39712 | 2967 | |
2aefad49 | 2968 | if (!dispc_mgr_timings_ok(channel, &t)) { |
8f366162 | 2969 | BUG(); |
c6eee968 TV |
2970 | return; |
2971 | } | |
80c39712 | 2972 | |
dd88b7a6 | 2973 | if (dss_mgr_is_lcd(channel)) { |
2aefad49 | 2974 | _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, |
655e2941 AT |
2975 | t.vfp, t.vbp, t.vsync_level, t.hsync_level, |
2976 | t.data_pclk_edge, t.de_level, t.sync_pclk_edge); | |
80c39712 | 2977 | |
2aefad49 AT |
2978 | xtot = t.x_res + t.hfp + t.hsw + t.hbp; |
2979 | ytot = t.y_res + t.vfp + t.vsw + t.vbp; | |
80c39712 | 2980 | |
d8d78941 TV |
2981 | ht = timings->pixelclock / xtot; |
2982 | vt = timings->pixelclock / xtot / ytot; | |
c51d921a | 2983 | |
d8d78941 | 2984 | DSSDBG("pck %u\n", timings->pixelclock); |
c51d921a | 2985 | DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", |
2aefad49 | 2986 | t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); |
655e2941 AT |
2987 | DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", |
2988 | t.vsync_level, t.hsync_level, t.data_pclk_edge, | |
2989 | t.de_level, t.sync_pclk_edge); | |
80c39712 | 2990 | |
c51d921a | 2991 | DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); |
2aefad49 | 2992 | } else { |
23c8f88e | 2993 | if (t.interlace == true) |
2aefad49 | 2994 | t.y_res /= 2; |
c51d921a | 2995 | } |
8f366162 | 2996 | |
2aefad49 | 2997 | dispc_mgr_set_size(channel, t.x_res, t.y_res); |
80c39712 | 2998 | } |
348be69d | 2999 | EXPORT_SYMBOL(dispc_mgr_set_timings); |
80c39712 | 3000 | |
26d9dd0d | 3001 | static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, |
ff1b2cde | 3002 | u16 pck_div) |
80c39712 TV |
3003 | { |
3004 | BUG_ON(lck_div < 1); | |
9eaaf207 | 3005 | BUG_ON(pck_div < 1); |
80c39712 | 3006 | |
ce7fa5eb | 3007 | dispc_write_reg(DISPC_DIVISORo(channel), |
80c39712 | 3008 | FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); |
7b3926b3 TV |
3009 | |
3010 | if (dss_has_feature(FEAT_CORE_CLK_DIV) == false && | |
3011 | channel == OMAP_DSS_CHANNEL_LCD) | |
3012 | dispc.core_clk_rate = dispc_fclk_rate() / lck_div; | |
80c39712 TV |
3013 | } |
3014 | ||
26d9dd0d | 3015 | static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, |
2a205f34 | 3016 | int *pck_div) |
80c39712 TV |
3017 | { |
3018 | u32 l; | |
ce7fa5eb | 3019 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 TV |
3020 | *lck_div = FLD_GET(l, 23, 16); |
3021 | *pck_div = FLD_GET(l, 7, 0); | |
3022 | } | |
3023 | ||
3024 | unsigned long dispc_fclk_rate(void) | |
3025 | { | |
a72b64b9 | 3026 | struct platform_device *dsidev; |
80c39712 TV |
3027 | unsigned long r = 0; |
3028 | ||
66534e8e | 3029 | switch (dss_get_dispc_clk_source()) { |
89a35e51 | 3030 | case OMAP_DSS_CLK_SRC_FCK: |
5aaee69d | 3031 | r = dss_get_dispc_clk_rate(); |
66534e8e | 3032 | break; |
89a35e51 | 3033 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
a72b64b9 AT |
3034 | dsidev = dsi_get_dsidev_from_id(0); |
3035 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
66534e8e | 3036 | break; |
5a8b572d AT |
3037 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
3038 | dsidev = dsi_get_dsidev_from_id(1); | |
3039 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
3040 | break; | |
66534e8e TA |
3041 | default: |
3042 | BUG(); | |
c6eee968 | 3043 | return 0; |
66534e8e TA |
3044 | } |
3045 | ||
80c39712 TV |
3046 | return r; |
3047 | } | |
3048 | ||
26d9dd0d | 3049 | unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) |
80c39712 | 3050 | { |
a72b64b9 | 3051 | struct platform_device *dsidev; |
80c39712 TV |
3052 | int lcd; |
3053 | unsigned long r; | |
3054 | u32 l; | |
3055 | ||
c31cba8a TV |
3056 | if (dss_mgr_is_lcd(channel)) { |
3057 | l = dispc_read_reg(DISPC_DIVISORo(channel)); | |
80c39712 | 3058 | |
c31cba8a | 3059 | lcd = FLD_GET(l, 23, 16); |
80c39712 | 3060 | |
c31cba8a TV |
3061 | switch (dss_get_lcd_clk_source(channel)) { |
3062 | case OMAP_DSS_CLK_SRC_FCK: | |
5aaee69d | 3063 | r = dss_get_dispc_clk_rate(); |
c31cba8a TV |
3064 | break; |
3065 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: | |
3066 | dsidev = dsi_get_dsidev_from_id(0); | |
3067 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
3068 | break; | |
3069 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: | |
3070 | dsidev = dsi_get_dsidev_from_id(1); | |
3071 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
3072 | break; | |
3073 | default: | |
3074 | BUG(); | |
3075 | return 0; | |
3076 | } | |
80c39712 | 3077 | |
c31cba8a TV |
3078 | return r / lcd; |
3079 | } else { | |
3080 | return dispc_fclk_rate(); | |
3081 | } | |
80c39712 TV |
3082 | } |
3083 | ||
26d9dd0d | 3084 | unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) |
80c39712 | 3085 | { |
80c39712 | 3086 | unsigned long r; |
80c39712 | 3087 | |
dd88b7a6 | 3088 | if (dss_mgr_is_lcd(channel)) { |
c3dc6a7a AT |
3089 | int pcd; |
3090 | u32 l; | |
80c39712 | 3091 | |
c3dc6a7a | 3092 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 | 3093 | |
c3dc6a7a | 3094 | pcd = FLD_GET(l, 7, 0); |
80c39712 | 3095 | |
c3dc6a7a AT |
3096 | r = dispc_mgr_lclk_rate(channel); |
3097 | ||
3098 | return r / pcd; | |
3099 | } else { | |
5391e87d | 3100 | return dispc.tv_pclk_rate; |
c3dc6a7a | 3101 | } |
80c39712 TV |
3102 | } |
3103 | ||
5391e87d TV |
3104 | void dispc_set_tv_pclk(unsigned long pclk) |
3105 | { | |
3106 | dispc.tv_pclk_rate = pclk; | |
3107 | } | |
3108 | ||
8b53d991 CM |
3109 | unsigned long dispc_core_clk_rate(void) |
3110 | { | |
7b3926b3 | 3111 | return dispc.core_clk_rate; |
8b53d991 CM |
3112 | } |
3113 | ||
3e8a6ff2 AT |
3114 | static unsigned long dispc_plane_pclk_rate(enum omap_plane plane) |
3115 | { | |
251886d8 TV |
3116 | enum omap_channel channel; |
3117 | ||
3118 | if (plane == OMAP_DSS_WB) | |
3119 | return 0; | |
3120 | ||
3121 | channel = dispc_ovl_get_channel_out(plane); | |
3e8a6ff2 AT |
3122 | |
3123 | return dispc_mgr_pclk_rate(channel); | |
3124 | } | |
3125 | ||
3126 | static unsigned long dispc_plane_lclk_rate(enum omap_plane plane) | |
3127 | { | |
251886d8 TV |
3128 | enum omap_channel channel; |
3129 | ||
3130 | if (plane == OMAP_DSS_WB) | |
3131 | return 0; | |
3132 | ||
3133 | channel = dispc_ovl_get_channel_out(plane); | |
3e8a6ff2 | 3134 | |
c31cba8a | 3135 | return dispc_mgr_lclk_rate(channel); |
3e8a6ff2 | 3136 | } |
c31cba8a | 3137 | |
6f1891fc | 3138 | static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) |
80c39712 TV |
3139 | { |
3140 | int lcd, pcd; | |
6f1891fc CM |
3141 | enum omap_dss_clk_source lcd_clk_src; |
3142 | ||
3143 | seq_printf(s, "- %s -\n", mgr_desc[channel].name); | |
3144 | ||
3145 | lcd_clk_src = dss_get_lcd_clk_source(channel); | |
3146 | ||
3147 | seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name, | |
3148 | dss_get_generic_clk_source_name(lcd_clk_src), | |
3149 | dss_feat_get_clk_source_name(lcd_clk_src)); | |
3150 | ||
3151 | dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); | |
3152 | ||
3153 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
3154 | dispc_mgr_lclk_rate(channel), lcd); | |
3155 | seq_printf(s, "pck\t\t%-16lupck div\t%u\n", | |
3156 | dispc_mgr_pclk_rate(channel), pcd); | |
3157 | } | |
3158 | ||
3159 | void dispc_dump_clocks(struct seq_file *s) | |
3160 | { | |
3161 | int lcd; | |
0cf35df3 | 3162 | u32 l; |
89a35e51 | 3163 | enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); |
80c39712 | 3164 | |
4fbafaf3 TV |
3165 | if (dispc_runtime_get()) |
3166 | return; | |
80c39712 | 3167 | |
80c39712 TV |
3168 | seq_printf(s, "- DISPC -\n"); |
3169 | ||
067a57e4 AT |
3170 | seq_printf(s, "dispc fclk source = %s (%s)\n", |
3171 | dss_get_generic_clk_source_name(dispc_clk_src), | |
3172 | dss_feat_get_clk_source_name(dispc_clk_src)); | |
80c39712 TV |
3173 | |
3174 | seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); | |
2a205f34 | 3175 | |
0cf35df3 MR |
3176 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { |
3177 | seq_printf(s, "- DISPC-CORE-CLK -\n"); | |
3178 | l = dispc_read_reg(DISPC_DIVISOR); | |
3179 | lcd = FLD_GET(l, 23, 16); | |
3180 | ||
3181 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
3182 | (dispc_fclk_rate()/lcd), lcd); | |
3183 | } | |
2a205f34 | 3184 | |
6f1891fc | 3185 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); |
ea75159e | 3186 | |
6f1891fc CM |
3187 | if (dss_has_feature(FEAT_MGR_LCD2)) |
3188 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); | |
3189 | if (dss_has_feature(FEAT_MGR_LCD3)) | |
3190 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); | |
4fbafaf3 TV |
3191 | |
3192 | dispc_runtime_put(); | |
80c39712 TV |
3193 | } |
3194 | ||
e40402cf | 3195 | static void dispc_dump_regs(struct seq_file *s) |
80c39712 | 3196 | { |
4dd2da15 AT |
3197 | int i, j; |
3198 | const char *mgr_names[] = { | |
3199 | [OMAP_DSS_CHANNEL_LCD] = "LCD", | |
3200 | [OMAP_DSS_CHANNEL_DIGIT] = "TV", | |
3201 | [OMAP_DSS_CHANNEL_LCD2] = "LCD2", | |
6f1891fc | 3202 | [OMAP_DSS_CHANNEL_LCD3] = "LCD3", |
4dd2da15 AT |
3203 | }; |
3204 | const char *ovl_names[] = { | |
3205 | [OMAP_DSS_GFX] = "GFX", | |
3206 | [OMAP_DSS_VIDEO1] = "VID1", | |
3207 | [OMAP_DSS_VIDEO2] = "VID2", | |
b8c095b4 | 3208 | [OMAP_DSS_VIDEO3] = "VID3", |
4dd2da15 AT |
3209 | }; |
3210 | const char **p_names; | |
3211 | ||
9b372c2d | 3212 | #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) |
80c39712 | 3213 | |
4fbafaf3 TV |
3214 | if (dispc_runtime_get()) |
3215 | return; | |
80c39712 | 3216 | |
5010be80 | 3217 | /* DISPC common registers */ |
80c39712 TV |
3218 | DUMPREG(DISPC_REVISION); |
3219 | DUMPREG(DISPC_SYSCONFIG); | |
3220 | DUMPREG(DISPC_SYSSTATUS); | |
3221 | DUMPREG(DISPC_IRQSTATUS); | |
3222 | DUMPREG(DISPC_IRQENABLE); | |
3223 | DUMPREG(DISPC_CONTROL); | |
3224 | DUMPREG(DISPC_CONFIG); | |
3225 | DUMPREG(DISPC_CAPABLE); | |
80c39712 TV |
3226 | DUMPREG(DISPC_LINE_STATUS); |
3227 | DUMPREG(DISPC_LINE_NUMBER); | |
11354dd5 AT |
3228 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
3229 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 3230 | DUMPREG(DISPC_GLOBAL_ALPHA); |
2a205f34 SS |
3231 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
3232 | DUMPREG(DISPC_CONTROL2); | |
3233 | DUMPREG(DISPC_CONFIG2); | |
5010be80 | 3234 | } |
6f1891fc CM |
3235 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
3236 | DUMPREG(DISPC_CONTROL3); | |
3237 | DUMPREG(DISPC_CONFIG3); | |
3238 | } | |
29fceeeb TV |
3239 | if (dss_has_feature(FEAT_MFLAG)) |
3240 | DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); | |
5010be80 AT |
3241 | |
3242 | #undef DUMPREG | |
3243 | ||
3244 | #define DISPC_REG(i, name) name(i) | |
4dd2da15 | 3245 | #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ |
311d5ce8 | 3246 | (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ |
5010be80 AT |
3247 | dispc_read_reg(DISPC_REG(i, r))) |
3248 | ||
4dd2da15 | 3249 | p_names = mgr_names; |
5010be80 | 3250 | |
4dd2da15 AT |
3251 | /* DISPC channel specific registers */ |
3252 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { | |
3253 | DUMPREG(i, DISPC_DEFAULT_COLOR); | |
3254 | DUMPREG(i, DISPC_TRANS_COLOR); | |
3255 | DUMPREG(i, DISPC_SIZE_MGR); | |
80c39712 | 3256 | |
4dd2da15 AT |
3257 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
3258 | continue; | |
5010be80 | 3259 | |
4dd2da15 AT |
3260 | DUMPREG(i, DISPC_DEFAULT_COLOR); |
3261 | DUMPREG(i, DISPC_TRANS_COLOR); | |
3262 | DUMPREG(i, DISPC_TIMING_H); | |
3263 | DUMPREG(i, DISPC_TIMING_V); | |
3264 | DUMPREG(i, DISPC_POL_FREQ); | |
3265 | DUMPREG(i, DISPC_DIVISORo); | |
3266 | DUMPREG(i, DISPC_SIZE_MGR); | |
5010be80 | 3267 | |
4dd2da15 AT |
3268 | DUMPREG(i, DISPC_DATA_CYCLE1); |
3269 | DUMPREG(i, DISPC_DATA_CYCLE2); | |
3270 | DUMPREG(i, DISPC_DATA_CYCLE3); | |
2a205f34 | 3271 | |
332e9d70 | 3272 | if (dss_has_feature(FEAT_CPR)) { |
4dd2da15 AT |
3273 | DUMPREG(i, DISPC_CPR_COEF_R); |
3274 | DUMPREG(i, DISPC_CPR_COEF_G); | |
3275 | DUMPREG(i, DISPC_CPR_COEF_B); | |
332e9d70 | 3276 | } |
2a205f34 | 3277 | } |
80c39712 | 3278 | |
4dd2da15 AT |
3279 | p_names = ovl_names; |
3280 | ||
3281 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { | |
3282 | DUMPREG(i, DISPC_OVL_BA0); | |
3283 | DUMPREG(i, DISPC_OVL_BA1); | |
3284 | DUMPREG(i, DISPC_OVL_POSITION); | |
3285 | DUMPREG(i, DISPC_OVL_SIZE); | |
3286 | DUMPREG(i, DISPC_OVL_ATTRIBUTES); | |
3287 | DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); | |
3288 | DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); | |
3289 | DUMPREG(i, DISPC_OVL_ROW_INC); | |
3290 | DUMPREG(i, DISPC_OVL_PIXEL_INC); | |
3291 | if (dss_has_feature(FEAT_PRELOAD)) | |
3292 | DUMPREG(i, DISPC_OVL_PRELOAD); | |
3293 | ||
3294 | if (i == OMAP_DSS_GFX) { | |
3295 | DUMPREG(i, DISPC_OVL_WINDOW_SKIP); | |
3296 | DUMPREG(i, DISPC_OVL_TABLE_BA); | |
3297 | continue; | |
3298 | } | |
3299 | ||
3300 | DUMPREG(i, DISPC_OVL_FIR); | |
3301 | DUMPREG(i, DISPC_OVL_PICTURE_SIZE); | |
3302 | DUMPREG(i, DISPC_OVL_ACCU0); | |
3303 | DUMPREG(i, DISPC_OVL_ACCU1); | |
3304 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3305 | DUMPREG(i, DISPC_OVL_BA0_UV); | |
3306 | DUMPREG(i, DISPC_OVL_BA1_UV); | |
3307 | DUMPREG(i, DISPC_OVL_FIR2); | |
3308 | DUMPREG(i, DISPC_OVL_ACCU2_0); | |
3309 | DUMPREG(i, DISPC_OVL_ACCU2_1); | |
3310 | } | |
3311 | if (dss_has_feature(FEAT_ATTR2)) | |
3312 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); | |
3313 | if (dss_has_feature(FEAT_PRELOAD)) | |
3314 | DUMPREG(i, DISPC_OVL_PRELOAD); | |
29fceeeb TV |
3315 | if (dss_has_feature(FEAT_MFLAG)) |
3316 | DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); | |
ab5ca071 | 3317 | } |
5010be80 AT |
3318 | |
3319 | #undef DISPC_REG | |
3320 | #undef DUMPREG | |
3321 | ||
3322 | #define DISPC_REG(plane, name, i) name(plane, i) | |
3323 | #define DUMPREG(plane, name, i) \ | |
4dd2da15 | 3324 | seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ |
311d5ce8 | 3325 | (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ |
5010be80 AT |
3326 | dispc_read_reg(DISPC_REG(plane, name, i))) |
3327 | ||
4dd2da15 | 3328 | /* Video pipeline coefficient registers */ |
332e9d70 | 3329 | |
4dd2da15 AT |
3330 | /* start from OMAP_DSS_VIDEO1 */ |
3331 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { | |
3332 | for (j = 0; j < 8; j++) | |
3333 | DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); | |
9b372c2d | 3334 | |
4dd2da15 AT |
3335 | for (j = 0; j < 8; j++) |
3336 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); | |
5010be80 | 3337 | |
4dd2da15 AT |
3338 | for (j = 0; j < 5; j++) |
3339 | DUMPREG(i, DISPC_OVL_CONV_COEF, j); | |
ab5ca071 | 3340 | |
4dd2da15 AT |
3341 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
3342 | for (j = 0; j < 8; j++) | |
3343 | DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); | |
3344 | } | |
3345 | ||
3346 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3347 | for (j = 0; j < 8; j++) | |
3348 | DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); | |
3349 | ||
3350 | for (j = 0; j < 8; j++) | |
3351 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); | |
3352 | ||
3353 | for (j = 0; j < 8; j++) | |
3354 | DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); | |
3355 | } | |
332e9d70 | 3356 | } |
80c39712 | 3357 | |
4fbafaf3 | 3358 | dispc_runtime_put(); |
5010be80 AT |
3359 | |
3360 | #undef DISPC_REG | |
80c39712 TV |
3361 | #undef DUMPREG |
3362 | } | |
3363 | ||
80c39712 TV |
3364 | /* calculate clock rates using dividers in cinfo */ |
3365 | int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, | |
80c39712 TV |
3366 | struct dispc_clock_info *cinfo) |
3367 | { | |
80c39712 TV |
3368 | if (cinfo->lck_div > 255 || cinfo->lck_div == 0) |
3369 | return -EINVAL; | |
9eaaf207 | 3370 | if (cinfo->pck_div < 1 || cinfo->pck_div > 255) |
80c39712 | 3371 | return -EINVAL; |
80c39712 | 3372 | |
80c39712 TV |
3373 | cinfo->lck = dispc_fclk_rate / cinfo->lck_div; |
3374 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
9eaaf207 | 3375 | |
80c39712 TV |
3376 | return 0; |
3377 | } | |
80c39712 | 3378 | |
7c284e6e TV |
3379 | bool dispc_div_calc(unsigned long dispc, |
3380 | unsigned long pck_min, unsigned long pck_max, | |
3381 | dispc_div_calc_func func, void *data) | |
3382 | { | |
3383 | int lckd, lckd_start, lckd_stop; | |
3384 | int pckd, pckd_start, pckd_stop; | |
3385 | unsigned long pck, lck; | |
3386 | unsigned long lck_max; | |
3387 | unsigned long pckd_hw_min, pckd_hw_max; | |
3388 | unsigned min_fck_per_pck; | |
3389 | unsigned long fck; | |
80c39712 | 3390 | |
7c284e6e TV |
3391 | #ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK |
3392 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
3393 | #else | |
3394 | min_fck_per_pck = 0; | |
3395 | #endif | |
80c39712 | 3396 | |
7c284e6e TV |
3397 | pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); |
3398 | pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); | |
80c39712 | 3399 | |
7c284e6e | 3400 | lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
80c39712 | 3401 | |
7c284e6e TV |
3402 | pck_min = pck_min ? pck_min : 1; |
3403 | pck_max = pck_max ? pck_max : ULONG_MAX; | |
80c39712 | 3404 | |
7c284e6e TV |
3405 | lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul); |
3406 | lckd_stop = min(dispc / pck_min, 255ul); | |
80c39712 | 3407 | |
7c284e6e TV |
3408 | for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) { |
3409 | lck = dispc / lckd; | |
80c39712 | 3410 | |
7c284e6e TV |
3411 | pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min); |
3412 | pckd_stop = min(lck / pck_min, pckd_hw_max); | |
80c39712 | 3413 | |
7c284e6e TV |
3414 | for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) { |
3415 | pck = lck / pckd; | |
80c39712 | 3416 | |
7c284e6e TV |
3417 | /* |
3418 | * For OMAP2/3 the DISPC fclk is the same as LCD's logic | |
3419 | * clock, which means we're configuring DISPC fclk here | |
3420 | * also. Thus we need to use the calculated lck. For | |
3421 | * OMAP4+ the DISPC fclk is a separate clock. | |
3422 | */ | |
3423 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
3424 | fck = dispc_core_clk_rate(); | |
3425 | else | |
3426 | fck = lck; | |
3427 | ||
3428 | if (fck < pck * min_fck_per_pck) | |
3429 | continue; | |
3430 | ||
3431 | if (func(lckd, pckd, lck, pck, data)) | |
3432 | return true; | |
3433 | } | |
3434 | } | |
3435 | ||
3436 | return false; | |
80c39712 TV |
3437 | } |
3438 | ||
f0d08f89 | 3439 | void dispc_mgr_set_clock_div(enum omap_channel channel, |
a8f3fcd1 | 3440 | const struct dispc_clock_info *cinfo) |
80c39712 TV |
3441 | { |
3442 | DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); | |
3443 | DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); | |
3444 | ||
26d9dd0d | 3445 | dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); |
80c39712 TV |
3446 | } |
3447 | ||
26d9dd0d | 3448 | int dispc_mgr_get_clock_div(enum omap_channel channel, |
ff1b2cde | 3449 | struct dispc_clock_info *cinfo) |
80c39712 TV |
3450 | { |
3451 | unsigned long fck; | |
3452 | ||
3453 | fck = dispc_fclk_rate(); | |
3454 | ||
ce7fa5eb MR |
3455 | cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); |
3456 | cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); | |
80c39712 TV |
3457 | |
3458 | cinfo->lck = fck / cinfo->lck_div; | |
3459 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
3460 | ||
3461 | return 0; | |
3462 | } | |
3463 | ||
4e0397cf TV |
3464 | u32 dispc_read_irqstatus(void) |
3465 | { | |
3466 | return dispc_read_reg(DISPC_IRQSTATUS); | |
3467 | } | |
348be69d | 3468 | EXPORT_SYMBOL(dispc_read_irqstatus); |
4e0397cf TV |
3469 | |
3470 | void dispc_clear_irqstatus(u32 mask) | |
3471 | { | |
3472 | dispc_write_reg(DISPC_IRQSTATUS, mask); | |
3473 | } | |
348be69d | 3474 | EXPORT_SYMBOL(dispc_clear_irqstatus); |
4e0397cf TV |
3475 | |
3476 | u32 dispc_read_irqenable(void) | |
3477 | { | |
3478 | return dispc_read_reg(DISPC_IRQENABLE); | |
3479 | } | |
348be69d | 3480 | EXPORT_SYMBOL(dispc_read_irqenable); |
4e0397cf TV |
3481 | |
3482 | void dispc_write_irqenable(u32 mask) | |
3483 | { | |
3484 | u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); | |
3485 | ||
3486 | /* clear the irqstatus for newly enabled irqs */ | |
3487 | dispc_clear_irqstatus((mask ^ old_mask) & mask); | |
3488 | ||
3489 | dispc_write_reg(DISPC_IRQENABLE, mask); | |
3490 | } | |
348be69d | 3491 | EXPORT_SYMBOL(dispc_write_irqenable); |
4e0397cf | 3492 | |
80c39712 TV |
3493 | void dispc_enable_sidle(void) |
3494 | { | |
3495 | REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ | |
3496 | } | |
3497 | ||
3498 | void dispc_disable_sidle(void) | |
3499 | { | |
3500 | REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ | |
3501 | } | |
3502 | ||
3503 | static void _omap_dispc_initial_config(void) | |
3504 | { | |
3505 | u32 l; | |
3506 | ||
0cf35df3 MR |
3507 | /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ |
3508 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { | |
3509 | l = dispc_read_reg(DISPC_DIVISOR); | |
3510 | /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ | |
3511 | l = FLD_MOD(l, 1, 0, 0); | |
3512 | l = FLD_MOD(l, 1, 23, 16); | |
3513 | dispc_write_reg(DISPC_DIVISOR, l); | |
7b3926b3 TV |
3514 | |
3515 | dispc.core_clk_rate = dispc_fclk_rate(); | |
0cf35df3 MR |
3516 | } |
3517 | ||
80c39712 | 3518 | /* FUNCGATED */ |
6ced40bf AT |
3519 | if (dss_has_feature(FEAT_FUNCGATED)) |
3520 | REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); | |
80c39712 | 3521 | |
6e5264b0 | 3522 | dispc_setup_color_conv_coef(); |
80c39712 TV |
3523 | |
3524 | dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); | |
3525 | ||
42a6961c | 3526 | dispc_init_fifos(); |
5ed8cf5b TV |
3527 | |
3528 | dispc_configure_burst_sizes(); | |
54128701 AT |
3529 | |
3530 | dispc_ovl_enable_zorder_planes(); | |
d0df9a2c AT |
3531 | |
3532 | if (dispc.feat->mstandby_workaround) | |
3533 | REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); | |
80c39712 TV |
3534 | } |
3535 | ||
dcbe765b CM |
3536 | static const struct dispc_features omap24xx_dispc_feats __initconst = { |
3537 | .sw_start = 5, | |
3538 | .fp_start = 15, | |
3539 | .bp_start = 27, | |
3540 | .sw_max = 64, | |
3541 | .vp_max = 255, | |
3542 | .hp_max = 256, | |
33b89928 AT |
3543 | .mgr_width_start = 10, |
3544 | .mgr_height_start = 26, | |
3545 | .mgr_width_max = 2048, | |
3546 | .mgr_height_max = 2048, | |
ca5ca69c | 3547 | .max_lcd_pclk = 66500000, |
dcbe765b CM |
3548 | .calc_scaling = dispc_ovl_calc_scaling_24xx, |
3549 | .calc_core_clk = calc_core_clk_24xx, | |
42a6961c | 3550 | .num_fifos = 3, |
cffa947d | 3551 | .no_framedone_tv = true, |
8bc65552 | 3552 | .set_max_preload = false, |
dcbe765b CM |
3553 | }; |
3554 | ||
3555 | static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { | |
3556 | .sw_start = 5, | |
3557 | .fp_start = 15, | |
3558 | .bp_start = 27, | |
3559 | .sw_max = 64, | |
3560 | .vp_max = 255, | |
3561 | .hp_max = 256, | |
33b89928 AT |
3562 | .mgr_width_start = 10, |
3563 | .mgr_height_start = 26, | |
3564 | .mgr_width_max = 2048, | |
3565 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3566 | .max_lcd_pclk = 173000000, |
3567 | .max_tv_pclk = 59000000, | |
dcbe765b CM |
3568 | .calc_scaling = dispc_ovl_calc_scaling_34xx, |
3569 | .calc_core_clk = calc_core_clk_34xx, | |
42a6961c | 3570 | .num_fifos = 3, |
cffa947d | 3571 | .no_framedone_tv = true, |
8bc65552 | 3572 | .set_max_preload = false, |
dcbe765b CM |
3573 | }; |
3574 | ||
3575 | static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { | |
3576 | .sw_start = 7, | |
3577 | .fp_start = 19, | |
3578 | .bp_start = 31, | |
3579 | .sw_max = 256, | |
3580 | .vp_max = 4095, | |
3581 | .hp_max = 4096, | |
33b89928 AT |
3582 | .mgr_width_start = 10, |
3583 | .mgr_height_start = 26, | |
3584 | .mgr_width_max = 2048, | |
3585 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3586 | .max_lcd_pclk = 173000000, |
3587 | .max_tv_pclk = 59000000, | |
dcbe765b CM |
3588 | .calc_scaling = dispc_ovl_calc_scaling_34xx, |
3589 | .calc_core_clk = calc_core_clk_34xx, | |
42a6961c | 3590 | .num_fifos = 3, |
cffa947d | 3591 | .no_framedone_tv = true, |
8bc65552 | 3592 | .set_max_preload = false, |
dcbe765b CM |
3593 | }; |
3594 | ||
3595 | static const struct dispc_features omap44xx_dispc_feats __initconst = { | |
3596 | .sw_start = 7, | |
3597 | .fp_start = 19, | |
3598 | .bp_start = 31, | |
3599 | .sw_max = 256, | |
3600 | .vp_max = 4095, | |
3601 | .hp_max = 4096, | |
33b89928 AT |
3602 | .mgr_width_start = 10, |
3603 | .mgr_height_start = 26, | |
3604 | .mgr_width_max = 2048, | |
3605 | .mgr_height_max = 2048, | |
ca5ca69c AT |
3606 | .max_lcd_pclk = 170000000, |
3607 | .max_tv_pclk = 185625000, | |
dcbe765b CM |
3608 | .calc_scaling = dispc_ovl_calc_scaling_44xx, |
3609 | .calc_core_clk = calc_core_clk_44xx, | |
42a6961c | 3610 | .num_fifos = 5, |
66a0f9e4 | 3611 | .gfx_fifo_workaround = true, |
8bc65552 | 3612 | .set_max_preload = true, |
dcbe765b CM |
3613 | }; |
3614 | ||
264236f8 AT |
3615 | static const struct dispc_features omap54xx_dispc_feats __initconst = { |
3616 | .sw_start = 7, | |
3617 | .fp_start = 19, | |
3618 | .bp_start = 31, | |
3619 | .sw_max = 256, | |
3620 | .vp_max = 4095, | |
3621 | .hp_max = 4096, | |
3622 | .mgr_width_start = 11, | |
3623 | .mgr_height_start = 27, | |
3624 | .mgr_width_max = 4096, | |
3625 | .mgr_height_max = 4096, | |
ca5ca69c AT |
3626 | .max_lcd_pclk = 170000000, |
3627 | .max_tv_pclk = 186000000, | |
264236f8 AT |
3628 | .calc_scaling = dispc_ovl_calc_scaling_44xx, |
3629 | .calc_core_clk = calc_core_clk_44xx, | |
3630 | .num_fifos = 5, | |
3631 | .gfx_fifo_workaround = true, | |
d0df9a2c | 3632 | .mstandby_workaround = true, |
8bc65552 | 3633 | .set_max_preload = true, |
264236f8 AT |
3634 | }; |
3635 | ||
84b47623 | 3636 | static int __init dispc_init_features(struct platform_device *pdev) |
dcbe765b CM |
3637 | { |
3638 | const struct dispc_features *src; | |
3639 | struct dispc_features *dst; | |
3640 | ||
84b47623 | 3641 | dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); |
dcbe765b | 3642 | if (!dst) { |
84b47623 | 3643 | dev_err(&pdev->dev, "Failed to allocate DISPC Features\n"); |
dcbe765b CM |
3644 | return -ENOMEM; |
3645 | } | |
3646 | ||
b2c7d54f | 3647 | switch (omapdss_get_version()) { |
84b47623 | 3648 | case OMAPDSS_VER_OMAP24xx: |
dcbe765b | 3649 | src = &omap24xx_dispc_feats; |
84b47623 TV |
3650 | break; |
3651 | ||
3652 | case OMAPDSS_VER_OMAP34xx_ES1: | |
3653 | src = &omap34xx_rev1_0_dispc_feats; | |
3654 | break; | |
3655 | ||
3656 | case OMAPDSS_VER_OMAP34xx_ES3: | |
3657 | case OMAPDSS_VER_OMAP3630: | |
3658 | case OMAPDSS_VER_AM35xx: | |
3659 | src = &omap34xx_rev3_0_dispc_feats; | |
3660 | break; | |
3661 | ||
3662 | case OMAPDSS_VER_OMAP4430_ES1: | |
3663 | case OMAPDSS_VER_OMAP4430_ES2: | |
3664 | case OMAPDSS_VER_OMAP4: | |
dcbe765b | 3665 | src = &omap44xx_dispc_feats; |
84b47623 TV |
3666 | break; |
3667 | ||
3668 | case OMAPDSS_VER_OMAP5: | |
264236f8 | 3669 | src = &omap54xx_dispc_feats; |
84b47623 TV |
3670 | break; |
3671 | ||
3672 | default: | |
dcbe765b CM |
3673 | return -ENODEV; |
3674 | } | |
3675 | ||
3676 | memcpy(dst, src, sizeof(*dst)); | |
3677 | dispc.feat = dst; | |
3678 | ||
3679 | return 0; | |
3680 | } | |
3681 | ||
0925afc9 TV |
3682 | static irqreturn_t dispc_irq_handler(int irq, void *arg) |
3683 | { | |
3684 | if (!dispc.is_enabled) | |
3685 | return IRQ_NONE; | |
3686 | ||
3687 | return dispc.user_handler(irq, dispc.user_data); | |
3688 | } | |
3689 | ||
96e2e637 TV |
3690 | int dispc_request_irq(irq_handler_t handler, void *dev_id) |
3691 | { | |
0925afc9 TV |
3692 | int r; |
3693 | ||
3694 | if (dispc.user_handler != NULL) | |
3695 | return -EBUSY; | |
3696 | ||
3697 | dispc.user_handler = handler; | |
3698 | dispc.user_data = dev_id; | |
3699 | ||
3700 | /* ensure the dispc_irq_handler sees the values above */ | |
3701 | smp_wmb(); | |
3702 | ||
3703 | r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, | |
3704 | IRQF_SHARED, "OMAP DISPC", &dispc); | |
3705 | if (r) { | |
3706 | dispc.user_handler = NULL; | |
3707 | dispc.user_data = NULL; | |
3708 | } | |
3709 | ||
3710 | return r; | |
96e2e637 | 3711 | } |
348be69d | 3712 | EXPORT_SYMBOL(dispc_request_irq); |
96e2e637 TV |
3713 | |
3714 | void dispc_free_irq(void *dev_id) | |
3715 | { | |
0925afc9 TV |
3716 | devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); |
3717 | ||
3718 | dispc.user_handler = NULL; | |
3719 | dispc.user_data = NULL; | |
96e2e637 | 3720 | } |
348be69d | 3721 | EXPORT_SYMBOL(dispc_free_irq); |
96e2e637 | 3722 | |
060b6d9c | 3723 | /* DISPC HW IP initialisation */ |
6e7e8f06 | 3724 | static int __init omap_dispchw_probe(struct platform_device *pdev) |
060b6d9c SG |
3725 | { |
3726 | u32 rev; | |
affe360d | 3727 | int r = 0; |
ea9da36a SG |
3728 | struct resource *dispc_mem; |
3729 | ||
060b6d9c SG |
3730 | dispc.pdev = pdev; |
3731 | ||
84b47623 | 3732 | r = dispc_init_features(dispc.pdev); |
dcbe765b CM |
3733 | if (r) |
3734 | return r; | |
3735 | ||
ea9da36a SG |
3736 | dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); |
3737 | if (!dispc_mem) { | |
3738 | DSSERR("can't get IORESOURCE_MEM DISPC\n"); | |
cd3b3449 | 3739 | return -EINVAL; |
ea9da36a | 3740 | } |
cd3b3449 | 3741 | |
6e2a14d2 JL |
3742 | dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, |
3743 | resource_size(dispc_mem)); | |
060b6d9c SG |
3744 | if (!dispc.base) { |
3745 | DSSERR("can't ioremap DISPC\n"); | |
cd3b3449 | 3746 | return -ENOMEM; |
affe360d | 3747 | } |
cd3b3449 | 3748 | |
affe360d | 3749 | dispc.irq = platform_get_irq(dispc.pdev, 0); |
3750 | if (dispc.irq < 0) { | |
3751 | DSSERR("platform_get_irq failed\n"); | |
cd3b3449 | 3752 | return -ENODEV; |
affe360d | 3753 | } |
3754 | ||
4fbafaf3 TV |
3755 | pm_runtime_enable(&pdev->dev); |
3756 | ||
3757 | r = dispc_runtime_get(); | |
3758 | if (r) | |
3759 | goto err_runtime_get; | |
060b6d9c SG |
3760 | |
3761 | _omap_dispc_initial_config(); | |
3762 | ||
060b6d9c | 3763 | rev = dispc_read_reg(DISPC_REVISION); |
a06b62f8 | 3764 | dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", |
060b6d9c SG |
3765 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
3766 | ||
4fbafaf3 | 3767 | dispc_runtime_put(); |
060b6d9c | 3768 | |
04b1fc02 TV |
3769 | dss_init_overlay_managers(); |
3770 | ||
e40402cf TV |
3771 | dss_debugfs_create_file("dispc", dispc_dump_regs); |
3772 | ||
060b6d9c | 3773 | return 0; |
4fbafaf3 TV |
3774 | |
3775 | err_runtime_get: | |
3776 | pm_runtime_disable(&pdev->dev); | |
affe360d | 3777 | return r; |
060b6d9c SG |
3778 | } |
3779 | ||
6e7e8f06 | 3780 | static int __exit omap_dispchw_remove(struct platform_device *pdev) |
060b6d9c | 3781 | { |
4fbafaf3 TV |
3782 | pm_runtime_disable(&pdev->dev); |
3783 | ||
04b1fc02 TV |
3784 | dss_uninit_overlay_managers(); |
3785 | ||
060b6d9c SG |
3786 | return 0; |
3787 | } | |
3788 | ||
4fbafaf3 TV |
3789 | static int dispc_runtime_suspend(struct device *dev) |
3790 | { | |
0925afc9 TV |
3791 | dispc.is_enabled = false; |
3792 | /* ensure the dispc_irq_handler sees the is_enabled value */ | |
3793 | smp_wmb(); | |
3794 | /* wait for current handler to finish before turning the DISPC off */ | |
3795 | synchronize_irq(dispc.irq); | |
3796 | ||
4fbafaf3 | 3797 | dispc_save_context(); |
4fbafaf3 TV |
3798 | |
3799 | return 0; | |
3800 | } | |
3801 | ||
3802 | static int dispc_runtime_resume(struct device *dev) | |
3803 | { | |
9229b516 TV |
3804 | /* |
3805 | * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) | |
3806 | * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in | |
3807 | * _omap_dispc_initial_config(). We can thus use it to detect if | |
3808 | * we have lost register context. | |
3809 | */ | |
0925afc9 TV |
3810 | if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { |
3811 | _omap_dispc_initial_config(); | |
9229b516 | 3812 | |
0925afc9 TV |
3813 | dispc_restore_context(); |
3814 | } | |
be07dcd7 | 3815 | |
0925afc9 TV |
3816 | dispc.is_enabled = true; |
3817 | /* ensure the dispc_irq_handler sees the is_enabled value */ | |
3818 | smp_wmb(); | |
4fbafaf3 TV |
3819 | |
3820 | return 0; | |
3821 | } | |
3822 | ||
3823 | static const struct dev_pm_ops dispc_pm_ops = { | |
3824 | .runtime_suspend = dispc_runtime_suspend, | |
3825 | .runtime_resume = dispc_runtime_resume, | |
3826 | }; | |
3827 | ||
d7977f88 TV |
3828 | static const struct of_device_id dispc_of_match[] = { |
3829 | { .compatible = "ti,omap2-dispc", }, | |
3830 | { .compatible = "ti,omap3-dispc", }, | |
3831 | { .compatible = "ti,omap4-dispc", }, | |
3832 | {}, | |
3833 | }; | |
3834 | ||
060b6d9c | 3835 | static struct platform_driver omap_dispchw_driver = { |
6e7e8f06 | 3836 | .remove = __exit_p(omap_dispchw_remove), |
060b6d9c SG |
3837 | .driver = { |
3838 | .name = "omapdss_dispc", | |
3839 | .owner = THIS_MODULE, | |
4fbafaf3 | 3840 | .pm = &dispc_pm_ops, |
d7977f88 | 3841 | .of_match_table = dispc_of_match, |
060b6d9c SG |
3842 | }, |
3843 | }; | |
3844 | ||
6e7e8f06 | 3845 | int __init dispc_init_platform_driver(void) |
060b6d9c | 3846 | { |
11436e1d | 3847 | return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe); |
060b6d9c SG |
3848 | } |
3849 | ||
6e7e8f06 | 3850 | void __exit dispc_uninit_platform_driver(void) |
060b6d9c | 3851 | { |
04c742c3 | 3852 | platform_driver_unregister(&omap_dispchw_driver); |
060b6d9c | 3853 | } |