Commit | Line | Data |
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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dss.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DSS" | |
24 | ||
25 | #include <linux/kernel.h> | |
2ecef246 | 26 | #include <linux/module.h> |
559d6701 | 27 | #include <linux/io.h> |
a8a35931 | 28 | #include <linux/export.h> |
559d6701 TV |
29 | #include <linux/err.h> |
30 | #include <linux/delay.h> | |
559d6701 TV |
31 | #include <linux/seq_file.h> |
32 | #include <linux/clk.h> | |
24e6289c | 33 | #include <linux/platform_device.h> |
4fbafaf3 | 34 | #include <linux/pm_runtime.h> |
185bae10 | 35 | #include <linux/gfp.h> |
33366d0e | 36 | #include <linux/sizes.h> |
be40eecf TV |
37 | #include <linux/mfd/syscon.h> |
38 | #include <linux/regmap.h> | |
2ecef246 | 39 | #include <linux/of.h> |
99767548 | 40 | #include <linux/regulator/consumer.h> |
cb17a4ae | 41 | #include <linux/suspend.h> |
559d6701 | 42 | |
a0b38cc4 | 43 | #include <video/omapdss.h> |
2c799cef | 44 | |
559d6701 | 45 | #include "dss.h" |
6ec549e5 | 46 | #include "dss_features.h" |
559d6701 | 47 | |
559d6701 TV |
48 | #define DSS_SZ_REGS SZ_512 |
49 | ||
50 | struct dss_reg { | |
51 | u16 idx; | |
52 | }; | |
53 | ||
54 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) | |
55 | ||
56 | #define DSS_REVISION DSS_REG(0x0000) | |
57 | #define DSS_SYSCONFIG DSS_REG(0x0010) | |
58 | #define DSS_SYSSTATUS DSS_REG(0x0014) | |
559d6701 TV |
59 | #define DSS_CONTROL DSS_REG(0x0040) |
60 | #define DSS_SDI_CONTROL DSS_REG(0x0044) | |
61 | #define DSS_PLL_CONTROL DSS_REG(0x0048) | |
62 | #define DSS_SDI_STATUS DSS_REG(0x005C) | |
63 | ||
64 | #define REG_GET(idx, start, end) \ | |
65 | FLD_GET(dss_read_reg(idx), start, end) | |
66 | ||
67 | #define REG_FLD_MOD(idx, val, start, end) \ | |
68 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) | |
69 | ||
185bae10 CM |
70 | struct dss_features { |
71 | u8 fck_div_max; | |
72 | u8 dss_fck_multiplier; | |
64ad846f | 73 | const char *parent_clk_name; |
234f9a22 | 74 | const enum omap_display_type *ports; |
387ce9f2 | 75 | int num_ports; |
064c2a47 | 76 | int (*dpi_select_source)(int port, enum omap_channel channel); |
185bae10 CM |
77 | }; |
78 | ||
559d6701 | 79 | static struct { |
96c401bc | 80 | struct platform_device *pdev; |
559d6701 | 81 | void __iomem *base; |
be40eecf TV |
82 | struct regmap *syscon_pll_ctrl; |
83 | u32 syscon_pll_ctrl_offset; | |
4fbafaf3 | 84 | |
64ad846f | 85 | struct clk *parent_clk; |
4fbafaf3 | 86 | struct clk *dss_clk; |
5aaee69d | 87 | unsigned long dss_clk_rate; |
559d6701 TV |
88 | |
89 | unsigned long cache_req_pck; | |
90 | unsigned long cache_prate; | |
559d6701 TV |
91 | struct dispc_clock_info cache_dispc_cinfo; |
92 | ||
5a8b572d | 93 | enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; |
89a35e51 AT |
94 | enum omap_dss_clk_source dispc_clk_source; |
95 | enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; | |
2f18c4d8 | 96 | |
69f06054 | 97 | bool ctx_valid; |
559d6701 | 98 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
185bae10 CM |
99 | |
100 | const struct dss_features *feat; | |
99767548 TV |
101 | |
102 | struct dss_pll *video1_pll; | |
103 | struct dss_pll *video2_pll; | |
559d6701 TV |
104 | } dss; |
105 | ||
235e7dba | 106 | static const char * const dss_generic_clk_source_names[] = { |
89a35e51 AT |
107 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", |
108 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", | |
109 | [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", | |
901e5fe5 TV |
110 | [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC", |
111 | [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DSI_PLL2_HSDIV_DSI", | |
067a57e4 AT |
112 | }; |
113 | ||
f99467b3 TV |
114 | static bool dss_initialized; |
115 | ||
116 | bool omapdss_is_initialized(void) | |
117 | { | |
118 | return dss_initialized; | |
119 | } | |
120 | EXPORT_SYMBOL(omapdss_is_initialized); | |
121 | ||
559d6701 TV |
122 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) |
123 | { | |
124 | __raw_writel(val, dss.base + idx.idx); | |
125 | } | |
126 | ||
127 | static inline u32 dss_read_reg(const struct dss_reg idx) | |
128 | { | |
129 | return __raw_readl(dss.base + idx.idx); | |
130 | } | |
131 | ||
132 | #define SR(reg) \ | |
133 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) | |
134 | #define RR(reg) \ | |
135 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) | |
136 | ||
4fbafaf3 | 137 | static void dss_save_context(void) |
559d6701 | 138 | { |
4fbafaf3 | 139 | DSSDBG("dss_save_context\n"); |
559d6701 | 140 | |
559d6701 TV |
141 | SR(CONTROL); |
142 | ||
6ec549e5 TV |
143 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
144 | OMAP_DISPLAY_TYPE_SDI) { | |
145 | SR(SDI_CONTROL); | |
146 | SR(PLL_CONTROL); | |
147 | } | |
69f06054 TV |
148 | |
149 | dss.ctx_valid = true; | |
150 | ||
151 | DSSDBG("context saved\n"); | |
559d6701 TV |
152 | } |
153 | ||
4fbafaf3 | 154 | static void dss_restore_context(void) |
559d6701 | 155 | { |
4fbafaf3 | 156 | DSSDBG("dss_restore_context\n"); |
559d6701 | 157 | |
69f06054 TV |
158 | if (!dss.ctx_valid) |
159 | return; | |
160 | ||
559d6701 TV |
161 | RR(CONTROL); |
162 | ||
6ec549e5 TV |
163 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
164 | OMAP_DISPLAY_TYPE_SDI) { | |
165 | RR(SDI_CONTROL); | |
166 | RR(PLL_CONTROL); | |
167 | } | |
69f06054 TV |
168 | |
169 | DSSDBG("context restored\n"); | |
559d6701 TV |
170 | } |
171 | ||
172 | #undef SR | |
173 | #undef RR | |
174 | ||
be40eecf TV |
175 | void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable) |
176 | { | |
177 | unsigned shift; | |
178 | unsigned val; | |
179 | ||
180 | if (!dss.syscon_pll_ctrl) | |
181 | return; | |
182 | ||
183 | val = !enable; | |
184 | ||
185 | switch (pll_id) { | |
186 | case DSS_PLL_VIDEO1: | |
187 | shift = 0; | |
188 | break; | |
189 | case DSS_PLL_VIDEO2: | |
190 | shift = 1; | |
191 | break; | |
192 | case DSS_PLL_HDMI: | |
193 | shift = 2; | |
194 | break; | |
195 | default: | |
196 | DSSERR("illegal DSS PLL ID %d\n", pll_id); | |
197 | return; | |
198 | } | |
199 | ||
200 | regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, | |
201 | 1 << shift, val << shift); | |
202 | } | |
203 | ||
204 | void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id, | |
205 | enum omap_channel channel) | |
206 | { | |
207 | unsigned shift, val; | |
208 | ||
209 | if (!dss.syscon_pll_ctrl) | |
210 | return; | |
211 | ||
212 | switch (channel) { | |
213 | case OMAP_DSS_CHANNEL_LCD: | |
214 | shift = 3; | |
215 | ||
216 | switch (pll_id) { | |
217 | case DSS_PLL_VIDEO1: | |
218 | val = 0; break; | |
219 | case DSS_PLL_HDMI: | |
220 | val = 1; break; | |
221 | default: | |
222 | DSSERR("error in PLL mux config for LCD\n"); | |
223 | return; | |
224 | } | |
225 | ||
226 | break; | |
227 | case OMAP_DSS_CHANNEL_LCD2: | |
228 | shift = 5; | |
229 | ||
230 | switch (pll_id) { | |
231 | case DSS_PLL_VIDEO1: | |
232 | val = 0; break; | |
233 | case DSS_PLL_VIDEO2: | |
234 | val = 1; break; | |
235 | case DSS_PLL_HDMI: | |
236 | val = 2; break; | |
237 | default: | |
238 | DSSERR("error in PLL mux config for LCD2\n"); | |
239 | return; | |
240 | } | |
241 | ||
242 | break; | |
243 | case OMAP_DSS_CHANNEL_LCD3: | |
244 | shift = 7; | |
245 | ||
246 | switch (pll_id) { | |
247 | case DSS_PLL_VIDEO1: | |
248 | val = 1; break; | |
249 | case DSS_PLL_VIDEO2: | |
250 | val = 0; break; | |
251 | case DSS_PLL_HDMI: | |
252 | val = 2; break; | |
253 | default: | |
254 | DSSERR("error in PLL mux config for LCD3\n"); | |
255 | return; | |
256 | } | |
257 | ||
258 | break; | |
259 | default: | |
260 | DSSERR("error in PLL mux config\n"); | |
261 | return; | |
262 | } | |
263 | ||
264 | regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, | |
265 | 0x3 << shift, val << shift); | |
266 | } | |
267 | ||
889b4fd7 | 268 | void dss_sdi_init(int datapairs) |
559d6701 TV |
269 | { |
270 | u32 l; | |
271 | ||
272 | BUG_ON(datapairs > 3 || datapairs < 1); | |
273 | ||
274 | l = dss_read_reg(DSS_SDI_CONTROL); | |
275 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ | |
276 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ | |
277 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ | |
278 | dss_write_reg(DSS_SDI_CONTROL, l); | |
279 | ||
280 | l = dss_read_reg(DSS_PLL_CONTROL); | |
281 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ | |
282 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ | |
283 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ | |
284 | dss_write_reg(DSS_PLL_CONTROL, l); | |
285 | } | |
286 | ||
287 | int dss_sdi_enable(void) | |
288 | { | |
289 | unsigned long timeout; | |
290 | ||
291 | dispc_pck_free_enable(1); | |
292 | ||
293 | /* Reset SDI PLL */ | |
294 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ | |
295 | udelay(1); /* wait 2x PCLK */ | |
296 | ||
297 | /* Lock SDI PLL */ | |
298 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ | |
299 | ||
300 | /* Waiting for PLL lock request to complete */ | |
301 | timeout = jiffies + msecs_to_jiffies(500); | |
302 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { | |
303 | if (time_after_eq(jiffies, timeout)) { | |
304 | DSSERR("PLL lock request timed out\n"); | |
305 | goto err1; | |
306 | } | |
307 | } | |
308 | ||
309 | /* Clearing PLL_GO bit */ | |
310 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); | |
311 | ||
312 | /* Waiting for PLL to lock */ | |
313 | timeout = jiffies + msecs_to_jiffies(500); | |
314 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { | |
315 | if (time_after_eq(jiffies, timeout)) { | |
316 | DSSERR("PLL lock timed out\n"); | |
317 | goto err1; | |
318 | } | |
319 | } | |
320 | ||
321 | dispc_lcd_enable_signal(1); | |
322 | ||
323 | /* Waiting for SDI reset to complete */ | |
324 | timeout = jiffies + msecs_to_jiffies(500); | |
325 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { | |
326 | if (time_after_eq(jiffies, timeout)) { | |
327 | DSSERR("SDI reset timed out\n"); | |
328 | goto err2; | |
329 | } | |
330 | } | |
331 | ||
332 | return 0; | |
333 | ||
334 | err2: | |
335 | dispc_lcd_enable_signal(0); | |
336 | err1: | |
337 | /* Reset SDI PLL */ | |
338 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
339 | ||
340 | dispc_pck_free_enable(0); | |
341 | ||
342 | return -ETIMEDOUT; | |
343 | } | |
344 | ||
345 | void dss_sdi_disable(void) | |
346 | { | |
347 | dispc_lcd_enable_signal(0); | |
348 | ||
349 | dispc_pck_free_enable(0); | |
350 | ||
351 | /* Reset SDI PLL */ | |
352 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
353 | } | |
354 | ||
89a35e51 | 355 | const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) |
067a57e4 | 356 | { |
235e7dba | 357 | return dss_generic_clk_source_names[clk_src]; |
067a57e4 AT |
358 | } |
359 | ||
559d6701 TV |
360 | void dss_dump_clocks(struct seq_file *s) |
361 | { | |
0acf659f TV |
362 | const char *fclk_name, *fclk_real_name; |
363 | unsigned long fclk_rate; | |
559d6701 | 364 | |
4fbafaf3 TV |
365 | if (dss_runtime_get()) |
366 | return; | |
559d6701 | 367 | |
559d6701 TV |
368 | seq_printf(s, "- DSS -\n"); |
369 | ||
89a35e51 AT |
370 | fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
371 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); | |
4fbafaf3 | 372 | fclk_rate = clk_get_rate(dss.dss_clk); |
559d6701 | 373 | |
9c15d762 TV |
374 | seq_printf(s, "%s (%s) = %lu\n", |
375 | fclk_name, fclk_real_name, | |
376 | fclk_rate); | |
559d6701 | 377 | |
4fbafaf3 | 378 | dss_runtime_put(); |
559d6701 TV |
379 | } |
380 | ||
e40402cf | 381 | static void dss_dump_regs(struct seq_file *s) |
559d6701 TV |
382 | { |
383 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) | |
384 | ||
4fbafaf3 TV |
385 | if (dss_runtime_get()) |
386 | return; | |
559d6701 TV |
387 | |
388 | DUMPREG(DSS_REVISION); | |
389 | DUMPREG(DSS_SYSCONFIG); | |
390 | DUMPREG(DSS_SYSSTATUS); | |
559d6701 | 391 | DUMPREG(DSS_CONTROL); |
6ec549e5 TV |
392 | |
393 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & | |
394 | OMAP_DISPLAY_TYPE_SDI) { | |
395 | DUMPREG(DSS_SDI_CONTROL); | |
396 | DUMPREG(DSS_PLL_CONTROL); | |
397 | DUMPREG(DSS_SDI_STATUS); | |
398 | } | |
559d6701 | 399 | |
4fbafaf3 | 400 | dss_runtime_put(); |
559d6701 TV |
401 | #undef DUMPREG |
402 | } | |
403 | ||
a5b8399f | 404 | static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src) |
2f18c4d8 TV |
405 | { |
406 | int b; | |
ea75159e | 407 | u8 start, end; |
2f18c4d8 | 408 | |
66534e8e | 409 | switch (clk_src) { |
89a35e51 | 410 | case OMAP_DSS_CLK_SRC_FCK: |
66534e8e TA |
411 | b = 0; |
412 | break; | |
89a35e51 | 413 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
66534e8e | 414 | b = 1; |
66534e8e | 415 | break; |
5a8b572d AT |
416 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
417 | b = 2; | |
5a8b572d | 418 | break; |
66534e8e TA |
419 | default: |
420 | BUG(); | |
c6eee968 | 421 | return; |
66534e8e | 422 | } |
e406f907 | 423 | |
ea75159e TA |
424 | dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); |
425 | ||
426 | REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ | |
2f18c4d8 TV |
427 | |
428 | dss.dispc_clk_source = clk_src; | |
429 | } | |
430 | ||
5a8b572d AT |
431 | void dss_select_dsi_clk_source(int dsi_module, |
432 | enum omap_dss_clk_source clk_src) | |
559d6701 | 433 | { |
a2e5d827 | 434 | int b, pos; |
2f18c4d8 | 435 | |
66534e8e | 436 | switch (clk_src) { |
89a35e51 | 437 | case OMAP_DSS_CLK_SRC_FCK: |
66534e8e TA |
438 | b = 0; |
439 | break; | |
89a35e51 | 440 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: |
5a8b572d | 441 | BUG_ON(dsi_module != 0); |
66534e8e | 442 | b = 1; |
66534e8e | 443 | break; |
5a8b572d AT |
444 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI: |
445 | BUG_ON(dsi_module != 1); | |
446 | b = 1; | |
5a8b572d | 447 | break; |
66534e8e TA |
448 | default: |
449 | BUG(); | |
c6eee968 | 450 | return; |
66534e8e | 451 | } |
e406f907 | 452 | |
a2e5d827 AT |
453 | pos = dsi_module == 0 ? 1 : 10; |
454 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ | |
2f18c4d8 | 455 | |
5a8b572d | 456 | dss.dsi_clk_source[dsi_module] = clk_src; |
559d6701 TV |
457 | } |
458 | ||
ea75159e | 459 | void dss_select_lcd_clk_source(enum omap_channel channel, |
89a35e51 | 460 | enum omap_dss_clk_source clk_src) |
ea75159e TA |
461 | { |
462 | int b, ix, pos; | |
463 | ||
a5b8399f TV |
464 | if (!dss_has_feature(FEAT_LCD_CLK_SRC)) { |
465 | dss_select_dispc_clk_source(clk_src); | |
ea75159e | 466 | return; |
a5b8399f | 467 | } |
ea75159e TA |
468 | |
469 | switch (clk_src) { | |
89a35e51 | 470 | case OMAP_DSS_CLK_SRC_FCK: |
ea75159e TA |
471 | b = 0; |
472 | break; | |
89a35e51 | 473 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
ea75159e TA |
474 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); |
475 | b = 1; | |
ea75159e | 476 | break; |
5a8b572d | 477 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
e86d456a CM |
478 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 && |
479 | channel != OMAP_DSS_CHANNEL_LCD3); | |
5a8b572d | 480 | b = 1; |
5a8b572d | 481 | break; |
ea75159e TA |
482 | default: |
483 | BUG(); | |
c6eee968 | 484 | return; |
ea75159e TA |
485 | } |
486 | ||
e86d456a CM |
487 | pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : |
488 | (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19); | |
ea75159e TA |
489 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ |
490 | ||
e86d456a CM |
491 | ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : |
492 | (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2); | |
ea75159e TA |
493 | dss.lcd_clk_source[ix] = clk_src; |
494 | } | |
495 | ||
89a35e51 | 496 | enum omap_dss_clk_source dss_get_dispc_clk_source(void) |
559d6701 | 497 | { |
2f18c4d8 | 498 | return dss.dispc_clk_source; |
559d6701 TV |
499 | } |
500 | ||
5a8b572d | 501 | enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module) |
559d6701 | 502 | { |
5a8b572d | 503 | return dss.dsi_clk_source[dsi_module]; |
559d6701 TV |
504 | } |
505 | ||
89a35e51 | 506 | enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) |
ea75159e | 507 | { |
89976f29 | 508 | if (dss_has_feature(FEAT_LCD_CLK_SRC)) { |
e86d456a CM |
509 | int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : |
510 | (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2); | |
89976f29 AT |
511 | return dss.lcd_clk_source[ix]; |
512 | } else { | |
513 | /* LCD_CLK source is the same as DISPC_FCLK source for | |
514 | * OMAP2 and OMAP3 */ | |
515 | return dss.dispc_clk_source; | |
516 | } | |
ea75159e TA |
517 | } |
518 | ||
688af02d TV |
519 | bool dss_div_calc(unsigned long pck, unsigned long fck_min, |
520 | dss_div_calc_func func, void *data) | |
43417823 TV |
521 | { |
522 | int fckd, fckd_start, fckd_stop; | |
523 | unsigned long fck; | |
524 | unsigned long fck_hw_max; | |
525 | unsigned long fckd_hw_max; | |
526 | unsigned long prate; | |
648a55e1 | 527 | unsigned m; |
43417823 | 528 | |
fc1fe6e7 TV |
529 | fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
530 | ||
64ad846f | 531 | if (dss.parent_clk == NULL) { |
fc1fe6e7 TV |
532 | unsigned pckd; |
533 | ||
534 | pckd = fck_hw_max / pck; | |
535 | ||
536 | fck = pck * pckd; | |
537 | ||
538 | fck = clk_round_rate(dss.dss_clk, fck); | |
539 | ||
d0f58bd3 | 540 | return func(fck, data); |
43417823 TV |
541 | } |
542 | ||
43417823 TV |
543 | fckd_hw_max = dss.feat->fck_div_max; |
544 | ||
648a55e1 | 545 | m = dss.feat->dss_fck_multiplier; |
ada9443f | 546 | prate = clk_get_rate(dss.parent_clk); |
43417823 TV |
547 | |
548 | fck_min = fck_min ? fck_min : 1; | |
549 | ||
648a55e1 TV |
550 | fckd_start = min(prate * m / fck_min, fckd_hw_max); |
551 | fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul); | |
43417823 TV |
552 | |
553 | for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { | |
d0e224f9 | 554 | fck = DIV_ROUND_UP(prate, fckd) * m; |
43417823 | 555 | |
d0f58bd3 | 556 | if (func(fck, data)) |
43417823 TV |
557 | return true; |
558 | } | |
559 | ||
560 | return false; | |
561 | } | |
562 | ||
d0f58bd3 | 563 | int dss_set_fck_rate(unsigned long rate) |
559d6701 | 564 | { |
ada9443f | 565 | int r; |
559d6701 | 566 | |
ada9443f | 567 | DSSDBG("set fck to %lu\n", rate); |
559d6701 | 568 | |
ada9443f TV |
569 | r = clk_set_rate(dss.dss_clk, rate); |
570 | if (r) | |
571 | return r; | |
559d6701 | 572 | |
5aaee69d TV |
573 | dss.dss_clk_rate = clk_get_rate(dss.dss_clk); |
574 | ||
d0f58bd3 | 575 | WARN_ONCE(dss.dss_clk_rate != rate, |
648a55e1 | 576 | "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, |
d0f58bd3 | 577 | rate); |
559d6701 TV |
578 | |
579 | return 0; | |
580 | } | |
581 | ||
5aaee69d TV |
582 | unsigned long dss_get_dispc_clk_rate(void) |
583 | { | |
584 | return dss.dss_clk_rate; | |
585 | } | |
586 | ||
13a1a2b2 TV |
587 | static int dss_setup_default_clock(void) |
588 | { | |
589 | unsigned long max_dss_fck, prate; | |
d0f58bd3 | 590 | unsigned long fck; |
13a1a2b2 | 591 | unsigned fck_div; |
13a1a2b2 TV |
592 | int r; |
593 | ||
13a1a2b2 TV |
594 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
595 | ||
fc1fe6e7 TV |
596 | if (dss.parent_clk == NULL) { |
597 | fck = clk_round_rate(dss.dss_clk, max_dss_fck); | |
598 | } else { | |
599 | prate = clk_get_rate(dss.parent_clk); | |
13a1a2b2 | 600 | |
fc1fe6e7 TV |
601 | fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, |
602 | max_dss_fck); | |
d0e224f9 | 603 | fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; |
fc1fe6e7 | 604 | } |
13a1a2b2 | 605 | |
d0f58bd3 | 606 | r = dss_set_fck_rate(fck); |
13a1a2b2 TV |
607 | if (r) |
608 | return r; | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
559d6701 TV |
613 | void dss_set_venc_output(enum omap_dss_venc_type type) |
614 | { | |
615 | int l = 0; | |
616 | ||
617 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) | |
618 | l = 0; | |
619 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) | |
620 | l = 1; | |
621 | else | |
622 | BUG(); | |
623 | ||
624 | /* venc out selection. 0 = comp, 1 = svideo */ | |
625 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); | |
626 | } | |
627 | ||
628 | void dss_set_dac_pwrdn_bgz(bool enable) | |
629 | { | |
630 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ | |
631 | } | |
632 | ||
8aa2eed1 | 633 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) |
7ed024aa | 634 | { |
8aa2eed1 RN |
635 | enum omap_display_type dp; |
636 | dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); | |
637 | ||
638 | /* Complain about invalid selections */ | |
639 | WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC)); | |
640 | WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI)); | |
641 | ||
642 | /* Select only if we have options */ | |
643 | if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI)) | |
644 | REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ | |
7ed024aa M |
645 | } |
646 | ||
4a61e267 TV |
647 | enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void) |
648 | { | |
649 | enum omap_display_type displays; | |
650 | ||
651 | displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT); | |
652 | if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0) | |
653 | return DSS_VENC_TV_CLK; | |
654 | ||
8aa2eed1 RN |
655 | if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0) |
656 | return DSS_HDMI_M_PCLK; | |
657 | ||
4a61e267 TV |
658 | return REG_GET(DSS_CONTROL, 15, 15); |
659 | } | |
660 | ||
064c2a47 | 661 | static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel) |
de09e455 TV |
662 | { |
663 | if (channel != OMAP_DSS_CHANNEL_LCD) | |
664 | return -EINVAL; | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
064c2a47 | 669 | static int dss_dpi_select_source_omap4(int port, enum omap_channel channel) |
de09e455 TV |
670 | { |
671 | int val; | |
672 | ||
673 | switch (channel) { | |
674 | case OMAP_DSS_CHANNEL_LCD2: | |
675 | val = 0; | |
676 | break; | |
677 | case OMAP_DSS_CHANNEL_DIGIT: | |
678 | val = 1; | |
679 | break; | |
680 | default: | |
681 | return -EINVAL; | |
682 | } | |
683 | ||
684 | REG_FLD_MOD(DSS_CONTROL, val, 17, 17); | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
064c2a47 | 689 | static int dss_dpi_select_source_omap5(int port, enum omap_channel channel) |
de09e455 TV |
690 | { |
691 | int val; | |
692 | ||
693 | switch (channel) { | |
694 | case OMAP_DSS_CHANNEL_LCD: | |
695 | val = 1; | |
696 | break; | |
697 | case OMAP_DSS_CHANNEL_LCD2: | |
698 | val = 2; | |
699 | break; | |
700 | case OMAP_DSS_CHANNEL_LCD3: | |
701 | val = 3; | |
702 | break; | |
703 | case OMAP_DSS_CHANNEL_DIGIT: | |
704 | val = 0; | |
705 | break; | |
706 | default: | |
707 | return -EINVAL; | |
708 | } | |
709 | ||
710 | REG_FLD_MOD(DSS_CONTROL, val, 17, 16); | |
711 | ||
712 | return 0; | |
713 | } | |
714 | ||
6d817880 TV |
715 | static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel) |
716 | { | |
717 | switch (port) { | |
718 | case 0: | |
719 | return dss_dpi_select_source_omap5(port, channel); | |
720 | case 1: | |
721 | if (channel != OMAP_DSS_CHANNEL_LCD2) | |
722 | return -EINVAL; | |
723 | break; | |
724 | case 2: | |
725 | if (channel != OMAP_DSS_CHANNEL_LCD3) | |
726 | return -EINVAL; | |
727 | break; | |
728 | default: | |
729 | return -EINVAL; | |
730 | } | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
064c2a47 | 735 | int dss_dpi_select_source(int port, enum omap_channel channel) |
de09e455 | 736 | { |
064c2a47 | 737 | return dss.feat->dpi_select_source(port, channel); |
de09e455 TV |
738 | } |
739 | ||
8b9cb3a8 SG |
740 | static int dss_get_clocks(void) |
741 | { | |
4fbafaf3 | 742 | struct clk *clk; |
8b9cb3a8 | 743 | |
b2c9c8ee | 744 | clk = devm_clk_get(&dss.pdev->dev, "fck"); |
4fbafaf3 TV |
745 | if (IS_ERR(clk)) { |
746 | DSSERR("can't get clock fck\n"); | |
b2c9c8ee | 747 | return PTR_ERR(clk); |
a1a0dcca | 748 | } |
8b9cb3a8 | 749 | |
4fbafaf3 | 750 | dss.dss_clk = clk; |
8b9cb3a8 | 751 | |
64ad846f TV |
752 | if (dss.feat->parent_clk_name) { |
753 | clk = clk_get(NULL, dss.feat->parent_clk_name); | |
8ad9375f | 754 | if (IS_ERR(clk)) { |
64ad846f | 755 | DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); |
b2c9c8ee | 756 | return PTR_ERR(clk); |
8ad9375f AK |
757 | } |
758 | } else { | |
759 | clk = NULL; | |
94c042ce TV |
760 | } |
761 | ||
64ad846f | 762 | dss.parent_clk = clk; |
94c042ce | 763 | |
8b9cb3a8 | 764 | return 0; |
8b9cb3a8 SG |
765 | } |
766 | ||
767 | static void dss_put_clocks(void) | |
768 | { | |
64ad846f TV |
769 | if (dss.parent_clk) |
770 | clk_put(dss.parent_clk); | |
8b9cb3a8 SG |
771 | } |
772 | ||
99767548 | 773 | int dss_runtime_get(void) |
8b9cb3a8 | 774 | { |
4fbafaf3 | 775 | int r; |
8b9cb3a8 | 776 | |
4fbafaf3 | 777 | DSSDBG("dss_runtime_get\n"); |
8b9cb3a8 | 778 | |
4fbafaf3 TV |
779 | r = pm_runtime_get_sync(&dss.pdev->dev); |
780 | WARN_ON(r < 0); | |
781 | return r < 0 ? r : 0; | |
8b9cb3a8 SG |
782 | } |
783 | ||
99767548 | 784 | void dss_runtime_put(void) |
8b9cb3a8 | 785 | { |
4fbafaf3 | 786 | int r; |
8b9cb3a8 | 787 | |
4fbafaf3 | 788 | DSSDBG("dss_runtime_put\n"); |
8b9cb3a8 | 789 | |
0eaf9f52 | 790 | r = pm_runtime_put_sync(&dss.pdev->dev); |
5be3aebd | 791 | WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); |
8b9cb3a8 SG |
792 | } |
793 | ||
8b9cb3a8 | 794 | /* DEBUGFS */ |
1b3bcb33 | 795 | #if defined(CONFIG_OMAP2_DSS_DEBUGFS) |
8b9cb3a8 SG |
796 | void dss_debug_dump_clocks(struct seq_file *s) |
797 | { | |
8b9cb3a8 SG |
798 | dss_dump_clocks(s); |
799 | dispc_dump_clocks(s); | |
800 | #ifdef CONFIG_OMAP2_DSS_DSI | |
801 | dsi_dump_clocks(s); | |
802 | #endif | |
803 | } | |
804 | #endif | |
805 | ||
387ce9f2 | 806 | |
234f9a22 | 807 | static const enum omap_display_type omap2plus_ports[] = { |
387ce9f2 AT |
808 | OMAP_DISPLAY_TYPE_DPI, |
809 | }; | |
810 | ||
234f9a22 | 811 | static const enum omap_display_type omap34xx_ports[] = { |
387ce9f2 AT |
812 | OMAP_DISPLAY_TYPE_DPI, |
813 | OMAP_DISPLAY_TYPE_SDI, | |
814 | }; | |
815 | ||
6d817880 TV |
816 | static const enum omap_display_type dra7xx_ports[] = { |
817 | OMAP_DISPLAY_TYPE_DPI, | |
818 | OMAP_DISPLAY_TYPE_DPI, | |
819 | OMAP_DISPLAY_TYPE_DPI, | |
820 | }; | |
821 | ||
ede92695 | 822 | static const struct dss_features omap24xx_dss_feats = { |
6e555e27 TV |
823 | /* |
824 | * fck div max is really 16, but the divider range has gaps. The range | |
825 | * from 1 to 6 has no gaps, so let's use that as a max. | |
826 | */ | |
827 | .fck_div_max = 6, | |
84273a95 | 828 | .dss_fck_multiplier = 2, |
ada9443f | 829 | .parent_clk_name = "core_ck", |
de09e455 | 830 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
387ce9f2 AT |
831 | .ports = omap2plus_ports, |
832 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
84273a95 TV |
833 | }; |
834 | ||
ede92695 | 835 | static const struct dss_features omap34xx_dss_feats = { |
84273a95 TV |
836 | .fck_div_max = 16, |
837 | .dss_fck_multiplier = 2, | |
ada9443f | 838 | .parent_clk_name = "dpll4_ck", |
de09e455 | 839 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
387ce9f2 AT |
840 | .ports = omap34xx_ports, |
841 | .num_ports = ARRAY_SIZE(omap34xx_ports), | |
84273a95 TV |
842 | }; |
843 | ||
ede92695 | 844 | static const struct dss_features omap3630_dss_feats = { |
84273a95 TV |
845 | .fck_div_max = 32, |
846 | .dss_fck_multiplier = 1, | |
ada9443f | 847 | .parent_clk_name = "dpll4_ck", |
de09e455 | 848 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, |
387ce9f2 AT |
849 | .ports = omap2plus_ports, |
850 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
84273a95 TV |
851 | }; |
852 | ||
ede92695 | 853 | static const struct dss_features omap44xx_dss_feats = { |
84273a95 TV |
854 | .fck_div_max = 32, |
855 | .dss_fck_multiplier = 1, | |
ada9443f | 856 | .parent_clk_name = "dpll_per_x2_ck", |
de09e455 | 857 | .dpi_select_source = &dss_dpi_select_source_omap4, |
387ce9f2 AT |
858 | .ports = omap2plus_ports, |
859 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
84273a95 TV |
860 | }; |
861 | ||
ede92695 | 862 | static const struct dss_features omap54xx_dss_feats = { |
84273a95 TV |
863 | .fck_div_max = 64, |
864 | .dss_fck_multiplier = 1, | |
ada9443f | 865 | .parent_clk_name = "dpll_per_x2_ck", |
de09e455 | 866 | .dpi_select_source = &dss_dpi_select_source_omap5, |
387ce9f2 AT |
867 | .ports = omap2plus_ports, |
868 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
84273a95 TV |
869 | }; |
870 | ||
ede92695 | 871 | static const struct dss_features am43xx_dss_feats = { |
d6279d4a SP |
872 | .fck_div_max = 0, |
873 | .dss_fck_multiplier = 0, | |
874 | .parent_clk_name = NULL, | |
875 | .dpi_select_source = &dss_dpi_select_source_omap2_omap3, | |
387ce9f2 AT |
876 | .ports = omap2plus_ports, |
877 | .num_ports = ARRAY_SIZE(omap2plus_ports), | |
d6279d4a SP |
878 | }; |
879 | ||
ede92695 | 880 | static const struct dss_features dra7xx_dss_feats = { |
6d817880 TV |
881 | .fck_div_max = 64, |
882 | .dss_fck_multiplier = 1, | |
883 | .parent_clk_name = "dpll_per_x2_ck", | |
884 | .dpi_select_source = &dss_dpi_select_source_dra7xx, | |
885 | .ports = dra7xx_ports, | |
886 | .num_ports = ARRAY_SIZE(dra7xx_ports), | |
887 | }; | |
888 | ||
ede92695 | 889 | static int dss_init_features(struct platform_device *pdev) |
185bae10 CM |
890 | { |
891 | const struct dss_features *src; | |
892 | struct dss_features *dst; | |
893 | ||
bd81ed08 | 894 | dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL); |
185bae10 | 895 | if (!dst) { |
bd81ed08 | 896 | dev_err(&pdev->dev, "Failed to allocate local DSS Features\n"); |
185bae10 CM |
897 | return -ENOMEM; |
898 | } | |
899 | ||
b2c7d54f | 900 | switch (omapdss_get_version()) { |
bd81ed08 | 901 | case OMAPDSS_VER_OMAP24xx: |
185bae10 | 902 | src = &omap24xx_dss_feats; |
bd81ed08 TV |
903 | break; |
904 | ||
905 | case OMAPDSS_VER_OMAP34xx_ES1: | |
906 | case OMAPDSS_VER_OMAP34xx_ES3: | |
907 | case OMAPDSS_VER_AM35xx: | |
185bae10 | 908 | src = &omap34xx_dss_feats; |
bd81ed08 TV |
909 | break; |
910 | ||
911 | case OMAPDSS_VER_OMAP3630: | |
185bae10 | 912 | src = &omap3630_dss_feats; |
bd81ed08 TV |
913 | break; |
914 | ||
915 | case OMAPDSS_VER_OMAP4430_ES1: | |
916 | case OMAPDSS_VER_OMAP4430_ES2: | |
917 | case OMAPDSS_VER_OMAP4: | |
185bae10 | 918 | src = &omap44xx_dss_feats; |
bd81ed08 TV |
919 | break; |
920 | ||
921 | case OMAPDSS_VER_OMAP5: | |
23362832 | 922 | src = &omap54xx_dss_feats; |
bd81ed08 TV |
923 | break; |
924 | ||
d6279d4a SP |
925 | case OMAPDSS_VER_AM43xx: |
926 | src = &am43xx_dss_feats; | |
927 | break; | |
928 | ||
6d817880 TV |
929 | case OMAPDSS_VER_DRA7xx: |
930 | src = &dra7xx_dss_feats; | |
931 | break; | |
932 | ||
bd81ed08 | 933 | default: |
185bae10 | 934 | return -ENODEV; |
bd81ed08 | 935 | } |
185bae10 CM |
936 | |
937 | memcpy(dst, src, sizeof(*dst)); | |
938 | dss.feat = dst; | |
939 | ||
940 | return 0; | |
941 | } | |
942 | ||
ede92695 | 943 | static int dss_init_ports(struct platform_device *pdev) |
2ecef246 TV |
944 | { |
945 | struct device_node *parent = pdev->dev.of_node; | |
946 | struct device_node *port; | |
947 | int r; | |
948 | ||
949 | if (parent == NULL) | |
950 | return 0; | |
951 | ||
952 | port = omapdss_of_get_next_port(parent, NULL); | |
00592772 | 953 | if (!port) |
2ecef246 | 954 | return 0; |
2ecef246 | 955 | |
387ce9f2 AT |
956 | if (dss.feat->num_ports == 0) |
957 | return 0; | |
958 | ||
2ecef246 | 959 | do { |
387ce9f2 | 960 | enum omap_display_type port_type; |
2ecef246 TV |
961 | u32 reg; |
962 | ||
963 | r = of_property_read_u32(port, "reg", ®); | |
964 | if (r) | |
965 | reg = 0; | |
966 | ||
387ce9f2 AT |
967 | if (reg >= dss.feat->num_ports) |
968 | continue; | |
2ecef246 | 969 | |
387ce9f2 | 970 | port_type = dss.feat->ports[reg]; |
2ecef246 | 971 | |
387ce9f2 AT |
972 | switch (port_type) { |
973 | case OMAP_DISPLAY_TYPE_DPI: | |
974 | dpi_init_port(pdev, port); | |
975 | break; | |
976 | case OMAP_DISPLAY_TYPE_SDI: | |
977 | sdi_init_port(pdev, port); | |
978 | break; | |
979 | default: | |
980 | break; | |
981 | } | |
2ecef246 TV |
982 | } while ((port = omapdss_of_get_next_port(parent, port)) != NULL); |
983 | ||
984 | return 0; | |
985 | } | |
986 | ||
ede92695 | 987 | static void dss_uninit_ports(struct platform_device *pdev) |
2ecef246 | 988 | { |
80eb6751 AT |
989 | struct device_node *parent = pdev->dev.of_node; |
990 | struct device_node *port; | |
991 | ||
992 | if (parent == NULL) | |
993 | return; | |
994 | ||
995 | port = omapdss_of_get_next_port(parent, NULL); | |
996 | if (!port) | |
997 | return; | |
998 | ||
387ce9f2 AT |
999 | if (dss.feat->num_ports == 0) |
1000 | return; | |
2ecef246 | 1001 | |
387ce9f2 AT |
1002 | do { |
1003 | enum omap_display_type port_type; | |
1004 | u32 reg; | |
1005 | int r; | |
1006 | ||
1007 | r = of_property_read_u32(port, "reg", ®); | |
1008 | if (r) | |
1009 | reg = 0; | |
1010 | ||
1011 | if (reg >= dss.feat->num_ports) | |
1012 | continue; | |
1013 | ||
1014 | port_type = dss.feat->ports[reg]; | |
1015 | ||
1016 | switch (port_type) { | |
1017 | case OMAP_DISPLAY_TYPE_DPI: | |
1018 | dpi_uninit_port(port); | |
1019 | break; | |
1020 | case OMAP_DISPLAY_TYPE_SDI: | |
1021 | sdi_uninit_port(port); | |
1022 | break; | |
1023 | default: | |
1024 | break; | |
1025 | } | |
1026 | } while ((port = omapdss_of_get_next_port(parent, port)) != NULL); | |
2ecef246 TV |
1027 | } |
1028 | ||
7e328f5a TV |
1029 | static int dss_video_pll_probe(struct platform_device *pdev) |
1030 | { | |
1031 | struct device_node *np = pdev->dev.of_node; | |
1032 | struct regulator *pll_regulator; | |
1033 | int r; | |
1034 | ||
1035 | if (!np) | |
1036 | return 0; | |
1037 | ||
1038 | if (of_property_read_bool(np, "syscon-pll-ctrl")) { | |
1039 | dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, | |
1040 | "syscon-pll-ctrl"); | |
1041 | if (IS_ERR(dss.syscon_pll_ctrl)) { | |
1042 | dev_err(&pdev->dev, | |
1043 | "failed to get syscon-pll-ctrl regmap\n"); | |
1044 | return PTR_ERR(dss.syscon_pll_ctrl); | |
1045 | } | |
1046 | ||
1047 | if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, | |
1048 | &dss.syscon_pll_ctrl_offset)) { | |
1049 | dev_err(&pdev->dev, | |
1050 | "failed to get syscon-pll-ctrl offset\n"); | |
1051 | return -EINVAL; | |
1052 | } | |
1053 | } | |
1054 | ||
1055 | pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); | |
1056 | if (IS_ERR(pll_regulator)) { | |
1057 | r = PTR_ERR(pll_regulator); | |
1058 | ||
1059 | switch (r) { | |
1060 | case -ENOENT: | |
1061 | pll_regulator = NULL; | |
1062 | break; | |
1063 | ||
1064 | case -EPROBE_DEFER: | |
1065 | return -EPROBE_DEFER; | |
1066 | ||
1067 | default: | |
1068 | DSSERR("can't get DPLL VDDA regulator\n"); | |
1069 | return r; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | if (of_property_match_string(np, "reg-names", "pll1") >= 0) { | |
1074 | dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); | |
1075 | if (IS_ERR(dss.video1_pll)) | |
1076 | return PTR_ERR(dss.video1_pll); | |
1077 | } | |
1078 | ||
1079 | if (of_property_match_string(np, "reg-names", "pll2") >= 0) { | |
1080 | dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); | |
1081 | if (IS_ERR(dss.video2_pll)) { | |
1082 | dss_video_pll_uninit(dss.video1_pll); | |
1083 | return PTR_ERR(dss.video2_pll); | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
96c401bc | 1090 | /* DSS HW IP initialisation */ |
ede92695 | 1091 | static int omap_dsshw_probe(struct platform_device *pdev) |
96c401bc | 1092 | { |
b98482ed TV |
1093 | struct resource *dss_mem; |
1094 | u32 rev; | |
96c401bc | 1095 | int r; |
96c401bc SG |
1096 | |
1097 | dss.pdev = pdev; | |
1098 | ||
bd81ed08 | 1099 | r = dss_init_features(dss.pdev); |
185bae10 CM |
1100 | if (r) |
1101 | return r; | |
1102 | ||
b98482ed TV |
1103 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
1104 | if (!dss_mem) { | |
1105 | DSSERR("can't get IORESOURCE_MEM DSS\n"); | |
cd3b3449 | 1106 | return -EINVAL; |
b98482ed | 1107 | } |
cd3b3449 | 1108 | |
6e2a14d2 JL |
1109 | dss.base = devm_ioremap(&pdev->dev, dss_mem->start, |
1110 | resource_size(dss_mem)); | |
b98482ed TV |
1111 | if (!dss.base) { |
1112 | DSSERR("can't ioremap DSS\n"); | |
cd3b3449 | 1113 | return -ENOMEM; |
b98482ed TV |
1114 | } |
1115 | ||
8b9cb3a8 SG |
1116 | r = dss_get_clocks(); |
1117 | if (r) | |
cd3b3449 | 1118 | return r; |
8b9cb3a8 | 1119 | |
13a1a2b2 TV |
1120 | r = dss_setup_default_clock(); |
1121 | if (r) | |
1122 | goto err_setup_clocks; | |
1123 | ||
7e328f5a TV |
1124 | r = dss_video_pll_probe(pdev); |
1125 | if (r) | |
1126 | goto err_pll_init; | |
1127 | ||
f5a1a1f8 TV |
1128 | r = dss_init_ports(pdev); |
1129 | if (r) | |
1130 | goto err_init_ports; | |
1131 | ||
4fbafaf3 | 1132 | pm_runtime_enable(&pdev->dev); |
b98482ed | 1133 | |
4fbafaf3 TV |
1134 | r = dss_runtime_get(); |
1135 | if (r) | |
1136 | goto err_runtime_get; | |
b98482ed | 1137 | |
5aaee69d TV |
1138 | dss.dss_clk_rate = clk_get_rate(dss.dss_clk); |
1139 | ||
b98482ed TV |
1140 | /* Select DPLL */ |
1141 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); | |
1142 | ||
a5b8399f TV |
1143 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
1144 | ||
b98482ed TV |
1145 | #ifdef CONFIG_OMAP2_DSS_VENC |
1146 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ | |
1147 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ | |
1148 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ | |
1149 | #endif | |
1150 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | |
1151 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | |
1152 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; | |
1153 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | |
1154 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | |
96c401bc | 1155 | |
b98482ed TV |
1156 | rev = dss_read_reg(DSS_REVISION); |
1157 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", | |
1158 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
1159 | ||
4fbafaf3 | 1160 | dss_runtime_put(); |
b98482ed | 1161 | |
e40402cf TV |
1162 | dss_debugfs_create_file("dss", dss_dump_regs); |
1163 | ||
cb17a4ae TV |
1164 | pm_set_vt_switch(0); |
1165 | ||
f99467b3 TV |
1166 | dss_initialized = true; |
1167 | ||
8b9cb3a8 | 1168 | return 0; |
a57dd4fe | 1169 | |
7e328f5a TV |
1170 | err_runtime_get: |
1171 | pm_runtime_disable(&pdev->dev); | |
f5a1a1f8 TV |
1172 | dss_uninit_ports(pdev); |
1173 | err_init_ports: | |
99767548 TV |
1174 | if (dss.video1_pll) |
1175 | dss_video_pll_uninit(dss.video1_pll); | |
1176 | ||
1177 | if (dss.video2_pll) | |
1178 | dss_video_pll_uninit(dss.video2_pll); | |
7e328f5a | 1179 | err_pll_init: |
13a1a2b2 | 1180 | err_setup_clocks: |
8b9cb3a8 | 1181 | dss_put_clocks(); |
96c401bc SG |
1182 | return r; |
1183 | } | |
1184 | ||
ede92695 | 1185 | static int omap_dsshw_remove(struct platform_device *pdev) |
96c401bc | 1186 | { |
f99467b3 TV |
1187 | dss_initialized = false; |
1188 | ||
99767548 TV |
1189 | if (dss.video1_pll) |
1190 | dss_video_pll_uninit(dss.video1_pll); | |
1191 | ||
1192 | if (dss.video2_pll) | |
1193 | dss_video_pll_uninit(dss.video2_pll); | |
1194 | ||
2ac6a1aa | 1195 | dss_uninit_ports(pdev); |
2ecef246 | 1196 | |
4fbafaf3 | 1197 | pm_runtime_disable(&pdev->dev); |
8b9cb3a8 SG |
1198 | |
1199 | dss_put_clocks(); | |
b98482ed | 1200 | |
96c401bc SG |
1201 | return 0; |
1202 | } | |
1203 | ||
4fbafaf3 TV |
1204 | static int dss_runtime_suspend(struct device *dev) |
1205 | { | |
1206 | dss_save_context(); | |
a8081d31 | 1207 | dss_set_min_bus_tput(dev, 0); |
4fbafaf3 TV |
1208 | return 0; |
1209 | } | |
1210 | ||
1211 | static int dss_runtime_resume(struct device *dev) | |
1212 | { | |
a8081d31 TV |
1213 | int r; |
1214 | /* | |
1215 | * Set an arbitrarily high tput request to ensure OPP100. | |
1216 | * What we should really do is to make a request to stay in OPP100, | |
1217 | * without any tput requirements, but that is not currently possible | |
1218 | * via the PM layer. | |
1219 | */ | |
1220 | ||
1221 | r = dss_set_min_bus_tput(dev, 1000000000); | |
1222 | if (r) | |
1223 | return r; | |
1224 | ||
39020710 | 1225 | dss_restore_context(); |
4fbafaf3 TV |
1226 | return 0; |
1227 | } | |
1228 | ||
1229 | static const struct dev_pm_ops dss_pm_ops = { | |
1230 | .runtime_suspend = dss_runtime_suspend, | |
1231 | .runtime_resume = dss_runtime_resume, | |
1232 | }; | |
1233 | ||
2ecef246 TV |
1234 | static const struct of_device_id dss_of_match[] = { |
1235 | { .compatible = "ti,omap2-dss", }, | |
1236 | { .compatible = "ti,omap3-dss", }, | |
1237 | { .compatible = "ti,omap4-dss", }, | |
2e7e6b68 | 1238 | { .compatible = "ti,omap5-dss", }, |
6d817880 | 1239 | { .compatible = "ti,dra7-dss", }, |
2ecef246 TV |
1240 | {}, |
1241 | }; | |
1242 | ||
1243 | MODULE_DEVICE_TABLE(of, dss_of_match); | |
1244 | ||
96c401bc | 1245 | static struct platform_driver omap_dsshw_driver = { |
ede92695 | 1246 | .remove = omap_dsshw_remove, |
96c401bc SG |
1247 | .driver = { |
1248 | .name = "omapdss_dss", | |
4fbafaf3 | 1249 | .pm = &dss_pm_ops, |
2ecef246 | 1250 | .of_match_table = dss_of_match, |
422ccbd5 | 1251 | .suppress_bind_attrs = true, |
96c401bc SG |
1252 | }, |
1253 | }; | |
1254 | ||
6e7e8f06 | 1255 | int __init dss_init_platform_driver(void) |
96c401bc | 1256 | { |
11436e1d | 1257 | return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe); |
96c401bc SG |
1258 | } |
1259 | ||
1260 | void dss_uninit_platform_driver(void) | |
1261 | { | |
04c742c3 | 1262 | platform_driver_unregister(&omap_dsshw_driver); |
96c401bc | 1263 | } |