OMAPDSS: HDMI: improve Makefile
[deliverable/linux.git] / drivers / video / fbdev / omap2 / dss / hdmi4.c
CommitLineData
c3198a5e 1/*
ef26958a 2 * HDMI interface DSS driver for TI's OMAP4 family of SoCs.
c3198a5e
M
3 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
4 * Authors: Yong Zhi
5 * Mythri pk <mythripk@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "HDMI"
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/interrupt.h>
27#include <linux/mutex.h>
28#include <linux/delay.h>
29#include <linux/string.h>
24e6289c 30#include <linux/platform_device.h>
4fbafaf3
TV
31#include <linux/pm_runtime.h>
32#include <linux/clk.h>
cca35017 33#include <linux/gpio.h>
17486943 34#include <linux/regulator/consumer.h>
a0b38cc4 35#include <video/omapdss.h>
c3198a5e 36
ef26958a 37#include "hdmi4_core.h"
c3198a5e 38#include "dss.h"
ad44cc32 39#include "dss_features.h"
c3198a5e
M
40
41static struct {
42 struct mutex lock;
c3198a5e 43 struct platform_device *pdev;
66a06b0c 44
275cfa1a
AT
45 struct hdmi_wp_data wp;
46 struct hdmi_pll_data pll;
47 struct hdmi_phy_data phy;
48 struct hdmi_core_data core;
49
50 struct hdmi_config cfg;
4fbafaf3
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51
52 struct clk *sys_clk;
17486943 53 struct regulator *vdda_hdmi_dac_reg;
cca35017 54
0b450c31
TV
55 bool core_enabled;
56
1f68d9c4 57 struct omap_dss_device output;
c3198a5e
M
58} hdmi;
59
4fbafaf3
TV
60static int hdmi_runtime_get(void)
61{
62 int r;
63
64 DSSDBG("hdmi_runtime_get\n");
65
66 r = pm_runtime_get_sync(&hdmi.pdev->dev);
67 WARN_ON(r < 0);
a247ce78 68 if (r < 0)
852f0838 69 return r;
a247ce78
AT
70
71 return 0;
4fbafaf3
TV
72}
73
74static void hdmi_runtime_put(void)
75{
76 int r;
77
78 DSSDBG("hdmi_runtime_put\n");
79
0eaf9f52 80 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 81 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV
82}
83
e25001d8
TV
84static int hdmi_init_regulator(void)
85{
818a053c 86 int r;
e25001d8
TV
87 struct regulator *reg;
88
89 if (hdmi.vdda_hdmi_dac_reg != NULL)
90 return 0;
91
931d4bd6 92 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
e25001d8
TV
93
94 if (IS_ERR(reg)) {
40359a9b 95 if (PTR_ERR(reg) != -EPROBE_DEFER)
931d4bd6 96 DSSERR("can't get VDDA regulator\n");
e25001d8
TV
97 return PTR_ERR(reg);
98 }
99
818a053c
TV
100 if (regulator_can_change_voltage(reg)) {
101 r = regulator_set_voltage(reg, 1800000, 1800000);
102 if (r) {
103 devm_regulator_put(reg);
104 DSSWARN("can't set the regulator voltage\n");
105 return r;
106 }
107 }
108
e25001d8
TV
109 hdmi.vdda_hdmi_dac_reg = reg;
110
111 return 0;
112}
113
bb426fc9 114static int hdmi_power_on_core(struct omap_dss_device *dssdev)
c3198a5e 115{
46095b2d 116 int r;
c3198a5e 117
17486943
TV
118 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
119 if (r)
164ebdd1 120 return r;
17486943 121
4fbafaf3
TV
122 r = hdmi_runtime_get();
123 if (r)
cca35017 124 goto err_runtime_get;
c3198a5e 125
bb426fc9
TV
126 /* Make selection of HDMI in DSS */
127 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
128
0b450c31
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129 hdmi.core_enabled = true;
130
bb426fc9
TV
131 return 0;
132
133err_runtime_get:
134 regulator_disable(hdmi.vdda_hdmi_dac_reg);
164ebdd1 135
bb426fc9
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136 return r;
137}
138
139static void hdmi_power_off_core(struct omap_dss_device *dssdev)
140{
0b450c31
TV
141 hdmi.core_enabled = false;
142
bb426fc9
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143 hdmi_runtime_put();
144 regulator_disable(hdmi.vdda_hdmi_dac_reg);
bb426fc9
TV
145}
146
147static int hdmi_power_on_full(struct omap_dss_device *dssdev)
148{
149 int r;
150 struct omap_video_timings *p;
7ae9a71e 151 struct omap_overlay_manager *mgr = hdmi.output.manager;
bb426fc9
TV
152 unsigned long phy;
153
154 r = hdmi_power_on_core(dssdev);
155 if (r)
156 return r;
157
275cfa1a 158 p = &hdmi.cfg.timings;
c3198a5e 159
7849398f 160 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 161
d8d78941
TV
162 /* the functions below use kHz pixel clock. TODO: change to Hz */
163 phy = p->pixelclock / 1000;
c3198a5e 164
275cfa1a 165 hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), phy);
c3198a5e 166
95a8aeb6 167 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
275cfa1a 168 r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
c3198a5e
M
169 if (r) {
170 DSSDBG("Failed to lock PLL\n");
cca35017 171 goto err_pll_enable;
c3198a5e
M
172 }
173
275cfa1a 174 r = hdmi_phy_enable(&hdmi.phy, &hdmi.wp, &hdmi.cfg);
c3198a5e
M
175 if (r) {
176 DSSDBG("Failed to start PHY\n");
d3b4aa51 177 goto err_phy_enable;
c3198a5e
M
178 }
179
275cfa1a 180 hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
c3198a5e 181
c3198a5e
M
182 /* bypass TV gamma table */
183 dispc_enable_gamma_table(0);
184
185 /* tv size */
cea87b92 186 dss_mgr_set_timings(mgr, p);
c3198a5e 187
275cfa1a 188 r = hdmi_wp_video_start(&hdmi.wp);
c0456be3
RN
189 if (r)
190 goto err_vid_enable;
c3198a5e 191
cea87b92 192 r = dss_mgr_enable(mgr);
33ca237f
TV
193 if (r)
194 goto err_mgr_enable;
3870c909 195
c3198a5e 196 return 0;
33ca237f
TV
197
198err_mgr_enable:
275cfa1a 199 hdmi_wp_video_stop(&hdmi.wp);
c0456be3 200err_vid_enable:
275cfa1a 201 hdmi_phy_disable(&hdmi.phy, &hdmi.wp);
d3b4aa51 202err_phy_enable:
275cfa1a 203 hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
cca35017 204err_pll_enable:
bb426fc9 205 hdmi_power_off_core(dssdev);
c3198a5e
M
206 return -EIO;
207}
208
bb426fc9 209static void hdmi_power_off_full(struct omap_dss_device *dssdev)
c3198a5e 210{
7ae9a71e 211 struct omap_overlay_manager *mgr = hdmi.output.manager;
cea87b92
AT
212
213 dss_mgr_disable(mgr);
c3198a5e 214
275cfa1a
AT
215 hdmi_wp_video_stop(&hdmi.wp);
216 hdmi_phy_disable(&hdmi.phy, &hdmi.wp);
217 hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
17486943 218
bb426fc9 219 hdmi_power_off_core(dssdev);
c3198a5e
M
220}
221
164ebdd1 222static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
c3198a5e
M
223 struct omap_video_timings *timings)
224{
1e676248 225 struct omap_dss_device *out = &hdmi.output;
c3198a5e 226
1e676248 227 if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
c3198a5e 228 return -EINVAL;
c3198a5e
M
229
230 return 0;
c3198a5e
M
231}
232
164ebdd1 233static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
7849398f 234 struct omap_video_timings *timings)
c3198a5e
M
235{
236 struct hdmi_cm cm;
7849398f 237 const struct hdmi_config *t;
c3198a5e 238
ed1aa900
AT
239 mutex_lock(&hdmi.lock);
240
7849398f 241 cm = hdmi_get_code(timings);
275cfa1a 242 hdmi.cfg.cm = cm;
7849398f 243
08d83e4e 244 t = hdmi_get_timings(cm.mode, cm.code);
db680c65 245 if (t != NULL) {
275cfa1a 246 hdmi.cfg = *t;
fa70dc5f 247
d8d78941 248 dispc_set_tv_pclk(t->timings.pixelclock);
1e676248
AT
249 } else {
250 hdmi.cfg.timings = *timings;
251 hdmi.cfg.cm.code = 0;
252 hdmi.cfg.cm.mode = HDMI_DVI;
253
d8d78941 254 dispc_set_tv_pclk(timings->pixelclock);
db680c65 255 }
5391e87d 256
1e676248
AT
257 DSSDBG("using mode: %s, code %d\n", hdmi.cfg.cm.mode == HDMI_DVI ?
258 "DVI" : "HDMI", hdmi.cfg.cm.code);
259
ed1aa900 260 mutex_unlock(&hdmi.lock);
c3198a5e
M
261}
262
164ebdd1 263static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
0b450c31
TV
264 struct omap_video_timings *timings)
265{
266 const struct hdmi_config *cfg;
08d83e4e 267 struct hdmi_cm cm = hdmi.cfg.cm;
0b450c31 268
08d83e4e 269 cfg = hdmi_get_timings(cm.mode, cm.code);
0b450c31 270 if (cfg == NULL)
08d83e4e 271 cfg = hdmi_default_timing();
0b450c31
TV
272
273 memcpy(timings, &cfg->timings, sizeof(cfg->timings));
274}
275
e40402cf 276static void hdmi_dump_regs(struct seq_file *s)
162874d5
M
277{
278 mutex_lock(&hdmi.lock);
279
f8fb7d7b
WY
280 if (hdmi_runtime_get()) {
281 mutex_unlock(&hdmi.lock);
162874d5 282 return;
f8fb7d7b 283 }
162874d5 284
275cfa1a
AT
285 hdmi_wp_dump(&hdmi.wp, s);
286 hdmi_pll_dump(&hdmi.pll, s);
287 hdmi_phy_dump(&hdmi.phy, s);
288 hdmi4_core_dump(&hdmi.core, s);
162874d5
M
289
290 hdmi_runtime_put();
291 mutex_unlock(&hdmi.lock);
292}
293
164ebdd1 294static int read_edid(u8 *buf, int len)
47024565
TV
295{
296 int r;
297
298 mutex_lock(&hdmi.lock);
299
300 r = hdmi_runtime_get();
301 BUG_ON(r);
302
275cfa1a 303 r = hdmi4_read_edid(&hdmi.core, buf, len);
47024565
TV
304
305 hdmi_runtime_put();
306 mutex_unlock(&hdmi.lock);
307
308 return r;
309}
310
164ebdd1 311static int hdmi_display_enable(struct omap_dss_device *dssdev)
c3198a5e 312{
1f68d9c4 313 struct omap_dss_device *out = &hdmi.output;
c3198a5e
M
314 int r = 0;
315
316 DSSDBG("ENTER hdmi_display_enable\n");
317
318 mutex_lock(&hdmi.lock);
319
cea87b92
AT
320 if (out == NULL || out->manager == NULL) {
321 DSSERR("failed to enable display: no output/manager\n");
05e1d606
TV
322 r = -ENODEV;
323 goto err0;
324 }
325
bb426fc9 326 r = hdmi_power_on_full(dssdev);
c3198a5e
M
327 if (r) {
328 DSSERR("failed to power on device\n");
d3923933 329 goto err0;
c3198a5e
M
330 }
331
332 mutex_unlock(&hdmi.lock);
333 return 0;
334
c3198a5e
M
335err0:
336 mutex_unlock(&hdmi.lock);
337 return r;
338}
339
164ebdd1 340static void hdmi_display_disable(struct omap_dss_device *dssdev)
c3198a5e
M
341{
342 DSSDBG("Enter hdmi_display_disable\n");
343
344 mutex_lock(&hdmi.lock);
345
bb426fc9 346 hdmi_power_off_full(dssdev);
c3198a5e 347
c3198a5e
M
348 mutex_unlock(&hdmi.lock);
349}
350
164ebdd1 351static int hdmi_core_enable(struct omap_dss_device *dssdev)
4489823c
TV
352{
353 int r = 0;
354
355 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
356
357 mutex_lock(&hdmi.lock);
358
4489823c
TV
359 r = hdmi_power_on_core(dssdev);
360 if (r) {
361 DSSERR("failed to power on device\n");
362 goto err0;
363 }
364
365 mutex_unlock(&hdmi.lock);
366 return 0;
367
368err0:
369 mutex_unlock(&hdmi.lock);
370 return r;
371}
372
164ebdd1 373static void hdmi_core_disable(struct omap_dss_device *dssdev)
4489823c
TV
374{
375 DSSDBG("Enter omapdss_hdmi_core_disable\n");
376
377 mutex_lock(&hdmi.lock);
378
379 hdmi_power_off_core(dssdev);
380
381 mutex_unlock(&hdmi.lock);
382}
383
4fbafaf3
TV
384static int hdmi_get_clocks(struct platform_device *pdev)
385{
386 struct clk *clk;
387
b2c9c8ee 388 clk = devm_clk_get(&pdev->dev, "sys_clk");
4fbafaf3
TV
389 if (IS_ERR(clk)) {
390 DSSERR("can't get sys_clk\n");
391 return PTR_ERR(clk);
392 }
393
394 hdmi.sys_clk = clk;
395
4fbafaf3
TV
396 return 0;
397}
398
0b450c31
TV
399static int hdmi_connect(struct omap_dss_device *dssdev,
400 struct omap_dss_device *dst)
401{
402 struct omap_overlay_manager *mgr;
403 int r;
404
0b450c31
TV
405 r = hdmi_init_regulator();
406 if (r)
407 return r;
408
409 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
410 if (!mgr)
411 return -ENODEV;
412
413 r = dss_mgr_connect(mgr, dssdev);
414 if (r)
415 return r;
416
417 r = omapdss_output_set_device(dssdev, dst);
418 if (r) {
419 DSSERR("failed to connect output to new device: %s\n",
420 dst->name);
421 dss_mgr_disconnect(mgr, dssdev);
422 return r;
423 }
424
425 return 0;
426}
427
428static void hdmi_disconnect(struct omap_dss_device *dssdev,
429 struct omap_dss_device *dst)
430{
9560dc10 431 WARN_ON(dst != dssdev->dst);
0b450c31 432
9560dc10 433 if (dst != dssdev->dst)
0b450c31
TV
434 return;
435
436 omapdss_output_unset_device(dssdev);
437
438 if (dssdev->manager)
439 dss_mgr_disconnect(dssdev->manager, dssdev);
440}
441
442static int hdmi_read_edid(struct omap_dss_device *dssdev,
443 u8 *edid, int len)
444{
445 bool need_enable;
446 int r;
447
448 need_enable = hdmi.core_enabled == false;
449
450 if (need_enable) {
164ebdd1 451 r = hdmi_core_enable(dssdev);
0b450c31
TV
452 if (r)
453 return r;
454 }
455
164ebdd1 456 r = read_edid(edid, len);
0b450c31
TV
457
458 if (need_enable)
164ebdd1 459 hdmi_core_disable(dssdev);
0b450c31
TV
460
461 return r;
462}
463
464#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
164ebdd1 465static int hdmi_audio_enable(struct omap_dss_device *dssdev)
0b450c31
TV
466{
467 int r;
468
469 mutex_lock(&hdmi.lock);
470
08d83e4e 471 if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
0b450c31
TV
472 r = -EPERM;
473 goto err;
474 }
475
275cfa1a 476 r = hdmi_wp_audio_enable(&hdmi.wp, true);
0b450c31
TV
477 if (r)
478 goto err;
479
480 mutex_unlock(&hdmi.lock);
481 return 0;
482
483err:
484 mutex_unlock(&hdmi.lock);
485 return r;
486}
487
164ebdd1 488static void hdmi_audio_disable(struct omap_dss_device *dssdev)
0b450c31 489{
275cfa1a 490 hdmi_wp_audio_enable(&hdmi.wp, false);
0b450c31
TV
491}
492
164ebdd1 493static int hdmi_audio_start(struct omap_dss_device *dssdev)
0b450c31 494{
275cfa1a 495 return hdmi4_audio_start(&hdmi.core, &hdmi.wp);
0b450c31
TV
496}
497
164ebdd1 498static void hdmi_audio_stop(struct omap_dss_device *dssdev)
0b450c31 499{
275cfa1a 500 hdmi4_audio_stop(&hdmi.core, &hdmi.wp);
0b450c31
TV
501}
502
164ebdd1 503static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
0b450c31
TV
504{
505 bool r;
506
507 mutex_lock(&hdmi.lock);
508
08d83e4e 509 r = hdmi_mode_has_audio(hdmi.cfg.cm.mode);
0b450c31
TV
510
511 mutex_unlock(&hdmi.lock);
512 return r;
513}
514
164ebdd1 515static int hdmi_audio_config(struct omap_dss_device *dssdev,
0b450c31
TV
516 struct omap_dss_audio *audio)
517{
518 int r;
d8d78941 519 u32 pclk = hdmi.cfg.timings.pixelclock;
0b450c31
TV
520
521 mutex_lock(&hdmi.lock);
522
08d83e4e 523 if (!hdmi_mode_has_audio(hdmi.cfg.cm.mode)) {
0b450c31
TV
524 r = -EPERM;
525 goto err;
526 }
527
08d83e4e 528 r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, audio, pclk);
0b450c31
TV
529 if (r)
530 goto err;
531
532 mutex_unlock(&hdmi.lock);
533 return 0;
534
535err:
536 mutex_unlock(&hdmi.lock);
537 return r;
538}
539#else
164ebdd1 540static int hdmi_audio_enable(struct omap_dss_device *dssdev)
0b450c31
TV
541{
542 return -EPERM;
543}
544
164ebdd1 545static void hdmi_audio_disable(struct omap_dss_device *dssdev)
0b450c31
TV
546{
547}
548
164ebdd1 549static int hdmi_audio_start(struct omap_dss_device *dssdev)
0b450c31
TV
550{
551 return -EPERM;
552}
553
164ebdd1 554static void hdmi_audio_stop(struct omap_dss_device *dssdev)
0b450c31
TV
555{
556}
557
164ebdd1 558static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
0b450c31
TV
559{
560 return false;
561}
562
164ebdd1 563static int hdmi_audio_config(struct omap_dss_device *dssdev,
0b450c31
TV
564 struct omap_dss_audio *audio)
565{
566 return -EPERM;
567}
568#endif
569
570static const struct omapdss_hdmi_ops hdmi_ops = {
571 .connect = hdmi_connect,
572 .disconnect = hdmi_disconnect,
573
164ebdd1
TV
574 .enable = hdmi_display_enable,
575 .disable = hdmi_display_disable,
0b450c31 576
164ebdd1
TV
577 .check_timings = hdmi_display_check_timing,
578 .set_timings = hdmi_display_set_timing,
579 .get_timings = hdmi_display_get_timings,
0b450c31
TV
580
581 .read_edid = hdmi_read_edid,
582
164ebdd1
TV
583 .audio_enable = hdmi_audio_enable,
584 .audio_disable = hdmi_audio_disable,
585 .audio_start = hdmi_audio_start,
586 .audio_stop = hdmi_audio_stop,
587 .audio_supported = hdmi_audio_supported,
588 .audio_config = hdmi_audio_config,
0b450c31
TV
589};
590
17ae4e8c 591static void hdmi_init_output(struct platform_device *pdev)
81b87f51 592{
1f68d9c4 593 struct omap_dss_device *out = &hdmi.output;
81b87f51 594
1f68d9c4 595 out->dev = &pdev->dev;
81b87f51 596 out->id = OMAP_DSS_OUTPUT_HDMI;
1f68d9c4 597 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
7286a08f 598 out->name = "hdmi.0";
2eea5ae6 599 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
0b450c31 600 out->ops.hdmi = &hdmi_ops;
b7328e14 601 out->owner = THIS_MODULE;
81b87f51 602
5d47dbc8 603 omapdss_register_output(out);
81b87f51
AT
604}
605
606static void __exit hdmi_uninit_output(struct platform_device *pdev)
607{
1f68d9c4 608 struct omap_dss_device *out = &hdmi.output;
81b87f51 609
5d47dbc8 610 omapdss_unregister_output(out);
81b87f51
AT
611}
612
2f5dc676
TV
613static int hdmi_probe_of(struct platform_device *pdev)
614{
615 struct device_node *node = pdev->dev.of_node;
616 struct device_node *ep;
617 int r;
618
619 ep = omapdss_of_get_first_endpoint(node);
620 if (!ep)
621 return 0;
622
623 r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
624 if (r)
625 goto err;
626
627 of_node_put(ep);
628 return 0;
629
630err:
631 of_node_put(ep);
632 return r;
633}
634
c3198a5e 635/* HDMI HW IP initialisation */
17ae4e8c 636static int omapdss_hdmihw_probe(struct platform_device *pdev)
c3198a5e 637{
38f3daf6 638 int r;
c3198a5e 639
c3198a5e
M
640 hdmi.pdev = pdev;
641
642 mutex_init(&hdmi.lock);
643
2f5dc676
TV
644 if (pdev->dev.of_node) {
645 r = hdmi_probe_of(pdev);
646 if (r)
647 return r;
648 }
649
275cfa1a 650 r = hdmi_wp_init(pdev, &hdmi.wp);
f382d9eb
AT
651 if (r)
652 return r;
c3198a5e 653
275cfa1a 654 r = hdmi_pll_init(pdev, &hdmi.pll);
c1577c1e
AT
655 if (r)
656 return r;
657
275cfa1a 658 r = hdmi_phy_init(pdev, &hdmi.phy);
5cac5aee
AT
659 if (r)
660 return r;
ddb1d5ca 661
275cfa1a 662 r = hdmi4_core_init(pdev, &hdmi.core);
425f02fd
AT
663 if (r)
664 return r;
665
4fbafaf3
TV
666 r = hdmi_get_clocks(pdev);
667 if (r) {
47e443bc 668 DSSERR("can't get clocks\n");
4fbafaf3
TV
669 return r;
670 }
671
672 pm_runtime_enable(&pdev->dev);
673
002d368d
TV
674 hdmi_init_output(pdev);
675
e40402cf
TV
676 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
677
cca35017
TV
678 return 0;
679}
680
6e7e8f06 681static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
c3198a5e 682{
81b87f51
AT
683 hdmi_uninit_output(pdev);
684
4fbafaf3
TV
685 pm_runtime_disable(&pdev->dev);
686
c3198a5e
M
687 return 0;
688}
689
4fbafaf3
TV
690static int hdmi_runtime_suspend(struct device *dev)
691{
f11766d1 692 clk_disable_unprepare(hdmi.sys_clk);
4fbafaf3
TV
693
694 dispc_runtime_put();
4fbafaf3
TV
695
696 return 0;
697}
698
699static int hdmi_runtime_resume(struct device *dev)
700{
701 int r;
702
4fbafaf3
TV
703 r = dispc_runtime_get();
704 if (r < 0)
852f0838 705 return r;
4fbafaf3 706
f11766d1 707 clk_prepare_enable(hdmi.sys_clk);
4fbafaf3
TV
708
709 return 0;
4fbafaf3
TV
710}
711
712static const struct dev_pm_ops hdmi_pm_ops = {
713 .runtime_suspend = hdmi_runtime_suspend,
714 .runtime_resume = hdmi_runtime_resume,
715};
716
0465616d
TV
717static const struct of_device_id hdmi_of_match[] = {
718 { .compatible = "ti,omap4-hdmi", },
719 {},
720};
721
c3198a5e 722static struct platform_driver omapdss_hdmihw_driver = {
17ae4e8c 723 .probe = omapdss_hdmihw_probe,
6e7e8f06 724 .remove = __exit_p(omapdss_hdmihw_remove),
c3198a5e
M
725 .driver = {
726 .name = "omapdss_hdmi",
727 .owner = THIS_MODULE,
4fbafaf3 728 .pm = &hdmi_pm_ops,
0465616d 729 .of_match_table = hdmi_of_match,
c3198a5e
M
730 },
731};
732
ef26958a 733int __init hdmi4_init_platform_driver(void)
c3198a5e 734{
17ae4e8c 735 return platform_driver_register(&omapdss_hdmihw_driver);
c3198a5e
M
736}
737
ef26958a 738void __exit hdmi4_uninit_platform_driver(void)
c3198a5e 739{
04c742c3 740 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 741}
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