projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / video / fbdev / omap2 / omapfb / dss / dispc.c
CommitLineData
f76ee892
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/export.h>
29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
35#include <linux/hardirq.h>
36#include <linux/platform_device.h>
37#include <linux/pm_runtime.h>
38#include <linux/sizes.h>
39#include <linux/mfd/syscon.h>
40#include <linux/regmap.h>
41#include <linux/of.h>
42#include <linux/component.h>
43
62d9e44e 44#include <video/omapfb_dss.h>
f76ee892
TV		 45
46#include "dss.h"
47#include "dss_features.h"
48#include "dispc.h"
49
50/* DISPC */
51#define DISPC_SZ_REGS SZ_4K
52
53enum omap_burst_size {
54 BURST_SIZE_X2 = 0,
55 BURST_SIZE_X4 = 1,
56 BURST_SIZE_X8 = 2,
57};
58
59#define REG_GET(idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end)
61
62#define REG_FLD_MOD(idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
64
65struct dispc_features {
66 u8 sw_start;
67 u8 fp_start;
68 u8 bp_start;
69 u16 sw_max;
70 u16 vp_max;
71 u16 hp_max;
72 u8 mgr_width_start;
73 u8 mgr_height_start;
74 u16 mgr_width_max;
75 u16 mgr_height_max;
76 unsigned long max_lcd_pclk;
77 unsigned long max_tv_pclk;
78 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
79 const struct omap_video_timings *mgr_timings,
80 u16 width, u16 height, u16 out_width, u16 out_height,
81 enum omap_color_mode color_mode, bool *five_taps,
82 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
83 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
84 unsigned long (*calc_core_clk) (unsigned long pclk,
85 u16 width, u16 height, u16 out_width, u16 out_height,
86 bool mem_to_mem);
87 u8 num_fifos;
88
89 /* swap GFX & WB fifos */
90 bool gfx_fifo_workaround:1;
91
92 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
93 bool no_framedone_tv:1;
94
95 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
96 bool mstandby_workaround:1;
97
98 bool set_max_preload:1;
99
100 /* PIXEL_INC is not added to the last pixel of a line */
101 bool last_pixel_inc_missing:1;
102
103 /* POL_FREQ has ALIGN bit */
104 bool supports_sync_align:1;
105
106 bool has_writeback:1;
107};
108
109#define DISPC_MAX_NR_FIFOS 5
110
111static struct {
112 struct platform_device *pdev;
113 void __iomem *base;
114
115 int irq;
116 irq_handler_t user_handler;
117 void *user_data;
118
119 unsigned long core_clk_rate;
120 unsigned long tv_pclk_rate;
121
122 u32 fifo_size[DISPC_MAX_NR_FIFOS];
123 /* maps which plane is using a fifo. fifo-id -> plane-id */
124 int fifo_assignment[DISPC_MAX_NR_FIFOS];
125
126 bool ctx_valid;
127 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
128
129 const struct dispc_features *feat;
130
131 bool is_enabled;
132
133 struct regmap *syscon_pol;
134 u32 syscon_pol_offset;
135
136 /* DISPC_CONTROL & DISPC_CONFIG lock*/
137 spinlock_t control_lock;
138} dispc;
139
140enum omap_color_component {
141 /* used for all color formats for OMAP3 and earlier
142 * and for RGB and Y color component on OMAP4
143 */
144 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
145 /* used for UV component for
146 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
147 * color formats on OMAP4
148 */
149 DISPC_COLOR_COMPONENT_UV = 1 << 1,
150};
151
152enum mgr_reg_fields {
153 DISPC_MGR_FLD_ENABLE,
154 DISPC_MGR_FLD_STNTFT,
155 DISPC_MGR_FLD_GO,
156 DISPC_MGR_FLD_TFTDATALINES,
157 DISPC_MGR_FLD_STALLMODE,
158 DISPC_MGR_FLD_TCKENABLE,
159 DISPC_MGR_FLD_TCKSELECTION,
160 DISPC_MGR_FLD_CPR,
161 DISPC_MGR_FLD_FIFOHANDCHECK,
162 /* used to maintain a count of the above fields */
163 DISPC_MGR_FLD_NUM,
164};
165
166struct dispc_reg_field {
167 u16 reg;
168 u8 high;
169 u8 low;
170};
171
172static const struct {
173 const char *name;
174 u32 vsync_irq;
175 u32 framedone_irq;
176 u32 sync_lost_irq;
177 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
178} mgr_desc[] = {
179 [OMAP_DSS_CHANNEL_LCD] = {
180 .name = "LCD",
181 .vsync_irq = DISPC_IRQ_VSYNC,
182 .framedone_irq = DISPC_IRQ_FRAMEDONE,
183 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
184 .reg_desc = {
185 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
186 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
187 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
188 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
189 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
190 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
191 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
192 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
193 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
194 },
195 },
196 [OMAP_DSS_CHANNEL_DIGIT] = {
197 .name = "DIGIT",
198 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
199 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
200 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
201 .reg_desc = {
202 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
203 [DISPC_MGR_FLD_STNTFT] = { },
204 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
205 [DISPC_MGR_FLD_TFTDATALINES] = { },
206 [DISPC_MGR_FLD_STALLMODE] = { },
207 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
208 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
209 [DISPC_MGR_FLD_CPR] = { },
210 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
211 },
212 },
213 [OMAP_DSS_CHANNEL_LCD2] = {
214 .name = "LCD2",
215 .vsync_irq = DISPC_IRQ_VSYNC2,
216 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
217 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
218 .reg_desc = {
219 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
220 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
221 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
222 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
223 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
224 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
225 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
226 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
227 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
228 },
229 },
230 [OMAP_DSS_CHANNEL_LCD3] = {
231 .name = "LCD3",
232 .vsync_irq = DISPC_IRQ_VSYNC3,
233 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
234 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
235 .reg_desc = {
236 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
237 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
238 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
239 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
240 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
241 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
242 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
243 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
244 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
245 },
246 },
247};
248
249struct color_conv_coef {
250 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
251 int full_range;
252};
253
254static unsigned long dispc_fclk_rate(void);
255static unsigned long dispc_core_clk_rate(void);
256static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
257static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
258
259static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
260static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
261
262static inline void dispc_write_reg(const u16 idx, u32 val)
263{
264 __raw_writel(val, dispc.base + idx);
265}
266
267static inline u32 dispc_read_reg(const u16 idx)
268{
269 return __raw_readl(dispc.base + idx);
270}
271
272static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
273{
274 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275 return REG_GET(rfld.reg, rfld.high, rfld.low);
276}
277
278static void mgr_fld_write(enum omap_channel channel,
279 enum mgr_reg_fields regfld, int val) {
280 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
281 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
282 unsigned long flags;
283
284 if (need_lock)
285 spin_lock_irqsave(&dispc.control_lock, flags);
286
287 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
288
289 if (need_lock)
290 spin_unlock_irqrestore(&dispc.control_lock, flags);
291}
292
293#define SR(reg) \
294 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
295#define RR(reg) \
296 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
297
298static void dispc_save_context(void)
299{
300 int i, j;
301
302 DSSDBG("dispc_save_context\n");
303
304 SR(IRQENABLE);
305 SR(CONTROL);
306 SR(CONFIG);
307 SR(LINE_NUMBER);
308 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
309 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
310 SR(GLOBAL_ALPHA);
311 if (dss_has_feature(FEAT_MGR_LCD2)) {
312 SR(CONTROL2);
313 SR(CONFIG2);
314 }
315 if (dss_has_feature(FEAT_MGR_LCD3)) {
316 SR(CONTROL3);
317 SR(CONFIG3);
318 }
319
320 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
321 SR(DEFAULT_COLOR(i));
322 SR(TRANS_COLOR(i));
323 SR(SIZE_MGR(i));
324 if (i == OMAP_DSS_CHANNEL_DIGIT)
325 continue;
326 SR(TIMING_H(i));
327 SR(TIMING_V(i));
328 SR(POL_FREQ(i));
329 SR(DIVISORo(i));
330
331 SR(DATA_CYCLE1(i));
332 SR(DATA_CYCLE2(i));
333 SR(DATA_CYCLE3(i));
334
335 if (dss_has_feature(FEAT_CPR)) {
336 SR(CPR_COEF_R(i));
337 SR(CPR_COEF_G(i));
338 SR(CPR_COEF_B(i));
339 }
340 }
341
342 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
343 SR(OVL_BA0(i));
344 SR(OVL_BA1(i));
345 SR(OVL_POSITION(i));
346 SR(OVL_SIZE(i));
347 SR(OVL_ATTRIBUTES(i));
348 SR(OVL_FIFO_THRESHOLD(i));
349 SR(OVL_ROW_INC(i));
350 SR(OVL_PIXEL_INC(i));
351 if (dss_has_feature(FEAT_PRELOAD))
352 SR(OVL_PRELOAD(i));
353 if (i == OMAP_DSS_GFX) {
354 SR(OVL_WINDOW_SKIP(i));
355 SR(OVL_TABLE_BA(i));
356 continue;
357 }
358 SR(OVL_FIR(i));
359 SR(OVL_PICTURE_SIZE(i));
360 SR(OVL_ACCU0(i));
361 SR(OVL_ACCU1(i));
362
363 for (j = 0; j < 8; j++)
364 SR(OVL_FIR_COEF_H(i, j));
365
366 for (j = 0; j < 8; j++)
367 SR(OVL_FIR_COEF_HV(i, j));
368
369 for (j = 0; j < 5; j++)
370 SR(OVL_CONV_COEF(i, j));
371
372 if (dss_has_feature(FEAT_FIR_COEF_V)) {
373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_V(i, j));
375 }
376
377 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
378 SR(OVL_BA0_UV(i));
379 SR(OVL_BA1_UV(i));
380 SR(OVL_FIR2(i));
381 SR(OVL_ACCU2_0(i));
382 SR(OVL_ACCU2_1(i));
383
384 for (j = 0; j < 8; j++)
385 SR(OVL_FIR_COEF_H2(i, j));
386
387 for (j = 0; j < 8; j++)
388 SR(OVL_FIR_COEF_HV2(i, j));
389
390 for (j = 0; j < 8; j++)
391 SR(OVL_FIR_COEF_V2(i, j));
392 }
393 if (dss_has_feature(FEAT_ATTR2))
394 SR(OVL_ATTRIBUTES2(i));
395 }
396
397 if (dss_has_feature(FEAT_CORE_CLK_DIV))
398 SR(DIVISOR);
399
400 dispc.ctx_valid = true;
401
402 DSSDBG("context saved\n");
403}
404
405static void dispc_restore_context(void)
406{
407 int i, j;
408
409 DSSDBG("dispc_restore_context\n");
410
411 if (!dispc.ctx_valid)
412 return;
413
414 /*RR(IRQENABLE);*/
415 /*RR(CONTROL);*/
416 RR(CONFIG);
417 RR(LINE_NUMBER);
418 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
419 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
420 RR(GLOBAL_ALPHA);
421 if (dss_has_feature(FEAT_MGR_LCD2))
422 RR(CONFIG2);
423 if (dss_has_feature(FEAT_MGR_LCD3))
424 RR(CONFIG3);
425
426 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
427 RR(DEFAULT_COLOR(i));
428 RR(TRANS_COLOR(i));
429 RR(SIZE_MGR(i));
430 if (i == OMAP_DSS_CHANNEL_DIGIT)
431 continue;
432 RR(TIMING_H(i));
433 RR(TIMING_V(i));
434 RR(POL_FREQ(i));
435 RR(DIVISORo(i));
436
437 RR(DATA_CYCLE1(i));
438 RR(DATA_CYCLE2(i));
439 RR(DATA_CYCLE3(i));
440
441 if (dss_has_feature(FEAT_CPR)) {
442 RR(CPR_COEF_R(i));
443 RR(CPR_COEF_G(i));
444 RR(CPR_COEF_B(i));
445 }
446 }
447
448 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
449 RR(OVL_BA0(i));
450 RR(OVL_BA1(i));
451 RR(OVL_POSITION(i));
452 RR(OVL_SIZE(i));
453 RR(OVL_ATTRIBUTES(i));
454 RR(OVL_FIFO_THRESHOLD(i));
455 RR(OVL_ROW_INC(i));
456 RR(OVL_PIXEL_INC(i));
457 if (dss_has_feature(FEAT_PRELOAD))
458 RR(OVL_PRELOAD(i));
459 if (i == OMAP_DSS_GFX) {
460 RR(OVL_WINDOW_SKIP(i));
461 RR(OVL_TABLE_BA(i));
462 continue;
463 }
464 RR(OVL_FIR(i));
465 RR(OVL_PICTURE_SIZE(i));
466 RR(OVL_ACCU0(i));
467 RR(OVL_ACCU1(i));
468
469 for (j = 0; j < 8; j++)
470 RR(OVL_FIR_COEF_H(i, j));
471
472 for (j = 0; j < 8; j++)
473 RR(OVL_FIR_COEF_HV(i, j));
474
475 for (j = 0; j < 5; j++)
476 RR(OVL_CONV_COEF(i, j));
477
478 if (dss_has_feature(FEAT_FIR_COEF_V)) {
479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_V(i, j));
481 }
482
483 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
484 RR(OVL_BA0_UV(i));
485 RR(OVL_BA1_UV(i));
486 RR(OVL_FIR2(i));
487 RR(OVL_ACCU2_0(i));
488 RR(OVL_ACCU2_1(i));
489
490 for (j = 0; j < 8; j++)
491 RR(OVL_FIR_COEF_H2(i, j));
492
493 for (j = 0; j < 8; j++)
494 RR(OVL_FIR_COEF_HV2(i, j));
495
496 for (j = 0; j < 8; j++)
497 RR(OVL_FIR_COEF_V2(i, j));
498 }
499 if (dss_has_feature(FEAT_ATTR2))
500 RR(OVL_ATTRIBUTES2(i));
501 }
502
503 if (dss_has_feature(FEAT_CORE_CLK_DIV))
504 RR(DIVISOR);
505
506 /* enable last, because LCD & DIGIT enable are here */
507 RR(CONTROL);
508 if (dss_has_feature(FEAT_MGR_LCD2))
509 RR(CONTROL2);
510 if (dss_has_feature(FEAT_MGR_LCD3))
511 RR(CONTROL3);
512 /* clear spurious SYNC_LOST_DIGIT interrupts */
513 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
514
515 /*
516 * enable last so IRQs won't trigger before
517 * the context is fully restored
518 */
519 RR(IRQENABLE);
520
521 DSSDBG("context restored\n");
522}
523
524#undef SR
525#undef RR
526
527int dispc_runtime_get(void)
528{
529 int r;
530
531 DSSDBG("dispc_runtime_get\n");
532
533 r = pm_runtime_get_sync(&dispc.pdev->dev);
534 WARN_ON(r < 0);
535 return r < 0 ? r : 0;
536}
537EXPORT_SYMBOL(dispc_runtime_get);
538
539void dispc_runtime_put(void)
540{
541 int r;
542
543 DSSDBG("dispc_runtime_put\n");
544
545 r = pm_runtime_put_sync(&dispc.pdev->dev);
546 WARN_ON(r < 0 && r != -ENOSYS);
547}
548EXPORT_SYMBOL(dispc_runtime_put);
549
550u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
551{
552 return mgr_desc[channel].vsync_irq;
553}
554EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
555
556u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
557{
558 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
559 return 0;
560
561 return mgr_desc[channel].framedone_irq;
562}
563EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
564
565u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
566{
567 return mgr_desc[channel].sync_lost_irq;
568}
569EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
570
571u32 dispc_wb_get_framedone_irq(void)
572{
573 return DISPC_IRQ_FRAMEDONEWB;
574}
575
576bool dispc_mgr_go_busy(enum omap_channel channel)
577{
578 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
579}
580EXPORT_SYMBOL(dispc_mgr_go_busy);
581
582void dispc_mgr_go(enum omap_channel channel)
583{
584 WARN_ON(!dispc_mgr_is_enabled(channel));
585 WARN_ON(dispc_mgr_go_busy(channel));
586
587 DSSDBG("GO %s\n", mgr_desc[channel].name);
588
589 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
590}
591EXPORT_SYMBOL(dispc_mgr_go);
592
593bool dispc_wb_go_busy(void)
594{
595 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
596}
597
598void dispc_wb_go(void)
599{
600 enum omap_plane plane = OMAP_DSS_WB;
601 bool enable, go;
602
603 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
604
605 if (!enable)
606 return;
607
608 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
609 if (go) {
610 DSSERR("GO bit not down for WB\n");
611 return;
612 }
613
614 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
615}
616
617static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
618{
619 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
620}
621
622static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
623{
624 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
625}
626
627static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
628{
629 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
630}
631
632static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
633{
634 BUG_ON(plane == OMAP_DSS_GFX);
635
636 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
637}
638
639static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
640 u32 value)
641{
642 BUG_ON(plane == OMAP_DSS_GFX);
643
644 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
645}
646
647static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
648{
649 BUG_ON(plane == OMAP_DSS_GFX);
650
651 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
652}
653
654static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
655 int fir_vinc, int five_taps,
656 enum omap_color_component color_comp)
657{
658 const struct dispc_coef *h_coef, *v_coef;
659 int i;
660
661 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
662 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
663
664 for (i = 0; i < 8; i++) {
665 u32 h, hv;
666
667 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
668 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
669 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
670 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
671 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
672 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
673 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
674 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
675
676 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
677 dispc_ovl_write_firh_reg(plane, i, h);
678 dispc_ovl_write_firhv_reg(plane, i, hv);
679 } else {
680 dispc_ovl_write_firh2_reg(plane, i, h);
681 dispc_ovl_write_firhv2_reg(plane, i, hv);
682 }
683
684 }
685
686 if (five_taps) {
687 for (i = 0; i < 8; i++) {
688 u32 v;
689 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
690 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
691 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
692 dispc_ovl_write_firv_reg(plane, i, v);
693 else
694 dispc_ovl_write_firv2_reg(plane, i, v);
695 }
696 }
697}
698
699
700static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
701 const struct color_conv_coef *ct)
702{
703#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
704
705 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
706 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
707 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
709 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
710
711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
712
713#undef CVAL
714}
715
716static void dispc_setup_color_conv_coef(void)
717{
718 int i;
719 int num_ovl = dss_feat_get_num_ovls();
720 const struct color_conv_coef ctbl_bt601_5_ovl = {
721 /* YUV -> RGB */
722 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
723 };
724 const struct color_conv_coef ctbl_bt601_5_wb = {
725 /* RGB -> YUV */
726 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
727 };
728
729 for (i = 1; i < num_ovl; i++)
730 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
731
732 if (dispc.feat->has_writeback)
733 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
734}
735
736static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
737{
738 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
739}
740
741static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
742{
743 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
744}
745
746static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
747{
748 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
749}
750
751static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
752{
753 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
754}
755
756static void dispc_ovl_set_pos(enum omap_plane plane,
757 enum omap_overlay_caps caps, int x, int y)
758{
759 u32 val;
760
761 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
762 return;
763
764 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
765
766 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
767}
768
769static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
770 int height)
771{
772 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
773
774 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
775 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
776 else
777 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
778}
779
780static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
781 int height)
782{
783 u32 val;
784
785 BUG_ON(plane == OMAP_DSS_GFX);
786
787 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
788
789 if (plane == OMAP_DSS_WB)
790 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
791 else
792 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
793}
794
795static void dispc_ovl_set_zorder(enum omap_plane plane,
796 enum omap_overlay_caps caps, u8 zorder)
797{
798 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
799 return;
800
801 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
802}
803
804static void dispc_ovl_enable_zorder_planes(void)
805{
806 int i;
807
808 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
809 return;
810
811 for (i = 0; i < dss_feat_get_num_ovls(); i++)
812 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
813}
814
815static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
816 enum omap_overlay_caps caps, bool enable)
817{
818 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
819 return;
820
821 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
822}
823
824static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
825 enum omap_overlay_caps caps, u8 global_alpha)
826{
827 static const unsigned shifts[] = { 0, 8, 16, 24, };
828 int shift;
829
830 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
831 return;
832
833 shift = shifts[plane];
834 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
835}
836
837static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
838{
839 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
840}
841
842static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
843{
844 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
845}
846
847static void dispc_ovl_set_color_mode(enum omap_plane plane,
848 enum omap_color_mode color_mode)
849{
850 u32 m = 0;
851 if (plane != OMAP_DSS_GFX) {
852 switch (color_mode) {
853 case OMAP_DSS_COLOR_NV12:
854 m = 0x0; break;
855 case OMAP_DSS_COLOR_RGBX16:
856 m = 0x1; break;
857 case OMAP_DSS_COLOR_RGBA16:
858 m = 0x2; break;
859 case OMAP_DSS_COLOR_RGB12U:
860 m = 0x4; break;
861 case OMAP_DSS_COLOR_ARGB16:
862 m = 0x5; break;
863 case OMAP_DSS_COLOR_RGB16:
864 m = 0x6; break;
865 case OMAP_DSS_COLOR_ARGB16_1555:
866 m = 0x7; break;
867 case OMAP_DSS_COLOR_RGB24U:
868 m = 0x8; break;
869 case OMAP_DSS_COLOR_RGB24P:
870 m = 0x9; break;
871 case OMAP_DSS_COLOR_YUV2:
872 m = 0xa; break;
873 case OMAP_DSS_COLOR_UYVY:
874 m = 0xb; break;
875 case OMAP_DSS_COLOR_ARGB32:
876 m = 0xc; break;
877 case OMAP_DSS_COLOR_RGBA32:
878 m = 0xd; break;
879 case OMAP_DSS_COLOR_RGBX32:
880 m = 0xe; break;
881 case OMAP_DSS_COLOR_XRGB16_1555:
882 m = 0xf; break;
883 default:
884 BUG(); return;
885 }
886 } else {
887 switch (color_mode) {
888 case OMAP_DSS_COLOR_CLUT1:
889 m = 0x0; break;
890 case OMAP_DSS_COLOR_CLUT2:
891 m = 0x1; break;
892 case OMAP_DSS_COLOR_CLUT4:
893 m = 0x2; break;
894 case OMAP_DSS_COLOR_CLUT8:
895 m = 0x3; break;
896 case OMAP_DSS_COLOR_RGB12U:
897 m = 0x4; break;
898 case OMAP_DSS_COLOR_ARGB16:
899 m = 0x5; break;
900 case OMAP_DSS_COLOR_RGB16:
901 m = 0x6; break;
902 case OMAP_DSS_COLOR_ARGB16_1555:
903 m = 0x7; break;
904 case OMAP_DSS_COLOR_RGB24U:
905 m = 0x8; break;
906 case OMAP_DSS_COLOR_RGB24P:
907 m = 0x9; break;
908 case OMAP_DSS_COLOR_RGBX16:
909 m = 0xa; break;
910 case OMAP_DSS_COLOR_RGBA16:
911 m = 0xb; break;
912 case OMAP_DSS_COLOR_ARGB32:
913 m = 0xc; break;
914 case OMAP_DSS_COLOR_RGBA32:
915 m = 0xd; break;
916 case OMAP_DSS_COLOR_RGBX32:
917 m = 0xe; break;
918 case OMAP_DSS_COLOR_XRGB16_1555:
919 m = 0xf; break;
920 default:
921 BUG(); return;
922 }
923 }
924
925 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
926}
927
928static void dispc_ovl_configure_burst_type(enum omap_plane plane,
929 enum omap_dss_rotation_type rotation_type)
930{
931 if (dss_has_feature(FEAT_BURST_2D) == 0)
932 return;
933
934 if (rotation_type == OMAP_DSS_ROT_TILER)
935 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
936 else
937 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
938}
939
940void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
941{
942 int shift;
943 u32 val;
944 int chan = 0, chan2 = 0;
945
946 switch (plane) {
947 case OMAP_DSS_GFX:
948 shift = 8;
949 break;
950 case OMAP_DSS_VIDEO1:
951 case OMAP_DSS_VIDEO2:
952 case OMAP_DSS_VIDEO3:
953 shift = 16;
954 break;
955 default:
956 BUG();
957 return;
958 }
959
960 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
961 if (dss_has_feature(FEAT_MGR_LCD2)) {
962 switch (channel) {
963 case OMAP_DSS_CHANNEL_LCD:
964 chan = 0;
965 chan2 = 0;
966 break;
967 case OMAP_DSS_CHANNEL_DIGIT:
968 chan = 1;
969 chan2 = 0;
970 break;
971 case OMAP_DSS_CHANNEL_LCD2:
972 chan = 0;
973 chan2 = 1;
974 break;
975 case OMAP_DSS_CHANNEL_LCD3:
976 if (dss_has_feature(FEAT_MGR_LCD3)) {
977 chan = 0;
978 chan2 = 2;
979 } else {
980 BUG();
981 return;
982 }
983 break;
984 case OMAP_DSS_CHANNEL_WB:
985 chan = 0;
986 chan2 = 3;
987 break;
988 default:
989 BUG();
990 return;
991 }
992
993 val = FLD_MOD(val, chan, shift, shift);
994 val = FLD_MOD(val, chan2, 31, 30);
995 } else {
996 val = FLD_MOD(val, channel, shift, shift);
997 }
998 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
999}
1000EXPORT_SYMBOL(dispc_ovl_set_channel_out);
1001
1002static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
1003{
1004 int shift;
1005 u32 val;
1006
1007 switch (plane) {
1008 case OMAP_DSS_GFX:
1009 shift = 8;
1010 break;
1011 case OMAP_DSS_VIDEO1:
1012 case OMAP_DSS_VIDEO2:
1013 case OMAP_DSS_VIDEO3:
1014 shift = 16;
1015 break;
1016 default:
1017 BUG();
1018 return 0;
1019 }
1020
1021 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1022
1023 if (FLD_GET(val, shift, shift) == 1)
1024 return OMAP_DSS_CHANNEL_DIGIT;
1025
1026 if (!dss_has_feature(FEAT_MGR_LCD2))
1027 return OMAP_DSS_CHANNEL_LCD;
1028
1029 switch (FLD_GET(val, 31, 30)) {
1030 case 0:
1031 default:
1032 return OMAP_DSS_CHANNEL_LCD;
1033 case 1:
1034 return OMAP_DSS_CHANNEL_LCD2;
1035 case 2:
1036 return OMAP_DSS_CHANNEL_LCD3;
1037 case 3:
1038 return OMAP_DSS_CHANNEL_WB;
1039 }
1040}
1041
1042void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1043{
1044 enum omap_plane plane = OMAP_DSS_WB;
1045
1046 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1047}
1048
1049static void dispc_ovl_set_burst_size(enum omap_plane plane,
1050 enum omap_burst_size burst_size)
1051{
1052 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1053 int shift;
1054
1055 shift = shifts[plane];
1056 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1057}
1058
1059static void dispc_configure_burst_sizes(void)
1060{
1061 int i;
1062 const int burst_size = BURST_SIZE_X8;
1063
1064 /* Configure burst size always to maximum size */
1065 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1066 dispc_ovl_set_burst_size(i, burst_size);
1067 if (dispc.feat->has_writeback)
1068 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1069}
1070
1071static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1072{
1073 unsigned unit = dss_feat_get_burst_size_unit();
1074 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1075 return unit * 8;
1076}
1077
1078void dispc_enable_gamma_table(bool enable)
1079{
1080 /*
1081 * This is partially implemented to support only disabling of
1082 * the gamma table.
1083 */
1084 if (enable) {
1085 DSSWARN("Gamma table enabling for TV not yet supported");
1086 return;
1087 }
1088
1089 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1090}
1091
1092static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1093{
1094 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1095 return;
1096
1097 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1098}
1099
1100static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1101 const struct omap_dss_cpr_coefs *coefs)
1102{
1103 u32 coef_r, coef_g, coef_b;
1104
1105 if (!dss_mgr_is_lcd(channel))
1106 return;
1107
1108 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1109 FLD_VAL(coefs->rb, 9, 0);
1110 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1111 FLD_VAL(coefs->gb, 9, 0);
1112 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1113 FLD_VAL(coefs->bb, 9, 0);
1114
1115 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1116 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1117 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1118}
1119
1120static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1121{
1122 u32 val;
1123
1124 BUG_ON(plane == OMAP_DSS_GFX);
1125
1126 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1127 val = FLD_MOD(val, enable, 9, 9);
1128 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1129}
1130
1131static void dispc_ovl_enable_replication(enum omap_plane plane,
1132 enum omap_overlay_caps caps, bool enable)
1133{
1134 static const unsigned shifts[] = { 5, 10, 10, 10 };
1135 int shift;
1136
1137 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1138 return;
1139
1140 shift = shifts[plane];
1141 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1142}
1143
1144static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1145 u16 height)
1146{
1147 u32 val;
1148
1149 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1150 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1151
1152 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1153}
1154
1155static void dispc_init_fifos(void)
1156{
1157 u32 size;
1158 int fifo;
1159 u8 start, end;
1160 u32 unit;
1161 int i;
1162
1163 unit = dss_feat_get_buffer_size_unit();
1164
1165 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1166
1167 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1168 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1169 size *= unit;
1170 dispc.fifo_size[fifo] = size;
1171
1172 /*
1173 * By default fifos are mapped directly to overlays, fifo 0 to
1174 * ovl 0, fifo 1 to ovl 1, etc.
1175 */
1176 dispc.fifo_assignment[fifo] = fifo;
1177 }
1178
1179 /*
1180 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1181 * causes problems with certain use cases, like using the tiler in 2D
1182 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1183 * giving GFX plane a larger fifo. WB but should work fine with a
1184 * smaller fifo.
1185 */
1186 if (dispc.feat->gfx_fifo_workaround) {
1187 u32 v;
1188
1189 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1190
1191 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1192 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1193 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1194 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1195
1196 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1197
1198 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1199 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1200 }
1201
1202 /*
1203 * Setup default fifo thresholds.
1204 */
1205 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1206 u32 low, high;
1207 const bool use_fifomerge = false;
1208 const bool manual_update = false;
1209
1210 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1211 use_fifomerge, manual_update);
1212
1213 dispc_ovl_set_fifo_threshold(i, low, high);
1214 }
1215
1216 if (dispc.feat->has_writeback) {
1217 u32 low, high;
1218 const bool use_fifomerge = false;
1219 const bool manual_update = false;
1220
1221 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1222 use_fifomerge, manual_update);
1223
1224 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1225 }
1226}
1227
1228static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1229{
1230 int fifo;
1231 u32 size = 0;
1232
1233 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1234 if (dispc.fifo_assignment[fifo] == plane)
1235 size += dispc.fifo_size[fifo];
1236 }
1237
1238 return size;
1239}
1240
1241void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1242{
1243 u8 hi_start, hi_end, lo_start, lo_end;
1244 u32 unit;
1245
1246 unit = dss_feat_get_buffer_size_unit();
1247
1248 WARN_ON(low % unit != 0);
1249 WARN_ON(high % unit != 0);
1250
1251 low /= unit;
1252 high /= unit;
1253
1254 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1255 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1256
1257 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1258 plane,
1259 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1260 lo_start, lo_end) * unit,
1261 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1262 hi_start, hi_end) * unit,
1263 low * unit, high * unit);
1264
1265 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1266 FLD_VAL(high, hi_start, hi_end) |
1267 FLD_VAL(low, lo_start, lo_end));
1268
1269 /*
1270 * configure the preload to the pipeline's high threhold, if HT it's too
1271 * large for the preload field, set the threshold to the maximum value
1272 * that can be held by the preload register
1273 */
1274 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1275 plane != OMAP_DSS_WB)
1276 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1277}
1278
1279void dispc_enable_fifomerge(bool enable)
1280{
1281 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1282 WARN_ON(enable);
1283 return;
1284 }
1285
1286 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1287 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1288}
1289
1290void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1291 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1292 bool manual_update)
1293{
1294 /*
1295 * All sizes are in bytes. Both the buffer and burst are made of
1296 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1297 */
1298
1299 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1300 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1301 int i;
1302
1303 burst_size = dispc_ovl_get_burst_size(plane);
1304 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1305
1306 if (use_fifomerge) {
1307 total_fifo_size = 0;
1308 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1309 total_fifo_size += dispc_ovl_get_fifo_size(i);
1310 } else {
1311 total_fifo_size = ovl_fifo_size;
1312 }
1313
1314 /*
1315 * We use the same low threshold for both fifomerge and non-fifomerge
1316 * cases, but for fifomerge we calculate the high threshold using the
1317 * combined fifo size
1318 */
1319
1320 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1321 *fifo_low = ovl_fifo_size - burst_size * 2;
1322 *fifo_high = total_fifo_size - burst_size;
1323 } else if (plane == OMAP_DSS_WB) {
1324 /*
1325 * Most optimal configuration for writeback is to push out data
1326 * to the interconnect the moment writeback pushes enough pixels
1327 * in the FIFO to form a burst
1328 */
1329 *fifo_low = 0;
1330 *fifo_high = burst_size;
1331 } else {
1332 *fifo_low = ovl_fifo_size - burst_size;
1333 *fifo_high = total_fifo_size - buf_unit;
1334 }
1335}
1336
1337static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1338{
1339 int bit;
1340
1341 if (plane == OMAP_DSS_GFX)
1342 bit = 14;
1343 else
1344 bit = 23;
1345
1346 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1347}
1348
1349static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1350 int low, int high)
1351{
1352 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1353 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1354}
1355
1356static void dispc_init_mflag(void)
1357{
1358 int i;
1359
1360 /*
1361 * HACK: NV12 color format and MFLAG seem to have problems working
1362 * together: using two displays, and having an NV12 overlay on one of
1363 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1364 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1365 * remove the errors, but there doesn't seem to be a clear logic on
1366 * which values work and which not.
1367 *
1368 * As a work-around, set force MFLAG to always on.
1369 */
1370 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1371 (1 << 0) | /* MFLAG_CTRL = force always on */
1372 (0 << 2)); /* MFLAG_START = disable */
1373
1374 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1375 u32 size = dispc_ovl_get_fifo_size(i);
1376 u32 unit = dss_feat_get_buffer_size_unit();
1377 u32 low, high;
1378
1379 dispc_ovl_set_mflag(i, true);
1380
1381 /*
1382 * Simulation team suggests below thesholds:
1383 * HT = fifosize * 5 / 8;
1384 * LT = fifosize * 4 / 8;
1385 */
1386
1387 low = size * 4 / 8 / unit;
1388 high = size * 5 / 8 / unit;
1389
1390 dispc_ovl_set_mflag_threshold(i, low, high);
1391 }
1392
1393 if (dispc.feat->has_writeback) {
1394 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1395 u32 unit = dss_feat_get_buffer_size_unit();
1396 u32 low, high;
1397
1398 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1399
1400 /*
1401 * Simulation team suggests below thesholds:
1402 * HT = fifosize * 5 / 8;
1403 * LT = fifosize * 4 / 8;
1404 */
1405
1406 low = size * 4 / 8 / unit;
1407 high = size * 5 / 8 / unit;
1408
1409 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1410 }
1411}
1412
1413static void dispc_ovl_set_fir(enum omap_plane plane,
1414 int hinc, int vinc,
1415 enum omap_color_component color_comp)
1416{
1417 u32 val;
1418
1419 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1420 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1421
1422 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1423 &hinc_start, &hinc_end);
1424 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1425 &vinc_start, &vinc_end);
1426 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1427 FLD_VAL(hinc, hinc_start, hinc_end);
1428
1429 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1430 } else {
1431 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1432 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1433 }
1434}
1435
1436static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1437{
1438 u32 val;
1439 u8 hor_start, hor_end, vert_start, vert_end;
1440
1441 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1442 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1443
1444 val = FLD_VAL(vaccu, vert_start, vert_end) |
1445 FLD_VAL(haccu, hor_start, hor_end);
1446
1447 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1448}
1449
1450static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1451{
1452 u32 val;
1453 u8 hor_start, hor_end, vert_start, vert_end;
1454
1455 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1456 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1457
1458 val = FLD_VAL(vaccu, vert_start, vert_end) |
1459 FLD_VAL(haccu, hor_start, hor_end);
1460
1461 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1462}
1463
1464static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1465 int vaccu)
1466{
1467 u32 val;
1468
1469 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1470 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1471}
1472
1473static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1474 int vaccu)
1475{
1476 u32 val;
1477
1478 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1479 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1480}
1481
1482static void dispc_ovl_set_scale_param(enum omap_plane plane,
1483 u16 orig_width, u16 orig_height,
1484 u16 out_width, u16 out_height,
1485 bool five_taps, u8 rotation,
1486 enum omap_color_component color_comp)
1487{
1488 int fir_hinc, fir_vinc;
1489
1490 fir_hinc = 1024 * orig_width / out_width;
1491 fir_vinc = 1024 * orig_height / out_height;
1492
1493 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1494 color_comp);
1495 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1496}
1497
1498static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1499 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1500 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1501{
1502 int h_accu2_0, h_accu2_1;
1503 int v_accu2_0, v_accu2_1;
1504 int chroma_hinc, chroma_vinc;
1505 int idx;
1506
1507 struct accu {
1508 s8 h0_m, h0_n;
1509 s8 h1_m, h1_n;
1510 s8 v0_m, v0_n;
1511 s8 v1_m, v1_n;
1512 };
1513
1514 const struct accu *accu_table;
1515 const struct accu *accu_val;
1516
1517 static const struct accu accu_nv12[4] = {
1518 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1519 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1520 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1521 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1522 };
1523
1524 static const struct accu accu_nv12_ilace[4] = {
1525 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1526 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1527 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1528 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1529 };
1530
1531 static const struct accu accu_yuv[4] = {
1532 { 0, 1, 0, 1, 0, 1, 0, 1 },
1533 { 0, 1, 0, 1, 0, 1, 0, 1 },
1534 { -1, 1, 0, 1, 0, 1, 0, 1 },
1535 { 0, 1, 0, 1, -1, 1, 0, 1 },
1536 };
1537
1538 switch (rotation) {
1539 case OMAP_DSS_ROT_0:
1540 idx = 0;
1541 break;
1542 case OMAP_DSS_ROT_90:
1543 idx = 1;
1544 break;
1545 case OMAP_DSS_ROT_180:
1546 idx = 2;
1547 break;
1548 case OMAP_DSS_ROT_270:
1549 idx = 3;
1550 break;
1551 default:
1552 BUG();
1553 return;
1554 }
1555
1556 switch (color_mode) {
1557 case OMAP_DSS_COLOR_NV12:
1558 if (ilace)
1559 accu_table = accu_nv12_ilace;
1560 else
1561 accu_table = accu_nv12;
1562 break;
1563 case OMAP_DSS_COLOR_YUV2:
1564 case OMAP_DSS_COLOR_UYVY:
1565 accu_table = accu_yuv;
1566 break;
1567 default:
1568 BUG();
1569 return;
1570 }
1571
1572 accu_val = &accu_table[idx];
1573
1574 chroma_hinc = 1024 * orig_width / out_width;
1575 chroma_vinc = 1024 * orig_height / out_height;
1576
1577 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1578 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1579 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1580 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1581
1582 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1583 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1584}
1585
1586static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1587 u16 orig_width, u16 orig_height,
1588 u16 out_width, u16 out_height,
1589 bool ilace, bool five_taps,
1590 bool fieldmode, enum omap_color_mode color_mode,
1591 u8 rotation)
1592{
1593 int accu0 = 0;
1594 int accu1 = 0;
1595 u32 l;
1596
1597 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1598 out_width, out_height, five_taps,
1599 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1600 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1601
1602 /* RESIZEENABLE and VERTICALTAPS */
1603 l &= ~((0x3 << 5) | (0x1 << 21));
1604 l |= (orig_width != out_width) ? (1 << 5) : 0;
1605 l |= (orig_height != out_height) ? (1 << 6) : 0;
1606 l |= five_taps ? (1 << 21) : 0;
1607
1608 /* VRESIZECONF and HRESIZECONF */
1609 if (dss_has_feature(FEAT_RESIZECONF)) {
1610 l &= ~(0x3 << 7);
1611 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1612 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1613 }
1614
1615 /* LINEBUFFERSPLIT */
1616 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1617 l &= ~(0x1 << 22);
1618 l |= five_taps ? (1 << 22) : 0;
1619 }
1620
1621 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1622
1623 /*
1624 * field 0 = even field = bottom field
1625 * field 1 = odd field = top field
1626 */
1627 if (ilace && !fieldmode) {
1628 accu1 = 0;
1629 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1630 if (accu0 >= 1024/2) {
1631 accu1 = 1024/2;
1632 accu0 -= accu1;
1633 }
1634 }
1635
1636 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1637 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1638}
1639
1640static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1641 u16 orig_width, u16 orig_height,
1642 u16 out_width, u16 out_height,
1643 bool ilace, bool five_taps,
1644 bool fieldmode, enum omap_color_mode color_mode,
1645 u8 rotation)
1646{
1647 int scale_x = out_width != orig_width;
1648 int scale_y = out_height != orig_height;
1649 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
1650
1651 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1652 return;
1653 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1654 color_mode != OMAP_DSS_COLOR_UYVY &&
1655 color_mode != OMAP_DSS_COLOR_NV12)) {
1656 /* reset chroma resampling for RGB formats */
1657 if (plane != OMAP_DSS_WB)
1658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1659 return;
1660 }
1661
1662 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1663 out_height, ilace, color_mode, rotation);
1664
1665 switch (color_mode) {
1666 case OMAP_DSS_COLOR_NV12:
1667 if (chroma_upscale) {
1668 /* UV is subsampled by 2 horizontally and vertically */
1669 orig_height >>= 1;
1670 orig_width >>= 1;
1671 } else {
1672 /* UV is downsampled by 2 horizontally and vertically */
1673 orig_height <<= 1;
1674 orig_width <<= 1;
1675 }
1676
1677 break;
1678 case OMAP_DSS_COLOR_YUV2:
1679 case OMAP_DSS_COLOR_UYVY:
1680 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1681 if (rotation == OMAP_DSS_ROT_0 ||
1682 rotation == OMAP_DSS_ROT_180) {
1683 if (chroma_upscale)
1684 /* UV is subsampled by 2 horizontally */
1685 orig_width >>= 1;
1686 else
1687 /* UV is downsampled by 2 horizontally */
1688 orig_width <<= 1;
1689 }
1690
1691 /* must use FIR for YUV422 if rotated */
1692 if (rotation != OMAP_DSS_ROT_0)
1693 scale_x = scale_y = true;
1694
1695 break;
1696 default:
1697 BUG();
1698 return;
1699 }
1700
1701 if (out_width != orig_width)
1702 scale_x = true;
1703 if (out_height != orig_height)
1704 scale_y = true;
1705
1706 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1707 out_width, out_height, five_taps,
1708 rotation, DISPC_COLOR_COMPONENT_UV);
1709
1710 if (plane != OMAP_DSS_WB)
1711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1712 (scale_x || scale_y) ? 1 : 0, 8, 8);
1713
1714 /* set H scaling */
1715 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1716 /* set V scaling */
1717 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1718}
1719
1720static void dispc_ovl_set_scaling(enum omap_plane plane,
1721 u16 orig_width, u16 orig_height,
1722 u16 out_width, u16 out_height,
1723 bool ilace, bool five_taps,
1724 bool fieldmode, enum omap_color_mode color_mode,
1725 u8 rotation)
1726{
1727 BUG_ON(plane == OMAP_DSS_GFX);
1728
1729 dispc_ovl_set_scaling_common(plane,
1730 orig_width, orig_height,
1731 out_width, out_height,
1732 ilace, five_taps,
1733 fieldmode, color_mode,
1734 rotation);
1735
1736 dispc_ovl_set_scaling_uv(plane,
1737 orig_width, orig_height,
1738 out_width, out_height,
1739 ilace, five_taps,
1740 fieldmode, color_mode,
1741 rotation);
1742}
1743
1744static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1745 enum omap_dss_rotation_type rotation_type,
1746 bool mirroring, enum omap_color_mode color_mode)
1747{
1748 bool row_repeat = false;
1749 int vidrot = 0;
1750
1751 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1752 color_mode == OMAP_DSS_COLOR_UYVY) {
1753
1754 if (mirroring) {
1755 switch (rotation) {
1756 case OMAP_DSS_ROT_0:
1757 vidrot = 2;
1758 break;
1759 case OMAP_DSS_ROT_90:
1760 vidrot = 1;
1761 break;
1762 case OMAP_DSS_ROT_180:
1763 vidrot = 0;
1764 break;
1765 case OMAP_DSS_ROT_270:
1766 vidrot = 3;
1767 break;
1768 }
1769 } else {
1770 switch (rotation) {
1771 case OMAP_DSS_ROT_0:
1772 vidrot = 0;
1773 break;
1774 case OMAP_DSS_ROT_90:
1775 vidrot = 1;
1776 break;
1777 case OMAP_DSS_ROT_180:
1778 vidrot = 2;
1779 break;
1780 case OMAP_DSS_ROT_270:
1781 vidrot = 3;
1782 break;
1783 }
1784 }
1785
1786 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1787 row_repeat = true;
1788 else
1789 row_repeat = false;
1790 }
1791
1792 /*
1793 * OMAP4/5 Errata i631:
1794 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1795 * rows beyond the framebuffer, which may cause OCP error.
1796 */
1797 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1798 rotation_type != OMAP_DSS_ROT_TILER)
1799 vidrot = 1;
1800
1801 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1802 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1803 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1804 row_repeat ? 1 : 0, 18, 18);
1805
1806 if (color_mode == OMAP_DSS_COLOR_NV12) {
1807 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1808 (rotation == OMAP_DSS_ROT_0 ||
1809 rotation == OMAP_DSS_ROT_180);
1810 /* DOUBLESTRIDE */
1811 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1812 }
1813
1814}
1815
1816static int color_mode_to_bpp(enum omap_color_mode color_mode)
1817{
1818 switch (color_mode) {
1819 case OMAP_DSS_COLOR_CLUT1:
1820 return 1;
1821 case OMAP_DSS_COLOR_CLUT2:
1822 return 2;
1823 case OMAP_DSS_COLOR_CLUT4:
1824 return 4;
1825 case OMAP_DSS_COLOR_CLUT8:
1826 case OMAP_DSS_COLOR_NV12:
1827 return 8;
1828 case OMAP_DSS_COLOR_RGB12U:
1829 case OMAP_DSS_COLOR_RGB16:
1830 case OMAP_DSS_COLOR_ARGB16:
1831 case OMAP_DSS_COLOR_YUV2:
1832 case OMAP_DSS_COLOR_UYVY:
1833 case OMAP_DSS_COLOR_RGBA16:
1834 case OMAP_DSS_COLOR_RGBX16:
1835 case OMAP_DSS_COLOR_ARGB16_1555:
1836 case OMAP_DSS_COLOR_XRGB16_1555:
1837 return 16;
1838 case OMAP_DSS_COLOR_RGB24P:
1839 return 24;
1840 case OMAP_DSS_COLOR_RGB24U:
1841 case OMAP_DSS_COLOR_ARGB32:
1842 case OMAP_DSS_COLOR_RGBA32:
1843 case OMAP_DSS_COLOR_RGBX32:
1844 return 32;
1845 default:
1846 BUG();
1847 return 0;
1848 }
1849}
1850
1851static s32 pixinc(int pixels, u8 ps)
1852{
1853 if (pixels == 1)
1854 return 1;
1855 else if (pixels > 1)
1856 return 1 + (pixels - 1) * ps;
1857 else if (pixels < 0)
1858 return 1 - (-pixels + 1) * ps;
1859 else
1860 BUG();
1861 return 0;
1862}
1863
1864static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1865 u16 screen_width,
1866 u16 width, u16 height,
1867 enum omap_color_mode color_mode, bool fieldmode,
1868 unsigned int field_offset,
1869 unsigned *offset0, unsigned *offset1,
1870 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1871{
1872 u8 ps;
1873
1874 /* FIXME CLUT formats */
1875 switch (color_mode) {
1876 case OMAP_DSS_COLOR_CLUT1:
1877 case OMAP_DSS_COLOR_CLUT2:
1878 case OMAP_DSS_COLOR_CLUT4:
1879 case OMAP_DSS_COLOR_CLUT8:
1880 BUG();
1881 return;
1882 case OMAP_DSS_COLOR_YUV2:
1883 case OMAP_DSS_COLOR_UYVY:
1884 ps = 4;
1885 break;
1886 default:
1887 ps = color_mode_to_bpp(color_mode) / 8;
1888 break;
1889 }
1890
1891 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1892 width, height);
1893
1894 /*
1895 * field 0 = even field = bottom field
1896 * field 1 = odd field = top field
1897 */
1898 switch (rotation + mirror * 4) {
1899 case OMAP_DSS_ROT_0:
1900 case OMAP_DSS_ROT_180:
1901 /*
1902 * If the pixel format is YUV or UYVY divide the width
1903 * of the image by 2 for 0 and 180 degree rotation.
1904 */
1905 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1906 color_mode == OMAP_DSS_COLOR_UYVY)
1907 width = width >> 1;
1908 case OMAP_DSS_ROT_90:
1909 case OMAP_DSS_ROT_270:
1910 *offset1 = 0;
1911 if (field_offset)
1912 *offset0 = field_offset * screen_width * ps;
1913 else
1914 *offset0 = 0;
1915
1916 *row_inc = pixinc(1 +
1917 (y_predecim * screen_width - x_predecim * width) +
1918 (fieldmode ? screen_width : 0), ps);
1919 *pix_inc = pixinc(x_predecim, ps);
1920 break;
1921
1922 case OMAP_DSS_ROT_0 + 4:
1923 case OMAP_DSS_ROT_180 + 4:
1924 /* If the pixel format is YUV or UYVY divide the width
1925 * of the image by 2 for 0 degree and 180 degree
1926 */
1927 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1928 color_mode == OMAP_DSS_COLOR_UYVY)
1929 width = width >> 1;
1930 case OMAP_DSS_ROT_90 + 4:
1931 case OMAP_DSS_ROT_270 + 4:
1932 *offset1 = 0;
1933 if (field_offset)
1934 *offset0 = field_offset * screen_width * ps;
1935 else
1936 *offset0 = 0;
1937 *row_inc = pixinc(1 -
1938 (y_predecim * screen_width + x_predecim * width) -
1939 (fieldmode ? screen_width : 0), ps);
1940 *pix_inc = pixinc(x_predecim, ps);
1941 break;
1942
1943 default:
1944 BUG();
1945 return;
1946 }
1947}
1948
1949static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1950 u16 screen_width,
1951 u16 width, u16 height,
1952 enum omap_color_mode color_mode, bool fieldmode,
1953 unsigned int field_offset,
1954 unsigned *offset0, unsigned *offset1,
1955 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1956{
1957 u8 ps;
1958 u16 fbw, fbh;
1959
1960 /* FIXME CLUT formats */
1961 switch (color_mode) {
1962 case OMAP_DSS_COLOR_CLUT1:
1963 case OMAP_DSS_COLOR_CLUT2:
1964 case OMAP_DSS_COLOR_CLUT4:
1965 case OMAP_DSS_COLOR_CLUT8:
1966 BUG();
1967 return;
1968 default:
1969 ps = color_mode_to_bpp(color_mode) / 8;
1970 break;
1971 }
1972
1973 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1974 width, height);
1975
1976 /* width & height are overlay sizes, convert to fb sizes */
1977
1978 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1979 fbw = width;
1980 fbh = height;
1981 } else {
1982 fbw = height;
1983 fbh = width;
1984 }
1985
1986 /*
1987 * field 0 = even field = bottom field
1988 * field 1 = odd field = top field
1989 */
1990 switch (rotation + mirror * 4) {
1991 case OMAP_DSS_ROT_0:
1992 *offset1 = 0;
1993 if (field_offset)
1994 *offset0 = *offset1 + field_offset * screen_width * ps;
1995 else
1996 *offset0 = *offset1;
1997 *row_inc = pixinc(1 +
1998 (y_predecim * screen_width - fbw * x_predecim) +
1999 (fieldmode ? screen_width : 0), ps);
2000 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2001 color_mode == OMAP_DSS_COLOR_UYVY)
2002 *pix_inc = pixinc(x_predecim, 2 * ps);
2003 else
2004 *pix_inc = pixinc(x_predecim, ps);
2005 break;
2006 case OMAP_DSS_ROT_90:
2007 *offset1 = screen_width * (fbh - 1) * ps;
2008 if (field_offset)
2009 *offset0 = *offset1 + field_offset * ps;
2010 else
2011 *offset0 = *offset1;
2012 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
2013 y_predecim + (fieldmode ? 1 : 0), ps);
2014 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2015 break;
2016 case OMAP_DSS_ROT_180:
2017 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2018 if (field_offset)
2019 *offset0 = *offset1 - field_offset * screen_width * ps;
2020 else
2021 *offset0 = *offset1;
2022 *row_inc = pixinc(-1 -
2023 (y_predecim * screen_width - fbw * x_predecim) -
2024 (fieldmode ? screen_width : 0), ps);
2025 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2026 color_mode == OMAP_DSS_COLOR_UYVY)
2027 *pix_inc = pixinc(-x_predecim, 2 * ps);
2028 else
2029 *pix_inc = pixinc(-x_predecim, ps);
2030 break;
2031 case OMAP_DSS_ROT_270:
2032 *offset1 = (fbw - 1) * ps;
2033 if (field_offset)
2034 *offset0 = *offset1 - field_offset * ps;
2035 else
2036 *offset0 = *offset1;
2037 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
2038 y_predecim - (fieldmode ? 1 : 0), ps);
2039 *pix_inc = pixinc(x_predecim * screen_width, ps);
2040 break;
2041
2042 /* mirroring */
2043 case OMAP_DSS_ROT_0 + 4:
2044 *offset1 = (fbw - 1) * ps;
2045 if (field_offset)
2046 *offset0 = *offset1 + field_offset * screen_width * ps;
2047 else
2048 *offset0 = *offset1;
2049 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
2050 (fieldmode ? screen_width : 0),
2051 ps);
2052 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2053 color_mode == OMAP_DSS_COLOR_UYVY)
2054 *pix_inc = pixinc(-x_predecim, 2 * ps);
2055 else
2056 *pix_inc = pixinc(-x_predecim, ps);
2057 break;
2058
2059 case OMAP_DSS_ROT_90 + 4:
2060 *offset1 = 0;
2061 if (field_offset)
2062 *offset0 = *offset1 + field_offset * ps;
2063 else
2064 *offset0 = *offset1;
2065 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2066 y_predecim + (fieldmode ? 1 : 0),
2067 ps);
2068 *pix_inc = pixinc(x_predecim * screen_width, ps);
2069 break;
2070
2071 case OMAP_DSS_ROT_180 + 4:
2072 *offset1 = screen_width * (fbh - 1) * ps;
2073 if (field_offset)
2074 *offset0 = *offset1 - field_offset * screen_width * ps;
2075 else
2076 *offset0 = *offset1;
2077 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2078 (fieldmode ? screen_width : 0),
2079 ps);
2080 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2081 color_mode == OMAP_DSS_COLOR_UYVY)
2082 *pix_inc = pixinc(x_predecim, 2 * ps);
2083 else
2084 *pix_inc = pixinc(x_predecim, ps);
2085 break;
2086
2087 case OMAP_DSS_ROT_270 + 4:
2088 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2089 if (field_offset)
2090 *offset0 = *offset1 - field_offset * ps;
2091 else
2092 *offset0 = *offset1;
2093 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2094 y_predecim - (fieldmode ? 1 : 0),
2095 ps);
2096 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2097 break;
2098
2099 default:
2100 BUG();
2101 return;
2102 }
2103}
2104
2105static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2106 enum omap_color_mode color_mode, bool fieldmode,
2107 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2108 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2109{
2110 u8 ps;
2111
2112 switch (color_mode) {
2113 case OMAP_DSS_COLOR_CLUT1:
2114 case OMAP_DSS_COLOR_CLUT2:
2115 case OMAP_DSS_COLOR_CLUT4:
2116 case OMAP_DSS_COLOR_CLUT8:
2117 BUG();
2118 return;
2119 default:
2120 ps = color_mode_to_bpp(color_mode) / 8;
2121 break;
2122 }
2123
2124 DSSDBG("scrw %d, width %d\n", screen_width, width);
2125
2126 /*
2127 * field 0 = even field = bottom field
2128 * field 1 = odd field = top field
2129 */
2130 *offset1 = 0;
2131 if (field_offset)
2132 *offset0 = *offset1 + field_offset * screen_width * ps;
2133 else
2134 *offset0 = *offset1;
2135 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2136 (fieldmode ? screen_width : 0), ps);
2137 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2138 color_mode == OMAP_DSS_COLOR_UYVY)
2139 *pix_inc = pixinc(x_predecim, 2 * ps);
2140 else
2141 *pix_inc = pixinc(x_predecim, ps);
2142}
2143
2144/*
2145 * This function is used to avoid synclosts in OMAP3, because of some
2146 * undocumented horizontal position and timing related limitations.
2147 */
2148static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2149 const struct omap_video_timings *t, u16 pos_x,
2150 u16 width, u16 height, u16 out_width, u16 out_height,
2151 bool five_taps)
2152{
2153 const int ds = DIV_ROUND_UP(height, out_height);
2154 unsigned long nonactive;
2155 static const u8 limits[3] = { 8, 10, 20 };
2156 u64 val, blank;
2157 int i;
2158
2159 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2160
2161 i = 0;
2162 if (out_height < height)
2163 i++;
2164 if (out_width < width)
2165 i++;
2166 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2167 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2168 if (blank <= limits[i])
2169 return -EINVAL;
2170
2171 /* FIXME add checks for 3-tap filter once the limitations are known */
2172 if (!five_taps)
2173 return 0;
2174
2175 /*
2176 * Pixel data should be prepared before visible display point starts.
2177 * So, atleast DS-2 lines must have already been fetched by DISPC
2178 * during nonactive - pos_x period.
2179 */
2180 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2181 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2182 val, max(0, ds - 2) * width);
2183 if (val < max(0, ds - 2) * width)
2184 return -EINVAL;
2185
2186 /*
2187 * All lines need to be refilled during the nonactive period of which
2188 * only one line can be loaded during the active period. So, atleast
2189 * DS - 1 lines should be loaded during nonactive period.
2190 */
2191 val = div_u64((u64)nonactive * lclk, pclk);
2192 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2193 val, max(0, ds - 1) * width);
2194 if (val < max(0, ds - 1) * width)
2195 return -EINVAL;
2196
2197 return 0;
2198}
2199
2200static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2201 const struct omap_video_timings *mgr_timings, u16 width,
2202 u16 height, u16 out_width, u16 out_height,
2203 enum omap_color_mode color_mode)
2204{
2205 u32 core_clk = 0;
2206 u64 tmp;
2207
2208 if (height <= out_height && width <= out_width)
2209 return (unsigned long) pclk;
2210
2211 if (height > out_height) {
2212 unsigned int ppl = mgr_timings->x_res;
2213
2214 tmp = (u64)pclk * height * out_width;
2215 do_div(tmp, 2 * out_height * ppl);
2216 core_clk = tmp;
2217
2218 if (height > 2 * out_height) {
2219 if (ppl == out_width)
2220 return 0;
2221
2222 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2223 do_div(tmp, 2 * out_height * (ppl - out_width));
2224 core_clk = max_t(u32, core_clk, tmp);
2225 }
2226 }
2227
2228 if (width > out_width) {
2229 tmp = (u64)pclk * width;
2230 do_div(tmp, out_width);
2231 core_clk = max_t(u32, core_clk, tmp);
2232
2233 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2234 core_clk <<= 1;
2235 }
2236
2237 return core_clk;
2238}
2239
2240static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2241 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2242{
2243 if (height > out_height && width > out_width)
2244 return pclk * 4;
2245 else
2246 return pclk * 2;
2247}
2248
2249static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2250 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2251{
2252 unsigned int hf, vf;
2253
2254 /*
2255 * FIXME how to determine the 'A' factor
2256 * for the no downscaling case ?
2257 */
2258
2259 if (width > 3 * out_width)
2260 hf = 4;
2261 else if (width > 2 * out_width)
2262 hf = 3;
2263 else if (width > out_width)
2264 hf = 2;
2265 else
2266 hf = 1;
2267 if (height > out_height)
2268 vf = 2;
2269 else
2270 vf = 1;
2271
2272 return pclk * vf * hf;
2273}
2274
2275static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2276 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2277{
2278 /*
2279 * If the overlay/writeback is in mem to mem mode, there are no
2280 * downscaling limitations with respect to pixel clock, return 1 as
2281 * required core clock to represent that we have sufficient enough
2282 * core clock to do maximum downscaling
2283 */
2284 if (mem_to_mem)
2285 return 1;
2286
2287 if (width > out_width)
2288 return DIV_ROUND_UP(pclk, out_width) * width;
2289 else
2290 return pclk;
2291}
2292
2293static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2294 const struct omap_video_timings *mgr_timings,
2295 u16 width, u16 height, u16 out_width, u16 out_height,
2296 enum omap_color_mode color_mode, bool *five_taps,
2297 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2298 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2299{
2300 int error;
2301 u16 in_width, in_height;
2302 int min_factor = min(*decim_x, *decim_y);
2303 const int maxsinglelinewidth =
2304 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2305
2306 *five_taps = false;
2307
2308 do {
2309 in_height = height / *decim_y;
2310 in_width = width / *decim_x;
2311 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2312 in_height, out_width, out_height, mem_to_mem);
2313 error = (in_width > maxsinglelinewidth || !*core_clk ||
2314 *core_clk > dispc_core_clk_rate());
2315 if (error) {
2316 if (*decim_x == *decim_y) {
2317 *decim_x = min_factor;
2318 ++*decim_y;
2319 } else {
2320 swap(*decim_x, *decim_y);
2321 if (*decim_x < *decim_y)
2322 ++*decim_x;
2323 }
2324 }
2325 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2326
2327 if (error) {
2328 DSSERR("failed to find scaling settings\n");
2329 return -EINVAL;
2330 }
2331
2332 if (in_width > maxsinglelinewidth) {
2333 DSSERR("Cannot scale max input width exceeded");
2334 return -EINVAL;
2335 }
2336 return 0;
2337}
2338
2339static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2340 const struct omap_video_timings *mgr_timings,
2341 u16 width, u16 height, u16 out_width, u16 out_height,
2342 enum omap_color_mode color_mode, bool *five_taps,
2343 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2344 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2345{
2346 int error;
2347 u16 in_width, in_height;
2348 const int maxsinglelinewidth =
2349 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2350
2351 do {
2352 in_height = height / *decim_y;
2353 in_width = width / *decim_x;
2354 *five_taps = in_height > out_height;
2355
2356 if (in_width > maxsinglelinewidth)
2357 if (in_height > out_height &&
2358 in_height < out_height * 2)
2359 *five_taps = false;
2360again:
2361 if (*five_taps)
2362 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2363 in_width, in_height, out_width,
2364 out_height, color_mode);
2365 else
2366 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2367 in_height, out_width, out_height,
2368 mem_to_mem);
2369
2370 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2371 pos_x, in_width, in_height, out_width,
2372 out_height, *five_taps);
2373 if (error && *five_taps) {
2374 *five_taps = false;
2375 goto again;
2376 }
2377
2378 error = (error || in_width > maxsinglelinewidth * 2 ||
2379 (in_width > maxsinglelinewidth && *five_taps) ||
2380 !*core_clk || *core_clk > dispc_core_clk_rate());
2381
2382 if (!error) {
2383 /* verify that we're inside the limits of scaler */
2384 if (in_width / 4 > out_width)
2385 error = 1;
2386
2387 if (*five_taps) {
2388 if (in_height / 4 > out_height)
2389 error = 1;
2390 } else {
2391 if (in_height / 2 > out_height)
2392 error = 1;
2393 }
2394 }
2395
2396 if (error)
2397 ++*decim_y;
2398 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2399
2400 if (error) {
2401 DSSERR("failed to find scaling settings\n");
2402 return -EINVAL;
2403 }
2404
2405 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2406 in_height, out_width, out_height, *five_taps)) {
2407 DSSERR("horizontal timing too tight\n");
2408 return -EINVAL;
2409 }
2410
2411 if (in_width > (maxsinglelinewidth * 2)) {
2412 DSSERR("Cannot setup scaling");
2413 DSSERR("width exceeds maximum width possible");
2414 return -EINVAL;
2415 }
2416
2417 if (in_width > maxsinglelinewidth && *five_taps) {
2418 DSSERR("cannot setup scaling with five taps");
2419 return -EINVAL;
2420 }
2421 return 0;
2422}
2423
2424static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2425 const struct omap_video_timings *mgr_timings,
2426 u16 width, u16 height, u16 out_width, u16 out_height,
2427 enum omap_color_mode color_mode, bool *five_taps,
2428 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2429 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2430{
2431 u16 in_width, in_width_max;
2432 int decim_x_min = *decim_x;
2433 u16 in_height = height / *decim_y;
2434 const int maxsinglelinewidth =
2435 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2436 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2437
2438 if (mem_to_mem) {
2439 in_width_max = out_width * maxdownscale;
2440 } else {
2441 in_width_max = dispc_core_clk_rate() /
2442 DIV_ROUND_UP(pclk, out_width);
2443 }
2444
2445 *decim_x = DIV_ROUND_UP(width, in_width_max);
2446
2447 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2448 if (*decim_x > *x_predecim)
2449 return -EINVAL;
2450
2451 do {
2452 in_width = width / *decim_x;
2453 } while (*decim_x <= *x_predecim &&
2454 in_width > maxsinglelinewidth && ++*decim_x);
2455
2456 if (in_width > maxsinglelinewidth) {
2457 DSSERR("Cannot scale width exceeds max line width");
2458 return -EINVAL;
2459 }
2460
2461 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2462 out_width, out_height, mem_to_mem);
2463 return 0;
2464}
2465
2466#define DIV_FRAC(dividend, divisor) \
2467 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2468
2469static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2470 enum omap_overlay_caps caps,
2471 const struct omap_video_timings *mgr_timings,
2472 u16 width, u16 height, u16 out_width, u16 out_height,
2473 enum omap_color_mode color_mode, bool *five_taps,
2474 int *x_predecim, int *y_predecim, u16 pos_x,
2475 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2476{
2477 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2478 const int max_decim_limit = 16;
2479 unsigned long core_clk = 0;
2480 int decim_x, decim_y, ret;
2481
2482 if (width == out_width && height == out_height)
2483 return 0;
2484
2485 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2486 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2487 return -EINVAL;
2488 }
2489
2490 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2491 return -EINVAL;
2492
2493 if (mem_to_mem) {
2494 *x_predecim = *y_predecim = 1;
2495 } else {
2496 *x_predecim = max_decim_limit;
2497 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2498 dss_has_feature(FEAT_BURST_2D)) ?
2499 2 : max_decim_limit;
2500 }
2501
2502 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2503 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2504 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2505 color_mode == OMAP_DSS_COLOR_CLUT8) {
2506 *x_predecim = 1;
2507 *y_predecim = 1;
2508 *five_taps = false;
2509 return 0;
2510 }
2511
2512 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2513 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2514
2515 if (decim_x > *x_predecim || out_width > width * 8)
2516 return -EINVAL;
2517
2518 if (decim_y > *y_predecim || out_height > height * 8)
2519 return -EINVAL;
2520
2521 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2522 out_width, out_height, color_mode, five_taps,
2523 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2524 mem_to_mem);
2525 if (ret)
2526 return ret;
2527
2528 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2529 width, height,
2530 out_width, out_height,
2531 out_width / width, DIV_FRAC(out_width, width),
2532 out_height / height, DIV_FRAC(out_height, height),
2533
2534 decim_x, decim_y,
2535 width / decim_x, height / decim_y,
2536 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2537 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2538
2539 *five_taps ? 5 : 3,
2540 core_clk, dispc_core_clk_rate());
2541
2542 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2543 DSSERR("failed to set up scaling, "
2544 "required core clk rate = %lu Hz, "
2545 "current core clk rate = %lu Hz\n",
2546 core_clk, dispc_core_clk_rate());
2547 return -EINVAL;
2548 }
2549
2550 *x_predecim = decim_x;
2551 *y_predecim = decim_y;
2552 return 0;
2553}
2554
2555int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2556 const struct omap_overlay_info *oi,
2557 const struct omap_video_timings *timings,
2558 int *x_predecim, int *y_predecim)
2559{
2560 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2561 bool five_taps = true;
2562 bool fieldmode = false;
2563 u16 in_height = oi->height;
2564 u16 in_width = oi->width;
2565 bool ilace = timings->interlace;
2566 u16 out_width, out_height;
2567 int pos_x = oi->pos_x;
2568 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2569 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2570
2571 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2572 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2573
2574 if (ilace && oi->height == out_height)
2575 fieldmode = true;
2576
2577 if (ilace) {
2578 if (fieldmode)
2579 in_height /= 2;
2580 out_height /= 2;
2581
2582 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2583 in_height, out_height);
2584 }
2585
2586 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2587 return -EINVAL;
2588
2589 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2590 in_height, out_width, out_height, oi->color_mode,
2591 &five_taps, x_predecim, y_predecim, pos_x,
2592 oi->rotation_type, false);
2593}
2594EXPORT_SYMBOL(dispc_ovl_check);
2595
2596static int dispc_ovl_setup_common(enum omap_plane plane,
2597 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2598 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2599 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2600 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2601 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2602 bool replication, const struct omap_video_timings *mgr_timings,
2603 bool mem_to_mem)
2604{
2605 bool five_taps = true;
2606 bool fieldmode = false;
2607 int r, cconv = 0;
2608 unsigned offset0, offset1;
2609 s32 row_inc;
2610 s32 pix_inc;
2611 u16 frame_width, frame_height;
2612 unsigned int field_offset = 0;
2613 u16 in_height = height;
2614 u16 in_width = width;
2615 int x_predecim = 1, y_predecim = 1;
2616 bool ilace = mgr_timings->interlace;
2617 unsigned long pclk = dispc_plane_pclk_rate(plane);
2618 unsigned long lclk = dispc_plane_lclk_rate(plane);
2619
2620 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2621 return -EINVAL;
2622
2623 switch (color_mode) {
2624 case OMAP_DSS_COLOR_YUV2:
2625 case OMAP_DSS_COLOR_UYVY:
2626 case OMAP_DSS_COLOR_NV12:
2627 if (in_width & 1) {
2628 DSSERR("input width %d is not even for YUV format\n",
2629 in_width);
2630 return -EINVAL;
2631 }
2632 break;
2633
2634 default:
2635 break;
2636 }
2637
2638 out_width = out_width == 0 ? width : out_width;
2639 out_height = out_height == 0 ? height : out_height;
2640
2641 if (ilace && height == out_height)
2642 fieldmode = true;
2643
2644 if (ilace) {
2645 if (fieldmode)
2646 in_height /= 2;
2647 pos_y /= 2;
2648 out_height /= 2;
2649
2650 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2651 "out_height %d\n", in_height, pos_y,
2652 out_height);
2653 }
2654
2655 if (!dss_feat_color_mode_supported(plane, color_mode))
2656 return -EINVAL;
2657
2658 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2659 in_height, out_width, out_height, color_mode,
2660 &five_taps, &x_predecim, &y_predecim, pos_x,
2661 rotation_type, mem_to_mem);
2662 if (r)
2663 return r;
2664
2665 in_width = in_width / x_predecim;
2666 in_height = in_height / y_predecim;
2667
2668 if (x_predecim > 1 || y_predecim > 1)
2669 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2670 x_predecim, y_predecim, in_width, in_height);
2671
2672 switch (color_mode) {
2673 case OMAP_DSS_COLOR_YUV2:
2674 case OMAP_DSS_COLOR_UYVY:
2675 case OMAP_DSS_COLOR_NV12:
2676 if (in_width & 1) {
2677 DSSDBG("predecimated input width is not even for YUV format\n");
2678 DSSDBG("adjusting input width %d -> %d\n",
2679 in_width, in_width & ~1);
2680
2681 in_width &= ~1;
2682 }
2683 break;
2684
2685 default:
2686 break;
2687 }
2688
2689 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2690 color_mode == OMAP_DSS_COLOR_UYVY ||
2691 color_mode == OMAP_DSS_COLOR_NV12)
2692 cconv = 1;
2693
2694 if (ilace && !fieldmode) {
2695 /*
2696 * when downscaling the bottom field may have to start several
2697 * source lines below the top field. Unfortunately ACCUI
2698 * registers will only hold the fractional part of the offset
2699 * so the integer part must be added to the base address of the
2700 * bottom field.
2701 */
2702 if (!in_height || in_height == out_height)
2703 field_offset = 0;
2704 else
2705 field_offset = in_height / out_height / 2;
2706 }
2707
2708 /* Fields are independent but interleaved in memory. */
2709 if (fieldmode)
2710 field_offset = 1;
2711
2712 offset0 = 0;
2713 offset1 = 0;
2714 row_inc = 0;
2715 pix_inc = 0;
2716
2717 if (plane == OMAP_DSS_WB) {
2718 frame_width = out_width;
2719 frame_height = out_height;
2720 } else {
2721 frame_width = in_width;
2722 frame_height = height;
2723 }
2724
2725 if (rotation_type == OMAP_DSS_ROT_TILER)
2726 calc_tiler_rotation_offset(screen_width, frame_width,
2727 color_mode, fieldmode, field_offset,
2728 &offset0, &offset1, &row_inc, &pix_inc,
2729 x_predecim, y_predecim);
2730 else if (rotation_type == OMAP_DSS_ROT_DMA)
2731 calc_dma_rotation_offset(rotation, mirror, screen_width,
2732 frame_width, frame_height,
2733 color_mode, fieldmode, field_offset,
2734 &offset0, &offset1, &row_inc, &pix_inc,
2735 x_predecim, y_predecim);
2736 else
2737 calc_vrfb_rotation_offset(rotation, mirror,
2738 screen_width, frame_width, frame_height,
2739 color_mode, fieldmode, field_offset,
2740 &offset0, &offset1, &row_inc, &pix_inc,
2741 x_predecim, y_predecim);
2742
2743 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2744 offset0, offset1, row_inc, pix_inc);
2745
2746 dispc_ovl_set_color_mode(plane, color_mode);
2747
2748 dispc_ovl_configure_burst_type(plane, rotation_type);
2749
2750 dispc_ovl_set_ba0(plane, paddr + offset0);
2751 dispc_ovl_set_ba1(plane, paddr + offset1);
2752
2753 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2754 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2755 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2756 }
2757
2758 if (dispc.feat->last_pixel_inc_missing)
2759 row_inc += pix_inc - 1;
2760
2761 dispc_ovl_set_row_inc(plane, row_inc);
2762 dispc_ovl_set_pix_inc(plane, pix_inc);
2763
2764 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2765 in_height, out_width, out_height);
2766
2767 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2768
2769 dispc_ovl_set_input_size(plane, in_width, in_height);
2770
2771 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2772 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2773 out_height, ilace, five_taps, fieldmode,
2774 color_mode, rotation);
2775 dispc_ovl_set_output_size(plane, out_width, out_height);
2776 dispc_ovl_set_vid_color_conv(plane, cconv);
2777 }
2778
2779 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2780 color_mode);
2781
2782 dispc_ovl_set_zorder(plane, caps, zorder);
2783 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2784 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2785
2786 dispc_ovl_enable_replication(plane, caps, replication);
2787
2788 return 0;
2789}
2790
2791int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2792 bool replication, const struct omap_video_timings *mgr_timings,
2793 bool mem_to_mem)
2794{
2795 int r;
2796 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2797 enum omap_channel channel;
2798
2799 channel = dispc_ovl_get_channel_out(plane);
2800
2801 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2802 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2803 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2804 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2805 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2806
2807 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2808 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2809 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2810 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2811 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2812
2813 return r;
2814}
2815EXPORT_SYMBOL(dispc_ovl_setup);
2816
2817int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2818 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
2819{
2820 int r;
2821 u32 l;
2822 enum omap_plane plane = OMAP_DSS_WB;
2823 const int pos_x = 0, pos_y = 0;
2824 const u8 zorder = 0, global_alpha = 0;
2825 const bool replication = false;
2826 bool truncation;
2827 int in_width = mgr_timings->x_res;
2828 int in_height = mgr_timings->y_res;
2829 enum omap_overlay_caps caps =
2830 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2831
2832 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2833 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2834 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2835 wi->mirror);
2836
2837 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2838 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2839 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2840 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2841 replication, mgr_timings, mem_to_mem);
2842
2843 switch (wi->color_mode) {
2844 case OMAP_DSS_COLOR_RGB16:
2845 case OMAP_DSS_COLOR_RGB24P:
2846 case OMAP_DSS_COLOR_ARGB16:
2847 case OMAP_DSS_COLOR_RGBA16:
2848 case OMAP_DSS_COLOR_RGB12U:
2849 case OMAP_DSS_COLOR_ARGB16_1555:
2850 case OMAP_DSS_COLOR_XRGB16_1555:
2851 case OMAP_DSS_COLOR_RGBX16:
2852 truncation = true;
2853 break;
2854 default:
2855 truncation = false;
2856 break;
2857 }
2858
2859 /* setup extra DISPC_WB_ATTRIBUTES */
2860 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2861 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2862 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2863 if (mem_to_mem)
2864 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2865 else
2866 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2867 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
2868
2869 if (mem_to_mem) {
2870 /* WBDELAYCOUNT */
2871 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2872 } else {
2873 int wbdelay;
2874
2875 wbdelay = min(mgr_timings->vfp + mgr_timings->vsw +
2876 mgr_timings->vbp, 255);
2877
2878 /* WBDELAYCOUNT */
2879 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2880 }
2881
2882 return r;
2883}
2884
2885int dispc_ovl_enable(enum omap_plane plane, bool enable)
2886{
2887 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2888
2889 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2890
2891 return 0;
2892}
2893EXPORT_SYMBOL(dispc_ovl_enable);
2894
2895bool dispc_ovl_enabled(enum omap_plane plane)
2896{
2897 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2898}
2899EXPORT_SYMBOL(dispc_ovl_enabled);
2900
2901void dispc_mgr_enable(enum omap_channel channel, bool enable)
2902{
2903 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2904 /* flush posted write */
2905 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2906}
2907EXPORT_SYMBOL(dispc_mgr_enable);
2908
2909bool dispc_mgr_is_enabled(enum omap_channel channel)
2910{
2911 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2912}
2913EXPORT_SYMBOL(dispc_mgr_is_enabled);
2914
2915void dispc_wb_enable(bool enable)
2916{
2917 dispc_ovl_enable(OMAP_DSS_WB, enable);
2918}
2919
2920bool dispc_wb_is_enabled(void)
2921{
2922 return dispc_ovl_enabled(OMAP_DSS_WB);
2923}
2924
2925static void dispc_lcd_enable_signal_polarity(bool act_high)
2926{
2927 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2928 return;
2929
2930 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2931}
2932
2933void dispc_lcd_enable_signal(bool enable)
2934{
2935 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2936 return;
2937
2938 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2939}
2940
2941void dispc_pck_free_enable(bool enable)
2942{
2943 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2944 return;
2945
2946 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2947}
2948
2949static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2950{
2951 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2952}
2953
2954
2955static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2956{
2957 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2958}
2959
2960static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2961{
2962 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2963}
2964
2965
2966static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2967{
2968 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2969}
2970
2971static void dispc_mgr_set_trans_key(enum omap_channel ch,
2972 enum omap_dss_trans_key_type type,
2973 u32 trans_key)
2974{
2975 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2976
2977 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2978}
2979
2980static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2981{
2982 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2983}
2984
2985static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2986 bool enable)
2987{
2988 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2989 return;
2990
2991 if (ch == OMAP_DSS_CHANNEL_LCD)
2992 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2993 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2994 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2995}
2996
2997void dispc_mgr_setup(enum omap_channel channel,
2998 const struct omap_overlay_manager_info *info)
2999{
3000 dispc_mgr_set_default_color(channel, info->default_color);
3001 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
3002 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
3003 dispc_mgr_enable_alpha_fixed_zorder(channel,
3004 info->partial_alpha_enabled);
3005 if (dss_has_feature(FEAT_CPR)) {
3006 dispc_mgr_enable_cpr(channel, info->cpr_enable);
3007 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
3008 }
3009}
3010EXPORT_SYMBOL(dispc_mgr_setup);
3011
3012static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
3013{
3014 int code;
3015
3016 switch (data_lines) {
3017 case 12:
3018 code = 0;
3019 break;
3020 case 16:
3021 code = 1;
3022 break;
3023 case 18:
3024 code = 2;
3025 break;
3026 case 24:
3027 code = 3;
3028 break;
3029 default:
3030 BUG();
3031 return;
3032 }
3033
3034 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
3035}
3036
3037static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
3038{
3039 u32 l;
3040 int gpout0, gpout1;
3041
3042 switch (mode) {
3043 case DSS_IO_PAD_MODE_RESET:
3044 gpout0 = 0;
3045 gpout1 = 0;
3046 break;
3047 case DSS_IO_PAD_MODE_RFBI:
3048 gpout0 = 1;
3049 gpout1 = 0;
3050 break;
3051 case DSS_IO_PAD_MODE_BYPASS:
3052 gpout0 = 1;
3053 gpout1 = 1;
3054 break;
3055 default:
3056 BUG();
3057 return;
3058 }
3059
3060 l = dispc_read_reg(DISPC_CONTROL);
3061 l = FLD_MOD(l, gpout0, 15, 15);
3062 l = FLD_MOD(l, gpout1, 16, 16);
3063 dispc_write_reg(DISPC_CONTROL, l);
3064}
3065
3066static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
3067{
3068 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
3069}
3070
3071void dispc_mgr_set_lcd_config(enum omap_channel channel,
3072 const struct dss_lcd_mgr_config *config)
3073{
3074 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3075
3076 dispc_mgr_enable_stallmode(channel, config->stallmode);
3077 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3078
3079 dispc_mgr_set_clock_div(channel, &config->clock_info);
3080
3081 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3082
3083 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3084
3085 dispc_mgr_set_lcd_type_tft(channel);
3086}
3087EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
3088
3089static bool _dispc_mgr_size_ok(u16 width, u16 height)
3090{
3091 return width <= dispc.feat->mgr_width_max &&
3092 height <= dispc.feat->mgr_height_max;
3093}
3094
3095static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3096 int vsw, int vfp, int vbp)
3097{
3098 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3099 hfp < 1 || hfp > dispc.feat->hp_max ||
3100 hbp < 1 || hbp > dispc.feat->hp_max ||
3101 vsw < 1 || vsw > dispc.feat->sw_max ||
3102 vfp < 0 || vfp > dispc.feat->vp_max ||
3103 vbp < 0 || vbp > dispc.feat->vp_max)
3104 return false;
3105 return true;
3106}
3107
3108static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
3109 unsigned long pclk)
3110{
3111 if (dss_mgr_is_lcd(channel))
3112 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
3113 else
3114 return pclk <= dispc.feat->max_tv_pclk ? true : false;
3115}
3116
3117bool dispc_mgr_timings_ok(enum omap_channel channel,
3118 const struct omap_video_timings *timings)
3119{
3120 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
3121 return false;
3122
3123 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
3124 return false;
3125
3126 if (dss_mgr_is_lcd(channel)) {
3127 /* TODO: OMAP4+ supports interlace for LCD outputs */
3128 if (timings->interlace)
3129 return false;
3130
3131 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
3132 timings->hbp, timings->vsw, timings->vfp,
3133 timings->vbp))
3134 return false;
3135 }
3136
3137 return true;
3138}
3139
3140static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3141 int hfp, int hbp, int vsw, int vfp, int vbp,
3142 enum omap_dss_signal_level vsync_level,
3143 enum omap_dss_signal_level hsync_level,
3144 enum omap_dss_signal_edge data_pclk_edge,
3145 enum omap_dss_signal_level de_level,
3146 enum omap_dss_signal_edge sync_pclk_edge)
3147
3148{
3149 u32 timing_h, timing_v, l;
3150 bool onoff, rf, ipc, vs, hs, de;
3151
3152 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3153 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3154 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3155 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3156 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3157 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3158
3159 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3160 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3161
3162 switch (vsync_level) {
3163 case OMAPDSS_SIG_ACTIVE_LOW:
3164 vs = true;
3165 break;
3166 case OMAPDSS_SIG_ACTIVE_HIGH:
3167 vs = false;
3168 break;
3169 default:
3170 BUG();
3171 }
3172
3173 switch (hsync_level) {
3174 case OMAPDSS_SIG_ACTIVE_LOW:
3175 hs = true;
3176 break;
3177 case OMAPDSS_SIG_ACTIVE_HIGH:
3178 hs = false;
3179 break;
3180 default:
3181 BUG();
3182 }
3183
3184 switch (de_level) {
3185 case OMAPDSS_SIG_ACTIVE_LOW:
3186 de = true;
3187 break;
3188 case OMAPDSS_SIG_ACTIVE_HIGH:
3189 de = false;
3190 break;
3191 default:
3192 BUG();
3193 }
3194
3195 switch (data_pclk_edge) {
3196 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3197 ipc = false;
3198 break;
3199 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3200 ipc = true;
3201 break;
3202 default:
3203 BUG();
3204 }
3205
3206 /* always use the 'rf' setting */
3207 onoff = true;
3208
3209 switch (sync_pclk_edge) {
3210 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3211 rf = false;
3212 break;
3213 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3214 rf = true;
3215 break;
3216 default:
3217 BUG();
3218 }
3219
3220 l = FLD_VAL(onoff, 17, 17) |
3221 FLD_VAL(rf, 16, 16) |
3222 FLD_VAL(de, 15, 15) |
3223 FLD_VAL(ipc, 14, 14) |
3224 FLD_VAL(hs, 13, 13) |
3225 FLD_VAL(vs, 12, 12);
3226
3227 /* always set ALIGN bit when available */
3228 if (dispc.feat->supports_sync_align)
3229 l |= (1 << 18);
3230
3231 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3232
3233 if (dispc.syscon_pol) {
3234 const int shifts[] = {
3235 [OMAP_DSS_CHANNEL_LCD] = 0,
3236 [OMAP_DSS_CHANNEL_LCD2] = 1,
3237 [OMAP_DSS_CHANNEL_LCD3] = 2,
3238 };
3239
3240 u32 mask, val;
3241
3242 mask = (1 << 0) | (1 << 3) | (1 << 6);
3243 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3244
3245 mask <<= 16 + shifts[channel];
3246 val <<= 16 + shifts[channel];
3247
3248 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3249 mask, val);
3250 }
3251}
3252
3253/* change name to mode? */
3254void dispc_mgr_set_timings(enum omap_channel channel,
3255 const struct omap_video_timings *timings)
3256{
3257 unsigned xtot, ytot;
3258 unsigned long ht, vt;
3259 struct omap_video_timings t = *timings;
3260
3261 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3262
3263 if (!dispc_mgr_timings_ok(channel, &t)) {
3264 BUG();
3265 return;
3266 }
3267
3268 if (dss_mgr_is_lcd(channel)) {
3269 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3270 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3271 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3272
3273 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3274 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3275
3276 ht = timings->pixelclock / xtot;
3277 vt = timings->pixelclock / xtot / ytot;
3278
3279 DSSDBG("pck %u\n", timings->pixelclock);
3280 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3281 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3282 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3283 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3284 t.de_level, t.sync_pclk_edge);
3285
3286 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3287 } else {
3288 if (t.interlace)
3289 t.y_res /= 2;
3290 }
3291
3292 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3293}
3294EXPORT_SYMBOL(dispc_mgr_set_timings);
3295
3296static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3297 u16 pck_div)
3298{
3299 BUG_ON(lck_div < 1);
3300 BUG_ON(pck_div < 1);
3301
3302 dispc_write_reg(DISPC_DIVISORo(channel),
3303 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3304
3305 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3306 channel == OMAP_DSS_CHANNEL_LCD)
3307 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3308}
3309
3310static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3311 int *pck_div)
3312{
3313 u32 l;
3314 l = dispc_read_reg(DISPC_DIVISORo(channel));
3315 *lck_div = FLD_GET(l, 23, 16);
3316 *pck_div = FLD_GET(l, 7, 0);
3317}
3318
3319static unsigned long dispc_fclk_rate(void)
3320{
3321 struct dss_pll *pll;
3322 unsigned long r = 0;
3323
3324 switch (dss_get_dispc_clk_source()) {
3325 case OMAP_DSS_CLK_SRC_FCK:
3326 r = dss_get_dispc_clk_rate();
3327 break;
3328 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3329 pll = dss_pll_find("dsi0");
3330 if (!pll)
3331 pll = dss_pll_find("video0");
3332
3333 r = pll->cinfo.clkout[0];
3334 break;
3335 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3336 pll = dss_pll_find("dsi1");
3337 if (!pll)
3338 pll = dss_pll_find("video1");
3339
3340 r = pll->cinfo.clkout[0];
3341 break;
3342 default:
3343 BUG();
3344 return 0;
3345 }
3346
3347 return r;
3348}
3349
3350static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3351{
3352 struct dss_pll *pll;
3353 int lcd;
3354 unsigned long r;
3355 u32 l;
3356
3357 if (dss_mgr_is_lcd(channel)) {
3358 l = dispc_read_reg(DISPC_DIVISORo(channel));
3359
3360 lcd = FLD_GET(l, 23, 16);
3361
3362 switch (dss_get_lcd_clk_source(channel)) {
3363 case OMAP_DSS_CLK_SRC_FCK:
3364 r = dss_get_dispc_clk_rate();
3365 break;
3366 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3367 pll = dss_pll_find("dsi0");
3368 if (!pll)
3369 pll = dss_pll_find("video0");
3370
3371 r = pll->cinfo.clkout[0];
3372 break;
3373 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3374 pll = dss_pll_find("dsi1");
3375 if (!pll)
3376 pll = dss_pll_find("video1");
3377
3378 r = pll->cinfo.clkout[0];
3379 break;
3380 default:
3381 BUG();
3382 return 0;
3383 }
3384
3385 return r / lcd;
3386 } else {
3387 return dispc_fclk_rate();
3388 }
3389}
3390
3391static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3392{
3393 unsigned long r;
3394
3395 if (dss_mgr_is_lcd(channel)) {
3396 int pcd;
3397 u32 l;
3398
3399 l = dispc_read_reg(DISPC_DIVISORo(channel));
3400
3401 pcd = FLD_GET(l, 7, 0);
3402
3403 r = dispc_mgr_lclk_rate(channel);
3404
3405 return r / pcd;
3406 } else {
3407 return dispc.tv_pclk_rate;
3408 }
3409}
3410
3411void dispc_set_tv_pclk(unsigned long pclk)
3412{
3413 dispc.tv_pclk_rate = pclk;
3414}
3415
3416static unsigned long dispc_core_clk_rate(void)
3417{
3418 return dispc.core_clk_rate;
3419}
3420
3421static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3422{
3423 enum omap_channel channel;
3424
3425 if (plane == OMAP_DSS_WB)
3426 return 0;
3427
3428 channel = dispc_ovl_get_channel_out(plane);
3429
3430 return dispc_mgr_pclk_rate(channel);
3431}
3432
3433static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3434{
3435 enum omap_channel channel;
3436
3437 if (plane == OMAP_DSS_WB)
3438 return 0;
3439
3440 channel = dispc_ovl_get_channel_out(plane);
3441
3442 return dispc_mgr_lclk_rate(channel);
3443}
3444
3445static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3446{
3447 int lcd, pcd;
3448 enum omap_dss_clk_source lcd_clk_src;
3449
3450 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3451
3452 lcd_clk_src = dss_get_lcd_clk_source(channel);
3453
3454 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3455 dss_get_generic_clk_source_name(lcd_clk_src),
3456 dss_feat_get_clk_source_name(lcd_clk_src));
3457
3458 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3459
3460 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3461 dispc_mgr_lclk_rate(channel), lcd);
3462 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3463 dispc_mgr_pclk_rate(channel), pcd);
3464}
3465
3466void dispc_dump_clocks(struct seq_file *s)
3467{
3468 int lcd;
3469 u32 l;
3470 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3471
3472 if (dispc_runtime_get())
3473 return;
3474
3475 seq_printf(s, "- DISPC -\n");
3476
3477 seq_printf(s, "dispc fclk source = %s (%s)\n",
3478 dss_get_generic_clk_source_name(dispc_clk_src),
3479 dss_feat_get_clk_source_name(dispc_clk_src));
3480
3481 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3482
3483 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3484 seq_printf(s, "- DISPC-CORE-CLK -\n");
3485 l = dispc_read_reg(DISPC_DIVISOR);
3486 lcd = FLD_GET(l, 23, 16);
3487
3488 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3489 (dispc_fclk_rate()/lcd), lcd);
3490 }
3491
3492 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3493
3494 if (dss_has_feature(FEAT_MGR_LCD2))
3495 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3496 if (dss_has_feature(FEAT_MGR_LCD3))
3497 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3498
3499 dispc_runtime_put();
3500}
3501
3502static void dispc_dump_regs(struct seq_file *s)
3503{
3504 int i, j;
3505 const char *mgr_names[] = {
3506 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3507 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3508 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3509 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3510 };
3511 const char *ovl_names[] = {
3512 [OMAP_DSS_GFX] = "GFX",
3513 [OMAP_DSS_VIDEO1] = "VID1",
3514 [OMAP_DSS_VIDEO2] = "VID2",
3515 [OMAP_DSS_VIDEO3] = "VID3",
3516 [OMAP_DSS_WB] = "WB",
3517 };
3518 const char **p_names;
3519
3520#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3521
3522 if (dispc_runtime_get())
3523 return;
3524
3525 /* DISPC common registers */
3526 DUMPREG(DISPC_REVISION);
3527 DUMPREG(DISPC_SYSCONFIG);
3528 DUMPREG(DISPC_SYSSTATUS);
3529 DUMPREG(DISPC_IRQSTATUS);
3530 DUMPREG(DISPC_IRQENABLE);
3531 DUMPREG(DISPC_CONTROL);
3532 DUMPREG(DISPC_CONFIG);
3533 DUMPREG(DISPC_CAPABLE);
3534 DUMPREG(DISPC_LINE_STATUS);
3535 DUMPREG(DISPC_LINE_NUMBER);
3536 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3537 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3538 DUMPREG(DISPC_GLOBAL_ALPHA);
3539 if (dss_has_feature(FEAT_MGR_LCD2)) {
3540 DUMPREG(DISPC_CONTROL2);
3541 DUMPREG(DISPC_CONFIG2);
3542 }
3543 if (dss_has_feature(FEAT_MGR_LCD3)) {
3544 DUMPREG(DISPC_CONTROL3);
3545 DUMPREG(DISPC_CONFIG3);
3546 }
3547 if (dss_has_feature(FEAT_MFLAG))
3548 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3549
3550#undef DUMPREG
3551
3552#define DISPC_REG(i, name) name(i)
3553#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3554 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3555 dispc_read_reg(DISPC_REG(i, r)))
3556
3557 p_names = mgr_names;
3558
3559 /* DISPC channel specific registers */
3560 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3561 DUMPREG(i, DISPC_DEFAULT_COLOR);
3562 DUMPREG(i, DISPC_TRANS_COLOR);
3563 DUMPREG(i, DISPC_SIZE_MGR);
3564
3565 if (i == OMAP_DSS_CHANNEL_DIGIT)
3566 continue;
3567
3568 DUMPREG(i, DISPC_TIMING_H);
3569 DUMPREG(i, DISPC_TIMING_V);
3570 DUMPREG(i, DISPC_POL_FREQ);
3571 DUMPREG(i, DISPC_DIVISORo);
3572
3573 DUMPREG(i, DISPC_DATA_CYCLE1);
3574 DUMPREG(i, DISPC_DATA_CYCLE2);
3575 DUMPREG(i, DISPC_DATA_CYCLE3);
3576
3577 if (dss_has_feature(FEAT_CPR)) {
3578 DUMPREG(i, DISPC_CPR_COEF_R);
3579 DUMPREG(i, DISPC_CPR_COEF_G);
3580 DUMPREG(i, DISPC_CPR_COEF_B);
3581 }
3582 }
3583
3584 p_names = ovl_names;
3585
3586 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3587 DUMPREG(i, DISPC_OVL_BA0);
3588 DUMPREG(i, DISPC_OVL_BA1);
3589 DUMPREG(i, DISPC_OVL_POSITION);
3590 DUMPREG(i, DISPC_OVL_SIZE);
3591 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3592 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3593 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3594 DUMPREG(i, DISPC_OVL_ROW_INC);
3595 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3596
3597 if (dss_has_feature(FEAT_PRELOAD))
3598 DUMPREG(i, DISPC_OVL_PRELOAD);
3599 if (dss_has_feature(FEAT_MFLAG))
3600 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3601
3602 if (i == OMAP_DSS_GFX) {
3603 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3604 DUMPREG(i, DISPC_OVL_TABLE_BA);
3605 continue;
3606 }
3607
3608 DUMPREG(i, DISPC_OVL_FIR);
3609 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3610 DUMPREG(i, DISPC_OVL_ACCU0);
3611 DUMPREG(i, DISPC_OVL_ACCU1);
3612 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3613 DUMPREG(i, DISPC_OVL_BA0_UV);
3614 DUMPREG(i, DISPC_OVL_BA1_UV);
3615 DUMPREG(i, DISPC_OVL_FIR2);
3616 DUMPREG(i, DISPC_OVL_ACCU2_0);
3617 DUMPREG(i, DISPC_OVL_ACCU2_1);
3618 }
3619 if (dss_has_feature(FEAT_ATTR2))
3620 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3621 }
3622
3623 if (dispc.feat->has_writeback) {
3624 i = OMAP_DSS_WB;
3625 DUMPREG(i, DISPC_OVL_BA0);
3626 DUMPREG(i, DISPC_OVL_BA1);
3627 DUMPREG(i, DISPC_OVL_SIZE);
3628 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3629 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3630 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3631 DUMPREG(i, DISPC_OVL_ROW_INC);
3632 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3633
3634 if (dss_has_feature(FEAT_MFLAG))
3635 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3636
3637 DUMPREG(i, DISPC_OVL_FIR);
3638 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3639 DUMPREG(i, DISPC_OVL_ACCU0);
3640 DUMPREG(i, DISPC_OVL_ACCU1);
3641 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3642 DUMPREG(i, DISPC_OVL_BA0_UV);
3643 DUMPREG(i, DISPC_OVL_BA1_UV);
3644 DUMPREG(i, DISPC_OVL_FIR2);
3645 DUMPREG(i, DISPC_OVL_ACCU2_0);
3646 DUMPREG(i, DISPC_OVL_ACCU2_1);
3647 }
3648 if (dss_has_feature(FEAT_ATTR2))
3649 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3650 }
3651
3652#undef DISPC_REG
3653#undef DUMPREG
3654
3655#define DISPC_REG(plane, name, i) name(plane, i)
3656#define DUMPREG(plane, name, i) \
3657 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3658 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3659 dispc_read_reg(DISPC_REG(plane, name, i)))
3660
3661 /* Video pipeline coefficient registers */
3662
3663 /* start from OMAP_DSS_VIDEO1 */
3664 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3665 for (j = 0; j < 8; j++)
3666 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3667
3668 for (j = 0; j < 8; j++)
3669 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3670
3671 for (j = 0; j < 5; j++)
3672 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3673
3674 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3675 for (j = 0; j < 8; j++)
3676 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3677 }
3678
3679 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3680 for (j = 0; j < 8; j++)
3681 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3682
3683 for (j = 0; j < 8; j++)
3684 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3685
3686 for (j = 0; j < 8; j++)
3687 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3688 }
3689 }
3690
3691 dispc_runtime_put();
3692
3693#undef DISPC_REG
3694#undef DUMPREG
3695}
3696
3697/* calculate clock rates using dividers in cinfo */
3698int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3699 struct dispc_clock_info *cinfo)
3700{
3701 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3702 return -EINVAL;
3703 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3704 return -EINVAL;
3705
3706 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3707 cinfo->pck = cinfo->lck / cinfo->pck_div;
3708
3709 return 0;
3710}
3711
3712bool dispc_div_calc(unsigned long dispc,
3713 unsigned long pck_min, unsigned long pck_max,
3714 dispc_div_calc_func func, void *data)
3715{
3716 int lckd, lckd_start, lckd_stop;
3717 int pckd, pckd_start, pckd_stop;
3718 unsigned long pck, lck;
3719 unsigned long lck_max;
3720 unsigned long pckd_hw_min, pckd_hw_max;
3721 unsigned min_fck_per_pck;
3722 unsigned long fck;
3723
35b522cf
TV		 3724#ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3725 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
f76ee892
TV		 3726#else
3727 min_fck_per_pck = 0;
3728#endif
3729
3730 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3731 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3732
3733 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3734
3735 pck_min = pck_min ? pck_min : 1;
3736 pck_max = pck_max ? pck_max : ULONG_MAX;
3737
3738 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3739 lckd_stop = min(dispc / pck_min, 255ul);
3740
3741 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3742 lck = dispc / lckd;
3743
3744 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3745 pckd_stop = min(lck / pck_min, pckd_hw_max);
3746
3747 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3748 pck = lck / pckd;
3749
3750 /*
3751 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3752 * clock, which means we're configuring DISPC fclk here
3753 * also. Thus we need to use the calculated lck. For
3754 * OMAP4+ the DISPC fclk is a separate clock.
3755 */
3756 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3757 fck = dispc_core_clk_rate();
3758 else
3759 fck = lck;
3760
3761 if (fck < pck * min_fck_per_pck)
3762 continue;
3763
3764 if (func(lckd, pckd, lck, pck, data))
3765 return true;
3766 }
3767 }
3768
3769 return false;
3770}
3771
3772void dispc_mgr_set_clock_div(enum omap_channel channel,
3773 const struct dispc_clock_info *cinfo)
3774{
3775 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3776 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3777
3778 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3779}
3780
3781int dispc_mgr_get_clock_div(enum omap_channel channel,
3782 struct dispc_clock_info *cinfo)
3783{
3784 unsigned long fck;
3785
3786 fck = dispc_fclk_rate();
3787
3788 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3789 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3790
3791 cinfo->lck = fck / cinfo->lck_div;
3792 cinfo->pck = cinfo->lck / cinfo->pck_div;
3793
3794 return 0;
3795}
3796
3797u32 dispc_read_irqstatus(void)
3798{
3799 return dispc_read_reg(DISPC_IRQSTATUS);
3800}
3801EXPORT_SYMBOL(dispc_read_irqstatus);
3802
3803void dispc_clear_irqstatus(u32 mask)
3804{
3805 dispc_write_reg(DISPC_IRQSTATUS, mask);
3806}
3807EXPORT_SYMBOL(dispc_clear_irqstatus);
3808
3809u32 dispc_read_irqenable(void)
3810{
3811 return dispc_read_reg(DISPC_IRQENABLE);
3812}
3813EXPORT_SYMBOL(dispc_read_irqenable);
3814
3815void dispc_write_irqenable(u32 mask)
3816{
3817 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3818
3819 /* clear the irqstatus for newly enabled irqs */
3820 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3821
3822 dispc_write_reg(DISPC_IRQENABLE, mask);
3823}
3824EXPORT_SYMBOL(dispc_write_irqenable);
3825
3826void dispc_enable_sidle(void)
3827{
3828 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3829}
3830
3831void dispc_disable_sidle(void)
3832{
3833 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3834}
3835
3836static void _omap_dispc_initial_config(void)
3837{
3838 u32 l;
3839
3840 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3841 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3842 l = dispc_read_reg(DISPC_DIVISOR);
3843 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3844 l = FLD_MOD(l, 1, 0, 0);
3845 l = FLD_MOD(l, 1, 23, 16);
3846 dispc_write_reg(DISPC_DIVISOR, l);
3847
3848 dispc.core_clk_rate = dispc_fclk_rate();
3849 }
3850
3851 /* FUNCGATED */
3852 if (dss_has_feature(FEAT_FUNCGATED))
3853 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3854
3855 dispc_setup_color_conv_coef();
3856
3857 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3858
3859 dispc_init_fifos();
3860
3861 dispc_configure_burst_sizes();
3862
3863 dispc_ovl_enable_zorder_planes();
3864
3865 if (dispc.feat->mstandby_workaround)
3866 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3867
3868 if (dss_has_feature(FEAT_MFLAG))
3869 dispc_init_mflag();
3870}
3871
3872static const struct dispc_features omap24xx_dispc_feats = {
3873 .sw_start = 5,
3874 .fp_start = 15,
3875 .bp_start = 27,
3876 .sw_max = 64,
3877 .vp_max = 255,
3878 .hp_max = 256,
3879 .mgr_width_start = 10,
3880 .mgr_height_start = 26,
3881 .mgr_width_max = 2048,
3882 .mgr_height_max = 2048,
3883 .max_lcd_pclk = 66500000,
3884 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3885 .calc_core_clk = calc_core_clk_24xx,
3886 .num_fifos = 3,
3887 .no_framedone_tv = true,
3888 .set_max_preload = false,
3889 .last_pixel_inc_missing = true,
3890};
3891
3892static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3893 .sw_start = 5,
3894 .fp_start = 15,
3895 .bp_start = 27,
3896 .sw_max = 64,
3897 .vp_max = 255,
3898 .hp_max = 256,
3899 .mgr_width_start = 10,
3900 .mgr_height_start = 26,
3901 .mgr_width_max = 2048,
3902 .mgr_height_max = 2048,
3903 .max_lcd_pclk = 173000000,
3904 .max_tv_pclk = 59000000,
3905 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3906 .calc_core_clk = calc_core_clk_34xx,
3907 .num_fifos = 3,
3908 .no_framedone_tv = true,
3909 .set_max_preload = false,
3910 .last_pixel_inc_missing = true,
3911};
3912
3913static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3914 .sw_start = 7,
3915 .fp_start = 19,
3916 .bp_start = 31,
3917 .sw_max = 256,
3918 .vp_max = 4095,
3919 .hp_max = 4096,
3920 .mgr_width_start = 10,
3921 .mgr_height_start = 26,
3922 .mgr_width_max = 2048,
3923 .mgr_height_max = 2048,
3924 .max_lcd_pclk = 173000000,
3925 .max_tv_pclk = 59000000,
3926 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3927 .calc_core_clk = calc_core_clk_34xx,
3928 .num_fifos = 3,
3929 .no_framedone_tv = true,
3930 .set_max_preload = false,
3931 .last_pixel_inc_missing = true,
3932};
3933
3934static const struct dispc_features omap44xx_dispc_feats = {
3935 .sw_start = 7,
3936 .fp_start = 19,
3937 .bp_start = 31,
3938 .sw_max = 256,
3939 .vp_max = 4095,
3940 .hp_max = 4096,
3941 .mgr_width_start = 10,
3942 .mgr_height_start = 26,
3943 .mgr_width_max = 2048,
3944 .mgr_height_max = 2048,
3945 .max_lcd_pclk = 170000000,
3946 .max_tv_pclk = 185625000,
3947 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3948 .calc_core_clk = calc_core_clk_44xx,
3949 .num_fifos = 5,
3950 .gfx_fifo_workaround = true,
3951 .set_max_preload = true,
3952 .supports_sync_align = true,
3953 .has_writeback = true,
3954};
3955
3956static const struct dispc_features omap54xx_dispc_feats = {
3957 .sw_start = 7,
3958 .fp_start = 19,
3959 .bp_start = 31,
3960 .sw_max = 256,
3961 .vp_max = 4095,
3962 .hp_max = 4096,
3963 .mgr_width_start = 11,
3964 .mgr_height_start = 27,
3965 .mgr_width_max = 4096,
3966 .mgr_height_max = 4096,
3967 .max_lcd_pclk = 170000000,
3968 .max_tv_pclk = 186000000,
3969 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3970 .calc_core_clk = calc_core_clk_44xx,
3971 .num_fifos = 5,
3972 .gfx_fifo_workaround = true,
3973 .mstandby_workaround = true,
3974 .set_max_preload = true,
3975 .supports_sync_align = true,
3976 .has_writeback = true,
3977};
3978
3979static int dispc_init_features(struct platform_device *pdev)
3980{
3981 const struct dispc_features *src;
3982 struct dispc_features *dst;
3983
3984 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
3985 if (!dst) {
3986 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
3987 return -ENOMEM;
3988 }
3989
3990 switch (omapdss_get_version()) {
3991 case OMAPDSS_VER_OMAP24xx:
3992 src = &omap24xx_dispc_feats;
3993 break;
3994
3995 case OMAPDSS_VER_OMAP34xx_ES1:
3996 src = &omap34xx_rev1_0_dispc_feats;
3997 break;
3998
3999 case OMAPDSS_VER_OMAP34xx_ES3:
4000 case OMAPDSS_VER_OMAP3630:
4001 case OMAPDSS_VER_AM35xx:
4002 case OMAPDSS_VER_AM43xx:
4003 src = &omap34xx_rev3_0_dispc_feats;
4004 break;
4005
4006 case OMAPDSS_VER_OMAP4430_ES1:
4007 case OMAPDSS_VER_OMAP4430_ES2:
4008 case OMAPDSS_VER_OMAP4:
4009 src = &omap44xx_dispc_feats;
4010 break;
4011
4012 case OMAPDSS_VER_OMAP5:
4013 case OMAPDSS_VER_DRA7xx:
4014 src = &omap54xx_dispc_feats;
4015 break;
4016
4017 default:
4018 return -ENODEV;
4019 }
4020
4021 memcpy(dst, src, sizeof(*dst));
4022 dispc.feat = dst;
4023
4024 return 0;
4025}
4026
4027static irqreturn_t dispc_irq_handler(int irq, void *arg)
4028{
4029 if (!dispc.is_enabled)
4030 return IRQ_NONE;
4031
4032 return dispc.user_handler(irq, dispc.user_data);
4033}
4034
4035int dispc_request_irq(irq_handler_t handler, void *dev_id)
4036{
4037 int r;
4038
4039 if (dispc.user_handler != NULL)
4040 return -EBUSY;
4041
4042 dispc.user_handler = handler;
4043 dispc.user_data = dev_id;
4044
4045 /* ensure the dispc_irq_handler sees the values above */
4046 smp_wmb();
4047
4048 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
4049 IRQF_SHARED, "OMAP DISPC", &dispc);
4050 if (r) {
4051 dispc.user_handler = NULL;
4052 dispc.user_data = NULL;
4053 }
4054
4055 return r;
4056}
4057EXPORT_SYMBOL(dispc_request_irq);
4058
4059void dispc_free_irq(void *dev_id)
4060{
4061 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
4062
4063 dispc.user_handler = NULL;
4064 dispc.user_data = NULL;
4065}
4066EXPORT_SYMBOL(dispc_free_irq);
4067
4068/* DISPC HW IP initialisation */
4069static int dispc_bind(struct device *dev, struct device *master, void *data)
4070{
4071 struct platform_device *pdev = to_platform_device(dev);
4072 u32 rev;
4073 int r = 0;
4074 struct resource *dispc_mem;
4075 struct device_node *np = pdev->dev.of_node;
4076
4077 dispc.pdev = pdev;
4078
4079 spin_lock_init(&dispc.control_lock);
4080
4081 r = dispc_init_features(dispc.pdev);
4082 if (r)
4083 return r;
4084
4085 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4086 if (!dispc_mem) {
4087 DSSERR("can't get IORESOURCE_MEM DISPC\n");
4088 return -EINVAL;
4089 }
4090
4091 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4092 resource_size(dispc_mem));
4093 if (!dispc.base) {
4094 DSSERR("can't ioremap DISPC\n");
4095 return -ENOMEM;
4096 }
4097
4098 dispc.irq = platform_get_irq(dispc.pdev, 0);
4099 if (dispc.irq < 0) {
4100 DSSERR("platform_get_irq failed\n");
4101 return -ENODEV;
4102 }
4103
4104 if (np && of_property_read_bool(np, "syscon-pol")) {
4105 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4106 if (IS_ERR(dispc.syscon_pol)) {
4107 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4108 return PTR_ERR(dispc.syscon_pol);
4109 }
4110
4111 if (of_property_read_u32_index(np, "syscon-pol", 1,
4112 &dispc.syscon_pol_offset)) {
4113 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4114 return -EINVAL;
4115 }
4116 }
4117
4118 pm_runtime_enable(&pdev->dev);
4119
4120 r = dispc_runtime_get();
4121 if (r)
4122 goto err_runtime_get;
4123
4124 _omap_dispc_initial_config();
4125
4126 rev = dispc_read_reg(DISPC_REVISION);
4127 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4128 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4129
4130 dispc_runtime_put();
4131
4132 dss_init_overlay_managers();
4133
4134 dss_debugfs_create_file("dispc", dispc_dump_regs);
4135
4136 return 0;
4137
4138err_runtime_get:
4139 pm_runtime_disable(&pdev->dev);
4140 return r;
4141}
4142
4143static void dispc_unbind(struct device *dev, struct device *master,
4144 void *data)
4145{
4146 pm_runtime_disable(dev);
4147
4148 dss_uninit_overlay_managers();
4149}
4150
4151static const struct component_ops dispc_component_ops = {
4152 .bind = dispc_bind,
4153 .unbind = dispc_unbind,
4154};
4155
4156static int dispc_probe(struct platform_device *pdev)
4157{
4158 return component_add(&pdev->dev, &dispc_component_ops);
4159}
4160
4161static int dispc_remove(struct platform_device *pdev)
4162{
4163 component_del(&pdev->dev, &dispc_component_ops);
4164 return 0;
4165}
4166
4167static int dispc_runtime_suspend(struct device *dev)
4168{
4169 dispc.is_enabled = false;
4170 /* ensure the dispc_irq_handler sees the is_enabled value */
4171 smp_wmb();
4172 /* wait for current handler to finish before turning the DISPC off */
4173 synchronize_irq(dispc.irq);
4174
4175 dispc_save_context();
4176
4177 return 0;
4178}
4179
4180static int dispc_runtime_resume(struct device *dev)
4181{
4182 /*
4183 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4184 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4185 * _omap_dispc_initial_config(). We can thus use it to detect if
4186 * we have lost register context.
4187 */
4188 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4189 _omap_dispc_initial_config();
4190
4191 dispc_restore_context();
4192 }
4193
4194 dispc.is_enabled = true;
4195 /* ensure the dispc_irq_handler sees the is_enabled value */
4196 smp_wmb();
4197
4198 return 0;
4199}
4200
4201static const struct dev_pm_ops dispc_pm_ops = {
4202 .runtime_suspend = dispc_runtime_suspend,
4203 .runtime_resume = dispc_runtime_resume,
4204};
4205
4206static const struct of_device_id dispc_of_match[] = {
4207 { .compatible = "ti,omap2-dispc", },
4208 { .compatible = "ti,omap3-dispc", },
4209 { .compatible = "ti,omap4-dispc", },
4210 { .compatible = "ti,omap5-dispc", },
4211 { .compatible = "ti,dra7-dispc", },
4212 {},
4213};
4214
4215static struct platform_driver omap_dispchw_driver = {
4216 .probe = dispc_probe,
4217 .remove = dispc_remove,
4218 .driver = {
4219 .name = "omapdss_dispc",
4220 .pm = &dispc_pm_ops,
4221 .of_match_table = dispc_of_match,
4222 .suppress_bind_attrs = true,
4223 },
4224};
4225
4226int __init dispc_init_platform_driver(void)
4227{
4228 return platform_driver_register(&omap_dispchw_driver);
4229}
4230
4231void dispc_uninit_platform_driver(void)
4232{
4233 platform_driver_unregister(&omap_dispchw_driver);
4234}
Linux kernel - Deliverables
This page took 0.201835 seconds and 5 git commands to generate.