Commit | Line | Data |
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1da177e4 LT |
1 | /* ffb.c: Creator/Elite3D frame buffer driver |
2 | * | |
50312ce9 | 3 | * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz) |
5 | * | |
6 | * Driver layout based loosely on tgafb.c, see that file for credits. | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/string.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/fb.h> | |
17 | #include <linux/mm.h> | |
18 | #include <linux/timer.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | #include <asm/upa.h> | |
50312ce9 DM |
22 | #include <asm/prom.h> |
23 | #include <asm/of_device.h> | |
1da177e4 LT |
24 | #include <asm/fbio.h> |
25 | ||
26 | #include "sbuslib.h" | |
27 | ||
28 | /* | |
29 | * Local functions. | |
30 | */ | |
31 | ||
32 | static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned, | |
33 | unsigned, struct fb_info *); | |
34 | static int ffb_blank(int, struct fb_info *); | |
35 | static void ffb_init_fix(struct fb_info *); | |
36 | ||
37 | static void ffb_imageblit(struct fb_info *, const struct fb_image *); | |
38 | static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *); | |
39 | static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *); | |
40 | static int ffb_sync(struct fb_info *); | |
216d526c | 41 | static int ffb_mmap(struct fb_info *, struct vm_area_struct *); |
67a6680d | 42 | static int ffb_ioctl(struct fb_info *, unsigned int, unsigned long); |
1da177e4 LT |
43 | static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *); |
44 | ||
45 | /* | |
46 | * Frame buffer operations | |
47 | */ | |
48 | ||
49 | static struct fb_ops ffb_ops = { | |
50 | .owner = THIS_MODULE, | |
51 | .fb_setcolreg = ffb_setcolreg, | |
52 | .fb_blank = ffb_blank, | |
53 | .fb_pan_display = ffb_pan_display, | |
54 | .fb_fillrect = ffb_fillrect, | |
55 | .fb_copyarea = ffb_copyarea, | |
56 | .fb_imageblit = ffb_imageblit, | |
57 | .fb_sync = ffb_sync, | |
58 | .fb_mmap = ffb_mmap, | |
59 | .fb_ioctl = ffb_ioctl, | |
9ffb83bc CH |
60 | #ifdef CONFIG_COMPAT |
61 | .fb_compat_ioctl = sbusfb_compat_ioctl, | |
62 | #endif | |
1da177e4 LT |
63 | }; |
64 | ||
65 | /* Register layout and definitions */ | |
66 | #define FFB_SFB8R_VOFF 0x00000000 | |
67 | #define FFB_SFB8G_VOFF 0x00400000 | |
68 | #define FFB_SFB8B_VOFF 0x00800000 | |
69 | #define FFB_SFB8X_VOFF 0x00c00000 | |
70 | #define FFB_SFB32_VOFF 0x01000000 | |
71 | #define FFB_SFB64_VOFF 0x02000000 | |
72 | #define FFB_FBC_REGS_VOFF 0x04000000 | |
73 | #define FFB_BM_FBC_REGS_VOFF 0x04002000 | |
74 | #define FFB_DFB8R_VOFF 0x04004000 | |
75 | #define FFB_DFB8G_VOFF 0x04404000 | |
76 | #define FFB_DFB8B_VOFF 0x04804000 | |
77 | #define FFB_DFB8X_VOFF 0x04c04000 | |
78 | #define FFB_DFB24_VOFF 0x05004000 | |
79 | #define FFB_DFB32_VOFF 0x06004000 | |
80 | #define FFB_DFB422A_VOFF 0x07004000 /* DFB 422 mode write to A */ | |
81 | #define FFB_DFB422AD_VOFF 0x07804000 /* DFB 422 mode with line doubling */ | |
82 | #define FFB_DFB24B_VOFF 0x08004000 /* DFB 24bit mode write to B */ | |
83 | #define FFB_DFB422B_VOFF 0x09004000 /* DFB 422 mode write to B */ | |
84 | #define FFB_DFB422BD_VOFF 0x09804000 /* DFB 422 mode with line doubling */ | |
85 | #define FFB_SFB16Z_VOFF 0x0a004000 /* 16bit mode Z planes */ | |
86 | #define FFB_SFB8Z_VOFF 0x0a404000 /* 8bit mode Z planes */ | |
87 | #define FFB_SFB422_VOFF 0x0ac04000 /* SFB 422 mode write to A/B */ | |
88 | #define FFB_SFB422D_VOFF 0x0b404000 /* SFB 422 mode with line doubling */ | |
89 | #define FFB_FBC_KREGS_VOFF 0x0bc04000 | |
90 | #define FFB_DAC_VOFF 0x0bc06000 | |
91 | #define FFB_PROM_VOFF 0x0bc08000 | |
92 | #define FFB_EXP_VOFF 0x0bc18000 | |
93 | ||
94 | #define FFB_SFB8R_POFF 0x04000000UL | |
95 | #define FFB_SFB8G_POFF 0x04400000UL | |
96 | #define FFB_SFB8B_POFF 0x04800000UL | |
97 | #define FFB_SFB8X_POFF 0x04c00000UL | |
98 | #define FFB_SFB32_POFF 0x05000000UL | |
99 | #define FFB_SFB64_POFF 0x06000000UL | |
100 | #define FFB_FBC_REGS_POFF 0x00600000UL | |
101 | #define FFB_BM_FBC_REGS_POFF 0x00600000UL | |
102 | #define FFB_DFB8R_POFF 0x01000000UL | |
103 | #define FFB_DFB8G_POFF 0x01400000UL | |
104 | #define FFB_DFB8B_POFF 0x01800000UL | |
105 | #define FFB_DFB8X_POFF 0x01c00000UL | |
106 | #define FFB_DFB24_POFF 0x02000000UL | |
107 | #define FFB_DFB32_POFF 0x03000000UL | |
108 | #define FFB_FBC_KREGS_POFF 0x00610000UL | |
109 | #define FFB_DAC_POFF 0x00400000UL | |
110 | #define FFB_PROM_POFF 0x00000000UL | |
111 | #define FFB_EXP_POFF 0x00200000UL | |
112 | #define FFB_DFB422A_POFF 0x09000000UL | |
113 | #define FFB_DFB422AD_POFF 0x09800000UL | |
114 | #define FFB_DFB24B_POFF 0x0a000000UL | |
115 | #define FFB_DFB422B_POFF 0x0b000000UL | |
116 | #define FFB_DFB422BD_POFF 0x0b800000UL | |
117 | #define FFB_SFB16Z_POFF 0x0c800000UL | |
118 | #define FFB_SFB8Z_POFF 0x0c000000UL | |
119 | #define FFB_SFB422_POFF 0x0d000000UL | |
120 | #define FFB_SFB422D_POFF 0x0d800000UL | |
121 | ||
122 | /* Draw operations */ | |
123 | #define FFB_DRAWOP_DOT 0x00 | |
124 | #define FFB_DRAWOP_AADOT 0x01 | |
125 | #define FFB_DRAWOP_BRLINECAP 0x02 | |
126 | #define FFB_DRAWOP_BRLINEOPEN 0x03 | |
127 | #define FFB_DRAWOP_DDLINE 0x04 | |
128 | #define FFB_DRAWOP_AALINE 0x05 | |
129 | #define FFB_DRAWOP_TRIANGLE 0x06 | |
130 | #define FFB_DRAWOP_POLYGON 0x07 | |
131 | #define FFB_DRAWOP_RECTANGLE 0x08 | |
132 | #define FFB_DRAWOP_FASTFILL 0x09 | |
133 | #define FFB_DRAWOP_BCOPY 0x0a | |
134 | #define FFB_DRAWOP_VSCROLL 0x0b | |
135 | ||
136 | /* Pixel processor control */ | |
137 | /* Force WID */ | |
138 | #define FFB_PPC_FW_DISABLE 0x800000 | |
139 | #define FFB_PPC_FW_ENABLE 0xc00000 | |
140 | /* Auxiliary clip */ | |
141 | #define FFB_PPC_ACE_DISABLE 0x040000 | |
142 | #define FFB_PPC_ACE_AUX_SUB 0x080000 | |
143 | #define FFB_PPC_ACE_AUX_ADD 0x0c0000 | |
144 | /* Depth cue */ | |
145 | #define FFB_PPC_DCE_DISABLE 0x020000 | |
146 | #define FFB_PPC_DCE_ENABLE 0x030000 | |
147 | /* Alpha blend */ | |
148 | #define FFB_PPC_ABE_DISABLE 0x008000 | |
149 | #define FFB_PPC_ABE_ENABLE 0x00c000 | |
150 | /* View clip */ | |
151 | #define FFB_PPC_VCE_DISABLE 0x001000 | |
152 | #define FFB_PPC_VCE_2D 0x002000 | |
153 | #define FFB_PPC_VCE_3D 0x003000 | |
154 | /* Area pattern */ | |
155 | #define FFB_PPC_APE_DISABLE 0x000800 | |
156 | #define FFB_PPC_APE_ENABLE 0x000c00 | |
157 | /* Transparent background */ | |
158 | #define FFB_PPC_TBE_OPAQUE 0x000200 | |
159 | #define FFB_PPC_TBE_TRANSPARENT 0x000300 | |
160 | /* Z source */ | |
161 | #define FFB_PPC_ZS_VAR 0x000080 | |
162 | #define FFB_PPC_ZS_CONST 0x0000c0 | |
163 | /* Y source */ | |
164 | #define FFB_PPC_YS_VAR 0x000020 | |
165 | #define FFB_PPC_YS_CONST 0x000030 | |
166 | /* X source */ | |
167 | #define FFB_PPC_XS_WID 0x000004 | |
168 | #define FFB_PPC_XS_VAR 0x000008 | |
169 | #define FFB_PPC_XS_CONST 0x00000c | |
170 | /* Color (BGR) source */ | |
171 | #define FFB_PPC_CS_VAR 0x000002 | |
172 | #define FFB_PPC_CS_CONST 0x000003 | |
173 | ||
174 | #define FFB_ROP_NEW 0x83 | |
175 | #define FFB_ROP_OLD 0x85 | |
176 | #define FFB_ROP_NEW_XOR_OLD 0x86 | |
177 | ||
178 | #define FFB_UCSR_FIFO_MASK 0x00000fff | |
179 | #define FFB_UCSR_FB_BUSY 0x01000000 | |
180 | #define FFB_UCSR_RP_BUSY 0x02000000 | |
181 | #define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY) | |
182 | #define FFB_UCSR_READ_ERR 0x40000000 | |
183 | #define FFB_UCSR_FIFO_OVFL 0x80000000 | |
184 | #define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL) | |
185 | ||
186 | struct ffb_fbc { | |
187 | /* Next vertex registers */ | |
50312ce9 DM |
188 | u32 xxx1[3]; |
189 | u32 alpha; | |
190 | u32 red; | |
191 | u32 green; | |
192 | u32 blue; | |
193 | u32 depth; | |
194 | u32 y; | |
195 | u32 x; | |
196 | u32 xxx2[2]; | |
197 | u32 ryf; | |
198 | u32 rxf; | |
199 | u32 xxx3[2]; | |
1da177e4 | 200 | |
50312ce9 DM |
201 | u32 dmyf; |
202 | u32 dmxf; | |
203 | u32 xxx4[2]; | |
204 | u32 ebyi; | |
205 | u32 ebxi; | |
206 | u32 xxx5[2]; | |
207 | u32 by; | |
208 | u32 bx; | |
209 | u32 dy; | |
210 | u32 dx; | |
211 | u32 bh; | |
212 | u32 bw; | |
213 | u32 xxx6[2]; | |
1da177e4 | 214 | |
50312ce9 | 215 | u32 xxx7[32]; |
1da177e4 LT |
216 | |
217 | /* Setup unit vertex state register */ | |
50312ce9 DM |
218 | u32 suvtx; |
219 | u32 xxx8[63]; | |
1da177e4 LT |
220 | |
221 | /* Control registers */ | |
50312ce9 DM |
222 | u32 ppc; |
223 | u32 wid; | |
224 | u32 fg; | |
225 | u32 bg; | |
226 | u32 consty; | |
227 | u32 constz; | |
228 | u32 xclip; | |
229 | u32 dcss; | |
230 | u32 vclipmin; | |
231 | u32 vclipmax; | |
232 | u32 vclipzmin; | |
233 | u32 vclipzmax; | |
234 | u32 dcsf; | |
235 | u32 dcsb; | |
236 | u32 dczf; | |
237 | u32 dczb; | |
1da177e4 | 238 | |
50312ce9 DM |
239 | u32 xxx9; |
240 | u32 blendc; | |
241 | u32 blendc1; | |
242 | u32 blendc2; | |
243 | u32 fbramitc; | |
244 | u32 fbc; | |
245 | u32 rop; | |
246 | u32 cmp; | |
247 | u32 matchab; | |
248 | u32 matchc; | |
249 | u32 magnab; | |
250 | u32 magnc; | |
251 | u32 fbcfg0; | |
252 | u32 fbcfg1; | |
253 | u32 fbcfg2; | |
254 | u32 fbcfg3; | |
1da177e4 | 255 | |
50312ce9 DM |
256 | u32 ppcfg; |
257 | u32 pick; | |
258 | u32 fillmode; | |
259 | u32 fbramwac; | |
260 | u32 pmask; | |
261 | u32 xpmask; | |
262 | u32 ypmask; | |
263 | u32 zpmask; | |
264 | u32 clip0min; | |
265 | u32 clip0max; | |
266 | u32 clip1min; | |
267 | u32 clip1max; | |
268 | u32 clip2min; | |
269 | u32 clip2max; | |
270 | u32 clip3min; | |
271 | u32 clip3max; | |
1da177e4 LT |
272 | |
273 | /* New 3dRAM III support regs */ | |
50312ce9 DM |
274 | u32 rawblend2; |
275 | u32 rawpreblend; | |
276 | u32 rawstencil; | |
277 | u32 rawstencilctl; | |
278 | u32 threedram1; | |
279 | u32 threedram2; | |
280 | u32 passin; | |
281 | u32 rawclrdepth; | |
282 | u32 rawpmask; | |
283 | u32 rawcsrc; | |
284 | u32 rawmatch; | |
285 | u32 rawmagn; | |
286 | u32 rawropblend; | |
287 | u32 rawcmp; | |
288 | u32 rawwac; | |
289 | u32 fbramid; | |
1da177e4 | 290 | |
50312ce9 DM |
291 | u32 drawop; |
292 | u32 xxx10[2]; | |
293 | u32 fontlpat; | |
294 | u32 xxx11; | |
295 | u32 fontxy; | |
296 | u32 fontw; | |
297 | u32 fontinc; | |
298 | u32 font; | |
299 | u32 xxx12[3]; | |
300 | u32 blend2; | |
301 | u32 preblend; | |
302 | u32 stencil; | |
303 | u32 stencilctl; | |
304 | ||
305 | u32 xxx13[4]; | |
306 | u32 dcss1; | |
307 | u32 dcss2; | |
308 | u32 dcss3; | |
309 | u32 widpmask; | |
310 | u32 dcs2; | |
311 | u32 dcs3; | |
312 | u32 dcs4; | |
313 | u32 xxx14; | |
314 | u32 dcd2; | |
315 | u32 dcd3; | |
316 | u32 dcd4; | |
317 | u32 xxx15; | |
1da177e4 | 318 | |
50312ce9 | 319 | u32 pattern[32]; |
1da177e4 | 320 | |
50312ce9 | 321 | u32 xxx16[256]; |
1da177e4 | 322 | |
50312ce9 DM |
323 | u32 devid; |
324 | u32 xxx17[63]; | |
1da177e4 | 325 | |
50312ce9 DM |
326 | u32 ucsr; |
327 | u32 xxx18[31]; | |
1da177e4 | 328 | |
50312ce9 | 329 | u32 mer; |
1da177e4 LT |
330 | }; |
331 | ||
332 | struct ffb_dac { | |
50312ce9 DM |
333 | u32 type; |
334 | u32 value; | |
335 | u32 type2; | |
336 | u32 value2; | |
1da177e4 LT |
337 | }; |
338 | ||
339 | struct ffb_par { | |
340 | spinlock_t lock; | |
50312ce9 DM |
341 | struct ffb_fbc __iomem *fbc; |
342 | struct ffb_dac __iomem *dac; | |
1da177e4 LT |
343 | |
344 | u32 flags; | |
345 | #define FFB_FLAG_AFB 0x00000001 | |
346 | #define FFB_FLAG_BLANKED 0x00000002 | |
347 | ||
348 | u32 fg_cache __attribute__((aligned (8))); | |
349 | u32 bg_cache; | |
350 | u32 rop_cache; | |
351 | ||
352 | int fifo_cache; | |
353 | ||
354 | unsigned long physbase; | |
355 | unsigned long fbsize; | |
356 | ||
1da177e4 LT |
357 | int dac_rev; |
358 | int board_type; | |
1da177e4 LT |
359 | }; |
360 | ||
361 | static void FFBFifo(struct ffb_par *par, int n) | |
362 | { | |
50312ce9 | 363 | struct ffb_fbc __iomem *fbc; |
1da177e4 LT |
364 | int cache = par->fifo_cache; |
365 | ||
366 | if (cache - n < 0) { | |
367 | fbc = par->fbc; | |
368 | do { cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK) - 8; | |
369 | } while (cache - n < 0); | |
370 | } | |
371 | par->fifo_cache = cache - n; | |
372 | } | |
373 | ||
374 | static void FFBWait(struct ffb_par *par) | |
375 | { | |
50312ce9 | 376 | struct ffb_fbc __iomem *fbc; |
1da177e4 LT |
377 | int limit = 10000; |
378 | ||
379 | fbc = par->fbc; | |
380 | do { | |
381 | if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0) | |
382 | break; | |
383 | if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) { | |
384 | upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr); | |
385 | } | |
386 | udelay(10); | |
387 | } while(--limit > 0); | |
388 | } | |
389 | ||
390 | static int ffb_sync(struct fb_info *p) | |
391 | { | |
392 | struct ffb_par *par = (struct ffb_par *) p->par; | |
393 | ||
394 | FFBWait(par); | |
395 | return 0; | |
396 | } | |
397 | ||
398 | static __inline__ void ffb_rop(struct ffb_par *par, u32 rop) | |
399 | { | |
400 | if (par->rop_cache != rop) { | |
401 | FFBFifo(par, 1); | |
402 | upa_writel(rop, &par->fbc->rop); | |
403 | par->rop_cache = rop; | |
404 | } | |
405 | } | |
406 | ||
407 | static void ffb_switch_from_graph(struct ffb_par *par) | |
408 | { | |
50312ce9 DM |
409 | struct ffb_fbc __iomem *fbc = par->fbc; |
410 | struct ffb_dac __iomem *dac = par->dac; | |
1da177e4 LT |
411 | unsigned long flags; |
412 | ||
413 | spin_lock_irqsave(&par->lock, flags); | |
414 | FFBWait(par); | |
415 | par->fifo_cache = 0; | |
416 | FFBFifo(par, 7); | |
417 | upa_writel(FFB_PPC_VCE_DISABLE|FFB_PPC_TBE_OPAQUE| | |
418 | FFB_PPC_APE_DISABLE|FFB_PPC_CS_CONST, | |
419 | &fbc->ppc); | |
420 | upa_writel(0x2000707f, &fbc->fbc); | |
421 | upa_writel(par->rop_cache, &fbc->rop); | |
422 | upa_writel(0xffffffff, &fbc->pmask); | |
423 | upa_writel((1 << 16) | (0 << 0), &fbc->fontinc); | |
424 | upa_writel(par->fg_cache, &fbc->fg); | |
425 | upa_writel(par->bg_cache, &fbc->bg); | |
426 | FFBWait(par); | |
427 | ||
428 | /* Disable cursor. */ | |
429 | upa_writel(0x100, &dac->type2); | |
430 | if (par->dac_rev <= 2) | |
431 | upa_writel(0, &dac->value2); | |
432 | else | |
433 | upa_writel(3, &dac->value2); | |
434 | ||
435 | spin_unlock_irqrestore(&par->lock, flags); | |
436 | } | |
437 | ||
438 | static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |
439 | { | |
440 | struct ffb_par *par = (struct ffb_par *) info->par; | |
441 | ||
442 | /* We just use this to catch switches out of | |
443 | * graphics mode. | |
444 | */ | |
445 | ffb_switch_from_graph(par); | |
446 | ||
447 | if (var->xoffset || var->yoffset || var->vmode) | |
448 | return -EINVAL; | |
449 | return 0; | |
450 | } | |
451 | ||
452 | /** | |
453 | * ffb_fillrect - REQUIRED function. Can use generic routines if | |
454 | * non acclerated hardware and packed pixel based. | |
455 | * Draws a rectangle on the screen. | |
456 | * | |
457 | * @info: frame buffer structure that represents a single frame buffer | |
458 | * @rect: structure defining the rectagle and operation. | |
459 | */ | |
460 | static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
461 | { | |
462 | struct ffb_par *par = (struct ffb_par *) info->par; | |
50312ce9 | 463 | struct ffb_fbc __iomem *fbc = par->fbc; |
1da177e4 LT |
464 | unsigned long flags; |
465 | u32 fg; | |
466 | ||
232443e2 | 467 | BUG_ON(rect->rop != ROP_COPY && rect->rop != ROP_XOR); |
1da177e4 LT |
468 | |
469 | fg = ((u32 *)info->pseudo_palette)[rect->color]; | |
470 | ||
471 | spin_lock_irqsave(&par->lock, flags); | |
472 | ||
473 | if (fg != par->fg_cache) { | |
474 | FFBFifo(par, 1); | |
475 | upa_writel(fg, &fbc->fg); | |
476 | par->fg_cache = fg; | |
477 | } | |
478 | ||
479 | ffb_rop(par, (rect->rop == ROP_COPY ? | |
480 | FFB_ROP_NEW : | |
481 | FFB_ROP_NEW_XOR_OLD)); | |
482 | ||
483 | FFBFifo(par, 5); | |
484 | upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop); | |
485 | upa_writel(rect->dy, &fbc->by); | |
486 | upa_writel(rect->dx, &fbc->bx); | |
487 | upa_writel(rect->height, &fbc->bh); | |
488 | upa_writel(rect->width, &fbc->bw); | |
489 | ||
490 | spin_unlock_irqrestore(&par->lock, flags); | |
491 | } | |
492 | ||
493 | /** | |
494 | * ffb_copyarea - REQUIRED function. Can use generic routines if | |
495 | * non acclerated hardware and packed pixel based. | |
496 | * Copies on area of the screen to another area. | |
497 | * | |
498 | * @info: frame buffer structure that represents a single frame buffer | |
499 | * @area: structure defining the source and destination. | |
500 | */ | |
501 | ||
502 | static void | |
503 | ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area) | |
504 | { | |
505 | struct ffb_par *par = (struct ffb_par *) info->par; | |
50312ce9 | 506 | struct ffb_fbc __iomem *fbc = par->fbc; |
1da177e4 LT |
507 | unsigned long flags; |
508 | ||
509 | if (area->dx != area->sx || | |
510 | area->dy == area->sy) { | |
511 | cfb_copyarea(info, area); | |
512 | return; | |
513 | } | |
514 | ||
515 | spin_lock_irqsave(&par->lock, flags); | |
516 | ||
517 | ffb_rop(par, FFB_ROP_OLD); | |
518 | ||
519 | FFBFifo(par, 7); | |
520 | upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop); | |
521 | upa_writel(area->sy, &fbc->by); | |
522 | upa_writel(area->sx, &fbc->bx); | |
523 | upa_writel(area->dy, &fbc->dy); | |
524 | upa_writel(area->dx, &fbc->dx); | |
525 | upa_writel(area->height, &fbc->bh); | |
526 | upa_writel(area->width, &fbc->bw); | |
527 | ||
528 | spin_unlock_irqrestore(&par->lock, flags); | |
529 | } | |
530 | ||
531 | /** | |
532 | * ffb_imageblit - REQUIRED function. Can use generic routines if | |
533 | * non acclerated hardware and packed pixel based. | |
534 | * Copies a image from system memory to the screen. | |
535 | * | |
536 | * @info: frame buffer structure that represents a single frame buffer | |
537 | * @image: structure defining the image. | |
538 | */ | |
539 | static void ffb_imageblit(struct fb_info *info, const struct fb_image *image) | |
540 | { | |
541 | struct ffb_par *par = (struct ffb_par *) info->par; | |
50312ce9 | 542 | struct ffb_fbc __iomem *fbc = par->fbc; |
1da177e4 LT |
543 | const u8 *data = image->data; |
544 | unsigned long flags; | |
545 | u32 fg, bg, xy; | |
546 | u64 fgbg; | |
547 | int i, width, stride; | |
548 | ||
549 | if (image->depth > 1) { | |
550 | cfb_imageblit(info, image); | |
551 | return; | |
552 | } | |
553 | ||
554 | fg = ((u32 *)info->pseudo_palette)[image->fg_color]; | |
555 | bg = ((u32 *)info->pseudo_palette)[image->bg_color]; | |
556 | fgbg = ((u64) fg << 32) | (u64) bg; | |
557 | xy = (image->dy << 16) | image->dx; | |
558 | width = image->width; | |
559 | stride = ((width + 7) >> 3); | |
560 | ||
561 | spin_lock_irqsave(&par->lock, flags); | |
562 | ||
563 | if (fgbg != *(u64 *)&par->fg_cache) { | |
564 | FFBFifo(par, 2); | |
565 | upa_writeq(fgbg, &fbc->fg); | |
566 | *(u64 *)&par->fg_cache = fgbg; | |
567 | } | |
568 | ||
569 | if (width >= 32) { | |
570 | FFBFifo(par, 1); | |
571 | upa_writel(32, &fbc->fontw); | |
572 | } | |
573 | ||
574 | while (width >= 32) { | |
575 | const u8 *next_data = data + 4; | |
576 | ||
577 | FFBFifo(par, 1); | |
578 | upa_writel(xy, &fbc->fontxy); | |
579 | xy += (32 << 0); | |
580 | ||
581 | for (i = 0; i < image->height; i++) { | |
582 | u32 val = (((u32)data[0] << 24) | | |
583 | ((u32)data[1] << 16) | | |
584 | ((u32)data[2] << 8) | | |
585 | ((u32)data[3] << 0)); | |
586 | FFBFifo(par, 1); | |
587 | upa_writel(val, &fbc->font); | |
588 | ||
589 | data += stride; | |
590 | } | |
591 | ||
592 | data = next_data; | |
593 | width -= 32; | |
594 | } | |
595 | ||
596 | if (width) { | |
597 | FFBFifo(par, 2); | |
598 | upa_writel(width, &fbc->fontw); | |
599 | upa_writel(xy, &fbc->fontxy); | |
600 | ||
601 | for (i = 0; i < image->height; i++) { | |
602 | u32 val = (((u32)data[0] << 24) | | |
603 | ((u32)data[1] << 16) | | |
604 | ((u32)data[2] << 8) | | |
605 | ((u32)data[3] << 0)); | |
606 | FFBFifo(par, 1); | |
607 | upa_writel(val, &fbc->font); | |
608 | ||
609 | data += stride; | |
610 | } | |
611 | } | |
612 | ||
613 | spin_unlock_irqrestore(&par->lock, flags); | |
614 | } | |
615 | ||
616 | static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var) | |
617 | { | |
618 | var->red.offset = 0; | |
619 | var->red.length = 8; | |
620 | var->green.offset = 8; | |
621 | var->green.length = 8; | |
622 | var->blue.offset = 16; | |
623 | var->blue.length = 8; | |
624 | var->transp.offset = 0; | |
625 | var->transp.length = 0; | |
626 | } | |
627 | ||
628 | /** | |
629 | * ffb_setcolreg - Optional function. Sets a color register. | |
630 | * @regno: boolean, 0 copy local, 1 get_user() function | |
631 | * @red: frame buffer colormap structure | |
632 | * @green: The green value which can be up to 16 bits wide | |
633 | * @blue: The blue value which can be up to 16 bits wide. | |
634 | * @transp: If supported the alpha value which can be up to 16 bits wide. | |
635 | * @info: frame buffer info structure | |
636 | */ | |
637 | static int ffb_setcolreg(unsigned regno, | |
638 | unsigned red, unsigned green, unsigned blue, | |
639 | unsigned transp, struct fb_info *info) | |
640 | { | |
641 | u32 value; | |
642 | ||
643 | if (regno >= 256) | |
644 | return 1; | |
645 | ||
646 | red >>= 8; | |
647 | green >>= 8; | |
648 | blue >>= 8; | |
649 | ||
650 | value = (blue << 16) | (green << 8) | red; | |
651 | ((u32 *)info->pseudo_palette)[regno] = value; | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | /** | |
657 | * ffb_blank - Optional function. Blanks the display. | |
658 | * @blank_mode: the blank mode we want. | |
659 | * @info: frame buffer structure that represents a single frame buffer | |
660 | */ | |
661 | static int | |
662 | ffb_blank(int blank, struct fb_info *info) | |
663 | { | |
664 | struct ffb_par *par = (struct ffb_par *) info->par; | |
50312ce9 | 665 | struct ffb_dac __iomem *dac = par->dac; |
1da177e4 LT |
666 | unsigned long flags; |
667 | u32 tmp; | |
668 | ||
669 | spin_lock_irqsave(&par->lock, flags); | |
670 | ||
671 | FFBWait(par); | |
672 | ||
673 | switch (blank) { | |
674 | case FB_BLANK_UNBLANK: /* Unblanking */ | |
675 | upa_writel(0x6000, &dac->type); | |
676 | tmp = (upa_readl(&dac->value) | 0x1); | |
677 | upa_writel(0x6000, &dac->type); | |
678 | upa_writel(tmp, &dac->value); | |
679 | par->flags &= ~FFB_FLAG_BLANKED; | |
680 | break; | |
681 | ||
682 | case FB_BLANK_NORMAL: /* Normal blanking */ | |
683 | case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ | |
684 | case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ | |
685 | case FB_BLANK_POWERDOWN: /* Poweroff */ | |
686 | upa_writel(0x6000, &dac->type); | |
687 | tmp = (upa_readl(&dac->value) & ~0x1); | |
688 | upa_writel(0x6000, &dac->type); | |
689 | upa_writel(tmp, &dac->value); | |
690 | par->flags |= FFB_FLAG_BLANKED; | |
691 | break; | |
692 | } | |
693 | ||
694 | spin_unlock_irqrestore(&par->lock, flags); | |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
699 | static struct sbus_mmap_map ffb_mmap_map[] = { | |
700 | { | |
701 | .voff = FFB_SFB8R_VOFF, | |
702 | .poff = FFB_SFB8R_POFF, | |
703 | .size = 0x0400000 | |
704 | }, | |
705 | { | |
706 | .voff = FFB_SFB8G_VOFF, | |
707 | .poff = FFB_SFB8G_POFF, | |
708 | .size = 0x0400000 | |
709 | }, | |
710 | { | |
711 | .voff = FFB_SFB8B_VOFF, | |
712 | .poff = FFB_SFB8B_POFF, | |
713 | .size = 0x0400000 | |
714 | }, | |
715 | { | |
716 | .voff = FFB_SFB8X_VOFF, | |
717 | .poff = FFB_SFB8X_POFF, | |
718 | .size = 0x0400000 | |
719 | }, | |
720 | { | |
721 | .voff = FFB_SFB32_VOFF, | |
722 | .poff = FFB_SFB32_POFF, | |
723 | .size = 0x1000000 | |
724 | }, | |
725 | { | |
726 | .voff = FFB_SFB64_VOFF, | |
727 | .poff = FFB_SFB64_POFF, | |
728 | .size = 0x2000000 | |
729 | }, | |
730 | { | |
731 | .voff = FFB_FBC_REGS_VOFF, | |
732 | .poff = FFB_FBC_REGS_POFF, | |
733 | .size = 0x0002000 | |
734 | }, | |
735 | { | |
736 | .voff = FFB_BM_FBC_REGS_VOFF, | |
737 | .poff = FFB_BM_FBC_REGS_POFF, | |
738 | .size = 0x0002000 | |
739 | }, | |
740 | { | |
741 | .voff = FFB_DFB8R_VOFF, | |
742 | .poff = FFB_DFB8R_POFF, | |
743 | .size = 0x0400000 | |
744 | }, | |
745 | { | |
746 | .voff = FFB_DFB8G_VOFF, | |
747 | .poff = FFB_DFB8G_POFF, | |
748 | .size = 0x0400000 | |
749 | }, | |
750 | { | |
751 | .voff = FFB_DFB8B_VOFF, | |
752 | .poff = FFB_DFB8B_POFF, | |
753 | .size = 0x0400000 | |
754 | }, | |
755 | { | |
756 | .voff = FFB_DFB8X_VOFF, | |
757 | .poff = FFB_DFB8X_POFF, | |
758 | .size = 0x0400000 | |
759 | }, | |
760 | { | |
761 | .voff = FFB_DFB24_VOFF, | |
762 | .poff = FFB_DFB24_POFF, | |
763 | .size = 0x1000000 | |
764 | }, | |
765 | { | |
766 | .voff = FFB_DFB32_VOFF, | |
767 | .poff = FFB_DFB32_POFF, | |
768 | .size = 0x1000000 | |
769 | }, | |
770 | { | |
771 | .voff = FFB_FBC_KREGS_VOFF, | |
772 | .poff = FFB_FBC_KREGS_POFF, | |
773 | .size = 0x0002000 | |
774 | }, | |
775 | { | |
776 | .voff = FFB_DAC_VOFF, | |
777 | .poff = FFB_DAC_POFF, | |
778 | .size = 0x0002000 | |
779 | }, | |
780 | { | |
781 | .voff = FFB_PROM_VOFF, | |
782 | .poff = FFB_PROM_POFF, | |
783 | .size = 0x0010000 | |
784 | }, | |
785 | { | |
786 | .voff = FFB_EXP_VOFF, | |
787 | .poff = FFB_EXP_POFF, | |
788 | .size = 0x0002000 | |
789 | }, | |
790 | { | |
791 | .voff = FFB_DFB422A_VOFF, | |
792 | .poff = FFB_DFB422A_POFF, | |
793 | .size = 0x0800000 | |
794 | }, | |
795 | { | |
796 | .voff = FFB_DFB422AD_VOFF, | |
797 | .poff = FFB_DFB422AD_POFF, | |
798 | .size = 0x0800000 | |
799 | }, | |
800 | { | |
801 | .voff = FFB_DFB24B_VOFF, | |
802 | .poff = FFB_DFB24B_POFF, | |
803 | .size = 0x1000000 | |
804 | }, | |
805 | { | |
806 | .voff = FFB_DFB422B_VOFF, | |
807 | .poff = FFB_DFB422B_POFF, | |
808 | .size = 0x0800000 | |
809 | }, | |
810 | { | |
811 | .voff = FFB_DFB422BD_VOFF, | |
812 | .poff = FFB_DFB422BD_POFF, | |
813 | .size = 0x0800000 | |
814 | }, | |
815 | { | |
816 | .voff = FFB_SFB16Z_VOFF, | |
817 | .poff = FFB_SFB16Z_POFF, | |
818 | .size = 0x0800000 | |
819 | }, | |
820 | { | |
821 | .voff = FFB_SFB8Z_VOFF, | |
822 | .poff = FFB_SFB8Z_POFF, | |
823 | .size = 0x0800000 | |
824 | }, | |
825 | { | |
826 | .voff = FFB_SFB422_VOFF, | |
827 | .poff = FFB_SFB422_POFF, | |
828 | .size = 0x0800000 | |
829 | }, | |
830 | { | |
831 | .voff = FFB_SFB422D_VOFF, | |
832 | .poff = FFB_SFB422D_POFF, | |
833 | .size = 0x0800000 | |
834 | }, | |
835 | { .size = 0 } | |
836 | }; | |
837 | ||
216d526c | 838 | static int ffb_mmap(struct fb_info *info, struct vm_area_struct *vma) |
1da177e4 LT |
839 | { |
840 | struct ffb_par *par = (struct ffb_par *)info->par; | |
841 | ||
842 | return sbusfb_mmap_helper(ffb_mmap_map, | |
843 | par->physbase, par->fbsize, | |
844 | 0, vma); | |
845 | } | |
846 | ||
67a6680d | 847 | static int ffb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
848 | { |
849 | struct ffb_par *par = (struct ffb_par *) info->par; | |
850 | ||
851 | return sbusfb_ioctl_helper(cmd, arg, info, | |
852 | FBTYPE_CREATOR, 24, par->fbsize); | |
853 | } | |
854 | ||
855 | /* | |
856 | * Initialisation | |
857 | */ | |
858 | ||
859 | static void | |
860 | ffb_init_fix(struct fb_info *info) | |
861 | { | |
862 | struct ffb_par *par = (struct ffb_par *)info->par; | |
863 | const char *ffb_type_name; | |
864 | ||
865 | if (!(par->flags & FFB_FLAG_AFB)) { | |
866 | if ((par->board_type & 0x7) == 0x3) | |
867 | ffb_type_name = "Creator 3D"; | |
868 | else | |
869 | ffb_type_name = "Creator"; | |
870 | } else | |
871 | ffb_type_name = "Elite 3D"; | |
872 | ||
873 | strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id)); | |
874 | ||
875 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
876 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
877 | ||
878 | /* Framebuffer length is the same regardless of resolution. */ | |
879 | info->fix.line_length = 8192; | |
880 | ||
881 | info->fix.accel = FB_ACCEL_SUN_CREATOR; | |
882 | } | |
883 | ||
1da177e4 LT |
884 | struct all_info { |
885 | struct fb_info info; | |
886 | struct ffb_par par; | |
887 | u32 pseudo_palette[256]; | |
1da177e4 | 888 | }; |
1da177e4 | 889 | |
50312ce9 | 890 | static int ffb_init_one(struct of_device *op) |
1da177e4 | 891 | { |
50312ce9 DM |
892 | struct device_node *dp = op->node; |
893 | struct ffb_fbc __iomem *fbc; | |
894 | struct ffb_dac __iomem *dac; | |
1da177e4 | 895 | struct all_info *all; |
50312ce9 | 896 | int err; |
1da177e4 | 897 | |
50312ce9 DM |
898 | all = kzalloc(sizeof(*all), GFP_KERNEL); |
899 | if (!all) | |
900 | return -ENOMEM; | |
1da177e4 | 901 | |
50312ce9 DM |
902 | spin_lock_init(&all->par.lock); |
903 | all->par.fbc = of_ioremap(&op->resource[2], 0, | |
904 | sizeof(struct ffb_fbc), "ffb fbc"); | |
905 | if (!all->par.fbc) { | |
906 | kfree(all); | |
907 | return -ENOMEM; | |
1da177e4 LT |
908 | } |
909 | ||
50312ce9 DM |
910 | all->par.dac = of_ioremap(&op->resource[1], 0, |
911 | sizeof(struct ffb_dac), "ffb dac"); | |
912 | if (!all->par.dac) { | |
913 | of_iounmap(all->par.fbc, sizeof(struct ffb_fbc)); | |
914 | kfree(all); | |
915 | return -ENOMEM; | |
1da177e4 | 916 | } |
1da177e4 | 917 | |
1da177e4 | 918 | all->par.rop_cache = FFB_ROP_NEW; |
50312ce9 | 919 | all->par.physbase = op->resource[0].start; |
1da177e4 LT |
920 | |
921 | /* Don't mention copyarea, so SCROLL_REDRAW is always | |
922 | * used. It is the fastest on this chip. | |
923 | */ | |
924 | all->info.flags = (FBINFO_DEFAULT | | |
925 | /* FBINFO_HWACCEL_COPYAREA | */ | |
926 | FBINFO_HWACCEL_FILLRECT | | |
927 | FBINFO_HWACCEL_IMAGEBLIT); | |
928 | all->info.fbops = &ffb_ops; | |
929 | all->info.screen_base = (char *) all->par.physbase + FFB_DFB24_POFF; | |
930 | all->info.par = &all->par; | |
931 | all->info.pseudo_palette = all->pseudo_palette; | |
932 | ||
50312ce9 | 933 | sbusfb_fill_var(&all->info.var, dp->node, 32); |
1da177e4 LT |
934 | all->par.fbsize = PAGE_ALIGN(all->info.var.xres * |
935 | all->info.var.yres * | |
936 | 4); | |
937 | ffb_fixup_var_rgb(&all->info.var); | |
938 | ||
939 | all->info.var.accel_flags = FB_ACCELF_TEXT; | |
940 | ||
50312ce9 | 941 | if (!strcmp(dp->name, "SUNW,afb")) |
1da177e4 LT |
942 | all->par.flags |= FFB_FLAG_AFB; |
943 | ||
50312ce9 | 944 | all->par.board_type = of_getintprop_default(dp, "board_type", 0); |
1da177e4 LT |
945 | |
946 | fbc = all->par.fbc; | |
50312ce9 | 947 | if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) |
1da177e4 LT |
948 | upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr); |
949 | ||
950 | ffb_switch_from_graph(&all->par); | |
951 | ||
952 | dac = all->par.dac; | |
953 | upa_writel(0x8000, &dac->type); | |
954 | all->par.dac_rev = upa_readl(&dac->value) >> 0x1c; | |
955 | ||
956 | /* Elite3D has different DAC revision numbering, and no DAC revisions | |
957 | * have the reversed meaning of cursor enable. | |
958 | */ | |
959 | if (all->par.flags & FFB_FLAG_AFB) | |
960 | all->par.dac_rev = 10; | |
961 | ||
962 | /* Unblank it just to be sure. When there are multiple | |
963 | * FFB/AFB cards in the system, or it is not the OBP | |
964 | * chosen console, it will have video outputs off in | |
965 | * the DAC. | |
966 | */ | |
967 | ffb_blank(0, &all->info); | |
968 | ||
969 | if (fb_alloc_cmap(&all->info.cmap, 256, 0)) { | |
970 | printk(KERN_ERR "ffb: Could not allocate color map.\n"); | |
971 | kfree(all); | |
50312ce9 | 972 | return -ENOMEM; |
1da177e4 LT |
973 | } |
974 | ||
975 | ffb_init_fix(&all->info); | |
976 | ||
50312ce9 DM |
977 | err = register_framebuffer(&all->info); |
978 | if (err < 0) { | |
1da177e4 LT |
979 | printk(KERN_ERR "ffb: Could not register framebuffer.\n"); |
980 | fb_dealloc_cmap(&all->info.cmap); | |
981 | kfree(all); | |
50312ce9 | 982 | return err; |
1da177e4 LT |
983 | } |
984 | ||
50312ce9 | 985 | dev_set_drvdata(&op->dev, all); |
1da177e4 | 986 | |
50312ce9 DM |
987 | printk("%s: %s at %016lx, type %d, DAC revision %d\n", |
988 | dp->full_name, | |
1da177e4 | 989 | ((all->par.flags & FFB_FLAG_AFB) ? "AFB" : "FFB"), |
50312ce9 DM |
990 | all->par.physbase, all->par.board_type, all->par.dac_rev); |
991 | ||
992 | return 0; | |
1da177e4 LT |
993 | } |
994 | ||
50312ce9 | 995 | static int __devinit ffb_probe(struct of_device *dev, const struct of_device_id *match) |
1da177e4 | 996 | { |
50312ce9 DM |
997 | struct of_device *op = to_of_device(&dev->dev); |
998 | ||
999 | return ffb_init_one(op); | |
1da177e4 LT |
1000 | } |
1001 | ||
50312ce9 | 1002 | static int __devexit ffb_remove(struct of_device *dev) |
1da177e4 | 1003 | { |
50312ce9 | 1004 | struct all_info *all = dev_get_drvdata(&dev->dev); |
1da177e4 | 1005 | |
50312ce9 DM |
1006 | unregister_framebuffer(&all->info); |
1007 | fb_dealloc_cmap(&all->info.cmap); | |
1da177e4 | 1008 | |
50312ce9 DM |
1009 | of_iounmap(all->par.fbc, sizeof(struct ffb_fbc)); |
1010 | of_iounmap(all->par.dac, sizeof(struct ffb_dac)); | |
1da177e4 | 1011 | |
50312ce9 DM |
1012 | kfree(all); |
1013 | ||
1014 | dev_set_drvdata(&dev->dev, NULL); | |
1da177e4 LT |
1015 | |
1016 | return 0; | |
1017 | } | |
1018 | ||
50312ce9 DM |
1019 | static struct of_device_id ffb_match[] = { |
1020 | { | |
1021 | .name = "SUNW,ffb", | |
1022 | }, | |
1023 | { | |
1024 | .name = "SUNW,afb", | |
1025 | }, | |
1026 | {}, | |
1027 | }; | |
1028 | MODULE_DEVICE_TABLE(of, ffb_match); | |
1029 | ||
1030 | static struct of_platform_driver ffb_driver = { | |
1031 | .name = "ffb", | |
1032 | .match_table = ffb_match, | |
1033 | .probe = ffb_probe, | |
1034 | .remove = __devexit_p(ffb_remove), | |
1035 | }; | |
1da177e4 | 1036 | |
50312ce9 DM |
1037 | int __init ffb_init(void) |
1038 | { | |
1039 | if (fb_get_options("ffb", NULL)) | |
1040 | return -ENODEV; | |
1da177e4 | 1041 | |
50312ce9 | 1042 | return of_register_driver(&ffb_driver, &of_bus_type); |
1da177e4 LT |
1043 | } |
1044 | ||
50312ce9 | 1045 | void __exit ffb_exit(void) |
1da177e4 | 1046 | { |
50312ce9 | 1047 | of_unregister_driver(&ffb_driver); |
1da177e4 LT |
1048 | } |
1049 | ||
1050 | module_init(ffb_init); | |
1da177e4 | 1051 | module_exit(ffb_exit); |
1da177e4 LT |
1052 | |
1053 | MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets"); | |
50312ce9 DM |
1054 | MODULE_AUTHOR("David S. Miller <davem@davemloft.net>"); |
1055 | MODULE_VERSION("2.0"); | |
1da177e4 | 1056 | MODULE_LICENSE("GPL"); |