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[SPARC]: Fix RTC compat ioctl kernel log spam.
[deliverable/linux.git] / drivers / video / ffb.c
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1da177e4
LT		 1/* ffb.c: Creator/Elite3D frame buffer driver
2 *
3 * Copyright (C) 2003 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
5 *
6 * Driver layout based loosely on tgafb.c, see that file for credits.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/errno.h>
12#include <linux/string.h>
13#include <linux/slab.h>
14#include <linux/delay.h>
15#include <linux/init.h>
16#include <linux/fb.h>
17#include <linux/mm.h>
18#include <linux/timer.h>
19
20#include <asm/io.h>
21#include <asm/upa.h>
22#include <asm/oplib.h>
23#include <asm/fbio.h>
24
25#include "sbuslib.h"
26
27/*
28 * Local functions.
29 */
30
31static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned,
32 unsigned, struct fb_info *);
33static int ffb_blank(int, struct fb_info *);
34static void ffb_init_fix(struct fb_info *);
35
36static void ffb_imageblit(struct fb_info *, const struct fb_image *);
37static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *);
38static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *);
39static int ffb_sync(struct fb_info *);
40static int ffb_mmap(struct fb_info *, struct file *, struct vm_area_struct *);
41static int ffb_ioctl(struct inode *, struct file *, unsigned int,
42 unsigned long, struct fb_info *);
43static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *);
44
45/*
46 * Frame buffer operations
47 */
48
49static struct fb_ops ffb_ops = {
50 .owner = THIS_MODULE,
51 .fb_setcolreg = ffb_setcolreg,
52 .fb_blank = ffb_blank,
53 .fb_pan_display = ffb_pan_display,
54 .fb_fillrect = ffb_fillrect,
55 .fb_copyarea = ffb_copyarea,
56 .fb_imageblit = ffb_imageblit,
57 .fb_sync = ffb_sync,
58 .fb_mmap = ffb_mmap,
59 .fb_ioctl = ffb_ioctl,
1da177e4
LT		 60};
61
62/* Register layout and definitions */
63#define FFB_SFB8R_VOFF 0x00000000
64#define FFB_SFB8G_VOFF 0x00400000
65#define FFB_SFB8B_VOFF 0x00800000
66#define FFB_SFB8X_VOFF 0x00c00000
67#define FFB_SFB32_VOFF 0x01000000
68#define FFB_SFB64_VOFF 0x02000000
69#define FFB_FBC_REGS_VOFF 0x04000000
70#define FFB_BM_FBC_REGS_VOFF 0x04002000
71#define FFB_DFB8R_VOFF 0x04004000
72#define FFB_DFB8G_VOFF 0x04404000
73#define FFB_DFB8B_VOFF 0x04804000
74#define FFB_DFB8X_VOFF 0x04c04000
75#define FFB_DFB24_VOFF 0x05004000
76#define FFB_DFB32_VOFF 0x06004000
77#define FFB_DFB422A_VOFF 0x07004000 /* DFB 422 mode write to A */
78#define FFB_DFB422AD_VOFF 0x07804000 /* DFB 422 mode with line doubling */
79#define FFB_DFB24B_VOFF 0x08004000 /* DFB 24bit mode write to B */
80#define FFB_DFB422B_VOFF 0x09004000 /* DFB 422 mode write to B */
81#define FFB_DFB422BD_VOFF 0x09804000 /* DFB 422 mode with line doubling */
82#define FFB_SFB16Z_VOFF 0x0a004000 /* 16bit mode Z planes */
83#define FFB_SFB8Z_VOFF 0x0a404000 /* 8bit mode Z planes */
84#define FFB_SFB422_VOFF 0x0ac04000 /* SFB 422 mode write to A/B */
85#define FFB_SFB422D_VOFF 0x0b404000 /* SFB 422 mode with line doubling */
86#define FFB_FBC_KREGS_VOFF 0x0bc04000
87#define FFB_DAC_VOFF 0x0bc06000
88#define FFB_PROM_VOFF 0x0bc08000
89#define FFB_EXP_VOFF 0x0bc18000
90
91#define FFB_SFB8R_POFF 0x04000000UL
92#define FFB_SFB8G_POFF 0x04400000UL
93#define FFB_SFB8B_POFF 0x04800000UL
94#define FFB_SFB8X_POFF 0x04c00000UL
95#define FFB_SFB32_POFF 0x05000000UL
96#define FFB_SFB64_POFF 0x06000000UL
97#define FFB_FBC_REGS_POFF 0x00600000UL
98#define FFB_BM_FBC_REGS_POFF 0x00600000UL
99#define FFB_DFB8R_POFF 0x01000000UL
100#define FFB_DFB8G_POFF 0x01400000UL
101#define FFB_DFB8B_POFF 0x01800000UL
102#define FFB_DFB8X_POFF 0x01c00000UL
103#define FFB_DFB24_POFF 0x02000000UL
104#define FFB_DFB32_POFF 0x03000000UL
105#define FFB_FBC_KREGS_POFF 0x00610000UL
106#define FFB_DAC_POFF 0x00400000UL
107#define FFB_PROM_POFF 0x00000000UL
108#define FFB_EXP_POFF 0x00200000UL
109#define FFB_DFB422A_POFF 0x09000000UL
110#define FFB_DFB422AD_POFF 0x09800000UL
111#define FFB_DFB24B_POFF 0x0a000000UL
112#define FFB_DFB422B_POFF 0x0b000000UL
113#define FFB_DFB422BD_POFF 0x0b800000UL
114#define FFB_SFB16Z_POFF 0x0c800000UL
115#define FFB_SFB8Z_POFF 0x0c000000UL
116#define FFB_SFB422_POFF 0x0d000000UL
117#define FFB_SFB422D_POFF 0x0d800000UL
118
119/* Draw operations */
120#define FFB_DRAWOP_DOT 0x00
121#define FFB_DRAWOP_AADOT 0x01
122#define FFB_DRAWOP_BRLINECAP 0x02
123#define FFB_DRAWOP_BRLINEOPEN 0x03
124#define FFB_DRAWOP_DDLINE 0x04
125#define FFB_DRAWOP_AALINE 0x05
126#define FFB_DRAWOP_TRIANGLE 0x06
127#define FFB_DRAWOP_POLYGON 0x07
128#define FFB_DRAWOP_RECTANGLE 0x08
129#define FFB_DRAWOP_FASTFILL 0x09
130#define FFB_DRAWOP_BCOPY 0x0a
131#define FFB_DRAWOP_VSCROLL 0x0b
132
133/* Pixel processor control */
134/* Force WID */
135#define FFB_PPC_FW_DISABLE 0x800000
136#define FFB_PPC_FW_ENABLE 0xc00000
137/* Auxiliary clip */
138#define FFB_PPC_ACE_DISABLE 0x040000
139#define FFB_PPC_ACE_AUX_SUB 0x080000
140#define FFB_PPC_ACE_AUX_ADD 0x0c0000
141/* Depth cue */
142#define FFB_PPC_DCE_DISABLE 0x020000
143#define FFB_PPC_DCE_ENABLE 0x030000
144/* Alpha blend */
145#define FFB_PPC_ABE_DISABLE 0x008000
146#define FFB_PPC_ABE_ENABLE 0x00c000
147/* View clip */
148#define FFB_PPC_VCE_DISABLE 0x001000
149#define FFB_PPC_VCE_2D 0x002000
150#define FFB_PPC_VCE_3D 0x003000
151/* Area pattern */
152#define FFB_PPC_APE_DISABLE 0x000800
153#define FFB_PPC_APE_ENABLE 0x000c00
154/* Transparent background */
155#define FFB_PPC_TBE_OPAQUE 0x000200
156#define FFB_PPC_TBE_TRANSPARENT 0x000300
157/* Z source */
158#define FFB_PPC_ZS_VAR 0x000080
159#define FFB_PPC_ZS_CONST 0x0000c0
160/* Y source */
161#define FFB_PPC_YS_VAR 0x000020
162#define FFB_PPC_YS_CONST 0x000030
163/* X source */
164#define FFB_PPC_XS_WID 0x000004
165#define FFB_PPC_XS_VAR 0x000008
166#define FFB_PPC_XS_CONST 0x00000c
167/* Color (BGR) source */
168#define FFB_PPC_CS_VAR 0x000002
169#define FFB_PPC_CS_CONST 0x000003
170
171#define FFB_ROP_NEW 0x83
172#define FFB_ROP_OLD 0x85
173#define FFB_ROP_NEW_XOR_OLD 0x86
174
175#define FFB_UCSR_FIFO_MASK 0x00000fff
176#define FFB_UCSR_FB_BUSY 0x01000000
177#define FFB_UCSR_RP_BUSY 0x02000000
178#define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY)
179#define FFB_UCSR_READ_ERR 0x40000000
180#define FFB_UCSR_FIFO_OVFL 0x80000000
181#define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL)
182
183struct ffb_fbc {
184 /* Next vertex registers */
185 u32 xxx1[3];
186 volatile u32 alpha;
187 volatile u32 red;
188 volatile u32 green;
189 volatile u32 blue;
190 volatile u32 depth;
191 volatile u32 y;
192 volatile u32 x;
193 u32 xxx2[2];
194 volatile u32 ryf;
195 volatile u32 rxf;
196 u32 xxx3[2];
197
198 volatile u32 dmyf;
199 volatile u32 dmxf;
200 u32 xxx4[2];
201 volatile u32 ebyi;
202 volatile u32 ebxi;
203 u32 xxx5[2];
204 volatile u32 by;
205 volatile u32 bx;
206 u32 dy;
207 u32 dx;
208 volatile u32 bh;
209 volatile u32 bw;
210 u32 xxx6[2];
211
212 u32 xxx7[32];
213
214 /* Setup unit vertex state register */
215 volatile u32 suvtx;
216 u32 xxx8[63];
217
218 /* Control registers */
219 volatile u32 ppc;
220 volatile u32 wid;
221 volatile u32 fg;
222 volatile u32 bg;
223 volatile u32 consty;
224 volatile u32 constz;
225 volatile u32 xclip;
226 volatile u32 dcss;
227 volatile u32 vclipmin;
228 volatile u32 vclipmax;
229 volatile u32 vclipzmin;
230 volatile u32 vclipzmax;
231 volatile u32 dcsf;
232 volatile u32 dcsb;
233 volatile u32 dczf;
234 volatile u32 dczb;
235
236 u32 xxx9;
237 volatile u32 blendc;
238 volatile u32 blendc1;
239 volatile u32 blendc2;
240 volatile u32 fbramitc;
241 volatile u32 fbc;
242 volatile u32 rop;
243 volatile u32 cmp;
244 volatile u32 matchab;
245 volatile u32 matchc;
246 volatile u32 magnab;
247 volatile u32 magnc;
248 volatile u32 fbcfg0;
249 volatile u32 fbcfg1;
250 volatile u32 fbcfg2;
251 volatile u32 fbcfg3;
252
253 u32 ppcfg;
254 volatile u32 pick;
255 volatile u32 fillmode;
256 volatile u32 fbramwac;
257 volatile u32 pmask;
258 volatile u32 xpmask;
259 volatile u32 ypmask;
260 volatile u32 zpmask;
261 volatile u32 clip0min;
262 volatile u32 clip0max;
263 volatile u32 clip1min;
264 volatile u32 clip1max;
265 volatile u32 clip2min;
266 volatile u32 clip2max;
267 volatile u32 clip3min;
268 volatile u32 clip3max;
269
270 /* New 3dRAM III support regs */
271 volatile u32 rawblend2;
272 volatile u32 rawpreblend;
273 volatile u32 rawstencil;
274 volatile u32 rawstencilctl;
275 volatile u32 threedram1;
276 volatile u32 threedram2;
277 volatile u32 passin;
278 volatile u32 rawclrdepth;
279 volatile u32 rawpmask;
280 volatile u32 rawcsrc;
281 volatile u32 rawmatch;
282 volatile u32 rawmagn;
283 volatile u32 rawropblend;
284 volatile u32 rawcmp;
285 volatile u32 rawwac;
286 volatile u32 fbramid;
287
288 volatile u32 drawop;
289 u32 xxx10[2];
290 volatile u32 fontlpat;
291 u32 xxx11;
292 volatile u32 fontxy;
293 volatile u32 fontw;
294 volatile u32 fontinc;
295 volatile u32 font;
296 u32 xxx12[3];
297 volatile u32 blend2;
298 volatile u32 preblend;
299 volatile u32 stencil;
300 volatile u32 stencilctl;
301
302 u32 xxx13[4];
303 volatile u32 dcss1;
304 volatile u32 dcss2;
305 volatile u32 dcss3;
306 volatile u32 widpmask;
307 volatile u32 dcs2;
308 volatile u32 dcs3;
309 volatile u32 dcs4;
310 u32 xxx14;
311 volatile u32 dcd2;
312 volatile u32 dcd3;
313 volatile u32 dcd4;
314 u32 xxx15;
315
316 volatile u32 pattern[32];
317
318 u32 xxx16[256];
319
320 volatile u32 devid;
321 u32 xxx17[63];
322
323 volatile u32 ucsr;
324 u32 xxx18[31];
325
326 volatile u32 mer;
327};
328
329struct ffb_dac {
330 volatile u32 type;
331 volatile u32 value;
332 volatile u32 type2;
333 volatile u32 value2;
334};
335
336struct ffb_par {
337 spinlock_t lock;
338 struct ffb_fbc *fbc;
339 struct ffb_dac *dac;
340
341 u32 flags;
342#define FFB_FLAG_AFB 0x00000001
343#define FFB_FLAG_BLANKED 0x00000002
344
345 u32 fg_cache __attribute__((aligned (8)));
346 u32 bg_cache;
347 u32 rop_cache;
348
349 int fifo_cache;
350
351 unsigned long physbase;
352 unsigned long fbsize;
353
354 char name[64];
355 int prom_node;
356 int prom_parent_node;
357 int dac_rev;
358 int board_type;
359 struct list_head list;
360};
361
362static void FFBFifo(struct ffb_par *par, int n)
363{
364 struct ffb_fbc *fbc;
365 int cache = par->fifo_cache;
366
367 if (cache - n < 0) {
368 fbc = par->fbc;
369 do { cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK) - 8;
370 } while (cache - n < 0);
371 }
372 par->fifo_cache = cache - n;
373}
374
375static void FFBWait(struct ffb_par *par)
376{
377 struct ffb_fbc *fbc;
378 int limit = 10000;
379
380 fbc = par->fbc;
381 do {
382 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0)
383 break;
384 if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) {
385 upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
386 }
387 udelay(10);
388 } while(--limit > 0);
389}
390
391static int ffb_sync(struct fb_info *p)
392{
393 struct ffb_par *par = (struct ffb_par *) p->par;
394
395 FFBWait(par);
396 return 0;
397}
398
399static __inline__ void ffb_rop(struct ffb_par *par, u32 rop)
400{
401 if (par->rop_cache != rop) {
402 FFBFifo(par, 1);
403 upa_writel(rop, &par->fbc->rop);
404 par->rop_cache = rop;
405 }
406}
407
408static void ffb_switch_from_graph(struct ffb_par *par)
409{
410 struct ffb_fbc *fbc = par->fbc;
411 struct ffb_dac *dac = par->dac;
412 unsigned long flags;
413
414 spin_lock_irqsave(&par->lock, flags);
415 FFBWait(par);
416 par->fifo_cache = 0;
417 FFBFifo(par, 7);
418 upa_writel(FFB_PPC_VCE_DISABLE|FFB_PPC_TBE_OPAQUE|
419 FFB_PPC_APE_DISABLE|FFB_PPC_CS_CONST,
420 &fbc->ppc);
421 upa_writel(0x2000707f, &fbc->fbc);
422 upa_writel(par->rop_cache, &fbc->rop);
423 upa_writel(0xffffffff, &fbc->pmask);
424 upa_writel((1 << 16) | (0 << 0), &fbc->fontinc);
425 upa_writel(par->fg_cache, &fbc->fg);
426 upa_writel(par->bg_cache, &fbc->bg);
427 FFBWait(par);
428
429 /* Disable cursor. */
430 upa_writel(0x100, &dac->type2);
431 if (par->dac_rev <= 2)
432 upa_writel(0, &dac->value2);
433 else
434 upa_writel(3, &dac->value2);
435
436 spin_unlock_irqrestore(&par->lock, flags);
437}
438
439static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
440{
441 struct ffb_par *par = (struct ffb_par *) info->par;
442
443 /* We just use this to catch switches out of
444 * graphics mode.
445 */
446 ffb_switch_from_graph(par);
447
448 if (var->xoffset || var->yoffset || var->vmode)
449 return -EINVAL;
450 return 0;
451}
452
453/**
454 * ffb_fillrect - REQUIRED function. Can use generic routines if
455 * non acclerated hardware and packed pixel based.
456 * Draws a rectangle on the screen.
457 *
458 * @info: frame buffer structure that represents a single frame buffer
459 * @rect: structure defining the rectagle and operation.
460 */
461static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
462{
463 struct ffb_par *par = (struct ffb_par *) info->par;
464 struct ffb_fbc *fbc = par->fbc;
465 unsigned long flags;
466 u32 fg;
467
468 if (rect->rop != ROP_COPY && rect->rop != ROP_XOR)
469 BUG();
470
471 fg = ((u32 *)info->pseudo_palette)[rect->color];
472
473 spin_lock_irqsave(&par->lock, flags);
474
475 if (fg != par->fg_cache) {
476 FFBFifo(par, 1);
477 upa_writel(fg, &fbc->fg);
478 par->fg_cache = fg;
479 }
480
481 ffb_rop(par, (rect->rop == ROP_COPY ?
482 FFB_ROP_NEW :
483 FFB_ROP_NEW_XOR_OLD));
484
485 FFBFifo(par, 5);
486 upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop);
487 upa_writel(rect->dy, &fbc->by);
488 upa_writel(rect->dx, &fbc->bx);
489 upa_writel(rect->height, &fbc->bh);
490 upa_writel(rect->width, &fbc->bw);
491
492 spin_unlock_irqrestore(&par->lock, flags);
493}
494
495/**
496 * ffb_copyarea - REQUIRED function. Can use generic routines if
497 * non acclerated hardware and packed pixel based.
498 * Copies on area of the screen to another area.
499 *
500 * @info: frame buffer structure that represents a single frame buffer
501 * @area: structure defining the source and destination.
502 */
503
504static void
505ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
506{
507 struct ffb_par *par = (struct ffb_par *) info->par;
508 struct ffb_fbc *fbc = par->fbc;
509 unsigned long flags;
510
511 if (area->dx != area->sx ||
512 area->dy == area->sy) {
513 cfb_copyarea(info, area);
514 return;
515 }
516
517 spin_lock_irqsave(&par->lock, flags);
518
519 ffb_rop(par, FFB_ROP_OLD);
520
521 FFBFifo(par, 7);
522 upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop);
523 upa_writel(area->sy, &fbc->by);
524 upa_writel(area->sx, &fbc->bx);
525 upa_writel(area->dy, &fbc->dy);
526 upa_writel(area->dx, &fbc->dx);
527 upa_writel(area->height, &fbc->bh);
528 upa_writel(area->width, &fbc->bw);
529
530 spin_unlock_irqrestore(&par->lock, flags);
531}
532
533/**
534 * ffb_imageblit - REQUIRED function. Can use generic routines if
535 * non acclerated hardware and packed pixel based.
536 * Copies a image from system memory to the screen.
537 *
538 * @info: frame buffer structure that represents a single frame buffer
539 * @image: structure defining the image.
540 */
541static void ffb_imageblit(struct fb_info *info, const struct fb_image *image)
542{
543 struct ffb_par *par = (struct ffb_par *) info->par;
544 struct ffb_fbc *fbc = par->fbc;
545 const u8 *data = image->data;
546 unsigned long flags;
547 u32 fg, bg, xy;
548 u64 fgbg;
549 int i, width, stride;
550
551 if (image->depth > 1) {
552 cfb_imageblit(info, image);
553 return;
554 }
555
556 fg = ((u32 *)info->pseudo_palette)[image->fg_color];
557 bg = ((u32 *)info->pseudo_palette)[image->bg_color];
558 fgbg = ((u64) fg << 32) | (u64) bg;
559 xy = (image->dy << 16) | image->dx;
560 width = image->width;
561 stride = ((width + 7) >> 3);
562
563 spin_lock_irqsave(&par->lock, flags);
564
565 if (fgbg != *(u64 *)&par->fg_cache) {
566 FFBFifo(par, 2);
567 upa_writeq(fgbg, &fbc->fg);
568 *(u64 *)&par->fg_cache = fgbg;
569 }
570
571 if (width >= 32) {
572 FFBFifo(par, 1);
573 upa_writel(32, &fbc->fontw);
574 }
575
576 while (width >= 32) {
577 const u8 *next_data = data + 4;
578
579 FFBFifo(par, 1);
580 upa_writel(xy, &fbc->fontxy);
581 xy += (32 << 0);
582
583 for (i = 0; i < image->height; i++) {
584 u32 val = (((u32)data[0] << 24) |
585 ((u32)data[1] << 16) |
586 ((u32)data[2] << 8) |
587 ((u32)data[3] << 0));
588 FFBFifo(par, 1);
589 upa_writel(val, &fbc->font);
590
591 data += stride;
592 }
593
594 data = next_data;
595 width -= 32;
596 }
597
598 if (width) {
599 FFBFifo(par, 2);
600 upa_writel(width, &fbc->fontw);
601 upa_writel(xy, &fbc->fontxy);
602
603 for (i = 0; i < image->height; i++) {
604 u32 val = (((u32)data[0] << 24) |
605 ((u32)data[1] << 16) |
606 ((u32)data[2] << 8) |
607 ((u32)data[3] << 0));
608 FFBFifo(par, 1);
609 upa_writel(val, &fbc->font);
610
611 data += stride;
612 }
613 }
614
615 spin_unlock_irqrestore(&par->lock, flags);
616}
617
618static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var)
619{
620 var->red.offset = 0;
621 var->red.length = 8;
622 var->green.offset = 8;
623 var->green.length = 8;
624 var->blue.offset = 16;
625 var->blue.length = 8;
626 var->transp.offset = 0;
627 var->transp.length = 0;
628}
629
630/**
631 * ffb_setcolreg - Optional function. Sets a color register.
632 * @regno: boolean, 0 copy local, 1 get_user() function
633 * @red: frame buffer colormap structure
634 * @green: The green value which can be up to 16 bits wide
635 * @blue: The blue value which can be up to 16 bits wide.
636 * @transp: If supported the alpha value which can be up to 16 bits wide.
637 * @info: frame buffer info structure
638 */
639static int ffb_setcolreg(unsigned regno,
640 unsigned red, unsigned green, unsigned blue,
641 unsigned transp, struct fb_info *info)
642{
643 u32 value;
644
645 if (regno >= 256)
646 return 1;
647
648 red >>= 8;
649 green >>= 8;
650 blue >>= 8;
651
652 value = (blue << 16) | (green << 8) | red;
653 ((u32 *)info->pseudo_palette)[regno] = value;
654
655 return 0;
656}
657
658/**
659 * ffb_blank - Optional function. Blanks the display.
660 * @blank_mode: the blank mode we want.
661 * @info: frame buffer structure that represents a single frame buffer
662 */
663static int
664ffb_blank(int blank, struct fb_info *info)
665{
666 struct ffb_par *par = (struct ffb_par *) info->par;
667 struct ffb_dac *dac = par->dac;
668 unsigned long flags;
669 u32 tmp;
670
671 spin_lock_irqsave(&par->lock, flags);
672
673 FFBWait(par);
674
675 switch (blank) {
676 case FB_BLANK_UNBLANK: /* Unblanking */
677 upa_writel(0x6000, &dac->type);
678 tmp = (upa_readl(&dac->value) | 0x1);
679 upa_writel(0x6000, &dac->type);
680 upa_writel(tmp, &dac->value);
681 par->flags &= ~FFB_FLAG_BLANKED;
682 break;
683
684 case FB_BLANK_NORMAL: /* Normal blanking */
685 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
686 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
687 case FB_BLANK_POWERDOWN: /* Poweroff */
688 upa_writel(0x6000, &dac->type);
689 tmp = (upa_readl(&dac->value) & ~0x1);
690 upa_writel(0x6000, &dac->type);
691 upa_writel(tmp, &dac->value);
692 par->flags |= FFB_FLAG_BLANKED;
693 break;
694 }
695
696 spin_unlock_irqrestore(&par->lock, flags);
697
698 return 0;
699}
700
701static struct sbus_mmap_map ffb_mmap_map[] = {
702 {
703 .voff = FFB_SFB8R_VOFF,
704 .poff = FFB_SFB8R_POFF,
705 .size = 0x0400000
706 },
707 {
708 .voff = FFB_SFB8G_VOFF,
709 .poff = FFB_SFB8G_POFF,
710 .size = 0x0400000
711 },
712 {
713 .voff = FFB_SFB8B_VOFF,
714 .poff = FFB_SFB8B_POFF,
715 .size = 0x0400000
716 },
717 {
718 .voff = FFB_SFB8X_VOFF,
719 .poff = FFB_SFB8X_POFF,
720 .size = 0x0400000
721 },
722 {
723 .voff = FFB_SFB32_VOFF,
724 .poff = FFB_SFB32_POFF,
725 .size = 0x1000000
726 },
727 {
728 .voff = FFB_SFB64_VOFF,
729 .poff = FFB_SFB64_POFF,
730 .size = 0x2000000
731 },
732 {
733 .voff = FFB_FBC_REGS_VOFF,
734 .poff = FFB_FBC_REGS_POFF,
735 .size = 0x0002000
736 },
737 {
738 .voff = FFB_BM_FBC_REGS_VOFF,
739 .poff = FFB_BM_FBC_REGS_POFF,
740 .size = 0x0002000
741 },
742 {
743 .voff = FFB_DFB8R_VOFF,
744 .poff = FFB_DFB8R_POFF,
745 .size = 0x0400000
746 },
747 {
748 .voff = FFB_DFB8G_VOFF,
749 .poff = FFB_DFB8G_POFF,
750 .size = 0x0400000
751 },
752 {
753 .voff = FFB_DFB8B_VOFF,
754 .poff = FFB_DFB8B_POFF,
755 .size = 0x0400000
756 },
757 {
758 .voff = FFB_DFB8X_VOFF,
759 .poff = FFB_DFB8X_POFF,
760 .size = 0x0400000
761 },
762 {
763 .voff = FFB_DFB24_VOFF,
764 .poff = FFB_DFB24_POFF,
765 .size = 0x1000000
766 },
767 {
768 .voff = FFB_DFB32_VOFF,
769 .poff = FFB_DFB32_POFF,
770 .size = 0x1000000
771 },
772 {
773 .voff = FFB_FBC_KREGS_VOFF,
774 .poff = FFB_FBC_KREGS_POFF,
775 .size = 0x0002000
776 },
777 {
778 .voff = FFB_DAC_VOFF,
779 .poff = FFB_DAC_POFF,
780 .size = 0x0002000
781 },
782 {
783 .voff = FFB_PROM_VOFF,
784 .poff = FFB_PROM_POFF,
785 .size = 0x0010000
786 },
787 {
788 .voff = FFB_EXP_VOFF,
789 .poff = FFB_EXP_POFF,
790 .size = 0x0002000
791 },
792 {
793 .voff = FFB_DFB422A_VOFF,
794 .poff = FFB_DFB422A_POFF,
795 .size = 0x0800000
796 },
797 {
798 .voff = FFB_DFB422AD_VOFF,
799 .poff = FFB_DFB422AD_POFF,
800 .size = 0x0800000
801 },
802 {
803 .voff = FFB_DFB24B_VOFF,
804 .poff = FFB_DFB24B_POFF,
805 .size = 0x1000000
806 },
807 {
808 .voff = FFB_DFB422B_VOFF,
809 .poff = FFB_DFB422B_POFF,
810 .size = 0x0800000
811 },
812 {
813 .voff = FFB_DFB422BD_VOFF,
814 .poff = FFB_DFB422BD_POFF,
815 .size = 0x0800000
816 },
817 {
818 .voff = FFB_SFB16Z_VOFF,
819 .poff = FFB_SFB16Z_POFF,
820 .size = 0x0800000
821 },
822 {
823 .voff = FFB_SFB8Z_VOFF,
824 .poff = FFB_SFB8Z_POFF,
825 .size = 0x0800000
826 },
827 {
828 .voff = FFB_SFB422_VOFF,
829 .poff = FFB_SFB422_POFF,
830 .size = 0x0800000
831 },
832 {
833 .voff = FFB_SFB422D_VOFF,
834 .poff = FFB_SFB422D_POFF,
835 .size = 0x0800000
836 },
837 { .size = 0 }
838};
839
840static int ffb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
841{
842 struct ffb_par *par = (struct ffb_par *)info->par;
843
844 return sbusfb_mmap_helper(ffb_mmap_map,
845 par->physbase, par->fbsize,
846 0, vma);
847}
848
849static int ffb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
850 unsigned long arg, struct fb_info *info)
851{
852 struct ffb_par *par = (struct ffb_par *) info->par;
853
854 return sbusfb_ioctl_helper(cmd, arg, info,
855 FBTYPE_CREATOR, 24, par->fbsize);
856}
857
858/*
859 * Initialisation
860 */
861
862static void
863ffb_init_fix(struct fb_info *info)
864{
865 struct ffb_par *par = (struct ffb_par *)info->par;
866 const char *ffb_type_name;
867
868 if (!(par->flags & FFB_FLAG_AFB)) {
869 if ((par->board_type & 0x7) == 0x3)
870 ffb_type_name = "Creator 3D";
871 else
872 ffb_type_name = "Creator";
873 } else
874 ffb_type_name = "Elite 3D";
875
876 strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id));
877
878 info->fix.type = FB_TYPE_PACKED_PIXELS;
879 info->fix.visual = FB_VISUAL_TRUECOLOR;
880
881 /* Framebuffer length is the same regardless of resolution. */
882 info->fix.line_length = 8192;
883
884 info->fix.accel = FB_ACCEL_SUN_CREATOR;
885}
886
887static int ffb_apply_upa_parent_ranges(int parent,
888 struct linux_prom64_registers *regs)
889{
890 struct linux_prom64_ranges ranges[PROMREG_MAX];
891 char name[128];
892 int len, i;
893
894 prom_getproperty(parent, "name", name, sizeof(name));
895 if (strcmp(name, "upa") != 0)
896 return 0;
897
898 len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges));
899 if (len <= 0)
900 return 1;
901
902 len /= sizeof(struct linux_prom64_ranges);
903 for (i = 0; i < len; i++) {
904 struct linux_prom64_ranges *rng = &ranges[i];
905 u64 phys_addr = regs->phys_addr;
906
907 if (phys_addr >= rng->ot_child_base &&
908 phys_addr < (rng->ot_child_base + rng->or_size)) {
909 regs->phys_addr -= rng->ot_child_base;
910 regs->phys_addr += rng->ot_parent_base;
911 return 0;
912 }
913 }
914
915 return 1;
916}
917
918struct all_info {
919 struct fb_info info;
920 struct ffb_par par;
921 u32 pseudo_palette[256];
922 struct list_head list;
923};
924static LIST_HEAD(ffb_list);
925
926static void ffb_init_one(int node, int parent)
927{
928 struct linux_prom64_registers regs[2*PROMREG_MAX];
929 struct ffb_fbc *fbc;
930 struct ffb_dac *dac;
931 struct all_info *all;
932
933 if (prom_getproperty(node, "reg", (void *) regs, sizeof(regs)) <= 0) {
934 printk("ffb: Cannot get reg device node property.\n");
935 return;
936 }
937
938 if (ffb_apply_upa_parent_ranges(parent, &regs[0])) {
939 printk("ffb: Cannot apply parent ranges to regs.\n");
940 return;
941 }
942
943 all = kmalloc(sizeof(*all), GFP_KERNEL);
944 if (!all) {
945 printk(KERN_ERR "ffb: Cannot allocate memory.\n");
946 return;
947 }
948 memset(all, 0, sizeof(*all));
949
950 INIT_LIST_HEAD(&all->list);
951
952 spin_lock_init(&all->par.lock);
953 all->par.fbc = (struct ffb_fbc *)(regs[0].phys_addr + FFB_FBC_REGS_POFF);
954 all->par.dac = (struct ffb_dac *)(regs[0].phys_addr + FFB_DAC_POFF);
955 all->par.rop_cache = FFB_ROP_NEW;
956 all->par.physbase = regs[0].phys_addr;
957 all->par.prom_node = node;
958 all->par.prom_parent_node = parent;
959
960 /* Don't mention copyarea, so SCROLL_REDRAW is always
961 * used. It is the fastest on this chip.
962 */
963 all->info.flags = (FBINFO_DEFAULT |
964 /* FBINFO_HWACCEL_COPYAREA | */
965 FBINFO_HWACCEL_FILLRECT |
966 FBINFO_HWACCEL_IMAGEBLIT);
967 all->info.fbops = &ffb_ops;
968 all->info.screen_base = (char *) all->par.physbase + FFB_DFB24_POFF;
969 all->info.par = &all->par;
970 all->info.pseudo_palette = all->pseudo_palette;
971
972 sbusfb_fill_var(&all->info.var, all->par.prom_node, 32);
973 all->par.fbsize = PAGE_ALIGN(all->info.var.xres *
974 all->info.var.yres *
975 4);
976 ffb_fixup_var_rgb(&all->info.var);
977
978 all->info.var.accel_flags = FB_ACCELF_TEXT;
979
980 prom_getstring(node, "name", all->par.name, sizeof(all->par.name));
981 if (!strcmp(all->par.name, "SUNW,afb"))
982 all->par.flags |= FFB_FLAG_AFB;
983
984 all->par.board_type = prom_getintdefault(node, "board_type", 0);
985
986 fbc = all->par.fbc;
987 if((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0)
988 upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr);
989
990 ffb_switch_from_graph(&all->par);
991
992 dac = all->par.dac;
993 upa_writel(0x8000, &dac->type);
994 all->par.dac_rev = upa_readl(&dac->value) >> 0x1c;
995
996 /* Elite3D has different DAC revision numbering, and no DAC revisions
997 * have the reversed meaning of cursor enable.
998 */
999 if (all->par.flags & FFB_FLAG_AFB)
1000 all->par.dac_rev = 10;
1001
1002 /* Unblank it just to be sure. When there are multiple
1003 * FFB/AFB cards in the system, or it is not the OBP
1004 * chosen console, it will have video outputs off in
1005 * the DAC.
1006 */
1007 ffb_blank(0, &all->info);
1008
1009 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1010 printk(KERN_ERR "ffb: Could not allocate color map.\n");
1011 kfree(all);
1012 return;
1013 }
1014
1015 ffb_init_fix(&all->info);
1016
1017 if (register_framebuffer(&all->info) < 0) {
1018 printk(KERN_ERR "ffb: Could not register framebuffer.\n");
1019 fb_dealloc_cmap(&all->info.cmap);
1020 kfree(all);
1021 return;
1022 }
1023
1024 list_add(&all->list, &ffb_list);
1025
1026 printk("ffb: %s at %016lx type %d DAC %d\n",
1027 ((all->par.flags & FFB_FLAG_AFB) ? "AFB" : "FFB"),
1028 regs[0].phys_addr, all->par.board_type, all->par.dac_rev);
1029}
1030
1031static void ffb_scan_siblings(int root)
1032{
1033 int node, child;
1034
1035 child = prom_getchild(root);
1036 for (node = prom_searchsiblings(child, "SUNW,ffb"); node;
1037 node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb"))
1038 ffb_init_one(node, root);
1039 for (node = prom_searchsiblings(child, "SUNW,afb"); node;
1040 node = prom_searchsiblings(prom_getsibling(node), "SUNW,afb"))
1041 ffb_init_one(node, root);
1042}
1043
1044int __init ffb_init(void)
1045{
1046 int root;
1047
1048 if (fb_get_options("ffb", NULL))
1049 return -ENODEV;
1050
1051 ffb_scan_siblings(prom_root_node);
1052
1053 root = prom_getchild(prom_root_node);
1054 for (root = prom_searchsiblings(root, "upa"); root;
1055 root = prom_searchsiblings(prom_getsibling(root), "upa"))
1056 ffb_scan_siblings(root);
1057
1058 return 0;
1059}
1060
1061void __exit ffb_exit(void)
1062{
1063 struct list_head *pos, *tmp;
1064
1065 list_for_each_safe(pos, tmp, &ffb_list) {
1066 struct all_info *all = list_entry(pos, typeof(*all), list);
1067
1068 unregister_framebuffer(&all->info);
1069 fb_dealloc_cmap(&all->info.cmap);
1070 kfree(all);
1071 }
1072}
1073
1074int __init
1075ffb_setup(char *arg)
1076{
1077 /* No cmdline options yet... */
1078 return 0;
1079}
1080
1081module_init(ffb_init);
1082
1083#ifdef MODULE
1084module_exit(ffb_exit);
1085#endif
1086
1087MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets");
1088MODULE_AUTHOR("David S. Miller <davem@redhat.com>");
1089MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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