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drivers/video: fsl-diu-fb: use an enum for the AOI index
[deliverable/linux.git] / drivers / video / fsl-diu-fb.c
CommitLineData
9b53a9e2
YS		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Freescale DIU Frame Buffer device driver
5 *
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
10 *
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/uaccess.h>
32#include <linux/vmalloc.h>
b715f9f0 33#include <linux/spinlock.h>
9b53a9e2 34
9b53a9e2 35#include <sysdev/fsl_soc.h>
0814a979 36#include <linux/fsl-diu-fb.h>
8b856f04 37#include "edid.h"
9b53a9e2 38
b715f9f0
TT		 39#define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */
40 /* 1 for plane 0, 2 for plane 1&2 each */
41
42/* HW cursor parameters */
43#define MAX_CURS 32
44
45/* INT_STATUS/INT_MASK field descriptions */
46#define INT_VSYNC 0x01 /* Vsync interrupt */
47#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
48#define INT_UNDRUN 0x04 /* Under run exception interrupt */
49#define INT_PARERR 0x08 /* Display parameters error interrupt */
50#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
51
52/* Panels'operation modes */
53#define MFB_TYPE_OUTPUT 0 /* Panel output to display */
54#define MFB_TYPE_OFF 1 /* Panel off */
55#define MFB_TYPE_WB 2 /* Panel written back to memory */
56#define MFB_TYPE_TEST 3 /* Panel generate color bar */
57
58struct diu_hw {
59 struct diu __iomem *diu_reg;
60 spinlock_t reg_lock;
61 unsigned int mode; /* DIU operation mode */
62};
63
64struct diu_addr {
65 void *vaddr; /* Virtual address */
66 dma_addr_t paddr; /* Physical address */
67 __u32 offset;
68};
69
70struct diu_pool {
71 struct diu_addr ad;
72 struct diu_addr gamma;
73 struct diu_addr pallete;
74 struct diu_addr cursor;
75};
76
9b53a9e2 77/*
63cf8df4
TT		 78 * List of supported video modes
79 *
760af8f8
TT		 80 * The first entry is the default video mode. The remain entries are in
81 * order if increasing resolution and frequency. The 320x240-60 mode is
82 * the initial AOI for the second and third planes.
9b53a9e2 83 */
9b53a9e2
YS		 84static struct fb_videomode __devinitdata fsl_diu_mode_db[] = {
85 {
9b53a9e2
YS		 86 .refresh = 60,
87 .xres = 1024,
88 .yres = 768,
89 .pixclock = 15385,
90 .left_margin = 160,
91 .right_margin = 24,
92 .upper_margin = 29,
93 .lower_margin = 3,
94 .hsync_len = 136,
95 .vsync_len = 6,
96 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
97 .vmode = FB_VMODE_NONINTERLACED
98 },
99 {
760af8f8
TT		 100 .refresh = 60,
101 .xres = 320,
102 .yres = 240,
103 .pixclock = 79440,
104 .left_margin = 16,
105 .right_margin = 16,
106 .upper_margin = 16,
107 .lower_margin = 5,
108 .hsync_len = 48,
109 .vsync_len = 1,
110 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
111 .vmode = FB_VMODE_NONINTERLACED
112 },
113 {
114 .refresh = 60,
115 .xres = 640,
116 .yres = 480,
117 .pixclock = 39722,
118 .left_margin = 48,
119 .right_margin = 16,
120 .upper_margin = 33,
121 .lower_margin = 10,
122 .hsync_len = 96,
123 .vsync_len = 2,
124 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
125 .vmode = FB_VMODE_NONINTERLACED
126 },
127 {
128 .refresh = 72,
129 .xres = 640,
130 .yres = 480,
131 .pixclock = 32052,
132 .left_margin = 128,
133 .right_margin = 24,
134 .upper_margin = 28,
135 .lower_margin = 9,
136 .hsync_len = 40,
137 .vsync_len = 3,
138 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
139 .vmode = FB_VMODE_NONINTERLACED
140 },
141 {
142 .refresh = 75,
143 .xres = 640,
144 .yres = 480,
145 .pixclock = 31747,
146 .left_margin = 120,
147 .right_margin = 16,
148 .upper_margin = 16,
149 .lower_margin = 1,
150 .hsync_len = 64,
151 .vsync_len = 3,
152 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
153 .vmode = FB_VMODE_NONINTERLACED
154 },
155 {
156 .refresh = 90,
157 .xres = 640,
158 .yres = 480,
159 .pixclock = 25057,
160 .left_margin = 120,
161 .right_margin = 32,
162 .upper_margin = 14,
163 .lower_margin = 25,
164 .hsync_len = 40,
165 .vsync_len = 14,
166 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
167 .vmode = FB_VMODE_NONINTERLACED
168 },
169 {
170 .refresh = 100,
171 .xres = 640,
172 .yres = 480,
173 .pixclock = 22272,
174 .left_margin = 48,
175 .right_margin = 32,
176 .upper_margin = 17,
177 .lower_margin = 22,
178 .hsync_len = 128,
179 .vsync_len = 12,
180 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
181 .vmode = FB_VMODE_NONINTERLACED
182 },
183 {
184 .refresh = 60,
185 .xres = 800,
186 .yres = 480,
187 .pixclock = 33805,
188 .left_margin = 96,
189 .right_margin = 24,
190 .upper_margin = 10,
191 .lower_margin = 3,
192 .hsync_len = 72,
193 .vsync_len = 7,
194 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
195 .vmode = FB_VMODE_NONINTERLACED
196 },
197 {
198 .refresh = 60,
199 .xres = 800,
200 .yres = 600,
201 .pixclock = 25000,
202 .left_margin = 88,
203 .right_margin = 40,
204 .upper_margin = 23,
205 .lower_margin = 1,
206 .hsync_len = 128,
207 .vsync_len = 4,
208 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
209 .vmode = FB_VMODE_NONINTERLACED
210 },
211 {
212 .refresh = 60,
213 .xres = 854,
214 .yres = 480,
215 .pixclock = 31518,
216 .left_margin = 104,
217 .right_margin = 16,
218 .upper_margin = 13,
219 .lower_margin = 1,
220 .hsync_len = 88,
221 .vsync_len = 3,
222 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
223 .vmode = FB_VMODE_NONINTERLACED
224 },
225 {
9b53a9e2
YS		 226 .refresh = 70,
227 .xres = 1024,
228 .yres = 768,
229 .pixclock = 16886,
230 .left_margin = 3,
231 .right_margin = 3,
232 .upper_margin = 2,
233 .lower_margin = 2,
234 .hsync_len = 40,
235 .vsync_len = 18,
236 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
237 .vmode = FB_VMODE_NONINTERLACED
238 },
239 {
9b53a9e2
YS		 240 .refresh = 75,
241 .xres = 1024,
242 .yres = 768,
243 .pixclock = 15009,
244 .left_margin = 3,
245 .right_margin = 3,
246 .upper_margin = 2,
247 .lower_margin = 2,
248 .hsync_len = 80,
249 .vsync_len = 32,
250 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
251 .vmode = FB_VMODE_NONINTERLACED
252 },
253 {
760af8f8
TT		 254 .refresh = 60,
255 .xres = 1280,
256 .yres = 480,
257 .pixclock = 18939,
258 .left_margin = 353,
259 .right_margin = 47,
260 .upper_margin = 39,
261 .lower_margin = 4,
262 .hsync_len = 8,
263 .vsync_len = 2,
264 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
265 .vmode = FB_VMODE_NONINTERLACED
266 },
267 {
268 .refresh = 60,
269 .xres = 1280,
270 .yres = 720,
271 .pixclock = 13426,
272 .left_margin = 192,
273 .right_margin = 64,
274 .upper_margin = 22,
275 .lower_margin = 1,
276 .hsync_len = 136,
277 .vsync_len = 3,
278 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
279 .vmode = FB_VMODE_NONINTERLACED
280 },
281 {
9b53a9e2
YS		 282 .refresh = 60,
283 .xres = 1280,
284 .yres = 1024,
285 .pixclock = 9375,
286 .left_margin = 38,
287 .right_margin = 128,
288 .upper_margin = 2,
289 .lower_margin = 7,
290 .hsync_len = 216,
291 .vsync_len = 37,
292 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
293 .vmode = FB_VMODE_NONINTERLACED
294 },
295 {
9b53a9e2
YS		 296 .refresh = 70,
297 .xres = 1280,
298 .yres = 1024,
299 .pixclock = 9380,
300 .left_margin = 6,
301 .right_margin = 6,
302 .upper_margin = 4,
303 .lower_margin = 4,
304 .hsync_len = 60,
305 .vsync_len = 94,
306 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
307 .vmode = FB_VMODE_NONINTERLACED
308 },
309 {
9b53a9e2
YS		 310 .refresh = 75,
311 .xres = 1280,
312 .yres = 1024,
313 .pixclock = 9380,
314 .left_margin = 6,
315 .right_margin = 6,
316 .upper_margin = 4,
317 .lower_margin = 4,
318 .hsync_len = 60,
319 .vsync_len = 15,
320 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
321 .vmode = FB_VMODE_NONINTERLACED
322 },
323 {
9b53a9e2 324 .refresh = 60,
760af8f8
TT		 325 .xres = 1920,
326 .yres = 1080,
327 .pixclock = 5787,
328 .left_margin = 328,
329 .right_margin = 120,
330 .upper_margin = 34,
331 .lower_margin = 1,
332 .hsync_len = 208,
333 .vsync_len = 3,
9b53a9e2
YS		 334 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
335 .vmode = FB_VMODE_NONINTERLACED
336 },
337};
338
760af8f8 339static char *fb_mode;
9b53a9e2 340static unsigned long default_bpp = 32;
7653aaab
TT		 341static enum fsl_diu_monitor_port monitor_port;
342static char *monitor_string;
9b53a9e2
YS		 343
344#if defined(CONFIG_NOT_COHERENT_CACHE)
345static u8 *coherence_data;
346static size_t coherence_data_size;
347static unsigned int d_cache_line_size;
348#endif
349
350static DEFINE_SPINLOCK(diu_lock);
351
352struct fsl_diu_data {
353 struct fb_info *fsl_diu_info[FSL_AOI_NUM - 1];
354 /*FSL_AOI_NUM has one dummy AOI */
355 struct device_attribute dev_attr;
356 struct diu_ad *dummy_ad;
357 void *dummy_aoi_virt;
358 unsigned int irq;
359 int fb_enabled;
7653aaab 360 enum fsl_diu_monitor_port monitor_port;
9b53a9e2
YS		 361};
362
2572df91
TT		 363enum mfb_index {
364 PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */
365 PLANE1_AOI0, /* Plane 1, first AOI */
366 PLANE1_AOI1, /* Plane 1, second AOI */
367 PLANE2_AOI0, /* Plane 2, first AOI */
368 PLANE2_AOI1, /* Plane 2, second AOI */
369};
370
9b53a9e2 371struct mfb_info {
2572df91 372 enum mfb_index index;
9b53a9e2
YS		 373 int type;
374 char *id;
375 int registered;
9b53a9e2
YS		 376 unsigned long pseudo_palette[16];
377 struct diu_ad *ad;
378 int cursor_reset;
379 unsigned char g_alpha;
380 unsigned int count;
381 int x_aoi_d; /* aoi display x offset to physical screen */
382 int y_aoi_d; /* aoi display y offset to physical screen */
383 struct fsl_diu_data *parent;
8b856f04 384 u8 *edid_data;
9b53a9e2
YS		 385};
386
387
388static struct mfb_info mfb_template[] = {
2572df91
TT		 389 {
390 .index = PLANE0,
4a85dc8b
TT		 391 .type = MFB_TYPE_OUTPUT,
392 .id = "Panel0",
393 .registered = 0,
394 .count = 0,
395 .x_aoi_d = 0,
396 .y_aoi_d = 0,
9b53a9e2 397 },
2572df91
TT		 398 {
399 .index = PLANE1_AOI0,
4a85dc8b
TT		 400 .type = MFB_TYPE_OUTPUT,
401 .id = "Panel1 AOI0",
402 .registered = 0,
403 .g_alpha = 0xff,
404 .count = 0,
405 .x_aoi_d = 0,
406 .y_aoi_d = 0,
9b53a9e2 407 },
2572df91
TT		 408 {
409 .index = PLANE1_AOI1,
4a85dc8b
TT		 410 .type = MFB_TYPE_OUTPUT,
411 .id = "Panel1 AOI1",
412 .registered = 0,
413 .g_alpha = 0xff,
414 .count = 0,
415 .x_aoi_d = 0,
416 .y_aoi_d = 480,
9b53a9e2 417 },
2572df91
TT		 418 {
419 .index = PLANE2_AOI0,
4a85dc8b
TT		 420 .type = MFB_TYPE_OUTPUT,
421 .id = "Panel2 AOI0",
422 .registered = 0,
423 .g_alpha = 0xff,
424 .count = 0,
425 .x_aoi_d = 640,
426 .y_aoi_d = 0,
9b53a9e2 427 },
2572df91
TT		 428 {
429 .index = PLANE2_AOI1,
4a85dc8b
TT		 430 .type = MFB_TYPE_OUTPUT,
431 .id = "Panel2 AOI1",
432 .registered = 0,
433 .g_alpha = 0xff,
434 .count = 0,
435 .x_aoi_d = 640,
436 .y_aoi_d = 480,
9b53a9e2
YS		 437 },
438};
439
440static struct diu_hw dr = {
441 .mode = MFB_MODE1,
442 .reg_lock = __SPIN_LOCK_UNLOCKED(diu_hw.reg_lock),
443};
444
445static struct diu_pool pool;
446
7653aaab
TT		 447/**
448 * fsl_diu_name_to_port - convert a port name to a monitor port enum
449 *
450 * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
451 * the enum fsl_diu_monitor_port that corresponds to that string.
452 *
453 * For compatibility with older versions, a number ("0", "1", or "2") is also
454 * supported.
455 *
456 * If the string is unknown, DVI is assumed.
457 *
458 * If the particular port is not supported by the platform, another port
459 * (platform-specific) is chosen instead.
460 */
461static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s)
462{
463 enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI;
464 unsigned long val;
465
466 if (s) {
467 if (!strict_strtoul(s, 10, &val) && (val <= 2))
468 port = (enum fsl_diu_monitor_port) val;
469 else if (strncmp(s, "lvds", 4) == 0)
470 port = FSL_DIU_PORT_LVDS;
471 else if (strncmp(s, "dlvds", 5) == 0)
472 port = FSL_DIU_PORT_DLVDS;
473 }
474
475 return diu_ops.valid_monitor_port(port);
476}
477
6b51d51a
TT		 478/**
479 * fsl_diu_alloc - allocate memory for the DIU
480 * @size: number of bytes to allocate
481 * @param: returned physical address of memory
482 *
483 * This function allocates a physically-contiguous block of memory.
9b53a9e2 484 */
6b51d51a 485static void *fsl_diu_alloc(size_t size, phys_addr_t *phys)
9b53a9e2
YS		 486{
487 void *virt;
488
6b51d51a 489 virt = alloc_pages_exact(size, GFP_DMA | __GFP_ZERO);
154152ae 490 if (virt)
9b53a9e2 491 *phys = virt_to_phys(virt);
9b53a9e2 492
9b53a9e2
YS		 493 return virt;
494}
495
6b51d51a
TT		 496/**
497 * fsl_diu_free - release DIU memory
498 * @virt: pointer returned by fsl_diu_alloc()
499 * @size: number of bytes allocated by fsl_diu_alloc()
500 *
501 * This function releases memory allocated by fsl_diu_alloc().
502 */
503static void fsl_diu_free(void *virt, size_t size)
9b53a9e2 504{
6b51d51a
TT		 505 if (virt && size)
506 free_pages_exact(virt, size);
9b53a9e2
YS		 507}
508
0d9dab39
AG		 509/*
510 * Workaround for failed writing desc register of planes.
511 * Needed with MPC5121 DIU rev 2.0 silicon.
512 */
513void wr_reg_wa(u32 *reg, u32 val)
514{
515 do {
516 out_be32(reg, val);
517 } while (in_be32(reg) != val);
518}
519
9b53a9e2
YS		 520static int fsl_diu_enable_panel(struct fb_info *info)
521{
522 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
523 struct diu *hw = dr.diu_reg;
524 struct diu_ad *ad = mfbi->ad;
525 struct fsl_diu_data *machine_data = mfbi->parent;
526 int res = 0;
527
9b53a9e2
YS		 528 if (mfbi->type != MFB_TYPE_OFF) {
529 switch (mfbi->index) {
2572df91 530 case PLANE0:
9b53a9e2 531 if (hw->desc[0] != ad->paddr)
0d9dab39 532 wr_reg_wa(&hw->desc[0], ad->paddr);
9b53a9e2 533 break;
2572df91 534 case PLANE1_AOI0:
9b53a9e2
YS		 535 cmfbi = machine_data->fsl_diu_info[2]->par;
536 if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
537 if (cmfbi->count > 0) /* AOI1 open */
538 ad->next_ad =
539 cpu_to_le32(cmfbi->ad->paddr);
540 else
541 ad->next_ad = 0;
0d9dab39 542 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2
YS		 543 }
544 break;
2572df91 545 case PLANE2_AOI0:
9b53a9e2
YS		 546 cmfbi = machine_data->fsl_diu_info[4]->par;
547 if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
548 if (cmfbi->count > 0) /* AOI1 open */
549 ad->next_ad =
550 cpu_to_le32(cmfbi->ad->paddr);
551 else
552 ad->next_ad = 0;
0d9dab39 553 wr_reg_wa(&hw->desc[2], ad->paddr);
9b53a9e2
YS		 554 }
555 break;
2572df91 556 case PLANE1_AOI1:
9b53a9e2
YS		 557 pmfbi = machine_data->fsl_diu_info[1]->par;
558 ad->next_ad = 0;
559 if (hw->desc[1] == machine_data->dummy_ad->paddr)
0d9dab39 560 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2
YS		 561 else /* AOI0 open */
562 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
563 break;
2572df91 564 case PLANE2_AOI1:
9b53a9e2
YS		 565 pmfbi = machine_data->fsl_diu_info[3]->par;
566 ad->next_ad = 0;
567 if (hw->desc[2] == machine_data->dummy_ad->paddr)
0d9dab39 568 wr_reg_wa(&hw->desc[2], ad->paddr);
9b53a9e2
YS		 569 else /* AOI0 was open */
570 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
571 break;
9b53a9e2
YS		 572 }
573 } else
574 res = -EINVAL;
575 return res;
576}
577
2572df91 578static void fsl_diu_disable_panel(struct fb_info *info)
9b53a9e2
YS		 579{
580 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
581 struct diu *hw = dr.diu_reg;
582 struct diu_ad *ad = mfbi->ad;
583 struct fsl_diu_data *machine_data = mfbi->parent;
9b53a9e2
YS		 584
585 switch (mfbi->index) {
2572df91 586 case PLANE0:
9b53a9e2 587 if (hw->desc[0] != machine_data->dummy_ad->paddr)
0d9dab39 588 wr_reg_wa(&hw->desc[0], machine_data->dummy_ad->paddr);
9b53a9e2 589 break;
2572df91 590 case PLANE1_AOI0:
9b53a9e2
YS		 591 cmfbi = machine_data->fsl_diu_info[2]->par;
592 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 593 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
9b53a9e2
YS		 594 /* move AOI1 to the first */
595 else /* AOI1 was closed */
0d9dab39 596 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 597 /* close AOI 0 */
598 break;
2572df91 599 case PLANE2_AOI0:
9b53a9e2
YS		 600 cmfbi = machine_data->fsl_diu_info[4]->par;
601 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 602 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
9b53a9e2
YS		 603 /* move AOI1 to the first */
604 else /* AOI1 was closed */
0d9dab39 605 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 606 /* close AOI 0 */
607 break;
2572df91 608 case PLANE1_AOI1:
9b53a9e2
YS		 609 pmfbi = machine_data->fsl_diu_info[1]->par;
610 if (hw->desc[1] != ad->paddr) {
611 /* AOI1 is not the first in the chain */
612 if (pmfbi->count > 0)
613 /* AOI0 is open, must be the first */
614 pmfbi->ad->next_ad = 0;
615 } else /* AOI1 is the first in the chain */
0d9dab39 616 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 617 /* close AOI 1 */
618 break;
2572df91 619 case PLANE2_AOI1:
9b53a9e2
YS		 620 pmfbi = machine_data->fsl_diu_info[3]->par;
621 if (hw->desc[2] != ad->paddr) {
622 /* AOI1 is not the first in the chain */
623 if (pmfbi->count > 0)
624 /* AOI0 is open, must be the first */
625 pmfbi->ad->next_ad = 0;
626 } else /* AOI1 is the first in the chain */
0d9dab39 627 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 628 /* close AOI 1 */
629 break;
9b53a9e2 630 }
9b53a9e2
YS		 631}
632
633static void enable_lcdc(struct fb_info *info)
634{
635 struct diu *hw = dr.diu_reg;
636 struct mfb_info *mfbi = info->par;
637 struct fsl_diu_data *machine_data = mfbi->parent;
638
639 if (!machine_data->fb_enabled) {
640 out_be32(&hw->diu_mode, dr.mode);
641 machine_data->fb_enabled++;
642 }
643}
644
645static void disable_lcdc(struct fb_info *info)
646{
647 struct diu *hw = dr.diu_reg;
648 struct mfb_info *mfbi = info->par;
649 struct fsl_diu_data *machine_data = mfbi->parent;
650
651 if (machine_data->fb_enabled) {
652 out_be32(&hw->diu_mode, 0);
653 machine_data->fb_enabled = 0;
654 }
655}
656
657static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
658 struct fb_info *info)
659{
660 struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
661 struct fsl_diu_data *machine_data = mfbi->parent;
2572df91
TT		 662 int available_height, upper_aoi_bottom;
663 enum mfb_index index = mfbi->index;
9b53a9e2
YS		 664 int lower_aoi_is_open, upper_aoi_is_open;
665 __u32 base_plane_width, base_plane_height, upper_aoi_height;
666
667 base_plane_width = machine_data->fsl_diu_info[0]->var.xres;
668 base_plane_height = machine_data->fsl_diu_info[0]->var.yres;
669
fdfaa483
YS		 670 if (mfbi->x_aoi_d < 0)
671 mfbi->x_aoi_d = 0;
672 if (mfbi->y_aoi_d < 0)
673 mfbi->y_aoi_d = 0;
9b53a9e2 674 switch (index) {
2572df91 675 case PLANE0:
9b53a9e2
YS		 676 if (mfbi->x_aoi_d != 0)
677 mfbi->x_aoi_d = 0;
678 if (mfbi->y_aoi_d != 0)
679 mfbi->y_aoi_d = 0;
680 break;
2572df91
TT		 681 case PLANE1_AOI0:
682 case PLANE2_AOI0:
9b53a9e2
YS		 683 lower_aoi_mfbi = machine_data->fsl_diu_info[index+1]->par;
684 lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
685 if (var->xres > base_plane_width)
686 var->xres = base_plane_width;
687 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
688 mfbi->x_aoi_d = base_plane_width - var->xres;
689
690 if (lower_aoi_is_open)
691 available_height = lower_aoi_mfbi->y_aoi_d;
692 else
693 available_height = base_plane_height;
694 if (var->yres > available_height)
695 var->yres = available_height;
696 if ((mfbi->y_aoi_d + var->yres) > available_height)
697 mfbi->y_aoi_d = available_height - var->yres;
698 break;
2572df91
TT		 699 case PLANE1_AOI1:
700 case PLANE2_AOI1:
9b53a9e2
YS		 701 upper_aoi_mfbi = machine_data->fsl_diu_info[index-1]->par;
702 upper_aoi_height =
703 machine_data->fsl_diu_info[index-1]->var.yres;
704 upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
705 upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
706 if (var->xres > base_plane_width)
707 var->xres = base_plane_width;
708 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
709 mfbi->x_aoi_d = base_plane_width - var->xres;
710 if (mfbi->y_aoi_d < 0)
711 mfbi->y_aoi_d = 0;
712 if (upper_aoi_is_open) {
713 if (mfbi->y_aoi_d < upper_aoi_bottom)
714 mfbi->y_aoi_d = upper_aoi_bottom;
715 available_height = base_plane_height
716 - upper_aoi_bottom;
717 } else
718 available_height = base_plane_height;
719 if (var->yres > available_height)
720 var->yres = available_height;
721 if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
722 mfbi->y_aoi_d = base_plane_height - var->yres;
723 break;
724 }
725}
726/*
727 * Checks to see if the hardware supports the state requested by var passed
728 * in. This function does not alter the hardware state! If the var passed in
729 * is slightly off by what the hardware can support then we alter the var
730 * PASSED in to what we can do. If the hardware doesn't support mode change
731 * a -EINVAL will be returned by the upper layers.
732 */
733static int fsl_diu_check_var(struct fb_var_screeninfo *var,
734 struct fb_info *info)
735{
9b53a9e2
YS		 736 if (var->xres_virtual < var->xres)
737 var->xres_virtual = var->xres;
738 if (var->yres_virtual < var->yres)
739 var->yres_virtual = var->yres;
740
741 if (var->xoffset < 0)
742 var->xoffset = 0;
743
744 if (var->yoffset < 0)
745 var->yoffset = 0;
746
747 if (var->xoffset + info->var.xres > info->var.xres_virtual)
748 var->xoffset = info->var.xres_virtual - info->var.xres;
749
750 if (var->yoffset + info->var.yres > info->var.yres_virtual)
751 var->yoffset = info->var.yres_virtual - info->var.yres;
752
753 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
754 (var->bits_per_pixel != 16))
755 var->bits_per_pixel = default_bpp;
756
757 switch (var->bits_per_pixel) {
758 case 16:
759 var->red.length = 5;
760 var->red.offset = 11;
761 var->red.msb_right = 0;
762
763 var->green.length = 6;
764 var->green.offset = 5;
765 var->green.msb_right = 0;
766
767 var->blue.length = 5;
768 var->blue.offset = 0;
769 var->blue.msb_right = 0;
770
771 var->transp.length = 0;
772 var->transp.offset = 0;
773 var->transp.msb_right = 0;
774 break;
775 case 24:
776 var->red.length = 8;
777 var->red.offset = 0;
778 var->red.msb_right = 0;
779
780 var->green.length = 8;
781 var->green.offset = 8;
782 var->green.msb_right = 0;
783
784 var->blue.length = 8;
785 var->blue.offset = 16;
786 var->blue.msb_right = 0;
787
788 var->transp.length = 0;
789 var->transp.offset = 0;
790 var->transp.msb_right = 0;
791 break;
792 case 32:
793 var->red.length = 8;
794 var->red.offset = 16;
795 var->red.msb_right = 0;
796
797 var->green.length = 8;
798 var->green.offset = 8;
799 var->green.msb_right = 0;
800
801 var->blue.length = 8;
802 var->blue.offset = 0;
803 var->blue.msb_right = 0;
804
805 var->transp.length = 8;
806 var->transp.offset = 24;
807 var->transp.msb_right = 0;
808
809 break;
810 }
9b53a9e2
YS		 811
812 var->height = -1;
813 var->width = -1;
814 var->grayscale = 0;
815
816 /* Copy nonstd field to/from sync for fbset usage */
817 var->sync |= var->nonstd;
818 var->nonstd |= var->sync;
819
820 adjust_aoi_size_position(var, info);
821 return 0;
822}
823
824static void set_fix(struct fb_info *info)
825{
826 struct fb_fix_screeninfo *fix = &info->fix;
827 struct fb_var_screeninfo *var = &info->var;
828 struct mfb_info *mfbi = info->par;
829
ec02dd23 830 strncpy(fix->id, mfbi->id, sizeof(fix->id));
9b53a9e2
YS		 831 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
832 fix->type = FB_TYPE_PACKED_PIXELS;
833 fix->accel = FB_ACCEL_NONE;
834 fix->visual = FB_VISUAL_TRUECOLOR;
835 fix->xpanstep = 1;
836 fix->ypanstep = 1;
837}
838
839static void update_lcdc(struct fb_info *info)
840{
841 struct fb_var_screeninfo *var = &info->var;
842 struct mfb_info *mfbi = info->par;
843 struct fsl_diu_data *machine_data = mfbi->parent;
844 struct diu *hw;
845 int i, j;
846 char __iomem *cursor_base, *gamma_table_base;
847
848 u32 temp;
849
850 hw = dr.diu_reg;
851
852 if (mfbi->type == MFB_TYPE_OFF) {
853 fsl_diu_disable_panel(info);
854 return;
855 }
856
857 diu_ops.set_monitor_port(machine_data->monitor_port);
858 gamma_table_base = pool.gamma.vaddr;
859 cursor_base = pool.cursor.vaddr;
860 /* Prep for DIU init - gamma table, cursor table */
861
862 for (i = 0; i <= 2; i++)
4a85dc8b
TT		 863 for (j = 0; j <= 255; j++)
864 *gamma_table_base++ = j;
9b53a9e2
YS		 865
866 diu_ops.set_gamma_table(machine_data->monitor_port, pool.gamma.vaddr);
867
9b53a9e2
YS		 868 disable_lcdc(info);
869
870 /* Program DIU registers */
871
872 out_be32(&hw->gamma, pool.gamma.paddr);
873 out_be32(&hw->cursor, pool.cursor.paddr);
874
875 out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */
876 out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
877 out_be32(&hw->disp_size, (var->yres << 16 | var->xres));
878 /* DISP SIZE */
9b53a9e2
YS		 879 out_be32(&hw->wb_size, 0); /* WB SIZE */
880 out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
881
882 /* Horizontal and vertical configuration register */
883 temp = var->left_margin << 22 | /* BP_H */
884 var->hsync_len << 11 | /* PW_H */
885 var->right_margin; /* FP_H */
886
887 out_be32(&hw->hsyn_para, temp);
888
889 temp = var->upper_margin << 22 | /* BP_V */
890 var->vsync_len << 11 | /* PW_V */
891 var->lower_margin; /* FP_V */
892
893 out_be32(&hw->vsyn_para, temp);
894
9b53a9e2
YS		 895 diu_ops.set_pixel_clock(var->pixclock);
896
897 out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
898 out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
899 out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
900 out_be32(&hw->plut, 0x01F5F666);
901
902 /* Enable the DIU */
903 enable_lcdc(info);
904}
905
906static int map_video_memory(struct fb_info *info)
907{
908 phys_addr_t phys;
537a1bf0 909 u32 smem_len = info->fix.line_length * info->var.yres_virtual;
9b53a9e2 910
537a1bf0 911 info->screen_base = fsl_diu_alloc(smem_len, &phys);
05946bce 912 if (info->screen_base == NULL) {
154152ae 913 dev_err(info->dev, "unable to allocate fb memory\n");
9b53a9e2
YS		 914 return -ENOMEM;
915 }
537a1bf0 916 mutex_lock(&info->mm_lock);
9b53a9e2 917 info->fix.smem_start = (unsigned long) phys;
537a1bf0
KH		 918 info->fix.smem_len = smem_len;
919 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 920 info->screen_size = info->fix.smem_len;
921
9b53a9e2
YS		 922 return 0;
923}
924
925static void unmap_video_memory(struct fb_info *info)
926{
927 fsl_diu_free(info->screen_base, info->fix.smem_len);
537a1bf0 928 mutex_lock(&info->mm_lock);
05946bce 929 info->screen_base = NULL;
9b53a9e2
YS		 930 info->fix.smem_start = 0;
931 info->fix.smem_len = 0;
537a1bf0 932 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 933}
934
ae5591e3
YS		 935/*
936 * Using the fb_var_screeninfo in fb_info we set the aoi of this
937 * particular framebuffer. It is a light version of fsl_diu_set_par.
938 */
939static int fsl_diu_set_aoi(struct fb_info *info)
940{
941 struct fb_var_screeninfo *var = &info->var;
942 struct mfb_info *mfbi = info->par;
943 struct diu_ad *ad = mfbi->ad;
944
945 /* AOI should not be greater than display size */
946 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
947 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
948 return 0;
949}
950
9b53a9e2
YS		 951/*
952 * Using the fb_var_screeninfo in fb_info we set the resolution of this
953 * particular framebuffer. This function alters the fb_fix_screeninfo stored
954 * in fb_info. It does not alter var in fb_info since we are using that
955 * data. This means we depend on the data in var inside fb_info to be
956 * supported by the hardware. fsl_diu_check_var is always called before
957 * fsl_diu_set_par to ensure this.
958 */
959static int fsl_diu_set_par(struct fb_info *info)
960{
961 unsigned long len;
962 struct fb_var_screeninfo *var = &info->var;
963 struct mfb_info *mfbi = info->par;
964 struct fsl_diu_data *machine_data = mfbi->parent;
965 struct diu_ad *ad = mfbi->ad;
966 struct diu *hw;
967
968 hw = dr.diu_reg;
969
970 set_fix(info);
971 mfbi->cursor_reset = 1;
972
973 len = info->var.yres_virtual * info->fix.line_length;
974 /* Alloc & dealloc each time resolution/bpp change */
975 if (len != info->fix.smem_len) {
976 if (info->fix.smem_start)
977 unmap_video_memory(info);
9b53a9e2
YS		 978
979 /* Memory allocation for framebuffer */
980 if (map_video_memory(info)) {
154152ae 981 dev_err(info->dev, "unable to allocate fb memory 1\n");
9b53a9e2
YS		 982 return -ENOMEM;
983 }
984 }
985
7653aaab
TT		 986 ad->pix_fmt = diu_ops.get_pixel_format(machine_data->monitor_port,
987 var->bits_per_pixel);
9b53a9e2 988 ad->addr = cpu_to_le32(info->fix.smem_start);
ae5591e3
YS		 989 ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
990 var->xres_virtual) | mfbi->g_alpha;
991 /* AOI should not be greater than display size */
9b53a9e2 992 ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
ae5591e3 993 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
9b53a9e2
YS		 994 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
995
996 /* Disable chroma keying function */
997 ad->ckmax_r = 0;
998 ad->ckmax_g = 0;
999 ad->ckmax_b = 0;
1000
1001 ad->ckmin_r = 255;
1002 ad->ckmin_g = 255;
1003 ad->ckmin_b = 255;
1004
2572df91 1005 if (mfbi->index == PLANE0)
9b53a9e2
YS		 1006 update_lcdc(info);
1007 return 0;
1008}
1009
1010static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
1011{
4a85dc8b 1012 return ((val << width) + 0x7FFF - val) >> 16;
9b53a9e2
YS		 1013}
1014
1015/*
1016 * Set a single color register. The values supplied have a 16 bit magnitude
1017 * which needs to be scaled in this function for the hardware. Things to take
1018 * into consideration are how many color registers, if any, are supported with
1019 * the current color visual. With truecolor mode no color palettes are
25985edc 1020 * supported. Here a pseudo palette is created which we store the value in
9b53a9e2
YS		 1021 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
1022 * color palette.
1023 */
4a85dc8b
TT		 1024static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
1025 unsigned int green, unsigned int blue,
1026 unsigned int transp, struct fb_info *info)
9b53a9e2
YS		 1027{
1028 int ret = 1;
1029
1030 /*
1031 * If greyscale is true, then we convert the RGB value
1032 * to greyscale no matter what visual we are using.
1033 */
1034 if (info->var.grayscale)
1035 red = green = blue = (19595 * red + 38470 * green +
1036 7471 * blue) >> 16;
1037 switch (info->fix.visual) {
1038 case FB_VISUAL_TRUECOLOR:
1039 /*
1040 * 16-bit True Colour. We encode the RGB value
1041 * according to the RGB bitfield information.
1042 */
1043 if (regno < 16) {
1044 u32 *pal = info->pseudo_palette;
1045 u32 v;
1046
1047 red = CNVT_TOHW(red, info->var.red.length);
1048 green = CNVT_TOHW(green, info->var.green.length);
1049 blue = CNVT_TOHW(blue, info->var.blue.length);
1050 transp = CNVT_TOHW(transp, info->var.transp.length);
1051
1052 v = (red << info->var.red.offset) |
1053 (green << info->var.green.offset) |
1054 (blue << info->var.blue.offset) |
1055 (transp << info->var.transp.offset);
1056
1057 pal[regno] = v;
1058 ret = 0;
1059 }
1060 break;
9b53a9e2
YS		 1061 }
1062
1063 return ret;
1064}
1065
1066/*
1067 * Pan (or wrap, depending on the `vmode' field) the display using the
1068 * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
1069 * don't fit, return -EINVAL.
1070 */
1071static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
1072 struct fb_info *info)
1073{
1074 if ((info->var.xoffset == var->xoffset) &&
1075 (info->var.yoffset == var->yoffset))
1076 return 0; /* No change, do nothing */
1077
1078 if (var->xoffset < 0 || var->yoffset < 0
1079 || var->xoffset + info->var.xres > info->var.xres_virtual
1080 || var->yoffset + info->var.yres > info->var.yres_virtual)
1081 return -EINVAL;
1082
1083 info->var.xoffset = var->xoffset;
1084 info->var.yoffset = var->yoffset;
1085
1086 if (var->vmode & FB_VMODE_YWRAP)
1087 info->var.vmode |= FB_VMODE_YWRAP;
1088 else
1089 info->var.vmode &= ~FB_VMODE_YWRAP;
1090
ae5591e3
YS		 1091 fsl_diu_set_aoi(info);
1092
9b53a9e2
YS		 1093 return 0;
1094}
1095
9b53a9e2
YS		 1096static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
1097 unsigned long arg)
1098{
1099 struct mfb_info *mfbi = info->par;
1100 struct diu_ad *ad = mfbi->ad;
1101 struct mfb_chroma_key ck;
1102 unsigned char global_alpha;
1103 struct aoi_display_offset aoi_d;
1104 __u32 pix_fmt;
1105 void __user *buf = (void __user *)arg;
1106
1107 if (!arg)
1108 return -EINVAL;
1109 switch (cmd) {
36b0b1d4
TT		 1110 case MFB_SET_PIXFMT_OLD:
1111 dev_warn(info->dev,
1112 "MFB_SET_PIXFMT value of 0x%08x is deprecated.\n",
1113 MFB_SET_PIXFMT_OLD);
9b53a9e2
YS		 1114 case MFB_SET_PIXFMT:
1115 if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
1116 return -EFAULT;
1117 ad->pix_fmt = pix_fmt;
9b53a9e2 1118 break;
36b0b1d4
TT		 1119 case MFB_GET_PIXFMT_OLD:
1120 dev_warn(info->dev,
1121 "MFB_GET_PIXFMT value of 0x%08x is deprecated.\n",
1122 MFB_GET_PIXFMT_OLD);
9b53a9e2
YS		 1123 case MFB_GET_PIXFMT:
1124 pix_fmt = ad->pix_fmt;
1125 if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
1126 return -EFAULT;
9b53a9e2
YS		 1127 break;
1128 case MFB_SET_AOID:
1129 if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
1130 return -EFAULT;
1131 mfbi->x_aoi_d = aoi_d.x_aoi_d;
1132 mfbi->y_aoi_d = aoi_d.y_aoi_d;
9b53a9e2 1133 fsl_diu_check_var(&info->var, info);
ae5591e3 1134 fsl_diu_set_aoi(info);
9b53a9e2
YS		 1135 break;
1136 case MFB_GET_AOID:
1137 aoi_d.x_aoi_d = mfbi->x_aoi_d;
1138 aoi_d.y_aoi_d = mfbi->y_aoi_d;
1139 if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
1140 return -EFAULT;
9b53a9e2
YS		 1141 break;
1142 case MFB_GET_ALPHA:
1143 global_alpha = mfbi->g_alpha;
1144 if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
1145 return -EFAULT;
9b53a9e2
YS		 1146 break;
1147 case MFB_SET_ALPHA:
1148 /* set panel information */
1149 if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
1150 return -EFAULT;
1151 ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
1152 (global_alpha & 0xff);
1153 mfbi->g_alpha = global_alpha;
9b53a9e2
YS		 1154 break;
1155 case MFB_SET_CHROMA_KEY:
1156 /* set panel winformation */
1157 if (copy_from_user(&ck, buf, sizeof(ck)))
1158 return -EFAULT;
1159
1160 if (ck.enable &&
1161 (ck.red_max < ck.red_min ||
1162 ck.green_max < ck.green_min ||
1163 ck.blue_max < ck.blue_min))
1164 return -EINVAL;
1165
1166 if (!ck.enable) {
1167 ad->ckmax_r = 0;
1168 ad->ckmax_g = 0;
1169 ad->ckmax_b = 0;
1170 ad->ckmin_r = 255;
1171 ad->ckmin_g = 255;
1172 ad->ckmin_b = 255;
1173 } else {
1174 ad->ckmax_r = ck.red_max;
1175 ad->ckmax_g = ck.green_max;
1176 ad->ckmax_b = ck.blue_max;
1177 ad->ckmin_r = ck.red_min;
1178 ad->ckmin_g = ck.green_min;
1179 ad->ckmin_b = ck.blue_min;
1180 }
9b53a9e2 1181 break;
9b53a9e2 1182 default:
154152ae 1183 dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd);
9b53a9e2
YS		 1184 return -ENOIOCTLCMD;
1185 }
1186
1187 return 0;
1188}
1189
1190/* turn on fb if count == 1
1191 */
1192static int fsl_diu_open(struct fb_info *info, int user)
1193{
1194 struct mfb_info *mfbi = info->par;
1195 int res = 0;
1196
4b5006ec 1197 /* free boot splash memory on first /dev/fb0 open */
2572df91 1198 if ((mfbi->index == PLANE0) && diu_ops.release_bootmem)
4b5006ec
AG		 1199 diu_ops.release_bootmem();
1200
9b53a9e2
YS		 1201 spin_lock(&diu_lock);
1202 mfbi->count++;
1203 if (mfbi->count == 1) {
9b53a9e2
YS		 1204 fsl_diu_check_var(&info->var, info);
1205 res = fsl_diu_set_par(info);
1206 if (res < 0)
1207 mfbi->count--;
1208 else {
1209 res = fsl_diu_enable_panel(info);
1210 if (res < 0)
1211 mfbi->count--;
1212 }
1213 }
1214
1215 spin_unlock(&diu_lock);
1216 return res;
1217}
1218
1219/* turn off fb if count == 0
1220 */
1221static int fsl_diu_release(struct fb_info *info, int user)
1222{
1223 struct mfb_info *mfbi = info->par;
1224 int res = 0;
1225
1226 spin_lock(&diu_lock);
1227 mfbi->count--;
2572df91
TT		 1228 if (mfbi->count == 0)
1229 fsl_diu_disable_panel(info);
1230
9b53a9e2
YS		 1231 spin_unlock(&diu_lock);
1232 return res;
1233}
1234
1235static struct fb_ops fsl_diu_ops = {
1236 .owner = THIS_MODULE,
1237 .fb_check_var = fsl_diu_check_var,
1238 .fb_set_par = fsl_diu_set_par,
1239 .fb_setcolreg = fsl_diu_setcolreg,
9b53a9e2
YS		 1240 .fb_pan_display = fsl_diu_pan_display,
1241 .fb_fillrect = cfb_fillrect,
1242 .fb_copyarea = cfb_copyarea,
1243 .fb_imageblit = cfb_imageblit,
1244 .fb_ioctl = fsl_diu_ioctl,
1245 .fb_open = fsl_diu_open,
1246 .fb_release = fsl_diu_release,
1247};
1248
1249static int init_fbinfo(struct fb_info *info)
1250{
1251 struct mfb_info *mfbi = info->par;
1252
1253 info->device = NULL;
1254 info->var.activate = FB_ACTIVATE_NOW;
1255 info->fbops = &fsl_diu_ops;
1256 info->flags = FBINFO_FLAG_DEFAULT;
1257 info->pseudo_palette = &mfbi->pseudo_palette;
1258
1259 /* Allocate colormap */
1260 fb_alloc_cmap(&info->cmap, 16, 0);
1261 return 0;
1262}
1263
05946bce 1264static int __devinit install_fb(struct fb_info *info)
9b53a9e2
YS		 1265{
1266 int rc;
1267 struct mfb_info *mfbi = info->par;
1268 const char *aoi_mode, *init_aoi_mode = "320x240";
8b856f04
AG		 1269 struct fb_videomode *db = fsl_diu_mode_db;
1270 unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
1271 int has_default_mode = 1;
9b53a9e2
YS		 1272
1273 if (init_fbinfo(info))
1274 return -EINVAL;
1275
2572df91 1276 if (mfbi->index == PLANE0) {
8b856f04
AG		 1277 if (mfbi->edid_data) {
1278 /* Now build modedb from EDID */
1279 fb_edid_to_monspecs(mfbi->edid_data, &info->monspecs);
1280 fb_videomode_to_modelist(info->monspecs.modedb,
1281 info->monspecs.modedb_len,
1282 &info->modelist);
1283 db = info->monspecs.modedb;
1284 dbsize = info->monspecs.modedb_len;
1285 }
9b53a9e2 1286 aoi_mode = fb_mode;
8b856f04 1287 } else {
9b53a9e2 1288 aoi_mode = init_aoi_mode;
8b856f04 1289 }
63cf8df4
TT		 1290 rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL,
1291 default_bpp);
154152ae 1292 if (!rc) {
8b856f04
AG		 1293 /*
1294 * For plane 0 we continue and look into
1295 * driver's internal modedb.
1296 */
2572df91 1297 if ((mfbi->index == PLANE0) && mfbi->edid_data)
8b856f04
AG		 1298 has_default_mode = 0;
1299 else
1300 return -EINVAL;
9b53a9e2
YS		 1301 }
1302
8b856f04
AG		 1303 if (!has_default_mode) {
1304 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
63cf8df4
TT		 1305 ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp);
1306 if (rc)
8b856f04
AG		 1307 has_default_mode = 1;
1308 }
1309
1310 /* Still not found, use preferred mode from database if any */
1311 if (!has_default_mode && info->monspecs.modedb) {
1312 struct fb_monspecs *specs = &info->monspecs;
1313 struct fb_videomode *modedb = &specs->modedb[0];
1314
1315 /*
1316 * Get preferred timing. If not found,
1317 * first mode in database will be used.
1318 */
1319 if (specs->misc & FB_MISC_1ST_DETAIL) {
1320 int i;
1321
1322 for (i = 0; i < specs->modedb_len; i++) {
1323 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1324 modedb = &specs->modedb[i];
1325 break;
1326 }
1327 }
1328 }
1329
1330 info->var.bits_per_pixel = default_bpp;
1331 fb_videomode_to_var(&info->var, modedb);
1332 }
1333
9b53a9e2 1334 if (fsl_diu_check_var(&info->var, info)) {
154152ae 1335 dev_err(info->dev, "fsl_diu_check_var failed\n");
589c7971 1336 unmap_video_memory(info);
9b53a9e2
YS		 1337 fb_dealloc_cmap(&info->cmap);
1338 return -EINVAL;
1339 }
1340
9b53a9e2 1341 if (register_framebuffer(info) < 0) {
154152ae 1342 dev_err(info->dev, "register_framebuffer failed\n");
9b53a9e2
YS		 1343 unmap_video_memory(info);
1344 fb_dealloc_cmap(&info->cmap);
1345 return -EINVAL;
1346 }
1347
1348 mfbi->registered = 1;
154152ae 1349 dev_info(info->dev, "%s registered successfully\n", mfbi->id);
9b53a9e2
YS		 1350
1351 return 0;
1352}
1353
05946bce 1354static void uninstall_fb(struct fb_info *info)
9b53a9e2
YS		 1355{
1356 struct mfb_info *mfbi = info->par;
1357
1358 if (!mfbi->registered)
1359 return;
1360
2572df91 1361 if (mfbi->index == PLANE0)
8b856f04
AG		 1362 kfree(mfbi->edid_data);
1363
9b53a9e2
YS		 1364 unregister_framebuffer(info);
1365 unmap_video_memory(info);
1366 if (&info->cmap)
1367 fb_dealloc_cmap(&info->cmap);
1368
1369 mfbi->registered = 0;
1370}
1371
1372static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
1373{
1374 struct diu *hw = dr.diu_reg;
1375 unsigned int status = in_be32(&hw->int_status);
1376
1377 if (status) {
1378 /* This is the workaround for underrun */
1379 if (status & INT_UNDRUN) {
1380 out_be32(&hw->diu_mode, 0);
9b53a9e2
YS		 1381 udelay(1);
1382 out_be32(&hw->diu_mode, 1);
1383 }
1384#if defined(CONFIG_NOT_COHERENT_CACHE)
1385 else if (status & INT_VSYNC) {
1386 unsigned int i;
4a85dc8b 1387
9b53a9e2
YS		 1388 for (i = 0; i < coherence_data_size;
1389 i += d_cache_line_size)
1390 __asm__ __volatile__ (
1391 "dcbz 0, %[input]"
1392 ::[input]"r"(&coherence_data[i]));
1393 }
1394#endif
1395 return IRQ_HANDLED;
1396 }
1397 return IRQ_NONE;
1398}
1399
1400static int request_irq_local(int irq)
1401{
bada04fc 1402 u32 ints;
9b53a9e2
YS		 1403 struct diu *hw;
1404 int ret;
1405
1406 hw = dr.diu_reg;
1407
1408 /* Read to clear the status */
bada04fc 1409 in_be32(&hw->int_status);
9b53a9e2 1410
f8c6bf6a 1411 ret = request_irq(irq, fsl_diu_isr, 0, "fsl-diu-fb", NULL);
154152ae 1412 if (!ret) {
9b53a9e2
YS		 1413 ints = INT_PARERR | INT_LS_BF_VS;
1414#if !defined(CONFIG_NOT_COHERENT_CACHE)
1415 ints |= INT_VSYNC;
1416#endif
4a85dc8b 1417
9b53a9e2
YS		 1418 if (dr.mode == MFB_MODE2 || dr.mode == MFB_MODE3)
1419 ints |= INT_VSYNC_WB;
1420
1421 /* Read to clear the status */
bada04fc 1422 in_be32(&hw->int_status);
9b53a9e2
YS		 1423 out_be32(&hw->int_mask, ints);
1424 }
4a85dc8b 1425
9b53a9e2
YS		 1426 return ret;
1427}
1428
1429static void free_irq_local(int irq)
1430{
1431 struct diu *hw = dr.diu_reg;
1432
1433 /* Disable all LCDC interrupt */
1434 out_be32(&hw->int_mask, 0x1f);
1435
05946bce 1436 free_irq(irq, NULL);
9b53a9e2
YS		 1437}
1438
1439#ifdef CONFIG_PM
1440/*
1441 * Power management hooks. Note that we won't be called from IRQ context,
1442 * unlike the blank functions above, so we may sleep.
1443 */
2dc11581 1444static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state)
9b53a9e2
YS		 1445{
1446 struct fsl_diu_data *machine_data;
1447
48948a3e 1448 machine_data = dev_get_drvdata(&ofdev->dev);
9b53a9e2
YS		 1449 disable_lcdc(machine_data->fsl_diu_info[0]);
1450
1451 return 0;
1452}
1453
2dc11581 1454static int fsl_diu_resume(struct platform_device *ofdev)
9b53a9e2
YS		 1455{
1456 struct fsl_diu_data *machine_data;
1457
48948a3e 1458 machine_data = dev_get_drvdata(&ofdev->dev);
9b53a9e2
YS		 1459 enable_lcdc(machine_data->fsl_diu_info[0]);
1460
1461 return 0;
1462}
1463
1464#else
1465#define fsl_diu_suspend NULL
1466#define fsl_diu_resume NULL
1467#endif /* CONFIG_PM */
1468
1469/* Align to 64-bit(8-byte), 32-byte, etc. */
f3791889
AV		 1470static int allocate_buf(struct device *dev, struct diu_addr *buf, u32 size,
1471 u32 bytes_align)
9b53a9e2 1472{
bada04fc
TT		 1473 u32 offset;
1474 dma_addr_t mask;
9b53a9e2 1475
bada04fc
TT		 1476 buf->vaddr =
1477 dma_alloc_coherent(dev, size + bytes_align, &buf->paddr,
1478 GFP_DMA | __GFP_ZERO);
9b53a9e2
YS		 1479 if (!buf->vaddr)
1480 return -ENOMEM;
1481
9b53a9e2 1482 mask = bytes_align - 1;
bada04fc 1483 offset = buf->paddr & mask;
9b53a9e2
YS		 1484 if (offset) {
1485 buf->offset = bytes_align - offset;
bada04fc 1486 buf->paddr = buf->paddr + offset;
9b53a9e2
YS		 1487 } else
1488 buf->offset = 0;
4a85dc8b 1489
9b53a9e2
YS		 1490 return 0;
1491}
1492
f3791889
AV		 1493static void free_buf(struct device *dev, struct diu_addr *buf, u32 size,
1494 u32 bytes_align)
9b53a9e2 1495{
4a85dc8b
TT		 1496 dma_free_coherent(dev, size + bytes_align, buf->vaddr,
1497 buf->paddr - buf->offset);
9b53a9e2
YS		 1498}
1499
1500static ssize_t store_monitor(struct device *device,
1501 struct device_attribute *attr, const char *buf, size_t count)
1502{
7653aaab 1503 enum fsl_diu_monitor_port old_monitor_port;
9b53a9e2
YS		 1504 struct fsl_diu_data *machine_data =
1505 container_of(attr, struct fsl_diu_data, dev_attr);
1506
9b53a9e2 1507 old_monitor_port = machine_data->monitor_port;
7653aaab 1508 machine_data->monitor_port = fsl_diu_name_to_port(buf);
9b53a9e2
YS		 1509
1510 if (old_monitor_port != machine_data->monitor_port) {
1511 /* All AOIs need adjust pixel format
1512 * fsl_diu_set_par only change the pixsel format here
1513 * unlikely to fail. */
1514 fsl_diu_set_par(machine_data->fsl_diu_info[0]);
1515 fsl_diu_set_par(machine_data->fsl_diu_info[1]);
1516 fsl_diu_set_par(machine_data->fsl_diu_info[2]);
1517 fsl_diu_set_par(machine_data->fsl_diu_info[3]);
1518 fsl_diu_set_par(machine_data->fsl_diu_info[4]);
1519 }
1520 return count;
1521}
1522
1523static ssize_t show_monitor(struct device *device,
1524 struct device_attribute *attr, char *buf)
1525{
1526 struct fsl_diu_data *machine_data =
1527 container_of(attr, struct fsl_diu_data, dev_attr);
7653aaab
TT		 1528
1529 switch (machine_data->monitor_port) {
1530 case FSL_DIU_PORT_DVI:
1531 return sprintf(buf, "DVI\n");
1532 case FSL_DIU_PORT_LVDS:
1533 return sprintf(buf, "Single-link LVDS\n");
1534 case FSL_DIU_PORT_DLVDS:
1535 return sprintf(buf, "Dual-link LVDS\n");
1536 }
1537
1538 return 0;
9b53a9e2
YS		 1539}
1540
9e52ba61 1541static int __devinit fsl_diu_probe(struct platform_device *pdev)
9b53a9e2 1542{
9e52ba61 1543 struct device_node *np = pdev->dev.of_node;
9b53a9e2 1544 struct mfb_info *mfbi;
89f08e3e 1545 phys_addr_t dummy_ad_addr = 0;
9b53a9e2 1546 int ret, i, error = 0;
9b53a9e2 1547 struct fsl_diu_data *machine_data;
4b5006ec 1548 int diu_mode;
9b53a9e2
YS		 1549
1550 machine_data = kzalloc(sizeof(struct fsl_diu_data), GFP_KERNEL);
1551 if (!machine_data)
1552 return -ENOMEM;
1553
1554 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
1555 machine_data->fsl_diu_info[i] =
9e52ba61 1556 framebuffer_alloc(sizeof(struct mfb_info), &pdev->dev);
9b53a9e2 1557 if (!machine_data->fsl_diu_info[i]) {
9e52ba61 1558 dev_err(&pdev->dev, "cannot allocate memory\n");
9b53a9e2
YS		 1559 ret = -ENOMEM;
1560 goto error2;
1561 }
1562 mfbi = machine_data->fsl_diu_info[i]->par;
1563 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
1564 mfbi->parent = machine_data;
8b856f04 1565
2572df91 1566 if (mfbi->index == PLANE0) {
8b856f04
AG		 1567 const u8 *prop;
1568 int len;
1569
1570 /* Get EDID */
1571 prop = of_get_property(np, "edid", &len);
1572 if (prop && len == EDID_LENGTH)
1573 mfbi->edid_data = kmemdup(prop, EDID_LENGTH,
1574 GFP_KERNEL);
1575 }
9b53a9e2
YS		 1576 }
1577
9e52ba61 1578 dr.diu_reg = of_iomap(np, 0);
9b53a9e2 1579 if (!dr.diu_reg) {
9e52ba61 1580 dev_err(&pdev->dev, "cannot map DIU registers\n");
9b53a9e2
YS		 1581 ret = -EFAULT;
1582 goto error2;
1583 }
1584
4b5006ec
AG		 1585 diu_mode = in_be32(&dr.diu_reg->diu_mode);
1586 if (diu_mode != MFB_MODE1)
1587 out_be32(&dr.diu_reg->diu_mode, 0); /* disable DIU */
9b53a9e2
YS		 1588
1589 /* Get the IRQ of the DIU */
1590 machine_data->irq = irq_of_parse_and_map(np, 0);
1591
1592 if (!machine_data->irq) {
9e52ba61 1593 dev_err(&pdev->dev, "could not get DIU IRQ\n");
9b53a9e2
YS		 1594 ret = -EINVAL;
1595 goto error;
1596 }
1597 machine_data->monitor_port = monitor_port;
1598
1599 /* Area descriptor memory pool aligns to 64-bit boundary */
9e52ba61 1600 if (allocate_buf(&pdev->dev, &pool.ad,
f3791889 1601 sizeof(struct diu_ad) * FSL_AOI_NUM, 8))
9b53a9e2
YS		 1602 return -ENOMEM;
1603
1604 /* Get memory for Gamma Table - 32-byte aligned memory */
9e52ba61 1605 if (allocate_buf(&pdev->dev, &pool.gamma, 768, 32)) {
9b53a9e2
YS		 1606 ret = -ENOMEM;
1607 goto error;
1608 }
1609
1610 /* For performance, cursor bitmap buffer aligns to 32-byte boundary */
9e52ba61 1611 if (allocate_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
f3791889 1612 32)) {
9b53a9e2
YS		 1613 ret = -ENOMEM;
1614 goto error;
1615 }
1616
1617 i = ARRAY_SIZE(machine_data->fsl_diu_info);
1618 machine_data->dummy_ad = (struct diu_ad *)
1619 ((u32)pool.ad.vaddr + pool.ad.offset) + i;
1620 machine_data->dummy_ad->paddr = pool.ad.paddr +
1621 i * sizeof(struct diu_ad);
1622 machine_data->dummy_aoi_virt = fsl_diu_alloc(64, &dummy_ad_addr);
1623 if (!machine_data->dummy_aoi_virt) {
1624 ret = -ENOMEM;
1625 goto error;
1626 }
1627 machine_data->dummy_ad->addr = cpu_to_le32(dummy_ad_addr);
1628 machine_data->dummy_ad->pix_fmt = 0x88882317;
1629 machine_data->dummy_ad->src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
1630 machine_data->dummy_ad->aoi_size = cpu_to_le32((4 << 16) | 2);
1631 machine_data->dummy_ad->offset_xyi = 0;
1632 machine_data->dummy_ad->offset_xyd = 0;
1633 machine_data->dummy_ad->next_ad = 0;
1634
4b5006ec
AG		 1635 /*
1636 * Let DIU display splash screen if it was pre-initialized
1637 * by the bootloader, set dummy area descriptor otherwise.
1638 */
1639 if (diu_mode != MFB_MODE1)
1640 out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr);
1641
9b53a9e2
YS		 1642 out_be32(&dr.diu_reg->desc[1], machine_data->dummy_ad->paddr);
1643 out_be32(&dr.diu_reg->desc[2], machine_data->dummy_ad->paddr);
1644
1645 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
1646 machine_data->fsl_diu_info[i]->fix.smem_start = 0;
1647 mfbi = machine_data->fsl_diu_info[i]->par;
1648 mfbi->ad = (struct diu_ad *)((u32)pool.ad.vaddr
1649 + pool.ad.offset) + i;
1650 mfbi->ad->paddr = pool.ad.paddr + i * sizeof(struct diu_ad);
1651 ret = install_fb(machine_data->fsl_diu_info[i]);
1652 if (ret) {
9e52ba61 1653 dev_err(&pdev->dev, "could not register fb %d\n", i);
9b53a9e2
YS		 1654 goto error;
1655 }
1656 }
1657
1658 if (request_irq_local(machine_data->irq)) {
9e52ba61 1659 dev_err(&pdev->dev, "could not claim irq\n");
9b53a9e2
YS		 1660 goto error;
1661 }
1662
12765517 1663 sysfs_attr_init(&machine_data->dev_attr.attr);
9b53a9e2
YS		 1664 machine_data->dev_attr.attr.name = "monitor";
1665 machine_data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
1666 machine_data->dev_attr.show = show_monitor;
1667 machine_data->dev_attr.store = store_monitor;
1668 error = device_create_file(machine_data->fsl_diu_info[0]->dev,
1669 &machine_data->dev_attr);
1670 if (error) {
9e52ba61 1671 dev_err(&pdev->dev, "could not create sysfs file %s\n",
9b53a9e2
YS		 1672 machine_data->dev_attr.attr.name);
1673 }
1674
9e52ba61 1675 dev_set_drvdata(&pdev->dev, machine_data);
9b53a9e2
YS		 1676 return 0;
1677
1678error:
3f78bbd1
TT		 1679 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1680 uninstall_fb(machine_data->fsl_diu_info[i]);
1681
9b53a9e2 1682 if (pool.ad.vaddr)
9e52ba61 1683 free_buf(&pdev->dev, &pool.ad,
f3791889 1684 sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
9b53a9e2 1685 if (pool.gamma.vaddr)
9e52ba61 1686 free_buf(&pdev->dev, &pool.gamma, 768, 32);
9b53a9e2 1687 if (pool.cursor.vaddr)
9e52ba61 1688 free_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
f3791889 1689 32);
9b53a9e2
YS		 1690 if (machine_data->dummy_aoi_virt)
1691 fsl_diu_free(machine_data->dummy_aoi_virt, 64);
1692 iounmap(dr.diu_reg);
1693
1694error2:
1695 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1696 if (machine_data->fsl_diu_info[i])
1697 framebuffer_release(machine_data->fsl_diu_info[i]);
1698 kfree(machine_data);
1699
1700 return ret;
1701}
1702
9e52ba61 1703static int fsl_diu_remove(struct platform_device *pdev)
9b53a9e2
YS		 1704{
1705 struct fsl_diu_data *machine_data;
1706 int i;
1707
9e52ba61 1708 machine_data = dev_get_drvdata(&pdev->dev);
9b53a9e2
YS		 1709 disable_lcdc(machine_data->fsl_diu_info[0]);
1710 free_irq_local(machine_data->irq);
3f78bbd1
TT		 1711 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1712 uninstall_fb(machine_data->fsl_diu_info[i]);
9b53a9e2 1713 if (pool.ad.vaddr)
9e52ba61 1714 free_buf(&pdev->dev, &pool.ad,
f3791889 1715 sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
9b53a9e2 1716 if (pool.gamma.vaddr)
9e52ba61 1717 free_buf(&pdev->dev, &pool.gamma, 768, 32);
9b53a9e2 1718 if (pool.cursor.vaddr)
9e52ba61 1719 free_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2, 32);
9b53a9e2
YS		 1720 if (machine_data->dummy_aoi_virt)
1721 fsl_diu_free(machine_data->dummy_aoi_virt, 64);
1722 iounmap(dr.diu_reg);
1723 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1724 if (machine_data->fsl_diu_info[i])
1725 framebuffer_release(machine_data->fsl_diu_info[i]);
1726 kfree(machine_data);
1727
1728 return 0;
1729}
1730
1731#ifndef MODULE
1732static int __init fsl_diu_setup(char *options)
1733{
1734 char *opt;
1735 unsigned long val;
1736
1737 if (!options || !*options)
1738 return 0;
1739
1740 while ((opt = strsep(&options, ",")) != NULL) {
1741 if (!*opt)
1742 continue;
1743 if (!strncmp(opt, "monitor=", 8)) {
7653aaab 1744 monitor_port = fsl_diu_name_to_port(opt + 8);
9b53a9e2
YS		 1745 } else if (!strncmp(opt, "bpp=", 4)) {
1746 if (!strict_strtoul(opt + 4, 10, &val))
1747 default_bpp = val;
1748 } else
1749 fb_mode = opt;
1750 }
1751
1752 return 0;
1753}
1754#endif
1755
1756static struct of_device_id fsl_diu_match[] = {
d24720a4
AG		 1757#ifdef CONFIG_PPC_MPC512x
1758 {
1759 .compatible = "fsl,mpc5121-diu",
1760 },
1761#endif
9b53a9e2
YS		 1762 {
1763 .compatible = "fsl,diu",
1764 },
1765 {}
1766};
1767MODULE_DEVICE_TABLE(of, fsl_diu_match);
1768
28541d0f 1769static struct platform_driver fsl_diu_driver = {
4018294b 1770 .driver = {
f8c6bf6a 1771 .name = "fsl-diu-fb",
4018294b
GL		 1772 .owner = THIS_MODULE,
1773 .of_match_table = fsl_diu_match,
1774 },
9b53a9e2
YS		 1775 .probe = fsl_diu_probe,
1776 .remove = fsl_diu_remove,
1777 .suspend = fsl_diu_suspend,
1778 .resume = fsl_diu_resume,
1779};
1780
1781static int __init fsl_diu_init(void)
1782{
1783#ifdef CONFIG_NOT_COHERENT_CACHE
1784 struct device_node *np;
1785 const u32 *prop;
1786#endif
1787 int ret;
1788#ifndef MODULE
1789 char *option;
1790
1791 /*
1792 * For kernel boot options (in 'video=xxxfb:<options>' format)
1793 */
1794 if (fb_get_options("fslfb", &option))
1795 return -ENODEV;
1796 fsl_diu_setup(option);
7653aaab
TT		 1797#else
1798 monitor_port = fsl_diu_name_to_port(monitor_string);
9b53a9e2 1799#endif
154152ae 1800 pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
9b53a9e2
YS		 1801
1802#ifdef CONFIG_NOT_COHERENT_CACHE
1803 np = of_find_node_by_type(NULL, "cpu");
1804 if (!np) {
154152ae 1805 pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
9b53a9e2
YS		 1806 return -ENODEV;
1807 }
1808
1809 prop = of_get_property(np, "d-cache-size", NULL);
5394ba0f 1810 if (prop == NULL) {
154152ae
TT		 1811 pr_err("fsl-diu-fb: missing 'd-cache-size' property' "
1812 "in 'cpu' node\n");
5394ba0f 1813 of_node_put(np);
9b53a9e2 1814 return -ENODEV;
5394ba0f 1815 }
9b53a9e2 1816
4a85dc8b
TT		 1817 /*
1818 * Freescale PLRU requires 13/8 times the cache size to do a proper
1819 * displacement flush
9b53a9e2 1820 */
9e52ba61 1821 coherence_data_size = be32_to_cpup(prop) * 13;
9b53a9e2
YS		 1822 coherence_data_size /= 8;
1823
1824 prop = of_get_property(np, "d-cache-line-size", NULL);
5394ba0f 1825 if (prop == NULL) {
154152ae
TT		 1826 pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' "
1827 "in 'cpu' node\n");
5394ba0f 1828 of_node_put(np);
9b53a9e2 1829 return -ENODEV;
5394ba0f 1830 }
9e52ba61 1831 d_cache_line_size = be32_to_cpup(prop);
9b53a9e2
YS		 1832
1833 of_node_put(np);
1834 coherence_data = vmalloc(coherence_data_size);
1835 if (!coherence_data)
1836 return -ENOMEM;
1837#endif
4a85dc8b 1838
28541d0f 1839 ret = platform_driver_register(&fsl_diu_driver);
9b53a9e2 1840 if (ret) {
154152ae 1841 pr_err("fsl-diu-fb: failed to register platform driver\n");
9b53a9e2
YS		 1842#if defined(CONFIG_NOT_COHERENT_CACHE)
1843 vfree(coherence_data);
1844#endif
1845 iounmap(dr.diu_reg);
1846 }
1847 return ret;
1848}
1849
1850static void __exit fsl_diu_exit(void)
1851{
28541d0f 1852 platform_driver_unregister(&fsl_diu_driver);
9b53a9e2
YS		 1853#if defined(CONFIG_NOT_COHERENT_CACHE)
1854 vfree(coherence_data);
1855#endif
1856}
1857
1858module_init(fsl_diu_init);
1859module_exit(fsl_diu_exit);
1860
1861MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
1862MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
1863MODULE_LICENSE("GPL");
1864
1865module_param_named(mode, fb_mode, charp, 0);
1866MODULE_PARM_DESC(mode,
1867 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
1868module_param_named(bpp, default_bpp, ulong, 0);
154152ae 1869MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'");
7653aaab
TT		 1870module_param_named(monitor, monitor_string, charp, 0);
1871MODULE_PARM_DESC(monitor, "Specify the monitor port "
1872 "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
9b53a9e2 1873
Linux kernel - Deliverables
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