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drivers/video: fsl-diu-fb: improve device tree usage
[deliverable/linux.git] / drivers / video / fsl-diu-fb.c
CommitLineData
9b53a9e2
YS		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Freescale DIU Frame Buffer device driver
5 *
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
10 *
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/uaccess.h>
32#include <linux/vmalloc.h>
33
9b53a9e2 34#include <sysdev/fsl_soc.h>
0814a979 35#include <linux/fsl-diu-fb.h>
8b856f04 36#include "edid.h"
9b53a9e2
YS		 37
38/*
39 * These parameters give default parameters
40 * for video output 1024x768,
41 * FIXME - change timing to proper amounts
42 * hsync 31.5kHz, vsync 60Hz
43 */
44static struct fb_videomode __devinitdata fsl_diu_default_mode = {
45 .refresh = 60,
46 .xres = 1024,
47 .yres = 768,
48 .pixclock = 15385,
49 .left_margin = 160,
50 .right_margin = 24,
51 .upper_margin = 29,
52 .lower_margin = 3,
53 .hsync_len = 136,
54 .vsync_len = 6,
55 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
56 .vmode = FB_VMODE_NONINTERLACED
57};
58
59static struct fb_videomode __devinitdata fsl_diu_mode_db[] = {
60 {
61 .name = "1024x768-60",
62 .refresh = 60,
63 .xres = 1024,
64 .yres = 768,
65 .pixclock = 15385,
66 .left_margin = 160,
67 .right_margin = 24,
68 .upper_margin = 29,
69 .lower_margin = 3,
70 .hsync_len = 136,
71 .vsync_len = 6,
72 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
73 .vmode = FB_VMODE_NONINTERLACED
74 },
75 {
76 .name = "1024x768-70",
77 .refresh = 70,
78 .xres = 1024,
79 .yres = 768,
80 .pixclock = 16886,
81 .left_margin = 3,
82 .right_margin = 3,
83 .upper_margin = 2,
84 .lower_margin = 2,
85 .hsync_len = 40,
86 .vsync_len = 18,
87 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
88 .vmode = FB_VMODE_NONINTERLACED
89 },
90 {
91 .name = "1024x768-75",
92 .refresh = 75,
93 .xres = 1024,
94 .yres = 768,
95 .pixclock = 15009,
96 .left_margin = 3,
97 .right_margin = 3,
98 .upper_margin = 2,
99 .lower_margin = 2,
100 .hsync_len = 80,
101 .vsync_len = 32,
102 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
103 .vmode = FB_VMODE_NONINTERLACED
104 },
105 {
106 .name = "1280x1024-60",
107 .refresh = 60,
108 .xres = 1280,
109 .yres = 1024,
110 .pixclock = 9375,
111 .left_margin = 38,
112 .right_margin = 128,
113 .upper_margin = 2,
114 .lower_margin = 7,
115 .hsync_len = 216,
116 .vsync_len = 37,
117 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 .vmode = FB_VMODE_NONINTERLACED
119 },
120 {
121 .name = "1280x1024-70",
122 .refresh = 70,
123 .xres = 1280,
124 .yres = 1024,
125 .pixclock = 9380,
126 .left_margin = 6,
127 .right_margin = 6,
128 .upper_margin = 4,
129 .lower_margin = 4,
130 .hsync_len = 60,
131 .vsync_len = 94,
132 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
133 .vmode = FB_VMODE_NONINTERLACED
134 },
135 {
136 .name = "1280x1024-75",
137 .refresh = 75,
138 .xres = 1280,
139 .yres = 1024,
140 .pixclock = 9380,
141 .left_margin = 6,
142 .right_margin = 6,
143 .upper_margin = 4,
144 .lower_margin = 4,
145 .hsync_len = 60,
146 .vsync_len = 15,
147 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
148 .vmode = FB_VMODE_NONINTERLACED
149 },
150 {
151 .name = "320x240", /* for AOI only */
152 .refresh = 60,
153 .xres = 320,
154 .yres = 240,
155 .pixclock = 15385,
156 .left_margin = 0,
157 .right_margin = 0,
158 .upper_margin = 0,
159 .lower_margin = 0,
160 .hsync_len = 0,
161 .vsync_len = 0,
162 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
163 .vmode = FB_VMODE_NONINTERLACED
164 },
165 {
166 .name = "1280x480-60",
167 .refresh = 60,
168 .xres = 1280,
169 .yres = 480,
170 .pixclock = 18939,
171 .left_margin = 353,
172 .right_margin = 47,
173 .upper_margin = 39,
174 .lower_margin = 4,
175 .hsync_len = 8,
176 .vsync_len = 2,
177 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
178 .vmode = FB_VMODE_NONINTERLACED
179 },
180};
181
182static char *fb_mode = "1024x768-32@60";
183static unsigned long default_bpp = 32;
7653aaab
TT		 184static enum fsl_diu_monitor_port monitor_port;
185static char *monitor_string;
9b53a9e2
YS		 186
187#if defined(CONFIG_NOT_COHERENT_CACHE)
188static u8 *coherence_data;
189static size_t coherence_data_size;
190static unsigned int d_cache_line_size;
191#endif
192
193static DEFINE_SPINLOCK(diu_lock);
194
195struct fsl_diu_data {
196 struct fb_info *fsl_diu_info[FSL_AOI_NUM - 1];
197 /*FSL_AOI_NUM has one dummy AOI */
198 struct device_attribute dev_attr;
199 struct diu_ad *dummy_ad;
200 void *dummy_aoi_virt;
201 unsigned int irq;
202 int fb_enabled;
7653aaab 203 enum fsl_diu_monitor_port monitor_port;
9b53a9e2
YS		 204};
205
206struct mfb_info {
207 int index;
208 int type;
209 char *id;
210 int registered;
211 int blank;
212 unsigned long pseudo_palette[16];
213 struct diu_ad *ad;
214 int cursor_reset;
215 unsigned char g_alpha;
216 unsigned int count;
217 int x_aoi_d; /* aoi display x offset to physical screen */
218 int y_aoi_d; /* aoi display y offset to physical screen */
219 struct fsl_diu_data *parent;
8b856f04 220 u8 *edid_data;
9b53a9e2
YS		 221};
222
223
224static struct mfb_info mfb_template[] = {
225 { /* AOI 0 for plane 0 */
4a85dc8b
TT		 226 .index = 0,
227 .type = MFB_TYPE_OUTPUT,
228 .id = "Panel0",
229 .registered = 0,
230 .count = 0,
231 .x_aoi_d = 0,
232 .y_aoi_d = 0,
9b53a9e2
YS		 233 },
234 { /* AOI 0 for plane 1 */
4a85dc8b
TT		 235 .index = 1,
236 .type = MFB_TYPE_OUTPUT,
237 .id = "Panel1 AOI0",
238 .registered = 0,
239 .g_alpha = 0xff,
240 .count = 0,
241 .x_aoi_d = 0,
242 .y_aoi_d = 0,
9b53a9e2
YS		 243 },
244 { /* AOI 1 for plane 1 */
4a85dc8b
TT		 245 .index = 2,
246 .type = MFB_TYPE_OUTPUT,
247 .id = "Panel1 AOI1",
248 .registered = 0,
249 .g_alpha = 0xff,
250 .count = 0,
251 .x_aoi_d = 0,
252 .y_aoi_d = 480,
9b53a9e2
YS		 253 },
254 { /* AOI 0 for plane 2 */
4a85dc8b
TT		 255 .index = 3,
256 .type = MFB_TYPE_OUTPUT,
257 .id = "Panel2 AOI0",
258 .registered = 0,
259 .g_alpha = 0xff,
260 .count = 0,
261 .x_aoi_d = 640,
262 .y_aoi_d = 0,
9b53a9e2
YS		 263 },
264 { /* AOI 1 for plane 2 */
4a85dc8b
TT		 265 .index = 4,
266 .type = MFB_TYPE_OUTPUT,
267 .id = "Panel2 AOI1",
268 .registered = 0,
269 .g_alpha = 0xff,
270 .count = 0,
271 .x_aoi_d = 640,
272 .y_aoi_d = 480,
9b53a9e2
YS		 273 },
274};
275
276static struct diu_hw dr = {
277 .mode = MFB_MODE1,
278 .reg_lock = __SPIN_LOCK_UNLOCKED(diu_hw.reg_lock),
279};
280
281static struct diu_pool pool;
282
7653aaab
TT		 283/**
284 * fsl_diu_name_to_port - convert a port name to a monitor port enum
285 *
286 * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
287 * the enum fsl_diu_monitor_port that corresponds to that string.
288 *
289 * For compatibility with older versions, a number ("0", "1", or "2") is also
290 * supported.
291 *
292 * If the string is unknown, DVI is assumed.
293 *
294 * If the particular port is not supported by the platform, another port
295 * (platform-specific) is chosen instead.
296 */
297static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s)
298{
299 enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI;
300 unsigned long val;
301
302 if (s) {
303 if (!strict_strtoul(s, 10, &val) && (val <= 2))
304 port = (enum fsl_diu_monitor_port) val;
305 else if (strncmp(s, "lvds", 4) == 0)
306 port = FSL_DIU_PORT_LVDS;
307 else if (strncmp(s, "dlvds", 5) == 0)
308 port = FSL_DIU_PORT_DLVDS;
309 }
310
311 return diu_ops.valid_monitor_port(port);
312}
313
6b51d51a
TT		 314/**
315 * fsl_diu_alloc - allocate memory for the DIU
316 * @size: number of bytes to allocate
317 * @param: returned physical address of memory
318 *
319 * This function allocates a physically-contiguous block of memory.
9b53a9e2 320 */
6b51d51a 321static void *fsl_diu_alloc(size_t size, phys_addr_t *phys)
9b53a9e2
YS		 322{
323 void *virt;
324
6b51d51a 325 virt = alloc_pages_exact(size, GFP_DMA | __GFP_ZERO);
154152ae 326 if (virt)
9b53a9e2 327 *phys = virt_to_phys(virt);
9b53a9e2 328
9b53a9e2
YS		 329 return virt;
330}
331
6b51d51a
TT		 332/**
333 * fsl_diu_free - release DIU memory
334 * @virt: pointer returned by fsl_diu_alloc()
335 * @size: number of bytes allocated by fsl_diu_alloc()
336 *
337 * This function releases memory allocated by fsl_diu_alloc().
338 */
339static void fsl_diu_free(void *virt, size_t size)
9b53a9e2 340{
6b51d51a
TT		 341 if (virt && size)
342 free_pages_exact(virt, size);
9b53a9e2
YS		 343}
344
0d9dab39
AG		 345/*
346 * Workaround for failed writing desc register of planes.
347 * Needed with MPC5121 DIU rev 2.0 silicon.
348 */
349void wr_reg_wa(u32 *reg, u32 val)
350{
351 do {
352 out_be32(reg, val);
353 } while (in_be32(reg) != val);
354}
355
9b53a9e2
YS		 356static int fsl_diu_enable_panel(struct fb_info *info)
357{
358 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
359 struct diu *hw = dr.diu_reg;
360 struct diu_ad *ad = mfbi->ad;
361 struct fsl_diu_data *machine_data = mfbi->parent;
362 int res = 0;
363
9b53a9e2
YS		 364 if (mfbi->type != MFB_TYPE_OFF) {
365 switch (mfbi->index) {
366 case 0: /* plane 0 */
367 if (hw->desc[0] != ad->paddr)
0d9dab39 368 wr_reg_wa(&hw->desc[0], ad->paddr);
9b53a9e2
YS		 369 break;
370 case 1: /* plane 1 AOI 0 */
371 cmfbi = machine_data->fsl_diu_info[2]->par;
372 if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
373 if (cmfbi->count > 0) /* AOI1 open */
374 ad->next_ad =
375 cpu_to_le32(cmfbi->ad->paddr);
376 else
377 ad->next_ad = 0;
0d9dab39 378 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2
YS		 379 }
380 break;
381 case 3: /* plane 2 AOI 0 */
382 cmfbi = machine_data->fsl_diu_info[4]->par;
383 if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
384 if (cmfbi->count > 0) /* AOI1 open */
385 ad->next_ad =
386 cpu_to_le32(cmfbi->ad->paddr);
387 else
388 ad->next_ad = 0;
0d9dab39 389 wr_reg_wa(&hw->desc[2], ad->paddr);
9b53a9e2
YS		 390 }
391 break;
392 case 2: /* plane 1 AOI 1 */
393 pmfbi = machine_data->fsl_diu_info[1]->par;
394 ad->next_ad = 0;
395 if (hw->desc[1] == machine_data->dummy_ad->paddr)
0d9dab39 396 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2
YS		 397 else /* AOI0 open */
398 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
399 break;
400 case 4: /* plane 2 AOI 1 */
401 pmfbi = machine_data->fsl_diu_info[3]->par;
402 ad->next_ad = 0;
403 if (hw->desc[2] == machine_data->dummy_ad->paddr)
0d9dab39 404 wr_reg_wa(&hw->desc[2], ad->paddr);
9b53a9e2
YS		 405 else /* AOI0 was open */
406 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
407 break;
408 default:
409 res = -EINVAL;
410 break;
411 }
412 } else
413 res = -EINVAL;
414 return res;
415}
416
417static int fsl_diu_disable_panel(struct fb_info *info)
418{
419 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
420 struct diu *hw = dr.diu_reg;
421 struct diu_ad *ad = mfbi->ad;
422 struct fsl_diu_data *machine_data = mfbi->parent;
423 int res = 0;
424
425 switch (mfbi->index) {
426 case 0: /* plane 0 */
427 if (hw->desc[0] != machine_data->dummy_ad->paddr)
0d9dab39 428 wr_reg_wa(&hw->desc[0], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 429 break;
430 case 1: /* plane 1 AOI 0 */
431 cmfbi = machine_data->fsl_diu_info[2]->par;
432 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 433 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
9b53a9e2
YS		 434 /* move AOI1 to the first */
435 else /* AOI1 was closed */
0d9dab39 436 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 437 /* close AOI 0 */
438 break;
439 case 3: /* plane 2 AOI 0 */
440 cmfbi = machine_data->fsl_diu_info[4]->par;
441 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 442 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
9b53a9e2
YS		 443 /* move AOI1 to the first */
444 else /* AOI1 was closed */
0d9dab39 445 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 446 /* close AOI 0 */
447 break;
448 case 2: /* plane 1 AOI 1 */
449 pmfbi = machine_data->fsl_diu_info[1]->par;
450 if (hw->desc[1] != ad->paddr) {
451 /* AOI1 is not the first in the chain */
452 if (pmfbi->count > 0)
453 /* AOI0 is open, must be the first */
454 pmfbi->ad->next_ad = 0;
455 } else /* AOI1 is the first in the chain */
0d9dab39 456 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 457 /* close AOI 1 */
458 break;
459 case 4: /* plane 2 AOI 1 */
460 pmfbi = machine_data->fsl_diu_info[3]->par;
461 if (hw->desc[2] != ad->paddr) {
462 /* AOI1 is not the first in the chain */
463 if (pmfbi->count > 0)
464 /* AOI0 is open, must be the first */
465 pmfbi->ad->next_ad = 0;
466 } else /* AOI1 is the first in the chain */
0d9dab39 467 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 468 /* close AOI 1 */
469 break;
470 default:
471 res = -EINVAL;
472 break;
473 }
474
475 return res;
476}
477
478static void enable_lcdc(struct fb_info *info)
479{
480 struct diu *hw = dr.diu_reg;
481 struct mfb_info *mfbi = info->par;
482 struct fsl_diu_data *machine_data = mfbi->parent;
483
484 if (!machine_data->fb_enabled) {
485 out_be32(&hw->diu_mode, dr.mode);
486 machine_data->fb_enabled++;
487 }
488}
489
490static void disable_lcdc(struct fb_info *info)
491{
492 struct diu *hw = dr.diu_reg;
493 struct mfb_info *mfbi = info->par;
494 struct fsl_diu_data *machine_data = mfbi->parent;
495
496 if (machine_data->fb_enabled) {
497 out_be32(&hw->diu_mode, 0);
498 machine_data->fb_enabled = 0;
499 }
500}
501
502static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
503 struct fb_info *info)
504{
505 struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
506 struct fsl_diu_data *machine_data = mfbi->parent;
507 int available_height, upper_aoi_bottom, index = mfbi->index;
508 int lower_aoi_is_open, upper_aoi_is_open;
509 __u32 base_plane_width, base_plane_height, upper_aoi_height;
510
511 base_plane_width = machine_data->fsl_diu_info[0]->var.xres;
512 base_plane_height = machine_data->fsl_diu_info[0]->var.yres;
513
fdfaa483
YS		 514 if (mfbi->x_aoi_d < 0)
515 mfbi->x_aoi_d = 0;
516 if (mfbi->y_aoi_d < 0)
517 mfbi->y_aoi_d = 0;
9b53a9e2
YS		 518 switch (index) {
519 case 0:
520 if (mfbi->x_aoi_d != 0)
521 mfbi->x_aoi_d = 0;
522 if (mfbi->y_aoi_d != 0)
523 mfbi->y_aoi_d = 0;
524 break;
525 case 1: /* AOI 0 */
526 case 3:
527 lower_aoi_mfbi = machine_data->fsl_diu_info[index+1]->par;
528 lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
529 if (var->xres > base_plane_width)
530 var->xres = base_plane_width;
531 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
532 mfbi->x_aoi_d = base_plane_width - var->xres;
533
534 if (lower_aoi_is_open)
535 available_height = lower_aoi_mfbi->y_aoi_d;
536 else
537 available_height = base_plane_height;
538 if (var->yres > available_height)
539 var->yres = available_height;
540 if ((mfbi->y_aoi_d + var->yres) > available_height)
541 mfbi->y_aoi_d = available_height - var->yres;
542 break;
543 case 2: /* AOI 1 */
544 case 4:
545 upper_aoi_mfbi = machine_data->fsl_diu_info[index-1]->par;
546 upper_aoi_height =
547 machine_data->fsl_diu_info[index-1]->var.yres;
548 upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
549 upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
550 if (var->xres > base_plane_width)
551 var->xres = base_plane_width;
552 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
553 mfbi->x_aoi_d = base_plane_width - var->xres;
554 if (mfbi->y_aoi_d < 0)
555 mfbi->y_aoi_d = 0;
556 if (upper_aoi_is_open) {
557 if (mfbi->y_aoi_d < upper_aoi_bottom)
558 mfbi->y_aoi_d = upper_aoi_bottom;
559 available_height = base_plane_height
560 - upper_aoi_bottom;
561 } else
562 available_height = base_plane_height;
563 if (var->yres > available_height)
564 var->yres = available_height;
565 if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
566 mfbi->y_aoi_d = base_plane_height - var->yres;
567 break;
568 }
569}
570/*
571 * Checks to see if the hardware supports the state requested by var passed
572 * in. This function does not alter the hardware state! If the var passed in
573 * is slightly off by what the hardware can support then we alter the var
574 * PASSED in to what we can do. If the hardware doesn't support mode change
575 * a -EINVAL will be returned by the upper layers.
576 */
577static int fsl_diu_check_var(struct fb_var_screeninfo *var,
578 struct fb_info *info)
579{
9b53a9e2
YS		 580 if (var->xres_virtual < var->xres)
581 var->xres_virtual = var->xres;
582 if (var->yres_virtual < var->yres)
583 var->yres_virtual = var->yres;
584
585 if (var->xoffset < 0)
586 var->xoffset = 0;
587
588 if (var->yoffset < 0)
589 var->yoffset = 0;
590
591 if (var->xoffset + info->var.xres > info->var.xres_virtual)
592 var->xoffset = info->var.xres_virtual - info->var.xres;
593
594 if (var->yoffset + info->var.yres > info->var.yres_virtual)
595 var->yoffset = info->var.yres_virtual - info->var.yres;
596
597 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
598 (var->bits_per_pixel != 16))
599 var->bits_per_pixel = default_bpp;
600
601 switch (var->bits_per_pixel) {
602 case 16:
603 var->red.length = 5;
604 var->red.offset = 11;
605 var->red.msb_right = 0;
606
607 var->green.length = 6;
608 var->green.offset = 5;
609 var->green.msb_right = 0;
610
611 var->blue.length = 5;
612 var->blue.offset = 0;
613 var->blue.msb_right = 0;
614
615 var->transp.length = 0;
616 var->transp.offset = 0;
617 var->transp.msb_right = 0;
618 break;
619 case 24:
620 var->red.length = 8;
621 var->red.offset = 0;
622 var->red.msb_right = 0;
623
624 var->green.length = 8;
625 var->green.offset = 8;
626 var->green.msb_right = 0;
627
628 var->blue.length = 8;
629 var->blue.offset = 16;
630 var->blue.msb_right = 0;
631
632 var->transp.length = 0;
633 var->transp.offset = 0;
634 var->transp.msb_right = 0;
635 break;
636 case 32:
637 var->red.length = 8;
638 var->red.offset = 16;
639 var->red.msb_right = 0;
640
641 var->green.length = 8;
642 var->green.offset = 8;
643 var->green.msb_right = 0;
644
645 var->blue.length = 8;
646 var->blue.offset = 0;
647 var->blue.msb_right = 0;
648
649 var->transp.length = 8;
650 var->transp.offset = 24;
651 var->transp.msb_right = 0;
652
653 break;
654 }
9b53a9e2
YS		 655
656 var->height = -1;
657 var->width = -1;
658 var->grayscale = 0;
659
660 /* Copy nonstd field to/from sync for fbset usage */
661 var->sync |= var->nonstd;
662 var->nonstd |= var->sync;
663
664 adjust_aoi_size_position(var, info);
665 return 0;
666}
667
668static void set_fix(struct fb_info *info)
669{
670 struct fb_fix_screeninfo *fix = &info->fix;
671 struct fb_var_screeninfo *var = &info->var;
672 struct mfb_info *mfbi = info->par;
673
674 strncpy(fix->id, mfbi->id, strlen(mfbi->id));
675 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
676 fix->type = FB_TYPE_PACKED_PIXELS;
677 fix->accel = FB_ACCEL_NONE;
678 fix->visual = FB_VISUAL_TRUECOLOR;
679 fix->xpanstep = 1;
680 fix->ypanstep = 1;
681}
682
683static void update_lcdc(struct fb_info *info)
684{
685 struct fb_var_screeninfo *var = &info->var;
686 struct mfb_info *mfbi = info->par;
687 struct fsl_diu_data *machine_data = mfbi->parent;
688 struct diu *hw;
689 int i, j;
690 char __iomem *cursor_base, *gamma_table_base;
691
692 u32 temp;
693
694 hw = dr.diu_reg;
695
696 if (mfbi->type == MFB_TYPE_OFF) {
697 fsl_diu_disable_panel(info);
698 return;
699 }
700
701 diu_ops.set_monitor_port(machine_data->monitor_port);
702 gamma_table_base = pool.gamma.vaddr;
703 cursor_base = pool.cursor.vaddr;
704 /* Prep for DIU init - gamma table, cursor table */
705
706 for (i = 0; i <= 2; i++)
4a85dc8b
TT		 707 for (j = 0; j <= 255; j++)
708 *gamma_table_base++ = j;
9b53a9e2
YS		 709
710 diu_ops.set_gamma_table(machine_data->monitor_port, pool.gamma.vaddr);
711
9b53a9e2
YS		 712 disable_lcdc(info);
713
714 /* Program DIU registers */
715
716 out_be32(&hw->gamma, pool.gamma.paddr);
717 out_be32(&hw->cursor, pool.cursor.paddr);
718
719 out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */
720 out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
721 out_be32(&hw->disp_size, (var->yres << 16 | var->xres));
722 /* DISP SIZE */
9b53a9e2
YS		 723 out_be32(&hw->wb_size, 0); /* WB SIZE */
724 out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
725
726 /* Horizontal and vertical configuration register */
727 temp = var->left_margin << 22 | /* BP_H */
728 var->hsync_len << 11 | /* PW_H */
729 var->right_margin; /* FP_H */
730
731 out_be32(&hw->hsyn_para, temp);
732
733 temp = var->upper_margin << 22 | /* BP_V */
734 var->vsync_len << 11 | /* PW_V */
735 var->lower_margin; /* FP_V */
736
737 out_be32(&hw->vsyn_para, temp);
738
9b53a9e2
YS		 739 diu_ops.set_pixel_clock(var->pixclock);
740
741 out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
742 out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
743 out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
744 out_be32(&hw->plut, 0x01F5F666);
745
746 /* Enable the DIU */
747 enable_lcdc(info);
748}
749
750static int map_video_memory(struct fb_info *info)
751{
752 phys_addr_t phys;
537a1bf0 753 u32 smem_len = info->fix.line_length * info->var.yres_virtual;
9b53a9e2 754
537a1bf0 755 info->screen_base = fsl_diu_alloc(smem_len, &phys);
05946bce 756 if (info->screen_base == NULL) {
154152ae 757 dev_err(info->dev, "unable to allocate fb memory\n");
9b53a9e2
YS		 758 return -ENOMEM;
759 }
537a1bf0 760 mutex_lock(&info->mm_lock);
9b53a9e2 761 info->fix.smem_start = (unsigned long) phys;
537a1bf0
KH		 762 info->fix.smem_len = smem_len;
763 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 764 info->screen_size = info->fix.smem_len;
765
9b53a9e2
YS		 766 return 0;
767}
768
769static void unmap_video_memory(struct fb_info *info)
770{
771 fsl_diu_free(info->screen_base, info->fix.smem_len);
537a1bf0 772 mutex_lock(&info->mm_lock);
05946bce 773 info->screen_base = NULL;
9b53a9e2
YS		 774 info->fix.smem_start = 0;
775 info->fix.smem_len = 0;
537a1bf0 776 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 777}
778
ae5591e3
YS		 779/*
780 * Using the fb_var_screeninfo in fb_info we set the aoi of this
781 * particular framebuffer. It is a light version of fsl_diu_set_par.
782 */
783static int fsl_diu_set_aoi(struct fb_info *info)
784{
785 struct fb_var_screeninfo *var = &info->var;
786 struct mfb_info *mfbi = info->par;
787 struct diu_ad *ad = mfbi->ad;
788
789 /* AOI should not be greater than display size */
790 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
791 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
792 return 0;
793}
794
9b53a9e2
YS		 795/*
796 * Using the fb_var_screeninfo in fb_info we set the resolution of this
797 * particular framebuffer. This function alters the fb_fix_screeninfo stored
798 * in fb_info. It does not alter var in fb_info since we are using that
799 * data. This means we depend on the data in var inside fb_info to be
800 * supported by the hardware. fsl_diu_check_var is always called before
801 * fsl_diu_set_par to ensure this.
802 */
803static int fsl_diu_set_par(struct fb_info *info)
804{
805 unsigned long len;
806 struct fb_var_screeninfo *var = &info->var;
807 struct mfb_info *mfbi = info->par;
808 struct fsl_diu_data *machine_data = mfbi->parent;
809 struct diu_ad *ad = mfbi->ad;
810 struct diu *hw;
811
812 hw = dr.diu_reg;
813
814 set_fix(info);
815 mfbi->cursor_reset = 1;
816
817 len = info->var.yres_virtual * info->fix.line_length;
818 /* Alloc & dealloc each time resolution/bpp change */
819 if (len != info->fix.smem_len) {
820 if (info->fix.smem_start)
821 unmap_video_memory(info);
9b53a9e2
YS		 822
823 /* Memory allocation for framebuffer */
824 if (map_video_memory(info)) {
154152ae 825 dev_err(info->dev, "unable to allocate fb memory 1\n");
9b53a9e2
YS		 826 return -ENOMEM;
827 }
828 }
829
7653aaab
TT		 830 ad->pix_fmt = diu_ops.get_pixel_format(machine_data->monitor_port,
831 var->bits_per_pixel);
9b53a9e2 832 ad->addr = cpu_to_le32(info->fix.smem_start);
ae5591e3
YS		 833 ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
834 var->xres_virtual) | mfbi->g_alpha;
835 /* AOI should not be greater than display size */
9b53a9e2 836 ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
ae5591e3 837 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
9b53a9e2
YS		 838 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
839
840 /* Disable chroma keying function */
841 ad->ckmax_r = 0;
842 ad->ckmax_g = 0;
843 ad->ckmax_b = 0;
844
845 ad->ckmin_r = 255;
846 ad->ckmin_g = 255;
847 ad->ckmin_b = 255;
848
849 if (mfbi->index == 0)
850 update_lcdc(info);
851 return 0;
852}
853
854static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
855{
4a85dc8b 856 return ((val << width) + 0x7FFF - val) >> 16;
9b53a9e2
YS		 857}
858
859/*
860 * Set a single color register. The values supplied have a 16 bit magnitude
861 * which needs to be scaled in this function for the hardware. Things to take
862 * into consideration are how many color registers, if any, are supported with
863 * the current color visual. With truecolor mode no color palettes are
25985edc 864 * supported. Here a pseudo palette is created which we store the value in
9b53a9e2
YS		 865 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
866 * color palette.
867 */
4a85dc8b
TT		 868static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
869 unsigned int green, unsigned int blue,
870 unsigned int transp, struct fb_info *info)
9b53a9e2
YS		 871{
872 int ret = 1;
873
874 /*
875 * If greyscale is true, then we convert the RGB value
876 * to greyscale no matter what visual we are using.
877 */
878 if (info->var.grayscale)
879 red = green = blue = (19595 * red + 38470 * green +
880 7471 * blue) >> 16;
881 switch (info->fix.visual) {
882 case FB_VISUAL_TRUECOLOR:
883 /*
884 * 16-bit True Colour. We encode the RGB value
885 * according to the RGB bitfield information.
886 */
887 if (regno < 16) {
888 u32 *pal = info->pseudo_palette;
889 u32 v;
890
891 red = CNVT_TOHW(red, info->var.red.length);
892 green = CNVT_TOHW(green, info->var.green.length);
893 blue = CNVT_TOHW(blue, info->var.blue.length);
894 transp = CNVT_TOHW(transp, info->var.transp.length);
895
896 v = (red << info->var.red.offset) |
897 (green << info->var.green.offset) |
898 (blue << info->var.blue.offset) |
899 (transp << info->var.transp.offset);
900
901 pal[regno] = v;
902 ret = 0;
903 }
904 break;
9b53a9e2
YS		 905 }
906
907 return ret;
908}
909
910/*
911 * Pan (or wrap, depending on the `vmode' field) the display using the
912 * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
913 * don't fit, return -EINVAL.
914 */
915static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
916 struct fb_info *info)
917{
918 if ((info->var.xoffset == var->xoffset) &&
919 (info->var.yoffset == var->yoffset))
920 return 0; /* No change, do nothing */
921
922 if (var->xoffset < 0 || var->yoffset < 0
923 || var->xoffset + info->var.xres > info->var.xres_virtual
924 || var->yoffset + info->var.yres > info->var.yres_virtual)
925 return -EINVAL;
926
927 info->var.xoffset = var->xoffset;
928 info->var.yoffset = var->yoffset;
929
930 if (var->vmode & FB_VMODE_YWRAP)
931 info->var.vmode |= FB_VMODE_YWRAP;
932 else
933 info->var.vmode &= ~FB_VMODE_YWRAP;
934
ae5591e3
YS		 935 fsl_diu_set_aoi(info);
936
9b53a9e2
YS		 937 return 0;
938}
939
940/*
941 * Blank the screen if blank_mode != 0, else unblank. Return 0 if blanking
942 * succeeded, != 0 if un-/blanking failed.
943 * blank_mode == 2: suspend vsync
944 * blank_mode == 3: suspend hsync
945 * blank_mode == 4: powerdown
946 */
947static int fsl_diu_blank(int blank_mode, struct fb_info *info)
948{
949 struct mfb_info *mfbi = info->par;
950
951 mfbi->blank = blank_mode;
952
953 switch (blank_mode) {
954 case FB_BLANK_VSYNC_SUSPEND:
955 case FB_BLANK_HSYNC_SUSPEND:
956 /* FIXME: fixes to enable_panel and enable lcdc needed */
957 case FB_BLANK_NORMAL:
958 /* fsl_diu_disable_panel(info);*/
959 break;
960 case FB_BLANK_POWERDOWN:
961 /* disable_lcdc(info); */
962 break;
963 case FB_BLANK_UNBLANK:
964 /* fsl_diu_enable_panel(info);*/
965 break;
966 }
967
968 return 0;
969}
970
971static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
972 unsigned long arg)
973{
974 struct mfb_info *mfbi = info->par;
975 struct diu_ad *ad = mfbi->ad;
976 struct mfb_chroma_key ck;
977 unsigned char global_alpha;
978 struct aoi_display_offset aoi_d;
979 __u32 pix_fmt;
980 void __user *buf = (void __user *)arg;
981
982 if (!arg)
983 return -EINVAL;
984 switch (cmd) {
985 case MFB_SET_PIXFMT:
986 if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
987 return -EFAULT;
988 ad->pix_fmt = pix_fmt;
9b53a9e2
YS		 989 break;
990 case MFB_GET_PIXFMT:
991 pix_fmt = ad->pix_fmt;
992 if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
993 return -EFAULT;
9b53a9e2
YS		 994 break;
995 case MFB_SET_AOID:
996 if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
997 return -EFAULT;
998 mfbi->x_aoi_d = aoi_d.x_aoi_d;
999 mfbi->y_aoi_d = aoi_d.y_aoi_d;
9b53a9e2 1000 fsl_diu_check_var(&info->var, info);
ae5591e3 1001 fsl_diu_set_aoi(info);
9b53a9e2
YS		 1002 break;
1003 case MFB_GET_AOID:
1004 aoi_d.x_aoi_d = mfbi->x_aoi_d;
1005 aoi_d.y_aoi_d = mfbi->y_aoi_d;
1006 if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
1007 return -EFAULT;
9b53a9e2
YS		 1008 break;
1009 case MFB_GET_ALPHA:
1010 global_alpha = mfbi->g_alpha;
1011 if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
1012 return -EFAULT;
9b53a9e2
YS		 1013 break;
1014 case MFB_SET_ALPHA:
1015 /* set panel information */
1016 if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
1017 return -EFAULT;
1018 ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
1019 (global_alpha & 0xff);
1020 mfbi->g_alpha = global_alpha;
9b53a9e2
YS		 1021 break;
1022 case MFB_SET_CHROMA_KEY:
1023 /* set panel winformation */
1024 if (copy_from_user(&ck, buf, sizeof(ck)))
1025 return -EFAULT;
1026
1027 if (ck.enable &&
1028 (ck.red_max < ck.red_min ||
1029 ck.green_max < ck.green_min ||
1030 ck.blue_max < ck.blue_min))
1031 return -EINVAL;
1032
1033 if (!ck.enable) {
1034 ad->ckmax_r = 0;
1035 ad->ckmax_g = 0;
1036 ad->ckmax_b = 0;
1037 ad->ckmin_r = 255;
1038 ad->ckmin_g = 255;
1039 ad->ckmin_b = 255;
1040 } else {
1041 ad->ckmax_r = ck.red_max;
1042 ad->ckmax_g = ck.green_max;
1043 ad->ckmax_b = ck.blue_max;
1044 ad->ckmin_r = ck.red_min;
1045 ad->ckmin_g = ck.green_min;
1046 ad->ckmin_b = ck.blue_min;
1047 }
9b53a9e2
YS		 1048 break;
1049 case FBIOGET_GWINFO:
1050 if (mfbi->type == MFB_TYPE_OFF)
1051 return -ENODEV;
1052 /* get graphic window information */
1053 if (copy_to_user(buf, ad, sizeof(*ad)))
1054 return -EFAULT;
1055 break;
9b53a9e2
YS		 1056
1057 default:
154152ae 1058 dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd);
9b53a9e2
YS		 1059 return -ENOIOCTLCMD;
1060 }
1061
1062 return 0;
1063}
1064
1065/* turn on fb if count == 1
1066 */
1067static int fsl_diu_open(struct fb_info *info, int user)
1068{
1069 struct mfb_info *mfbi = info->par;
1070 int res = 0;
1071
4b5006ec
AG		 1072 /* free boot splash memory on first /dev/fb0 open */
1073 if (!mfbi->index && diu_ops.release_bootmem)
1074 diu_ops.release_bootmem();
1075
9b53a9e2
YS		 1076 spin_lock(&diu_lock);
1077 mfbi->count++;
1078 if (mfbi->count == 1) {
9b53a9e2
YS		 1079 fsl_diu_check_var(&info->var, info);
1080 res = fsl_diu_set_par(info);
1081 if (res < 0)
1082 mfbi->count--;
1083 else {
1084 res = fsl_diu_enable_panel(info);
1085 if (res < 0)
1086 mfbi->count--;
1087 }
1088 }
1089
1090 spin_unlock(&diu_lock);
1091 return res;
1092}
1093
1094/* turn off fb if count == 0
1095 */
1096static int fsl_diu_release(struct fb_info *info, int user)
1097{
1098 struct mfb_info *mfbi = info->par;
1099 int res = 0;
1100
1101 spin_lock(&diu_lock);
1102 mfbi->count--;
1103 if (mfbi->count == 0) {
9b53a9e2
YS		 1104 res = fsl_diu_disable_panel(info);
1105 if (res < 0)
1106 mfbi->count++;
1107 }
1108 spin_unlock(&diu_lock);
1109 return res;
1110}
1111
1112static struct fb_ops fsl_diu_ops = {
1113 .owner = THIS_MODULE,
1114 .fb_check_var = fsl_diu_check_var,
1115 .fb_set_par = fsl_diu_set_par,
1116 .fb_setcolreg = fsl_diu_setcolreg,
1117 .fb_blank = fsl_diu_blank,
1118 .fb_pan_display = fsl_diu_pan_display,
1119 .fb_fillrect = cfb_fillrect,
1120 .fb_copyarea = cfb_copyarea,
1121 .fb_imageblit = cfb_imageblit,
1122 .fb_ioctl = fsl_diu_ioctl,
1123 .fb_open = fsl_diu_open,
1124 .fb_release = fsl_diu_release,
1125};
1126
1127static int init_fbinfo(struct fb_info *info)
1128{
1129 struct mfb_info *mfbi = info->par;
1130
1131 info->device = NULL;
1132 info->var.activate = FB_ACTIVATE_NOW;
1133 info->fbops = &fsl_diu_ops;
1134 info->flags = FBINFO_FLAG_DEFAULT;
1135 info->pseudo_palette = &mfbi->pseudo_palette;
1136
1137 /* Allocate colormap */
1138 fb_alloc_cmap(&info->cmap, 16, 0);
1139 return 0;
1140}
1141
05946bce 1142static int __devinit install_fb(struct fb_info *info)
9b53a9e2
YS		 1143{
1144 int rc;
1145 struct mfb_info *mfbi = info->par;
1146 const char *aoi_mode, *init_aoi_mode = "320x240";
8b856f04
AG		 1147 struct fb_videomode *db = fsl_diu_mode_db;
1148 unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
1149 int has_default_mode = 1;
9b53a9e2
YS		 1150
1151 if (init_fbinfo(info))
1152 return -EINVAL;
1153
8b856f04
AG		 1154 if (mfbi->index == 0) { /* plane 0 */
1155 if (mfbi->edid_data) {
1156 /* Now build modedb from EDID */
1157 fb_edid_to_monspecs(mfbi->edid_data, &info->monspecs);
1158 fb_videomode_to_modelist(info->monspecs.modedb,
1159 info->monspecs.modedb_len,
1160 &info->modelist);
1161 db = info->monspecs.modedb;
1162 dbsize = info->monspecs.modedb_len;
1163 }
9b53a9e2 1164 aoi_mode = fb_mode;
8b856f04 1165 } else {
9b53a9e2 1166 aoi_mode = init_aoi_mode;
8b856f04 1167 }
8b856f04
AG		 1168 rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize,
1169 &fsl_diu_default_mode, default_bpp);
154152ae 1170 if (!rc) {
8b856f04
AG		 1171 /*
1172 * For plane 0 we continue and look into
1173 * driver's internal modedb.
1174 */
1175 if (mfbi->index == 0 && mfbi->edid_data)
1176 has_default_mode = 0;
1177 else
1178 return -EINVAL;
9b53a9e2
YS		 1179 }
1180
8b856f04
AG		 1181 if (!has_default_mode) {
1182 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
1183 ARRAY_SIZE(fsl_diu_mode_db),
1184 &fsl_diu_default_mode,
1185 default_bpp);
1186 if (rc > 0 && rc < 5)
1187 has_default_mode = 1;
1188 }
1189
1190 /* Still not found, use preferred mode from database if any */
1191 if (!has_default_mode && info->monspecs.modedb) {
1192 struct fb_monspecs *specs = &info->monspecs;
1193 struct fb_videomode *modedb = &specs->modedb[0];
1194
1195 /*
1196 * Get preferred timing. If not found,
1197 * first mode in database will be used.
1198 */
1199 if (specs->misc & FB_MISC_1ST_DETAIL) {
1200 int i;
1201
1202 for (i = 0; i < specs->modedb_len; i++) {
1203 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1204 modedb = &specs->modedb[i];
1205 break;
1206 }
1207 }
1208 }
1209
1210 info->var.bits_per_pixel = default_bpp;
1211 fb_videomode_to_var(&info->var, modedb);
1212 }
1213
9b53a9e2
YS		 1214 if (mfbi->type == MFB_TYPE_OFF)
1215 mfbi->blank = FB_BLANK_NORMAL;
1216 else
1217 mfbi->blank = FB_BLANK_UNBLANK;
1218
1219 if (fsl_diu_check_var(&info->var, info)) {
154152ae 1220 dev_err(info->dev, "fsl_diu_check_var failed\n");
9b53a9e2
YS		 1221 fb_dealloc_cmap(&info->cmap);
1222 return -EINVAL;
1223 }
1224
9b53a9e2 1225 if (register_framebuffer(info) < 0) {
154152ae 1226 dev_err(info->dev, "register_framebuffer failed\n");
9b53a9e2
YS		 1227 unmap_video_memory(info);
1228 fb_dealloc_cmap(&info->cmap);
1229 return -EINVAL;
1230 }
1231
1232 mfbi->registered = 1;
154152ae 1233 dev_info(info->dev, "%s registered successfully\n", mfbi->id);
9b53a9e2
YS		 1234
1235 return 0;
1236}
1237
05946bce 1238static void uninstall_fb(struct fb_info *info)
9b53a9e2
YS		 1239{
1240 struct mfb_info *mfbi = info->par;
1241
1242 if (!mfbi->registered)
1243 return;
1244
8b856f04
AG		 1245 if (mfbi->index == 0)
1246 kfree(mfbi->edid_data);
1247
9b53a9e2
YS		 1248 unregister_framebuffer(info);
1249 unmap_video_memory(info);
1250 if (&info->cmap)
1251 fb_dealloc_cmap(&info->cmap);
1252
1253 mfbi->registered = 0;
1254}
1255
1256static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
1257{
1258 struct diu *hw = dr.diu_reg;
1259 unsigned int status = in_be32(&hw->int_status);
1260
1261 if (status) {
1262 /* This is the workaround for underrun */
1263 if (status & INT_UNDRUN) {
1264 out_be32(&hw->diu_mode, 0);
9b53a9e2
YS		 1265 udelay(1);
1266 out_be32(&hw->diu_mode, 1);
1267 }
1268#if defined(CONFIG_NOT_COHERENT_CACHE)
1269 else if (status & INT_VSYNC) {
1270 unsigned int i;
4a85dc8b 1271
9b53a9e2
YS		 1272 for (i = 0; i < coherence_data_size;
1273 i += d_cache_line_size)
1274 __asm__ __volatile__ (
1275 "dcbz 0, %[input]"
1276 ::[input]"r"(&coherence_data[i]));
1277 }
1278#endif
1279 return IRQ_HANDLED;
1280 }
1281 return IRQ_NONE;
1282}
1283
1284static int request_irq_local(int irq)
1285{
1286 unsigned long status, ints;
1287 struct diu *hw;
1288 int ret;
1289
1290 hw = dr.diu_reg;
1291
1292 /* Read to clear the status */
1293 status = in_be32(&hw->int_status);
1294
05946bce 1295 ret = request_irq(irq, fsl_diu_isr, 0, "diu", NULL);
154152ae 1296 if (!ret) {
9b53a9e2
YS		 1297 ints = INT_PARERR | INT_LS_BF_VS;
1298#if !defined(CONFIG_NOT_COHERENT_CACHE)
1299 ints |= INT_VSYNC;
1300#endif
4a85dc8b 1301
9b53a9e2
YS		 1302 if (dr.mode == MFB_MODE2 || dr.mode == MFB_MODE3)
1303 ints |= INT_VSYNC_WB;
1304
1305 /* Read to clear the status */
1306 status = in_be32(&hw->int_status);
1307 out_be32(&hw->int_mask, ints);
1308 }
4a85dc8b 1309
9b53a9e2
YS		 1310 return ret;
1311}
1312
1313static void free_irq_local(int irq)
1314{
1315 struct diu *hw = dr.diu_reg;
1316
1317 /* Disable all LCDC interrupt */
1318 out_be32(&hw->int_mask, 0x1f);
1319
05946bce 1320 free_irq(irq, NULL);
9b53a9e2
YS		 1321}
1322
1323#ifdef CONFIG_PM
1324/*
1325 * Power management hooks. Note that we won't be called from IRQ context,
1326 * unlike the blank functions above, so we may sleep.
1327 */
2dc11581 1328static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state)
9b53a9e2
YS		 1329{
1330 struct fsl_diu_data *machine_data;
1331
48948a3e 1332 machine_data = dev_get_drvdata(&ofdev->dev);
9b53a9e2
YS		 1333 disable_lcdc(machine_data->fsl_diu_info[0]);
1334
1335 return 0;
1336}
1337
2dc11581 1338static int fsl_diu_resume(struct platform_device *ofdev)
9b53a9e2
YS		 1339{
1340 struct fsl_diu_data *machine_data;
1341
48948a3e 1342 machine_data = dev_get_drvdata(&ofdev->dev);
9b53a9e2
YS		 1343 enable_lcdc(machine_data->fsl_diu_info[0]);
1344
1345 return 0;
1346}
1347
1348#else
1349#define fsl_diu_suspend NULL
1350#define fsl_diu_resume NULL
1351#endif /* CONFIG_PM */
1352
1353/* Align to 64-bit(8-byte), 32-byte, etc. */
f3791889
AV		 1354static int allocate_buf(struct device *dev, struct diu_addr *buf, u32 size,
1355 u32 bytes_align)
9b53a9e2
YS		 1356{
1357 u32 offset, ssize;
1358 u32 mask;
1359 dma_addr_t paddr = 0;
1360
1361 ssize = size + bytes_align;
f3791889 1362 buf->vaddr = dma_alloc_coherent(dev, ssize, &paddr, GFP_DMA |
05946bce 1363 __GFP_ZERO);
9b53a9e2
YS		 1364 if (!buf->vaddr)
1365 return -ENOMEM;
1366
1367 buf->paddr = (__u32) paddr;
1368
1369 mask = bytes_align - 1;
1370 offset = (u32)buf->paddr & mask;
1371 if (offset) {
1372 buf->offset = bytes_align - offset;
1373 buf->paddr = (u32)buf->paddr + offset;
1374 } else
1375 buf->offset = 0;
4a85dc8b 1376
9b53a9e2
YS		 1377 return 0;
1378}
1379
f3791889
AV		 1380static void free_buf(struct device *dev, struct diu_addr *buf, u32 size,
1381 u32 bytes_align)
9b53a9e2 1382{
4a85dc8b
TT		 1383 dma_free_coherent(dev, size + bytes_align, buf->vaddr,
1384 buf->paddr - buf->offset);
9b53a9e2
YS		 1385}
1386
1387static ssize_t store_monitor(struct device *device,
1388 struct device_attribute *attr, const char *buf, size_t count)
1389{
7653aaab 1390 enum fsl_diu_monitor_port old_monitor_port;
9b53a9e2
YS		 1391 struct fsl_diu_data *machine_data =
1392 container_of(attr, struct fsl_diu_data, dev_attr);
1393
9b53a9e2 1394 old_monitor_port = machine_data->monitor_port;
7653aaab 1395 machine_data->monitor_port = fsl_diu_name_to_port(buf);
9b53a9e2
YS		 1396
1397 if (old_monitor_port != machine_data->monitor_port) {
1398 /* All AOIs need adjust pixel format
1399 * fsl_diu_set_par only change the pixsel format here
1400 * unlikely to fail. */
1401 fsl_diu_set_par(machine_data->fsl_diu_info[0]);
1402 fsl_diu_set_par(machine_data->fsl_diu_info[1]);
1403 fsl_diu_set_par(machine_data->fsl_diu_info[2]);
1404 fsl_diu_set_par(machine_data->fsl_diu_info[3]);
1405 fsl_diu_set_par(machine_data->fsl_diu_info[4]);
1406 }
1407 return count;
1408}
1409
1410static ssize_t show_monitor(struct device *device,
1411 struct device_attribute *attr, char *buf)
1412{
1413 struct fsl_diu_data *machine_data =
1414 container_of(attr, struct fsl_diu_data, dev_attr);
7653aaab
TT		 1415
1416 switch (machine_data->monitor_port) {
1417 case FSL_DIU_PORT_DVI:
1418 return sprintf(buf, "DVI\n");
1419 case FSL_DIU_PORT_LVDS:
1420 return sprintf(buf, "Single-link LVDS\n");
1421 case FSL_DIU_PORT_DLVDS:
1422 return sprintf(buf, "Dual-link LVDS\n");
1423 }
1424
1425 return 0;
9b53a9e2
YS		 1426}
1427
9e52ba61 1428static int __devinit fsl_diu_probe(struct platform_device *pdev)
9b53a9e2 1429{
9e52ba61 1430 struct device_node *np = pdev->dev.of_node;
9b53a9e2 1431 struct mfb_info *mfbi;
89f08e3e 1432 phys_addr_t dummy_ad_addr = 0;
9b53a9e2 1433 int ret, i, error = 0;
9b53a9e2 1434 struct fsl_diu_data *machine_data;
4b5006ec 1435 int diu_mode;
9b53a9e2
YS		 1436
1437 machine_data = kzalloc(sizeof(struct fsl_diu_data), GFP_KERNEL);
1438 if (!machine_data)
1439 return -ENOMEM;
1440
1441 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
1442 machine_data->fsl_diu_info[i] =
9e52ba61 1443 framebuffer_alloc(sizeof(struct mfb_info), &pdev->dev);
9b53a9e2 1444 if (!machine_data->fsl_diu_info[i]) {
9e52ba61 1445 dev_err(&pdev->dev, "cannot allocate memory\n");
9b53a9e2
YS		 1446 ret = -ENOMEM;
1447 goto error2;
1448 }
1449 mfbi = machine_data->fsl_diu_info[i]->par;
1450 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
1451 mfbi->parent = machine_data;
8b856f04
AG		 1452
1453 if (mfbi->index == 0) {
1454 const u8 *prop;
1455 int len;
1456
1457 /* Get EDID */
1458 prop = of_get_property(np, "edid", &len);
1459 if (prop && len == EDID_LENGTH)
1460 mfbi->edid_data = kmemdup(prop, EDID_LENGTH,
1461 GFP_KERNEL);
1462 }
9b53a9e2
YS		 1463 }
1464
9e52ba61 1465 dr.diu_reg = of_iomap(np, 0);
9b53a9e2 1466 if (!dr.diu_reg) {
9e52ba61 1467 dev_err(&pdev->dev, "cannot map DIU registers\n");
9b53a9e2
YS		 1468 ret = -EFAULT;
1469 goto error2;
1470 }
1471
4b5006ec
AG		 1472 diu_mode = in_be32(&dr.diu_reg->diu_mode);
1473 if (diu_mode != MFB_MODE1)
1474 out_be32(&dr.diu_reg->diu_mode, 0); /* disable DIU */
9b53a9e2
YS		 1475
1476 /* Get the IRQ of the DIU */
1477 machine_data->irq = irq_of_parse_and_map(np, 0);
1478
1479 if (!machine_data->irq) {
9e52ba61 1480 dev_err(&pdev->dev, "could not get DIU IRQ\n");
9b53a9e2
YS		 1481 ret = -EINVAL;
1482 goto error;
1483 }
1484 machine_data->monitor_port = monitor_port;
1485
1486 /* Area descriptor memory pool aligns to 64-bit boundary */
9e52ba61 1487 if (allocate_buf(&pdev->dev, &pool.ad,
f3791889 1488 sizeof(struct diu_ad) * FSL_AOI_NUM, 8))
9b53a9e2
YS		 1489 return -ENOMEM;
1490
1491 /* Get memory for Gamma Table - 32-byte aligned memory */
9e52ba61 1492 if (allocate_buf(&pdev->dev, &pool.gamma, 768, 32)) {
9b53a9e2
YS		 1493 ret = -ENOMEM;
1494 goto error;
1495 }
1496
1497 /* For performance, cursor bitmap buffer aligns to 32-byte boundary */
9e52ba61 1498 if (allocate_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
f3791889 1499 32)) {
9b53a9e2
YS		 1500 ret = -ENOMEM;
1501 goto error;
1502 }
1503
1504 i = ARRAY_SIZE(machine_data->fsl_diu_info);
1505 machine_data->dummy_ad = (struct diu_ad *)
1506 ((u32)pool.ad.vaddr + pool.ad.offset) + i;
1507 machine_data->dummy_ad->paddr = pool.ad.paddr +
1508 i * sizeof(struct diu_ad);
1509 machine_data->dummy_aoi_virt = fsl_diu_alloc(64, &dummy_ad_addr);
1510 if (!machine_data->dummy_aoi_virt) {
1511 ret = -ENOMEM;
1512 goto error;
1513 }
1514 machine_data->dummy_ad->addr = cpu_to_le32(dummy_ad_addr);
1515 machine_data->dummy_ad->pix_fmt = 0x88882317;
1516 machine_data->dummy_ad->src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
1517 machine_data->dummy_ad->aoi_size = cpu_to_le32((4 << 16) | 2);
1518 machine_data->dummy_ad->offset_xyi = 0;
1519 machine_data->dummy_ad->offset_xyd = 0;
1520 machine_data->dummy_ad->next_ad = 0;
1521
4b5006ec
AG		 1522 /*
1523 * Let DIU display splash screen if it was pre-initialized
1524 * by the bootloader, set dummy area descriptor otherwise.
1525 */
1526 if (diu_mode != MFB_MODE1)
1527 out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr);
1528
9b53a9e2
YS		 1529 out_be32(&dr.diu_reg->desc[1], machine_data->dummy_ad->paddr);
1530 out_be32(&dr.diu_reg->desc[2], machine_data->dummy_ad->paddr);
1531
1532 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
1533 machine_data->fsl_diu_info[i]->fix.smem_start = 0;
1534 mfbi = machine_data->fsl_diu_info[i]->par;
1535 mfbi->ad = (struct diu_ad *)((u32)pool.ad.vaddr
1536 + pool.ad.offset) + i;
1537 mfbi->ad->paddr = pool.ad.paddr + i * sizeof(struct diu_ad);
1538 ret = install_fb(machine_data->fsl_diu_info[i]);
1539 if (ret) {
9e52ba61 1540 dev_err(&pdev->dev, "could not register fb %d\n", i);
9b53a9e2
YS		 1541 goto error;
1542 }
1543 }
1544
1545 if (request_irq_local(machine_data->irq)) {
9e52ba61 1546 dev_err(&pdev->dev, "could not claim irq\n");
9b53a9e2
YS		 1547 goto error;
1548 }
1549
12765517 1550 sysfs_attr_init(&machine_data->dev_attr.attr);
9b53a9e2
YS		 1551 machine_data->dev_attr.attr.name = "monitor";
1552 machine_data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
1553 machine_data->dev_attr.show = show_monitor;
1554 machine_data->dev_attr.store = store_monitor;
1555 error = device_create_file(machine_data->fsl_diu_info[0]->dev,
1556 &machine_data->dev_attr);
1557 if (error) {
9e52ba61 1558 dev_err(&pdev->dev, "could not create sysfs file %s\n",
9b53a9e2
YS		 1559 machine_data->dev_attr.attr.name);
1560 }
1561
9e52ba61 1562 dev_set_drvdata(&pdev->dev, machine_data);
9b53a9e2
YS		 1563 return 0;
1564
1565error:
1566 for (i = ARRAY_SIZE(machine_data->fsl_diu_info);
1567 i > 0; i--)
1568 uninstall_fb(machine_data->fsl_diu_info[i - 1]);
1569 if (pool.ad.vaddr)
9e52ba61 1570 free_buf(&pdev->dev, &pool.ad,
f3791889 1571 sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
9b53a9e2 1572 if (pool.gamma.vaddr)
9e52ba61 1573 free_buf(&pdev->dev, &pool.gamma, 768, 32);
9b53a9e2 1574 if (pool.cursor.vaddr)
9e52ba61 1575 free_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
f3791889 1576 32);
9b53a9e2
YS		 1577 if (machine_data->dummy_aoi_virt)
1578 fsl_diu_free(machine_data->dummy_aoi_virt, 64);
1579 iounmap(dr.diu_reg);
1580
1581error2:
1582 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1583 if (machine_data->fsl_diu_info[i])
1584 framebuffer_release(machine_data->fsl_diu_info[i]);
1585 kfree(machine_data);
1586
1587 return ret;
1588}
1589
9e52ba61 1590static int fsl_diu_remove(struct platform_device *pdev)
9b53a9e2
YS		 1591{
1592 struct fsl_diu_data *machine_data;
1593 int i;
1594
9e52ba61 1595 machine_data = dev_get_drvdata(&pdev->dev);
9b53a9e2
YS		 1596 disable_lcdc(machine_data->fsl_diu_info[0]);
1597 free_irq_local(machine_data->irq);
1598 for (i = ARRAY_SIZE(machine_data->fsl_diu_info); i > 0; i--)
1599 uninstall_fb(machine_data->fsl_diu_info[i - 1]);
1600 if (pool.ad.vaddr)
9e52ba61 1601 free_buf(&pdev->dev, &pool.ad,
f3791889 1602 sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
9b53a9e2 1603 if (pool.gamma.vaddr)
9e52ba61 1604 free_buf(&pdev->dev, &pool.gamma, 768, 32);
9b53a9e2 1605 if (pool.cursor.vaddr)
9e52ba61 1606 free_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2, 32);
9b53a9e2
YS		 1607 if (machine_data->dummy_aoi_virt)
1608 fsl_diu_free(machine_data->dummy_aoi_virt, 64);
1609 iounmap(dr.diu_reg);
1610 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1611 if (machine_data->fsl_diu_info[i])
1612 framebuffer_release(machine_data->fsl_diu_info[i]);
1613 kfree(machine_data);
1614
1615 return 0;
1616}
1617
1618#ifndef MODULE
1619static int __init fsl_diu_setup(char *options)
1620{
1621 char *opt;
1622 unsigned long val;
1623
1624 if (!options || !*options)
1625 return 0;
1626
1627 while ((opt = strsep(&options, ",")) != NULL) {
1628 if (!*opt)
1629 continue;
1630 if (!strncmp(opt, "monitor=", 8)) {
7653aaab 1631 monitor_port = fsl_diu_name_to_port(opt + 8);
9b53a9e2
YS		 1632 } else if (!strncmp(opt, "bpp=", 4)) {
1633 if (!strict_strtoul(opt + 4, 10, &val))
1634 default_bpp = val;
1635 } else
1636 fb_mode = opt;
1637 }
1638
1639 return 0;
1640}
1641#endif
1642
1643static struct of_device_id fsl_diu_match[] = {
d24720a4
AG		 1644#ifdef CONFIG_PPC_MPC512x
1645 {
1646 .compatible = "fsl,mpc5121-diu",
1647 },
1648#endif
9b53a9e2
YS		 1649 {
1650 .compatible = "fsl,diu",
1651 },
1652 {}
1653};
1654MODULE_DEVICE_TABLE(of, fsl_diu_match);
1655
28541d0f 1656static struct platform_driver fsl_diu_driver = {
4018294b
GL		 1657 .driver = {
1658 .name = "fsl_diu",
1659 .owner = THIS_MODULE,
1660 .of_match_table = fsl_diu_match,
1661 },
9b53a9e2
YS		 1662 .probe = fsl_diu_probe,
1663 .remove = fsl_diu_remove,
1664 .suspend = fsl_diu_suspend,
1665 .resume = fsl_diu_resume,
1666};
1667
1668static int __init fsl_diu_init(void)
1669{
1670#ifdef CONFIG_NOT_COHERENT_CACHE
1671 struct device_node *np;
1672 const u32 *prop;
1673#endif
1674 int ret;
1675#ifndef MODULE
1676 char *option;
1677
1678 /*
1679 * For kernel boot options (in 'video=xxxfb:<options>' format)
1680 */
1681 if (fb_get_options("fslfb", &option))
1682 return -ENODEV;
1683 fsl_diu_setup(option);
7653aaab
TT		 1684#else
1685 monitor_port = fsl_diu_name_to_port(monitor_string);
9b53a9e2 1686#endif
154152ae 1687 pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
9b53a9e2
YS		 1688
1689#ifdef CONFIG_NOT_COHERENT_CACHE
1690 np = of_find_node_by_type(NULL, "cpu");
1691 if (!np) {
154152ae 1692 pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
9b53a9e2
YS		 1693 return -ENODEV;
1694 }
1695
1696 prop = of_get_property(np, "d-cache-size", NULL);
5394ba0f 1697 if (prop == NULL) {
154152ae
TT		 1698 pr_err("fsl-diu-fb: missing 'd-cache-size' property' "
1699 "in 'cpu' node\n");
5394ba0f 1700 of_node_put(np);
9b53a9e2 1701 return -ENODEV;
5394ba0f 1702 }
9b53a9e2 1703
4a85dc8b
TT		 1704 /*
1705 * Freescale PLRU requires 13/8 times the cache size to do a proper
1706 * displacement flush
9b53a9e2 1707 */
9e52ba61 1708 coherence_data_size = be32_to_cpup(prop) * 13;
9b53a9e2
YS		 1709 coherence_data_size /= 8;
1710
1711 prop = of_get_property(np, "d-cache-line-size", NULL);
5394ba0f 1712 if (prop == NULL) {
154152ae
TT		 1713 pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' "
1714 "in 'cpu' node\n");
5394ba0f 1715 of_node_put(np);
9b53a9e2 1716 return -ENODEV;
5394ba0f 1717 }
9e52ba61 1718 d_cache_line_size = be32_to_cpup(prop);
9b53a9e2
YS		 1719
1720 of_node_put(np);
1721 coherence_data = vmalloc(coherence_data_size);
1722 if (!coherence_data)
1723 return -ENOMEM;
1724#endif
4a85dc8b 1725
28541d0f 1726 ret = platform_driver_register(&fsl_diu_driver);
9b53a9e2 1727 if (ret) {
154152ae 1728 pr_err("fsl-diu-fb: failed to register platform driver\n");
9b53a9e2
YS		 1729#if defined(CONFIG_NOT_COHERENT_CACHE)
1730 vfree(coherence_data);
1731#endif
1732 iounmap(dr.diu_reg);
1733 }
1734 return ret;
1735}
1736
1737static void __exit fsl_diu_exit(void)
1738{
28541d0f 1739 platform_driver_unregister(&fsl_diu_driver);
9b53a9e2
YS		 1740#if defined(CONFIG_NOT_COHERENT_CACHE)
1741 vfree(coherence_data);
1742#endif
1743}
1744
1745module_init(fsl_diu_init);
1746module_exit(fsl_diu_exit);
1747
1748MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
1749MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
1750MODULE_LICENSE("GPL");
1751
1752module_param_named(mode, fb_mode, charp, 0);
1753MODULE_PARM_DESC(mode,
1754 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
1755module_param_named(bpp, default_bpp, ulong, 0);
154152ae 1756MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'");
7653aaab
TT		 1757module_param_named(monitor, monitor_string, charp, 0);
1758MODULE_PARM_DESC(monitor, "Specify the monitor port "
1759 "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
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Linux kernel - Deliverables
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