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powerpc/5121: doc/dts-bindings: update doc of FSL DIU bindings
[deliverable/linux.git] / drivers / video / fsl-diu-fb.c
CommitLineData
9b53a9e2
YS		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Freescale DIU Frame Buffer device driver
5 *
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
10 *
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/uaccess.h>
32#include <linux/vmalloc.h>
33
34#include <linux/of_platform.h>
35
36#include <sysdev/fsl_soc.h>
0814a979 37#include <linux/fsl-diu-fb.h>
9b53a9e2
YS		 38
39/*
40 * These parameters give default parameters
41 * for video output 1024x768,
42 * FIXME - change timing to proper amounts
43 * hsync 31.5kHz, vsync 60Hz
44 */
45static struct fb_videomode __devinitdata fsl_diu_default_mode = {
46 .refresh = 60,
47 .xres = 1024,
48 .yres = 768,
49 .pixclock = 15385,
50 .left_margin = 160,
51 .right_margin = 24,
52 .upper_margin = 29,
53 .lower_margin = 3,
54 .hsync_len = 136,
55 .vsync_len = 6,
56 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
57 .vmode = FB_VMODE_NONINTERLACED
58};
59
60static struct fb_videomode __devinitdata fsl_diu_mode_db[] = {
61 {
62 .name = "1024x768-60",
63 .refresh = 60,
64 .xres = 1024,
65 .yres = 768,
66 .pixclock = 15385,
67 .left_margin = 160,
68 .right_margin = 24,
69 .upper_margin = 29,
70 .lower_margin = 3,
71 .hsync_len = 136,
72 .vsync_len = 6,
73 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
74 .vmode = FB_VMODE_NONINTERLACED
75 },
76 {
77 .name = "1024x768-70",
78 .refresh = 70,
79 .xres = 1024,
80 .yres = 768,
81 .pixclock = 16886,
82 .left_margin = 3,
83 .right_margin = 3,
84 .upper_margin = 2,
85 .lower_margin = 2,
86 .hsync_len = 40,
87 .vsync_len = 18,
88 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
89 .vmode = FB_VMODE_NONINTERLACED
90 },
91 {
92 .name = "1024x768-75",
93 .refresh = 75,
94 .xres = 1024,
95 .yres = 768,
96 .pixclock = 15009,
97 .left_margin = 3,
98 .right_margin = 3,
99 .upper_margin = 2,
100 .lower_margin = 2,
101 .hsync_len = 80,
102 .vsync_len = 32,
103 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
104 .vmode = FB_VMODE_NONINTERLACED
105 },
106 {
107 .name = "1280x1024-60",
108 .refresh = 60,
109 .xres = 1280,
110 .yres = 1024,
111 .pixclock = 9375,
112 .left_margin = 38,
113 .right_margin = 128,
114 .upper_margin = 2,
115 .lower_margin = 7,
116 .hsync_len = 216,
117 .vsync_len = 37,
118 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
119 .vmode = FB_VMODE_NONINTERLACED
120 },
121 {
122 .name = "1280x1024-70",
123 .refresh = 70,
124 .xres = 1280,
125 .yres = 1024,
126 .pixclock = 9380,
127 .left_margin = 6,
128 .right_margin = 6,
129 .upper_margin = 4,
130 .lower_margin = 4,
131 .hsync_len = 60,
132 .vsync_len = 94,
133 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
134 .vmode = FB_VMODE_NONINTERLACED
135 },
136 {
137 .name = "1280x1024-75",
138 .refresh = 75,
139 .xres = 1280,
140 .yres = 1024,
141 .pixclock = 9380,
142 .left_margin = 6,
143 .right_margin = 6,
144 .upper_margin = 4,
145 .lower_margin = 4,
146 .hsync_len = 60,
147 .vsync_len = 15,
148 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
149 .vmode = FB_VMODE_NONINTERLACED
150 },
151 {
152 .name = "320x240", /* for AOI only */
153 .refresh = 60,
154 .xres = 320,
155 .yres = 240,
156 .pixclock = 15385,
157 .left_margin = 0,
158 .right_margin = 0,
159 .upper_margin = 0,
160 .lower_margin = 0,
161 .hsync_len = 0,
162 .vsync_len = 0,
163 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
164 .vmode = FB_VMODE_NONINTERLACED
165 },
166 {
167 .name = "1280x480-60",
168 .refresh = 60,
169 .xres = 1280,
170 .yres = 480,
171 .pixclock = 18939,
172 .left_margin = 353,
173 .right_margin = 47,
174 .upper_margin = 39,
175 .lower_margin = 4,
176 .hsync_len = 8,
177 .vsync_len = 2,
178 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
179 .vmode = FB_VMODE_NONINTERLACED
180 },
181};
182
183static char *fb_mode = "1024x768-32@60";
184static unsigned long default_bpp = 32;
185static int monitor_port;
186
187#if defined(CONFIG_NOT_COHERENT_CACHE)
188static u8 *coherence_data;
189static size_t coherence_data_size;
190static unsigned int d_cache_line_size;
191#endif
192
193static DEFINE_SPINLOCK(diu_lock);
194
195struct fsl_diu_data {
196 struct fb_info *fsl_diu_info[FSL_AOI_NUM - 1];
197 /*FSL_AOI_NUM has one dummy AOI */
198 struct device_attribute dev_attr;
199 struct diu_ad *dummy_ad;
200 void *dummy_aoi_virt;
201 unsigned int irq;
202 int fb_enabled;
203 int monitor_port;
204};
205
206struct mfb_info {
207 int index;
208 int type;
209 char *id;
210 int registered;
211 int blank;
212 unsigned long pseudo_palette[16];
213 struct diu_ad *ad;
214 int cursor_reset;
215 unsigned char g_alpha;
216 unsigned int count;
217 int x_aoi_d; /* aoi display x offset to physical screen */
218 int y_aoi_d; /* aoi display y offset to physical screen */
219 struct fsl_diu_data *parent;
220};
221
222
223static struct mfb_info mfb_template[] = {
224 { /* AOI 0 for plane 0 */
225 .index = 0,
226 .type = MFB_TYPE_OUTPUT,
227 .id = "Panel0",
228 .registered = 0,
229 .count = 0,
230 .x_aoi_d = 0,
231 .y_aoi_d = 0,
232 },
233 { /* AOI 0 for plane 1 */
234 .index = 1,
235 .type = MFB_TYPE_OUTPUT,
236 .id = "Panel1 AOI0",
237 .registered = 0,
238 .g_alpha = 0xff,
239 .count = 0,
240 .x_aoi_d = 0,
241 .y_aoi_d = 0,
242 },
243 { /* AOI 1 for plane 1 */
244 .index = 2,
245 .type = MFB_TYPE_OUTPUT,
246 .id = "Panel1 AOI1",
247 .registered = 0,
248 .g_alpha = 0xff,
249 .count = 0,
250 .x_aoi_d = 0,
251 .y_aoi_d = 480,
252 },
253 { /* AOI 0 for plane 2 */
254 .index = 3,
255 .type = MFB_TYPE_OUTPUT,
256 .id = "Panel2 AOI0",
257 .registered = 0,
258 .g_alpha = 0xff,
259 .count = 0,
260 .x_aoi_d = 640,
261 .y_aoi_d = 0,
262 },
263 { /* AOI 1 for plane 2 */
264 .index = 4,
265 .type = MFB_TYPE_OUTPUT,
266 .id = "Panel2 AOI1",
267 .registered = 0,
268 .g_alpha = 0xff,
269 .count = 0,
270 .x_aoi_d = 640,
271 .y_aoi_d = 480,
272 },
273};
274
275static struct diu_hw dr = {
276 .mode = MFB_MODE1,
277 .reg_lock = __SPIN_LOCK_UNLOCKED(diu_hw.reg_lock),
278};
279
280static struct diu_pool pool;
281
6b51d51a
TT		 282/**
283 * fsl_diu_alloc - allocate memory for the DIU
284 * @size: number of bytes to allocate
285 * @param: returned physical address of memory
286 *
287 * This function allocates a physically-contiguous block of memory.
9b53a9e2 288 */
6b51d51a 289static void *fsl_diu_alloc(size_t size, phys_addr_t *phys)
9b53a9e2
YS		 290{
291 void *virt;
292
6b51d51a 293 pr_debug("size=%zu\n", size);
9b53a9e2 294
6b51d51a 295 virt = alloc_pages_exact(size, GFP_DMA | __GFP_ZERO);
9b53a9e2
YS		 296 if (virt) {
297 *phys = virt_to_phys(virt);
6b51d51a
TT		 298 pr_debug("virt=%p phys=%llx\n", virt,
299 (unsigned long long)*phys);
9b53a9e2
YS		 300 }
301
9b53a9e2
YS		 302 return virt;
303}
304
6b51d51a
TT		 305/**
306 * fsl_diu_free - release DIU memory
307 * @virt: pointer returned by fsl_diu_alloc()
308 * @size: number of bytes allocated by fsl_diu_alloc()
309 *
310 * This function releases memory allocated by fsl_diu_alloc().
311 */
312static void fsl_diu_free(void *virt, size_t size)
9b53a9e2 313{
6b51d51a 314 pr_debug("virt=%p size=%zu\n", virt, size);
9b53a9e2 315
6b51d51a
TT		 316 if (virt && size)
317 free_pages_exact(virt, size);
9b53a9e2
YS		 318}
319
0d9dab39
AG		 320/*
321 * Workaround for failed writing desc register of planes.
322 * Needed with MPC5121 DIU rev 2.0 silicon.
323 */
324void wr_reg_wa(u32 *reg, u32 val)
325{
326 do {
327 out_be32(reg, val);
328 } while (in_be32(reg) != val);
329}
330
9b53a9e2
YS		 331static int fsl_diu_enable_panel(struct fb_info *info)
332{
333 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
334 struct diu *hw = dr.diu_reg;
335 struct diu_ad *ad = mfbi->ad;
336 struct fsl_diu_data *machine_data = mfbi->parent;
337 int res = 0;
338
339 pr_debug("enable_panel index %d\n", mfbi->index);
340 if (mfbi->type != MFB_TYPE_OFF) {
341 switch (mfbi->index) {
342 case 0: /* plane 0 */
343 if (hw->desc[0] != ad->paddr)
0d9dab39 344 wr_reg_wa(&hw->desc[0], ad->paddr);
9b53a9e2
YS		 345 break;
346 case 1: /* plane 1 AOI 0 */
347 cmfbi = machine_data->fsl_diu_info[2]->par;
348 if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
349 if (cmfbi->count > 0) /* AOI1 open */
350 ad->next_ad =
351 cpu_to_le32(cmfbi->ad->paddr);
352 else
353 ad->next_ad = 0;
0d9dab39 354 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2
YS		 355 }
356 break;
357 case 3: /* plane 2 AOI 0 */
358 cmfbi = machine_data->fsl_diu_info[4]->par;
359 if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
360 if (cmfbi->count > 0) /* AOI1 open */
361 ad->next_ad =
362 cpu_to_le32(cmfbi->ad->paddr);
363 else
364 ad->next_ad = 0;
0d9dab39 365 wr_reg_wa(&hw->desc[2], ad->paddr);
9b53a9e2
YS		 366 }
367 break;
368 case 2: /* plane 1 AOI 1 */
369 pmfbi = machine_data->fsl_diu_info[1]->par;
370 ad->next_ad = 0;
371 if (hw->desc[1] == machine_data->dummy_ad->paddr)
0d9dab39 372 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2
YS		 373 else /* AOI0 open */
374 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
375 break;
376 case 4: /* plane 2 AOI 1 */
377 pmfbi = machine_data->fsl_diu_info[3]->par;
378 ad->next_ad = 0;
379 if (hw->desc[2] == machine_data->dummy_ad->paddr)
0d9dab39 380 wr_reg_wa(&hw->desc[2], ad->paddr);
9b53a9e2
YS		 381 else /* AOI0 was open */
382 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
383 break;
384 default:
385 res = -EINVAL;
386 break;
387 }
388 } else
389 res = -EINVAL;
390 return res;
391}
392
393static int fsl_diu_disable_panel(struct fb_info *info)
394{
395 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
396 struct diu *hw = dr.diu_reg;
397 struct diu_ad *ad = mfbi->ad;
398 struct fsl_diu_data *machine_data = mfbi->parent;
399 int res = 0;
400
401 switch (mfbi->index) {
402 case 0: /* plane 0 */
403 if (hw->desc[0] != machine_data->dummy_ad->paddr)
0d9dab39 404 wr_reg_wa(&hw->desc[0], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 405 break;
406 case 1: /* plane 1 AOI 0 */
407 cmfbi = machine_data->fsl_diu_info[2]->par;
408 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 409 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
9b53a9e2
YS		 410 /* move AOI1 to the first */
411 else /* AOI1 was closed */
0d9dab39 412 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 413 /* close AOI 0 */
414 break;
415 case 3: /* plane 2 AOI 0 */
416 cmfbi = machine_data->fsl_diu_info[4]->par;
417 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 418 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
9b53a9e2
YS		 419 /* move AOI1 to the first */
420 else /* AOI1 was closed */
0d9dab39 421 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 422 /* close AOI 0 */
423 break;
424 case 2: /* plane 1 AOI 1 */
425 pmfbi = machine_data->fsl_diu_info[1]->par;
426 if (hw->desc[1] != ad->paddr) {
427 /* AOI1 is not the first in the chain */
428 if (pmfbi->count > 0)
429 /* AOI0 is open, must be the first */
430 pmfbi->ad->next_ad = 0;
431 } else /* AOI1 is the first in the chain */
0d9dab39 432 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 433 /* close AOI 1 */
434 break;
435 case 4: /* plane 2 AOI 1 */
436 pmfbi = machine_data->fsl_diu_info[3]->par;
437 if (hw->desc[2] != ad->paddr) {
438 /* AOI1 is not the first in the chain */
439 if (pmfbi->count > 0)
440 /* AOI0 is open, must be the first */
441 pmfbi->ad->next_ad = 0;
442 } else /* AOI1 is the first in the chain */
0d9dab39 443 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 444 /* close AOI 1 */
445 break;
446 default:
447 res = -EINVAL;
448 break;
449 }
450
451 return res;
452}
453
454static void enable_lcdc(struct fb_info *info)
455{
456 struct diu *hw = dr.diu_reg;
457 struct mfb_info *mfbi = info->par;
458 struct fsl_diu_data *machine_data = mfbi->parent;
459
460 if (!machine_data->fb_enabled) {
461 out_be32(&hw->diu_mode, dr.mode);
462 machine_data->fb_enabled++;
463 }
464}
465
466static void disable_lcdc(struct fb_info *info)
467{
468 struct diu *hw = dr.diu_reg;
469 struct mfb_info *mfbi = info->par;
470 struct fsl_diu_data *machine_data = mfbi->parent;
471
472 if (machine_data->fb_enabled) {
473 out_be32(&hw->diu_mode, 0);
474 machine_data->fb_enabled = 0;
475 }
476}
477
478static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
479 struct fb_info *info)
480{
481 struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
482 struct fsl_diu_data *machine_data = mfbi->parent;
483 int available_height, upper_aoi_bottom, index = mfbi->index;
484 int lower_aoi_is_open, upper_aoi_is_open;
485 __u32 base_plane_width, base_plane_height, upper_aoi_height;
486
487 base_plane_width = machine_data->fsl_diu_info[0]->var.xres;
488 base_plane_height = machine_data->fsl_diu_info[0]->var.yres;
489
fdfaa483
YS		 490 if (mfbi->x_aoi_d < 0)
491 mfbi->x_aoi_d = 0;
492 if (mfbi->y_aoi_d < 0)
493 mfbi->y_aoi_d = 0;
9b53a9e2
YS		 494 switch (index) {
495 case 0:
496 if (mfbi->x_aoi_d != 0)
497 mfbi->x_aoi_d = 0;
498 if (mfbi->y_aoi_d != 0)
499 mfbi->y_aoi_d = 0;
500 break;
501 case 1: /* AOI 0 */
502 case 3:
503 lower_aoi_mfbi = machine_data->fsl_diu_info[index+1]->par;
504 lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
505 if (var->xres > base_plane_width)
506 var->xres = base_plane_width;
507 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
508 mfbi->x_aoi_d = base_plane_width - var->xres;
509
510 if (lower_aoi_is_open)
511 available_height = lower_aoi_mfbi->y_aoi_d;
512 else
513 available_height = base_plane_height;
514 if (var->yres > available_height)
515 var->yres = available_height;
516 if ((mfbi->y_aoi_d + var->yres) > available_height)
517 mfbi->y_aoi_d = available_height - var->yres;
518 break;
519 case 2: /* AOI 1 */
520 case 4:
521 upper_aoi_mfbi = machine_data->fsl_diu_info[index-1]->par;
522 upper_aoi_height =
523 machine_data->fsl_diu_info[index-1]->var.yres;
524 upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
525 upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
526 if (var->xres > base_plane_width)
527 var->xres = base_plane_width;
528 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
529 mfbi->x_aoi_d = base_plane_width - var->xres;
530 if (mfbi->y_aoi_d < 0)
531 mfbi->y_aoi_d = 0;
532 if (upper_aoi_is_open) {
533 if (mfbi->y_aoi_d < upper_aoi_bottom)
534 mfbi->y_aoi_d = upper_aoi_bottom;
535 available_height = base_plane_height
536 - upper_aoi_bottom;
537 } else
538 available_height = base_plane_height;
539 if (var->yres > available_height)
540 var->yres = available_height;
541 if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
542 mfbi->y_aoi_d = base_plane_height - var->yres;
543 break;
544 }
545}
546/*
547 * Checks to see if the hardware supports the state requested by var passed
548 * in. This function does not alter the hardware state! If the var passed in
549 * is slightly off by what the hardware can support then we alter the var
550 * PASSED in to what we can do. If the hardware doesn't support mode change
551 * a -EINVAL will be returned by the upper layers.
552 */
553static int fsl_diu_check_var(struct fb_var_screeninfo *var,
554 struct fb_info *info)
555{
556 unsigned long htotal, vtotal;
557
558 pr_debug("check_var xres: %d\n", var->xres);
559 pr_debug("check_var yres: %d\n", var->yres);
560
561 if (var->xres_virtual < var->xres)
562 var->xres_virtual = var->xres;
563 if (var->yres_virtual < var->yres)
564 var->yres_virtual = var->yres;
565
566 if (var->xoffset < 0)
567 var->xoffset = 0;
568
569 if (var->yoffset < 0)
570 var->yoffset = 0;
571
572 if (var->xoffset + info->var.xres > info->var.xres_virtual)
573 var->xoffset = info->var.xres_virtual - info->var.xres;
574
575 if (var->yoffset + info->var.yres > info->var.yres_virtual)
576 var->yoffset = info->var.yres_virtual - info->var.yres;
577
578 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
579 (var->bits_per_pixel != 16))
580 var->bits_per_pixel = default_bpp;
581
582 switch (var->bits_per_pixel) {
583 case 16:
584 var->red.length = 5;
585 var->red.offset = 11;
586 var->red.msb_right = 0;
587
588 var->green.length = 6;
589 var->green.offset = 5;
590 var->green.msb_right = 0;
591
592 var->blue.length = 5;
593 var->blue.offset = 0;
594 var->blue.msb_right = 0;
595
596 var->transp.length = 0;
597 var->transp.offset = 0;
598 var->transp.msb_right = 0;
599 break;
600 case 24:
601 var->red.length = 8;
602 var->red.offset = 0;
603 var->red.msb_right = 0;
604
605 var->green.length = 8;
606 var->green.offset = 8;
607 var->green.msb_right = 0;
608
609 var->blue.length = 8;
610 var->blue.offset = 16;
611 var->blue.msb_right = 0;
612
613 var->transp.length = 0;
614 var->transp.offset = 0;
615 var->transp.msb_right = 0;
616 break;
617 case 32:
618 var->red.length = 8;
619 var->red.offset = 16;
620 var->red.msb_right = 0;
621
622 var->green.length = 8;
623 var->green.offset = 8;
624 var->green.msb_right = 0;
625
626 var->blue.length = 8;
627 var->blue.offset = 0;
628 var->blue.msb_right = 0;
629
630 var->transp.length = 8;
631 var->transp.offset = 24;
632 var->transp.msb_right = 0;
633
634 break;
635 }
636 /* If the pixclock is below the minimum spec'd value then set to
637 * refresh rate for 60Hz since this is supported by most monitors.
638 * Refer to Documentation/fb/ for calculations.
639 */
640 if ((var->pixclock < MIN_PIX_CLK) || (var->pixclock > MAX_PIX_CLK)) {
641 htotal = var->xres + var->right_margin + var->hsync_len +
642 var->left_margin;
643 vtotal = var->yres + var->lower_margin + var->vsync_len +
644 var->upper_margin;
645 var->pixclock = (vtotal * htotal * 6UL) / 100UL;
646 var->pixclock = KHZ2PICOS(var->pixclock);
647 pr_debug("pixclock set for 60Hz refresh = %u ps\n",
648 var->pixclock);
649 }
650
651 var->height = -1;
652 var->width = -1;
653 var->grayscale = 0;
654
655 /* Copy nonstd field to/from sync for fbset usage */
656 var->sync |= var->nonstd;
657 var->nonstd |= var->sync;
658
659 adjust_aoi_size_position(var, info);
660 return 0;
661}
662
663static void set_fix(struct fb_info *info)
664{
665 struct fb_fix_screeninfo *fix = &info->fix;
666 struct fb_var_screeninfo *var = &info->var;
667 struct mfb_info *mfbi = info->par;
668
669 strncpy(fix->id, mfbi->id, strlen(mfbi->id));
670 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
671 fix->type = FB_TYPE_PACKED_PIXELS;
672 fix->accel = FB_ACCEL_NONE;
673 fix->visual = FB_VISUAL_TRUECOLOR;
674 fix->xpanstep = 1;
675 fix->ypanstep = 1;
676}
677
678static void update_lcdc(struct fb_info *info)
679{
680 struct fb_var_screeninfo *var = &info->var;
681 struct mfb_info *mfbi = info->par;
682 struct fsl_diu_data *machine_data = mfbi->parent;
683 struct diu *hw;
684 int i, j;
685 char __iomem *cursor_base, *gamma_table_base;
686
687 u32 temp;
688
689 hw = dr.diu_reg;
690
691 if (mfbi->type == MFB_TYPE_OFF) {
692 fsl_diu_disable_panel(info);
693 return;
694 }
695
696 diu_ops.set_monitor_port(machine_data->monitor_port);
697 gamma_table_base = pool.gamma.vaddr;
698 cursor_base = pool.cursor.vaddr;
699 /* Prep for DIU init - gamma table, cursor table */
700
701 for (i = 0; i <= 2; i++)
702 for (j = 0; j <= 255; j++)
703 *gamma_table_base++ = j;
704
705 diu_ops.set_gamma_table(machine_data->monitor_port, pool.gamma.vaddr);
706
707 pr_debug("update-lcdc: HW - %p\n Disabling DIU\n", hw);
708 disable_lcdc(info);
709
710 /* Program DIU registers */
711
712 out_be32(&hw->gamma, pool.gamma.paddr);
713 out_be32(&hw->cursor, pool.cursor.paddr);
714
715 out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */
716 out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
717 out_be32(&hw->disp_size, (var->yres << 16 | var->xres));
718 /* DISP SIZE */
719 pr_debug("DIU xres: %d\n", var->xres);
720 pr_debug("DIU yres: %d\n", var->yres);
721
722 out_be32(&hw->wb_size, 0); /* WB SIZE */
723 out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
724
725 /* Horizontal and vertical configuration register */
726 temp = var->left_margin << 22 | /* BP_H */
727 var->hsync_len << 11 | /* PW_H */
728 var->right_margin; /* FP_H */
729
730 out_be32(&hw->hsyn_para, temp);
731
732 temp = var->upper_margin << 22 | /* BP_V */
733 var->vsync_len << 11 | /* PW_V */
734 var->lower_margin; /* FP_V */
735
736 out_be32(&hw->vsyn_para, temp);
737
738 pr_debug("DIU right_margin - %d\n", var->right_margin);
739 pr_debug("DIU left_margin - %d\n", var->left_margin);
740 pr_debug("DIU hsync_len - %d\n", var->hsync_len);
741 pr_debug("DIU upper_margin - %d\n", var->upper_margin);
742 pr_debug("DIU lower_margin - %d\n", var->lower_margin);
743 pr_debug("DIU vsync_len - %d\n", var->vsync_len);
744 pr_debug("DIU HSYNC - 0x%08x\n", hw->hsyn_para);
745 pr_debug("DIU VSYNC - 0x%08x\n", hw->vsyn_para);
746
747 diu_ops.set_pixel_clock(var->pixclock);
748
749 out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
750 out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
751 out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
752 out_be32(&hw->plut, 0x01F5F666);
753
754 /* Enable the DIU */
755 enable_lcdc(info);
756}
757
758static int map_video_memory(struct fb_info *info)
759{
760 phys_addr_t phys;
537a1bf0 761 u32 smem_len = info->fix.line_length * info->var.yres_virtual;
9b53a9e2
YS		 762
763 pr_debug("info->var.xres_virtual = %d\n", info->var.xres_virtual);
764 pr_debug("info->var.yres_virtual = %d\n", info->var.yres_virtual);
765 pr_debug("info->fix.line_length = %d\n", info->fix.line_length);
537a1bf0 766 pr_debug("MAP_VIDEO_MEMORY: smem_len = %u\n", smem_len);
9b53a9e2 767
537a1bf0 768 info->screen_base = fsl_diu_alloc(smem_len, &phys);
05946bce 769 if (info->screen_base == NULL) {
9b53a9e2
YS		 770 printk(KERN_ERR "Unable to allocate fb memory\n");
771 return -ENOMEM;
772 }
537a1bf0 773 mutex_lock(&info->mm_lock);
9b53a9e2 774 info->fix.smem_start = (unsigned long) phys;
537a1bf0
KH		 775 info->fix.smem_len = smem_len;
776 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 777 info->screen_size = info->fix.smem_len;
778
779 pr_debug("Allocated fb @ paddr=0x%08lx, size=%d.\n",
537a1bf0 780 info->fix.smem_start, info->fix.smem_len);
9b53a9e2
YS		 781 pr_debug("screen base %p\n", info->screen_base);
782
783 return 0;
784}
785
786static void unmap_video_memory(struct fb_info *info)
787{
788 fsl_diu_free(info->screen_base, info->fix.smem_len);
537a1bf0 789 mutex_lock(&info->mm_lock);
05946bce 790 info->screen_base = NULL;
9b53a9e2
YS		 791 info->fix.smem_start = 0;
792 info->fix.smem_len = 0;
537a1bf0 793 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 794}
795
ae5591e3
YS		 796/*
797 * Using the fb_var_screeninfo in fb_info we set the aoi of this
798 * particular framebuffer. It is a light version of fsl_diu_set_par.
799 */
800static int fsl_diu_set_aoi(struct fb_info *info)
801{
802 struct fb_var_screeninfo *var = &info->var;
803 struct mfb_info *mfbi = info->par;
804 struct diu_ad *ad = mfbi->ad;
805
806 /* AOI should not be greater than display size */
807 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
808 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
809 return 0;
810}
811
9b53a9e2
YS		 812/*
813 * Using the fb_var_screeninfo in fb_info we set the resolution of this
814 * particular framebuffer. This function alters the fb_fix_screeninfo stored
815 * in fb_info. It does not alter var in fb_info since we are using that
816 * data. This means we depend on the data in var inside fb_info to be
817 * supported by the hardware. fsl_diu_check_var is always called before
818 * fsl_diu_set_par to ensure this.
819 */
820static int fsl_diu_set_par(struct fb_info *info)
821{
822 unsigned long len;
823 struct fb_var_screeninfo *var = &info->var;
824 struct mfb_info *mfbi = info->par;
825 struct fsl_diu_data *machine_data = mfbi->parent;
826 struct diu_ad *ad = mfbi->ad;
827 struct diu *hw;
828
829 hw = dr.diu_reg;
830
831 set_fix(info);
832 mfbi->cursor_reset = 1;
833
834 len = info->var.yres_virtual * info->fix.line_length;
835 /* Alloc & dealloc each time resolution/bpp change */
836 if (len != info->fix.smem_len) {
837 if (info->fix.smem_start)
838 unmap_video_memory(info);
839 pr_debug("SET PAR: smem_len = %d\n", info->fix.smem_len);
840
841 /* Memory allocation for framebuffer */
842 if (map_video_memory(info)) {
843 printk(KERN_ERR "Unable to allocate fb memory 1\n");
844 return -ENOMEM;
845 }
846 }
847
848 ad->pix_fmt =
849 diu_ops.get_pixel_format(var->bits_per_pixel,
850 machine_data->monitor_port);
851 ad->addr = cpu_to_le32(info->fix.smem_start);
ae5591e3
YS		 852 ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
853 var->xres_virtual) | mfbi->g_alpha;
854 /* AOI should not be greater than display size */
9b53a9e2 855 ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
ae5591e3 856 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
9b53a9e2
YS		 857 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
858
859 /* Disable chroma keying function */
860 ad->ckmax_r = 0;
861 ad->ckmax_g = 0;
862 ad->ckmax_b = 0;
863
864 ad->ckmin_r = 255;
865 ad->ckmin_g = 255;
866 ad->ckmin_b = 255;
867
868 if (mfbi->index == 0)
869 update_lcdc(info);
870 return 0;
871}
872
873static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
874{
875 return ((val<<width) + 0x7FFF - val)>>16;
876}
877
878/*
879 * Set a single color register. The values supplied have a 16 bit magnitude
880 * which needs to be scaled in this function for the hardware. Things to take
881 * into consideration are how many color registers, if any, are supported with
882 * the current color visual. With truecolor mode no color palettes are
883 * supported. Here a psuedo palette is created which we store the value in
884 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
885 * color palette.
886 */
887static int fsl_diu_setcolreg(unsigned regno, unsigned red, unsigned green,
888 unsigned blue, unsigned transp, struct fb_info *info)
889{
890 int ret = 1;
891
892 /*
893 * If greyscale is true, then we convert the RGB value
894 * to greyscale no matter what visual we are using.
895 */
896 if (info->var.grayscale)
897 red = green = blue = (19595 * red + 38470 * green +
898 7471 * blue) >> 16;
899 switch (info->fix.visual) {
900 case FB_VISUAL_TRUECOLOR:
901 /*
902 * 16-bit True Colour. We encode the RGB value
903 * according to the RGB bitfield information.
904 */
905 if (regno < 16) {
906 u32 *pal = info->pseudo_palette;
907 u32 v;
908
909 red = CNVT_TOHW(red, info->var.red.length);
910 green = CNVT_TOHW(green, info->var.green.length);
911 blue = CNVT_TOHW(blue, info->var.blue.length);
912 transp = CNVT_TOHW(transp, info->var.transp.length);
913
914 v = (red << info->var.red.offset) |
915 (green << info->var.green.offset) |
916 (blue << info->var.blue.offset) |
917 (transp << info->var.transp.offset);
918
919 pal[regno] = v;
920 ret = 0;
921 }
922 break;
923 case FB_VISUAL_STATIC_PSEUDOCOLOR:
924 case FB_VISUAL_PSEUDOCOLOR:
925 break;
926 }
927
928 return ret;
929}
930
931/*
932 * Pan (or wrap, depending on the `vmode' field) the display using the
933 * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
934 * don't fit, return -EINVAL.
935 */
936static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
937 struct fb_info *info)
938{
939 if ((info->var.xoffset == var->xoffset) &&
940 (info->var.yoffset == var->yoffset))
941 return 0; /* No change, do nothing */
942
943 if (var->xoffset < 0 || var->yoffset < 0
944 || var->xoffset + info->var.xres > info->var.xres_virtual
945 || var->yoffset + info->var.yres > info->var.yres_virtual)
946 return -EINVAL;
947
948 info->var.xoffset = var->xoffset;
949 info->var.yoffset = var->yoffset;
950
951 if (var->vmode & FB_VMODE_YWRAP)
952 info->var.vmode |= FB_VMODE_YWRAP;
953 else
954 info->var.vmode &= ~FB_VMODE_YWRAP;
955
ae5591e3
YS		 956 fsl_diu_set_aoi(info);
957
9b53a9e2
YS		 958 return 0;
959}
960
961/*
962 * Blank the screen if blank_mode != 0, else unblank. Return 0 if blanking
963 * succeeded, != 0 if un-/blanking failed.
964 * blank_mode == 2: suspend vsync
965 * blank_mode == 3: suspend hsync
966 * blank_mode == 4: powerdown
967 */
968static int fsl_diu_blank(int blank_mode, struct fb_info *info)
969{
970 struct mfb_info *mfbi = info->par;
971
972 mfbi->blank = blank_mode;
973
974 switch (blank_mode) {
975 case FB_BLANK_VSYNC_SUSPEND:
976 case FB_BLANK_HSYNC_SUSPEND:
977 /* FIXME: fixes to enable_panel and enable lcdc needed */
978 case FB_BLANK_NORMAL:
979 /* fsl_diu_disable_panel(info);*/
980 break;
981 case FB_BLANK_POWERDOWN:
982 /* disable_lcdc(info); */
983 break;
984 case FB_BLANK_UNBLANK:
985 /* fsl_diu_enable_panel(info);*/
986 break;
987 }
988
989 return 0;
990}
991
992static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
993 unsigned long arg)
994{
995 struct mfb_info *mfbi = info->par;
996 struct diu_ad *ad = mfbi->ad;
997 struct mfb_chroma_key ck;
998 unsigned char global_alpha;
999 struct aoi_display_offset aoi_d;
1000 __u32 pix_fmt;
1001 void __user *buf = (void __user *)arg;
1002
1003 if (!arg)
1004 return -EINVAL;
1005 switch (cmd) {
1006 case MFB_SET_PIXFMT:
1007 if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
1008 return -EFAULT;
1009 ad->pix_fmt = pix_fmt;
1010 pr_debug("Set pixel format to 0x%08x\n", ad->pix_fmt);
1011 break;
1012 case MFB_GET_PIXFMT:
1013 pix_fmt = ad->pix_fmt;
1014 if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
1015 return -EFAULT;
1016 pr_debug("get pixel format 0x%08x\n", ad->pix_fmt);
1017 break;
1018 case MFB_SET_AOID:
1019 if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
1020 return -EFAULT;
1021 mfbi->x_aoi_d = aoi_d.x_aoi_d;
1022 mfbi->y_aoi_d = aoi_d.y_aoi_d;
1023 pr_debug("set AOI display offset of index %d to (%d,%d)\n",
1024 mfbi->index, aoi_d.x_aoi_d, aoi_d.y_aoi_d);
1025 fsl_diu_check_var(&info->var, info);
ae5591e3 1026 fsl_diu_set_aoi(info);
9b53a9e2
YS		 1027 break;
1028 case MFB_GET_AOID:
1029 aoi_d.x_aoi_d = mfbi->x_aoi_d;
1030 aoi_d.y_aoi_d = mfbi->y_aoi_d;
1031 if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
1032 return -EFAULT;
1033 pr_debug("get AOI display offset of index %d (%d,%d)\n",
1034 mfbi->index, aoi_d.x_aoi_d, aoi_d.y_aoi_d);
1035 break;
1036 case MFB_GET_ALPHA:
1037 global_alpha = mfbi->g_alpha;
1038 if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
1039 return -EFAULT;
1040 pr_debug("get global alpha of index %d\n", mfbi->index);
1041 break;
1042 case MFB_SET_ALPHA:
1043 /* set panel information */
1044 if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
1045 return -EFAULT;
1046 ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
1047 (global_alpha & 0xff);
1048 mfbi->g_alpha = global_alpha;
1049 pr_debug("set global alpha for index %d\n", mfbi->index);
1050 break;
1051 case MFB_SET_CHROMA_KEY:
1052 /* set panel winformation */
1053 if (copy_from_user(&ck, buf, sizeof(ck)))
1054 return -EFAULT;
1055
1056 if (ck.enable &&
1057 (ck.red_max < ck.red_min ||
1058 ck.green_max < ck.green_min ||
1059 ck.blue_max < ck.blue_min))
1060 return -EINVAL;
1061
1062 if (!ck.enable) {
1063 ad->ckmax_r = 0;
1064 ad->ckmax_g = 0;
1065 ad->ckmax_b = 0;
1066 ad->ckmin_r = 255;
1067 ad->ckmin_g = 255;
1068 ad->ckmin_b = 255;
1069 } else {
1070 ad->ckmax_r = ck.red_max;
1071 ad->ckmax_g = ck.green_max;
1072 ad->ckmax_b = ck.blue_max;
1073 ad->ckmin_r = ck.red_min;
1074 ad->ckmin_g = ck.green_min;
1075 ad->ckmin_b = ck.blue_min;
1076 }
1077 pr_debug("set chroma key\n");
1078 break;
1079 case FBIOGET_GWINFO:
1080 if (mfbi->type == MFB_TYPE_OFF)
1081 return -ENODEV;
1082 /* get graphic window information */
1083 if (copy_to_user(buf, ad, sizeof(*ad)))
1084 return -EFAULT;
1085 break;
1086 case FBIOGET_HWCINFO:
1087 pr_debug("FBIOGET_HWCINFO:0x%08x\n", FBIOGET_HWCINFO);
1088 break;
1089 case FBIOPUT_MODEINFO:
1090 pr_debug("FBIOPUT_MODEINFO:0x%08x\n", FBIOPUT_MODEINFO);
1091 break;
1092 case FBIOGET_DISPINFO:
1093 pr_debug("FBIOGET_DISPINFO:0x%08x\n", FBIOGET_DISPINFO);
1094 break;
1095
1096 default:
1097 printk(KERN_ERR "Unknown ioctl command (0x%08X)\n", cmd);
1098 return -ENOIOCTLCMD;
1099 }
1100
1101 return 0;
1102}
1103
1104/* turn on fb if count == 1
1105 */
1106static int fsl_diu_open(struct fb_info *info, int user)
1107{
1108 struct mfb_info *mfbi = info->par;
1109 int res = 0;
1110
4b5006ec
AG		 1111 /* free boot splash memory on first /dev/fb0 open */
1112 if (!mfbi->index && diu_ops.release_bootmem)
1113 diu_ops.release_bootmem();
1114
9b53a9e2
YS		 1115 spin_lock(&diu_lock);
1116 mfbi->count++;
1117 if (mfbi->count == 1) {
1118 pr_debug("open plane index %d\n", mfbi->index);
1119 fsl_diu_check_var(&info->var, info);
1120 res = fsl_diu_set_par(info);
1121 if (res < 0)
1122 mfbi->count--;
1123 else {
1124 res = fsl_diu_enable_panel(info);
1125 if (res < 0)
1126 mfbi->count--;
1127 }
1128 }
1129
1130 spin_unlock(&diu_lock);
1131 return res;
1132}
1133
1134/* turn off fb if count == 0
1135 */
1136static int fsl_diu_release(struct fb_info *info, int user)
1137{
1138 struct mfb_info *mfbi = info->par;
1139 int res = 0;
1140
1141 spin_lock(&diu_lock);
1142 mfbi->count--;
1143 if (mfbi->count == 0) {
1144 pr_debug("release plane index %d\n", mfbi->index);
1145 res = fsl_diu_disable_panel(info);
1146 if (res < 0)
1147 mfbi->count++;
1148 }
1149 spin_unlock(&diu_lock);
1150 return res;
1151}
1152
1153static struct fb_ops fsl_diu_ops = {
1154 .owner = THIS_MODULE,
1155 .fb_check_var = fsl_diu_check_var,
1156 .fb_set_par = fsl_diu_set_par,
1157 .fb_setcolreg = fsl_diu_setcolreg,
1158 .fb_blank = fsl_diu_blank,
1159 .fb_pan_display = fsl_diu_pan_display,
1160 .fb_fillrect = cfb_fillrect,
1161 .fb_copyarea = cfb_copyarea,
1162 .fb_imageblit = cfb_imageblit,
1163 .fb_ioctl = fsl_diu_ioctl,
1164 .fb_open = fsl_diu_open,
1165 .fb_release = fsl_diu_release,
1166};
1167
1168static int init_fbinfo(struct fb_info *info)
1169{
1170 struct mfb_info *mfbi = info->par;
1171
1172 info->device = NULL;
1173 info->var.activate = FB_ACTIVATE_NOW;
1174 info->fbops = &fsl_diu_ops;
1175 info->flags = FBINFO_FLAG_DEFAULT;
1176 info->pseudo_palette = &mfbi->pseudo_palette;
1177
1178 /* Allocate colormap */
1179 fb_alloc_cmap(&info->cmap, 16, 0);
1180 return 0;
1181}
1182
05946bce 1183static int __devinit install_fb(struct fb_info *info)
9b53a9e2
YS		 1184{
1185 int rc;
1186 struct mfb_info *mfbi = info->par;
1187 const char *aoi_mode, *init_aoi_mode = "320x240";
1188
1189 if (init_fbinfo(info))
1190 return -EINVAL;
1191
1192 if (mfbi->index == 0) /* plane 0 */
1193 aoi_mode = fb_mode;
1194 else
1195 aoi_mode = init_aoi_mode;
1196 pr_debug("mode used = %s\n", aoi_mode);
1197 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
1198 ARRAY_SIZE(fsl_diu_mode_db), &fsl_diu_default_mode, default_bpp);
1199
1200 switch (rc) {
1201 case 1:
1202 pr_debug("using mode specified in @mode\n");
1203 break;
1204 case 2:
1205 pr_debug("using mode specified in @mode "
1206 "with ignored refresh rate\n");
1207 break;
1208 case 3:
1209 pr_debug("using mode default mode\n");
1210 break;
1211 case 4:
1212 pr_debug("using mode from list\n");
1213 break;
1214 default:
1215 pr_debug("rc = %d\n", rc);
1216 pr_debug("failed to find mode\n");
1217 return -EINVAL;
1218 break;
1219 }
1220
1221 pr_debug("xres_virtual %d\n", info->var.xres_virtual);
1222 pr_debug("bits_per_pixel %d\n", info->var.bits_per_pixel);
1223
1224 pr_debug("info->var.yres_virtual = %d\n", info->var.yres_virtual);
1225 pr_debug("info->fix.line_length = %d\n", info->fix.line_length);
1226
1227 if (mfbi->type == MFB_TYPE_OFF)
1228 mfbi->blank = FB_BLANK_NORMAL;
1229 else
1230 mfbi->blank = FB_BLANK_UNBLANK;
1231
1232 if (fsl_diu_check_var(&info->var, info)) {
1233 printk(KERN_ERR "fb_check_var failed");
1234 fb_dealloc_cmap(&info->cmap);
1235 return -EINVAL;
1236 }
1237
9b53a9e2
YS		 1238 if (register_framebuffer(info) < 0) {
1239 printk(KERN_ERR "register_framebuffer failed");
1240 unmap_video_memory(info);
1241 fb_dealloc_cmap(&info->cmap);
1242 return -EINVAL;
1243 }
1244
1245 mfbi->registered = 1;
1246 printk(KERN_INFO "fb%d: %s fb device registered successfully.\n",
1247 info->node, info->fix.id);
1248
1249 return 0;
1250}
1251
05946bce 1252static void uninstall_fb(struct fb_info *info)
9b53a9e2
YS		 1253{
1254 struct mfb_info *mfbi = info->par;
1255
1256 if (!mfbi->registered)
1257 return;
1258
1259 unregister_framebuffer(info);
1260 unmap_video_memory(info);
1261 if (&info->cmap)
1262 fb_dealloc_cmap(&info->cmap);
1263
1264 mfbi->registered = 0;
1265}
1266
1267static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
1268{
1269 struct diu *hw = dr.diu_reg;
1270 unsigned int status = in_be32(&hw->int_status);
1271
1272 if (status) {
1273 /* This is the workaround for underrun */
1274 if (status & INT_UNDRUN) {
1275 out_be32(&hw->diu_mode, 0);
1276 pr_debug("Err: DIU occurs underrun!\n");
1277 udelay(1);
1278 out_be32(&hw->diu_mode, 1);
1279 }
1280#if defined(CONFIG_NOT_COHERENT_CACHE)
1281 else if (status & INT_VSYNC) {
1282 unsigned int i;
1283 for (i = 0; i < coherence_data_size;
1284 i += d_cache_line_size)
1285 __asm__ __volatile__ (
1286 "dcbz 0, %[input]"
1287 ::[input]"r"(&coherence_data[i]));
1288 }
1289#endif
1290 return IRQ_HANDLED;
1291 }
1292 return IRQ_NONE;
1293}
1294
1295static int request_irq_local(int irq)
1296{
1297 unsigned long status, ints;
1298 struct diu *hw;
1299 int ret;
1300
1301 hw = dr.diu_reg;
1302
1303 /* Read to clear the status */
1304 status = in_be32(&hw->int_status);
1305
05946bce 1306 ret = request_irq(irq, fsl_diu_isr, 0, "diu", NULL);
9b53a9e2
YS		 1307 if (ret)
1308 pr_info("Request diu IRQ failed.\n");
1309 else {
1310 ints = INT_PARERR | INT_LS_BF_VS;
1311#if !defined(CONFIG_NOT_COHERENT_CACHE)
1312 ints |= INT_VSYNC;
1313#endif
1314 if (dr.mode == MFB_MODE2 || dr.mode == MFB_MODE3)
1315 ints |= INT_VSYNC_WB;
1316
1317 /* Read to clear the status */
1318 status = in_be32(&hw->int_status);
1319 out_be32(&hw->int_mask, ints);
1320 }
1321 return ret;
1322}
1323
1324static void free_irq_local(int irq)
1325{
1326 struct diu *hw = dr.diu_reg;
1327
1328 /* Disable all LCDC interrupt */
1329 out_be32(&hw->int_mask, 0x1f);
1330
05946bce 1331 free_irq(irq, NULL);
9b53a9e2
YS		 1332}
1333
1334#ifdef CONFIG_PM
1335/*
1336 * Power management hooks. Note that we won't be called from IRQ context,
1337 * unlike the blank functions above, so we may sleep.
1338 */
f969c567 1339static int fsl_diu_suspend(struct of_device *ofdev, pm_message_t state)
9b53a9e2
YS		 1340{
1341 struct fsl_diu_data *machine_data;
1342
48948a3e 1343 machine_data = dev_get_drvdata(&ofdev->dev);
9b53a9e2
YS		 1344 disable_lcdc(machine_data->fsl_diu_info[0]);
1345
1346 return 0;
1347}
1348
f969c567 1349static int fsl_diu_resume(struct of_device *ofdev)
9b53a9e2
YS		 1350{
1351 struct fsl_diu_data *machine_data;
1352
48948a3e 1353 machine_data = dev_get_drvdata(&ofdev->dev);
9b53a9e2
YS		 1354 enable_lcdc(machine_data->fsl_diu_info[0]);
1355
1356 return 0;
1357}
1358
1359#else
1360#define fsl_diu_suspend NULL
1361#define fsl_diu_resume NULL
1362#endif /* CONFIG_PM */
1363
1364/* Align to 64-bit(8-byte), 32-byte, etc. */
f3791889
AV		 1365static int allocate_buf(struct device *dev, struct diu_addr *buf, u32 size,
1366 u32 bytes_align)
9b53a9e2
YS		 1367{
1368 u32 offset, ssize;
1369 u32 mask;
1370 dma_addr_t paddr = 0;
1371
1372 ssize = size + bytes_align;
f3791889 1373 buf->vaddr = dma_alloc_coherent(dev, ssize, &paddr, GFP_DMA |
05946bce 1374 __GFP_ZERO);
9b53a9e2
YS		 1375 if (!buf->vaddr)
1376 return -ENOMEM;
1377
1378 buf->paddr = (__u32) paddr;
1379
1380 mask = bytes_align - 1;
1381 offset = (u32)buf->paddr & mask;
1382 if (offset) {
1383 buf->offset = bytes_align - offset;
1384 buf->paddr = (u32)buf->paddr + offset;
1385 } else
1386 buf->offset = 0;
1387 return 0;
1388}
1389
f3791889
AV		 1390static void free_buf(struct device *dev, struct diu_addr *buf, u32 size,
1391 u32 bytes_align)
9b53a9e2 1392{
f3791889 1393 dma_free_coherent(dev, size + bytes_align,
9b53a9e2
YS		 1394 buf->vaddr, (buf->paddr - buf->offset));
1395 return;
1396}
1397
1398static ssize_t store_monitor(struct device *device,
1399 struct device_attribute *attr, const char *buf, size_t count)
1400{
1401 int old_monitor_port;
1402 unsigned long val;
1403 struct fsl_diu_data *machine_data =
1404 container_of(attr, struct fsl_diu_data, dev_attr);
1405
1406 if (strict_strtoul(buf, 10, &val))
1407 return 0;
1408
1409 old_monitor_port = machine_data->monitor_port;
1410 machine_data->monitor_port = diu_ops.set_sysfs_monitor_port(val);
1411
1412 if (old_monitor_port != machine_data->monitor_port) {
1413 /* All AOIs need adjust pixel format
1414 * fsl_diu_set_par only change the pixsel format here
1415 * unlikely to fail. */
1416 fsl_diu_set_par(machine_data->fsl_diu_info[0]);
1417 fsl_diu_set_par(machine_data->fsl_diu_info[1]);
1418 fsl_diu_set_par(machine_data->fsl_diu_info[2]);
1419 fsl_diu_set_par(machine_data->fsl_diu_info[3]);
1420 fsl_diu_set_par(machine_data->fsl_diu_info[4]);
1421 }
1422 return count;
1423}
1424
1425static ssize_t show_monitor(struct device *device,
1426 struct device_attribute *attr, char *buf)
1427{
1428 struct fsl_diu_data *machine_data =
1429 container_of(attr, struct fsl_diu_data, dev_attr);
1430 return diu_ops.show_monitor_port(machine_data->monitor_port, buf);
1431}
1432
05946bce 1433static int __devinit fsl_diu_probe(struct of_device *ofdev,
9b53a9e2
YS		 1434 const struct of_device_id *match)
1435{
61c7a080 1436 struct device_node *np = ofdev->dev.of_node;
9b53a9e2
YS		 1437 struct mfb_info *mfbi;
1438 phys_addr_t dummy_ad_addr;
1439 int ret, i, error = 0;
1440 struct resource res;
1441 struct fsl_diu_data *machine_data;
4b5006ec 1442 int diu_mode;
9b53a9e2
YS		 1443
1444 machine_data = kzalloc(sizeof(struct fsl_diu_data), GFP_KERNEL);
1445 if (!machine_data)
1446 return -ENOMEM;
1447
1448 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
1449 machine_data->fsl_diu_info[i] =
1450 framebuffer_alloc(sizeof(struct mfb_info), &ofdev->dev);
1451 if (!machine_data->fsl_diu_info[i]) {
1452 dev_err(&ofdev->dev, "cannot allocate memory\n");
1453 ret = -ENOMEM;
1454 goto error2;
1455 }
1456 mfbi = machine_data->fsl_diu_info[i]->par;
1457 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
1458 mfbi->parent = machine_data;
1459 }
1460
1461 ret = of_address_to_resource(np, 0, &res);
1462 if (ret) {
1463 dev_err(&ofdev->dev, "could not obtain DIU address\n");
1464 goto error;
1465 }
1466 if (!res.start) {
1467 dev_err(&ofdev->dev, "invalid DIU address\n");
1468 goto error;
1469 }
1470 dev_dbg(&ofdev->dev, "%s, res.start: 0x%08x\n", __func__, res.start);
1471
1472 dr.diu_reg = ioremap(res.start, sizeof(struct diu));
1473 if (!dr.diu_reg) {
1474 dev_err(&ofdev->dev, "Err: can't map DIU registers!\n");
1475 ret = -EFAULT;
1476 goto error2;
1477 }
1478
4b5006ec
AG		 1479 diu_mode = in_be32(&dr.diu_reg->diu_mode);
1480 if (diu_mode != MFB_MODE1)
1481 out_be32(&dr.diu_reg->diu_mode, 0); /* disable DIU */
9b53a9e2
YS		 1482
1483 /* Get the IRQ of the DIU */
1484 machine_data->irq = irq_of_parse_and_map(np, 0);
1485
1486 if (!machine_data->irq) {
1487 dev_err(&ofdev->dev, "could not get DIU IRQ\n");
1488 ret = -EINVAL;
1489 goto error;
1490 }
1491 machine_data->monitor_port = monitor_port;
1492
1493 /* Area descriptor memory pool aligns to 64-bit boundary */
f3791889
AV		 1494 if (allocate_buf(&ofdev->dev, &pool.ad,
1495 sizeof(struct diu_ad) * FSL_AOI_NUM, 8))
9b53a9e2
YS		 1496 return -ENOMEM;
1497
1498 /* Get memory for Gamma Table - 32-byte aligned memory */
f3791889 1499 if (allocate_buf(&ofdev->dev, &pool.gamma, 768, 32)) {
9b53a9e2
YS		 1500 ret = -ENOMEM;
1501 goto error;
1502 }
1503
1504 /* For performance, cursor bitmap buffer aligns to 32-byte boundary */
f3791889
AV		 1505 if (allocate_buf(&ofdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
1506 32)) {
9b53a9e2
YS		 1507 ret = -ENOMEM;
1508 goto error;
1509 }
1510
1511 i = ARRAY_SIZE(machine_data->fsl_diu_info);
1512 machine_data->dummy_ad = (struct diu_ad *)
1513 ((u32)pool.ad.vaddr + pool.ad.offset) + i;
1514 machine_data->dummy_ad->paddr = pool.ad.paddr +
1515 i * sizeof(struct diu_ad);
1516 machine_data->dummy_aoi_virt = fsl_diu_alloc(64, &dummy_ad_addr);
1517 if (!machine_data->dummy_aoi_virt) {
1518 ret = -ENOMEM;
1519 goto error;
1520 }
1521 machine_data->dummy_ad->addr = cpu_to_le32(dummy_ad_addr);
1522 machine_data->dummy_ad->pix_fmt = 0x88882317;
1523 machine_data->dummy_ad->src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
1524 machine_data->dummy_ad->aoi_size = cpu_to_le32((4 << 16) | 2);
1525 machine_data->dummy_ad->offset_xyi = 0;
1526 machine_data->dummy_ad->offset_xyd = 0;
1527 machine_data->dummy_ad->next_ad = 0;
1528
4b5006ec
AG		 1529 /*
1530 * Let DIU display splash screen if it was pre-initialized
1531 * by the bootloader, set dummy area descriptor otherwise.
1532 */
1533 if (diu_mode != MFB_MODE1)
1534 out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr);
1535
9b53a9e2
YS		 1536 out_be32(&dr.diu_reg->desc[1], machine_data->dummy_ad->paddr);
1537 out_be32(&dr.diu_reg->desc[2], machine_data->dummy_ad->paddr);
1538
1539 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
1540 machine_data->fsl_diu_info[i]->fix.smem_start = 0;
1541 mfbi = machine_data->fsl_diu_info[i]->par;
1542 mfbi->ad = (struct diu_ad *)((u32)pool.ad.vaddr
1543 + pool.ad.offset) + i;
1544 mfbi->ad->paddr = pool.ad.paddr + i * sizeof(struct diu_ad);
1545 ret = install_fb(machine_data->fsl_diu_info[i]);
1546 if (ret) {
1547 dev_err(&ofdev->dev,
1548 "Failed to register framebuffer %d\n",
1549 i);
1550 goto error;
1551 }
1552 }
1553
1554 if (request_irq_local(machine_data->irq)) {
1555 dev_err(machine_data->fsl_diu_info[0]->dev,
1556 "could not request irq for diu.");
1557 goto error;
1558 }
1559
12765517 1560 sysfs_attr_init(&machine_data->dev_attr.attr);
9b53a9e2
YS		 1561 machine_data->dev_attr.attr.name = "monitor";
1562 machine_data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
1563 machine_data->dev_attr.show = show_monitor;
1564 machine_data->dev_attr.store = store_monitor;
1565 error = device_create_file(machine_data->fsl_diu_info[0]->dev,
1566 &machine_data->dev_attr);
1567 if (error) {
1568 dev_err(machine_data->fsl_diu_info[0]->dev,
1569 "could not create sysfs %s file\n",
1570 machine_data->dev_attr.attr.name);
1571 }
1572
1573 dev_set_drvdata(&ofdev->dev, machine_data);
1574 return 0;
1575
1576error:
1577 for (i = ARRAY_SIZE(machine_data->fsl_diu_info);
1578 i > 0; i--)
1579 uninstall_fb(machine_data->fsl_diu_info[i - 1]);
1580 if (pool.ad.vaddr)
f3791889
AV		 1581 free_buf(&ofdev->dev, &pool.ad,
1582 sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
9b53a9e2 1583 if (pool.gamma.vaddr)
f3791889 1584 free_buf(&ofdev->dev, &pool.gamma, 768, 32);
9b53a9e2 1585 if (pool.cursor.vaddr)
f3791889
AV		 1586 free_buf(&ofdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
1587 32);
9b53a9e2
YS		 1588 if (machine_data->dummy_aoi_virt)
1589 fsl_diu_free(machine_data->dummy_aoi_virt, 64);
1590 iounmap(dr.diu_reg);
1591
1592error2:
1593 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1594 if (machine_data->fsl_diu_info[i])
1595 framebuffer_release(machine_data->fsl_diu_info[i]);
1596 kfree(machine_data);
1597
1598 return ret;
1599}
1600
1601
1602static int fsl_diu_remove(struct of_device *ofdev)
1603{
1604 struct fsl_diu_data *machine_data;
1605 int i;
1606
1607 machine_data = dev_get_drvdata(&ofdev->dev);
1608 disable_lcdc(machine_data->fsl_diu_info[0]);
1609 free_irq_local(machine_data->irq);
1610 for (i = ARRAY_SIZE(machine_data->fsl_diu_info); i > 0; i--)
1611 uninstall_fb(machine_data->fsl_diu_info[i - 1]);
1612 if (pool.ad.vaddr)
f3791889
AV		 1613 free_buf(&ofdev->dev, &pool.ad,
1614 sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
9b53a9e2 1615 if (pool.gamma.vaddr)
f3791889 1616 free_buf(&ofdev->dev, &pool.gamma, 768, 32);
9b53a9e2 1617 if (pool.cursor.vaddr)
f3791889
AV		 1618 free_buf(&ofdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
1619 32);
9b53a9e2
YS		 1620 if (machine_data->dummy_aoi_virt)
1621 fsl_diu_free(machine_data->dummy_aoi_virt, 64);
1622 iounmap(dr.diu_reg);
1623 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1624 if (machine_data->fsl_diu_info[i])
1625 framebuffer_release(machine_data->fsl_diu_info[i]);
1626 kfree(machine_data);
1627
1628 return 0;
1629}
1630
1631#ifndef MODULE
1632static int __init fsl_diu_setup(char *options)
1633{
1634 char *opt;
1635 unsigned long val;
1636
1637 if (!options || !*options)
1638 return 0;
1639
1640 while ((opt = strsep(&options, ",")) != NULL) {
1641 if (!*opt)
1642 continue;
1643 if (!strncmp(opt, "monitor=", 8)) {
1644 if (!strict_strtoul(opt + 8, 10, &val) && (val <= 2))
1645 monitor_port = val;
1646 } else if (!strncmp(opt, "bpp=", 4)) {
1647 if (!strict_strtoul(opt + 4, 10, &val))
1648 default_bpp = val;
1649 } else
1650 fb_mode = opt;
1651 }
1652
1653 return 0;
1654}
1655#endif
1656
1657static struct of_device_id fsl_diu_match[] = {
d24720a4
AG		 1658#ifdef CONFIG_PPC_MPC512x
1659 {
1660 .compatible = "fsl,mpc5121-diu",
1661 },
1662#endif
9b53a9e2
YS		 1663 {
1664 .compatible = "fsl,diu",
1665 },
1666 {}
1667};
1668MODULE_DEVICE_TABLE(of, fsl_diu_match);
1669
1670static struct of_platform_driver fsl_diu_driver = {
4018294b
GL		 1671 .driver = {
1672 .name = "fsl_diu",
1673 .owner = THIS_MODULE,
1674 .of_match_table = fsl_diu_match,
1675 },
9b53a9e2
YS		 1676 .probe = fsl_diu_probe,
1677 .remove = fsl_diu_remove,
1678 .suspend = fsl_diu_suspend,
1679 .resume = fsl_diu_resume,
1680};
1681
1682static int __init fsl_diu_init(void)
1683{
1684#ifdef CONFIG_NOT_COHERENT_CACHE
1685 struct device_node *np;
1686 const u32 *prop;
1687#endif
1688 int ret;
1689#ifndef MODULE
1690 char *option;
1691
1692 /*
1693 * For kernel boot options (in 'video=xxxfb:<options>' format)
1694 */
1695 if (fb_get_options("fslfb", &option))
1696 return -ENODEV;
1697 fsl_diu_setup(option);
1698#endif
1699 printk(KERN_INFO "Freescale DIU driver\n");
1700
1701#ifdef CONFIG_NOT_COHERENT_CACHE
1702 np = of_find_node_by_type(NULL, "cpu");
1703 if (!np) {
1704 printk(KERN_ERR "Err: can't find device node 'cpu'\n");
1705 return -ENODEV;
1706 }
1707
1708 prop = of_get_property(np, "d-cache-size", NULL);
5394ba0f
JL		 1709 if (prop == NULL) {
1710 of_node_put(np);
9b53a9e2 1711 return -ENODEV;
5394ba0f 1712 }
9b53a9e2
YS		 1713
1714 /* Freescale PLRU requires 13/8 times the cache size to do a proper
1715 displacement flush
1716 */
1717 coherence_data_size = *prop * 13;
1718 coherence_data_size /= 8;
1719
1720 prop = of_get_property(np, "d-cache-line-size", NULL);
5394ba0f
JL		 1721 if (prop == NULL) {
1722 of_node_put(np);
9b53a9e2 1723 return -ENODEV;
5394ba0f 1724 }
9b53a9e2
YS		 1725 d_cache_line_size = *prop;
1726
1727 of_node_put(np);
1728 coherence_data = vmalloc(coherence_data_size);
1729 if (!coherence_data)
1730 return -ENOMEM;
1731#endif
1732 ret = of_register_platform_driver(&fsl_diu_driver);
1733 if (ret) {
1734 printk(KERN_ERR
1735 "fsl-diu: failed to register platform driver\n");
1736#if defined(CONFIG_NOT_COHERENT_CACHE)
1737 vfree(coherence_data);
1738#endif
1739 iounmap(dr.diu_reg);
1740 }
1741 return ret;
1742}
1743
1744static void __exit fsl_diu_exit(void)
1745{
1746 of_unregister_platform_driver(&fsl_diu_driver);
1747#if defined(CONFIG_NOT_COHERENT_CACHE)
1748 vfree(coherence_data);
1749#endif
1750}
1751
1752module_init(fsl_diu_init);
1753module_exit(fsl_diu_exit);
1754
1755MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
1756MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
1757MODULE_LICENSE("GPL");
1758
1759module_param_named(mode, fb_mode, charp, 0);
1760MODULE_PARM_DESC(mode,
1761 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
1762module_param_named(bpp, default_bpp, ulong, 0);
1763MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified mode");
1764module_param_named(monitor, monitor_port, int, 0);
1765MODULE_PARM_DESC(monitor,
1766 "Specify the monitor port (0, 1 or 2) if supported by the platform");
1767
Linux kernel - Deliverables
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