[deliverable/linux.git] / drivers / video / intelfb / intelfbhw.h

#ifndef _INTELFBHW_H
#define _INTELFBHW_H

/* $DHD: intelfb/intelfbhw.h,v 1.5 2003/06/27 15:06:25 dawes Exp $ */


/*** HW-specific data ***/

/* Information about the 852GM/855GM variants */
#define INTEL_85X_CAPID		0x44
#define INTEL_85X_VARIANT_MASK		0x7
#define INTEL_85X_VARIANT_SHIFT		5
#define INTEL_VAR_855GME		0x0
#define INTEL_VAR_855GM			0x4
#define INTEL_VAR_852GME		0x2
#define INTEL_VAR_852GM			0x5

/* Information about DVO/LVDS Ports */
#define DVOA_PORT  0x1
#define DVOB_PORT  0x2
#define DVOC_PORT  0x4
#define LVDS_PORT  0x8

/*
 * The Bridge device's PCI config space has information about the
 * fb aperture size and the amount of pre-reserved memory.
 */
#define INTEL_GMCH_CTRL		0x52
#define INTEL_GMCH_ENABLED		0x4
#define INTEL_GMCH_MEM_MASK		0x1
#define INTEL_GMCH_MEM_64M		0x1
#define INTEL_GMCH_MEM_128M		0

#define INTEL_830_GMCH_GMS_MASK		(0x7 << 4)
#define INTEL_830_GMCH_GMS_DISABLED	(0x0 << 4)
#define INTEL_830_GMCH_GMS_LOCAL	(0x1 << 4)
#define INTEL_830_GMCH_GMS_STOLEN_512	(0x2 << 4)
#define INTEL_830_GMCH_GMS_STOLEN_1024	(0x3 << 4)
#define INTEL_830_GMCH_GMS_STOLEN_8192	(0x4 << 4)

#define INTEL_855_GMCH_GMS_MASK		(0x7 << 4)
#define INTEL_855_GMCH_GMS_DISABLED	(0x0 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_1M	(0x1 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_4M	(0x2 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_8M	(0x3 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_16M	(0x4 << 4)
#define INTEL_855_GMCH_GMS_STOLEN_32M	(0x5 << 4)

#define INTEL_915G_GMCH_GMS_STOLEN_48M	(0x6 << 4)
#define INTEL_915G_GMCH_GMS_STOLEN_64M	(0x7 << 4)

/* HW registers */

/* Fence registers */
#define FENCE			0x2000
#define FENCE_NUM			8

/* Primary ring buffer */
#define PRI_RING_TAIL		0x2030
#define RING_TAIL_MASK			0x001ffff8
#define RING_INUSE			0x1

#define PRI_RING_HEAD		0x2034
#define RING_HEAD_WRAP_MASK		0x7ff
#define RING_HEAD_WRAP_SHIFT		21
#define RING_HEAD_MASK			0x001ffffc

#define PRI_RING_START		0x2038
#define RING_START_MASK			0xfffff000

#define PRI_RING_LENGTH		0x203c
#define RING_LENGTH_MASK		0x001ff000
#define RING_REPORT_MASK		(0x3 << 1)
#define RING_NO_REPORT			(0x0 << 1)
#define RING_REPORT_64K			(0x1 << 1)
#define RING_REPORT_4K			(0x2 << 1)
#define RING_REPORT_128K		(0x3 << 1)
#define RING_ENABLE			0x1

/*
 * Tail can't wrap to any closer than RING_MIN_FREE bytes of the head,
 * and the last RING_MIN_FREE bytes need to be padded with MI_NOOP
 */
#define RING_MIN_FREE			64

#define IPEHR			0x2088

#define INSTDONE		0x2090
#define PRI_RING_EMPTY			1

#define HWSTAM			0x2098
#define IER			0x20A0
#define IIR			0x20A4
#define IMR			0x20A8
#define VSYNC_PIPE_A_INTERRUPT		(1 << 7)
#define PIPE_A_EVENT_INTERRUPT		(1 << 6)
#define VSYNC_PIPE_B_INTERRUPT		(1 << 5)
#define PIPE_B_EVENT_INTERRUPT		(1 << 4)
#define HOST_PORT_EVENT_INTERRUPT	(1 << 3)
#define CAPTURE_EVENT_INTERRUPT		(1 << 2)
#define USER_DEFINED_INTERRUPT		(1 << 1)
#define BREAKPOINT_INTERRUPT		1

#define INSTPM			0x20c0
#define SYNC_FLUSH_ENABLE		(1 << 5)

#define INSTPS			0x20c4

#define MEM_MODE		0x20cc

#define MASK_SHIFT			16

#define FW_BLC_0		0x20d8
#define FW_DISPA_WM_SHIFT		0
#define FW_DISPA_WM_MASK		0x3f
#define FW_DISPA_BL_SHIFT		8
#define FW_DISPA_BL_MASK		0xf
#define FW_DISPB_WM_SHIFT		16
#define FW_DISPB_WM_MASK		0x1f
#define FW_DISPB_BL_SHIFT		24
#define FW_DISPB_BL_MASK		0x7

#define FW_BLC_1		0x20dc
#define FW_DISPC_WM_SHIFT		0
#define FW_DISPC_WM_MASK		0x1f
#define FW_DISPC_BL_SHIFT		8
#define FW_DISPC_BL_MASK		0x7

#define GPIOA             0x5010
#define GPIOB             0x5014
#define GPIOC             0x5018 /* this may be external DDC on i830 */
#define GPIOD             0x501C /* this is DVO DDC */
#define GPIOE             0x5020 /* this is DVO i2C */
#define GPIOF             0x5024

/* PLL registers */
#define VGA0_DIVISOR		0x06000
#define VGA1_DIVISOR		0x06004
#define VGAPD			0x06010
#define VGAPD_0_P1_SHIFT		0
#define VGAPD_0_P1_FORCE_DIV2		(1 << 5)
#define VGAPD_0_P2_SHIFT		7
#define VGAPD_1_P1_SHIFT		8
#define VGAPD_1_P1_FORCE_DIV2		(1 << 13)
#define VGAPD_1_P2_SHIFT		15

#define DPLL_A			0x06014
#define DPLL_B			0x06018
#define DPLL_VCO_ENABLE			(1 << 31)
#define DPLL_2X_CLOCK_ENABLE		(1 << 30)
#define DPLL_SYNCLOCK_ENABLE		(1 << 29)
#define DPLL_VGA_MODE_DISABLE		(1 << 28)
#define DPLL_P2_MASK			1
#define DPLL_P2_SHIFT			23
#define DPLL_I9XX_P2_SHIFT              24
#define DPLL_P1_FORCE_DIV2		(1 << 21)
#define DPLL_P1_MASK			0x1f
#define DPLL_P1_SHIFT			16
#define DPLL_REFERENCE_SELECT_MASK	(0x3 << 13)
#define DPLL_REFERENCE_DEFAULT		(0x0 << 13)
#define DPLL_REFERENCE_TVCLK		(0x2 << 13)
#define DPLL_RATE_SELECT_MASK		(1 << 8)
#define DPLL_RATE_SELECT_FP0		(0 << 8)
#define DPLL_RATE_SELECT_FP1		(1 << 8)

#define FPA0			0x06040
#define FPA1			0x06044
#define FPB0			0x06048
#define FPB1			0x0604c
#define FP_DIVISOR_MASK			0x3f
#define FP_N_DIVISOR_SHIFT		16
#define FP_M1_DIVISOR_SHIFT		8
#define FP_M2_DIVISOR_SHIFT		0

/* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
/* Clock values are in units of kHz */
#define PLL_REFCLK		48000
#define MIN_CLOCK		25000
#define MAX_CLOCK		350000

/* Two pipes */
#define PIPE_A			0
#define PIPE_B			1
#define PIPE_MASK		1

/* palette registers */
#define PALETTE_A		0x0a000
#define PALETTE_B		0x0a800
#ifndef PALETTE_8_ENTRIES
#define PALETTE_8_ENTRIES		256
#endif
#define PALETTE_8_SIZE			(PALETTE_8_ENTRIES * 4)
#define PALETTE_10_ENTRIES		128
#define PALETTE_10_SIZE			(PALETTE_10_ENTRIES * 8)
#define PALETTE_8_MASK			0xff
#define PALETTE_8_RED_SHIFT		16
#define PALETTE_8_GREEN_SHIFT		8
#define PALETTE_8_BLUE_SHIFT		0

/* CRTC registers */
#define HTOTAL_A		0x60000
#define HBLANK_A		0x60004
#define HSYNC_A			0x60008
#define VTOTAL_A		0x6000c
#define VBLANK_A		0x60010
#define VSYNC_A			0x60014
#define SRC_SIZE_A		0x6001c
#define BCLRPAT_A		0x60020

#define HTOTAL_B		0x61000
#define HBLANK_B		0x61004
#define HSYNC_B			0x61008
#define VTOTAL_B		0x6100c
#define VBLANK_B		0x61010
#define VSYNC_B			0x61014
#define SRC_SIZE_B		0x6101c
#define BCLRPAT_B		0x61020

#define HTOTAL_MASK			0xfff
#define HTOTAL_SHIFT			16
#define HACTIVE_MASK			0x7ff
#define HACTIVE_SHIFT			0
#define HBLANKEND_MASK			0xfff
#define HBLANKEND_SHIFT			16
#define HBLANKSTART_MASK		0xfff
#define HBLANKSTART_SHIFT		0
#define HSYNCEND_MASK			0xfff
#define HSYNCEND_SHIFT			16
#define HSYNCSTART_MASK			0xfff
#define HSYNCSTART_SHIFT		0
#define VTOTAL_MASK			0xfff
#define VTOTAL_SHIFT			16
#define VACTIVE_MASK			0x7ff
#define VACTIVE_SHIFT			0
#define VBLANKEND_MASK			0xfff
#define VBLANKEND_SHIFT			16
#define VBLANKSTART_MASK		0xfff
#define VBLANKSTART_SHIFT		0
#define VSYNCEND_MASK			0xfff
#define VSYNCEND_SHIFT			16
#define VSYNCSTART_MASK			0xfff
#define VSYNCSTART_SHIFT		0
#define SRC_SIZE_HORIZ_MASK		0x7ff
#define SRC_SIZE_HORIZ_SHIFT		16
#define SRC_SIZE_VERT_MASK		0x7ff
#define SRC_SIZE_VERT_SHIFT		0

#define ADPA			0x61100
#define ADPA_DAC_ENABLE			(1 << 31)
#define ADPA_DAC_DISABLE		0
#define ADPA_PIPE_SELECT_SHIFT		30
#define ADPA_USE_VGA_HVPOLARITY		(1 << 15)
#define ADPA_SETS_HVPOLARITY		0
#define ADPA_DPMS_CONTROL_MASK		(0x3 << 10)
#define ADPA_DPMS_D0			(0x0 << 10)
#define ADPA_DPMS_D2			(0x1 << 10)
#define ADPA_DPMS_D1			(0x2 << 10)
#define ADPA_DPMS_D3			(0x3 << 10)
#define ADPA_VSYNC_ACTIVE_SHIFT		4
#define ADPA_HSYNC_ACTIVE_SHIFT		3
#define ADPA_SYNC_ACTIVE_MASK		1
#define ADPA_SYNC_ACTIVE_HIGH		1
#define ADPA_SYNC_ACTIVE_LOW		0

#define DVOA			0x61120
#define DVOB			0x61140
#define DVOC			0x61160
#define LVDS			0x61180
#define PORT_ENABLE		        (1 << 31)
#define PORT_PIPE_SELECT_SHIFT	        30
#define PORT_TV_FLAGS_MASK              0xFF
#define PORT_TV_FLAGS                   0xC4	/* ripped from my BIOS
						   to understand and correct */

#define DVOA_SRCDIM		0x61124
#define DVOB_SRCDIM		0x61144
#define DVOC_SRCDIM		0x61164

#define PIPEA_DSL		0x70000
#define PIPEB_DSL		0x71000
#define PIPEACONF		0x70008
#define PIPEBCONF		0x71008
#define PIPEASTAT		0x70024 /* bits 0-15 are "write 1 to clear" */
#define PIPEBSTAT		0x71024

#define PIPECONF_ENABLE			(1 << 31)
#define PIPECONF_DISABLE		0
#define PIPECONF_DOUBLE_WIDE		(1 << 30)
#define PIPECONF_SINGLE_WIDE		0
#define PIPECONF_LOCKED			(1 << 25)
#define PIPECONF_UNLOCKED		0
#define PIPECONF_GAMMA			(1 << 24)
#define PIPECONF_PALETTE		0
#define PIPECONF_PROGRESSIVE			(0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
#define PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
#define PIPECONF_INTERLACE_MASK			(7 << 21)

/* enable bits, write 1 to enable */
#define PIPESTAT_FIFO_UNDERRUN		(1 << 31)
#define PIPESTAT_CRC_ERROR_EN		(1 << 29)
#define PIPESTAT_CRC_DONE_EN		(1 << 28)
#define PIPESTAT_HOTPLUG_EN		(1 << 26)
#define PIPESTAT_VERTICAL_SYNC_EN	(1 << 25)
#define PIPESTAT_DISPLINE_COMP_EN	(1 << 24)
#define PIPESTAT_FLD_EVT_ODD_EN		(1 << 21)
#define PIPESTAT_FLD_EVT_EVEN_EN	(1 << 20)
#define PIPESTAT_TV_HOTPLUG_EN		(1 << 18)
#define PIPESTAT_VBLANK_EN		(1 << 17)
#define PIPESTAT_OVL_UPDATE_EN		(1 << 16)
/* status bits, write 1 to clear */
#define PIPESTAT_HOTPLUG_STATE		(1 << 15)
#define PIPESTAT_CRC_ERROR		(1 << 13)
#define PIPESTAT_CRC_DONE		(1 << 12)
#define PIPESTAT_HOTPLUG		(1 << 10)
#define PIPESTAT_VSYNC			(1 << 9)
#define PIPESTAT_DISPLINE_COMP		(1 << 8)
#define PIPESTAT_FLD_EVT_ODD		(1 << 5)
#define PIPESTAT_FLD_EVT_EVEN		(1 << 4)
#define PIPESTAT_TV_HOTPLUG		(1 << 2)
#define PIPESTAT_VBLANK			(1 << 1)
#define PIPESTAT_OVL_UPDATE		(1 << 0)

#define DISPARB			0x70030
#define DISPARB_AEND_MASK		0x1ff
#define DISPARB_AEND_SHIFT		0
#define DISPARB_BEND_MASK		0x3ff
#define DISPARB_BEND_SHIFT		9

/* Desktop HW cursor */
#define CURSOR_CONTROL		0x70080
#define CURSOR_ENABLE			(1 << 31)
#define CURSOR_GAMMA_ENABLE		(1 << 30)
#define CURSOR_STRIDE_MASK		(0x3 << 28)
#define CURSOR_STRIDE_256		(0x0 << 28)
#define CURSOR_STRIDE_512		(0x1 << 28)
#define CURSOR_STRIDE_1K		(0x2 << 28)
#define CURSOR_STRIDE_2K		(0x3 << 28)
#define CURSOR_FORMAT_MASK		(0x7 << 24)
#define CURSOR_FORMAT_2C		(0x0 << 24)
#define CURSOR_FORMAT_3C		(0x1 << 24)
#define CURSOR_FORMAT_4C		(0x2 << 24)
#define CURSOR_FORMAT_ARGB		(0x4 << 24)
#define CURSOR_FORMAT_XRGB		(0x5 << 24)

/* Mobile HW cursor (and i810) */
#define CURSOR_A_CONTROL	CURSOR_CONTROL
#define CURSOR_B_CONTROL	0x700c0
#define CURSOR_MODE_MASK		0x27
#define CURSOR_MODE_DISABLE		0
#define CURSOR_MODE_64_3C		0x04
#define CURSOR_MODE_64_4C_AX		0x05
#define CURSOR_MODE_64_4C		0x06
#define CURSOR_MODE_64_32B_AX		0x07
#define CURSOR_MODE_64_ARGB_AX		0x27
#define CURSOR_PIPE_SELECT_SHIFT	28
#define CURSOR_MOBILE_GAMMA_ENABLE	(1 << 26)
#define CURSOR_MEM_TYPE_LOCAL		(1 << 25)

/* All platforms (desktop has no pipe B) */
#define CURSOR_A_BASEADDR	0x70084
#define CURSOR_B_BASEADDR	0x700c4
#define CURSOR_BASE_MASK		0xffffff00

#define CURSOR_A_POSITION	0x70088
#define CURSOR_B_POSITION	0x700c8
#define CURSOR_POS_SIGN			(1 << 15)
#define CURSOR_POS_MASK			0x7ff
#define CURSOR_X_SHIFT			0
#define CURSOR_Y_SHIFT			16

#define CURSOR_A_PALETTE0	0x70090
#define CURSOR_A_PALETTE1	0x70094
#define CURSOR_A_PALETTE2	0x70098
#define CURSOR_A_PALETTE3	0x7009c
#define CURSOR_B_PALETTE0	0x700d0
#define CURSOR_B_PALETTE1	0x700d4
#define CURSOR_B_PALETTE2	0x700d8
#define CURSOR_B_PALETTE3	0x700dc
#define CURSOR_COLOR_MASK			0xff
#define CURSOR_RED_SHIFT			16
#define CURSOR_GREEN_SHIFT			8
#define CURSOR_BLUE_SHIFT			0
#define CURSOR_PALETTE_MASK			0xffffff

/* Desktop only */
#define CURSOR_SIZE		0x700a0
#define CURSOR_SIZE_MASK		0x3ff
#define CURSOR_SIZE_H_SHIFT		0
#define CURSOR_SIZE_V_SHIFT		12

#define DSPACNTR		0x70180
#define DSPBCNTR		0x71180
#define DISPPLANE_PLANE_ENABLE		(1 << 31)
#define DISPPLANE_PLANE_DISABLE		0
#define DISPPLANE_GAMMA_ENABLE		(1<<30)
#define DISPPLANE_GAMMA_DISABLE		0
#define DISPPLANE_PIXFORMAT_MASK	(0xf<<26)
#define DISPPLANE_8BPP			(0x2<<26)
#define DISPPLANE_15_16BPP		(0x4<<26)
#define DISPPLANE_16BPP			(0x5<<26)
#define DISPPLANE_32BPP_NO_ALPHA	(0x6<<26)
#define DISPPLANE_32BPP			(0x7<<26)
#define DISPPLANE_STEREO_ENABLE		(1<<25)
#define DISPPLANE_STEREO_DISABLE	0
#define DISPPLANE_SEL_PIPE_SHIFT	24
#define DISPPLANE_SRC_KEY_ENABLE	(1<<22)
#define DISPPLANE_SRC_KEY_DISABLE	0
#define DISPPLANE_LINE_DOUBLE		(1<<20)
#define DISPPLANE_NO_LINE_DOUBLE	0
#define DISPPLANE_STEREO_POLARITY_FIRST	0
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
/* plane B only */
#define DISPPLANE_ALPHA_TRANS_ENABLE	(1<<15)
#define DISPPLANE_ALPHA_TRANS_DISABLE	0
#define DISPPLANE_SPRITE_ABOVE_DISPLAYA	0
#define DISPPLANE_SPRITE_ABOVE_OVERLAY	1

#define DSPABASE		0x70184
#define DSPASTRIDE		0x70188

#define DSPBBASE		0x71184
#define DSPBSTRIDE		0x71188

#define VGACNTRL		0x71400
#define VGA_DISABLE			(1 << 31)
#define VGA_ENABLE			0
#define VGA_PIPE_SELECT_SHIFT		29
#define VGA_PALETTE_READ_SELECT		23
#define VGA_PALETTE_A_WRITE_DISABLE	(1 << 22)
#define VGA_PALETTE_B_WRITE_DISABLE	(1 << 21)
#define VGA_LEGACY_PALETTE		(1 << 20)
#define VGA_6BIT_DAC			0
#define VGA_8BIT_DAC			(1 << 20)

#define ADD_ID			0x71408
#define ADD_ID_MASK			0xff

/* BIOS scratch area registers (830M and 845G). */
#define SWF0			0x71410
#define SWF1			0x71414
#define SWF2			0x71418
#define SWF3			0x7141c
#define SWF4			0x71420
#define SWF5			0x71424
#define SWF6			0x71428

/* BIOS scratch area registers (852GM, 855GM, 865G). */
#define SWF00			0x70410
#define SWF01			0x70414
#define SWF02			0x70418
#define SWF03			0x7041c
#define SWF04			0x70420
#define SWF05			0x70424
#define SWF06			0x70428

#define SWF10			SWF0
#define SWF11			SWF1
#define SWF12			SWF2
#define SWF13			SWF3
#define SWF14			SWF4
#define SWF15			SWF5
#define SWF16			SWF6

#define SWF30			0x72414
#define SWF31			0x72418
#define SWF32			0x7241c

/* Memory Commands */
#define MI_NOOP			(0x00 << 23)
#define MI_NOOP_WRITE_ID		(1 << 22)
#define MI_NOOP_ID_MASK			((1 << 22) - 1)

#define MI_FLUSH		(0x04 << 23)
#define MI_WRITE_DIRTY_STATE		(1 << 4)
#define MI_END_SCENE			(1 << 3)
#define MI_INHIBIT_RENDER_CACHE_FLUSH	(1 << 2)
#define MI_INVALIDATE_MAP_CACHE		(1 << 0)

#define MI_STORE_DWORD_IMM	((0x20 << 23) | 1)

/* 2D Commands */
#define COLOR_BLT_CMD		((2 << 29) | (0x40 << 22) | 3)
#define XY_COLOR_BLT_CMD	((2 << 29) | (0x50 << 22) | 4)
#define XY_SETUP_CLIP_BLT_CMD	((2 << 29) | (0x03 << 22) | 1)
#define XY_SRC_COPY_BLT_CMD	((2 << 29) | (0x53 << 22) | 6)
#define SRC_COPY_BLT_CMD	((2 << 29) | (0x43 << 22) | 4)
#define XY_MONO_PAT_BLT_CMD	((2 << 29) | (0x52 << 22) | 7)
#define XY_MONO_SRC_BLT_CMD	((2 << 29) | (0x54 << 22) | 6)
#define XY_MONO_SRC_IMM_BLT_CMD	((2 << 29) | (0x71 << 22) | 5)
#define TXT_IMM_BLT_CMD	        ((2 << 29) | (0x30 << 22) | 2)
#define SETUP_BLT_CMD	        ((2 << 29) | (0x00 << 22) | 6)

#define DW_LENGTH_MASK			0xff

#define WRITE_ALPHA			(1 << 21)
#define WRITE_RGB			(1 << 20)
#define VERT_SEED			(3 << 8)
#define HORIZ_SEED			(3 << 12)

#define COLOR_DEPTH_8			(0 << 24)
#define COLOR_DEPTH_16			(1 << 24)
#define COLOR_DEPTH_32			(3 << 24)

#define SRC_ROP_GXCOPY			0xcc
#define SRC_ROP_GXXOR			0x66

#define PAT_ROP_GXCOPY                  0xf0
#define PAT_ROP_GXXOR                   0x5a

#define PITCH_SHIFT			0
#define ROP_SHIFT			16
#define WIDTH_SHIFT			0
#define HEIGHT_SHIFT			16

/* in bytes */
#define MAX_MONO_IMM_SIZE		128


/*** Macros ***/

/* I/O macros */
#define INREG8(addr)	      readb((u8 __iomem *)(dinfo->mmio_base + (addr)))
#define INREG16(addr)	      readw((u16 __iomem *)(dinfo->mmio_base + (addr)))
#define INREG(addr)	      readl((u32 __iomem *)(dinfo->mmio_base + (addr)))
#define OUTREG8(addr, val)    writeb((val),(u8 __iomem *)(dinfo->mmio_base + \
							   (addr)))
#define OUTREG16(addr, val)    writew((val),(u16 __iomem *)(dinfo->mmio_base + \
							   (addr)))
#define OUTREG(addr, val)     writel((val),(u32 __iomem *)(dinfo->mmio_base + \
                                     (addr)))

/* Ring buffer macros */
#define OUT_RING(n)	do {						\
	writel((n), (u32 __iomem *)(dinfo->ring.virtual + dinfo->ring_tail));\
	dinfo->ring_tail += 4;						\
	dinfo->ring_tail &= dinfo->ring_tail_mask;			\
} while (0)

#define START_RING(n)	do {						\
	if (dinfo->ring_space < (n) * 4)				\
		wait_ring(dinfo,(n) * 4);				\
	dinfo->ring_space -= (n) * 4;					\
} while (0)

#define ADVANCE_RING()	do {						\
	OUTREG(PRI_RING_TAIL, dinfo->ring_tail);                        \
} while (0)

#define DO_RING_IDLE()	do {						\
	u32 head, tail;							\
	do {								\
		head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;		\
		tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;		\
		udelay(10);						\
	} while (head != tail);						\
} while (0)


/* function protoypes */
extern int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo);
extern int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
				int *stolen_size);
extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);
extern const char *intelfbhw_dvo_to_string(int dvo);
extern int intelfbhw_validate_mode(struct intelfb_info *dinfo,
				   struct fb_var_screeninfo *var);
extern int intelfbhw_pan_display(struct fb_var_screeninfo *var,
				 struct fb_info *info);
extern void intelfbhw_do_blank(int blank, struct fb_info *info);
extern void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
				unsigned red, unsigned green, unsigned blue,
				unsigned transp);
extern int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
				   struct intelfb_hwstate *hw, int flag);
extern void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
				     struct intelfb_hwstate *hw);
extern int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
				struct intelfb_hwstate *hw,
				struct fb_var_screeninfo *var);
extern int intelfbhw_program_mode(struct intelfb_info *dinfo,
				  const struct intelfb_hwstate *hw, int blank);
extern void intelfbhw_do_sync(struct intelfb_info *dinfo);
extern void intelfbhw_2d_stop(struct intelfb_info *dinfo);
extern void intelfbhw_2d_start(struct intelfb_info *dinfo);
extern void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y,
				  u32 w, u32 h, u32 color, u32 pitch, u32 bpp,
				  u32 rop);
extern void intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
				u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch,
				u32 bpp);
extern int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg,
				  u32 w, u32 h, const u8* cdat, u32 x, u32 y,
				  u32 pitch, u32 bpp);
extern void intelfbhw_cursor_init(struct intelfb_info *dinfo);
extern void intelfbhw_cursor_hide(struct intelfb_info *dinfo);
extern void intelfbhw_cursor_show(struct intelfb_info *dinfo);
extern void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y);
extern void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg,
				      u32 fg);
extern void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width,
				  int height, u8 *data);
extern void intelfbhw_cursor_reset(struct intelfb_info *dinfo);
extern int intelfbhw_enable_irq(struct intelfb_info *dinfo);
extern void intelfbhw_disable_irq(struct intelfb_info *dinfo);
extern int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe);
extern int intelfbhw_active_pipe(const struct intelfb_hwstate *hw);

#endif /* _INTELFBHW_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _INTELFBHW_H
	2	#define _INTELFBHW_H
	3
	4	/* $DHD: intelfb/intelfbhw.h,v 1.5 2003/06/27 15:06:25 dawes Exp $ */
	5
	6
	7	/* HW-specific data */
	8
	9	/* Information about the 852GM/855GM variants */
	10	#define INTEL_85X_CAPID 0x44
	11	#define INTEL_85X_VARIANT_MASK 0x7
	12	#define INTEL_85X_VARIANT_SHIFT 5
	13	#define INTEL_VAR_855GME 0x0
	14	#define INTEL_VAR_855GM 0x4
	15	#define INTEL_VAR_852GME 0x2
	16	#define INTEL_VAR_852GM 0x5
	17
	18	/* Information about DVO/LVDS Ports */
	19	#define DVOA_PORT 0x1
	20	#define DVOB_PORT 0x2
	21	#define DVOC_PORT 0x4
	22	#define LVDS_PORT 0x8
	23
	24	/*
	25	* The Bridge device's PCI config space has information about the
	26	* fb aperture size and the amount of pre-reserved memory.
	27	*/
	28	#define INTEL_GMCH_CTRL 0x52
	29	#define INTEL_GMCH_ENABLED 0x4
	30	#define INTEL_GMCH_MEM_MASK 0x1
	31	#define INTEL_GMCH_MEM_64M 0x1
	32	#define INTEL_GMCH_MEM_128M 0
	33
	34	#define INTEL_830_GMCH_GMS_MASK (0x7 << 4)
	35	#define INTEL_830_GMCH_GMS_DISABLED (0x0 << 4)
	36	#define INTEL_830_GMCH_GMS_LOCAL (0x1 << 4)
	37	#define INTEL_830_GMCH_GMS_STOLEN_512 (0x2 << 4)
	38	#define INTEL_830_GMCH_GMS_STOLEN_1024 (0x3 << 4)
	39	#define INTEL_830_GMCH_GMS_STOLEN_8192 (0x4 << 4)
	40
	41	#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
	42	#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
	43	#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
	44	#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
	45	#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
	46	#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
	47	#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
	48
	49	#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
	50	#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
	51
	52	/* HW registers */
	53
	54	/* Fence registers */
	55	#define FENCE 0x2000
	56	#define FENCE_NUM 8
	57
	58	/* Primary ring buffer */
	59	#define PRI_RING_TAIL 0x2030
	60	#define RING_TAIL_MASK 0x001ffff8
	61	#define RING_INUSE 0x1
	62
	63	#define PRI_RING_HEAD 0x2034
	64	#define RING_HEAD_WRAP_MASK 0x7ff
65	#define RING_HEAD_WRAP_SHIFT 21
66	#define RING_HEAD_MASK 0x001ffffc
67
68	#define PRI_RING_START 0x2038
69	#define RING_START_MASK 0xfffff000
70
71	#define PRI_RING_LENGTH 0x203c
72	#define RING_LENGTH_MASK 0x001ff000
73	#define RING_REPORT_MASK (0x3 << 1)
74	#define RING_NO_REPORT (0x0 << 1)
75	#define RING_REPORT_64K (0x1 << 1)
76	#define RING_REPORT_4K (0x2 << 1)
77	#define RING_REPORT_128K (0x3 << 1)
78	#define RING_ENABLE 0x1
79
80	/*
81	* Tail can't wrap to any closer than RING_MIN_FREE bytes of the head,
82	* and the last RING_MIN_FREE bytes need to be padded with MI_NOOP
83	*/
84	#define RING_MIN_FREE 64
85
689c9568	86	#define IPEHR 0x2088
1da177e4 LT	87
	88	#define INSTDONE 0x2090
	89	#define PRI_RING_EMPTY 1
	90
9a5f019b EH	91	#define HWSTAM 0x2098
	92	#define IER 0x20A0
	93	#define IIR 0x20A4
	94	#define IMR 0x20A8
	95	#define VSYNC_PIPE_A_INTERRUPT (1 << 7)
ee5618f4	96	#define PIPE_A_EVENT_INTERRUPT (1 << 6)
9a5f019b EH	97	#define VSYNC_PIPE_B_INTERRUPT (1 << 5)
	98	#define PIPE_B_EVENT_INTERRUPT (1 << 4)
	99	#define HOST_PORT_EVENT_INTERRUPT (1 << 3)
	100	#define CAPTURE_EVENT_INTERRUPT (1 << 2)
	101	#define USER_DEFINED_INTERRUPT (1 << 1)
	102	#define BREAKPOINT_INTERRUPT 1
	103
1da177e4 LT	104	#define INSTPM 0x20c0
	105	#define SYNC_FLUSH_ENABLE (1 << 5)
	106
	107	#define INSTPS 0x20c4
	108
	109	#define MEM_MODE 0x20cc
	110
	111	#define MASK_SHIFT 16
	112
	113	#define FW_BLC_0 0x20d8
	114	#define FW_DISPA_WM_SHIFT 0
	115	#define FW_DISPA_WM_MASK 0x3f
	116	#define FW_DISPA_BL_SHIFT 8
	117	#define FW_DISPA_BL_MASK 0xf
	118	#define FW_DISPB_WM_SHIFT 16
	119	#define FW_DISPB_WM_MASK 0x1f
	120	#define FW_DISPB_BL_SHIFT 24
	121	#define FW_DISPB_BL_MASK 0x7
	122
	123	#define FW_BLC_1 0x20dc
	124	#define FW_DISPC_WM_SHIFT 0
	125	#define FW_DISPC_WM_MASK 0x1f
	126	#define FW_DISPC_BL_SHIFT 8
	127	#define FW_DISPC_BL_MASK 0x7
	128
82c10f07 DM	129	#define GPIOA 0x5010
82c10f07 DM	130	#define GPIOB 0x5014
689c9568 KH	131	#define GPIOC 0x5018 /* this may be external DDC on i830 */
	132	#define GPIOD 0x501C /* this is DVO DDC */
	133	#define GPIOE 0x5020 /* this is DVO i2C */
82c10f07	134	#define GPIOF 0x5024
1da177e4 LT	135
	136	/* PLL registers */
	137	#define VGA0_DIVISOR 0x06000
	138	#define VGA1_DIVISOR 0x06004
	139	#define VGAPD 0x06010
	140	#define VGAPD_0_P1_SHIFT 0
	141	#define VGAPD_0_P1_FORCE_DIV2 (1 << 5)
	142	#define VGAPD_0_P2_SHIFT 7
	143	#define VGAPD_1_P1_SHIFT 8
	144	#define VGAPD_1_P1_FORCE_DIV2 (1 << 13)
	145	#define VGAPD_1_P2_SHIFT 15
	146
	147	#define DPLL_A 0x06014
	148	#define DPLL_B 0x06018
	149	#define DPLL_VCO_ENABLE (1 << 31)
	150	#define DPLL_2X_CLOCK_ENABLE (1 << 30)
	151	#define DPLL_SYNCLOCK_ENABLE (1 << 29)
	152	#define DPLL_VGA_MODE_DISABLE (1 << 28)
	153	#define DPLL_P2_MASK 1
	154	#define DPLL_P2_SHIFT 23
3aff13cf	155	#define DPLL_I9XX_P2_SHIFT 24
1da177e4 LT	156	#define DPLL_P1_FORCE_DIV2 (1 << 21)
	157	#define DPLL_P1_MASK 0x1f
	158	#define DPLL_P1_SHIFT 16
	159	#define DPLL_REFERENCE_SELECT_MASK (0x3 << 13)
	160	#define DPLL_REFERENCE_DEFAULT (0x0 << 13)
	161	#define DPLL_REFERENCE_TVCLK (0x2 << 13)
	162	#define DPLL_RATE_SELECT_MASK (1 << 8)
	163	#define DPLL_RATE_SELECT_FP0 (0 << 8)
	164	#define DPLL_RATE_SELECT_FP1 (1 << 8)
	165
	166	#define FPA0 0x06040
	167	#define FPA1 0x06044
	168	#define FPB0 0x06048
	169	#define FPB1 0x0604c
	170	#define FP_DIVISOR_MASK 0x3f
	171	#define FP_N_DIVISOR_SHIFT 16
	172	#define FP_M1_DIVISOR_SHIFT 8
	173	#define FP_M2_DIVISOR_SHIFT 0
	174
	175	/* PLL parameters (these are for 852GM/855GM/865G, check earlier chips). */
	176	/* Clock values are in units of kHz */
	177	#define PLL_REFCLK 48000
1da177e4 LT	178	#define MIN_CLOCK 25000
1da177e4 LT	179	#define MAX_CLOCK 350000
1da177e4	180
1da177e4 LT	181	/* Two pipes */
	182	#define PIPE_A 0
	183	#define PIPE_B 1
	184	#define PIPE_MASK 1
	185
	186	/* palette registers */
	187	#define PALETTE_A 0x0a000
	188	#define PALETTE_B 0x0a800
	189	#ifndef PALETTE_8_ENTRIES
	190	#define PALETTE_8_ENTRIES 256
	191	#endif
	192	#define PALETTE_8_SIZE (PALETTE_8_ENTRIES * 4)
	193	#define PALETTE_10_ENTRIES 128
	194	#define PALETTE_10_SIZE (PALETTE_10_ENTRIES * 8)
	195	#define PALETTE_8_MASK 0xff
	196	#define PALETTE_8_RED_SHIFT 16
	197	#define PALETTE_8_GREEN_SHIFT 8
	198	#define PALETTE_8_BLUE_SHIFT 0
	199
	200	/* CRTC registers */
	201	#define HTOTAL_A 0x60000
	202	#define HBLANK_A 0x60004
	203	#define HSYNC_A 0x60008
	204	#define VTOTAL_A 0x6000c
	205	#define VBLANK_A 0x60010
	206	#define VSYNC_A 0x60014
	207	#define SRC_SIZE_A 0x6001c
	208	#define BCLRPAT_A 0x60020
	209
	210	#define HTOTAL_B 0x61000
	211	#define HBLANK_B 0x61004
	212	#define HSYNC_B 0x61008
	213	#define VTOTAL_B 0x6100c
	214	#define VBLANK_B 0x61010
	215	#define VSYNC_B 0x61014
	216	#define SRC_SIZE_B 0x6101c
	217	#define BCLRPAT_B 0x61020
	218
	219	#define HTOTAL_MASK 0xfff
	220	#define HTOTAL_SHIFT 16
	221	#define HACTIVE_MASK 0x7ff
	222	#define HACTIVE_SHIFT 0
	223	#define HBLANKEND_MASK 0xfff
	224	#define HBLANKEND_SHIFT 16
	225	#define HBLANKSTART_MASK 0xfff
	226	#define HBLANKSTART_SHIFT 0
	227	#define HSYNCEND_MASK 0xfff
	228	#define HSYNCEND_SHIFT 16
	229	#define HSYNCSTART_MASK 0xfff
	230	#define HSYNCSTART_SHIFT 0
	231	#define VTOTAL_MASK 0xfff
	232	#define VTOTAL_SHIFT 16
	233	#define VACTIVE_MASK 0x7ff
	234	#define VACTIVE_SHIFT 0
	235	#define VBLANKEND_MASK 0xfff
	236	#define VBLANKEND_SHIFT 16
	237	#define VBLANKSTART_MASK 0xfff
	238	#define VBLANKSTART_SHIFT 0
	239	#define VSYNCEND_MASK 0xfff
	240	#define VSYNCEND_SHIFT 16
	241	#define VSYNCSTART_MASK 0xfff
	242	#define VSYNCSTART_SHIFT 0
	243	#define SRC_SIZE_HORIZ_MASK 0x7ff
	244	#define SRC_SIZE_HORIZ_SHIFT 16
245	#define SRC_SIZE_VERT_MASK 0x7ff
246	#define SRC_SIZE_VERT_SHIFT 0
247
248	#define ADPA 0x61100
249	#define ADPA_DAC_ENABLE (1 << 31)
250	#define ADPA_DAC_DISABLE 0
251	#define ADPA_PIPE_SELECT_SHIFT 30
252	#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
253	#define ADPA_SETS_HVPOLARITY 0
254	#define ADPA_DPMS_CONTROL_MASK (0x3 << 10)
255	#define ADPA_DPMS_D0 (0x0 << 10)
256	#define ADPA_DPMS_D2 (0x1 << 10)
257	#define ADPA_DPMS_D1 (0x2 << 10)
258	#define ADPA_DPMS_D3 (0x3 << 10)
259	#define ADPA_VSYNC_ACTIVE_SHIFT 4
260	#define ADPA_HSYNC_ACTIVE_SHIFT 3
261	#define ADPA_SYNC_ACTIVE_MASK 1
262	#define ADPA_SYNC_ACTIVE_HIGH 1
263	#define ADPA_SYNC_ACTIVE_LOW 0
264
265	#define DVOA 0x61120
266	#define DVOB 0x61140
267	#define DVOC 0x61160
268	#define LVDS 0x61180
269	#define PORT_ENABLE (1 << 31)
270	#define PORT_PIPE_SELECT_SHIFT 30
271	#define PORT_TV_FLAGS_MASK 0xFF
689c9568 KH	272	#define PORT_TV_FLAGS 0xC4 /* ripped from my BIOS
689c9568 KH	273	to understand and correct */
1da177e4 LT	274
	275	#define DVOA_SRCDIM 0x61124
	276	#define DVOB_SRCDIM 0x61144
	277	#define DVOC_SRCDIM 0x61164
	278
ee5618f4 KH	279	#define PIPEA_DSL 0x70000
ee5618f4 KH	280	#define PIPEB_DSL 0x71000
1da177e4 LT	281	#define PIPEACONF 0x70008
1da177e4 LT	282	#define PIPEBCONF 0x71008
394d3af7 KH	283	#define PIPEASTAT 0x70024 /* bits 0-15 are "write 1 to clear" */
	284	#define PIPEBSTAT 0x71024
	285
1da177e4 LT	286	#define PIPECONF_ENABLE (1 << 31)
	287	#define PIPECONF_DISABLE 0
	288	#define PIPECONF_DOUBLE_WIDE (1 << 30)
	289	#define PIPECONF_SINGLE_WIDE 0
	290	#define PIPECONF_LOCKED (1 << 25)
	291	#define PIPECONF_UNLOCKED 0
	292	#define PIPECONF_GAMMA (1 << 24)
	293	#define PIPECONF_PALETTE 0
10b98368 KH	294	#define PIPECONF_PROGRESSIVE (0 << 21)
	295	#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
	296	#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
	297	#define PIPECONF_INTERLACE_MASK (7 << 21)
1da177e4	298
394d3af7 KH	299	/* enable bits, write 1 to enable */
	300	#define PIPESTAT_FIFO_UNDERRUN (1 << 31)
	301	#define PIPESTAT_CRC_ERROR_EN (1 << 29)
	302	#define PIPESTAT_CRC_DONE_EN (1 << 28)
	303	#define PIPESTAT_HOTPLUG_EN (1 << 26)
	304	#define PIPESTAT_VERTICAL_SYNC_EN (1 << 25)
	305	#define PIPESTAT_DISPLINE_COMP_EN (1 << 24)
	306	#define PIPESTAT_FLD_EVT_ODD_EN (1 << 21)
	307	#define PIPESTAT_FLD_EVT_EVEN_EN (1 << 20)
	308	#define PIPESTAT_TV_HOTPLUG_EN (1 << 18)
	309	#define PIPESTAT_VBLANK_EN (1 << 17)
	310	#define PIPESTAT_OVL_UPDATE_EN (1 << 16)
	311	/* status bits, write 1 to clear */
	312	#define PIPESTAT_HOTPLUG_STATE (1 << 15)
	313	#define PIPESTAT_CRC_ERROR (1 << 13)
	314	#define PIPESTAT_CRC_DONE (1 << 12)
	315	#define PIPESTAT_HOTPLUG (1 << 10)
	316	#define PIPESTAT_VSYNC (1 << 9)
	317	#define PIPESTAT_DISPLINE_COMP (1 << 8)
	318	#define PIPESTAT_FLD_EVT_ODD (1 << 5)
	319	#define PIPESTAT_FLD_EVT_EVEN (1 << 4)
	320	#define PIPESTAT_TV_HOTPLUG (1 << 2)
	321	#define PIPESTAT_VBLANK (1 << 1)
	322	#define PIPESTAT_OVL_UPDATE (1 << 0)
	323
1da177e4 LT	324	#define DISPARB 0x70030
	325	#define DISPARB_AEND_MASK 0x1ff
	326	#define DISPARB_AEND_SHIFT 0
	327	#define DISPARB_BEND_MASK 0x3ff
	328	#define DISPARB_BEND_SHIFT 9
	329
	330	/* Desktop HW cursor */
	331	#define CURSOR_CONTROL 0x70080
	332	#define CURSOR_ENABLE (1 << 31)
	333	#define CURSOR_GAMMA_ENABLE (1 << 30)
	334	#define CURSOR_STRIDE_MASK (0x3 << 28)
	335	#define CURSOR_STRIDE_256 (0x0 << 28)
	336	#define CURSOR_STRIDE_512 (0x1 << 28)
	337	#define CURSOR_STRIDE_1K (0x2 << 28)
	338	#define CURSOR_STRIDE_2K (0x3 << 28)
	339	#define CURSOR_FORMAT_MASK (0x7 << 24)
	340	#define CURSOR_FORMAT_2C (0x0 << 24)
	341	#define CURSOR_FORMAT_3C (0x1 << 24)
	342	#define CURSOR_FORMAT_4C (0x2 << 24)
	343	#define CURSOR_FORMAT_ARGB (0x4 << 24)
	344	#define CURSOR_FORMAT_XRGB (0x5 << 24)
	345
	346	/* Mobile HW cursor (and i810) */
	347	#define CURSOR_A_CONTROL CURSOR_CONTROL
	348	#define CURSOR_B_CONTROL 0x700c0
	349	#define CURSOR_MODE_MASK 0x27
	350	#define CURSOR_MODE_DISABLE 0
	351	#define CURSOR_MODE_64_3C 0x04
	352	#define CURSOR_MODE_64_4C_AX 0x05
	353	#define CURSOR_MODE_64_4C 0x06
	354	#define CURSOR_MODE_64_32B_AX 0x07
	355	#define CURSOR_MODE_64_ARGB_AX 0x27
	356	#define CURSOR_PIPE_SELECT_SHIFT 28
	357	#define CURSOR_MOBILE_GAMMA_ENABLE (1 << 26)
	358	#define CURSOR_MEM_TYPE_LOCAL (1 << 25)
	359
	360	/* All platforms (desktop has no pipe B) */
	361	#define CURSOR_A_BASEADDR 0x70084
	362	#define CURSOR_B_BASEADDR 0x700c4
	363	#define CURSOR_BASE_MASK 0xffffff00
	364
	365	#define CURSOR_A_POSITION 0x70088
	366	#define CURSOR_B_POSITION 0x700c8
	367	#define CURSOR_POS_SIGN (1 << 15)
	368	#define CURSOR_POS_MASK 0x7ff
	369	#define CURSOR_X_SHIFT 0
	370	#define CURSOR_Y_SHIFT 16
	371
	372	#define CURSOR_A_PALETTE0 0x70090
	373	#define CURSOR_A_PALETTE1 0x70094
	374	#define CURSOR_A_PALETTE2 0x70098
	375	#define CURSOR_A_PALETTE3 0x7009c
	376	#define CURSOR_B_PALETTE0 0x700d0
	377	#define CURSOR_B_PALETTE1 0x700d4
	378	#define CURSOR_B_PALETTE2 0x700d8
	379	#define CURSOR_B_PALETTE3 0x700dc
	380	#define CURSOR_COLOR_MASK 0xff
	381	#define CURSOR_RED_SHIFT 16
	382	#define CURSOR_GREEN_SHIFT 8
	383	#define CURSOR_BLUE_SHIFT 0
	384	#define CURSOR_PALETTE_MASK 0xffffff
	385
	386	/* Desktop only */
	387	#define CURSOR_SIZE 0x700a0
388	#define CURSOR_SIZE_MASK 0x3ff
389	#define CURSOR_SIZE_H_SHIFT 0
390	#define CURSOR_SIZE_V_SHIFT 12
391
392	#define DSPACNTR 0x70180
393	#define DSPBCNTR 0x71180
394	#define DISPPLANE_PLANE_ENABLE (1 << 31)
395	#define DISPPLANE_PLANE_DISABLE 0
396	#define DISPPLANE_GAMMA_ENABLE (1<<30)
397	#define DISPPLANE_GAMMA_DISABLE 0
398	#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
399	#define DISPPLANE_8BPP (0x2<<26)
400	#define DISPPLANE_15_16BPP (0x4<<26)
401	#define DISPPLANE_16BPP (0x5<<26)
689c9568	402	#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1da177e4 LT	403	#define DISPPLANE_32BPP (0x7<<26)
	404	#define DISPPLANE_STEREO_ENABLE (1<<25)
	405	#define DISPPLANE_STEREO_DISABLE 0
	406	#define DISPPLANE_SEL_PIPE_SHIFT 24
	407	#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
	408	#define DISPPLANE_SRC_KEY_DISABLE 0
	409	#define DISPPLANE_LINE_DOUBLE (1<<20)
	410	#define DISPPLANE_NO_LINE_DOUBLE 0
	411	#define DISPPLANE_STEREO_POLARITY_FIRST 0
	412	#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
	413	/* plane B only */
	414	#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
	415	#define DISPPLANE_ALPHA_TRANS_DISABLE 0
	416	#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
	417	#define DISPPLANE_SPRITE_ABOVE_OVERLAY 1
	418
	419	#define DSPABASE 0x70184
	420	#define DSPASTRIDE 0x70188
	421
	422	#define DSPBBASE 0x71184
	423	#define DSPBSTRIDE 0x71188
	424
	425	#define VGACNTRL 0x71400
	426	#define VGA_DISABLE (1 << 31)
	427	#define VGA_ENABLE 0
	428	#define VGA_PIPE_SELECT_SHIFT 29
	429	#define VGA_PALETTE_READ_SELECT 23
	430	#define VGA_PALETTE_A_WRITE_DISABLE (1 << 22)
	431	#define VGA_PALETTE_B_WRITE_DISABLE (1 << 21)
	432	#define VGA_LEGACY_PALETTE (1 << 20)
	433	#define VGA_6BIT_DAC 0
	434	#define VGA_8BIT_DAC (1 << 20)
	435
	436	#define ADD_ID 0x71408
	437	#define ADD_ID_MASK 0xff
	438
	439	/* BIOS scratch area registers (830M and 845G). */
	440	#define SWF0 0x71410
	441	#define SWF1 0x71414
	442	#define SWF2 0x71418
	443	#define SWF3 0x7141c
	444	#define SWF4 0x71420
	445	#define SWF5 0x71424
	446	#define SWF6 0x71428
	447
	448	/* BIOS scratch area registers (852GM, 855GM, 865G). */
	449	#define SWF00 0x70410
	450	#define SWF01 0x70414
	451	#define SWF02 0x70418
	452	#define SWF03 0x7041c
	453	#define SWF04 0x70420
	454	#define SWF05 0x70424
	455	#define SWF06 0x70428
	456
	457	#define SWF10 SWF0
	458	#define SWF11 SWF1
	459	#define SWF12 SWF2
	460	#define SWF13 SWF3
	461	#define SWF14 SWF4
	462	#define SWF15 SWF5
	463	#define SWF16 SWF6
	464
	465	#define SWF30 0x72414
	466	#define SWF31 0x72418
467	#define SWF32 0x7241c
468
469	/* Memory Commands */
470	#define MI_NOOP (0x00 << 23)
471	#define MI_NOOP_WRITE_ID (1 << 22)
472	#define MI_NOOP_ID_MASK ((1 << 22) - 1)
473
474	#define MI_FLUSH (0x04 << 23)
475	#define MI_WRITE_DIRTY_STATE (1 << 4)
476	#define MI_END_SCENE (1 << 3)
477	#define MI_INHIBIT_RENDER_CACHE_FLUSH (1 << 2)
478	#define MI_INVALIDATE_MAP_CACHE (1 << 0)
479
480	#define MI_STORE_DWORD_IMM ((0x20 << 23) \| 1)
481
482	/* 2D Commands */
483	#define COLOR_BLT_CMD ((2 << 29) \| (0x40 << 22) \| 3)
484	#define XY_COLOR_BLT_CMD ((2 << 29) \| (0x50 << 22) \| 4)
485	#define XY_SETUP_CLIP_BLT_CMD ((2 << 29) \| (0x03 << 22) \| 1)
486	#define XY_SRC_COPY_BLT_CMD ((2 << 29) \| (0x53 << 22) \| 6)
487	#define SRC_COPY_BLT_CMD ((2 << 29) \| (0x43 << 22) \| 4)
488	#define XY_MONO_PAT_BLT_CMD ((2 << 29) \| (0x52 << 22) \| 7)
489	#define XY_MONO_SRC_BLT_CMD ((2 << 29) \| (0x54 << 22) \| 6)
490	#define XY_MONO_SRC_IMM_BLT_CMD ((2 << 29) \| (0x71 << 22) \| 5)
491	#define TXT_IMM_BLT_CMD ((2 << 29) \| (0x30 << 22) \| 2)
492	#define SETUP_BLT_CMD ((2 << 29) \| (0x00 << 22) \| 6)
493
494	#define DW_LENGTH_MASK 0xff
495
496	#define WRITE_ALPHA (1 << 21)
497	#define WRITE_RGB (1 << 20)
498	#define VERT_SEED (3 << 8)
499	#define HORIZ_SEED (3 << 12)
500
501	#define COLOR_DEPTH_8 (0 << 24)
502	#define COLOR_DEPTH_16 (1 << 24)
503	#define COLOR_DEPTH_32 (3 << 24)
504
505	#define SRC_ROP_GXCOPY 0xcc
506	#define SRC_ROP_GXXOR 0x66
507
508	#define PAT_ROP_GXCOPY 0xf0
509	#define PAT_ROP_GXXOR 0x5a
510
511	#define PITCH_SHIFT 0
512	#define ROP_SHIFT 16
513	#define WIDTH_SHIFT 0
514	#define HEIGHT_SHIFT 16
515
516	/* in bytes */
517	#define MAX_MONO_IMM_SIZE 128
518
519
520	/* Macros */
521
522	/* I/O macros */
523	#define INREG8(addr) readb((u8 __iomem *)(dinfo->mmio_base + (addr)))
3ce6fb43	524	#define INREG16(addr) readw((u16 __iomem *)(dinfo->mmio_base + (addr)))
1da177e4 LT	525	#define INREG(addr) readl((u32 __iomem *)(dinfo->mmio_base + (addr)))
	526	#define OUTREG8(addr, val) writeb((val),(u8 __iomem *)(dinfo->mmio_base + \
	527	(addr)))
3ce6fb43 EH	528	#define OUTREG16(addr, val) writew((val),(u16 __iomem *)(dinfo->mmio_base + \
3ce6fb43 EH	529	(addr)))
1da177e4 LT	530	#define OUTREG(addr, val) writel((val),(u32 __iomem *)(dinfo->mmio_base + \
	531	(addr)))
	532
	533	/* Ring buffer macros */
	534	#define OUT_RING(n) do { \
	535	writel((n), (u32 __iomem *)(dinfo->ring.virtual + dinfo->ring_tail));\
	536	dinfo->ring_tail += 4; \
	537	dinfo->ring_tail &= dinfo->ring_tail_mask; \
	538	} while (0)
	539
	540	#define START_RING(n) do { \
	541	if (dinfo->ring_space < (n) * 4) \
	542	wait_ring(dinfo,(n) * 4); \
	543	dinfo->ring_space -= (n) * 4; \
	544	} while (0)
	545
	546	#define ADVANCE_RING() do { \
	547	OUTREG(PRI_RING_TAIL, dinfo->ring_tail); \
	548	} while (0)
	549
	550	#define DO_RING_IDLE() do { \
	551	u32 head, tail; \
	552	do { \
	553	head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; \
	554	tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; \
	555	udelay(10); \
	556	} while (head != tail); \
	557	} while (0)
	558
	559
	560	/* function protoypes */
d024960c	561	extern int intelfbhw_get_chipset(struct pci_dev pdev, struct intelfb_info dinfo);
1da177e4 LT	562	extern int intelfbhw_get_memory(struct pci_dev pdev, int aperture_size,
	563	int *stolen_size);
	564	extern int intelfbhw_check_non_crt(struct intelfb_info *dinfo);
	565	extern const char *intelfbhw_dvo_to_string(int dvo);
	566	extern int intelfbhw_validate_mode(struct intelfb_info *dinfo,
	567	struct fb_var_screeninfo *var);
	568	extern int intelfbhw_pan_display(struct fb_var_screeninfo *var,
	569	struct fb_info *info);
	570	extern void intelfbhw_do_blank(int blank, struct fb_info *info);
	571	extern void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
	572	unsigned red, unsigned green, unsigned blue,
	573	unsigned transp);
	574	extern int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
	575	struct intelfb_hwstate *hw, int flag);
	576	extern void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
	577	struct intelfb_hwstate *hw);
	578	extern int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
	579	struct intelfb_hwstate *hw,
	580	struct fb_var_screeninfo *var);
	581	extern int intelfbhw_program_mode(struct intelfb_info *dinfo,
	582	const struct intelfb_hwstate *hw, int blank);
	583	extern void intelfbhw_do_sync(struct intelfb_info *dinfo);
	584	extern void intelfbhw_2d_stop(struct intelfb_info *dinfo);
	585	extern void intelfbhw_2d_start(struct intelfb_info *dinfo);
	586	extern void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y,
	587	u32 w, u32 h, u32 color, u32 pitch, u32 bpp,
	588	u32 rop);
	589	extern void intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
	590	u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch,
	591	u32 bpp);
	592	extern int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg,
	593	u32 w, u32 h, const u8* cdat, u32 x, u32 y,
	594	u32 pitch, u32 bpp);
	595	extern void intelfbhw_cursor_init(struct intelfb_info *dinfo);
	596	extern void intelfbhw_cursor_hide(struct intelfb_info *dinfo);
	597	extern void intelfbhw_cursor_show(struct intelfb_info *dinfo);
	598	extern void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y);
	599	extern void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg,
	600	u32 fg);
	601	extern void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width,
	602	int height, u8 *data);
	603	extern void intelfbhw_cursor_reset(struct intelfb_info *dinfo);
394d3af7	604	extern int intelfbhw_enable_irq(struct intelfb_info *dinfo);
7649757b	605	extern void intelfbhw_disable_irq(struct intelfb_info *dinfo);
37bced38	606	extern int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe);
cfbd646f	607	extern int intelfbhw_active_pipe(const struct intelfb_hwstate *hw);
1da177e4 LT	608
1da177e4 LT	609	#endif /* _INTELFBHW_H */