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Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[deliverable/linux.git] / drivers / video / mb862xx / mb862xxfbdrv.c
CommitLineData
17a1217e
AG		 1/*
2 * drivers/mb862xx/mb862xxfb.c
3 *
4 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
5 *
6 * (C) 2008 Anatolij Gustschin <agust@denx.de>
7 * DENX Software Engineering
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#undef DEBUG
16
17#include <linux/fb.h>
18#include <linux/delay.h>
15f82d1b 19#include <linux/uaccess.h>
355b200b 20#include <linux/module.h>
17a1217e
AG		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24f01dcb 24#if defined(CONFIG_OF)
17a1217e
AG		 25#include <linux/of_platform.h>
26#endif
27#include "mb862xxfb.h"
28#include "mb862xx_reg.h"
29
30#define NR_PALETTE 256
31#define MB862XX_MEM_SIZE 0x1000000
f64d8a5f 32#define CORALP_MEM_SIZE 0x2000000
17a1217e
AG		 33#define CARMINE_MEM_SIZE 0x8000000
34#define DRV_NAME "mb862xxfb"
35
17a1217e
AG		 36#if defined(CONFIG_SOCRATES)
37static struct mb862xx_gc_mode socrates_gc_mode = {
38 /* Mode for Prime View PM070WL4 TFT LCD Panel */
39 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
40 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
41 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
42};
43#endif
44
45/* Helpers */
46static inline int h_total(struct fb_var_screeninfo *var)
47{
48 return var->xres + var->left_margin +
49 var->right_margin + var->hsync_len;
50}
51
52static inline int v_total(struct fb_var_screeninfo *var)
53{
54 return var->yres + var->upper_margin +
55 var->lower_margin + var->vsync_len;
56}
57
58static inline int hsp(struct fb_var_screeninfo *var)
59{
60 return var->xres + var->right_margin - 1;
61}
62
63static inline int vsp(struct fb_var_screeninfo *var)
64{
65 return var->yres + var->lower_margin - 1;
66}
67
68static inline int d_pitch(struct fb_var_screeninfo *var)
69{
70 return var->xres * var->bits_per_pixel / 8;
71}
72
73static inline unsigned int chan_to_field(unsigned int chan,
74 struct fb_bitfield *bf)
75{
76 chan &= 0xffff;
77 chan >>= 16 - bf->length;
78 return chan << bf->offset;
79}
80
81static int mb862xxfb_setcolreg(unsigned regno,
82 unsigned red, unsigned green, unsigned blue,
83 unsigned transp, struct fb_info *info)
84{
85 struct mb862xxfb_par *par = info->par;
86 unsigned int val;
87
88 switch (info->fix.visual) {
89 case FB_VISUAL_TRUECOLOR:
90 if (regno < 16) {
91 val = chan_to_field(red, &info->var.red);
92 val |= chan_to_field(green, &info->var.green);
93 val |= chan_to_field(blue, &info->var.blue);
94 par->pseudo_palette[regno] = val;
95 }
96 break;
97 case FB_VISUAL_PSEUDOCOLOR:
98 if (regno < 256) {
99 val = (red >> 8) << 16;
100 val |= (green >> 8) << 8;
101 val |= blue >> 8;
102 outreg(disp, GC_L0PAL0 + (regno * 4), val);
103 }
104 break;
105 default:
106 return 1; /* unsupported type */
107 }
108 return 0;
109}
110
111static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
112 struct fb_info *fbi)
113{
114 unsigned long tmp;
115
116 if (fbi->dev)
117 dev_dbg(fbi->dev, "%s\n", __func__);
118
119 /* check if these values fit into the registers */
120 if (var->hsync_len > 255 || var->vsync_len > 255)
121 return -EINVAL;
122
123 if ((var->xres + var->right_margin) >= 4096)
124 return -EINVAL;
125
126 if ((var->yres + var->lower_margin) > 4096)
127 return -EINVAL;
128
129 if (h_total(var) > 4096 || v_total(var) > 4096)
130 return -EINVAL;
131
132 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
133 return -EINVAL;
134
135 if (var->bits_per_pixel <= 8)
136 var->bits_per_pixel = 8;
137 else if (var->bits_per_pixel <= 16)
138 var->bits_per_pixel = 16;
139 else if (var->bits_per_pixel <= 32)
140 var->bits_per_pixel = 32;
141
142 /*
143 * can cope with 8,16 or 24/32bpp if resulting
144 * pitch is divisible by 64 without remainder
145 */
146 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
147 int r;
148
149 var->bits_per_pixel = 0;
150 do {
151 var->bits_per_pixel += 8;
152 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
153 } while (r && var->bits_per_pixel <= 32);
154
155 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
156 return -EINVAL;
157 }
158
159 /* line length is going to be 128 bit aligned */
160 tmp = (var->xres * var->bits_per_pixel) / 8;
161 if ((tmp & 15) != 0)
162 return -EINVAL;
163
164 /* set r/g/b positions and validate bpp */
165 switch (var->bits_per_pixel) {
166 case 8:
167 var->red.length = var->bits_per_pixel;
168 var->green.length = var->bits_per_pixel;
169 var->blue.length = var->bits_per_pixel;
170 var->red.offset = 0;
171 var->green.offset = 0;
172 var->blue.offset = 0;
173 var->transp.length = 0;
174 break;
175 case 16:
176 var->red.length = 5;
177 var->green.length = 5;
178 var->blue.length = 5;
179 var->red.offset = 10;
180 var->green.offset = 5;
181 var->blue.offset = 0;
182 var->transp.length = 0;
183 break;
184 case 24:
185 case 32:
186 var->transp.length = 8;
187 var->red.length = 8;
188 var->green.length = 8;
189 var->blue.length = 8;
190 var->transp.offset = 24;
191 var->red.offset = 16;
192 var->green.offset = 8;
193 var->blue.offset = 0;
194 break;
195 default:
196 return -EINVAL;
197 }
198 return 0;
199}
200
201/*
202 * set display parameters
203 */
204static int mb862xxfb_set_par(struct fb_info *fbi)
205{
206 struct mb862xxfb_par *par = fbi->par;
207 unsigned long reg, sc;
208
209 dev_dbg(par->dev, "%s\n", __func__);
2ec509b9
VS		 210 if (par->type == BT_CORALP)
211 mb862xxfb_init_accel(fbi, fbi->var.xres);
17a1217e
AG		 212
213 if (par->pre_init)
214 return 0;
215
216 /* disp off */
217 reg = inreg(disp, GC_DCM1);
218 reg &= ~GC_DCM01_DEN;
219 outreg(disp, GC_DCM1, reg);
220
221 /* set display reference clock div. */
222 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
223 reg = inreg(disp, GC_DCM1);
224 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
225 reg |= sc << 8;
226 outreg(disp, GC_DCM1, reg);
227 dev_dbg(par->dev, "SC 0x%lx\n", sc);
228
229 /* disp dimension, format */
230 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
231 (fbi->var.yres - 1));
232 if (fbi->var.bits_per_pixel == 16)
233 reg |= GC_L0M_L0C_16;
234 outreg(disp, GC_L0M, reg);
235
236 if (fbi->var.bits_per_pixel == 32) {
237 reg = inreg(disp, GC_L0EM);
238 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
239 }
240 outreg(disp, GC_WY_WX, 0);
241 reg = pack(fbi->var.yres - 1, fbi->var.xres);
242 outreg(disp, GC_WH_WW, reg);
243 outreg(disp, GC_L0OA0, 0);
244 outreg(disp, GC_L0DA0, 0);
245 outreg(disp, GC_L0DY_L0DX, 0);
246 outreg(disp, GC_L0WY_L0WX, 0);
247 outreg(disp, GC_L0WH_L0WW, reg);
248
249 /* both HW-cursors off */
250 reg = inreg(disp, GC_CPM_CUTC);
251 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
252 outreg(disp, GC_CPM_CUTC, reg);
253
254 /* timings */
255 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
256 outreg(disp, GC_HDB_HDP, reg);
257 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
258 outreg(disp, GC_VDP_VSP, reg);
259 reg = ((fbi->var.vsync_len - 1) << 24) |
260 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
261 outreg(disp, GC_VSW_HSW_HSP, reg);
262 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
263 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
264
265 /* display on */
266 reg = inreg(disp, GC_DCM1);
267 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
268 reg &= ~GC_DCM01_ESY;
269 outreg(disp, GC_DCM1, reg);
270 return 0;
271}
272
273static int mb862xxfb_pan(struct fb_var_screeninfo *var,
274 struct fb_info *info)
275{
276 struct mb862xxfb_par *par = info->par;
277 unsigned long reg;
278
279 reg = pack(var->yoffset, var->xoffset);
280 outreg(disp, GC_L0WY_L0WX, reg);
281
23dc8b1c 282 reg = pack(info->var.yres_virtual, info->var.xres_virtual);
17a1217e
AG		 283 outreg(disp, GC_L0WH_L0WW, reg);
284 return 0;
285}
286
287static int mb862xxfb_blank(int mode, struct fb_info *fbi)
288{
289 struct mb862xxfb_par *par = fbi->par;
290 unsigned long reg;
291
292 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
293
294 switch (mode) {
295 case FB_BLANK_POWERDOWN:
296 reg = inreg(disp, GC_DCM1);
297 reg &= ~GC_DCM01_DEN;
298 outreg(disp, GC_DCM1, reg);
299 break;
300 case FB_BLANK_UNBLANK:
301 reg = inreg(disp, GC_DCM1);
302 reg |= GC_DCM01_DEN;
303 outreg(disp, GC_DCM1, reg);
304 break;
305 case FB_BLANK_NORMAL:
306 case FB_BLANK_VSYNC_SUSPEND:
307 case FB_BLANK_HSYNC_SUSPEND:
308 default:
309 return 1;
310 }
311 return 0;
312}
313
f64d8a5f
AG		 314static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
315 unsigned long arg)
316{
317 struct mb862xxfb_par *par = fbi->par;
318 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
319 void __user *argp = (void __user *)arg;
320 int *enable;
321 u32 l1em = 0;
322
323 switch (cmd) {
324 case MB862XX_L1_GET_CFG:
325 if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
326 return -EFAULT;
327 break;
328 case MB862XX_L1_SET_CFG:
329 if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
330 return -EFAULT;
25682362
DC		 331 if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
332 return -EINVAL;
f64d8a5f
AG		 333 if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
334 /* downscaling */
335 outreg(cap, GC_CAP_CSC,
336 pack((l1_cfg->sh << 11) / l1_cfg->dh,
337 (l1_cfg->sw << 11) / l1_cfg->dw));
338 l1em = inreg(disp, GC_L1EM);
339 l1em &= ~GC_L1EM_DM;
340 } else if ((l1_cfg->sw <= l1_cfg->dw) &&
341 (l1_cfg->sh <= l1_cfg->dh)) {
342 /* upscaling */
343 outreg(cap, GC_CAP_CSC,
344 pack((l1_cfg->sh << 11) / l1_cfg->dh,
345 (l1_cfg->sw << 11) / l1_cfg->dw));
346 outreg(cap, GC_CAP_CMSS,
347 pack(l1_cfg->sw >> 1, l1_cfg->sh));
348 outreg(cap, GC_CAP_CMDS,
349 pack(l1_cfg->dw >> 1, l1_cfg->dh));
350 l1em = inreg(disp, GC_L1EM);
351 l1em |= GC_L1EM_DM;
352 }
353
354 if (l1_cfg->mirror) {
355 outreg(cap, GC_CAP_CBM,
356 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
357 l1em |= l1_cfg->dw * 2 - 8;
358 } else {
359 outreg(cap, GC_CAP_CBM,
360 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
361 l1em &= 0xffff0000;
362 }
363 outreg(disp, GC_L1EM, l1em);
364 break;
365 case MB862XX_L1_ENABLE:
366 enable = (int *)arg;
367 if (*enable) {
368 outreg(disp, GC_L1DA, par->cap_buf);
369 outreg(cap, GC_CAP_IMG_START,
370 pack(l1_cfg->sy >> 1, l1_cfg->sx));
371 outreg(cap, GC_CAP_IMG_END,
372 pack(l1_cfg->sh, l1_cfg->sw));
373 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
374 (par->l1_stride << 16));
375 outreg(disp, GC_L1WY_L1WX,
376 pack(l1_cfg->dy, l1_cfg->dx));
377 outreg(disp, GC_L1WH_L1WW,
378 pack(l1_cfg->dh - 1, l1_cfg->dw));
379 outreg(disp, GC_DLS, 1);
380 outreg(cap, GC_CAP_VCM,
381 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
382 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
383 GC_DCM1_DEN | GC_DCM1_L1E);
384 } else {
385 outreg(cap, GC_CAP_VCM,
386 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
387 outreg(disp, GC_DCM1,
388 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
389 }
390 break;
391 case MB862XX_L1_CAP_CTL:
392 enable = (int *)arg;
393 if (*enable) {
394 outreg(cap, GC_CAP_VCM,
395 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
396 } else {
397 outreg(cap, GC_CAP_VCM,
398 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
399 }
400 break;
401 default:
402 return -EINVAL;
403 }
404 return 0;
405}
406
17a1217e
AG		 407/* framebuffer ops */
408static struct fb_ops mb862xxfb_ops = {
409 .owner = THIS_MODULE,
410 .fb_check_var = mb862xxfb_check_var,
411 .fb_set_par = mb862xxfb_set_par,
412 .fb_setcolreg = mb862xxfb_setcolreg,
413 .fb_blank = mb862xxfb_blank,
414 .fb_pan_display = mb862xxfb_pan,
415 .fb_fillrect = cfb_fillrect,
416 .fb_copyarea = cfb_copyarea,
417 .fb_imageblit = cfb_imageblit,
f64d8a5f 418 .fb_ioctl = mb862xxfb_ioctl,
17a1217e
AG		 419};
420
421/* initialize fb_info data */
422static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
423{
424 struct mb862xxfb_par *par = fbi->par;
425 struct mb862xx_gc_mode *mode = par->gc_mode;
426 unsigned long reg;
f64d8a5f 427 int stride;
17a1217e
AG		 428
429 fbi->fbops = &mb862xxfb_ops;
430 fbi->pseudo_palette = par->pseudo_palette;
431 fbi->screen_base = par->fb_base;
432 fbi->screen_size = par->mapped_vram;
433
434 strcpy(fbi->fix.id, DRV_NAME);
435 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
17a1217e
AG		 436 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
437 fbi->fix.mmio_len = par->mmio_len;
438 fbi->fix.accel = FB_ACCEL_NONE;
439 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
440 fbi->fix.type_aux = 0;
441 fbi->fix.xpanstep = 1;
442 fbi->fix.ypanstep = 1;
443 fbi->fix.ywrapstep = 0;
444
445 reg = inreg(disp, GC_DCM1);
446 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
447 /* get the disp mode from active display cfg */
448 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
449 unsigned long hsp, vsp, ht, vt;
450
451 dev_dbg(par->dev, "using bootloader's disp. mode\n");
452 fbi->var.pixclock = (sc * 1000000) / par->refclk;
453 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
454 reg = inreg(disp, GC_VDP_VSP);
455 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
456 vsp = (reg & 0x0fff) + 1;
457 fbi->var.xres_virtual = fbi->var.xres;
458 fbi->var.yres_virtual = fbi->var.yres;
459 reg = inreg(disp, GC_L0EM);
460 if (reg & GC_L0EM_L0EC_24) {
461 fbi->var.bits_per_pixel = 32;
462 } else {
463 reg = inreg(disp, GC_L0M);
464 if (reg & GC_L0M_L0C_16)
465 fbi->var.bits_per_pixel = 16;
466 else
467 fbi->var.bits_per_pixel = 8;
468 }
469 reg = inreg(disp, GC_VSW_HSW_HSP);
470 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
471 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
472 hsp = (reg & 0xffff) + 1;
473 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
474 fbi->var.right_margin = hsp - fbi->var.xres;
475 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
476 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
477 fbi->var.lower_margin = vsp - fbi->var.yres;
478 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
479 } else if (mode) {
480 dev_dbg(par->dev, "using supplied mode\n");
481 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
482 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
483 } else {
484 int ret;
485
486 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
487 NULL, 0, NULL, 16);
488 if (ret == 0 || ret == 4) {
489 dev_err(par->dev,
490 "failed to get initial mode\n");
491 return -EINVAL;
492 }
493 }
494
495 fbi->var.xoffset = 0;
496 fbi->var.yoffset = 0;
497 fbi->var.grayscale = 0;
498 fbi->var.nonstd = 0;
499 fbi->var.height = -1;
500 fbi->var.width = -1;
501 fbi->var.accel_flags = 0;
502 fbi->var.vmode = FB_VMODE_NONINTERLACED;
503 fbi->var.activate = FB_ACTIVATE_NOW;
504 fbi->flags = FBINFO_DEFAULT |
505#ifdef __BIG_ENDIAN
506 FBINFO_FOREIGN_ENDIAN |
507#endif
508 FBINFO_HWACCEL_XPAN |
509 FBINFO_HWACCEL_YPAN;
510
511 /* check and possibly fix bpp */
512 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
513 dev_err(par->dev, "check_var() failed on initial setup?\n");
514
515 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
516 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
517 fbi->fix.line_length = (fbi->var.xres_virtual *
518 fbi->var.bits_per_pixel) / 8;
dcdf2f7e 519 fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
f64d8a5f
AG		 520
521 /*
522 * reserve space for capture buffers and two cursors
523 * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
524 */
525 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
526 par->cap_len = 0x1bd800;
527 par->l1_cfg.sx = 0;
528 par->l1_cfg.sy = 0;
529 par->l1_cfg.sw = 720;
530 par->l1_cfg.sh = 576;
531 par->l1_cfg.dx = 0;
532 par->l1_cfg.dy = 0;
533 par->l1_cfg.dw = 720;
534 par->l1_cfg.dh = 576;
535 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
536 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
537 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
538 (par->l1_stride << 16));
539 outreg(cap, GC_CAP_CBOA, par->cap_buf);
540 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
17a1217e
AG		 541 return 0;
542}
543
544/*
545 * show some display controller and cursor registers
546 */
547static ssize_t mb862xxfb_show_dispregs(struct device *dev,
548 struct device_attribute *attr, char *buf)
549{
550 struct fb_info *fbi = dev_get_drvdata(dev);
551 struct mb862xxfb_par *par = fbi->par;
552 char *ptr = buf;
553 unsigned int reg;
554
555 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
556 ptr += sprintf(ptr, "%08x = %08x\n",
557 reg, inreg(disp, reg));
558
559 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
560 ptr += sprintf(ptr, "%08x = %08x\n",
561 reg, inreg(disp, reg));
562
563 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
564 ptr += sprintf(ptr, "%08x = %08x\n",
565 reg, inreg(disp, reg));
566
2ec509b9
VS		 567 for (reg = 0x400; reg <= 0x410; reg += 4)
568 ptr += sprintf(ptr, "geo %08x = %08x\n",
569 reg, inreg(geo, reg));
570
571 for (reg = 0x400; reg <= 0x410; reg += 4)
572 ptr += sprintf(ptr, "draw %08x = %08x\n",
573 reg, inreg(draw, reg));
574
575 for (reg = 0x440; reg <= 0x450; reg += 4)
576 ptr += sprintf(ptr, "draw %08x = %08x\n",
577 reg, inreg(draw, reg));
578
17a1217e
AG		 579 return ptr - buf;
580}
581
582static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
583
b71b7633 584static irqreturn_t mb862xx_intr(int irq, void *dev_id)
17a1217e
AG		 585{
586 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
587 unsigned long reg_ist, mask;
588
589 if (!par)
590 return IRQ_NONE;
591
592 if (par->type == BT_CARMINE) {
593 /* Get Interrupt Status */
594 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
595 mask = inreg(ctrl, GC_CTRL_INT_MASK);
596 if (reg_ist == 0)
597 return IRQ_HANDLED;
598
599 reg_ist &= mask;
600 if (reg_ist == 0)
601 return IRQ_HANDLED;
602
603 /* Clear interrupt status */
604 outreg(ctrl, 0x0, reg_ist);
605 } else {
606 /* Get status */
607 reg_ist = inreg(host, GC_IST);
608 mask = inreg(host, GC_IMASK);
609
610 reg_ist &= mask;
611 if (reg_ist == 0)
612 return IRQ_HANDLED;
613
614 /* Clear status */
615 outreg(host, GC_IST, ~reg_ist);
616 }
617 return IRQ_HANDLED;
618}
619
620#if defined(CONFIG_FB_MB862XX_LIME)
621/*
622 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
623 */
624static int mb862xx_gdc_init(struct mb862xxfb_par *par)
625{
626 unsigned long ccf, mmr;
627 unsigned long ver, rev;
628
629 if (!par)
630 return -ENODEV;
631
632#if defined(CONFIG_FB_PRE_INIT_FB)
633 par->pre_init = 1;
634#endif
635 par->host = par->mmio_base;
636 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
637 par->disp = par->mmio_base + MB862XX_DISP_BASE;
638 par->cap = par->mmio_base + MB862XX_CAP_BASE;
639 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
640 par->geo = par->mmio_base + MB862XX_GEO_BASE;
641 par->pio = par->mmio_base + MB862XX_PIO_BASE;
642
643 par->refclk = GC_DISP_REFCLK_400;
644
645 ver = inreg(host, GC_CID);
646 rev = inreg(pio, GC_REVISION);
647 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
648 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
649 (int)rev & 0xff);
650 par->type = BT_LIME;
651 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
652 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
653 } else {
654 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
655 return -ENODEV;
656 }
657
658 if (!par->pre_init) {
659 outreg(host, GC_CCF, ccf);
660 udelay(200);
661 outreg(host, GC_MMR, mmr);
662 udelay(10);
663 }
664
665 /* interrupt status */
666 outreg(host, GC_IST, 0);
667 outreg(host, GC_IMASK, GC_INT_EN);
668 return 0;
669}
670
28541d0f 671static int __devinit of_platform_mb862xx_probe(struct platform_device *ofdev)
17a1217e 672{
d4b8b2c2 673 struct device_node *np = ofdev->dev.of_node;
17a1217e
AG		 674 struct device *dev = &ofdev->dev;
675 struct mb862xxfb_par *par;
676 struct fb_info *info;
677 struct resource res;
678 resource_size_t res_size;
679 unsigned long ret = -ENODEV;
680
681 if (of_address_to_resource(np, 0, &res)) {
682 dev_err(dev, "Invalid address\n");
683 return -ENXIO;
684 }
685
686 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
687 if (info == NULL) {
688 dev_err(dev, "cannot allocate framebuffer\n");
689 return -ENOMEM;
690 }
691
692 par = info->par;
693 par->info = info;
694 par->dev = dev;
695
696 par->irq = irq_of_parse_and_map(np, 0);
697 if (par->irq == NO_IRQ) {
698 dev_err(dev, "failed to map irq\n");
699 ret = -ENODEV;
700 goto fbrel;
701 }
702
28f65c11 703 res_size = resource_size(&res);
17a1217e
AG		 704 par->res = request_mem_region(res.start, res_size, DRV_NAME);
705 if (par->res == NULL) {
706 dev_err(dev, "Cannot claim framebuffer/mmio\n");
707 ret = -ENXIO;
708 goto irqdisp;
709 }
710
17a1217e
AG		 711#if defined(CONFIG_SOCRATES)
712 par->gc_mode = &socrates_gc_mode;
713#endif
714
715 par->fb_base_phys = res.start;
716 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
717 par->mmio_len = MB862XX_MMIO_SIZE;
718 if (par->gc_mode)
719 par->mapped_vram = par->gc_mode->max_vram;
720 else
721 par->mapped_vram = MB862XX_MEM_SIZE;
722
723 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
724 if (par->fb_base == NULL) {
725 dev_err(dev, "Cannot map framebuffer\n");
726 goto rel_reg;
727 }
728
729 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
730 if (par->mmio_base == NULL) {
731 dev_err(dev, "Cannot map registers\n");
732 goto fb_unmap;
733 }
734
735 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
736 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
737 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
738 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
739
740 if (mb862xx_gdc_init(par))
741 goto io_unmap;
742
f8798ccb 743 if (request_irq(par->irq, mb862xx_intr, 0,
17a1217e
AG		 744 DRV_NAME, (void *)par)) {
745 dev_err(dev, "Cannot request irq\n");
746 goto io_unmap;
747 }
748
749 mb862xxfb_init_fbinfo(info);
750
751 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
752 dev_err(dev, "Could not allocate cmap for fb_info.\n");
753 goto free_irq;
754 }
755
756 if ((info->fbops->fb_set_par)(info))
757 dev_err(dev, "set_var() failed on initial setup?\n");
758
759 if (register_framebuffer(info)) {
760 dev_err(dev, "failed to register framebuffer\n");
761 goto rel_cmap;
762 }
763
764 dev_set_drvdata(dev, info);
765
766 if (device_create_file(dev, &dev_attr_dispregs))
767 dev_err(dev, "Can't create sysfs regdump file\n");
768 return 0;
769
770rel_cmap:
771 fb_dealloc_cmap(&info->cmap);
772free_irq:
773 outreg(host, GC_IMASK, 0);
774 free_irq(par->irq, (void *)par);
775io_unmap:
776 iounmap(par->mmio_base);
777fb_unmap:
778 iounmap(par->fb_base);
779rel_reg:
780 release_mem_region(res.start, res_size);
781irqdisp:
782 irq_dispose_mapping(par->irq);
783fbrel:
784 dev_set_drvdata(dev, NULL);
785 framebuffer_release(info);
786 return ret;
787}
788
2dc11581 789static int __devexit of_platform_mb862xx_remove(struct platform_device *ofdev)
17a1217e
AG		 790{
791 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
792 struct mb862xxfb_par *par = fbi->par;
28f65c11 793 resource_size_t res_size = resource_size(par->res);
17a1217e
AG		 794 unsigned long reg;
795
796 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
797
798 /* display off */
799 reg = inreg(disp, GC_DCM1);
800 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
801 outreg(disp, GC_DCM1, reg);
802
803 /* disable interrupts */
804 outreg(host, GC_IMASK, 0);
805
806 free_irq(par->irq, (void *)par);
807 irq_dispose_mapping(par->irq);
808
809 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
810
811 unregister_framebuffer(fbi);
812 fb_dealloc_cmap(&fbi->cmap);
813
814 iounmap(par->mmio_base);
815 iounmap(par->fb_base);
816
817 dev_set_drvdata(&ofdev->dev, NULL);
818 release_mem_region(par->res->start, res_size);
819 framebuffer_release(fbi);
820 return 0;
821}
822
823/*
824 * common types
825 */
826static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = {
827 { .compatible = "fujitsu,MB86276", },
828 { .compatible = "fujitsu,lime", },
829 { .compatible = "fujitsu,MB86277", },
830 { .compatible = "fujitsu,mint", },
831 { .compatible = "fujitsu,MB86293", },
832 { .compatible = "fujitsu,MB86294", },
833 { .compatible = "fujitsu,coral", },
834 { /* end */ }
835};
836
28541d0f 837static struct platform_driver of_platform_mb862xxfb_driver = {
4018294b
GL		 838 .driver = {
839 .name = DRV_NAME,
840 .owner = THIS_MODULE,
841 .of_match_table = of_platform_mb862xx_tbl,
842 },
17a1217e
AG		 843 .probe = of_platform_mb862xx_probe,
844 .remove = __devexit_p(of_platform_mb862xx_remove),
845};
846#endif
847
848#if defined(CONFIG_FB_MB862XX_PCI_GDC)
849static int coralp_init(struct mb862xxfb_par *par)
850{
851 int cn, ver;
852
853 par->host = par->mmio_base;
854 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
855 par->disp = par->mmio_base + MB862XX_DISP_BASE;
856 par->cap = par->mmio_base + MB862XX_CAP_BASE;
857 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
858 par->geo = par->mmio_base + MB862XX_GEO_BASE;
859 par->pio = par->mmio_base + MB862XX_PIO_BASE;
860
861 par->refclk = GC_DISP_REFCLK_400;
862
12ed0c4b
AG		 863 if (par->mapped_vram >= 0x2000000) {
864 /* relocate gdc registers space */
865 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
866 udelay(1); /* wait at least 20 bus cycles */
867 }
868
17a1217e
AG		 869 ver = inreg(host, GC_CID);
870 cn = (ver & GC_CID_CNAME_MSK) >> 8;
871 ver = ver & GC_CID_VERSION_MSK;
872 if (cn == 3) {
3cadf945
AG		 873 unsigned long reg;
874
17a1217e
AG		 875 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
876 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
877 par->pdev->revision);
3cadf945
AG		 878 reg = inreg(disp, GC_DCM1);
879 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
880 par->pre_init = 1;
881
882 if (!par->pre_init) {
883 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
884 udelay(200);
885 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
886 udelay(10);
887 }
17a1217e
AG		 888 /* Clear interrupt status */
889 outreg(host, GC_IST, 0);
890 } else {
891 return -ENODEV;
892 }
f8a6b1f4
AG		 893
894 mb862xx_i2c_init(par);
17a1217e
AG		 895 return 0;
896}
897
898static int init_dram_ctrl(struct mb862xxfb_par *par)
899{
900 unsigned long i = 0;
901
902 /*
903 * Set io mode first! Spec. says IC may be destroyed
904 * if not set to SSTL2/LVCMOS before init.
905 */
906 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
907
908 /* DRAM init */
909 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
910 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
911 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
912 GC_EVB_DCTL_REFRESH_SETTIME2);
913 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
914 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
915 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
916
917 /* DLL reset done? */
918 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
919 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
920 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
921 dev_err(par->dev, "VRAM init failed.\n");
922 return -EINVAL;
923 }
924 }
925 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
926 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
927 return 0;
928}
929
930static int carmine_init(struct mb862xxfb_par *par)
931{
932 unsigned long reg;
933
934 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
935 par->i2c = par->mmio_base + MB86297_I2C_BASE;
936 par->disp = par->mmio_base + MB86297_DISP0_BASE;
937 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
938 par->cap = par->mmio_base + MB86297_CAP0_BASE;
939 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
940 par->draw = par->mmio_base + MB86297_DRAW_BASE;
941 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
942 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
943
944 par->refclk = GC_DISP_REFCLK_533;
945
946 /* warm up */
947 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
948 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
949
950 /* check for engine module revision */
951 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
952 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
953 par->pdev->revision);
954 else
955 goto err_init;
956
957 reg &= ~GC_CTRL_CLK_EN_2D3D;
958 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
959
960 /* set up vram */
961 if (init_dram_ctrl(par) < 0)
962 goto err_init;
963
964 outreg(ctrl, GC_CTRL_INT_MASK, 0);
965 return 0;
966
967err_init:
968 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
969 return -EINVAL;
970}
971
972static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
973{
974 switch (par->type) {
975 case BT_CORALP:
976 return coralp_init(par);
977 case BT_CARMINE:
978 return carmine_init(par);
979 default:
980 return -ENODEV;
981 }
982}
983
984#define CHIP_ID(id) \
985 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
986
987static struct pci_device_id mb862xx_pci_tbl[] __devinitdata = {
988 /* MB86295/MB86296 */
989 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
990 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
991 /* MB86297 */
992 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
993 { 0, }
994};
995
996MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
997
998static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
999 const struct pci_device_id *ent)
1000{
1001 struct mb862xxfb_par *par;
1002 struct fb_info *info;
1003 struct device *dev = &pdev->dev;
1004 int ret;
1005
1006 ret = pci_enable_device(pdev);
1007 if (ret < 0) {
1008 dev_err(dev, "Cannot enable PCI device\n");
1009 goto out;
1010 }
1011
1012 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
1013 if (!info) {
1014 dev_err(dev, "framebuffer alloc failed\n");
1015 ret = -ENOMEM;
1016 goto dis_dev;
1017 }
1018
1019 par = info->par;
1020 par->info = info;
1021 par->dev = dev;
1022 par->pdev = pdev;
1023 par->irq = pdev->irq;
1024
1025 ret = pci_request_regions(pdev, DRV_NAME);
1026 if (ret < 0) {
1027 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
1028 goto rel_fb;
1029 }
1030
1031 switch (pdev->device) {
1032 case PCI_DEVICE_ID_FUJITSU_CORALP:
1033 case PCI_DEVICE_ID_FUJITSU_CORALPA:
1034 par->fb_base_phys = pci_resource_start(par->pdev, 0);
1035 par->mapped_vram = CORALP_MEM_SIZE;
12ed0c4b
AG		 1036 if (par->mapped_vram >= 0x2000000) {
1037 par->mmio_base_phys = par->fb_base_phys +
1038 MB862XX_MMIO_HIGH_BASE;
1039 } else {
1040 par->mmio_base_phys = par->fb_base_phys +
1041 MB862XX_MMIO_BASE;
1042 }
17a1217e
AG		 1043 par->mmio_len = MB862XX_MMIO_SIZE;
1044 par->type = BT_CORALP;
1045 break;
1046 case PCI_DEVICE_ID_FUJITSU_CARMINE:
1047 par->fb_base_phys = pci_resource_start(par->pdev, 2);
1048 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1049 par->mmio_len = pci_resource_len(par->pdev, 3);
1050 par->mapped_vram = CARMINE_MEM_SIZE;
1051 par->type = BT_CARMINE;
1052 break;
1053 default:
1054 /* should never occur */
1055 goto rel_reg;
1056 }
1057
1058 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1059 if (par->fb_base == NULL) {
1060 dev_err(dev, "Cannot map framebuffer\n");
1061 goto rel_reg;
1062 }
1063
1064 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1065 if (par->mmio_base == NULL) {
1066 dev_err(dev, "Cannot map registers\n");
1067 ret = -EIO;
1068 goto fb_unmap;
1069 }
1070
1071 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
c1ab6cc6 1072 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
17a1217e 1073 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
c1ab6cc6 1074 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
17a1217e
AG		 1075
1076 if (mb862xx_pci_gdc_init(par))
1077 goto io_unmap;
1078
f8798ccb 1079 if (request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
17a1217e
AG		 1080 DRV_NAME, (void *)par)) {
1081 dev_err(dev, "Cannot request irq\n");
1082 goto io_unmap;
1083 }
1084
1085 mb862xxfb_init_fbinfo(info);
1086
1087 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
1088 dev_err(dev, "Could not allocate cmap for fb_info.\n");
1089 ret = -ENOMEM;
1090 goto free_irq;
1091 }
1092
1093 if ((info->fbops->fb_set_par)(info))
1094 dev_err(dev, "set_var() failed on initial setup?\n");
1095
1096 ret = register_framebuffer(info);
1097 if (ret < 0) {
1098 dev_err(dev, "failed to register framebuffer\n");
1099 goto rel_cmap;
1100 }
1101
1102 pci_set_drvdata(pdev, info);
1103
1104 if (device_create_file(dev, &dev_attr_dispregs))
1105 dev_err(dev, "Can't create sysfs regdump file\n");
1106
1107 if (par->type == BT_CARMINE)
1108 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
1109 else
1110 outreg(host, GC_IMASK, GC_INT_EN);
1111
1112 return 0;
1113
1114rel_cmap:
1115 fb_dealloc_cmap(&info->cmap);
1116free_irq:
1117 free_irq(par->irq, (void *)par);
1118io_unmap:
1119 iounmap(par->mmio_base);
1120fb_unmap:
1121 iounmap(par->fb_base);
1122rel_reg:
1123 pci_release_regions(pdev);
1124rel_fb:
1125 framebuffer_release(info);
1126dis_dev:
1127 pci_disable_device(pdev);
1128out:
1129 return ret;
1130}
1131
1132static void __devexit mb862xx_pci_remove(struct pci_dev *pdev)
1133{
1134 struct fb_info *fbi = pci_get_drvdata(pdev);
1135 struct mb862xxfb_par *par = fbi->par;
1136 unsigned long reg;
1137
1138 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
1139
1140 /* display off */
1141 reg = inreg(disp, GC_DCM1);
1142 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1143 outreg(disp, GC_DCM1, reg);
1144
1145 if (par->type == BT_CARMINE) {
1146 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1147 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1148 } else {
1149 outreg(host, GC_IMASK, 0);
1150 }
1151
f8a6b1f4
AG		 1152 mb862xx_i2c_exit(par);
1153
17a1217e
AG		 1154 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1155
1156 pci_set_drvdata(pdev, NULL);
1157 unregister_framebuffer(fbi);
1158 fb_dealloc_cmap(&fbi->cmap);
1159
1160 free_irq(par->irq, (void *)par);
1161 iounmap(par->mmio_base);
1162 iounmap(par->fb_base);
1163
1164 pci_release_regions(pdev);
1165 framebuffer_release(fbi);
1166 pci_disable_device(pdev);
1167}
1168
1169static struct pci_driver mb862xxfb_pci_driver = {
1170 .name = DRV_NAME,
1171 .id_table = mb862xx_pci_tbl,
1172 .probe = mb862xx_pci_probe,
1173 .remove = __devexit_p(mb862xx_pci_remove),
1174};
1175#endif
1176
1177static int __devinit mb862xxfb_init(void)
1178{
1179 int ret = -ENODEV;
1180
1181#if defined(CONFIG_FB_MB862XX_LIME)
28541d0f 1182 ret = platform_driver_register(&of_platform_mb862xxfb_driver);
17a1217e
AG		 1183#endif
1184#if defined(CONFIG_FB_MB862XX_PCI_GDC)
1185 ret = pci_register_driver(&mb862xxfb_pci_driver);
1186#endif
1187 return ret;
1188}
1189
1190static void __exit mb862xxfb_exit(void)
1191{
1192#if defined(CONFIG_FB_MB862XX_LIME)
28541d0f 1193 platform_driver_unregister(&of_platform_mb862xxfb_driver);
17a1217e
AG		 1194#endif
1195#if defined(CONFIG_FB_MB862XX_PCI_GDC)
1196 pci_unregister_driver(&mb862xxfb_pci_driver);
1197#endif
1198}
1199
1200module_init(mb862xxfb_init);
1201module_exit(mb862xxfb_exit);
1202
1203MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1204MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1205MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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