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[PATCH] remove the broken FB_S3TRIO driver
[deliverable/linux.git] / drivers / video / neofb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/neofb.c -- NeoMagic Framebuffer Driver
3 *
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 *
6 *
7 * Card specific code is based on XFree86's neomagic driver.
8 * Framebuffer framework code is based on code of cyber2000fb.
9 *
10 * This file is subject to the terms and conditions of the GNU General
11 * Public License. See the file COPYING in the main directory of this
12 * archive for more details.
13 *
14 *
15 * 0.4.1
16 * - Cosmetic changes (dok)
17 *
18 * 0.4
19 * - Toshiba Libretto support, allow modes larger than LCD size if
20 * LCD is disabled, keep BIOS settings if internal/external display
21 * haven't been enabled explicitly
22 * (Thomas J. Moore <dark@mama.indstate.edu>)
23 *
24 * 0.3.3
25 * - Porting over to new fbdev api. (jsimmons)
26 *
27 * 0.3.2
28 * - got rid of all floating point (dok)
29 *
30 * 0.3.1
31 * - added module license (dok)
32 *
33 * 0.3
34 * - hardware accelerated clear and move for 2200 and above (dok)
35 * - maximum allowed dotclock is handled now (dok)
36 *
37 * 0.2.1
38 * - correct panning after X usage (dok)
39 * - added module and kernel parameters (dok)
40 * - no stretching if external display is enabled (dok)
41 *
42 * 0.2
43 * - initial version (dok)
44 *
45 *
46 * TODO
47 * - ioctl for internal/external switching
48 * - blanking
49 * - 32bit depth support, maybe impossible
50 * - disable pan-on-sync, need specs
51 *
52 * BUGS
53 * - white margin on bootup like with tdfxfb (colormap problem?)
54 *
55 */
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/kernel.h>
59#include <linux/errno.h>
60#include <linux/string.h>
61#include <linux/mm.h>
1da177e4
LT		 62#include <linux/slab.h>
63#include <linux/delay.h>
64#include <linux/fb.h>
65#include <linux/pci.h>
66#include <linux/init.h>
67#ifdef CONFIG_TOSHIBA
68#include <linux/toshiba.h>
1da177e4
LT		 69#endif
70
71#include <asm/io.h>
72#include <asm/irq.h>
73#include <asm/pgtable.h>
74#include <asm/system.h>
75#include <asm/uaccess.h>
76
77#ifdef CONFIG_MTRR
78#include <asm/mtrr.h>
79#endif
80
81#include <video/vga.h>
82#include <video/neomagic.h>
83
84#define NEOFB_VERSION "0.4.2"
85
86/* --------------------------------------------------------------------- */
87
88static int internal;
89static int external;
90static int libretto;
91static int nostretch;
92static int nopciburst;
93static char *mode_option __devinitdata = NULL;
94
95#ifdef MODULE
96
97MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@convergence.de>");
98MODULE_LICENSE("GPL");
99MODULE_DESCRIPTION("FBDev driver for NeoMagic PCI Chips");
100module_param(internal, bool, 0);
101MODULE_PARM_DESC(internal, "Enable output on internal LCD Display.");
102module_param(external, bool, 0);
103MODULE_PARM_DESC(external, "Enable output on external CRT.");
104module_param(libretto, bool, 0);
105MODULE_PARM_DESC(libretto, "Force Libretto 100/110 800x480 LCD.");
106module_param(nostretch, bool, 0);
107MODULE_PARM_DESC(nostretch,
108 "Disable stretching of modes smaller than LCD.");
109module_param(nopciburst, bool, 0);
110MODULE_PARM_DESC(nopciburst, "Disable PCI burst mode.");
111module_param(mode_option, charp, 0);
112MODULE_PARM_DESC(mode_option, "Preferred video mode ('640x480-8@60', etc)");
113
114#endif
115
116
117/* --------------------------------------------------------------------- */
118
119static biosMode bios8[] = {
120 {320, 240, 0x40},
121 {300, 400, 0x42},
122 {640, 400, 0x20},
123 {640, 480, 0x21},
124 {800, 600, 0x23},
125 {1024, 768, 0x25},
126};
127
128static biosMode bios16[] = {
129 {320, 200, 0x2e},
130 {320, 240, 0x41},
131 {300, 400, 0x43},
132 {640, 480, 0x31},
133 {800, 600, 0x34},
134 {1024, 768, 0x37},
135};
136
137static biosMode bios24[] = {
138 {640, 480, 0x32},
139 {800, 600, 0x35},
140 {1024, 768, 0x38}
141};
142
143#ifdef NO_32BIT_SUPPORT_YET
144/* FIXME: guessed values, wrong */
145static biosMode bios32[] = {
146 {640, 480, 0x33},
147 {800, 600, 0x36},
148 {1024, 768, 0x39}
149};
150#endif
151
152static inline void write_le32(int regindex, u32 val, const struct neofb_par *par)
153{
154 writel(val, par->neo2200 + par->cursorOff + regindex);
155}
156
157static int neoFindMode(int xres, int yres, int depth)
158{
159 int xres_s;
160 int i, size;
161 biosMode *mode;
162
163 switch (depth) {
164 case 8:
d1ae418e 165 size = ARRAY_SIZE(bios8);
1da177e4
LT		 166 mode = bios8;
167 break;
168 case 16:
d1ae418e 169 size = ARRAY_SIZE(bios16);
1da177e4
LT		 170 mode = bios16;
171 break;
172 case 24:
d1ae418e 173 size = ARRAY_SIZE(bios24);
1da177e4
LT		 174 mode = bios24;
175 break;
176#ifdef NO_32BIT_SUPPORT_YET
177 case 32:
d1ae418e 178 size = ARRAY_SIZE(bios32);
1da177e4
LT		 179 mode = bios32;
180 break;
181#endif
182 default:
183 return 0;
184 }
185
186 for (i = 0; i < size; i++) {
187 if (xres <= mode[i].x_res) {
188 xres_s = mode[i].x_res;
189 for (; i < size; i++) {
190 if (mode[i].x_res != xres_s)
191 return mode[i - 1].mode;
192 if (yres <= mode[i].y_res)
193 return mode[i].mode;
194 }
195 }
196 }
197 return mode[size - 1].mode;
198}
199
200/*
201 * neoCalcVCLK --
202 *
203 * Determine the closest clock frequency to the one requested.
204 */
205#define REF_FREQ 0xe517 /* 14.31818 in 20.12 fixed point */
206#define MAX_N 127
207#define MAX_D 31
208#define MAX_F 1
209
210static void neoCalcVCLK(const struct fb_info *info,
211 struct neofb_par *par, long freq)
212{
213 int n, d, f;
214 int n_best = 0, d_best = 0, f_best = 0;
215 long f_best_diff = (0x7ffff << 12); /* 20.12 */
216 long f_target = (freq << 12) / 1000; /* 20.12 */
217
218 for (f = 0; f <= MAX_F; f++)
219 for (n = 0; n <= MAX_N; n++)
220 for (d = 0; d <= MAX_D; d++) {
221 long f_out; /* 20.12 */
222 long f_diff; /* 20.12 */
223
224 f_out =
225 ((((n + 1) << 12) / ((d +
226 1) *
227 (1 << f))) >> 12)
228 * REF_FREQ;
229 f_diff = abs(f_out - f_target);
230 if (f_diff < f_best_diff) {
231 f_best_diff = f_diff;
232 n_best = n;
233 d_best = d;
234 f_best = f;
235 }
236 }
237
238 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
239 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
240 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
241 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
242 /* NOT_DONE: We are trying the full range of the 2200 clock.
243 We should be able to try n up to 2047 */
244 par->VCLK3NumeratorLow = n_best;
245 par->VCLK3NumeratorHigh = (f_best << 7);
246 } else
247 par->VCLK3NumeratorLow = n_best | (f_best << 7);
248
249 par->VCLK3Denominator = d_best;
250
251#ifdef NEOFB_DEBUG
252 printk("neoVCLK: f:%d NumLow=%d NumHi=%d Den=%d Df=%d\n",
253 f_target >> 12,
254 par->VCLK3NumeratorLow,
255 par->VCLK3NumeratorHigh,
256 par->VCLK3Denominator, f_best_diff >> 12);
257#endif
258}
259
260/*
261 * vgaHWInit --
262 * Handle the initialization, etc. of a screen.
263 * Return FALSE on failure.
264 */
265
266static int vgaHWInit(const struct fb_var_screeninfo *var,
267 const struct fb_info *info,
268 struct neofb_par *par, struct xtimings *timings)
269{
270 par->MiscOutReg = 0x23;
271
272 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
273 par->MiscOutReg |= 0x40;
274
275 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
276 par->MiscOutReg |= 0x80;
277
278 /*
279 * Time Sequencer
280 */
281 par->Sequencer[0] = 0x00;
282 par->Sequencer[1] = 0x01;
283 par->Sequencer[2] = 0x0F;
284 par->Sequencer[3] = 0x00; /* Font select */
285 par->Sequencer[4] = 0x0E; /* Misc */
286
287 /*
288 * CRTC Controller
289 */
290 par->CRTC[0] = (timings->HTotal >> 3) - 5;
291 par->CRTC[1] = (timings->HDisplay >> 3) - 1;
292 par->CRTC[2] = (timings->HDisplay >> 3) - 1;
293 par->CRTC[3] = (((timings->HTotal >> 3) - 1) & 0x1F) | 0x80;
294 par->CRTC[4] = (timings->HSyncStart >> 3);
295 par->CRTC[5] = ((((timings->HTotal >> 3) - 1) & 0x20) << 2)
296 | (((timings->HSyncEnd >> 3)) & 0x1F);
297 par->CRTC[6] = (timings->VTotal - 2) & 0xFF;
298 par->CRTC[7] = (((timings->VTotal - 2) & 0x100) >> 8)
299 | (((timings->VDisplay - 1) & 0x100) >> 7)
300 | ((timings->VSyncStart & 0x100) >> 6)
301 | (((timings->VDisplay - 1) & 0x100) >> 5)
302 | 0x10 | (((timings->VTotal - 2) & 0x200) >> 4)
303 | (((timings->VDisplay - 1) & 0x200) >> 3)
304 | ((timings->VSyncStart & 0x200) >> 2);
305 par->CRTC[8] = 0x00;
306 par->CRTC[9] = (((timings->VDisplay - 1) & 0x200) >> 4) | 0x40;
307
308 if (timings->dblscan)
309 par->CRTC[9] |= 0x80;
310
311 par->CRTC[10] = 0x00;
312 par->CRTC[11] = 0x00;
313 par->CRTC[12] = 0x00;
314 par->CRTC[13] = 0x00;
315 par->CRTC[14] = 0x00;
316 par->CRTC[15] = 0x00;
317 par->CRTC[16] = timings->VSyncStart & 0xFF;
318 par->CRTC[17] = (timings->VSyncEnd & 0x0F) | 0x20;
319 par->CRTC[18] = (timings->VDisplay - 1) & 0xFF;
320 par->CRTC[19] = var->xres_virtual >> 4;
321 par->CRTC[20] = 0x00;
322 par->CRTC[21] = (timings->VDisplay - 1) & 0xFF;
323 par->CRTC[22] = (timings->VTotal - 1) & 0xFF;
324 par->CRTC[23] = 0xC3;
325 par->CRTC[24] = 0xFF;
326
327 /*
328 * are these unnecessary?
329 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
330 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
331 */
332
333 /*
334 * Graphics Display Controller
335 */
336 par->Graphics[0] = 0x00;
337 par->Graphics[1] = 0x00;
338 par->Graphics[2] = 0x00;
339 par->Graphics[3] = 0x00;
340 par->Graphics[4] = 0x00;
341 par->Graphics[5] = 0x40;
342 par->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
343 par->Graphics[7] = 0x0F;
344 par->Graphics[8] = 0xFF;
345
346
347 par->Attribute[0] = 0x00; /* standard colormap translation */
348 par->Attribute[1] = 0x01;
349 par->Attribute[2] = 0x02;
350 par->Attribute[3] = 0x03;
351 par->Attribute[4] = 0x04;
352 par->Attribute[5] = 0x05;
353 par->Attribute[6] = 0x06;
354 par->Attribute[7] = 0x07;
355 par->Attribute[8] = 0x08;
356 par->Attribute[9] = 0x09;
357 par->Attribute[10] = 0x0A;
358 par->Attribute[11] = 0x0B;
359 par->Attribute[12] = 0x0C;
360 par->Attribute[13] = 0x0D;
361 par->Attribute[14] = 0x0E;
362 par->Attribute[15] = 0x0F;
363 par->Attribute[16] = 0x41;
364 par->Attribute[17] = 0xFF;
365 par->Attribute[18] = 0x0F;
366 par->Attribute[19] = 0x00;
367 par->Attribute[20] = 0x00;
368 return 0;
369}
370
371static void vgaHWLock(struct vgastate *state)
372{
373 /* Protect CRTC[0-7] */
374 vga_wcrt(state->vgabase, 0x11, vga_rcrt(state->vgabase, 0x11) | 0x80);
375}
376
377static void vgaHWUnlock(void)
378{
379 /* Unprotect CRTC[0-7] */
380 vga_wcrt(NULL, 0x11, vga_rcrt(NULL, 0x11) & ~0x80);
381}
382
383static void neoLock(struct vgastate *state)
384{
385 vga_wgfx(state->vgabase, 0x09, 0x00);
386 vgaHWLock(state);
387}
388
389static void neoUnlock(void)
390{
391 vgaHWUnlock();
392 vga_wgfx(NULL, 0x09, 0x26);
393}
394
395/*
396 * VGA Palette management
397 */
398static int paletteEnabled = 0;
399
400static inline void VGAenablePalette(void)
401{
402 vga_r(NULL, VGA_IS1_RC);
403 vga_w(NULL, VGA_ATT_W, 0x00);
404 paletteEnabled = 1;
405}
406
407static inline void VGAdisablePalette(void)
408{
409 vga_r(NULL, VGA_IS1_RC);
410 vga_w(NULL, VGA_ATT_W, 0x20);
411 paletteEnabled = 0;
412}
413
414static inline void VGAwATTR(u8 index, u8 value)
415{
416 if (paletteEnabled)
417 index &= ~0x20;
418 else
419 index |= 0x20;
420
421 vga_r(NULL, VGA_IS1_RC);
422 vga_wattr(NULL, index, value);
423}
424
425static void vgaHWProtect(int on)
426{
427 unsigned char tmp;
428
429 if (on) {
430 /*
431 * Turn off screen and disable sequencer.
432 */
433 tmp = vga_rseq(NULL, 0x01);
434 vga_wseq(NULL, 0x00, 0x01); /* Synchronous Reset */
435 vga_wseq(NULL, 0x01, tmp | 0x20); /* disable the display */
436
437 VGAenablePalette();
438 } else {
439 /*
440 * Reenable sequencer, then turn on screen.
441 */
442 tmp = vga_rseq(NULL, 0x01);
443 vga_wseq(NULL, 0x01, tmp & ~0x20); /* reenable display */
444 vga_wseq(NULL, 0x00, 0x03); /* clear synchronousreset */
445
446 VGAdisablePalette();
447 }
448}
449
450static void vgaHWRestore(const struct fb_info *info,
451 const struct neofb_par *par)
452{
453 int i;
454
455 vga_w(NULL, VGA_MIS_W, par->MiscOutReg);
456
457 for (i = 1; i < 5; i++)
458 vga_wseq(NULL, i, par->Sequencer[i]);
459
460 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or CRTC[17] */
461 vga_wcrt(NULL, 17, par->CRTC[17] & ~0x80);
462
463 for (i = 0; i < 25; i++)
464 vga_wcrt(NULL, i, par->CRTC[i]);
465
466 for (i = 0; i < 9; i++)
467 vga_wgfx(NULL, i, par->Graphics[i]);
468
469 VGAenablePalette();
470
471 for (i = 0; i < 21; i++)
472 VGAwATTR(i, par->Attribute[i]);
473
474 VGAdisablePalette();
475}
476
477
478/* -------------------- Hardware specific routines ------------------------- */
479
480/*
481 * Hardware Acceleration for Neo2200+
482 */
483static inline int neo2200_sync(struct fb_info *info)
484{
9f19bc56 485 struct neofb_par *par = info->par;
1da177e4 486
6af7ffc4 487 while (readl(&par->neo2200->bltStat) & 1);
1da177e4
LT		 488 return 0;
489}
490
491static inline void neo2200_wait_fifo(struct fb_info *info,
492 int requested_fifo_space)
493{
494 // ndev->neo.waitfifo_calls++;
495 // ndev->neo.waitfifo_sum += requested_fifo_space;
496
497 /* FIXME: does not work
498 if (neo_fifo_space < requested_fifo_space)
499 {
500 neo_fifo_waitcycles++;
501
502 while (1)
503 {
504 neo_fifo_space = (neo2200->bltStat >> 8);
505 if (neo_fifo_space >= requested_fifo_space)
506 break;
507 }
508 }
509 else
510 {
511 neo_fifo_cache_hits++;
512 }
513
514 neo_fifo_space -= requested_fifo_space;
515 */
516
517 neo2200_sync(info);
518}
519
520static inline void neo2200_accel_init(struct fb_info *info,
521 struct fb_var_screeninfo *var)
522{
9f19bc56 523 struct neofb_par *par = info->par;
1da177e4
LT		 524 Neo2200 __iomem *neo2200 = par->neo2200;
525 u32 bltMod, pitch;
526
527 neo2200_sync(info);
528
529 switch (var->bits_per_pixel) {
530 case 8:
531 bltMod = NEO_MODE1_DEPTH8;
532 pitch = var->xres_virtual;
533 break;
534 case 15:
535 case 16:
536 bltMod = NEO_MODE1_DEPTH16;
537 pitch = var->xres_virtual * 2;
538 break;
539 case 24:
540 bltMod = NEO_MODE1_DEPTH24;
541 pitch = var->xres_virtual * 3;
542 break;
543 default:
544 printk(KERN_ERR
545 "neofb: neo2200_accel_init: unexpected bits per pixel!\n");
546 return;
547 }
548
549 writel(bltMod << 16, &neo2200->bltStat);
550 writel((pitch << 16) | pitch, &neo2200->pitch);
551}
552
553/* --------------------------------------------------------------------- */
554
555static int
556neofb_open(struct fb_info *info, int user)
557{
9f19bc56 558 struct neofb_par *par = info->par;
1da177e4
LT		 559 int cnt = atomic_read(&par->ref_count);
560
561 if (!cnt) {
562 memset(&par->state, 0, sizeof(struct vgastate));
563 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
564 save_vga(&par->state);
565 }
566 atomic_inc(&par->ref_count);
567 return 0;
568}
569
570static int
571neofb_release(struct fb_info *info, int user)
572{
9f19bc56 573 struct neofb_par *par = info->par;
1da177e4
LT		 574 int cnt = atomic_read(&par->ref_count);
575
576 if (!cnt)
577 return -EINVAL;
578 if (cnt == 1) {
579 restore_vga(&par->state);
580 }
581 atomic_dec(&par->ref_count);
582 return 0;
583}
584
585static int
586neofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
587{
9f19bc56 588 struct neofb_par *par = info->par;
1da177e4
LT		 589 unsigned int pixclock = var->pixclock;
590 struct xtimings timings;
591 int memlen, vramlen;
592 int mode_ok = 0;
593
594 DBG("neofb_check_var");
595
596 if (!pixclock)
597 pixclock = 10000; /* 10ns = 100MHz */
598 timings.pixclock = 1000000000 / pixclock;
599 if (timings.pixclock < 1)
600 timings.pixclock = 1;
601
602 if (timings.pixclock > par->maxClock)
603 return -EINVAL;
604
605 timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
606 timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
607 timings.HDisplay = var->xres;
608 timings.HSyncStart = timings.HDisplay + var->right_margin;
609 timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
610 timings.HTotal = timings.HSyncEnd + var->left_margin;
611 timings.VDisplay = var->yres;
612 timings.VSyncStart = timings.VDisplay + var->lower_margin;
613 timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
614 timings.VTotal = timings.VSyncEnd + var->upper_margin;
615 timings.sync = var->sync;
616
617 /* Is the mode larger than the LCD panel? */
618 if (par->internal_display &&
619 ((var->xres > par->NeoPanelWidth) ||
620 (var->yres > par->NeoPanelHeight))) {
621 printk(KERN_INFO
622 "Mode (%dx%d) larger than the LCD panel (%dx%d)\n",
623 var->xres, var->yres, par->NeoPanelWidth,
624 par->NeoPanelHeight);
625 return -EINVAL;
626 }
627
628 /* Is the mode one of the acceptable sizes? */
629 if (!par->internal_display)
630 mode_ok = 1;
631 else {
632 switch (var->xres) {
633 case 1280:
634 if (var->yres == 1024)
635 mode_ok = 1;
636 break;
637 case 1024:
638 if (var->yres == 768)
639 mode_ok = 1;
640 break;
641 case 800:
642 if (var->yres == (par->libretto ? 480 : 600))
643 mode_ok = 1;
644 break;
645 case 640:
646 if (var->yres == 480)
647 mode_ok = 1;
648 break;
649 }
650 }
651
652 if (!mode_ok) {
653 printk(KERN_INFO
654 "Mode (%dx%d) won't display properly on LCD\n",
655 var->xres, var->yres);
656 return -EINVAL;
657 }
658
659 var->red.msb_right = 0;
660 var->green.msb_right = 0;
661 var->blue.msb_right = 0;
662
663 switch (var->bits_per_pixel) {
664 case 8: /* PSEUDOCOLOUR, 256 */
665 var->transp.offset = 0;
666 var->transp.length = 0;
667 var->red.offset = 0;
668 var->red.length = 8;
669 var->green.offset = 0;
670 var->green.length = 8;
671 var->blue.offset = 0;
672 var->blue.length = 8;
673 break;
674
675 case 16: /* DIRECTCOLOUR, 64k */
676 var->transp.offset = 0;
677 var->transp.length = 0;
678 var->red.offset = 11;
679 var->red.length = 5;
680 var->green.offset = 5;
681 var->green.length = 6;
682 var->blue.offset = 0;
683 var->blue.length = 5;
684 break;
685
686 case 24: /* TRUECOLOUR, 16m */
687 var->transp.offset = 0;
688 var->transp.length = 0;
689 var->red.offset = 16;
690 var->red.length = 8;
691 var->green.offset = 8;
692 var->green.length = 8;
693 var->blue.offset = 0;
694 var->blue.length = 8;
695 break;
696
697#ifdef NO_32BIT_SUPPORT_YET
698 case 32: /* TRUECOLOUR, 16m */
699 var->transp.offset = 24;
700 var->transp.length = 8;
701 var->red.offset = 16;
702 var->red.length = 8;
703 var->green.offset = 8;
704 var->green.length = 8;
705 var->blue.offset = 0;
706 var->blue.length = 8;
707 break;
708#endif
709 default:
710 printk(KERN_WARNING "neofb: no support for %dbpp\n",
711 var->bits_per_pixel);
712 return -EINVAL;
713 }
714
715 vramlen = info->fix.smem_len;
716 if (vramlen > 4 * 1024 * 1024)
717 vramlen = 4 * 1024 * 1024;
718
719 if (var->yres_virtual < var->yres)
720 var->yres_virtual = var->yres;
721 if (var->xres_virtual < var->xres)
722 var->xres_virtual = var->xres;
723
724 memlen = var->xres_virtual * var->bits_per_pixel * var->yres_virtual >> 3;
725
726 if (memlen > vramlen) {
727 var->yres_virtual = vramlen * 8 / (var->xres_virtual *
728 var->bits_per_pixel);
729 memlen = var->xres_virtual * var->bits_per_pixel *
730 var->yres_virtual / 8;
731 }
732
733 /* we must round yres/xres down, we already rounded y/xres_virtual up
734 if it was possible. We should return -EINVAL, but I disagree */
735 if (var->yres_virtual < var->yres)
736 var->yres = var->yres_virtual;
737 if (var->xres_virtual < var->xres)
738 var->xres = var->xres_virtual;
739 if (var->xoffset + var->xres > var->xres_virtual)
740 var->xoffset = var->xres_virtual - var->xres;
741 if (var->yoffset + var->yres > var->yres_virtual)
742 var->yoffset = var->yres_virtual - var->yres;
743
744 var->nonstd = 0;
745 var->height = -1;
746 var->width = -1;
747
748 if (var->bits_per_pixel >= 24 || !par->neo2200)
749 var->accel_flags &= ~FB_ACCELF_TEXT;
750 return 0;
751}
752
753static int neofb_set_par(struct fb_info *info)
754{
9f19bc56 755 struct neofb_par *par = info->par;
1da177e4
LT		 756 struct xtimings timings;
757 unsigned char temp;
758 int i, clock_hi = 0;
759 int lcd_stretch;
760 int hoffset, voffset;
761
762 DBG("neofb_set_par");
763
764 neoUnlock();
765
766 vgaHWProtect(1); /* Blank the screen */
767
768 timings.dblscan = info->var.vmode & FB_VMODE_DOUBLE;
769 timings.interlaced = info->var.vmode & FB_VMODE_INTERLACED;
770 timings.HDisplay = info->var.xres;
771 timings.HSyncStart = timings.HDisplay + info->var.right_margin;
772 timings.HSyncEnd = timings.HSyncStart + info->var.hsync_len;
773 timings.HTotal = timings.HSyncEnd + info->var.left_margin;
774 timings.VDisplay = info->var.yres;
775 timings.VSyncStart = timings.VDisplay + info->var.lower_margin;
776 timings.VSyncEnd = timings.VSyncStart + info->var.vsync_len;
777 timings.VTotal = timings.VSyncEnd + info->var.upper_margin;
778 timings.sync = info->var.sync;
779 timings.pixclock = PICOS2KHZ(info->var.pixclock);
780
781 if (timings.pixclock < 1)
782 timings.pixclock = 1;
783
784 /*
785 * This will allocate the datastructure and initialize all of the
786 * generic VGA registers.
787 */
788
789 if (vgaHWInit(&info->var, info, par, &timings))
790 return -EINVAL;
791
792 /*
793 * The default value assigned by vgaHW.c is 0x41, but this does
794 * not work for NeoMagic.
795 */
796 par->Attribute[16] = 0x01;
797
798 switch (info->var.bits_per_pixel) {
799 case 8:
800 par->CRTC[0x13] = info->var.xres_virtual >> 3;
801 par->ExtCRTOffset = info->var.xres_virtual >> 11;
802 par->ExtColorModeSelect = 0x11;
803 break;
804 case 16:
805 par->CRTC[0x13] = info->var.xres_virtual >> 2;
806 par->ExtCRTOffset = info->var.xres_virtual >> 10;
807 par->ExtColorModeSelect = 0x13;
808 break;
809 case 24:
810 par->CRTC[0x13] = (info->var.xres_virtual * 3) >> 3;
811 par->ExtCRTOffset = (info->var.xres_virtual * 3) >> 11;
812 par->ExtColorModeSelect = 0x14;
813 break;
814#ifdef NO_32BIT_SUPPORT_YET
815 case 32: /* FIXME: guessed values */
816 par->CRTC[0x13] = info->var.xres_virtual >> 1;
817 par->ExtCRTOffset = info->var.xres_virtual >> 9;
818 par->ExtColorModeSelect = 0x15;
819 break;
820#endif
821 default:
822 break;
823 }
824
825 par->ExtCRTDispAddr = 0x10;
826
827 /* Vertical Extension */
828 par->VerticalExt = (((timings.VTotal - 2) & 0x400) >> 10)
829 | (((timings.VDisplay - 1) & 0x400) >> 9)
830 | (((timings.VSyncStart) & 0x400) >> 8)
831 | (((timings.VSyncStart) & 0x400) >> 7);
832
833 /* Fast write bursts on unless disabled. */
834 if (par->pci_burst)
835 par->SysIfaceCntl1 = 0x30;
836 else
837 par->SysIfaceCntl1 = 0x00;
838
839 par->SysIfaceCntl2 = 0xc0; /* VESA Bios sets this to 0x80! */
840
9f672004
CT		 841 /* Initialize: by default, we want display config register to be read */
842 par->PanelDispCntlRegRead = 1;
843
1da177e4
LT		 844 /* Enable any user specified display devices. */
845 par->PanelDispCntlReg1 = 0x00;
846 if (par->internal_display)
847 par->PanelDispCntlReg1 |= 0x02;
848 if (par->external_display)
849 par->PanelDispCntlReg1 |= 0x01;
850
851 /* If the user did not specify any display devices, then... */
852 if (par->PanelDispCntlReg1 == 0x00) {
853 /* Default to internal (i.e., LCD) only. */
4836f574 854 par->PanelDispCntlReg1 = vga_rgfx(NULL, 0x20) & 0x03;
1da177e4
LT		 855 }
856
857 /* If we are using a fixed mode, then tell the chip we are. */
858 switch (info->var.xres) {
859 case 1280:
860 par->PanelDispCntlReg1 |= 0x60;
861 break;
862 case 1024:
863 par->PanelDispCntlReg1 |= 0x40;
864 break;
865 case 800:
866 par->PanelDispCntlReg1 |= 0x20;
867 break;
868 case 640:
869 default:
870 break;
871 }
872
873 /* Setup shadow register locking. */
874 switch (par->PanelDispCntlReg1 & 0x03) {
875 case 0x01: /* External CRT only mode: */
876 par->GeneralLockReg = 0x00;
877 /* We need to program the VCLK for external display only mode. */
878 par->ProgramVCLK = 1;
879 break;
880 case 0x02: /* Internal LCD only mode: */
881 case 0x03: /* Simultaneous internal/external (LCD/CRT) mode: */
882 par->GeneralLockReg = 0x01;
883 /* Don't program the VCLK when using the LCD. */
884 par->ProgramVCLK = 0;
885 break;
886 }
887
888 /*
889 * If the screen is to be stretched, turn on stretching for the
890 * various modes.
891 *
892 * OPTION_LCD_STRETCH means stretching should be turned off!
893 */
894 par->PanelDispCntlReg2 = 0x00;
895 par->PanelDispCntlReg3 = 0x00;
896
897 if (par->lcd_stretch && (par->PanelDispCntlReg1 == 0x02) && /* LCD only */
898 (info->var.xres != par->NeoPanelWidth)) {
899 switch (info->var.xres) {
900 case 320: /* Needs testing. KEM -- 24 May 98 */
901 case 400: /* Needs testing. KEM -- 24 May 98 */
902 case 640:
903 case 800:
904 case 1024:
905 lcd_stretch = 1;
906 par->PanelDispCntlReg2 |= 0xC6;
907 break;
908 default:
909 lcd_stretch = 0;
910 /* No stretching in these modes. */
911 }
912 } else
913 lcd_stretch = 0;
914
915 /*
916 * If the screen is to be centerd, turn on the centering for the
917 * various modes.
918 */
919 par->PanelVertCenterReg1 = 0x00;
920 par->PanelVertCenterReg2 = 0x00;
921 par->PanelVertCenterReg3 = 0x00;
922 par->PanelVertCenterReg4 = 0x00;
923 par->PanelVertCenterReg5 = 0x00;
924 par->PanelHorizCenterReg1 = 0x00;
925 par->PanelHorizCenterReg2 = 0x00;
926 par->PanelHorizCenterReg3 = 0x00;
927 par->PanelHorizCenterReg4 = 0x00;
928 par->PanelHorizCenterReg5 = 0x00;
929
930
931 if (par->PanelDispCntlReg1 & 0x02) {
932 if (info->var.xres == par->NeoPanelWidth) {
933 /*
934 * No centering required when the requested display width
935 * equals the panel width.
936 */
937 } else {
938 par->PanelDispCntlReg2 |= 0x01;
939 par->PanelDispCntlReg3 |= 0x10;
940
941 /* Calculate the horizontal and vertical offsets. */
942 if (!lcd_stretch) {
943 hoffset =
944 ((par->NeoPanelWidth -
945 info->var.xres) >> 4) - 1;
946 voffset =
947 ((par->NeoPanelHeight -
948 info->var.yres) >> 1) - 2;
949 } else {
950 /* Stretched modes cannot be centered. */
951 hoffset = 0;
952 voffset = 0;
953 }
954
955 switch (info->var.xres) {
956 case 320: /* Needs testing. KEM -- 24 May 98 */
957 par->PanelHorizCenterReg3 = hoffset;
958 par->PanelVertCenterReg2 = voffset;
959 break;
960 case 400: /* Needs testing. KEM -- 24 May 98 */
961 par->PanelHorizCenterReg4 = hoffset;
962 par->PanelVertCenterReg1 = voffset;
963 break;
964 case 640:
965 par->PanelHorizCenterReg1 = hoffset;
966 par->PanelVertCenterReg3 = voffset;
967 break;
968 case 800:
969 par->PanelHorizCenterReg2 = hoffset;
970 par->PanelVertCenterReg4 = voffset;
971 break;
972 case 1024:
973 par->PanelHorizCenterReg5 = hoffset;
974 par->PanelVertCenterReg5 = voffset;
975 break;
976 case 1280:
977 default:
978 /* No centering in these modes. */
979 break;
980 }
981 }
982 }
983
984 par->biosMode =
985 neoFindMode(info->var.xres, info->var.yres,
986 info->var.bits_per_pixel);
987
988 /*
989 * Calculate the VCLK that most closely matches the requested dot
990 * clock.
991 */
992 neoCalcVCLK(info, par, timings.pixclock);
993
994 /* Since we program the clocks ourselves, always use VCLK3. */
995 par->MiscOutReg |= 0x0C;
996
997 /* alread unlocked above */
998 /* BOGUS vga_wgfx(NULL, 0x09, 0x26); */
999
1000 /* don't know what this is, but it's 0 from bootup anyway */
1001 vga_wgfx(NULL, 0x15, 0x00);
1002
1003 /* was set to 0x01 by my bios in text and vesa modes */
1004 vga_wgfx(NULL, 0x0A, par->GeneralLockReg);
1005
1006 /*
1007 * The color mode needs to be set before calling vgaHWRestore
1008 * to ensure the DAC is initialized properly.
1009 *
1010 * NOTE: Make sure we don't change bits make sure we don't change
1011 * any reserved bits.
1012 */
1013 temp = vga_rgfx(NULL, 0x90);
1014 switch (info->fix.accel) {
1015 case FB_ACCEL_NEOMAGIC_NM2070:
1016 temp &= 0xF0; /* Save bits 7:4 */
1017 temp |= (par->ExtColorModeSelect & ~0xF0);
1018 break;
1019 case FB_ACCEL_NEOMAGIC_NM2090:
1020 case FB_ACCEL_NEOMAGIC_NM2093:
1021 case FB_ACCEL_NEOMAGIC_NM2097:
1022 case FB_ACCEL_NEOMAGIC_NM2160:
1023 case FB_ACCEL_NEOMAGIC_NM2200:
1024 case FB_ACCEL_NEOMAGIC_NM2230:
1025 case FB_ACCEL_NEOMAGIC_NM2360:
1026 case FB_ACCEL_NEOMAGIC_NM2380:
1027 temp &= 0x70; /* Save bits 6:4 */
1028 temp |= (par->ExtColorModeSelect & ~0x70);
1029 break;
1030 }
1031
1032 vga_wgfx(NULL, 0x90, temp);
1033
1034 /*
1035 * In some rare cases a lockup might occur if we don't delay
1036 * here. (Reported by Miles Lane)
1037 */
1038 //mdelay(200);
1039
1040 /*
1041 * Disable horizontal and vertical graphics and text expansions so
1042 * that vgaHWRestore works properly.
1043 */
1044 temp = vga_rgfx(NULL, 0x25);
1045 temp &= 0x39;
1046 vga_wgfx(NULL, 0x25, temp);
1047
1048 /*
1049 * Sleep for 200ms to make sure that the two operations above have
1050 * had time to take effect.
1051 */
1052 mdelay(200);
1053
1054 /*
1055 * This function handles restoring the generic VGA registers. */
1056 vgaHWRestore(info, par);
1057
1058 /* linear colormap for non palettized modes */
1059 switch (info->var.bits_per_pixel) {
1060 case 8:
1061 /* PseudoColor, 256 */
1062 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1063 break;
1064 case 16:
1065 /* TrueColor, 64k */
1066 info->fix.visual = FB_VISUAL_TRUECOLOR;
1067
1068 for (i = 0; i < 64; i++) {
1069 outb(i, 0x3c8);
1070
1071 outb(i << 1, 0x3c9);
1072 outb(i, 0x3c9);
1073 outb(i << 1, 0x3c9);
1074 }
1075 break;
1076 case 24:
1077#ifdef NO_32BIT_SUPPORT_YET
1078 case 32:
1079#endif
1080 /* TrueColor, 16m */
1081 info->fix.visual = FB_VISUAL_TRUECOLOR;
1082
1083 for (i = 0; i < 256; i++) {
1084 outb(i, 0x3c8);
1085
1086 outb(i, 0x3c9);
1087 outb(i, 0x3c9);
1088 outb(i, 0x3c9);
1089 }
1090 break;
1091 }
1092
1093 vga_wgfx(NULL, 0x0E, par->ExtCRTDispAddr);
1094 vga_wgfx(NULL, 0x0F, par->ExtCRTOffset);
1095 temp = vga_rgfx(NULL, 0x10);
1096 temp &= 0x0F; /* Save bits 3:0 */
1097 temp |= (par->SysIfaceCntl1 & ~0x0F); /* VESA Bios sets bit 1! */
1098 vga_wgfx(NULL, 0x10, temp);
1099
1100 vga_wgfx(NULL, 0x11, par->SysIfaceCntl2);
1101 vga_wgfx(NULL, 0x15, 0 /*par->SingleAddrPage */ );
1102 vga_wgfx(NULL, 0x16, 0 /*par->DualAddrPage */ );
1103
1104 temp = vga_rgfx(NULL, 0x20);
1105 switch (info->fix.accel) {
1106 case FB_ACCEL_NEOMAGIC_NM2070:
1107 temp &= 0xFC; /* Save bits 7:2 */
1108 temp |= (par->PanelDispCntlReg1 & ~0xFC);
1109 break;
1110 case FB_ACCEL_NEOMAGIC_NM2090:
1111 case FB_ACCEL_NEOMAGIC_NM2093:
1112 case FB_ACCEL_NEOMAGIC_NM2097:
1113 case FB_ACCEL_NEOMAGIC_NM2160:
1114 temp &= 0xDC; /* Save bits 7:6,4:2 */
1115 temp |= (par->PanelDispCntlReg1 & ~0xDC);
1116 break;
1117 case FB_ACCEL_NEOMAGIC_NM2200:
1118 case FB_ACCEL_NEOMAGIC_NM2230:
1119 case FB_ACCEL_NEOMAGIC_NM2360:
1120 case FB_ACCEL_NEOMAGIC_NM2380:
1121 temp &= 0x98; /* Save bits 7,4:3 */
1122 temp |= (par->PanelDispCntlReg1 & ~0x98);
1123 break;
1124 }
1125 vga_wgfx(NULL, 0x20, temp);
1126
1127 temp = vga_rgfx(NULL, 0x25);
1128 temp &= 0x38; /* Save bits 5:3 */
1129 temp |= (par->PanelDispCntlReg2 & ~0x38);
1130 vga_wgfx(NULL, 0x25, temp);
1131
1132 if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
1133 temp = vga_rgfx(NULL, 0x30);
1134 temp &= 0xEF; /* Save bits 7:5 and bits 3:0 */
1135 temp |= (par->PanelDispCntlReg3 & ~0xEF);
1136 vga_wgfx(NULL, 0x30, temp);
1137 }
1138
1139 vga_wgfx(NULL, 0x28, par->PanelVertCenterReg1);
1140 vga_wgfx(NULL, 0x29, par->PanelVertCenterReg2);
1141 vga_wgfx(NULL, 0x2a, par->PanelVertCenterReg3);
1142
1143 if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
1144 vga_wgfx(NULL, 0x32, par->PanelVertCenterReg4);
1145 vga_wgfx(NULL, 0x33, par->PanelHorizCenterReg1);
1146 vga_wgfx(NULL, 0x34, par->PanelHorizCenterReg2);
1147 vga_wgfx(NULL, 0x35, par->PanelHorizCenterReg3);
1148 }
1149
1150 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2160)
1151 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1152
1153 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
1154 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
1155 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
1156 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
1157 vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
1158 vga_wgfx(NULL, 0x37, par->PanelVertCenterReg5);
1159 vga_wgfx(NULL, 0x38, par->PanelHorizCenterReg5);
1160
1161 clock_hi = 1;
1162 }
1163
1164 /* Program VCLK3 if needed. */
1165 if (par->ProgramVCLK && ((vga_rgfx(NULL, 0x9B) != par->VCLK3NumeratorLow)
1166 || (vga_rgfx(NULL, 0x9F) != par->VCLK3Denominator)
1167 || (clock_hi && ((vga_rgfx(NULL, 0x8F) & ~0x0f)
1168 != (par->VCLK3NumeratorHigh &
1169 ~0x0F))))) {
1170 vga_wgfx(NULL, 0x9B, par->VCLK3NumeratorLow);
1171 if (clock_hi) {
1172 temp = vga_rgfx(NULL, 0x8F);
1173 temp &= 0x0F; /* Save bits 3:0 */
1174 temp |= (par->VCLK3NumeratorHigh & ~0x0F);
1175 vga_wgfx(NULL, 0x8F, temp);
1176 }
1177 vga_wgfx(NULL, 0x9F, par->VCLK3Denominator);
1178 }
1179
1180 if (par->biosMode)
1181 vga_wcrt(NULL, 0x23, par->biosMode);
1182
1183 vga_wgfx(NULL, 0x93, 0xc0); /* Gives 5x faster framebuffer writes !!! */
1184
1185 /* Program vertical extension register */
1186 if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
1187 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
1188 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
1189 info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
1190 vga_wcrt(NULL, 0x70, par->VerticalExt);
1191 }
1192
1193 vgaHWProtect(0); /* Turn on screen */
1194
1195 /* Calling this also locks offset registers required in update_start */
1196 neoLock(&par->state);
1197
1198 info->fix.line_length =
1199 info->var.xres_virtual * (info->var.bits_per_pixel >> 3);
1200
1201 switch (info->fix.accel) {
1202 case FB_ACCEL_NEOMAGIC_NM2200:
1203 case FB_ACCEL_NEOMAGIC_NM2230:
1204 case FB_ACCEL_NEOMAGIC_NM2360:
1205 case FB_ACCEL_NEOMAGIC_NM2380:
1206 neo2200_accel_init(info, &info->var);
1207 break;
1208 default:
1209 break;
1210 }
1211 return 0;
1212}
1213
1214static void neofb_update_start(struct fb_info *info,
1215 struct fb_var_screeninfo *var)
1216{
9f19bc56 1217 struct neofb_par *par = info->par;
1da177e4
LT		 1218 struct vgastate *state = &par->state;
1219 int oldExtCRTDispAddr;
1220 int Base;
1221
1222 DBG("neofb_update_start");
1223
1224 Base = (var->yoffset * var->xres_virtual + var->xoffset) >> 2;
1225 Base *= (var->bits_per_pixel + 7) / 8;
1226
1227 neoUnlock();
1228
1229 /*
1230 * These are the generic starting address registers.
1231 */
1232 vga_wcrt(state->vgabase, 0x0C, (Base & 0x00FF00) >> 8);
1233 vga_wcrt(state->vgabase, 0x0D, (Base & 0x00FF));
1234
1235 /*
1236 * Make sure we don't clobber some other bits that might already
1237 * have been set. NOTE: NM2200 has a writable bit 3, but it shouldn't
1238 * be needed.
1239 */
1240 oldExtCRTDispAddr = vga_rgfx(NULL, 0x0E);
1241 vga_wgfx(state->vgabase, 0x0E, (((Base >> 16) & 0x0f) | (oldExtCRTDispAddr & 0xf0)));
1242
1243 neoLock(state);
1244}
1245
1246/*
1247 * Pan or Wrap the Display
1248 */
1249static int neofb_pan_display(struct fb_var_screeninfo *var,
1250 struct fb_info *info)
1251{
1252 u_int y_bottom;
1253
1254 y_bottom = var->yoffset;
1255
1256 if (!(var->vmode & FB_VMODE_YWRAP))
1257 y_bottom += var->yres;
1258
1259 if (var->xoffset > (var->xres_virtual - var->xres))
1260 return -EINVAL;
1261 if (y_bottom > info->var.yres_virtual)
1262 return -EINVAL;
1263
1264 neofb_update_start(info, var);
1265
1266 info->var.xoffset = var->xoffset;
1267 info->var.yoffset = var->yoffset;
1268
1269 if (var->vmode & FB_VMODE_YWRAP)
1270 info->var.vmode |= FB_VMODE_YWRAP;
1271 else
1272 info->var.vmode &= ~FB_VMODE_YWRAP;
1273 return 0;
1274}
1275
1276static int neofb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1277 u_int transp, struct fb_info *fb)
1278{
1279 if (regno >= fb->cmap.len || regno > 255)
1280 return -EINVAL;
1281
1282 switch (fb->var.bits_per_pixel) {
1283 case 8:
1284 outb(regno, 0x3c8);
1285
1286 outb(red >> 10, 0x3c9);
1287 outb(green >> 10, 0x3c9);
1288 outb(blue >> 10, 0x3c9);
1289 break;
1290 case 16:
1291 ((u32 *) fb->pseudo_palette)[regno] =
1292 ((red & 0xf800)) | ((green & 0xfc00) >> 5) |
1293 ((blue & 0xf800) >> 11);
1294 break;
1295 case 24:
1296 ((u32 *) fb->pseudo_palette)[regno] =
1297 ((red & 0xff00) << 8) | ((green & 0xff00)) |
1298 ((blue & 0xff00) >> 8);
1299 break;
1300#ifdef NO_32BIT_SUPPORT_YET
1301 case 32:
1302 ((u32 *) fb->pseudo_palette)[regno] =
1303 ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
1304 ((green & 0xff00)) | ((blue & 0xff00) >> 8);
1305 break;
1306#endif
1307 default:
1308 return 1;
1309 }
1310 return 0;
1311}
1312
1313/*
1314 * (Un)Blank the display.
1315 */
1316static int neofb_blank(int blank_mode, struct fb_info *info)
1317{
1318 /*
1319 * Blank the screen if blank_mode != 0, else unblank.
1320 * Return 0 if blanking succeeded, != 0 if un-/blanking failed due to
1321 * e.g. a video mode which doesn't support it. Implements VESA suspend
1322 * and powerdown modes for monitors, and backlight control on LCDs.
1323 * blank_mode == 0: unblanked (backlight on)
1324 * blank_mode == 1: blank (backlight on)
1325 * blank_mode == 2: suspend vsync (backlight off)
1326 * blank_mode == 3: suspend hsync (backlight off)
1327 * blank_mode == 4: powerdown (backlight off)
1328 *
1329 * wms...Enable VESA DPMS compatible powerdown mode
1330 * run "setterm -powersave powerdown" to take advantage
1331 */
9f19bc56 1332 struct neofb_par *par = info->par;
4efefd1d 1333 int seqflags, lcdflags, dpmsflags, reg, tmpdisp;
9f672004 1334
10ee39fe 1335 /*
4efefd1d
CT		 1336 * Read back the register bits related to display configuration. They might
1337 * have been changed underneath the driver via Fn key stroke.
1338 */
1339 neoUnlock();
1340 tmpdisp = vga_rgfx(NULL, 0x20) & 0x03;
1341 neoLock(&par->state);
1342
1343 /* In case we blank the screen, we want to store the possibly new
1344 * configuration in the driver. During un-blank, we re-apply this setting,
1345 * since the LCD bit will be cleared in order to switch off the backlight.
10ee39fe 1346 */
9f672004 1347 if (par->PanelDispCntlRegRead) {
4efefd1d 1348 par->PanelDispCntlReg1 = tmpdisp;
9f672004
CT		 1349 }
1350 par->PanelDispCntlRegRead = !blank_mode;
10ee39fe 1351
1da177e4
LT		 1352 switch (blank_mode) {
1353 case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
1354 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1355 lcdflags = 0; /* LCD off */
1356 dpmsflags = NEO_GR01_SUPPRESS_HSYNC |
1357 NEO_GR01_SUPPRESS_VSYNC;
1358#ifdef CONFIG_TOSHIBA
1359 /* Do we still need this ? */
1360 /* attempt to turn off backlight on toshiba; also turns off external */
1361 {
1362 SMMRegisters regs;
1363
1364 regs.eax = 0xff00; /* HCI_SET */
1365 regs.ebx = 0x0002; /* HCI_BACKLIGHT */
1366 regs.ecx = 0x0000; /* HCI_DISABLE */
1367 tosh_smm(&regs);
1368 }
1369#endif
1370 break;
1371 case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
1372 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1373 lcdflags = 0; /* LCD off */
1374 dpmsflags = NEO_GR01_SUPPRESS_HSYNC;
1375 break;
1376 case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
1377 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
1378 lcdflags = 0; /* LCD off */
1379 dpmsflags = NEO_GR01_SUPPRESS_VSYNC;
1380 break;
1381 case FB_BLANK_NORMAL: /* just blank screen (backlight stays on) */
1382 seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
4efefd1d
CT		 1383 /*
1384 * During a blank operation with the LID shut, we might store "LCD off"
1385 * by mistake. Due to timing issues, the BIOS may switch the lights
1386 * back on, and we turn it back off once we "unblank".
1387 *
1388 * So here is an attempt to implement ">=" - if we are in the process
1389 * of unblanking, and the LCD bit is unset in the driver but set in the
1390 * register, we must keep it.
1391 */
1392 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
10ee39fe 1393 dpmsflags = 0x00; /* no hsync/vsync suppression */
1da177e4
LT		 1394 break;
1395 case FB_BLANK_UNBLANK: /* unblank */
1396 seqflags = 0; /* Enable sequencer */
4efefd1d 1397 lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
1da177e4
LT		 1398 dpmsflags = 0x00; /* no hsync/vsync suppression */
1399#ifdef CONFIG_TOSHIBA
1400 /* Do we still need this ? */
1401 /* attempt to re-enable backlight/external on toshiba */
1402 {
1403 SMMRegisters regs;
1404
1405 regs.eax = 0xff00; /* HCI_SET */
1406 regs.ebx = 0x0002; /* HCI_BACKLIGHT */
1407 regs.ecx = 0x0001; /* HCI_ENABLE */
1408 tosh_smm(&regs);
1409 }
1410#endif
1411 break;
1412 default: /* Anything else we don't understand; return 1 to tell
1413 * fb_blank we didn't aactually do anything */
1414 return 1;
1415 }
1416
1417 neoUnlock();
1418 reg = (vga_rseq(NULL, 0x01) & ~0x20) | seqflags;
1419 vga_wseq(NULL, 0x01, reg);
1420 reg = (vga_rgfx(NULL, 0x20) & ~0x02) | lcdflags;
1421 vga_wgfx(NULL, 0x20, reg);
1422 reg = (vga_rgfx(NULL, 0x01) & ~0xF0) | 0x80 | dpmsflags;
1423 vga_wgfx(NULL, 0x01, reg);
1424 neoLock(&par->state);
1425 return 0;
1426}
1427
1428static void
1429neo2200_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1430{
9f19bc56 1431 struct neofb_par *par = info->par;
1da177e4
LT		 1432 u_long dst, rop;
1433
1434 dst = rect->dx + rect->dy * info->var.xres_virtual;
1435 rop = rect->rop ? 0x060000 : 0x0c0000;
1436
1437 neo2200_wait_fifo(info, 4);
1438
1439 /* set blt control */
1440 writel(NEO_BC3_FIFO_EN |
1441 NEO_BC0_SRC_IS_FG | NEO_BC3_SKIP_MAPPING |
1442 // NEO_BC3_DST_XY_ADDR |
1443 // NEO_BC3_SRC_XY_ADDR |
1444 rop, &par->neo2200->bltCntl);
1445
1446 switch (info->var.bits_per_pixel) {
1447 case 8:
1448 writel(rect->color, &par->neo2200->fgColor);
1449 break;
1450 case 16:
1451 case 24:
1452 writel(((u32 *) (info->pseudo_palette))[rect->color],
1453 &par->neo2200->fgColor);
1454 break;
1455 }
1456
1457 writel(dst * ((info->var.bits_per_pixel + 7) >> 3),
1458 &par->neo2200->dstStart);
1459 writel((rect->height << 16) | (rect->width & 0xffff),
1460 &par->neo2200->xyExt);
1461}
1462
1463static void
1464neo2200_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1465{
1466 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
9f19bc56 1467 struct neofb_par *par = info->par;
1da177e4
LT		 1468 u_long src, dst, bltCntl;
1469
1470 bltCntl = NEO_BC3_FIFO_EN | NEO_BC3_SKIP_MAPPING | 0x0C0000;
1471
1472 if ((dy > sy) || ((dy == sy) && (dx > sx))) {
1473 /* Start with the lower right corner */
1474 sy += (area->height - 1);
1475 dy += (area->height - 1);
1476 sx += (area->width - 1);
1477 dx += (area->width - 1);
1478
1479 bltCntl |= NEO_BC0_X_DEC | NEO_BC0_DST_Y_DEC | NEO_BC0_SRC_Y_DEC;
1480 }
1481
1482 src = sx * (info->var.bits_per_pixel >> 3) + sy*info->fix.line_length;
1483 dst = dx * (info->var.bits_per_pixel >> 3) + dy*info->fix.line_length;
1484
1485 neo2200_wait_fifo(info, 4);
1486
1487 /* set blt control */
1488 writel(bltCntl, &par->neo2200->bltCntl);
1489
1490 writel(src, &par->neo2200->srcStart);
1491 writel(dst, &par->neo2200->dstStart);
1492 writel((area->height << 16) | (area->width & 0xffff),
1493 &par->neo2200->xyExt);
1494}
1495
1496static void
1497neo2200_imageblit(struct fb_info *info, const struct fb_image *image)
1498{
9f19bc56 1499 struct neofb_par *par = info->par;
1da177e4
LT		 1500 int s_pitch = (image->width * image->depth + 7) >> 3;
1501 int scan_align = info->pixmap.scan_align - 1;
1502 int buf_align = info->pixmap.buf_align - 1;
1503 int bltCntl_flags, d_pitch, data_len;
1504
1505 // The data is padded for the hardware
1506 d_pitch = (s_pitch + scan_align) & ~scan_align;
1507 data_len = ((d_pitch * image->height) + buf_align) & ~buf_align;
1508
1509 neo2200_sync(info);
1510
1511 if (image->depth == 1) {
1512 if (info->var.bits_per_pixel == 24 && image->width < 16) {
1513 /* FIXME. There is a bug with accelerated color-expanded
1514 * transfers in 24 bit mode if the image being transferred
1515 * is less than 16 bits wide. This is due to insufficient
1516 * padding when writing the image. We need to adjust
1517 * struct fb_pixmap. Not yet done. */
1518 return cfb_imageblit(info, image);
1519 }
1520 bltCntl_flags = NEO_BC0_SRC_MONO;
1521 } else if (image->depth == info->var.bits_per_pixel) {
1522 bltCntl_flags = 0;
1523 } else {
1524 /* We don't currently support hardware acceleration if image
1525 * depth is different from display */
1526 return cfb_imageblit(info, image);
1527 }
1528
1529 switch (info->var.bits_per_pixel) {
1530 case 8:
1531 writel(image->fg_color, &par->neo2200->fgColor);
1532 writel(image->bg_color, &par->neo2200->bgColor);
1533 break;
1534 case 16:
1535 case 24:
1536 writel(((u32 *) (info->pseudo_palette))[image->fg_color],
1537 &par->neo2200->fgColor);
1538 writel(((u32 *) (info->pseudo_palette))[image->bg_color],
1539 &par->neo2200->bgColor);
1540 break;
1541 }
1542
1543 writel(NEO_BC0_SYS_TO_VID |
1544 NEO_BC3_SKIP_MAPPING | bltCntl_flags |
1545 // NEO_BC3_DST_XY_ADDR |
1546 0x0c0000, &par->neo2200->bltCntl);
1547
1548 writel(0, &par->neo2200->srcStart);
1549// par->neo2200->dstStart = (image->dy << 16) | (image->dx & 0xffff);
1550 writel(((image->dx & 0xffff) * (info->var.bits_per_pixel >> 3) +
1551 image->dy * info->fix.line_length), &par->neo2200->dstStart);
1552 writel((image->height << 16) | (image->width & 0xffff),
1553 &par->neo2200->xyExt);
1554
1555 memcpy_toio(par->mmio_vbase + 0x100000, image->data, data_len);
1556}
1557
1558static void
1559neofb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1560{
1561 switch (info->fix.accel) {
1562 case FB_ACCEL_NEOMAGIC_NM2200:
1563 case FB_ACCEL_NEOMAGIC_NM2230:
1564 case FB_ACCEL_NEOMAGIC_NM2360:
1565 case FB_ACCEL_NEOMAGIC_NM2380:
1566 neo2200_fillrect(info, rect);
1567 break;
1568 default:
1569 cfb_fillrect(info, rect);
1570 break;
1571 }
1572}
1573
1574static void
1575neofb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1576{
1577 switch (info->fix.accel) {
1578 case FB_ACCEL_NEOMAGIC_NM2200:
1579 case FB_ACCEL_NEOMAGIC_NM2230:
1580 case FB_ACCEL_NEOMAGIC_NM2360:
1581 case FB_ACCEL_NEOMAGIC_NM2380:
1582 neo2200_copyarea(info, area);
1583 break;
1584 default:
1585 cfb_copyarea(info, area);
1586 break;
1587 }
1588}
1589
1590static void
1591neofb_imageblit(struct fb_info *info, const struct fb_image *image)
1592{
1593 switch (info->fix.accel) {
1594 case FB_ACCEL_NEOMAGIC_NM2200:
1595 case FB_ACCEL_NEOMAGIC_NM2230:
1596 case FB_ACCEL_NEOMAGIC_NM2360:
1597 case FB_ACCEL_NEOMAGIC_NM2380:
1598 neo2200_imageblit(info, image);
1599 break;
1600 default:
1601 cfb_imageblit(info, image);
1602 break;
1603 }
1604}
1605
1606static int
1607neofb_sync(struct fb_info *info)
1608{
1609 switch (info->fix.accel) {
1610 case FB_ACCEL_NEOMAGIC_NM2200:
1611 case FB_ACCEL_NEOMAGIC_NM2230:
1612 case FB_ACCEL_NEOMAGIC_NM2360:
1613 case FB_ACCEL_NEOMAGIC_NM2380:
1614 neo2200_sync(info);
1615 break;
1616 default:
1617 break;
1618 }
1619 return 0;
1620}
1621
1622/*
1623static void
1624neofb_draw_cursor(struct fb_info *info, u8 *dst, u8 *src, unsigned int width)
1625{
1626 //memset_io(info->sprite.addr, 0xff, 1);
1627}
1628
1629static int
1630neofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1631{
1632 struct neofb_par *par = (struct neofb_par *) info->par;
1633
1634 * Disable cursor *
1635 write_le32(NEOREG_CURSCNTL, ~NEO_CURS_ENABLE, par);
1636
1637 if (cursor->set & FB_CUR_SETPOS) {
1638 u32 x = cursor->image.dx;
1639 u32 y = cursor->image.dy;
1640
1641 info->cursor.image.dx = x;
1642 info->cursor.image.dy = y;
1643 write_le32(NEOREG_CURSX, x, par);
1644 write_le32(NEOREG_CURSY, y, par);
1645 }
1646
1647 if (cursor->set & FB_CUR_SETSIZE) {
1648 info->cursor.image.height = cursor->image.height;
1649 info->cursor.image.width = cursor->image.width;
1650 }
1651
1652 if (cursor->set & FB_CUR_SETHOT)
1653 info->cursor.hot = cursor->hot;
1654
1655 if (cursor->set & FB_CUR_SETCMAP) {
1656 if (cursor->image.depth == 1) {
1657 u32 fg = cursor->image.fg_color;
1658 u32 bg = cursor->image.bg_color;
1659
1660 info->cursor.image.fg_color = fg;
1661 info->cursor.image.bg_color = bg;
1662
1663 fg = ((fg & 0xff0000) >> 16) | ((fg & 0xff) << 16) | (fg & 0xff00);
1664 bg = ((bg & 0xff0000) >> 16) | ((bg & 0xff) << 16) | (bg & 0xff00);
1665 write_le32(NEOREG_CURSFGCOLOR, fg, par);
1666 write_le32(NEOREG_CURSBGCOLOR, bg, par);
1667 }
1668 }
1669
1670 if (cursor->set & FB_CUR_SETSHAPE)
1671 fb_load_cursor_image(info);
1672
1673 if (info->cursor.enable)
1674 write_le32(NEOREG_CURSCNTL, NEO_CURS_ENABLE, par);
1675 return 0;
1676}
1677*/
1678
1679static struct fb_ops neofb_ops = {
1680 .owner = THIS_MODULE,
1681 .fb_open = neofb_open,
1682 .fb_release = neofb_release,
1683 .fb_check_var = neofb_check_var,
1684 .fb_set_par = neofb_set_par,
1685 .fb_setcolreg = neofb_setcolreg,
1686 .fb_pan_display = neofb_pan_display,
1687 .fb_blank = neofb_blank,
1688 .fb_sync = neofb_sync,
1689 .fb_fillrect = neofb_fillrect,
1690 .fb_copyarea = neofb_copyarea,
1691 .fb_imageblit = neofb_imageblit,
1da177e4
LT		 1692};
1693
1694/* --------------------------------------------------------------------- */
1695
1696static struct fb_videomode __devinitdata mode800x480 = {
1697 .xres = 800,
1698 .yres = 480,
1699 .pixclock = 25000,
1700 .left_margin = 88,
1701 .right_margin = 40,
1702 .upper_margin = 23,
1703 .lower_margin = 1,
1704 .hsync_len = 128,
1705 .vsync_len = 4,
1706 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1707 .vmode = FB_VMODE_NONINTERLACED
1708};
1709
1710static int __devinit neo_map_mmio(struct fb_info *info,
1711 struct pci_dev *dev)
1712{
9f19bc56 1713 struct neofb_par *par = info->par;
1da177e4
LT		 1714
1715 DBG("neo_map_mmio");
1716
1717 switch (info->fix.accel) {
1718 case FB_ACCEL_NEOMAGIC_NM2070:
1719 info->fix.mmio_start = pci_resource_start(dev, 0)+
1720 0x100000;
1721 break;
1722 case FB_ACCEL_NEOMAGIC_NM2090:
1723 case FB_ACCEL_NEOMAGIC_NM2093:
1724 info->fix.mmio_start = pci_resource_start(dev, 0)+
1725 0x200000;
1726 break;
1727 case FB_ACCEL_NEOMAGIC_NM2160:
1728 case FB_ACCEL_NEOMAGIC_NM2097:
1729 case FB_ACCEL_NEOMAGIC_NM2200:
1730 case FB_ACCEL_NEOMAGIC_NM2230:
1731 case FB_ACCEL_NEOMAGIC_NM2360:
1732 case FB_ACCEL_NEOMAGIC_NM2380:
1733 info->fix.mmio_start = pci_resource_start(dev, 1);
1734 break;
1735 default:
1736 info->fix.mmio_start = pci_resource_start(dev, 0);
1737 }
1738 info->fix.mmio_len = MMIO_SIZE;
1739
1740 if (!request_mem_region
1741 (info->fix.mmio_start, MMIO_SIZE, "memory mapped I/O")) {
1742 printk("neofb: memory mapped IO in use\n");
1743 return -EBUSY;
1744 }
1745
1746 par->mmio_vbase = ioremap(info->fix.mmio_start, MMIO_SIZE);
1747 if (!par->mmio_vbase) {
1748 printk("neofb: unable to map memory mapped IO\n");
1749 release_mem_region(info->fix.mmio_start,
1750 info->fix.mmio_len);
1751 return -ENOMEM;
1752 } else
1753 printk(KERN_INFO "neofb: mapped io at %p\n",
1754 par->mmio_vbase);
1755 return 0;
1756}
1757
1758static void neo_unmap_mmio(struct fb_info *info)
1759{
9f19bc56 1760 struct neofb_par *par = info->par;
1da177e4
LT		 1761
1762 DBG("neo_unmap_mmio");
1763
1764 iounmap(par->mmio_vbase);
1765 par->mmio_vbase = NULL;
1766
1767 release_mem_region(info->fix.mmio_start,
1768 info->fix.mmio_len);
1769}
1770
1771static int __devinit neo_map_video(struct fb_info *info,
1772 struct pci_dev *dev, int video_len)
1773{
1774 //unsigned long addr;
1775
1776 DBG("neo_map_video");
1777
1778 info->fix.smem_start = pci_resource_start(dev, 0);
1779 info->fix.smem_len = video_len;
1780
1781 if (!request_mem_region(info->fix.smem_start, info->fix.smem_len,
1782 "frame buffer")) {
1783 printk("neofb: frame buffer in use\n");
1784 return -EBUSY;
1785 }
1786
1787 info->screen_base =
1788 ioremap(info->fix.smem_start, info->fix.smem_len);
1789 if (!info->screen_base) {
1790 printk("neofb: unable to map screen memory\n");
1791 release_mem_region(info->fix.smem_start,
1792 info->fix.smem_len);
1793 return -ENOMEM;
1794 } else
1795 printk(KERN_INFO "neofb: mapped framebuffer at %p\n",
1796 info->screen_base);
1797
1798#ifdef CONFIG_MTRR
1799 ((struct neofb_par *)(info->par))->mtrr =
1800 mtrr_add(info->fix.smem_start, pci_resource_len(dev, 0),
1801 MTRR_TYPE_WRCOMB, 1);
1802#endif
1803
1804 /* Clear framebuffer, it's all white in memory after boot */
1805 memset_io(info->screen_base, 0, info->fix.smem_len);
1806
1807 /* Allocate Cursor drawing pad.
1808 info->fix.smem_len -= PAGE_SIZE;
1809 addr = info->fix.smem_start + info->fix.smem_len;
1810 write_le32(NEOREG_CURSMEMPOS, ((0x000f & (addr >> 10)) << 8) |
1811 ((0x0ff0 & (addr >> 10)) >> 4), par);
1812 addr = (unsigned long) info->screen_base + info->fix.smem_len;
1813 info->sprite.addr = (u8 *) addr; */
1814 return 0;
1815}
1816
1817static void neo_unmap_video(struct fb_info *info)
1818{
1819 DBG("neo_unmap_video");
1820
1821#ifdef CONFIG_MTRR
1822 {
9f19bc56 1823 struct neofb_par *par = info->par;
1da177e4
LT		 1824
1825 mtrr_del(par->mtrr, info->fix.smem_start,
1826 info->fix.smem_len);
1827 }
1828#endif
1829 iounmap(info->screen_base);
1830 info->screen_base = NULL;
1831
1832 release_mem_region(info->fix.smem_start,
1833 info->fix.smem_len);
1834}
1835
1836static int __devinit neo_scan_monitor(struct fb_info *info)
1837{
9f19bc56 1838 struct neofb_par *par = info->par;
1da177e4
LT		 1839 unsigned char type, display;
1840 int w;
1841
1842 // Eventually we will have i2c support.
1843 info->monspecs.modedb = kmalloc(sizeof(struct fb_videomode), GFP_KERNEL);
1844 if (!info->monspecs.modedb)
1845 return -ENOMEM;
1846 info->monspecs.modedb_len = 1;
1847
1848 /* Determine the panel type */
1849 vga_wgfx(NULL, 0x09, 0x26);
1850 type = vga_rgfx(NULL, 0x21);
1851 display = vga_rgfx(NULL, 0x20);
1852 if (!par->internal_display && !par->external_display) {
1853 par->internal_display = display & 2 || !(display & 3) ? 1 : 0;
1854 par->external_display = display & 1;
1855 printk (KERN_INFO "Autodetected %s display\n",
1856 par->internal_display && par->external_display ? "simultaneous" :
1857 par->internal_display ? "internal" : "external");
1858 }
1859
1860 /* Determine panel width -- used in NeoValidMode. */
1861 w = vga_rgfx(NULL, 0x20);
1862 vga_wgfx(NULL, 0x09, 0x00);
1863 switch ((w & 0x18) >> 3) {
1864 case 0x00:
1865 // 640x480@60
1866 par->NeoPanelWidth = 640;
1867 par->NeoPanelHeight = 480;
1868 memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
1869 break;
1870 case 0x01:
1871 par->NeoPanelWidth = 800;
1872 if (par->libretto) {
1873 par->NeoPanelHeight = 480;
1874 memcpy(info->monspecs.modedb, &mode800x480, sizeof(struct fb_videomode));
1875 } else {
1876 // 800x600@60
1877 par->NeoPanelHeight = 600;
1878 memcpy(info->monspecs.modedb, &vesa_modes[8], sizeof(struct fb_videomode));
1879 }
1880 break;
1881 case 0x02:
1882 // 1024x768@60
1883 par->NeoPanelWidth = 1024;
1884 par->NeoPanelHeight = 768;
1885 memcpy(info->monspecs.modedb, &vesa_modes[13], sizeof(struct fb_videomode));
1886 break;
1887 case 0x03:
1888 /* 1280x1024@60 panel support needs to be added */
1889#ifdef NOT_DONE
1890 par->NeoPanelWidth = 1280;
1891 par->NeoPanelHeight = 1024;
1892 memcpy(info->monspecs.modedb, &vesa_modes[20], sizeof(struct fb_videomode));
1893 break;
1894#else
1895 printk(KERN_ERR
1896 "neofb: Only 640x480, 800x600/480 and 1024x768 panels are currently supported\n");
1897 return -1;
1898#endif
1899 default:
1900 // 640x480@60
1901 par->NeoPanelWidth = 640;
1902 par->NeoPanelHeight = 480;
1903 memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
1904 break;
1905 }
1906
1907 printk(KERN_INFO "Panel is a %dx%d %s %s display\n",
1908 par->NeoPanelWidth,
1909 par->NeoPanelHeight,
1910 (type & 0x02) ? "color" : "monochrome",
1911 (type & 0x10) ? "TFT" : "dual scan");
1912 return 0;
1913}
1914
1915static int __devinit neo_init_hw(struct fb_info *info)
1916{
9f19bc56 1917 struct neofb_par *par = info->par;
1da177e4
LT		 1918 int videoRam = 896;
1919 int maxClock = 65000;
1920 int CursorMem = 1024;
1921 int CursorOff = 0x100;
1922 int linearSize = 1024;
1923 int maxWidth = 1024;
1924 int maxHeight = 1024;
1925
1926 DBG("neo_init_hw");
1927
1928 neoUnlock();
1929
1930#if 0
1931 printk(KERN_DEBUG "--- Neo extended register dump ---\n");
1932 for (int w = 0; w < 0x85; w++)
1933 printk(KERN_DEBUG "CR %p: %p\n", (void *) w,
4971bb70 1934 (void *) vga_rcrt(NULL, w));
1da177e4
LT		 1935 for (int w = 0; w < 0xC7; w++)
1936 printk(KERN_DEBUG "GR %p: %p\n", (void *) w,
1937 (void *) vga_rgfx(NULL, w));
1938#endif
1939 switch (info->fix.accel) {
1940 case FB_ACCEL_NEOMAGIC_NM2070:
1941 videoRam = 896;
1942 maxClock = 65000;
1943 CursorMem = 2048;
1944 CursorOff = 0x100;
1945 linearSize = 1024;
1946 maxWidth = 1024;
1947 maxHeight = 1024;
1948 break;
1949 case FB_ACCEL_NEOMAGIC_NM2090:
1950 case FB_ACCEL_NEOMAGIC_NM2093:
1951 videoRam = 1152;
1952 maxClock = 80000;
1953 CursorMem = 2048;
1954 CursorOff = 0x100;
1955 linearSize = 2048;
1956 maxWidth = 1024;
1957 maxHeight = 1024;
1958 break;
1959 case FB_ACCEL_NEOMAGIC_NM2097:
1960 videoRam = 1152;
1961 maxClock = 80000;
1962 CursorMem = 1024;
1963 CursorOff = 0x100;
1964 linearSize = 2048;
1965 maxWidth = 1024;
1966 maxHeight = 1024;
1967 break;
1968 case FB_ACCEL_NEOMAGIC_NM2160:
1969 videoRam = 2048;
1970 maxClock = 90000;
1971 CursorMem = 1024;
1972 CursorOff = 0x100;
1973 linearSize = 2048;
1974 maxWidth = 1024;
1975 maxHeight = 1024;
1976 break;
1977 case FB_ACCEL_NEOMAGIC_NM2200:
1978 videoRam = 2560;
1979 maxClock = 110000;
1980 CursorMem = 1024;
1981 CursorOff = 0x1000;
1982 linearSize = 4096;
1983 maxWidth = 1280;
1984 maxHeight = 1024; /* ???? */
1985
1986 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
1987 break;
1988 case FB_ACCEL_NEOMAGIC_NM2230:
1989 videoRam = 3008;
1990 maxClock = 110000;
1991 CursorMem = 1024;
1992 CursorOff = 0x1000;
1993 linearSize = 4096;
1994 maxWidth = 1280;
1995 maxHeight = 1024; /* ???? */
1996
1997 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
1998 break;
1999 case FB_ACCEL_NEOMAGIC_NM2360:
2000 videoRam = 4096;
2001 maxClock = 110000;
2002 CursorMem = 1024;
2003 CursorOff = 0x1000;
2004 linearSize = 4096;
2005 maxWidth = 1280;
2006 maxHeight = 1024; /* ???? */
2007
2008 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
2009 break;
2010 case FB_ACCEL_NEOMAGIC_NM2380:
2011 videoRam = 6144;
2012 maxClock = 110000;
2013 CursorMem = 1024;
2014 CursorOff = 0x1000;
2015 linearSize = 8192;
2016 maxWidth = 1280;
2017 maxHeight = 1024; /* ???? */
2018
2019 par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
2020 break;
2021 }
2022/*
2023 info->sprite.size = CursorMem;
2024 info->sprite.scan_align = 1;
2025 info->sprite.buf_align = 1;
2026 info->sprite.flags = FB_PIXMAP_IO;
2027 info->sprite.outbuf = neofb_draw_cursor;
2028*/
2029 par->maxClock = maxClock;
2030 par->cursorOff = CursorOff;
2031 return ((videoRam * 1024));
2032}
2033
2034
2035static struct fb_info *__devinit neo_alloc_fb_info(struct pci_dev *dev, const struct
2036 pci_device_id *id)
2037{
2038 struct fb_info *info;
2039 struct neofb_par *par;
2040
9f19bc56 2041 info = framebuffer_alloc(sizeof(struct neofb_par), &dev->dev);
1da177e4
LT		 2042
2043 if (!info)
2044 return NULL;
2045
2046 par = info->par;
2047
2048 info->fix.accel = id->driver_data;
2049
2050 par->pci_burst = !nopciburst;
2051 par->lcd_stretch = !nostretch;
2052 par->libretto = libretto;
2053
2054 par->internal_display = internal;
2055 par->external_display = external;
2056 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
2057
2058 switch (info->fix.accel) {
2059 case FB_ACCEL_NEOMAGIC_NM2070:
2060 sprintf(info->fix.id, "MagicGraph 128");
2061 break;
2062 case FB_ACCEL_NEOMAGIC_NM2090:
2063 sprintf(info->fix.id, "MagicGraph 128V");
2064 break;
2065 case FB_ACCEL_NEOMAGIC_NM2093:
2066 sprintf(info->fix.id, "MagicGraph 128ZV");
2067 break;
2068 case FB_ACCEL_NEOMAGIC_NM2097:
2069 sprintf(info->fix.id, "MagicGraph 128ZV+");
2070 break;
2071 case FB_ACCEL_NEOMAGIC_NM2160:
2072 sprintf(info->fix.id, "MagicGraph 128XD");
2073 break;
2074 case FB_ACCEL_NEOMAGIC_NM2200:
2075 sprintf(info->fix.id, "MagicGraph 256AV");
2076 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2077 FBINFO_HWACCEL_COPYAREA |
2078 FBINFO_HWACCEL_FILLRECT;
2079 break;
2080 case FB_ACCEL_NEOMAGIC_NM2230:
2081 sprintf(info->fix.id, "MagicGraph 256AV+");
2082 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2083 FBINFO_HWACCEL_COPYAREA |
2084 FBINFO_HWACCEL_FILLRECT;
2085 break;
2086 case FB_ACCEL_NEOMAGIC_NM2360:
2087 sprintf(info->fix.id, "MagicGraph 256ZX");
2088 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2089 FBINFO_HWACCEL_COPYAREA |
2090 FBINFO_HWACCEL_FILLRECT;
2091 break;
2092 case FB_ACCEL_NEOMAGIC_NM2380:
2093 sprintf(info->fix.id, "MagicGraph 256XL+");
2094 info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
2095 FBINFO_HWACCEL_COPYAREA |
2096 FBINFO_HWACCEL_FILLRECT;
2097 break;
2098 }
2099
2100 info->fix.type = FB_TYPE_PACKED_PIXELS;
2101 info->fix.type_aux = 0;
2102 info->fix.xpanstep = 0;
2103 info->fix.ypanstep = 4;
2104 info->fix.ywrapstep = 0;
2105 info->fix.accel = id->driver_data;
2106
2107 info->fbops = &neofb_ops;
9f19bc56 2108 info->pseudo_palette = par->palette;
1da177e4
LT		 2109 return info;
2110}
2111
2112static void neo_free_fb_info(struct fb_info *info)
2113{
2114 if (info) {
2115 /*
2116 * Free the colourmap
2117 */
2118 fb_dealloc_cmap(&info->cmap);
2119 framebuffer_release(info);
2120 }
2121}
2122
2123/* --------------------------------------------------------------------- */
2124
2125static int __devinit neofb_probe(struct pci_dev *dev,
2126 const struct pci_device_id *id)
2127{
2128 struct fb_info *info;
2129 u_int h_sync, v_sync;
2130 int video_len, err;
2131
2132 DBG("neofb_probe");
2133
2134 err = pci_enable_device(dev);
2135 if (err)
2136 return err;
2137
2138 err = -ENOMEM;
2139 info = neo_alloc_fb_info(dev, id);
2140 if (!info)
2141 return err;
2142
2143 err = neo_map_mmio(info, dev);
2144 if (err)
2145 goto err_map_mmio;
2146
2147 err = neo_scan_monitor(info);
2148 if (err)
2149 goto err_scan_monitor;
2150
2151 video_len = neo_init_hw(info);
2152 if (video_len < 0) {
2153 err = video_len;
2154 goto err_init_hw;
2155 }
2156
2157 err = neo_map_video(info, dev, video_len);
2158 if (err)
2159 goto err_init_hw;
2160
2161 if (!fb_find_mode(&info->var, info, mode_option, NULL, 0,
2162 info->monspecs.modedb, 16)) {
2163 printk(KERN_ERR "neofb: Unable to find usable video mode.\n");
2164 goto err_map_video;
2165 }
2166
2167 /*
2168 * Calculate the hsync and vsync frequencies. Note that
2169 * we split the 1e12 constant up so that we can preserve
2170 * the precision and fit the results into 32-bit registers.
2171 * (1953125000 * 512 = 1e12)
2172 */
2173 h_sync = 1953125000 / info->var.pixclock;
2174 h_sync =
2175 h_sync * 512 / (info->var.xres + info->var.left_margin +
2176 info->var.right_margin + info->var.hsync_len);
2177 v_sync =
2178 h_sync / (info->var.yres + info->var.upper_margin +
2179 info->var.lower_margin + info->var.vsync_len);
2180
2181 printk(KERN_INFO "neofb v" NEOFB_VERSION
2182 ": %dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2183 info->fix.smem_len >> 10, info->var.xres,
2184 info->var.yres, h_sync / 1000, h_sync % 1000, v_sync);
2185
2186 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
2187 goto err_map_video;
2188
2189 err = register_framebuffer(info);
2190 if (err < 0)
2191 goto err_reg_fb;
2192
2193 printk(KERN_INFO "fb%d: %s frame buffer device\n",
2194 info->node, info->fix.id);
2195
2196 /*
2197 * Our driver data
2198 */
2199 pci_set_drvdata(dev, info);
2200 return 0;
2201
2202err_reg_fb:
2203 fb_dealloc_cmap(&info->cmap);
2204err_map_video:
2205 neo_unmap_video(info);
2206err_init_hw:
2207 fb_destroy_modedb(info->monspecs.modedb);
2208err_scan_monitor:
2209 neo_unmap_mmio(info);
2210err_map_mmio:
2211 neo_free_fb_info(info);
2212 return err;
2213}
2214
2215static void __devexit neofb_remove(struct pci_dev *dev)
2216{
2217 struct fb_info *info = pci_get_drvdata(dev);
2218
2219 DBG("neofb_remove");
2220
2221 if (info) {
2222 /*
2223 * If unregister_framebuffer fails, then
2224 * we will be leaving hooks that could cause
2225 * oopsen laying around.
2226 */
2227 if (unregister_framebuffer(info))
2228 printk(KERN_WARNING
2229 "neofb: danger danger! Oopsen imminent!\n");
2230
2231 neo_unmap_video(info);
2232 fb_destroy_modedb(info->monspecs.modedb);
2233 neo_unmap_mmio(info);
2234 neo_free_fb_info(info);
2235
2236 /*
2237 * Ensure that the driver data is no longer
2238 * valid.
2239 */
2240 pci_set_drvdata(dev, NULL);
2241 }
2242}
2243
2244static struct pci_device_id neofb_devices[] = {
2245 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2070,
2246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2070},
2247
2248 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2090,
2249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2090},
2250
2251 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2093,
2252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2093},
2253
2254 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2097,
2255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2097},
2256
2257 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2160,
2258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2160},
2259
2260 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2200,
2261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2200},
2262
2263 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2230,
2264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2230},
2265
2266 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2360,
2267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2360},
2268
2269 {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2380,
2270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2380},
2271
2272 {0, 0, 0, 0, 0, 0, 0}
2273};
2274
2275MODULE_DEVICE_TABLE(pci, neofb_devices);
2276
2277static struct pci_driver neofb_driver = {
2278 .name = "neofb",
2279 .id_table = neofb_devices,
2280 .probe = neofb_probe,
2281 .remove = __devexit_p(neofb_remove)
2282};
2283
2284/* ************************* init in-kernel code ************************** */
2285
2286#ifndef MODULE
2287static int __init neofb_setup(char *options)
2288{
2289 char *this_opt;
2290
2291 DBG("neofb_setup");
2292
2293 if (!options || !*options)
2294 return 0;
2295
2296 while ((this_opt = strsep(&options, ",")) != NULL) {
2297 if (!*this_opt)
2298 continue;
2299
2300 if (!strncmp(this_opt, "internal", 8))
2301 internal = 1;
2302 else if (!strncmp(this_opt, "external", 8))
2303 external = 1;
2304 else if (!strncmp(this_opt, "nostretch", 9))
2305 nostretch = 1;
2306 else if (!strncmp(this_opt, "nopciburst", 10))
2307 nopciburst = 1;
2308 else if (!strncmp(this_opt, "libretto", 8))
2309 libretto = 1;
2310 else
2311 mode_option = this_opt;
2312 }
2313 return 0;
2314}
2315#endif /* MODULE */
2316
2317static int __init neofb_init(void)
2318{
2319#ifndef MODULE
2320 char *option = NULL;
2321
2322 if (fb_get_options("neofb", &option))
2323 return -ENODEV;
2324 neofb_setup(option);
2325#endif
2326 return pci_register_driver(&neofb_driver);
2327}
2328
2329module_init(neofb_init);
2330
2331#ifdef MODULE
2332static void __exit neofb_exit(void)
2333{
2334 pci_unregister_driver(&neofb_driver);
2335}
2336
2337module_exit(neofb_exit);
2338#endif /* MODULE */
Linux kernel - Deliverables
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