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OMAPDSS: DISPC: pass pclk & lclk to calc_scaling
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
33366d0e 39#include <linux/sizes.h>
80c39712 40
a0b38cc4 41#include <video/omapdss.h>
80c39712
TV		 42
43#include "dss.h"
a0acb557 44#include "dss_features.h"
9b372c2d 45#include "dispc.h"
80c39712
TV		 46
47/* DISPC */
8613b000 48#define DISPC_SZ_REGS SZ_4K
80c39712 49
80c39712
TV		 50#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
51 DISPC_IRQ_OCP_ERR | \
52 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
53 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
54 DISPC_IRQ_SYNC_LOST | \
55 DISPC_IRQ_SYNC_LOST_DIGIT)
56
57#define DISPC_MAX_NR_ISRS 8
58
59struct omap_dispc_isr_data {
60 omap_dispc_isr_t isr;
61 void *arg;
62 u32 mask;
63};
64
5ed8cf5b
TV		 65enum omap_burst_size {
66 BURST_SIZE_X2 = 0,
67 BURST_SIZE_X4 = 1,
68 BURST_SIZE_X8 = 2,
69};
70
80c39712
TV		 71#define REG_GET(idx, start, end) \
72 FLD_GET(dispc_read_reg(idx), start, end)
73
74#define REG_FLD_MOD(idx, val, start, end) \
75 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
76
dfc0fd8d
TV		 77struct dispc_irq_stats {
78 unsigned long last_reset;
79 unsigned irq_count;
80 unsigned irqs[32];
81};
82
dcbe765b
CM		 83struct dispc_features {
84 u8 sw_start;
85 u8 fp_start;
86 u8 bp_start;
87 u16 sw_max;
88 u16 vp_max;
89 u16 hp_max;
33b89928
AT		 90 u8 mgr_width_start;
91 u8 mgr_height_start;
92 u16 mgr_width_max;
93 u16 mgr_height_max;
0c6921de 94 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 95 const struct omap_video_timings *mgr_timings,
96 u16 width, u16 height, u16 out_width, u16 out_height,
97 enum omap_color_mode color_mode, bool *five_taps,
98 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 99 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 100 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 101 u16 width, u16 height, u16 out_width, u16 out_height,
102 bool mem_to_mem);
42a6961c 103 u8 num_fifos;
66a0f9e4
TV		 104
105 /* swap GFX & WB fifos */
106 bool gfx_fifo_workaround:1;
cffa947d
TV		 107
108 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
109 bool no_framedone_tv:1;
dcbe765b
CM		 110};
111
42a6961c
TV		 112#define DISPC_MAX_NR_FIFOS 5
113
80c39712 114static struct {
060b6d9c 115 struct platform_device *pdev;
80c39712 116 void __iomem *base;
4fbafaf3
TV		 117
118 int ctx_loss_cnt;
119
affe360d 120 int irq;
4fbafaf3 121 struct clk *dss_clk;
80c39712 122
42a6961c
TV		 123 u32 fifo_size[DISPC_MAX_NR_FIFOS];
124 /* maps which plane is using a fifo. fifo-id -> plane-id */
125 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712
TV		 126
127 spinlock_t irq_lock;
128 u32 irq_error_mask;
129 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
130 u32 error_irqs;
131 struct work_struct error_work;
132
49ea86f3 133 bool ctx_valid;
80c39712 134 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 135
dcbe765b
CM		 136 const struct dispc_features *feat;
137
dfc0fd8d
TV		 138#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
139 spinlock_t irq_stats_lock;
140 struct dispc_irq_stats irq_stats;
141#endif
80c39712
TV		 142} dispc;
143
0d66cbb5
AJ		 144enum omap_color_component {
145 /* used for all color formats for OMAP3 and earlier
146 * and for RGB and Y color component on OMAP4
147 */
148 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
149 /* used for UV component for
150 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
151 * color formats on OMAP4
152 */
153 DISPC_COLOR_COMPONENT_UV = 1 << 1,
154};
155
efa70b3b
CM		 156enum mgr_reg_fields {
157 DISPC_MGR_FLD_ENABLE,
158 DISPC_MGR_FLD_STNTFT,
159 DISPC_MGR_FLD_GO,
160 DISPC_MGR_FLD_TFTDATALINES,
161 DISPC_MGR_FLD_STALLMODE,
162 DISPC_MGR_FLD_TCKENABLE,
163 DISPC_MGR_FLD_TCKSELECTION,
164 DISPC_MGR_FLD_CPR,
165 DISPC_MGR_FLD_FIFOHANDCHECK,
166 /* used to maintain a count of the above fields */
167 DISPC_MGR_FLD_NUM,
168};
169
170static const struct {
171 const char *name;
172 u32 vsync_irq;
173 u32 framedone_irq;
174 u32 sync_lost_irq;
175 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
176} mgr_desc[] = {
177 [OMAP_DSS_CHANNEL_LCD] = {
178 .name = "LCD",
179 .vsync_irq = DISPC_IRQ_VSYNC,
180 .framedone_irq = DISPC_IRQ_FRAMEDONE,
181 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
182 .reg_desc = {
183 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
184 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
185 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
186 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
187 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
188 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
189 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
190 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
191 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
192 },
193 },
194 [OMAP_DSS_CHANNEL_DIGIT] = {
195 .name = "DIGIT",
196 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 197 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 198 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
199 .reg_desc = {
200 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
201 [DISPC_MGR_FLD_STNTFT] = { },
202 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
203 [DISPC_MGR_FLD_TFTDATALINES] = { },
204 [DISPC_MGR_FLD_STALLMODE] = { },
205 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
206 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
207 [DISPC_MGR_FLD_CPR] = { },
208 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
209 },
210 },
211 [OMAP_DSS_CHANNEL_LCD2] = {
212 .name = "LCD2",
213 .vsync_irq = DISPC_IRQ_VSYNC2,
214 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
215 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
216 .reg_desc = {
217 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
218 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
219 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
220 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
221 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
222 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
223 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
224 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
225 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
226 },
227 },
e86d456a
CM		 228 [OMAP_DSS_CHANNEL_LCD3] = {
229 .name = "LCD3",
230 .vsync_irq = DISPC_IRQ_VSYNC3,
231 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
232 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
233 .reg_desc = {
234 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
235 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
236 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
237 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
238 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
239 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
240 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
241 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
242 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
243 },
244 },
efa70b3b
CM		 245};
246
6e5264b0
AT		 247struct color_conv_coef {
248 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
249 int full_range;
250};
251
80c39712 252static void _omap_dispc_set_irqs(void);
3e8a6ff2
AT		 253static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
254static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 255
55978cc2 256static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 257{
55978cc2 258 __raw_writel(val, dispc.base + idx);
80c39712
TV		 259}
260
55978cc2 261static inline u32 dispc_read_reg(const u16 idx)
80c39712 262{
55978cc2 263 return __raw_readl(dispc.base + idx);
80c39712
TV		 264}
265
efa70b3b
CM		 266static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
267{
268 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
269 return REG_GET(rfld.reg, rfld.high, rfld.low);
270}
271
272static void mgr_fld_write(enum omap_channel channel,
273 enum mgr_reg_fields regfld, int val) {
274 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
276}
277
80c39712 278#define SR(reg) \
55978cc2 279 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 280#define RR(reg) \
55978cc2 281 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 282
4fbafaf3 283static void dispc_save_context(void)
80c39712 284{
c6104b8e 285 int i, j;
80c39712 286
4fbafaf3
TV		 287 DSSDBG("dispc_save_context\n");
288
80c39712
TV		 289 SR(IRQENABLE);
290 SR(CONTROL);
291 SR(CONFIG);
80c39712 292 SR(LINE_NUMBER);
11354dd5
AT		 293 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
294 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 295 SR(GLOBAL_ALPHA);
2a205f34
SS		 296 if (dss_has_feature(FEAT_MGR_LCD2)) {
297 SR(CONTROL2);
2a205f34
SS		 298 SR(CONFIG2);
299 }
e86d456a
CM		 300 if (dss_has_feature(FEAT_MGR_LCD3)) {
301 SR(CONTROL3);
302 SR(CONFIG3);
303 }
80c39712 304
c6104b8e
AT		 305 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
306 SR(DEFAULT_COLOR(i));
307 SR(TRANS_COLOR(i));
308 SR(SIZE_MGR(i));
309 if (i == OMAP_DSS_CHANNEL_DIGIT)
310 continue;
311 SR(TIMING_H(i));
312 SR(TIMING_V(i));
313 SR(POL_FREQ(i));
314 SR(DIVISORo(i));
315
316 SR(DATA_CYCLE1(i));
317 SR(DATA_CYCLE2(i));
318 SR(DATA_CYCLE3(i));
319
332e9d70 320 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 321 SR(CPR_COEF_R(i));
322 SR(CPR_COEF_G(i));
323 SR(CPR_COEF_B(i));
332e9d70 324 }
2a205f34 325 }
80c39712 326
c6104b8e
AT		 327 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
328 SR(OVL_BA0(i));
329 SR(OVL_BA1(i));
330 SR(OVL_POSITION(i));
331 SR(OVL_SIZE(i));
332 SR(OVL_ATTRIBUTES(i));
333 SR(OVL_FIFO_THRESHOLD(i));
334 SR(OVL_ROW_INC(i));
335 SR(OVL_PIXEL_INC(i));
336 if (dss_has_feature(FEAT_PRELOAD))
337 SR(OVL_PRELOAD(i));
338 if (i == OMAP_DSS_GFX) {
339 SR(OVL_WINDOW_SKIP(i));
340 SR(OVL_TABLE_BA(i));
341 continue;
342 }
343 SR(OVL_FIR(i));
344 SR(OVL_PICTURE_SIZE(i));
345 SR(OVL_ACCU0(i));
346 SR(OVL_ACCU1(i));
9b372c2d 347
c6104b8e
AT		 348 for (j = 0; j < 8; j++)
349 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 350
c6104b8e
AT		 351 for (j = 0; j < 8; j++)
352 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 353
c6104b8e
AT		 354 for (j = 0; j < 5; j++)
355 SR(OVL_CONV_COEF(i, j));
ab5ca071 356
c6104b8e
AT		 357 if (dss_has_feature(FEAT_FIR_COEF_V)) {
358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_V(i, j));
360 }
9b372c2d 361
c6104b8e
AT		 362 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
363 SR(OVL_BA0_UV(i));
364 SR(OVL_BA1_UV(i));
365 SR(OVL_FIR2(i));
366 SR(OVL_ACCU2_0(i));
367 SR(OVL_ACCU2_1(i));
ab5ca071 368
c6104b8e
AT		 369 for (j = 0; j < 8; j++)
370 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 371
c6104b8e
AT		 372 for (j = 0; j < 8; j++)
373 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 374
c6104b8e
AT		 375 for (j = 0; j < 8; j++)
376 SR(OVL_FIR_COEF_V2(i, j));
377 }
378 if (dss_has_feature(FEAT_ATTR2))
379 SR(OVL_ATTRIBUTES2(i));
ab5ca071 380 }
0cf35df3
MR		 381
382 if (dss_has_feature(FEAT_CORE_CLK_DIV))
383 SR(DIVISOR);
49ea86f3 384
00928eaf 385 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 386 dispc.ctx_valid = true;
387
388 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 389}
390
4fbafaf3 391static void dispc_restore_context(void)
80c39712 392{
c6104b8e 393 int i, j, ctx;
4fbafaf3
TV		 394
395 DSSDBG("dispc_restore_context\n");
396
49ea86f3
TV		 397 if (!dispc.ctx_valid)
398 return;
399
00928eaf 400 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 401
402 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
403 return;
404
405 DSSDBG("ctx_loss_count: saved %d, current %d\n",
406 dispc.ctx_loss_cnt, ctx);
407
75c7d59d 408 /*RR(IRQENABLE);*/
80c39712
TV		 409 /*RR(CONTROL);*/
410 RR(CONFIG);
80c39712 411 RR(LINE_NUMBER);
11354dd5
AT		 412 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
413 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 414 RR(GLOBAL_ALPHA);
c6104b8e 415 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 416 RR(CONFIG2);
e86d456a
CM		 417 if (dss_has_feature(FEAT_MGR_LCD3))
418 RR(CONFIG3);
80c39712 419
c6104b8e
AT		 420 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
421 RR(DEFAULT_COLOR(i));
422 RR(TRANS_COLOR(i));
423 RR(SIZE_MGR(i));
424 if (i == OMAP_DSS_CHANNEL_DIGIT)
425 continue;
426 RR(TIMING_H(i));
427 RR(TIMING_V(i));
428 RR(POL_FREQ(i));
429 RR(DIVISORo(i));
430
431 RR(DATA_CYCLE1(i));
432 RR(DATA_CYCLE2(i));
433 RR(DATA_CYCLE3(i));
2a205f34 434
332e9d70 435 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 436 RR(CPR_COEF_R(i));
437 RR(CPR_COEF_G(i));
438 RR(CPR_COEF_B(i));
332e9d70 439 }
2a205f34 440 }
80c39712 441
c6104b8e
AT		 442 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
443 RR(OVL_BA0(i));
444 RR(OVL_BA1(i));
445 RR(OVL_POSITION(i));
446 RR(OVL_SIZE(i));
447 RR(OVL_ATTRIBUTES(i));
448 RR(OVL_FIFO_THRESHOLD(i));
449 RR(OVL_ROW_INC(i));
450 RR(OVL_PIXEL_INC(i));
451 if (dss_has_feature(FEAT_PRELOAD))
452 RR(OVL_PRELOAD(i));
453 if (i == OMAP_DSS_GFX) {
454 RR(OVL_WINDOW_SKIP(i));
455 RR(OVL_TABLE_BA(i));
456 continue;
457 }
458 RR(OVL_FIR(i));
459 RR(OVL_PICTURE_SIZE(i));
460 RR(OVL_ACCU0(i));
461 RR(OVL_ACCU1(i));
9b372c2d 462
c6104b8e
AT		 463 for (j = 0; j < 8; j++)
464 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 465
c6104b8e
AT		 466 for (j = 0; j < 8; j++)
467 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 468
c6104b8e
AT		 469 for (j = 0; j < 5; j++)
470 RR(OVL_CONV_COEF(i, j));
ab5ca071 471
c6104b8e
AT		 472 if (dss_has_feature(FEAT_FIR_COEF_V)) {
473 for (j = 0; j < 8; j++)
474 RR(OVL_FIR_COEF_V(i, j));
475 }
9b372c2d 476
c6104b8e
AT		 477 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
478 RR(OVL_BA0_UV(i));
479 RR(OVL_BA1_UV(i));
480 RR(OVL_FIR2(i));
481 RR(OVL_ACCU2_0(i));
482 RR(OVL_ACCU2_1(i));
ab5ca071 483
c6104b8e
AT		 484 for (j = 0; j < 8; j++)
485 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 486
c6104b8e
AT		 487 for (j = 0; j < 8; j++)
488 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 489
c6104b8e
AT		 490 for (j = 0; j < 8; j++)
491 RR(OVL_FIR_COEF_V2(i, j));
492 }
493 if (dss_has_feature(FEAT_ATTR2))
494 RR(OVL_ATTRIBUTES2(i));
ab5ca071 495 }
80c39712 496
0cf35df3
MR		 497 if (dss_has_feature(FEAT_CORE_CLK_DIV))
498 RR(DIVISOR);
499
80c39712
TV		 500 /* enable last, because LCD & DIGIT enable are here */
501 RR(CONTROL);
2a205f34
SS		 502 if (dss_has_feature(FEAT_MGR_LCD2))
503 RR(CONTROL2);
e86d456a
CM		 504 if (dss_has_feature(FEAT_MGR_LCD3))
505 RR(CONTROL3);
75c7d59d 506 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 507 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 508
509 /*
510 * enable last so IRQs won't trigger before
511 * the context is fully restored
512 */
513 RR(IRQENABLE);
49ea86f3
TV		 514
515 DSSDBG("context restored\n");
80c39712
TV		 516}
517
518#undef SR
519#undef RR
520
4fbafaf3
TV		 521int dispc_runtime_get(void)
522{
523 int r;
524
525 DSSDBG("dispc_runtime_get\n");
526
527 r = pm_runtime_get_sync(&dispc.pdev->dev);
528 WARN_ON(r < 0);
529 return r < 0 ? r : 0;
530}
531
532void dispc_runtime_put(void)
533{
534 int r;
535
536 DSSDBG("dispc_runtime_put\n");
537
0eaf9f52 538 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 539 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 540}
541
3dcec4d6
TV		 542u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
543{
efa70b3b 544 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 545}
546
7d1365c9
TV		 547u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
548{
cffa947d
TV		 549 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
550 return 0;
551
efa70b3b 552 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 553}
554
cb699200
TV		 555u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
556{
557 return mgr_desc[channel].sync_lost_irq;
558}
559
0b23e5b8
AT		 560u32 dispc_wb_get_framedone_irq(void)
561{
562 return DISPC_IRQ_FRAMEDONEWB;
563}
564
26d9dd0d 565bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 566{
efa70b3b 567 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 568}
569
26d9dd0d 570void dispc_mgr_go(enum omap_channel channel)
80c39712 571{
3c91ee8c
TV		 572 WARN_ON(dispc_mgr_is_enabled(channel) == false);
573 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 574
efa70b3b 575 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 576
efa70b3b 577 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 578}
579
0b23e5b8
AT		 580bool dispc_wb_go_busy(void)
581{
582 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
583}
584
585void dispc_wb_go(void)
586{
587 enum omap_plane plane = OMAP_DSS_WB;
588 bool enable, go;
589
590 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
591
592 if (!enable)
593 return;
594
595 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
596 if (go) {
597 DSSERR("GO bit not down for WB\n");
598 return;
599 }
600
601 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
602}
603
f0e5caab 604static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 605{
9b372c2d 606 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 607}
608
f0e5caab 609static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 610{
9b372c2d 611 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 612}
613
f0e5caab 614static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 615{
9b372c2d 616 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 617}
618
f0e5caab 619static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 620{
621 BUG_ON(plane == OMAP_DSS_GFX);
622
623 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
624}
625
f0e5caab
TV		 626static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
627 u32 value)
ab5ca071
AJ		 628{
629 BUG_ON(plane == OMAP_DSS_GFX);
630
631 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
632}
633
f0e5caab 634static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 635{
636 BUG_ON(plane == OMAP_DSS_GFX);
637
638 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
639}
640
debd9074
CM		 641static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
642 int fir_vinc, int five_taps,
643 enum omap_color_component color_comp)
80c39712 644{
debd9074 645 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 646 int i;
647
debd9074
CM		 648 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
649 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 650
651 for (i = 0; i < 8; i++) {
652 u32 h, hv;
653
debd9074
CM		 654 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
655 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
656 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
657 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
658 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
659 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
660 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
661 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 662
0d66cbb5 663 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 664 dispc_ovl_write_firh_reg(plane, i, h);
665 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 666 } else {
f0e5caab
TV		 667 dispc_ovl_write_firh2_reg(plane, i, h);
668 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 669 }
670
80c39712
TV		 671 }
672
66be8f6c
GI		 673 if (five_taps) {
674 for (i = 0; i < 8; i++) {
675 u32 v;
debd9074
CM		 676 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
677 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 678 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 679 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 680 else
f0e5caab 681 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 682 }
80c39712
TV		 683 }
684}
685
80c39712 686
6e5264b0
AT		 687static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
688 const struct color_conv_coef *ct)
689{
80c39712
TV		 690#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
691
6e5264b0
AT		 692 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
693 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
694 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
695 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
696 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 697
6e5264b0 698 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 699
700#undef CVAL
80c39712
TV		 701}
702
6e5264b0
AT		 703static void dispc_setup_color_conv_coef(void)
704{
705 int i;
706 int num_ovl = dss_feat_get_num_ovls();
707 int num_wb = dss_feat_get_num_wbs();
708 const struct color_conv_coef ctbl_bt601_5_ovl = {
709 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
710 };
711 const struct color_conv_coef ctbl_bt601_5_wb = {
712 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
713 };
714
715 for (i = 1; i < num_ovl; i++)
716 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
717
718 for (; i < num_wb; i++)
719 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
720}
80c39712 721
f0e5caab 722static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 723{
9b372c2d 724 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 725}
726
f0e5caab 727static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 728{
9b372c2d 729 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 730}
731
f0e5caab 732static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 733{
734 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
735}
736
f0e5caab 737static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 738{
739 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
740}
741
d79db853
AT		 742static void dispc_ovl_set_pos(enum omap_plane plane,
743 enum omap_overlay_caps caps, int x, int y)
80c39712 744{
d79db853
AT		 745 u32 val;
746
747 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
748 return;
749
750 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 751
752 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 753}
754
78b687fc
AT		 755static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
756 int height)
80c39712 757{
80c39712 758 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 759
36d87d95 760 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 761 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
762 else
763 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 764}
765
78b687fc
AT		 766static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
767 int height)
80c39712
TV		 768{
769 u32 val;
80c39712
TV		 770
771 BUG_ON(plane == OMAP_DSS_GFX);
772
773 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 774
36d87d95
AT		 775 if (plane == OMAP_DSS_WB)
776 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
777 else
778 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 779}
780
5b54ed3e
AT		 781static void dispc_ovl_set_zorder(enum omap_plane plane,
782 enum omap_overlay_caps caps, u8 zorder)
54128701 783{
5b54ed3e 784 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 785 return;
786
787 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
788}
789
790static void dispc_ovl_enable_zorder_planes(void)
791{
792 int i;
793
794 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
795 return;
796
797 for (i = 0; i < dss_feat_get_num_ovls(); i++)
798 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
799}
800
5b54ed3e
AT		 801static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
802 enum omap_overlay_caps caps, bool enable)
fd28a390 803{
5b54ed3e 804 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 805 return;
806
9b372c2d 807 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 808}
809
5b54ed3e
AT		 810static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
811 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 812{
b8c095b4 813 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 814 int shift;
815
5b54ed3e 816 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 817 return;
a0acb557 818
fe3cc9d6
TV		 819 shift = shifts[plane];
820 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 821}
822
f0e5caab 823static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 824{
9b372c2d 825 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 826}
827
f0e5caab 828static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 829{
9b372c2d 830 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 831}
832
f0e5caab 833static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 834 enum omap_color_mode color_mode)
835{
836 u32 m = 0;
f20e4220
AJ		 837 if (plane != OMAP_DSS_GFX) {
838 switch (color_mode) {
839 case OMAP_DSS_COLOR_NV12:
840 m = 0x0; break;
08f3267e 841 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 842 m = 0x1; break;
843 case OMAP_DSS_COLOR_RGBA16:
844 m = 0x2; break;
08f3267e 845 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 846 m = 0x4; break;
847 case OMAP_DSS_COLOR_ARGB16:
848 m = 0x5; break;
849 case OMAP_DSS_COLOR_RGB16:
850 m = 0x6; break;
851 case OMAP_DSS_COLOR_ARGB16_1555:
852 m = 0x7; break;
853 case OMAP_DSS_COLOR_RGB24U:
854 m = 0x8; break;
855 case OMAP_DSS_COLOR_RGB24P:
856 m = 0x9; break;
857 case OMAP_DSS_COLOR_YUV2:
858 m = 0xa; break;
859 case OMAP_DSS_COLOR_UYVY:
860 m = 0xb; break;
861 case OMAP_DSS_COLOR_ARGB32:
862 m = 0xc; break;
863 case OMAP_DSS_COLOR_RGBA32:
864 m = 0xd; break;
865 case OMAP_DSS_COLOR_RGBX32:
866 m = 0xe; break;
867 case OMAP_DSS_COLOR_XRGB16_1555:
868 m = 0xf; break;
869 default:
c6eee968 870 BUG(); return;
f20e4220
AJ		 871 }
872 } else {
873 switch (color_mode) {
874 case OMAP_DSS_COLOR_CLUT1:
875 m = 0x0; break;
876 case OMAP_DSS_COLOR_CLUT2:
877 m = 0x1; break;
878 case OMAP_DSS_COLOR_CLUT4:
879 m = 0x2; break;
880 case OMAP_DSS_COLOR_CLUT8:
881 m = 0x3; break;
882 case OMAP_DSS_COLOR_RGB12U:
883 m = 0x4; break;
884 case OMAP_DSS_COLOR_ARGB16:
885 m = 0x5; break;
886 case OMAP_DSS_COLOR_RGB16:
887 m = 0x6; break;
888 case OMAP_DSS_COLOR_ARGB16_1555:
889 m = 0x7; break;
890 case OMAP_DSS_COLOR_RGB24U:
891 m = 0x8; break;
892 case OMAP_DSS_COLOR_RGB24P:
893 m = 0x9; break;
08f3267e 894 case OMAP_DSS_COLOR_RGBX16:
f20e4220 895 m = 0xa; break;
08f3267e 896 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 897 m = 0xb; break;
898 case OMAP_DSS_COLOR_ARGB32:
899 m = 0xc; break;
900 case OMAP_DSS_COLOR_RGBA32:
901 m = 0xd; break;
902 case OMAP_DSS_COLOR_RGBX32:
903 m = 0xe; break;
904 case OMAP_DSS_COLOR_XRGB16_1555:
905 m = 0xf; break;
906 default:
c6eee968 907 BUG(); return;
f20e4220 908 }
80c39712
TV		 909 }
910
9b372c2d 911 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 912}
913
65e006ff
CM		 914static void dispc_ovl_configure_burst_type(enum omap_plane plane,
915 enum omap_dss_rotation_type rotation_type)
916{
917 if (dss_has_feature(FEAT_BURST_2D) == 0)
918 return;
919
920 if (rotation_type == OMAP_DSS_ROT_TILER)
921 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
922 else
923 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
924}
925
f427984e 926void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 927{
928 int shift;
929 u32 val;
2a205f34 930 int chan = 0, chan2 = 0;
80c39712
TV		 931
932 switch (plane) {
933 case OMAP_DSS_GFX:
934 shift = 8;
935 break;
936 case OMAP_DSS_VIDEO1:
937 case OMAP_DSS_VIDEO2:
b8c095b4 938 case OMAP_DSS_VIDEO3:
80c39712
TV		 939 shift = 16;
940 break;
941 default:
942 BUG();
943 return;
944 }
945
9b372c2d 946 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 947 if (dss_has_feature(FEAT_MGR_LCD2)) {
948 switch (channel) {
949 case OMAP_DSS_CHANNEL_LCD:
950 chan = 0;
951 chan2 = 0;
952 break;
953 case OMAP_DSS_CHANNEL_DIGIT:
954 chan = 1;
955 chan2 = 0;
956 break;
957 case OMAP_DSS_CHANNEL_LCD2:
958 chan = 0;
959 chan2 = 1;
960 break;
e86d456a
CM		 961 case OMAP_DSS_CHANNEL_LCD3:
962 if (dss_has_feature(FEAT_MGR_LCD3)) {
963 chan = 0;
964 chan2 = 2;
965 } else {
966 BUG();
967 return;
968 }
969 break;
2a205f34
SS		 970 default:
971 BUG();
c6eee968 972 return;
2a205f34
SS		 973 }
974
975 val = FLD_MOD(val, chan, shift, shift);
976 val = FLD_MOD(val, chan2, 31, 30);
977 } else {
978 val = FLD_MOD(val, channel, shift, shift);
979 }
9b372c2d 980 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 981}
982
2cc5d1af
TV		 983static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
984{
985 int shift;
986 u32 val;
987 enum omap_channel channel;
988
989 switch (plane) {
990 case OMAP_DSS_GFX:
991 shift = 8;
992 break;
993 case OMAP_DSS_VIDEO1:
994 case OMAP_DSS_VIDEO2:
995 case OMAP_DSS_VIDEO3:
996 shift = 16;
997 break;
998 default:
999 BUG();
c6eee968 1000 return 0;
2cc5d1af
TV		 1001 }
1002
1003 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1004
e86d456a
CM		 1005 if (dss_has_feature(FEAT_MGR_LCD3)) {
1006 if (FLD_GET(val, 31, 30) == 0)
1007 channel = FLD_GET(val, shift, shift);
1008 else if (FLD_GET(val, 31, 30) == 1)
1009 channel = OMAP_DSS_CHANNEL_LCD2;
1010 else
1011 channel = OMAP_DSS_CHANNEL_LCD3;
1012 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 1013 if (FLD_GET(val, 31, 30) == 0)
1014 channel = FLD_GET(val, shift, shift);
1015 else
1016 channel = OMAP_DSS_CHANNEL_LCD2;
1017 } else {
1018 channel = FLD_GET(val, shift, shift);
1019 }
1020
1021 return channel;
1022}
1023
d9ac773c
AT		 1024void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1025{
1026 enum omap_plane plane = OMAP_DSS_WB;
1027
1028 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1029}
1030
f0e5caab 1031static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1032 enum omap_burst_size burst_size)
1033{
8bbe09ee 1034 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1035 int shift;
80c39712 1036
fe3cc9d6 1037 shift = shifts[plane];
5ed8cf5b 1038 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1039}
1040
5ed8cf5b
TV		 1041static void dispc_configure_burst_sizes(void)
1042{
1043 int i;
1044 const int burst_size = BURST_SIZE_X8;
1045
1046 /* Configure burst size always to maximum size */
392faa0e 1047 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1048 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1049}
1050
83fa2f2e 1051static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1052{
1053 unsigned unit = dss_feat_get_burst_size_unit();
1054 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1055 return unit * 8;
1056}
1057
d3862610
M		 1058void dispc_enable_gamma_table(bool enable)
1059{
1060 /*
1061 * This is partially implemented to support only disabling of
1062 * the gamma table.
1063 */
1064 if (enable) {
1065 DSSWARN("Gamma table enabling for TV not yet supported");
1066 return;
1067 }
1068
1069 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1070}
1071
c64dca40 1072static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1073{
efa70b3b 1074 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1075 return;
1076
efa70b3b 1077 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1078}
1079
c64dca40 1080static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1081 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1082{
1083 u32 coef_r, coef_g, coef_b;
1084
dd88b7a6 1085 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1086 return;
1087
1088 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1089 FLD_VAL(coefs->rb, 9, 0);
1090 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1091 FLD_VAL(coefs->gb, 9, 0);
1092 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1093 FLD_VAL(coefs->bb, 9, 0);
1094
1095 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1096 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1097 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1098}
1099
f0e5caab 1100static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1101{
1102 u32 val;
1103
1104 BUG_ON(plane == OMAP_DSS_GFX);
1105
9b372c2d 1106 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1107 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1108 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1109}
1110
d79db853
AT		 1111static void dispc_ovl_enable_replication(enum omap_plane plane,
1112 enum omap_overlay_caps caps, bool enable)
80c39712 1113{
b8c095b4 1114 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1115 int shift;
80c39712 1116
d79db853
AT		 1117 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1118 return;
1119
fe3cc9d6
TV		 1120 shift = shifts[plane];
1121 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1122}
1123
8f366162 1124static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1125 u16 height)
80c39712
TV		 1126{
1127 u32 val;
80c39712 1128
33b89928
AT		 1129 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1130 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1131
8f366162 1132 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1133}
1134
42a6961c 1135static void dispc_init_fifos(void)
80c39712 1136{
80c39712 1137 u32 size;
42a6961c 1138 int fifo;
a0acb557 1139 u8 start, end;
5ed8cf5b
TV		 1140 u32 unit;
1141
1142 unit = dss_feat_get_buffer_size_unit();
80c39712 1143
a0acb557 1144 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1145
42a6961c
TV		 1146 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1147 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1148 size *= unit;
42a6961c
TV		 1149 dispc.fifo_size[fifo] = size;
1150
1151 /*
1152 * By default fifos are mapped directly to overlays, fifo 0 to
1153 * ovl 0, fifo 1 to ovl 1, etc.
1154 */
1155 dispc.fifo_assignment[fifo] = fifo;
80c39712 1156 }
66a0f9e4
TV		 1157
1158 /*
1159 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1160 * causes problems with certain use cases, like using the tiler in 2D
1161 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1162 * giving GFX plane a larger fifo. WB but should work fine with a
1163 * smaller fifo.
1164 */
1165 if (dispc.feat->gfx_fifo_workaround) {
1166 u32 v;
1167
1168 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1169
1170 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1171 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1172 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1173 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1174
1175 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1176
1177 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1178 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1179 }
80c39712
TV		 1180}
1181
83fa2f2e 1182static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1183{
42a6961c
TV		 1184 int fifo;
1185 u32 size = 0;
1186
1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1188 if (dispc.fifo_assignment[fifo] == plane)
1189 size += dispc.fifo_size[fifo];
1190 }
1191
1192 return size;
80c39712
TV		 1193}
1194
6f04e1bf 1195void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1196{
a0acb557 1197 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1198 u32 unit;
1199
1200 unit = dss_feat_get_buffer_size_unit();
1201
1202 WARN_ON(low % unit != 0);
1203 WARN_ON(high % unit != 0);
1204
1205 low /= unit;
1206 high /= unit;
a0acb557 1207
9b372c2d
AT		 1208 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1209 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1210
3cb5d966 1211 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1212 plane,
9b372c2d 1213 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1214 lo_start, lo_end) * unit,
9b372c2d 1215 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1216 hi_start, hi_end) * unit,
1217 low * unit, high * unit);
80c39712 1218
9b372c2d 1219 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1220 FLD_VAL(high, hi_start, hi_end) |
1221 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1222}
1223
1224void dispc_enable_fifomerge(bool enable)
1225{
e6b0f884
TV		 1226 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1227 WARN_ON(enable);
1228 return;
1229 }
1230
80c39712
TV		 1231 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1232 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1233}
1234
83fa2f2e 1235void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1236 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1237 bool manual_update)
83fa2f2e
TV		 1238{
1239 /*
1240 * All sizes are in bytes. Both the buffer and burst are made of
1241 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1242 */
1243
1244 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1245 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1246 int i;
83fa2f2e
TV		 1247
1248 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1249 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1250
e0e405b9
TV		 1251 if (use_fifomerge) {
1252 total_fifo_size = 0;
392faa0e 1253 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1254 total_fifo_size += dispc_ovl_get_fifo_size(i);
1255 } else {
1256 total_fifo_size = ovl_fifo_size;
1257 }
1258
1259 /*
1260 * We use the same low threshold for both fifomerge and non-fifomerge
1261 * cases, but for fifomerge we calculate the high threshold using the
1262 * combined fifo size
1263 */
1264
3568f2a4 1265 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1266 *fifo_low = ovl_fifo_size - burst_size * 2;
1267 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1268 } else if (plane == OMAP_DSS_WB) {
1269 /*
1270 * Most optimal configuration for writeback is to push out data
1271 * to the interconnect the moment writeback pushes enough pixels
1272 * in the FIFO to form a burst
1273 */
1274 *fifo_low = 0;
1275 *fifo_high = burst_size;
e0e405b9
TV		 1276 } else {
1277 *fifo_low = ovl_fifo_size - burst_size;
1278 *fifo_high = total_fifo_size - buf_unit;
1279 }
83fa2f2e
TV		 1280}
1281
f0e5caab 1282static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1283 int hinc, int vinc,
1284 enum omap_color_component color_comp)
80c39712
TV		 1285{
1286 u32 val;
80c39712 1287
0d66cbb5
AJ		 1288 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1289 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1290
0d66cbb5
AJ		 1291 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1292 &hinc_start, &hinc_end);
1293 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1294 &vinc_start, &vinc_end);
1295 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1296 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1297
0d66cbb5
AJ		 1298 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1299 } else {
1300 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1301 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1302 }
80c39712
TV		 1303}
1304
f0e5caab 1305static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1306{
1307 u32 val;
87a7484b 1308 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1309
87a7484b
AT		 1310 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1311 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1312
1313 val = FLD_VAL(vaccu, vert_start, vert_end) |
1314 FLD_VAL(haccu, hor_start, hor_end);
1315
9b372c2d 1316 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1317}
1318
f0e5caab 1319static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1320{
1321 u32 val;
87a7484b 1322 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1323
87a7484b
AT		 1324 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1325 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1326
1327 val = FLD_VAL(vaccu, vert_start, vert_end) |
1328 FLD_VAL(haccu, hor_start, hor_end);
1329
9b372c2d 1330 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1331}
1332
f0e5caab
TV		 1333static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1334 int vaccu)
ab5ca071
AJ		 1335{
1336 u32 val;
1337
1338 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1339 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1340}
1341
f0e5caab
TV		 1342static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1343 int vaccu)
ab5ca071
AJ		 1344{
1345 u32 val;
1346
1347 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1348 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1349}
80c39712 1350
f0e5caab 1351static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1352 u16 orig_width, u16 orig_height,
1353 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1354 bool five_taps, u8 rotation,
1355 enum omap_color_component color_comp)
80c39712 1356{
0d66cbb5 1357 int fir_hinc, fir_vinc;
80c39712 1358
ed14a3ce
AJ		 1359 fir_hinc = 1024 * orig_width / out_width;
1360 fir_vinc = 1024 * orig_height / out_height;
80c39712 1361
debd9074
CM		 1362 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1363 color_comp);
f0e5caab 1364 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1365}
1366
05dd0f53
CM		 1367static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1368 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1369 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1370{
1371 int h_accu2_0, h_accu2_1;
1372 int v_accu2_0, v_accu2_1;
1373 int chroma_hinc, chroma_vinc;
1374 int idx;
1375
1376 struct accu {
1377 s8 h0_m, h0_n;
1378 s8 h1_m, h1_n;
1379 s8 v0_m, v0_n;
1380 s8 v1_m, v1_n;
1381 };
1382
1383 const struct accu *accu_table;
1384 const struct accu *accu_val;
1385
1386 static const struct accu accu_nv12[4] = {
1387 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1388 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1389 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1390 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1391 };
1392
1393 static const struct accu accu_nv12_ilace[4] = {
1394 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1395 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1396 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1397 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1398 };
1399
1400 static const struct accu accu_yuv[4] = {
1401 { 0, 1, 0, 1, 0, 1, 0, 1 },
1402 { 0, 1, 0, 1, 0, 1, 0, 1 },
1403 { -1, 1, 0, 1, 0, 1, 0, 1 },
1404 { 0, 1, 0, 1, -1, 1, 0, 1 },
1405 };
1406
1407 switch (rotation) {
1408 case OMAP_DSS_ROT_0:
1409 idx = 0;
1410 break;
1411 case OMAP_DSS_ROT_90:
1412 idx = 1;
1413 break;
1414 case OMAP_DSS_ROT_180:
1415 idx = 2;
1416 break;
1417 case OMAP_DSS_ROT_270:
1418 idx = 3;
1419 break;
1420 default:
1421 BUG();
c6eee968 1422 return;
05dd0f53
CM		 1423 }
1424
1425 switch (color_mode) {
1426 case OMAP_DSS_COLOR_NV12:
1427 if (ilace)
1428 accu_table = accu_nv12_ilace;
1429 else
1430 accu_table = accu_nv12;
1431 break;
1432 case OMAP_DSS_COLOR_YUV2:
1433 case OMAP_DSS_COLOR_UYVY:
1434 accu_table = accu_yuv;
1435 break;
1436 default:
1437 BUG();
c6eee968 1438 return;
05dd0f53
CM		 1439 }
1440
1441 accu_val = &accu_table[idx];
1442
1443 chroma_hinc = 1024 * orig_width / out_width;
1444 chroma_vinc = 1024 * orig_height / out_height;
1445
1446 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1447 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1448 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1449 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1450
1451 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1452 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1453}
1454
f0e5caab 1455static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1456 u16 orig_width, u16 orig_height,
1457 u16 out_width, u16 out_height,
1458 bool ilace, bool five_taps,
1459 bool fieldmode, enum omap_color_mode color_mode,
1460 u8 rotation)
1461{
1462 int accu0 = 0;
1463 int accu1 = 0;
1464 u32 l;
80c39712 1465
f0e5caab 1466 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1467 out_width, out_height, five_taps,
1468 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1469 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1470
87a7484b
AT		 1471 /* RESIZEENABLE and VERTICALTAPS */
1472 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1473 l |= (orig_width != out_width) ? (1 << 5) : 0;
1474 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1475 l |= five_taps ? (1 << 21) : 0;
80c39712 1476
87a7484b
AT		 1477 /* VRESIZECONF and HRESIZECONF */
1478 if (dss_has_feature(FEAT_RESIZECONF)) {
1479 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1480 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1481 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1482 }
80c39712 1483
87a7484b
AT		 1484 /* LINEBUFFERSPLIT */
1485 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1486 l &= ~(0x1 << 22);
1487 l |= five_taps ? (1 << 22) : 0;
1488 }
80c39712 1489
9b372c2d 1490 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1491
1492 /*
1493 * field 0 = even field = bottom field
1494 * field 1 = odd field = top field
1495 */
1496 if (ilace && !fieldmode) {
1497 accu1 = 0;
0d66cbb5 1498 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1499 if (accu0 >= 1024/2) {
1500 accu1 = 1024/2;
1501 accu0 -= accu1;
1502 }
1503 }
1504
f0e5caab
TV		 1505 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1506 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1507}
1508
f0e5caab 1509static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1510 u16 orig_width, u16 orig_height,
1511 u16 out_width, u16 out_height,
1512 bool ilace, bool five_taps,
1513 bool fieldmode, enum omap_color_mode color_mode,
1514 u8 rotation)
1515{
1516 int scale_x = out_width != orig_width;
1517 int scale_y = out_height != orig_height;
f92afae2 1518 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1519
1520 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1521 return;
1522 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1523 color_mode != OMAP_DSS_COLOR_UYVY &&
1524 color_mode != OMAP_DSS_COLOR_NV12)) {
1525 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1526 if (plane != OMAP_DSS_WB)
1527 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1528 return;
1529 }
36377357
TV		 1530
1531 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1532 out_height, ilace, color_mode, rotation);
1533
0d66cbb5
AJ		 1534 switch (color_mode) {
1535 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1536 if (chroma_upscale) {
1537 /* UV is subsampled by 2 horizontally and vertically */
1538 orig_height >>= 1;
1539 orig_width >>= 1;
1540 } else {
1541 /* UV is downsampled by 2 horizontally and vertically */
1542 orig_height <<= 1;
1543 orig_width <<= 1;
1544 }
1545
0d66cbb5
AJ		 1546 break;
1547 case OMAP_DSS_COLOR_YUV2:
1548 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1549 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1550 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1551 rotation == OMAP_DSS_ROT_180) {
1552 if (chroma_upscale)
1553 /* UV is subsampled by 2 horizontally */
1554 orig_width >>= 1;
1555 else
1556 /* UV is downsampled by 2 horizontally */
1557 orig_width <<= 1;
1558 }
1559
0d66cbb5
AJ		 1560 /* must use FIR for YUV422 if rotated */
1561 if (rotation != OMAP_DSS_ROT_0)
1562 scale_x = scale_y = true;
20fbb50b 1563
0d66cbb5
AJ		 1564 break;
1565 default:
1566 BUG();
c6eee968 1567 return;
0d66cbb5
AJ		 1568 }
1569
1570 if (out_width != orig_width)
1571 scale_x = true;
1572 if (out_height != orig_height)
1573 scale_y = true;
1574
f0e5caab 1575 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1576 out_width, out_height, five_taps,
1577 rotation, DISPC_COLOR_COMPONENT_UV);
1578
2a5561b1
AT		 1579 if (plane != OMAP_DSS_WB)
1580 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1581 (scale_x || scale_y) ? 1 : 0, 8, 8);
1582
0d66cbb5
AJ		 1583 /* set H scaling */
1584 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1585 /* set V scaling */
1586 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1587}
1588
f0e5caab 1589static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1590 u16 orig_width, u16 orig_height,
1591 u16 out_width, u16 out_height,
1592 bool ilace, bool five_taps,
1593 bool fieldmode, enum omap_color_mode color_mode,
1594 u8 rotation)
1595{
1596 BUG_ON(plane == OMAP_DSS_GFX);
1597
f0e5caab 1598 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1599 orig_width, orig_height,
1600 out_width, out_height,
1601 ilace, five_taps,
1602 fieldmode, color_mode,
1603 rotation);
1604
f0e5caab 1605 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1606 orig_width, orig_height,
1607 out_width, out_height,
1608 ilace, five_taps,
1609 fieldmode, color_mode,
1610 rotation);
1611}
1612
f0e5caab 1613static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1614 bool mirroring, enum omap_color_mode color_mode)
1615{
87a7484b
AT		 1616 bool row_repeat = false;
1617 int vidrot = 0;
1618
80c39712
TV		 1619 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1621
1622 if (mirroring) {
1623 switch (rotation) {
1624 case OMAP_DSS_ROT_0:
1625 vidrot = 2;
1626 break;
1627 case OMAP_DSS_ROT_90:
1628 vidrot = 1;
1629 break;
1630 case OMAP_DSS_ROT_180:
1631 vidrot = 0;
1632 break;
1633 case OMAP_DSS_ROT_270:
1634 vidrot = 3;
1635 break;
1636 }
1637 } else {
1638 switch (rotation) {
1639 case OMAP_DSS_ROT_0:
1640 vidrot = 0;
1641 break;
1642 case OMAP_DSS_ROT_90:
1643 vidrot = 1;
1644 break;
1645 case OMAP_DSS_ROT_180:
1646 vidrot = 2;
1647 break;
1648 case OMAP_DSS_ROT_270:
1649 vidrot = 3;
1650 break;
1651 }
1652 }
1653
80c39712 1654 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1655 row_repeat = true;
80c39712 1656 else
87a7484b 1657 row_repeat = false;
80c39712 1658 }
87a7484b 1659
9b372c2d 1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1661 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1662 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1663 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1664}
1665
1666static int color_mode_to_bpp(enum omap_color_mode color_mode)
1667{
1668 switch (color_mode) {
1669 case OMAP_DSS_COLOR_CLUT1:
1670 return 1;
1671 case OMAP_DSS_COLOR_CLUT2:
1672 return 2;
1673 case OMAP_DSS_COLOR_CLUT4:
1674 return 4;
1675 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1676 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1677 return 8;
1678 case OMAP_DSS_COLOR_RGB12U:
1679 case OMAP_DSS_COLOR_RGB16:
1680 case OMAP_DSS_COLOR_ARGB16:
1681 case OMAP_DSS_COLOR_YUV2:
1682 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1683 case OMAP_DSS_COLOR_RGBA16:
1684 case OMAP_DSS_COLOR_RGBX16:
1685 case OMAP_DSS_COLOR_ARGB16_1555:
1686 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1687 return 16;
1688 case OMAP_DSS_COLOR_RGB24P:
1689 return 24;
1690 case OMAP_DSS_COLOR_RGB24U:
1691 case OMAP_DSS_COLOR_ARGB32:
1692 case OMAP_DSS_COLOR_RGBA32:
1693 case OMAP_DSS_COLOR_RGBX32:
1694 return 32;
1695 default:
1696 BUG();
c6eee968 1697 return 0;
80c39712
TV		 1698 }
1699}
1700
1701static s32 pixinc(int pixels, u8 ps)
1702{
1703 if (pixels == 1)
1704 return 1;
1705 else if (pixels > 1)
1706 return 1 + (pixels - 1) * ps;
1707 else if (pixels < 0)
1708 return 1 - (-pixels + 1) * ps;
1709 else
1710 BUG();
c6eee968 1711 return 0;
80c39712
TV		 1712}
1713
1714static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1715 u16 screen_width,
1716 u16 width, u16 height,
1717 enum omap_color_mode color_mode, bool fieldmode,
1718 unsigned int field_offset,
1719 unsigned *offset0, unsigned *offset1,
aed74b55 1720 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1721{
1722 u8 ps;
1723
1724 /* FIXME CLUT formats */
1725 switch (color_mode) {
1726 case OMAP_DSS_COLOR_CLUT1:
1727 case OMAP_DSS_COLOR_CLUT2:
1728 case OMAP_DSS_COLOR_CLUT4:
1729 case OMAP_DSS_COLOR_CLUT8:
1730 BUG();
1731 return;
1732 case OMAP_DSS_COLOR_YUV2:
1733 case OMAP_DSS_COLOR_UYVY:
1734 ps = 4;
1735 break;
1736 default:
1737 ps = color_mode_to_bpp(color_mode) / 8;
1738 break;
1739 }
1740
1741 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1742 width, height);
1743
1744 /*
1745 * field 0 = even field = bottom field
1746 * field 1 = odd field = top field
1747 */
1748 switch (rotation + mirror * 4) {
1749 case OMAP_DSS_ROT_0:
1750 case OMAP_DSS_ROT_180:
1751 /*
1752 * If the pixel format is YUV or UYVY divide the width
1753 * of the image by 2 for 0 and 180 degree rotation.
1754 */
1755 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1756 color_mode == OMAP_DSS_COLOR_UYVY)
1757 width = width >> 1;
1758 case OMAP_DSS_ROT_90:
1759 case OMAP_DSS_ROT_270:
1760 *offset1 = 0;
1761 if (field_offset)
1762 *offset0 = field_offset * screen_width * ps;
1763 else
1764 *offset0 = 0;
1765
aed74b55
CM		 1766 *row_inc = pixinc(1 +
1767 (y_predecim * screen_width - x_predecim * width) +
1768 (fieldmode ? screen_width : 0), ps);
1769 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1770 break;
1771
1772 case OMAP_DSS_ROT_0 + 4:
1773 case OMAP_DSS_ROT_180 + 4:
1774 /* If the pixel format is YUV or UYVY divide the width
1775 * of the image by 2 for 0 degree and 180 degree
1776 */
1777 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1778 color_mode == OMAP_DSS_COLOR_UYVY)
1779 width = width >> 1;
1780 case OMAP_DSS_ROT_90 + 4:
1781 case OMAP_DSS_ROT_270 + 4:
1782 *offset1 = 0;
1783 if (field_offset)
1784 *offset0 = field_offset * screen_width * ps;
1785 else
1786 *offset0 = 0;
aed74b55
CM		 1787 *row_inc = pixinc(1 -
1788 (y_predecim * screen_width + x_predecim * width) -
1789 (fieldmode ? screen_width : 0), ps);
1790 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1791 break;
1792
1793 default:
1794 BUG();
c6eee968 1795 return;
80c39712
TV		 1796 }
1797}
1798
1799static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1800 u16 screen_width,
1801 u16 width, u16 height,
1802 enum omap_color_mode color_mode, bool fieldmode,
1803 unsigned int field_offset,
1804 unsigned *offset0, unsigned *offset1,
aed74b55 1805 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1806{
1807 u8 ps;
1808 u16 fbw, fbh;
1809
1810 /* FIXME CLUT formats */
1811 switch (color_mode) {
1812 case OMAP_DSS_COLOR_CLUT1:
1813 case OMAP_DSS_COLOR_CLUT2:
1814 case OMAP_DSS_COLOR_CLUT4:
1815 case OMAP_DSS_COLOR_CLUT8:
1816 BUG();
1817 return;
1818 default:
1819 ps = color_mode_to_bpp(color_mode) / 8;
1820 break;
1821 }
1822
1823 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1824 width, height);
1825
1826 /* width & height are overlay sizes, convert to fb sizes */
1827
1828 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1829 fbw = width;
1830 fbh = height;
1831 } else {
1832 fbw = height;
1833 fbh = width;
1834 }
1835
1836 /*
1837 * field 0 = even field = bottom field
1838 * field 1 = odd field = top field
1839 */
1840 switch (rotation + mirror * 4) {
1841 case OMAP_DSS_ROT_0:
1842 *offset1 = 0;
1843 if (field_offset)
1844 *offset0 = *offset1 + field_offset * screen_width * ps;
1845 else
1846 *offset0 = *offset1;
aed74b55
CM		 1847 *row_inc = pixinc(1 +
1848 (y_predecim * screen_width - fbw * x_predecim) +
1849 (fieldmode ? screen_width : 0), ps);
1850 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1851 color_mode == OMAP_DSS_COLOR_UYVY)
1852 *pix_inc = pixinc(x_predecim, 2 * ps);
1853 else
1854 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1855 break;
1856 case OMAP_DSS_ROT_90:
1857 *offset1 = screen_width * (fbh - 1) * ps;
1858 if (field_offset)
1859 *offset0 = *offset1 + field_offset * ps;
1860 else
1861 *offset0 = *offset1;
aed74b55
CM		 1862 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1863 y_predecim + (fieldmode ? 1 : 0), ps);
1864 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1865 break;
1866 case OMAP_DSS_ROT_180:
1867 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1868 if (field_offset)
1869 *offset0 = *offset1 - field_offset * screen_width * ps;
1870 else
1871 *offset0 = *offset1;
1872 *row_inc = pixinc(-1 -
aed74b55
CM		 1873 (y_predecim * screen_width - fbw * x_predecim) -
1874 (fieldmode ? screen_width : 0), ps);
1875 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1876 color_mode == OMAP_DSS_COLOR_UYVY)
1877 *pix_inc = pixinc(-x_predecim, 2 * ps);
1878 else
1879 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1880 break;
1881 case OMAP_DSS_ROT_270:
1882 *offset1 = (fbw - 1) * ps;
1883 if (field_offset)
1884 *offset0 = *offset1 - field_offset * ps;
1885 else
1886 *offset0 = *offset1;
aed74b55
CM		 1887 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1888 y_predecim - (fieldmode ? 1 : 0), ps);
1889 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1890 break;
1891
1892 /* mirroring */
1893 case OMAP_DSS_ROT_0 + 4:
1894 *offset1 = (fbw - 1) * ps;
1895 if (field_offset)
1896 *offset0 = *offset1 + field_offset * screen_width * ps;
1897 else
1898 *offset0 = *offset1;
aed74b55 1899 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1900 (fieldmode ? screen_width : 0),
1901 ps);
aed74b55
CM		 1902 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1903 color_mode == OMAP_DSS_COLOR_UYVY)
1904 *pix_inc = pixinc(-x_predecim, 2 * ps);
1905 else
1906 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1907 break;
1908
1909 case OMAP_DSS_ROT_90 + 4:
1910 *offset1 = 0;
1911 if (field_offset)
1912 *offset0 = *offset1 + field_offset * ps;
1913 else
1914 *offset0 = *offset1;
aed74b55
CM		 1915 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1916 y_predecim + (fieldmode ? 1 : 0),
80c39712 1917 ps);
aed74b55 1918 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1919 break;
1920
1921 case OMAP_DSS_ROT_180 + 4:
1922 *offset1 = screen_width * (fbh - 1) * ps;
1923 if (field_offset)
1924 *offset0 = *offset1 - field_offset * screen_width * ps;
1925 else
1926 *offset0 = *offset1;
aed74b55 1927 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1928 (fieldmode ? screen_width : 0),
1929 ps);
aed74b55
CM		 1930 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1931 color_mode == OMAP_DSS_COLOR_UYVY)
1932 *pix_inc = pixinc(x_predecim, 2 * ps);
1933 else
1934 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1935 break;
1936
1937 case OMAP_DSS_ROT_270 + 4:
1938 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1939 if (field_offset)
1940 *offset0 = *offset1 - field_offset * ps;
1941 else
1942 *offset0 = *offset1;
aed74b55
CM		 1943 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1944 y_predecim - (fieldmode ? 1 : 0),
80c39712 1945 ps);
aed74b55 1946 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1947 break;
1948
1949 default:
1950 BUG();
c6eee968 1951 return;
80c39712
TV		 1952 }
1953}
1954
65e006ff
CM		 1955static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1956 enum omap_color_mode color_mode, bool fieldmode,
1957 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1958 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1959{
1960 u8 ps;
1961
1962 switch (color_mode) {
1963 case OMAP_DSS_COLOR_CLUT1:
1964 case OMAP_DSS_COLOR_CLUT2:
1965 case OMAP_DSS_COLOR_CLUT4:
1966 case OMAP_DSS_COLOR_CLUT8:
1967 BUG();
1968 return;
1969 default:
1970 ps = color_mode_to_bpp(color_mode) / 8;
1971 break;
1972 }
1973
1974 DSSDBG("scrw %d, width %d\n", screen_width, width);
1975
1976 /*
1977 * field 0 = even field = bottom field
1978 * field 1 = odd field = top field
1979 */
1980 *offset1 = 0;
1981 if (field_offset)
1982 *offset0 = *offset1 + field_offset * screen_width * ps;
1983 else
1984 *offset0 = *offset1;
1985 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1986 (fieldmode ? screen_width : 0), ps);
1987 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1988 color_mode == OMAP_DSS_COLOR_UYVY)
1989 *pix_inc = pixinc(x_predecim, 2 * ps);
1990 else
1991 *pix_inc = pixinc(x_predecim, ps);
1992}
1993
7faa9233
CM		 1994/*
1995 * This function is used to avoid synclosts in OMAP3, because of some
1996 * undocumented horizontal position and timing related limitations.
1997 */
465ec13f 1998static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 1999 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 2000 u16 width, u16 height, u16 out_width, u16 out_height)
2001{
230edc03 2002 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2003 unsigned long nonactive;
7faa9233
CM		 2004 static const u8 limits[3] = { 8, 10, 20 };
2005 u64 val, blank;
2006 int i;
2007
81ab95b7 2008 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2009
2010 i = 0;
2011 if (out_height < height)
2012 i++;
2013 if (out_width < width)
2014 i++;
81ab95b7 2015 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2016 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2017 if (blank <= limits[i])
2018 return -EINVAL;
2019
2020 /*
2021 * Pixel data should be prepared before visible display point starts.
2022 * So, atleast DS-2 lines must have already been fetched by DISPC
2023 * during nonactive - pos_x period.
2024 */
2025 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2026 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2027 val, max(0, ds - 2) * width);
2028 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2029 return -EINVAL;
2030
2031 /*
2032 * All lines need to be refilled during the nonactive period of which
2033 * only one line can be loaded during the active period. So, atleast
2034 * DS - 1 lines should be loaded during nonactive period.
2035 */
2036 val = div_u64((u64)nonactive * lclk, pclk);
2037 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2038 val, max(0, ds - 1) * width);
2039 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2040 return -EINVAL;
2041
2042 return 0;
2043}
2044
8702ee50 2045static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2046 const struct omap_video_timings *mgr_timings, u16 width,
2047 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2048 enum omap_color_mode color_mode)
80c39712 2049{
8b53d991 2050 u32 core_clk = 0;
3e8a6ff2 2051 u64 tmp;
80c39712 2052
7282f1b7
CM		 2053 if (height <= out_height && width <= out_width)
2054 return (unsigned long) pclk;
2055
80c39712 2056 if (height > out_height) {
81ab95b7 2057 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2058
2059 tmp = pclk * height * out_width;
2060 do_div(tmp, 2 * out_height * ppl);
8b53d991 2061 core_clk = tmp;
80c39712 2062
2d9c5597
VS		 2063 if (height > 2 * out_height) {
2064 if (ppl == out_width)
2065 return 0;
2066
80c39712
TV		 2067 tmp = pclk * (height - 2 * out_height) * out_width;
2068 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2069 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2070 }
2071 }
2072
2073 if (width > out_width) {
2074 tmp = pclk * width;
2075 do_div(tmp, out_width);
8b53d991 2076 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2077
2078 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2079 core_clk <<= 1;
80c39712
TV		 2080 }
2081
8b53d991 2082 return core_clk;
80c39712
TV		 2083}
2084
8702ee50 2085static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2086 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2087{
dcbe765b
CM		 2088 if (height > out_height && width > out_width)
2089 return pclk * 4;
2090 else
2091 return pclk * 2;
2092}
2093
8702ee50 2094static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2095 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2096{
2097 unsigned int hf, vf;
2098
2099 /*
2100 * FIXME how to determine the 'A' factor
2101 * for the no downscaling case ?
2102 */
2103
2104 if (width > 3 * out_width)
2105 hf = 4;
2106 else if (width > 2 * out_width)
2107 hf = 3;
2108 else if (width > out_width)
2109 hf = 2;
2110 else
2111 hf = 1;
80c39712
TV		 2112 if (height > out_height)
2113 vf = 2;
2114 else
2115 vf = 1;
2116
dcbe765b
CM		 2117 return pclk * vf * hf;
2118}
2119
8702ee50 2120static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2121 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2122{
8ba85306
AT		 2123 /*
2124 * If the overlay/writeback is in mem to mem mode, there are no
2125 * downscaling limitations with respect to pixel clock, return 1 as
2126 * required core clock to represent that we have sufficient enough
2127 * core clock to do maximum downscaling
2128 */
2129 if (mem_to_mem)
2130 return 1;
2131
dcbe765b
CM		 2132 if (width > out_width)
2133 return DIV_ROUND_UP(pclk, out_width) * width;
2134 else
2135 return pclk;
2136}
2137
0c6921de 2138static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2139 const struct omap_video_timings *mgr_timings,
2140 u16 width, u16 height, u16 out_width, u16 out_height,
2141 enum omap_color_mode color_mode, bool *five_taps,
2142 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2143 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2144{
2145 int error;
2146 u16 in_width, in_height;
2147 int min_factor = min(*decim_x, *decim_y);
2148 const int maxsinglelinewidth =
2149 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2150
dcbe765b
CM		 2151 *five_taps = false;
2152
2153 do {
2154 in_height = DIV_ROUND_UP(height, *decim_y);
2155 in_width = DIV_ROUND_UP(width, *decim_x);
8702ee50 2156 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2157 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2158 error = (in_width > maxsinglelinewidth || !*core_clk ||
2159 *core_clk > dispc_core_clk_rate());
2160 if (error) {
2161 if (*decim_x == *decim_y) {
2162 *decim_x = min_factor;
2163 ++*decim_y;
2164 } else {
2165 swap(*decim_x, *decim_y);
2166 if (*decim_x < *decim_y)
2167 ++*decim_x;
2168 }
2169 }
2170 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2171
2172 if (in_width > maxsinglelinewidth) {
2173 DSSERR("Cannot scale max input width exceeded");
2174 return -EINVAL;
2175 }
2176 return 0;
2177}
2178
0c6921de 2179static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2180 const struct omap_video_timings *mgr_timings,
2181 u16 width, u16 height, u16 out_width, u16 out_height,
2182 enum omap_color_mode color_mode, bool *five_taps,
2183 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2184 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2185{
2186 int error;
2187 u16 in_width, in_height;
2188 int min_factor = min(*decim_x, *decim_y);
2189 const int maxsinglelinewidth =
2190 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2191
2192 do {
2193 in_height = DIV_ROUND_UP(height, *decim_y);
2194 in_width = DIV_ROUND_UP(width, *decim_x);
8702ee50 2195 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
dcbe765b
CM		 2196 in_width, in_height, out_width, out_height, color_mode);
2197
465ec13f 2198 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
3e8a6ff2
AT		 2199 pos_x, in_width, in_height, out_width,
2200 out_height);
dcbe765b
CM		 2201
2202 if (in_width > maxsinglelinewidth)
2203 if (in_height > out_height &&
2204 in_height < out_height * 2)
2205 *five_taps = false;
2206 if (!*five_taps)
8702ee50 2207 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2208 in_height, out_width, out_height,
2209 mem_to_mem);
dcbe765b
CM		 2210
2211 error = (error || in_width > maxsinglelinewidth * 2 ||
2212 (in_width > maxsinglelinewidth && *five_taps) ||
2213 !*core_clk || *core_clk > dispc_core_clk_rate());
2214 if (error) {
2215 if (*decim_x == *decim_y) {
2216 *decim_x = min_factor;
2217 ++*decim_y;
2218 } else {
2219 swap(*decim_x, *decim_y);
2220 if (*decim_x < *decim_y)
2221 ++*decim_x;
2222 }
2223 }
2224 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2225
465ec13f
TV		 2226 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2227 height, out_width, out_height)){
dcbe765b
CM		 2228 DSSERR("horizontal timing too tight\n");
2229 return -EINVAL;
7282f1b7 2230 }
dcbe765b
CM		 2231
2232 if (in_width > (maxsinglelinewidth * 2)) {
2233 DSSERR("Cannot setup scaling");
2234 DSSERR("width exceeds maximum width possible");
2235 return -EINVAL;
2236 }
2237
2238 if (in_width > maxsinglelinewidth && *five_taps) {
2239 DSSERR("cannot setup scaling with five taps");
2240 return -EINVAL;
2241 }
2242 return 0;
2243}
2244
0c6921de 2245static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2246 const struct omap_video_timings *mgr_timings,
2247 u16 width, u16 height, u16 out_width, u16 out_height,
2248 enum omap_color_mode color_mode, bool *five_taps,
2249 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2250 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2251{
2252 u16 in_width, in_width_max;
2253 int decim_x_min = *decim_x;
2254 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2255 const int maxsinglelinewidth =
2256 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2257 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2258
5d501085
AT		 2259 if (mem_to_mem) {
2260 in_width_max = out_width * maxdownscale;
2261 } else {
8ba85306
AT		 2262 in_width_max = dispc_core_clk_rate() /
2263 DIV_ROUND_UP(pclk, out_width);
5d501085 2264 }
dcbe765b 2265
dcbe765b
CM		 2266 *decim_x = DIV_ROUND_UP(width, in_width_max);
2267
2268 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2269 if (*decim_x > *x_predecim)
2270 return -EINVAL;
2271
2272 do {
2273 in_width = DIV_ROUND_UP(width, *decim_x);
2274 } while (*decim_x <= *x_predecim &&
2275 in_width > maxsinglelinewidth && ++*decim_x);
2276
2277 if (in_width > maxsinglelinewidth) {
2278 DSSERR("Cannot scale width exceeds max line width");
2279 return -EINVAL;
2280 }
2281
8702ee50 2282 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2283 out_width, out_height, mem_to_mem);
dcbe765b 2284 return 0;
80c39712
TV		 2285}
2286
79ad75f2 2287static int dispc_ovl_calc_scaling(enum omap_plane plane,
3e8a6ff2 2288 enum omap_overlay_caps caps,
81ab95b7
AT		 2289 const struct omap_video_timings *mgr_timings,
2290 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2291 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2292 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2293 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2294{
0373cac6 2295 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2296 const int max_decim_limit = 16;
8b53d991 2297 unsigned long core_clk = 0;
dcbe765b 2298 int decim_x, decim_y, ret;
0c6921de
TV		 2299 unsigned long pclk = dispc_plane_pclk_rate(plane);
2300 unsigned long lclk = dispc_plane_lclk_rate(plane);
79ad75f2 2301
f95cb5eb
TV		 2302 if (width == out_width && height == out_height)
2303 return 0;
2304
5b54ed3e 2305 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2306 return -EINVAL;
79ad75f2 2307
1c031441
AT		 2308 if (plane == OMAP_DSS_WB) {
2309 *x_predecim = *y_predecim = 1;
2310 } else {
2311 *x_predecim = max_decim_limit;
2312 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2313 dss_has_feature(FEAT_BURST_2D)) ?
2314 2 : max_decim_limit;
2315 }
aed74b55
CM		 2316
2317 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2318 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2319 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2320 color_mode == OMAP_DSS_COLOR_CLUT8) {
2321 *x_predecim = 1;
2322 *y_predecim = 1;
2323 *five_taps = false;
2324 return 0;
2325 }
2326
2327 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2328 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2329
aed74b55 2330 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2331 return -EINVAL;
2332
aed74b55 2333 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2334 return -EINVAL;
2335
0c6921de 2336 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2337 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2338 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2339 mem_to_mem);
dcbe765b
CM		 2340 if (ret)
2341 return ret;
79ad75f2 2342
8b53d991
CM		 2343 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2344 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2345
8b53d991 2346 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2347 DSSERR("failed to set up scaling, "
8b53d991
CM		 2348 "required core clk rate = %lu Hz, "
2349 "current core clk rate = %lu Hz\n",
2350 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2351 return -EINVAL;
2352 }
2353
aed74b55
CM		 2354 *x_predecim = decim_x;
2355 *y_predecim = decim_y;
79ad75f2
AT		 2356 return 0;
2357}
2358
84a880fd 2359static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2360 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2361 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2362 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2363 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2364 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2365 bool replication, const struct omap_video_timings *mgr_timings,
2366 bool mem_to_mem)
80c39712 2367{
7282f1b7 2368 bool five_taps = true;
80c39712 2369 bool fieldmode = 0;
79ad75f2 2370 int r, cconv = 0;
80c39712
TV		 2371 unsigned offset0, offset1;
2372 s32 row_inc;
2373 s32 pix_inc;
6be0d73e 2374 u16 frame_width, frame_height;
80c39712 2375 unsigned int field_offset = 0;
84a880fd
AT		 2376 u16 in_height = height;
2377 u16 in_width = width;
aed74b55 2378 int x_predecim = 1, y_predecim = 1;
8050cbe4 2379 bool ilace = mgr_timings->interlace;
e6d80f95 2380
84a880fd 2381 if (paddr == 0)
80c39712
TV		 2382 return -EINVAL;
2383
84a880fd
AT		 2384 out_width = out_width == 0 ? width : out_width;
2385 out_height = out_height == 0 ? height : out_height;
cf073668 2386
84a880fd 2387 if (ilace && height == out_height)
80c39712
TV		 2388 fieldmode = 1;
2389
2390 if (ilace) {
2391 if (fieldmode)
aed74b55 2392 in_height /= 2;
8eeb7019 2393 pos_y /= 2;
aed74b55 2394 out_height /= 2;
80c39712
TV		 2395
2396 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2397 "out_height %d\n", in_height, pos_y,
2398 out_height);
80c39712
TV		 2399 }
2400
84a880fd 2401 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2402 return -EINVAL;
2403
3e8a6ff2 2404 r = dispc_ovl_calc_scaling(plane, caps, mgr_timings, in_width,
84a880fd
AT		 2405 in_height, out_width, out_height, color_mode,
2406 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2407 rotation_type, mem_to_mem);
79ad75f2
AT		 2408 if (r)
2409 return r;
80c39712 2410
aed74b55
CM		 2411 in_width = DIV_ROUND_UP(in_width, x_predecim);
2412 in_height = DIV_ROUND_UP(in_height, y_predecim);
2413
84a880fd
AT		 2414 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2415 color_mode == OMAP_DSS_COLOR_UYVY ||
2416 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2417 cconv = 1;
80c39712
TV		 2418
2419 if (ilace && !fieldmode) {
2420 /*
2421 * when downscaling the bottom field may have to start several
2422 * source lines below the top field. Unfortunately ACCUI
2423 * registers will only hold the fractional part of the offset
2424 * so the integer part must be added to the base address of the
2425 * bottom field.
2426 */
aed74b55 2427 if (!in_height || in_height == out_height)
80c39712
TV		 2428 field_offset = 0;
2429 else
aed74b55 2430 field_offset = in_height / out_height / 2;
80c39712
TV		 2431 }
2432
2433 /* Fields are independent but interleaved in memory. */
2434 if (fieldmode)
2435 field_offset = 1;
2436
c6eee968
TV		 2437 offset0 = 0;
2438 offset1 = 0;
2439 row_inc = 0;
2440 pix_inc = 0;
2441
6be0d73e
AT		 2442 if (plane == OMAP_DSS_WB) {
2443 frame_width = out_width;
2444 frame_height = out_height;
2445 } else {
2446 frame_width = in_width;
2447 frame_height = height;
2448 }
2449
84a880fd 2450 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2451 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2452 color_mode, fieldmode, field_offset,
65e006ff
CM		 2453 &offset0, &offset1, &row_inc, &pix_inc,
2454 x_predecim, y_predecim);
84a880fd 2455 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2456 calc_dma_rotation_offset(rotation, mirror, screen_width,
2457 frame_width, frame_height,
84a880fd 2458 color_mode, fieldmode, field_offset,
aed74b55
CM		 2459 &offset0, &offset1, &row_inc, &pix_inc,
2460 x_predecim, y_predecim);
80c39712 2461 else
84a880fd 2462 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2463 screen_width, frame_width, frame_height,
84a880fd 2464 color_mode, fieldmode, field_offset,
aed74b55
CM		 2465 &offset0, &offset1, &row_inc, &pix_inc,
2466 x_predecim, y_predecim);
80c39712
TV		 2467
2468 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2469 offset0, offset1, row_inc, pix_inc);
2470
84a880fd 2471 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2472
84a880fd 2473 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2474
84a880fd
AT		 2475 dispc_ovl_set_ba0(plane, paddr + offset0);
2476 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2477
84a880fd
AT		 2478 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2479 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2480 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2481 }
2482
f0e5caab
TV		 2483 dispc_ovl_set_row_inc(plane, row_inc);
2484 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2485
84a880fd 2486 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2487 in_height, out_width, out_height);
80c39712 2488
84a880fd 2489 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2490
78b687fc 2491 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2492
5b54ed3e 2493 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2494 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2495 out_height, ilace, five_taps, fieldmode,
84a880fd 2496 color_mode, rotation);
78b687fc 2497 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2498 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2499 }
2500
84a880fd 2501 dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
80c39712 2502
84a880fd
AT		 2503 dispc_ovl_set_zorder(plane, caps, zorder);
2504 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2505 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2506
d79db853 2507 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2508
80c39712
TV		 2509 return 0;
2510}
2511
84a880fd 2512int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2513 bool replication, const struct omap_video_timings *mgr_timings,
2514 bool mem_to_mem)
84a880fd
AT		 2515{
2516 int r;
16bf20c7 2517 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2518 enum omap_channel channel;
2519
2520 channel = dispc_ovl_get_channel_out(plane);
2521
2522 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2523 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2524 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2525 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2526 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2527
16bf20c7 2528 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2529 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2530 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2531 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2532 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2533
2534 return r;
2535}
2536
749feffa 2537int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2538 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2539{
2540 int r;
9e4a0fc7 2541 u32 l;
749feffa
AT		 2542 enum omap_plane plane = OMAP_DSS_WB;
2543 const int pos_x = 0, pos_y = 0;
2544 const u8 zorder = 0, global_alpha = 0;
2545 const bool replication = false;
9e4a0fc7 2546 bool truncation;
749feffa
AT		 2547 int in_width = mgr_timings->x_res;
2548 int in_height = mgr_timings->y_res;
2549 enum omap_overlay_caps caps =
2550 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2551
2552 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2553 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2554 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2555 wi->mirror);
2556
2557 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2558 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2559 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2560 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2561 replication, mgr_timings, mem_to_mem);
2562
2563 switch (wi->color_mode) {
2564 case OMAP_DSS_COLOR_RGB16:
2565 case OMAP_DSS_COLOR_RGB24P:
2566 case OMAP_DSS_COLOR_ARGB16:
2567 case OMAP_DSS_COLOR_RGBA16:
2568 case OMAP_DSS_COLOR_RGB12U:
2569 case OMAP_DSS_COLOR_ARGB16_1555:
2570 case OMAP_DSS_COLOR_XRGB16_1555:
2571 case OMAP_DSS_COLOR_RGBX16:
2572 truncation = true;
2573 break;
2574 default:
2575 truncation = false;
2576 break;
2577 }
2578
2579 /* setup extra DISPC_WB_ATTRIBUTES */
2580 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2581 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2582 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2583 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2584
2585 return r;
2586}
2587
f0e5caab 2588int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2589{
e6d80f95
TV		 2590 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2591
9b372c2d 2592 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2593
2594 return 0;
80c39712
TV		 2595}
2596
04bd8ac1
TV		 2597bool dispc_ovl_enabled(enum omap_plane plane)
2598{
2599 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2600}
2601
b1112249 2602static void dispc_mgr_disable_isr(void *data, u32 mask)
80c39712
TV		 2603{
2604 struct completion *compl = data;
2605 complete(compl);
2606}
2607
f1a813d3 2608void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2609{
efa70b3b
CM		 2610 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2611 /* flush posted write */
2612 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2613}
2614
65398511
TV		 2615bool dispc_mgr_is_enabled(enum omap_channel channel)
2616{
2617 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2618}
2619
b1112249 2620static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
80c39712 2621{
f1a813d3 2622 dispc_mgr_enable(channel, true);
b1112249
TV		 2623}
2624
2625static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
2626{
2627 DECLARE_COMPLETION_ONSTACK(framedone_compl);
80c39712 2628 int r;
2a205f34 2629 u32 irq;
80c39712 2630
b1112249
TV		 2631 if (dispc_mgr_is_enabled(channel) == false)
2632 return;
2a205f34 2633
b1112249
TV		 2634 /*
2635 * When we disable LCD output, we need to wait for FRAMEDONE to know
2636 * that DISPC has finished with the LCD output.
2637 */
80c39712 2638
b1112249 2639 irq = dispc_mgr_get_framedone_irq(channel);
80c39712 2640
b1112249
TV		 2641 r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
2642 irq);
2643 if (r)
2644 DSSERR("failed to register FRAMEDONE isr\n");
80c39712 2645
f1a813d3 2646 dispc_mgr_enable(channel, false);
b1112249
TV		 2647
2648 /* if we couldn't register for framedone, just sleep and exit */
2649 if (r) {
2650 msleep(100);
2651 return;
80c39712
TV		 2652 }
2653
b1112249
TV		 2654 if (!wait_for_completion_timeout(&framedone_compl,
2655 msecs_to_jiffies(100)))
2656 DSSERR("timeout waiting for FRAME DONE\n");
80c39712 2657
b1112249
TV		 2658 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
2659 irq);
2660 if (r)
2661 DSSERR("failed to unregister FRAMEDONE isr\n");
2662}
80c39712 2663
b1112249
TV		 2664static void dispc_digit_out_enable_isr(void *data, u32 mask)
2665{
2666 struct completion *compl = data;
80c39712 2667
b1112249
TV		 2668 /* ignore any sync lost interrupts */
2669 if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
2670 complete(compl);
2671}
2672
2673static void dispc_mgr_enable_digit_out(void)
2674{
2675 DECLARE_COMPLETION_ONSTACK(vsync_compl);
2676 int r;
2677 u32 irq_mask;
2678
2679 if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
2680 return;
2681
2682 /*
2683 * Digit output produces some sync lost interrupts during the first
2684 * frame when enabling. Those need to be ignored, so we register for the
2685 * sync lost irq to prevent the error handler from triggering.
2686 */
2687
2688 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
2689 dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
2690
2691 r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
2692 irq_mask);
2693 if (r) {
2694 DSSERR("failed to register %x isr\n", irq_mask);
2695 return;
80c39712 2696 }
b1112249 2697
f1a813d3 2698 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, true);
b1112249
TV		 2699
2700 /* wait for the first evsync */
2701 if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
2702 DSSERR("timeout waiting for digit out to start\n");
2703
2704 r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
2705 irq_mask);
2706 if (r)
2707 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2708}
2709
b1112249 2710static void dispc_mgr_disable_digit_out(void)
80c39712 2711{
b1112249 2712 DECLARE_COMPLETION_ONSTACK(framedone_compl);
e82b090b
TV		 2713 int r, i;
2714 u32 irq_mask;
2715 int num_irqs;
80c39712 2716
b1112249 2717 if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
80c39712 2718 return;
80c39712 2719
b1112249
TV		 2720 /*
2721 * When we disable the digit output, we need to wait for FRAMEDONE to
15f5e732 2722 * know that DISPC has finished with the output.
b1112249 2723 */
80c39712 2724
15f5e732
TV		 2725 irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
2726 num_irqs = 1;
2727
2728 if (!irq_mask) {
2729 /*
2730 * omap 2/3 don't have framedone irq for TV, so we need to use
2731 * vsyncs for this.
2732 */
2733
b1112249
TV		 2734 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
2735 /*
2736 * We need to wait for both even and odd vsyncs. Note that this
2737 * is not totally reliable, as we could get a vsync interrupt
2738 * before we disable the output, which leads to timeout in the
2739 * wait_for_completion.
2740 */
e82b090b
TV		 2741 num_irqs = 2;
2742 }
2743
b1112249 2744 r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
e82b090b 2745 irq_mask);
80c39712 2746 if (r)
e82b090b 2747 DSSERR("failed to register %x isr\n", irq_mask);
80c39712 2748
f1a813d3 2749 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, false);
b1112249
TV		 2750
2751 /* if we couldn't register the irq, just sleep and exit */
2752 if (r) {
2753 msleep(100);
2754 return;
2755 }
80c39712 2756
e82b090b 2757 for (i = 0; i < num_irqs; ++i) {
b1112249 2758 if (!wait_for_completion_timeout(&framedone_compl,
e82b090b 2759 msecs_to_jiffies(100)))
b1112249 2760 DSSERR("timeout waiting for digit out to stop\n");
e82b090b 2761 }
80c39712 2762
b1112249 2763 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
e82b090b 2764 irq_mask);
80c39712 2765 if (r)
e82b090b 2766 DSSERR("failed to unregister %x isr\n", irq_mask);
b1112249 2767}
80c39712 2768
3a979f8a 2769void dispc_mgr_enable_sync(enum omap_channel channel)
b1112249
TV		 2770{
2771 if (dss_mgr_is_lcd(channel))
2772 dispc_mgr_enable_lcd_out(channel);
2773 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2774 dispc_mgr_enable_digit_out();
2775 else
2776 WARN_ON(1);
80c39712
TV		 2777}
2778
3a979f8a 2779void dispc_mgr_disable_sync(enum omap_channel channel)
a2faee84 2780{
dd88b7a6 2781 if (dss_mgr_is_lcd(channel))
b1112249 2782 dispc_mgr_disable_lcd_out(channel);
a2faee84 2783 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
b1112249 2784 dispc_mgr_disable_digit_out();
a2faee84 2785 else
b1112249 2786 WARN_ON(1);
a2faee84
TV		 2787}
2788
0b23e5b8
AT		 2789void dispc_wb_enable(bool enable)
2790{
916188a4 2791 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2792}
2793
2794bool dispc_wb_is_enabled(void)
2795{
916188a4 2796 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2797}
2798
fb2cec1f 2799static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2800{
6ced40bf
AT		 2801 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2802 return;
2803
80c39712 2804 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2805}
2806
2807void dispc_lcd_enable_signal(bool enable)
2808{
6ced40bf
AT		 2809 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2810 return;
2811
80c39712 2812 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2813}
2814
2815void dispc_pck_free_enable(bool enable)
2816{
6ced40bf
AT		 2817 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2818 return;
2819
80c39712 2820 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2821}
2822
fb2cec1f 2823static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2824{
efa70b3b 2825 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2826}
2827
2828
fb2cec1f 2829static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2830{
d21f43bc 2831 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2832}
2833
2834void dispc_set_loadmode(enum omap_dss_load_mode mode)
2835{
80c39712 2836 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2837}
2838
2839
c64dca40 2840static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2841{
8613b000 2842 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2843}
2844
c64dca40 2845static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2846 enum omap_dss_trans_key_type type,
2847 u32 trans_key)
2848{
efa70b3b 2849 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2850
8613b000 2851 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2852}
2853
c64dca40 2854static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2855{
efa70b3b 2856 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2857}
11354dd5 2858
c64dca40
TV		 2859static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2860 bool enable)
80c39712 2861{
11354dd5 2862 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2863 return;
2864
80c39712
TV		 2865 if (ch == OMAP_DSS_CHANNEL_LCD)
2866 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2867 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2868 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2869}
11354dd5 2870
c64dca40 2871void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2872 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2873{
2874 dispc_mgr_set_default_color(channel, info->default_color);
2875 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2876 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2877 dispc_mgr_enable_alpha_fixed_zorder(channel,
2878 info->partial_alpha_enabled);
2879 if (dss_has_feature(FEAT_CPR)) {
2880 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2881 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2882 }
2883}
80c39712 2884
fb2cec1f 2885static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2886{
2887 int code;
2888
2889 switch (data_lines) {
2890 case 12:
2891 code = 0;
2892 break;
2893 case 16:
2894 code = 1;
2895 break;
2896 case 18:
2897 code = 2;
2898 break;
2899 case 24:
2900 code = 3;
2901 break;
2902 default:
2903 BUG();
2904 return;
2905 }
2906
efa70b3b 2907 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2908}
2909
fb2cec1f 2910static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2911{
2912 u32 l;
569969d6 2913 int gpout0, gpout1;
80c39712
TV		 2914
2915 switch (mode) {
569969d6
AT		 2916 case DSS_IO_PAD_MODE_RESET:
2917 gpout0 = 0;
2918 gpout1 = 0;
80c39712 2919 break;
569969d6
AT		 2920 case DSS_IO_PAD_MODE_RFBI:
2921 gpout0 = 1;
80c39712
TV		 2922 gpout1 = 0;
2923 break;
569969d6
AT		 2924 case DSS_IO_PAD_MODE_BYPASS:
2925 gpout0 = 1;
80c39712
TV		 2926 gpout1 = 1;
2927 break;
80c39712
TV		 2928 default:
2929 BUG();
2930 return;
2931 }
2932
569969d6
AT		 2933 l = dispc_read_reg(DISPC_CONTROL);
2934 l = FLD_MOD(l, gpout0, 15, 15);
2935 l = FLD_MOD(l, gpout1, 16, 16);
2936 dispc_write_reg(DISPC_CONTROL, l);
2937}
2938
fb2cec1f 2939static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2940{
efa70b3b 2941 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2942}
2943
fb2cec1f
TV		 2944void dispc_mgr_set_lcd_config(enum omap_channel channel,
2945 const struct dss_lcd_mgr_config *config)
2946{
2947 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2948
2949 dispc_mgr_enable_stallmode(channel, config->stallmode);
2950 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2951
2952 dispc_mgr_set_clock_div(channel, &config->clock_info);
2953
2954 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2955
2956 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2957
2958 dispc_mgr_set_lcd_type_tft(channel);
2959}
2960
8f366162
AT		 2961static bool _dispc_mgr_size_ok(u16 width, u16 height)
2962{
33b89928
AT		 2963 return width <= dispc.feat->mgr_width_max &&
2964 height <= dispc.feat->mgr_height_max;
8f366162
AT		 2965}
2966
80c39712
TV		 2967static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2968 int vsw, int vfp, int vbp)
2969{
dcbe765b
CM		 2970 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2971 hfp < 1 || hfp > dispc.feat->hp_max ||
2972 hbp < 1 || hbp > dispc.feat->hp_max ||
2973 vsw < 1 || vsw > dispc.feat->sw_max ||
2974 vfp < 0 || vfp > dispc.feat->vp_max ||
2975 vbp < 0 || vbp > dispc.feat->vp_max)
2976 return false;
80c39712
TV		 2977 return true;
2978}
2979
8f366162 2980bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2981 const struct omap_video_timings *timings)
80c39712 2982{
8f366162
AT		 2983 bool timings_ok;
2984
2985 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2986
dd88b7a6 2987 if (dss_mgr_is_lcd(channel))
8f366162
AT		 2988 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2989 timings->hfp, timings->hbp,
2990 timings->vsw, timings->vfp,
2991 timings->vbp);
2992
2993 return timings_ok;
80c39712
TV		 2994}
2995
26d9dd0d 2996static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2997 int hfp, int hbp, int vsw, int vfp, int vbp,
2998 enum omap_dss_signal_level vsync_level,
2999 enum omap_dss_signal_level hsync_level,
3000 enum omap_dss_signal_edge data_pclk_edge,
3001 enum omap_dss_signal_level de_level,
3002 enum omap_dss_signal_edge sync_pclk_edge)
3003
80c39712 3004{
655e2941
AT		 3005 u32 timing_h, timing_v, l;
3006 bool onoff, rf, ipc;
80c39712 3007
dcbe765b
CM		 3008 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3009 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3010 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3011 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3012 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3013 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3014
64ba4f74
SS		 3015 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3016 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 3017
3018 switch (data_pclk_edge) {
3019 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3020 ipc = false;
3021 break;
3022 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3023 ipc = true;
3024 break;
3025 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
3026 default:
3027 BUG();
3028 }
3029
3030 switch (sync_pclk_edge) {
3031 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
3032 onoff = false;
3033 rf = false;
3034 break;
3035 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3036 onoff = true;
3037 rf = false;
3038 break;
3039 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3040 onoff = true;
3041 rf = true;
3042 break;
3043 default:
3044 BUG();
3045 };
3046
3047 l = dispc_read_reg(DISPC_POL_FREQ(channel));
3048 l |= FLD_VAL(onoff, 17, 17);
3049 l |= FLD_VAL(rf, 16, 16);
3050 l |= FLD_VAL(de_level, 15, 15);
3051 l |= FLD_VAL(ipc, 14, 14);
3052 l |= FLD_VAL(hsync_level, 13, 13);
3053 l |= FLD_VAL(vsync_level, 12, 12);
3054 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3055}
3056
3057/* change name to mode? */
c51d921a 3058void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3059 const struct omap_video_timings *timings)
80c39712
TV		 3060{
3061 unsigned xtot, ytot;
3062 unsigned long ht, vt;
2aefad49 3063 struct omap_video_timings t = *timings;
80c39712 3064
2aefad49 3065 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3066
2aefad49 3067 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3068 BUG();
c6eee968
TV		 3069 return;
3070 }
80c39712 3071
dd88b7a6 3072 if (dss_mgr_is_lcd(channel)) {
2aefad49 3073 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3074 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3075 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3076
2aefad49
AT		 3077 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3078 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3079
c51d921a
AT		 3080 ht = (timings->pixel_clock * 1000) / xtot;
3081 vt = (timings->pixel_clock * 1000) / xtot / ytot;
3082
3083 DSSDBG("pck %u\n", timings->pixel_clock);
3084 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3085 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3086 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3087 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3088 t.de_level, t.sync_pclk_edge);
80c39712 3089
c51d921a 3090 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3091 } else {
23c8f88e 3092 if (t.interlace == true)
2aefad49 3093 t.y_res /= 2;
c51d921a 3094 }
8f366162 3095
2aefad49 3096 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 3097}
3098
26d9dd0d 3099static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3100 u16 pck_div)
80c39712
TV		 3101{
3102 BUG_ON(lck_div < 1);
9eaaf207 3103 BUG_ON(pck_div < 1);
80c39712 3104
ce7fa5eb 3105 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3106 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 3107}
3108
26d9dd0d 3109static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3110 int *pck_div)
80c39712
TV		 3111{
3112 u32 l;
ce7fa5eb 3113 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3114 *lck_div = FLD_GET(l, 23, 16);
3115 *pck_div = FLD_GET(l, 7, 0);
3116}
3117
3118unsigned long dispc_fclk_rate(void)
3119{
a72b64b9 3120 struct platform_device *dsidev;
80c39712
TV		 3121 unsigned long r = 0;
3122
66534e8e 3123 switch (dss_get_dispc_clk_source()) {
89a35e51 3124 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 3125 r = clk_get_rate(dispc.dss_clk);
66534e8e 3126 break;
89a35e51 3127 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3128 dsidev = dsi_get_dsidev_from_id(0);
3129 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 3130 break;
5a8b572d
AT		 3131 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3132 dsidev = dsi_get_dsidev_from_id(1);
3133 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3134 break;
66534e8e
TA		 3135 default:
3136 BUG();
c6eee968 3137 return 0;
66534e8e
TA		 3138 }
3139
80c39712
TV		 3140 return r;
3141}
3142
26d9dd0d 3143unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3144{
a72b64b9 3145 struct platform_device *dsidev;
80c39712
TV		 3146 int lcd;
3147 unsigned long r;
3148 u32 l;
3149
c31cba8a
TV		 3150 if (dss_mgr_is_lcd(channel)) {
3151 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3152
c31cba8a 3153 lcd = FLD_GET(l, 23, 16);
80c39712 3154
c31cba8a
TV		 3155 switch (dss_get_lcd_clk_source(channel)) {
3156 case OMAP_DSS_CLK_SRC_FCK:
3157 r = clk_get_rate(dispc.dss_clk);
3158 break;
3159 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3160 dsidev = dsi_get_dsidev_from_id(0);
3161 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3162 break;
3163 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3164 dsidev = dsi_get_dsidev_from_id(1);
3165 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3166 break;
3167 default:
3168 BUG();
3169 return 0;
3170 }
80c39712 3171
c31cba8a
TV		 3172 return r / lcd;
3173 } else {
3174 return dispc_fclk_rate();
3175 }
80c39712
TV		 3176}
3177
26d9dd0d 3178unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3179{
80c39712 3180 unsigned long r;
80c39712 3181
dd88b7a6 3182 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3183 int pcd;
3184 u32 l;
80c39712 3185
c3dc6a7a 3186 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3187
c3dc6a7a 3188 pcd = FLD_GET(l, 7, 0);
80c39712 3189
c3dc6a7a
AT		 3190 r = dispc_mgr_lclk_rate(channel);
3191
3192 return r / pcd;
3193 } else {
3fa03ba8 3194 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 3195
3fa03ba8
AT		 3196 source = dss_get_hdmi_venc_clk_source();
3197
3198 switch (source) {
3199 case DSS_VENC_TV_CLK:
c3dc6a7a 3200 return venc_get_pixel_clock();
3fa03ba8 3201 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 3202 return hdmi_get_pixel_clock();
3203 default:
3204 BUG();
c6eee968 3205 return 0;
c3dc6a7a
AT		 3206 }
3207 }
80c39712
TV		 3208}
3209
8b53d991
CM		 3210unsigned long dispc_core_clk_rate(void)
3211{
3212 int lcd;
3213 unsigned long fclk = dispc_fclk_rate();
3214
3215 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3216 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3217 else
3218 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3219
3220 return fclk / lcd;
3221}
3222
3e8a6ff2
AT		 3223static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3224{
251886d8
TV		 3225 enum omap_channel channel;
3226
3227 if (plane == OMAP_DSS_WB)
3228 return 0;
3229
3230 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3231
3232 return dispc_mgr_pclk_rate(channel);
3233}
3234
3235static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3236{
251886d8
TV		 3237 enum omap_channel channel;
3238
3239 if (plane == OMAP_DSS_WB)
3240 return 0;
3241
3242 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3243
c31cba8a 3244 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3245}
c31cba8a 3246
6f1891fc 3247static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3248{
3249 int lcd, pcd;
6f1891fc
CM		 3250 enum omap_dss_clk_source lcd_clk_src;
3251
3252 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3253
3254 lcd_clk_src = dss_get_lcd_clk_source(channel);
3255
3256 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3257 dss_get_generic_clk_source_name(lcd_clk_src),
3258 dss_feat_get_clk_source_name(lcd_clk_src));
3259
3260 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3261
3262 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3263 dispc_mgr_lclk_rate(channel), lcd);
3264 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3265 dispc_mgr_pclk_rate(channel), pcd);
3266}
3267
3268void dispc_dump_clocks(struct seq_file *s)
3269{
3270 int lcd;
0cf35df3 3271 u32 l;
89a35e51 3272 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3273
4fbafaf3
TV		 3274 if (dispc_runtime_get())
3275 return;
80c39712 3276
80c39712
TV		 3277 seq_printf(s, "- DISPC -\n");
3278
067a57e4
AT		 3279 seq_printf(s, "dispc fclk source = %s (%s)\n",
3280 dss_get_generic_clk_source_name(dispc_clk_src),
3281 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3282
3283 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3284
0cf35df3
MR		 3285 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3286 seq_printf(s, "- DISPC-CORE-CLK -\n");
3287 l = dispc_read_reg(DISPC_DIVISOR);
3288 lcd = FLD_GET(l, 23, 16);
3289
3290 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3291 (dispc_fclk_rate()/lcd), lcd);
3292 }
2a205f34 3293
6f1891fc 3294 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3295
6f1891fc
CM		 3296 if (dss_has_feature(FEAT_MGR_LCD2))
3297 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3298 if (dss_has_feature(FEAT_MGR_LCD3))
3299 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3300
3301 dispc_runtime_put();
80c39712
TV		 3302}
3303
dfc0fd8d 3304#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5b30b7fb 3305static void dispc_dump_irqs(struct seq_file *s)
dfc0fd8d
TV		 3306{
3307 unsigned long flags;
3308 struct dispc_irq_stats stats;
3309
3310 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3311
3312 stats = dispc.irq_stats;
3313 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3314 dispc.irq_stats.last_reset = jiffies;
3315
3316 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3317
3318 seq_printf(s, "period %u ms\n",
3319 jiffies_to_msecs(jiffies - stats.last_reset));
3320
3321 seq_printf(s, "irqs %d\n", stats.irq_count);
3322#define PIS(x) \
3323 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3324
3325 PIS(FRAMEDONE);
3326 PIS(VSYNC);
3327 PIS(EVSYNC_EVEN);
3328 PIS(EVSYNC_ODD);
3329 PIS(ACBIAS_COUNT_STAT);
3330 PIS(PROG_LINE_NUM);
3331 PIS(GFX_FIFO_UNDERFLOW);
3332 PIS(GFX_END_WIN);
3333 PIS(PAL_GAMMA_MASK);
3334 PIS(OCP_ERR);
3335 PIS(VID1_FIFO_UNDERFLOW);
3336 PIS(VID1_END_WIN);
3337 PIS(VID2_FIFO_UNDERFLOW);
3338 PIS(VID2_END_WIN);
b8c095b4
AT		 3339 if (dss_feat_get_num_ovls() > 3) {
3340 PIS(VID3_FIFO_UNDERFLOW);
3341 PIS(VID3_END_WIN);
3342 }
dfc0fd8d
TV		 3343 PIS(SYNC_LOST);
3344 PIS(SYNC_LOST_DIGIT);
3345 PIS(WAKEUP);
2a205f34
SS		 3346 if (dss_has_feature(FEAT_MGR_LCD2)) {
3347 PIS(FRAMEDONE2);
3348 PIS(VSYNC2);
3349 PIS(ACBIAS_COUNT_STAT2);
3350 PIS(SYNC_LOST2);
3351 }
6f1891fc
CM		 3352 if (dss_has_feature(FEAT_MGR_LCD3)) {
3353 PIS(FRAMEDONE3);
3354 PIS(VSYNC3);
3355 PIS(ACBIAS_COUNT_STAT3);
3356 PIS(SYNC_LOST3);
3357 }
dfc0fd8d
TV		 3358#undef PIS
3359}
dfc0fd8d
TV		 3360#endif
3361
e40402cf 3362static void dispc_dump_regs(struct seq_file *s)
80c39712 3363{
4dd2da15
AT		 3364 int i, j;
3365 const char *mgr_names[] = {
3366 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3367 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3368 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3369 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3370 };
3371 const char *ovl_names[] = {
3372 [OMAP_DSS_GFX] = "GFX",
3373 [OMAP_DSS_VIDEO1] = "VID1",
3374 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3375 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3376 };
3377 const char **p_names;
3378
9b372c2d 3379#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3380
4fbafaf3
TV		 3381 if (dispc_runtime_get())
3382 return;
80c39712 3383
5010be80 3384 /* DISPC common registers */
80c39712
TV		 3385 DUMPREG(DISPC_REVISION);
3386 DUMPREG(DISPC_SYSCONFIG);
3387 DUMPREG(DISPC_SYSSTATUS);
3388 DUMPREG(DISPC_IRQSTATUS);
3389 DUMPREG(DISPC_IRQENABLE);
3390 DUMPREG(DISPC_CONTROL);
3391 DUMPREG(DISPC_CONFIG);
3392 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3393 DUMPREG(DISPC_LINE_STATUS);
3394 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3395 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3396 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3397 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3398 if (dss_has_feature(FEAT_MGR_LCD2)) {
3399 DUMPREG(DISPC_CONTROL2);
3400 DUMPREG(DISPC_CONFIG2);
5010be80 3401 }
6f1891fc
CM		 3402 if (dss_has_feature(FEAT_MGR_LCD3)) {
3403 DUMPREG(DISPC_CONTROL3);
3404 DUMPREG(DISPC_CONFIG3);
3405 }
5010be80
AT		 3406
3407#undef DUMPREG
3408
3409#define DISPC_REG(i, name) name(i)
4dd2da15 3410#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3411 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3412 dispc_read_reg(DISPC_REG(i, r)))
3413
4dd2da15 3414 p_names = mgr_names;
5010be80 3415
4dd2da15
AT		 3416 /* DISPC channel specific registers */
3417 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3418 DUMPREG(i, DISPC_DEFAULT_COLOR);
3419 DUMPREG(i, DISPC_TRANS_COLOR);
3420 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3421
4dd2da15
AT		 3422 if (i == OMAP_DSS_CHANNEL_DIGIT)
3423 continue;
5010be80 3424
4dd2da15
AT		 3425 DUMPREG(i, DISPC_DEFAULT_COLOR);
3426 DUMPREG(i, DISPC_TRANS_COLOR);
3427 DUMPREG(i, DISPC_TIMING_H);
3428 DUMPREG(i, DISPC_TIMING_V);
3429 DUMPREG(i, DISPC_POL_FREQ);
3430 DUMPREG(i, DISPC_DIVISORo);
3431 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3432
4dd2da15
AT		 3433 DUMPREG(i, DISPC_DATA_CYCLE1);
3434 DUMPREG(i, DISPC_DATA_CYCLE2);
3435 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3436
332e9d70 3437 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3438 DUMPREG(i, DISPC_CPR_COEF_R);
3439 DUMPREG(i, DISPC_CPR_COEF_G);
3440 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3441 }
2a205f34 3442 }
80c39712 3443
4dd2da15
AT		 3444 p_names = ovl_names;
3445
3446 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3447 DUMPREG(i, DISPC_OVL_BA0);
3448 DUMPREG(i, DISPC_OVL_BA1);
3449 DUMPREG(i, DISPC_OVL_POSITION);
3450 DUMPREG(i, DISPC_OVL_SIZE);
3451 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3452 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3453 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3454 DUMPREG(i, DISPC_OVL_ROW_INC);
3455 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3456 if (dss_has_feature(FEAT_PRELOAD))
3457 DUMPREG(i, DISPC_OVL_PRELOAD);
3458
3459 if (i == OMAP_DSS_GFX) {
3460 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3461 DUMPREG(i, DISPC_OVL_TABLE_BA);
3462 continue;
3463 }
3464
3465 DUMPREG(i, DISPC_OVL_FIR);
3466 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3467 DUMPREG(i, DISPC_OVL_ACCU0);
3468 DUMPREG(i, DISPC_OVL_ACCU1);
3469 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3470 DUMPREG(i, DISPC_OVL_BA0_UV);
3471 DUMPREG(i, DISPC_OVL_BA1_UV);
3472 DUMPREG(i, DISPC_OVL_FIR2);
3473 DUMPREG(i, DISPC_OVL_ACCU2_0);
3474 DUMPREG(i, DISPC_OVL_ACCU2_1);
3475 }
3476 if (dss_has_feature(FEAT_ATTR2))
3477 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3478 if (dss_has_feature(FEAT_PRELOAD))
3479 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3480 }
5010be80
AT		 3481
3482#undef DISPC_REG
3483#undef DUMPREG
3484
3485#define DISPC_REG(plane, name, i) name(plane, i)
3486#define DUMPREG(plane, name, i) \
4dd2da15 3487 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3488 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3489 dispc_read_reg(DISPC_REG(plane, name, i)))
3490
4dd2da15 3491 /* Video pipeline coefficient registers */
332e9d70 3492
4dd2da15
AT		 3493 /* start from OMAP_DSS_VIDEO1 */
3494 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3495 for (j = 0; j < 8; j++)
3496 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3497
4dd2da15
AT		 3498 for (j = 0; j < 8; j++)
3499 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3500
4dd2da15
AT		 3501 for (j = 0; j < 5; j++)
3502 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3503
4dd2da15
AT		 3504 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3505 for (j = 0; j < 8; j++)
3506 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3507 }
3508
3509 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3510 for (j = 0; j < 8; j++)
3511 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3512
3513 for (j = 0; j < 8; j++)
3514 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3515
3516 for (j = 0; j < 8; j++)
3517 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3518 }
332e9d70 3519 }
80c39712 3520
4fbafaf3 3521 dispc_runtime_put();
5010be80
AT		 3522
3523#undef DISPC_REG
80c39712
TV		 3524#undef DUMPREG
3525}
3526
80c39712 3527/* with fck as input clock rate, find dispc dividers that produce req_pck */
6d523e7b 3528void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
80c39712
TV		 3529 struct dispc_clock_info *cinfo)
3530{
9eaaf207 3531 u16 pcd_min, pcd_max;
80c39712
TV		 3532 unsigned long best_pck;
3533 u16 best_ld, cur_ld;
3534 u16 best_pd, cur_pd;
3535
9eaaf207
TV		 3536 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3537 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3538
80c39712
TV		 3539 best_pck = 0;
3540 best_ld = 0;
3541 best_pd = 0;
3542
3543 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3544 unsigned long lck = fck / cur_ld;
3545
9eaaf207 3546 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3547 unsigned long pck = lck / cur_pd;
3548 long old_delta = abs(best_pck - req_pck);
3549 long new_delta = abs(pck - req_pck);
3550
3551 if (best_pck == 0 || new_delta < old_delta) {
3552 best_pck = pck;
3553 best_ld = cur_ld;
3554 best_pd = cur_pd;
3555
3556 if (pck == req_pck)
3557 goto found;
3558 }
3559
3560 if (pck < req_pck)
3561 break;
3562 }
3563
3564 if (lck / pcd_min < req_pck)
3565 break;
3566 }
3567
3568found:
3569 cinfo->lck_div = best_ld;
3570 cinfo->pck_div = best_pd;
3571 cinfo->lck = fck / cinfo->lck_div;
3572 cinfo->pck = cinfo->lck / cinfo->pck_div;
3573}
3574
3575/* calculate clock rates using dividers in cinfo */
3576int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3577 struct dispc_clock_info *cinfo)
3578{
3579 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3580 return -EINVAL;
9eaaf207 3581 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3582 return -EINVAL;
3583
3584 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3585 cinfo->pck = cinfo->lck / cinfo->pck_div;
3586
3587 return 0;
3588}
3589
f0d08f89 3590void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3591 const struct dispc_clock_info *cinfo)
80c39712
TV		 3592{
3593 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3594 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3595
26d9dd0d 3596 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3597}
3598
26d9dd0d 3599int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3600 struct dispc_clock_info *cinfo)
80c39712
TV		 3601{
3602 unsigned long fck;
3603
3604 fck = dispc_fclk_rate();
3605
ce7fa5eb
MR		 3606 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3607 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3608
3609 cinfo->lck = fck / cinfo->lck_div;
3610 cinfo->pck = cinfo->lck / cinfo->pck_div;
3611
3612 return 0;
3613}
3614
4e0397cf
TV		 3615u32 dispc_read_irqstatus(void)
3616{
3617 return dispc_read_reg(DISPC_IRQSTATUS);
3618}
3619
3620void dispc_clear_irqstatus(u32 mask)
3621{
3622 dispc_write_reg(DISPC_IRQSTATUS, mask);
3623}
3624
3625u32 dispc_read_irqenable(void)
3626{
3627 return dispc_read_reg(DISPC_IRQENABLE);
3628}
3629
3630void dispc_write_irqenable(u32 mask)
3631{
3632 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3633
3634 /* clear the irqstatus for newly enabled irqs */
3635 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3636
3637 dispc_write_reg(DISPC_IRQENABLE, mask);
3638}
3639
80c39712
TV		 3640/* dispc.irq_lock has to be locked by the caller */
3641static void _omap_dispc_set_irqs(void)
3642{
3643 u32 mask;
80c39712
TV		 3644 int i;
3645 struct omap_dispc_isr_data *isr_data;
3646
3647 mask = dispc.irq_error_mask;
3648
3649 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3650 isr_data = &dispc.registered_isr[i];
3651
3652 if (isr_data->isr == NULL)
3653 continue;
3654
3655 mask |= isr_data->mask;
3656 }
3657
4e0397cf 3658 dispc_write_irqenable(mask);
80c39712
TV		 3659}
3660
3661int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3662{
3663 int i;
3664 int ret;
3665 unsigned long flags;
3666 struct omap_dispc_isr_data *isr_data;
3667
3668 if (isr == NULL)
3669 return -EINVAL;
3670
3671 spin_lock_irqsave(&dispc.irq_lock, flags);
3672
3673 /* check for duplicate entry */
3674 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3675 isr_data = &dispc.registered_isr[i];
3676 if (isr_data->isr == isr && isr_data->arg == arg &&
3677 isr_data->mask == mask) {
3678 ret = -EINVAL;
3679 goto err;
3680 }
3681 }
3682
3683 isr_data = NULL;
3684 ret = -EBUSY;
3685
3686 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3687 isr_data = &dispc.registered_isr[i];
3688
3689 if (isr_data->isr != NULL)
3690 continue;
3691
3692 isr_data->isr = isr;
3693 isr_data->arg = arg;
3694 isr_data->mask = mask;
3695 ret = 0;
3696
3697 break;
3698 }
3699
b9cb0984
TV		 3700 if (ret)
3701 goto err;
3702
80c39712
TV		 3703 _omap_dispc_set_irqs();
3704
3705 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3706
3707 return 0;
3708err:
3709 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3710
3711 return ret;
3712}
3713EXPORT_SYMBOL(omap_dispc_register_isr);
3714
3715int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3716{
3717 int i;
3718 unsigned long flags;
3719 int ret = -EINVAL;
3720 struct omap_dispc_isr_data *isr_data;
3721
3722 spin_lock_irqsave(&dispc.irq_lock, flags);
3723
3724 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3725 isr_data = &dispc.registered_isr[i];
3726 if (isr_data->isr != isr || isr_data->arg != arg ||
3727 isr_data->mask != mask)
3728 continue;
3729
3730 /* found the correct isr */
3731
3732 isr_data->isr = NULL;
3733 isr_data->arg = NULL;
3734 isr_data->mask = 0;
3735
3736 ret = 0;
3737 break;
3738 }
3739
3740 if (ret == 0)
3741 _omap_dispc_set_irqs();
3742
3743 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3744
3745 return ret;
3746}
3747EXPORT_SYMBOL(omap_dispc_unregister_isr);
3748
80c39712
TV		 3749static void print_irq_status(u32 status)
3750{
3751 if ((status & dispc.irq_error_mask) == 0)
3752 return;
3753
f30be7d3
CM		 3754#define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : ""
3755
3756 pr_debug("DISPC IRQ: 0x%x: %s%s%s%s%s%s%s%s%s\n",
3757 status,
3758 PIS(OCP_ERR),
3759 PIS(GFX_FIFO_UNDERFLOW),
3760 PIS(VID1_FIFO_UNDERFLOW),
3761 PIS(VID2_FIFO_UNDERFLOW),
3762 dss_feat_get_num_ovls() > 3 ? PIS(VID3_FIFO_UNDERFLOW) : "",
3763 PIS(SYNC_LOST),
3764 PIS(SYNC_LOST_DIGIT),
3765 dss_has_feature(FEAT_MGR_LCD2) ? PIS(SYNC_LOST2) : "",
3766 dss_has_feature(FEAT_MGR_LCD3) ? PIS(SYNC_LOST3) : "");
80c39712 3767#undef PIS
80c39712 3768}
80c39712
TV		 3769
3770/* Called from dss.c. Note that we don't touch clocks here,
3771 * but we presume they are on because we got an IRQ. However,
3772 * an irq handler may turn the clocks off, so we may not have
3773 * clock later in the function. */
affe360d 3774static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3775{
3776 int i;
affe360d 3777 u32 irqstatus, irqenable;
80c39712
TV		 3778 u32 handledirqs = 0;
3779 u32 unhandled_errors;
3780 struct omap_dispc_isr_data *isr_data;
3781 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3782
3783 spin_lock(&dispc.irq_lock);
3784
4e0397cf
TV		 3785 irqstatus = dispc_read_irqstatus();
3786 irqenable = dispc_read_irqenable();
affe360d 3787
3788 /* IRQ is not for us */
3789 if (!(irqstatus & irqenable)) {
3790 spin_unlock(&dispc.irq_lock);
3791 return IRQ_NONE;
3792 }
80c39712 3793
dfc0fd8d
TV		 3794#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3795 spin_lock(&dispc.irq_stats_lock);
3796 dispc.irq_stats.irq_count++;
3797 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3798 spin_unlock(&dispc.irq_stats_lock);
3799#endif
3800
28bcd199
CM		 3801 print_irq_status(irqstatus);
3802
80c39712
TV		 3803 /* Ack the interrupt. Do it here before clocks are possibly turned
3804 * off */
4e0397cf 3805 dispc_clear_irqstatus(irqstatus);
80c39712 3806 /* flush posted write */
4e0397cf 3807 dispc_read_irqstatus();
80c39712
TV		 3808
3809 /* make a copy and unlock, so that isrs can unregister
3810 * themselves */
3811 memcpy(registered_isr, dispc.registered_isr,
3812 sizeof(registered_isr));
3813
3814 spin_unlock(&dispc.irq_lock);
3815
3816 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3817 isr_data = &registered_isr[i];
3818
3819 if (!isr_data->isr)
3820 continue;
3821
3822 if (isr_data->mask & irqstatus) {
3823 isr_data->isr(isr_data->arg, irqstatus);
3824 handledirqs |= isr_data->mask;
3825 }
3826 }
3827
3828 spin_lock(&dispc.irq_lock);
3829
3830 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3831
3832 if (unhandled_errors) {
3833 dispc.error_irqs |= unhandled_errors;
3834
3835 dispc.irq_error_mask &= ~unhandled_errors;
3836 _omap_dispc_set_irqs();
3837
3838 schedule_work(&dispc.error_work);
3839 }
3840
3841 spin_unlock(&dispc.irq_lock);
affe360d 3842
3843 return IRQ_HANDLED;
80c39712
TV		 3844}
3845
3846static void dispc_error_worker(struct work_struct *work)
3847{
3848 int i;
3849 u32 errors;
3850 unsigned long flags;
fe3cc9d6
TV		 3851 static const unsigned fifo_underflow_bits[] = {
3852 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3853 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3854 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3855 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3856 };
3857
80c39712
TV		 3858 spin_lock_irqsave(&dispc.irq_lock, flags);
3859 errors = dispc.error_irqs;
3860 dispc.error_irqs = 0;
3861 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3862
13eae1f9
DZ		 3863 dispc_runtime_get();
3864
fe3cc9d6
TV		 3865 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3866 struct omap_overlay *ovl;
3867 unsigned bit;
80c39712 3868
fe3cc9d6
TV		 3869 ovl = omap_dss_get_overlay(i);
3870 bit = fifo_underflow_bits[i];
80c39712 3871
fe3cc9d6
TV		 3872 if (bit & errors) {
3873 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3874 ovl->name);
f0e5caab 3875 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3876 dispc_mgr_go(ovl->manager->id);
d7ad718d 3877 msleep(50);
80c39712
TV		 3878 }
3879 }
3880
fe3cc9d6
TV		 3881 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3882 struct omap_overlay_manager *mgr;
3883 unsigned bit;
80c39712 3884
fe3cc9d6 3885 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3886 bit = mgr_desc[i].sync_lost_irq;
80c39712 3887
fe3cc9d6 3888 if (bit & errors) {
4c6c65b0 3889 int j;
80c39712 3890
fe3cc9d6
TV		 3891 DSSERR("SYNC_LOST on channel %s, restarting the output "
3892 "with video overlays disabled\n",
3893 mgr->name);
2a205f34 3894
b276dd09 3895 dss_mgr_disable(mgr);
2a205f34 3896
4c6c65b0 3897 for (j = 0; j < omap_dss_get_num_overlays(); ++j) {
2a205f34 3898 struct omap_overlay *ovl;
4c6c65b0 3899 ovl = omap_dss_get_overlay(j);
2a205f34 3900
fe3cc9d6
TV		 3901 if (ovl->id != OMAP_DSS_GFX &&
3902 ovl->manager == mgr)
b276dd09 3903 ovl->disable(ovl);
2a205f34
SS		 3904 }
3905
b276dd09 3906 dss_mgr_enable(mgr);
2a205f34
SS		 3907 }
3908 }
3909
80c39712
TV		 3910 if (errors & DISPC_IRQ_OCP_ERR) {
3911 DSSERR("OCP_ERR\n");
3912 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3913 struct omap_overlay_manager *mgr;
794bc4ee 3914
80c39712 3915 mgr = omap_dss_get_overlay_manager(i);
b276dd09 3916 dss_mgr_disable(mgr);
80c39712
TV		 3917 }
3918 }
3919
3920 spin_lock_irqsave(&dispc.irq_lock, flags);
3921 dispc.irq_error_mask |= errors;
3922 _omap_dispc_set_irqs();
3923 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3924
3925 dispc_runtime_put();
80c39712
TV		 3926}
3927
3928int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3929{
3930 void dispc_irq_wait_handler(void *data, u32 mask)
3931 {
3932 complete((struct completion *)data);
3933 }
3934
3935 int r;
3936 DECLARE_COMPLETION_ONSTACK(completion);
3937
3938 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3939 irqmask);
3940
3941 if (r)
3942 return r;
3943
3944 timeout = wait_for_completion_timeout(&completion, timeout);
3945
3946 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3947
3948 if (timeout == 0)
3949 return -ETIMEDOUT;
3950
80c39712
TV		 3951 return 0;
3952}
3953
3954int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3955 unsigned long timeout)
3956{
3957 void dispc_irq_wait_handler(void *data, u32 mask)
3958 {
3959 complete((struct completion *)data);
3960 }
3961
3962 int r;
3963 DECLARE_COMPLETION_ONSTACK(completion);
3964
3965 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3966 irqmask);
3967
3968 if (r)
3969 return r;
3970
3971 timeout = wait_for_completion_interruptible_timeout(&completion,
3972 timeout);
3973
3974 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3975
3976 if (timeout == 0)
3977 return -ETIMEDOUT;
3978
3979 if (timeout == -ERESTARTSYS)
3980 return -ERESTARTSYS;
3981
3982 return 0;
3983}
3984
80c39712
TV		 3985static void _omap_dispc_initialize_irq(void)
3986{
3987 unsigned long flags;
3988
3989 spin_lock_irqsave(&dispc.irq_lock, flags);
3990
3991 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3992
3993 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3994 if (dss_has_feature(FEAT_MGR_LCD2))
3995 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
e86d456a
CM		 3996 if (dss_has_feature(FEAT_MGR_LCD3))
3997 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
b8c095b4
AT		 3998 if (dss_feat_get_num_ovls() > 3)
3999 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 4000
4001 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
4002 * so clear it */
4e0397cf 4003 dispc_clear_irqstatus(dispc_read_irqstatus());
80c39712
TV		 4004
4005 _omap_dispc_set_irqs();
4006
4007 spin_unlock_irqrestore(&dispc.irq_lock, flags);
4008}
4009
4010void dispc_enable_sidle(void)
4011{
4012 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
4013}
4014
4015void dispc_disable_sidle(void)
4016{
4017 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
4018}
4019
4020static void _omap_dispc_initial_config(void)
4021{
4022 u32 l;
4023
0cf35df3
MR		 4024 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
4025 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
4026 l = dispc_read_reg(DISPC_DIVISOR);
4027 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
4028 l = FLD_MOD(l, 1, 0, 0);
4029 l = FLD_MOD(l, 1, 23, 16);
4030 dispc_write_reg(DISPC_DIVISOR, l);
4031 }
4032
80c39712 4033 /* FUNCGATED */
6ced40bf
AT		 4034 if (dss_has_feature(FEAT_FUNCGATED))
4035 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 4036
6e5264b0 4037 dispc_setup_color_conv_coef();
80c39712
TV		 4038
4039 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
4040
42a6961c 4041 dispc_init_fifos();
5ed8cf5b
TV		 4042
4043 dispc_configure_burst_sizes();
54128701
AT		 4044
4045 dispc_ovl_enable_zorder_planes();
80c39712
TV		 4046}
4047
dcbe765b
CM		 4048static const struct dispc_features omap24xx_dispc_feats __initconst = {
4049 .sw_start = 5,
4050 .fp_start = 15,
4051 .bp_start = 27,
4052 .sw_max = 64,
4053 .vp_max = 255,
4054 .hp_max = 256,
33b89928
AT		 4055 .mgr_width_start = 10,
4056 .mgr_height_start = 26,
4057 .mgr_width_max = 2048,
4058 .mgr_height_max = 2048,
dcbe765b
CM		 4059 .calc_scaling = dispc_ovl_calc_scaling_24xx,
4060 .calc_core_clk = calc_core_clk_24xx,
42a6961c 4061 .num_fifos = 3,
cffa947d 4062 .no_framedone_tv = true,
dcbe765b
CM		 4063};
4064
4065static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
4066 .sw_start = 5,
4067 .fp_start = 15,
4068 .bp_start = 27,
4069 .sw_max = 64,
4070 .vp_max = 255,
4071 .hp_max = 256,
33b89928
AT		 4072 .mgr_width_start = 10,
4073 .mgr_height_start = 26,
4074 .mgr_width_max = 2048,
4075 .mgr_height_max = 2048,
dcbe765b
CM		 4076 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4077 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4078 .num_fifos = 3,
cffa947d 4079 .no_framedone_tv = true,
dcbe765b
CM		 4080};
4081
4082static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
4083 .sw_start = 7,
4084 .fp_start = 19,
4085 .bp_start = 31,
4086 .sw_max = 256,
4087 .vp_max = 4095,
4088 .hp_max = 4096,
33b89928
AT		 4089 .mgr_width_start = 10,
4090 .mgr_height_start = 26,
4091 .mgr_width_max = 2048,
4092 .mgr_height_max = 2048,
dcbe765b
CM		 4093 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4094 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4095 .num_fifos = 3,
cffa947d 4096 .no_framedone_tv = true,
dcbe765b
CM		 4097};
4098
4099static const struct dispc_features omap44xx_dispc_feats __initconst = {
4100 .sw_start = 7,
4101 .fp_start = 19,
4102 .bp_start = 31,
4103 .sw_max = 256,
4104 .vp_max = 4095,
4105 .hp_max = 4096,
33b89928
AT		 4106 .mgr_width_start = 10,
4107 .mgr_height_start = 26,
4108 .mgr_width_max = 2048,
4109 .mgr_height_max = 2048,
dcbe765b
CM		 4110 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4111 .calc_core_clk = calc_core_clk_44xx,
42a6961c 4112 .num_fifos = 5,
66a0f9e4 4113 .gfx_fifo_workaround = true,
dcbe765b
CM		 4114};
4115
264236f8
AT		 4116static const struct dispc_features omap54xx_dispc_feats __initconst = {
4117 .sw_start = 7,
4118 .fp_start = 19,
4119 .bp_start = 31,
4120 .sw_max = 256,
4121 .vp_max = 4095,
4122 .hp_max = 4096,
4123 .mgr_width_start = 11,
4124 .mgr_height_start = 27,
4125 .mgr_width_max = 4096,
4126 .mgr_height_max = 4096,
4127 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4128 .calc_core_clk = calc_core_clk_44xx,
4129 .num_fifos = 5,
4130 .gfx_fifo_workaround = true,
4131};
4132
84b47623 4133static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 4134{
4135 const struct dispc_features *src;
4136 struct dispc_features *dst;
4137
84b47623 4138 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 4139 if (!dst) {
84b47623 4140 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 4141 return -ENOMEM;
4142 }
4143
b2c7d54f 4144 switch (omapdss_get_version()) {
84b47623 4145 case OMAPDSS_VER_OMAP24xx:
dcbe765b 4146 src = &omap24xx_dispc_feats;
84b47623
TV		 4147 break;
4148
4149 case OMAPDSS_VER_OMAP34xx_ES1:
4150 src = &omap34xx_rev1_0_dispc_feats;
4151 break;
4152
4153 case OMAPDSS_VER_OMAP34xx_ES3:
4154 case OMAPDSS_VER_OMAP3630:
4155 case OMAPDSS_VER_AM35xx:
4156 src = &omap34xx_rev3_0_dispc_feats;
4157 break;
4158
4159 case OMAPDSS_VER_OMAP4430_ES1:
4160 case OMAPDSS_VER_OMAP4430_ES2:
4161 case OMAPDSS_VER_OMAP4:
dcbe765b 4162 src = &omap44xx_dispc_feats;
84b47623
TV		 4163 break;
4164
4165 case OMAPDSS_VER_OMAP5:
264236f8 4166 src = &omap54xx_dispc_feats;
84b47623
TV		 4167 break;
4168
4169 default:
dcbe765b
CM		 4170 return -ENODEV;
4171 }
4172
4173 memcpy(dst, src, sizeof(*dst));
4174 dispc.feat = dst;
4175
4176 return 0;
4177}
4178
060b6d9c 4179/* DISPC HW IP initialisation */
6e7e8f06 4180static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 4181{
4182 u32 rev;
affe360d 4183 int r = 0;
ea9da36a 4184 struct resource *dispc_mem;
4fbafaf3 4185 struct clk *clk;
ea9da36a 4186
060b6d9c
SG		 4187 dispc.pdev = pdev;
4188
84b47623 4189 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4190 if (r)
4191 return r;
4192
060b6d9c
SG		 4193 spin_lock_init(&dispc.irq_lock);
4194
4195#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4196 spin_lock_init(&dispc.irq_stats_lock);
4197 dispc.irq_stats.last_reset = jiffies;
4198#endif
4199
4200 INIT_WORK(&dispc.error_work, dispc_error_worker);
4201
ea9da36a
SG		 4202 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4203 if (!dispc_mem) {
4204 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 4205 return -EINVAL;
ea9da36a 4206 }
cd3b3449 4207
6e2a14d2
JL		 4208 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4209 resource_size(dispc_mem));
060b6d9c
SG		 4210 if (!dispc.base) {
4211 DSSERR("can't ioremap DISPC\n");
cd3b3449 4212 return -ENOMEM;
affe360d 4213 }
cd3b3449 4214
affe360d 4215 dispc.irq = platform_get_irq(dispc.pdev, 0);
4216 if (dispc.irq < 0) {
4217 DSSERR("platform_get_irq failed\n");
cd3b3449 4218 return -ENODEV;
affe360d 4219 }
4220
6e2a14d2
JL		 4221 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
4222 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 4223 if (r < 0) {
4224 DSSERR("request_irq failed\n");
cd3b3449
TV		 4225 return r;
4226 }
4227
4228 clk = clk_get(&pdev->dev, "fck");
4229 if (IS_ERR(clk)) {
4230 DSSERR("can't get fck\n");
4231 r = PTR_ERR(clk);
4232 return r;
060b6d9c
SG		 4233 }
4234
cd3b3449
TV		 4235 dispc.dss_clk = clk;
4236
4fbafaf3
TV		 4237 pm_runtime_enable(&pdev->dev);
4238
4239 r = dispc_runtime_get();
4240 if (r)
4241 goto err_runtime_get;
060b6d9c
SG		 4242
4243 _omap_dispc_initial_config();
4244
4245 _omap_dispc_initialize_irq();
4246
060b6d9c 4247 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4248 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4249 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4250
4fbafaf3 4251 dispc_runtime_put();
060b6d9c 4252
e40402cf
TV		 4253 dss_debugfs_create_file("dispc", dispc_dump_regs);
4254
4255#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4256 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
4257#endif
060b6d9c 4258 return 0;
4fbafaf3
TV		 4259
4260err_runtime_get:
4261 pm_runtime_disable(&pdev->dev);
4fbafaf3 4262 clk_put(dispc.dss_clk);
affe360d 4263 return r;
060b6d9c
SG		 4264}
4265
6e7e8f06 4266static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 4267{
4fbafaf3
TV		 4268 pm_runtime_disable(&pdev->dev);
4269
4270 clk_put(dispc.dss_clk);
4271
060b6d9c
SG		 4272 return 0;
4273}
4274
4fbafaf3
TV		 4275static int dispc_runtime_suspend(struct device *dev)
4276{
4277 dispc_save_context();
4fbafaf3
TV		 4278
4279 return 0;
4280}
4281
4282static int dispc_runtime_resume(struct device *dev)
4283{
49ea86f3 4284 dispc_restore_context();
4fbafaf3
TV		 4285
4286 return 0;
4287}
4288
4289static const struct dev_pm_ops dispc_pm_ops = {
4290 .runtime_suspend = dispc_runtime_suspend,
4291 .runtime_resume = dispc_runtime_resume,
4292};
4293
060b6d9c 4294static struct platform_driver omap_dispchw_driver = {
6e7e8f06 4295 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 4296 .driver = {
4297 .name = "omapdss_dispc",
4298 .owner = THIS_MODULE,
4fbafaf3 4299 .pm = &dispc_pm_ops,
060b6d9c
SG		 4300 },
4301};
4302
6e7e8f06 4303int __init dispc_init_platform_driver(void)
060b6d9c 4304{
11436e1d 4305 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 4306}
4307
6e7e8f06 4308void __exit dispc_uninit_platform_driver(void)
060b6d9c 4309{
04c742c3 4310 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4311}
Linux kernel - Deliverables
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