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OMAP: DSS2: DSI: sync when disabling a display
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
24e6289c 36#include <linux/platform_device.h>
80c39712
TV		 37
38#include <plat/sram.h>
39#include <plat/clock.h>
40
a0b38cc4 41#include <video/omapdss.h>
80c39712
TV		 42
43#include "dss.h"
a0acb557 44#include "dss_features.h"
9b372c2d 45#include "dispc.h"
80c39712
TV		 46
47/* DISPC */
8613b000 48#define DISPC_SZ_REGS SZ_4K
80c39712 49
80c39712
TV		 50#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
51 DISPC_IRQ_OCP_ERR | \
52 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
53 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
54 DISPC_IRQ_SYNC_LOST | \
55 DISPC_IRQ_SYNC_LOST_DIGIT)
56
57#define DISPC_MAX_NR_ISRS 8
58
59struct omap_dispc_isr_data {
60 omap_dispc_isr_t isr;
61 void *arg;
62 u32 mask;
63};
64
66be8f6c
GI		 65struct dispc_h_coef {
66 s8 hc4;
67 s8 hc3;
68 u8 hc2;
69 s8 hc1;
70 s8 hc0;
71};
72
73struct dispc_v_coef {
74 s8 vc22;
75 s8 vc2;
76 u8 vc1;
77 s8 vc0;
78 s8 vc00;
79};
80
80c39712
TV		 81#define REG_GET(idx, start, end) \
82 FLD_GET(dispc_read_reg(idx), start, end)
83
84#define REG_FLD_MOD(idx, val, start, end) \
85 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
86
dfc0fd8d
TV		 87struct dispc_irq_stats {
88 unsigned long last_reset;
89 unsigned irq_count;
90 unsigned irqs[32];
91};
92
80c39712 93static struct {
060b6d9c 94 struct platform_device *pdev;
80c39712 95 void __iomem *base;
affe360d 96 int irq;
80c39712
TV		 97
98 u32 fifo_size[3];
99
100 spinlock_t irq_lock;
101 u32 irq_error_mask;
102 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
103 u32 error_irqs;
104 struct work_struct error_work;
105
106 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 107
108#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
109 spinlock_t irq_stats_lock;
110 struct dispc_irq_stats irq_stats;
111#endif
80c39712
TV		 112} dispc;
113
0d66cbb5
AJ		 114enum omap_color_component {
115 /* used for all color formats for OMAP3 and earlier
116 * and for RGB and Y color component on OMAP4
117 */
118 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
119 /* used for UV component for
120 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
121 * color formats on OMAP4
122 */
123 DISPC_COLOR_COMPONENT_UV = 1 << 1,
124};
125
80c39712
TV		 126static void _omap_dispc_set_irqs(void);
127
55978cc2 128static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 129{
55978cc2 130 __raw_writel(val, dispc.base + idx);
80c39712
TV		 131}
132
55978cc2 133static inline u32 dispc_read_reg(const u16 idx)
80c39712 134{
55978cc2 135 return __raw_readl(dispc.base + idx);
80c39712
TV		 136}
137
138#define SR(reg) \
55978cc2 139 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 140#define RR(reg) \
55978cc2 141 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712
TV		 142
143void dispc_save_context(void)
144{
5719d35c 145 int i;
80c39712
TV		 146 if (cpu_is_omap24xx())
147 return;
148
149 SR(SYSCONFIG);
150 SR(IRQENABLE);
151 SR(CONTROL);
152 SR(CONFIG);
702d1448
AT		 153 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
154 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
155 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
156 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712 157 SR(LINE_NUMBER);
702d1448
AT		 158 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
159 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
160 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
161 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
332e9d70
TV		 162 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
163 SR(GLOBAL_ALPHA);
702d1448
AT		 164 SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
165 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34
SS		 166 if (dss_has_feature(FEAT_MGR_LCD2)) {
167 SR(CONTROL2);
702d1448
AT		 168 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
169 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
170 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
171 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
172 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
173 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
174 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2a205f34
SS		 175 SR(CONFIG2);
176 }
80c39712 177
9b372c2d
AT		 178 SR(OVL_BA0(OMAP_DSS_GFX));
179 SR(OVL_BA1(OMAP_DSS_GFX));
180 SR(OVL_POSITION(OMAP_DSS_GFX));
181 SR(OVL_SIZE(OMAP_DSS_GFX));
182 SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
183 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
184 SR(OVL_ROW_INC(OMAP_DSS_GFX));
185 SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
186 SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
187 SR(OVL_TABLE_BA(OMAP_DSS_GFX));
80c39712 188
702d1448
AT		 189 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
190 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
191 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 192
332e9d70
TV		 193 if (dss_has_feature(FEAT_CPR)) {
194 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
195 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
196 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
197 }
2a205f34 198 if (dss_has_feature(FEAT_MGR_LCD2)) {
332e9d70
TV		 199 if (dss_has_feature(FEAT_CPR)) {
200 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
201 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
202 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
203 }
2a205f34 204
702d1448
AT		 205 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
206 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
207 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 208 }
80c39712 209
332e9d70
TV		 210 if (dss_has_feature(FEAT_PRELOAD))
211 SR(OVL_PRELOAD(OMAP_DSS_GFX));
80c39712
TV		 212
213 /* VID1 */
9b372c2d
AT		 214 SR(OVL_BA0(OMAP_DSS_VIDEO1));
215 SR(OVL_BA1(OMAP_DSS_VIDEO1));
216 SR(OVL_POSITION(OMAP_DSS_VIDEO1));
217 SR(OVL_SIZE(OMAP_DSS_VIDEO1));
218 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
219 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
220 SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
221 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
222 SR(OVL_FIR(OMAP_DSS_VIDEO1));
223 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
224 SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
225 SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
226
5719d35c
AJ		 227 for (i = 0; i < 8; i++)
228 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
229
230 for (i = 0; i < 8; i++)
231 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
232
233 for (i = 0; i < 5; i++)
234 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
235
332e9d70
TV		 236 if (dss_has_feature(FEAT_FIR_COEF_V)) {
237 for (i = 0; i < 8; i++)
238 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
239 }
9b372c2d 240
ab5ca071
AJ		 241 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
242 SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
243 SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
244 SR(OVL_FIR2(OMAP_DSS_VIDEO1));
245 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
246 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
247
248 for (i = 0; i < 8; i++)
249 SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
250
251 for (i = 0; i < 8; i++)
252 SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
253
254 for (i = 0; i < 8; i++)
255 SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
256 }
257 if (dss_has_feature(FEAT_ATTR2))
258 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
259
332e9d70
TV		 260 if (dss_has_feature(FEAT_PRELOAD))
261 SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
80c39712
TV		 262
263 /* VID2 */
9b372c2d
AT		 264 SR(OVL_BA0(OMAP_DSS_VIDEO2));
265 SR(OVL_BA1(OMAP_DSS_VIDEO2));
266 SR(OVL_POSITION(OMAP_DSS_VIDEO2));
267 SR(OVL_SIZE(OMAP_DSS_VIDEO2));
268 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
269 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
270 SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
271 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
272 SR(OVL_FIR(OMAP_DSS_VIDEO2));
273 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
274 SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
275 SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
276
5719d35c
AJ		 277 for (i = 0; i < 8; i++)
278 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
279
280 for (i = 0; i < 8; i++)
281 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
282
283 for (i = 0; i < 5; i++)
284 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
285
332e9d70
TV		 286 if (dss_has_feature(FEAT_FIR_COEF_V)) {
287 for (i = 0; i < 8; i++)
288 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
289 }
9b372c2d 290
ab5ca071
AJ		 291 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
292 SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
293 SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
294 SR(OVL_FIR2(OMAP_DSS_VIDEO2));
295 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
296 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
297
298 for (i = 0; i < 8; i++)
299 SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
300
301 for (i = 0; i < 8; i++)
302 SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
303
304 for (i = 0; i < 8; i++)
305 SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
306 }
307 if (dss_has_feature(FEAT_ATTR2))
308 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
309
332e9d70
TV		 310 if (dss_has_feature(FEAT_PRELOAD))
311 SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
0cf35df3
MR		 312
313 if (dss_has_feature(FEAT_CORE_CLK_DIV))
314 SR(DIVISOR);
80c39712
TV		 315}
316
317void dispc_restore_context(void)
318{
5719d35c 319 int i;
80c39712 320 RR(SYSCONFIG);
75c7d59d 321 /*RR(IRQENABLE);*/
80c39712
TV		 322 /*RR(CONTROL);*/
323 RR(CONFIG);
702d1448
AT		 324 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
325 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
326 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
327 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712 328 RR(LINE_NUMBER);
702d1448
AT		 329 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
330 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
331 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
332 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
332e9d70
TV		 333 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
334 RR(GLOBAL_ALPHA);
702d1448
AT		 335 RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
336 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34 337 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 338 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
339 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
340 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
341 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
342 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
343 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
344 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2a205f34
SS		 345 RR(CONFIG2);
346 }
80c39712 347
9b372c2d
AT		 348 RR(OVL_BA0(OMAP_DSS_GFX));
349 RR(OVL_BA1(OMAP_DSS_GFX));
350 RR(OVL_POSITION(OMAP_DSS_GFX));
351 RR(OVL_SIZE(OMAP_DSS_GFX));
352 RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
353 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
354 RR(OVL_ROW_INC(OMAP_DSS_GFX));
355 RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
356 RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
357 RR(OVL_TABLE_BA(OMAP_DSS_GFX));
358
80c39712 359
702d1448
AT		 360 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
361 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
362 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 363
332e9d70
TV		 364 if (dss_has_feature(FEAT_CPR)) {
365 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
366 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
367 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
368 }
2a205f34 369 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 370 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
371 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
372 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 373
332e9d70
TV		 374 if (dss_has_feature(FEAT_CPR)) {
375 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
376 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
377 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
378 }
2a205f34 379 }
80c39712 380
332e9d70
TV		 381 if (dss_has_feature(FEAT_PRELOAD))
382 RR(OVL_PRELOAD(OMAP_DSS_GFX));
80c39712
TV		 383
384 /* VID1 */
9b372c2d
AT		 385 RR(OVL_BA0(OMAP_DSS_VIDEO1));
386 RR(OVL_BA1(OMAP_DSS_VIDEO1));
387 RR(OVL_POSITION(OMAP_DSS_VIDEO1));
388 RR(OVL_SIZE(OMAP_DSS_VIDEO1));
389 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
390 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
391 RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
392 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
393 RR(OVL_FIR(OMAP_DSS_VIDEO1));
394 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
395 RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
396 RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
397
5719d35c
AJ		 398 for (i = 0; i < 8; i++)
399 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
400
401 for (i = 0; i < 8; i++)
402 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
403
404 for (i = 0; i < 5; i++)
405 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
406
332e9d70
TV		 407 if (dss_has_feature(FEAT_FIR_COEF_V)) {
408 for (i = 0; i < 8; i++)
409 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
410 }
9b372c2d 411
ab5ca071
AJ		 412 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
413 RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
414 RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
415 RR(OVL_FIR2(OMAP_DSS_VIDEO1));
416 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
417 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
418
419 for (i = 0; i < 8; i++)
420 RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
421
422 for (i = 0; i < 8; i++)
423 RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
424
425 for (i = 0; i < 8; i++)
426 RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
427 }
428 if (dss_has_feature(FEAT_ATTR2))
429 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
430
332e9d70
TV		 431 if (dss_has_feature(FEAT_PRELOAD))
432 RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
80c39712
TV		 433
434 /* VID2 */
9b372c2d
AT		 435 RR(OVL_BA0(OMAP_DSS_VIDEO2));
436 RR(OVL_BA1(OMAP_DSS_VIDEO2));
437 RR(OVL_POSITION(OMAP_DSS_VIDEO2));
438 RR(OVL_SIZE(OMAP_DSS_VIDEO2));
439 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
440 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
441 RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
442 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
443 RR(OVL_FIR(OMAP_DSS_VIDEO2));
444 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
445 RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
446 RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
447
5719d35c
AJ		 448 for (i = 0; i < 8; i++)
449 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
450
451 for (i = 0; i < 8; i++)
452 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
453
454 for (i = 0; i < 5; i++)
455 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
456
332e9d70
TV		 457 if (dss_has_feature(FEAT_FIR_COEF_V)) {
458 for (i = 0; i < 8; i++)
459 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
460 }
9b372c2d 461
ab5ca071
AJ		 462 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
463 RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
464 RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
465 RR(OVL_FIR2(OMAP_DSS_VIDEO2));
466 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
467 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
468
469 for (i = 0; i < 8; i++)
470 RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
471
472 for (i = 0; i < 8; i++)
473 RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
474
475 for (i = 0; i < 8; i++)
476 RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
477 }
478 if (dss_has_feature(FEAT_ATTR2))
479 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
480
332e9d70
TV		 481 if (dss_has_feature(FEAT_PRELOAD))
482 RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
80c39712 483
0cf35df3
MR		 484 if (dss_has_feature(FEAT_CORE_CLK_DIV))
485 RR(DIVISOR);
486
80c39712
TV		 487 /* enable last, because LCD & DIGIT enable are here */
488 RR(CONTROL);
2a205f34
SS		 489 if (dss_has_feature(FEAT_MGR_LCD2))
490 RR(CONTROL2);
75c7d59d
VS		 491 /* clear spurious SYNC_LOST_DIGIT interrupts */
492 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
493
494 /*
495 * enable last so IRQs won't trigger before
496 * the context is fully restored
497 */
498 RR(IRQENABLE);
80c39712
TV		 499}
500
501#undef SR
502#undef RR
503
504static inline void enable_clocks(bool enable)
505{
506 if (enable)
6af9cd14 507 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712 508 else
6af9cd14 509 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 510}
511
512bool dispc_go_busy(enum omap_channel channel)
513{
514 int bit;
515
2a205f34
SS		 516 if (channel == OMAP_DSS_CHANNEL_LCD ||
517 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 518 bit = 5; /* GOLCD */
519 else
520 bit = 6; /* GODIGIT */
521
2a205f34
SS		 522 if (channel == OMAP_DSS_CHANNEL_LCD2)
523 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
524 else
525 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 526}
527
528void dispc_go(enum omap_channel channel)
529{
530 int bit;
2a205f34 531 bool enable_bit, go_bit;
80c39712
TV		 532
533 enable_clocks(1);
534
2a205f34
SS		 535 if (channel == OMAP_DSS_CHANNEL_LCD ||
536 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 537 bit = 0; /* LCDENABLE */
538 else
539 bit = 1; /* DIGITALENABLE */
540
541 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 542 if (channel == OMAP_DSS_CHANNEL_LCD2)
543 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
544 else
545 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
546
547 if (!enable_bit)
80c39712
TV		 548 goto end;
549
2a205f34
SS		 550 if (channel == OMAP_DSS_CHANNEL_LCD ||
551 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 552 bit = 5; /* GOLCD */
553 else
554 bit = 6; /* GODIGIT */
555
2a205f34
SS		 556 if (channel == OMAP_DSS_CHANNEL_LCD2)
557 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
558 else
559 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
560
561 if (go_bit) {
80c39712
TV		 562 DSSERR("GO bit not down for channel %d\n", channel);
563 goto end;
564 }
565
2a205f34
SS		 566 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
567 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 568
2a205f34
SS		 569 if (channel == OMAP_DSS_CHANNEL_LCD2)
570 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
571 else
572 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 573end:
574 enable_clocks(0);
575}
576
577static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
578{
9b372c2d 579 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 580}
581
582static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
583{
9b372c2d 584 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 585}
586
587static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
588{
9b372c2d 589 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 590}
591
ab5ca071
AJ		 592static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
593{
594 BUG_ON(plane == OMAP_DSS_GFX);
595
596 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
597}
598
599static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
600{
601 BUG_ON(plane == OMAP_DSS_GFX);
602
603 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
604}
605
606static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
607{
608 BUG_ON(plane == OMAP_DSS_GFX);
609
610 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
611}
612
80c39712 613static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
0d66cbb5
AJ		 614 int vscaleup, int five_taps,
615 enum omap_color_component color_comp)
80c39712
TV		 616{
617 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 618 static const struct dispc_h_coef coef_hup[8] = {
619 { 0, 0, 128, 0, 0 },
620 { -1, 13, 124, -8, 0 },
621 { -2, 30, 112, -11, -1 },
622 { -5, 51, 95, -11, -2 },
623 { 0, -9, 73, 73, -9 },
624 { -2, -11, 95, 51, -5 },
625 { -1, -11, 112, 30, -2 },
626 { 0, -8, 124, 13, -1 },
80c39712
TV		 627 };
628
66be8f6c
GI		 629 /* Coefficients for vertical up-sampling */
630 static const struct dispc_v_coef coef_vup_3tap[8] = {
631 { 0, 0, 128, 0, 0 },
632 { 0, 3, 123, 2, 0 },
633 { 0, 12, 111, 5, 0 },
634 { 0, 32, 89, 7, 0 },
635 { 0, 0, 64, 64, 0 },
636 { 0, 7, 89, 32, 0 },
637 { 0, 5, 111, 12, 0 },
638 { 0, 2, 123, 3, 0 },
80c39712
TV		 639 };
640
66be8f6c
GI		 641 static const struct dispc_v_coef coef_vup_5tap[8] = {
642 { 0, 0, 128, 0, 0 },
643 { -1, 13, 124, -8, 0 },
644 { -2, 30, 112, -11, -1 },
645 { -5, 51, 95, -11, -2 },
646 { 0, -9, 73, 73, -9 },
647 { -2, -11, 95, 51, -5 },
648 { -1, -11, 112, 30, -2 },
649 { 0, -8, 124, 13, -1 },
80c39712
TV		 650 };
651
66be8f6c
GI		 652 /* Coefficients for horizontal down-sampling */
653 static const struct dispc_h_coef coef_hdown[8] = {
654 { 0, 36, 56, 36, 0 },
655 { 4, 40, 55, 31, -2 },
656 { 8, 44, 54, 27, -5 },
657 { 12, 48, 53, 22, -7 },
658 { -9, 17, 52, 51, 17 },
659 { -7, 22, 53, 48, 12 },
660 { -5, 27, 54, 44, 8 },
661 { -2, 31, 55, 40, 4 },
80c39712
TV		 662 };
663
66be8f6c
GI		 664 /* Coefficients for vertical down-sampling */
665 static const struct dispc_v_coef coef_vdown_3tap[8] = {
666 { 0, 36, 56, 36, 0 },
667 { 0, 40, 57, 31, 0 },
668 { 0, 45, 56, 27, 0 },
669 { 0, 50, 55, 23, 0 },
670 { 0, 18, 55, 55, 0 },
671 { 0, 23, 55, 50, 0 },
672 { 0, 27, 56, 45, 0 },
673 { 0, 31, 57, 40, 0 },
80c39712
TV		 674 };
675
66be8f6c
GI		 676 static const struct dispc_v_coef coef_vdown_5tap[8] = {
677 { 0, 36, 56, 36, 0 },
678 { 4, 40, 55, 31, -2 },
679 { 8, 44, 54, 27, -5 },
680 { 12, 48, 53, 22, -7 },
681 { -9, 17, 52, 51, 17 },
682 { -7, 22, 53, 48, 12 },
683 { -5, 27, 54, 44, 8 },
684 { -2, 31, 55, 40, 4 },
80c39712
TV		 685 };
686
66be8f6c
GI		 687 const struct dispc_h_coef *h_coef;
688 const struct dispc_v_coef *v_coef;
80c39712
TV		 689 int i;
690
691 if (hscaleup)
692 h_coef = coef_hup;
693 else
694 h_coef = coef_hdown;
695
66be8f6c
GI		 696 if (vscaleup)
697 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
698 else
699 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 700
701 for (i = 0; i < 8; i++) {
702 u32 h, hv;
703
66be8f6c
GI		 704 h = FLD_VAL(h_coef[i].hc0, 7, 0)
705 | FLD_VAL(h_coef[i].hc1, 15, 8)
706 | FLD_VAL(h_coef[i].hc2, 23, 16)
707 | FLD_VAL(h_coef[i].hc3, 31, 24);
708 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
709 | FLD_VAL(v_coef[i].vc0, 15, 8)
710 | FLD_VAL(v_coef[i].vc1, 23, 16)
711 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712 712
0d66cbb5
AJ		 713 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
714 _dispc_write_firh_reg(plane, i, h);
715 _dispc_write_firhv_reg(plane, i, hv);
716 } else {
717 _dispc_write_firh2_reg(plane, i, h);
718 _dispc_write_firhv2_reg(plane, i, hv);
719 }
720
80c39712
TV		 721 }
722
66be8f6c
GI		 723 if (five_taps) {
724 for (i = 0; i < 8; i++) {
725 u32 v;
726 v = FLD_VAL(v_coef[i].vc00, 7, 0)
727 | FLD_VAL(v_coef[i].vc22, 15, 8);
0d66cbb5
AJ		 728 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
729 _dispc_write_firv_reg(plane, i, v);
730 else
731 _dispc_write_firv2_reg(plane, i, v);
66be8f6c 732 }
80c39712
TV		 733 }
734}
735
736static void _dispc_setup_color_conv_coef(void)
737{
738 const struct color_conv_coef {
739 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
740 int full_range;
741 } ctbl_bt601_5 = {
742 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
743 };
744
745 const struct color_conv_coef *ct;
746
747#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
748
749 ct = &ctbl_bt601_5;
750
9b372c2d
AT		 751 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
752 CVAL(ct->rcr, ct->ry));
753 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
754 CVAL(ct->gy, ct->rcb));
755 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
756 CVAL(ct->gcb, ct->gcr));
757 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
758 CVAL(ct->bcr, ct->by));
759 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
760 CVAL(0, ct->bcb));
761
762 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
763 CVAL(ct->rcr, ct->ry));
764 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
765 CVAL(ct->gy, ct->rcb));
766 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
767 CVAL(ct->gcb, ct->gcr));
768 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
769 CVAL(ct->bcr, ct->by));
770 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
771 CVAL(0, ct->bcb));
80c39712
TV		 772
773#undef CVAL
774
9b372c2d
AT		 775 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
776 ct->full_range, 11, 11);
777 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
778 ct->full_range, 11, 11);
80c39712
TV		 779}
780
781
782static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
783{
9b372c2d 784 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 785}
786
787static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
788{
9b372c2d 789 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 790}
791
ab5ca071
AJ		 792static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
793{
794 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
795}
796
797static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
798{
799 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
800}
801
80c39712
TV		 802static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
803{
80c39712 804 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 805
806 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 807}
808
809static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
810{
80c39712 811 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 812
813 if (plane == OMAP_DSS_GFX)
814 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
815 else
816 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 817}
818
819static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
820{
821 u32 val;
80c39712
TV		 822
823 BUG_ON(plane == OMAP_DSS_GFX);
824
825 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 826
827 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 828}
829
fd28a390
R		 830static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
831{
832 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
833 return;
834
835 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
836 plane == OMAP_DSS_VIDEO1)
837 return;
838
9b372c2d 839 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 840}
841
80c39712
TV		 842static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
843{
a0acb557 844 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 845 return;
846
fd28a390
R		 847 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
848 plane == OMAP_DSS_VIDEO1)
849 return;
a0acb557 850
80c39712
TV		 851 if (plane == OMAP_DSS_GFX)
852 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
853 else if (plane == OMAP_DSS_VIDEO2)
854 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
855}
856
857static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
858{
9b372c2d 859 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 860}
861
862static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
863{
9b372c2d 864 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 865}
866
867static void _dispc_set_color_mode(enum omap_plane plane,
868 enum omap_color_mode color_mode)
869{
870 u32 m = 0;
f20e4220
AJ		 871 if (plane != OMAP_DSS_GFX) {
872 switch (color_mode) {
873 case OMAP_DSS_COLOR_NV12:
874 m = 0x0; break;
875 case OMAP_DSS_COLOR_RGB12U:
876 m = 0x1; break;
877 case OMAP_DSS_COLOR_RGBA16:
878 m = 0x2; break;
879 case OMAP_DSS_COLOR_RGBX16:
880 m = 0x4; break;
881 case OMAP_DSS_COLOR_ARGB16:
882 m = 0x5; break;
883 case OMAP_DSS_COLOR_RGB16:
884 m = 0x6; break;
885 case OMAP_DSS_COLOR_ARGB16_1555:
886 m = 0x7; break;
887 case OMAP_DSS_COLOR_RGB24U:
888 m = 0x8; break;
889 case OMAP_DSS_COLOR_RGB24P:
890 m = 0x9; break;
891 case OMAP_DSS_COLOR_YUV2:
892 m = 0xa; break;
893 case OMAP_DSS_COLOR_UYVY:
894 m = 0xb; break;
895 case OMAP_DSS_COLOR_ARGB32:
896 m = 0xc; break;
897 case OMAP_DSS_COLOR_RGBA32:
898 m = 0xd; break;
899 case OMAP_DSS_COLOR_RGBX32:
900 m = 0xe; break;
901 case OMAP_DSS_COLOR_XRGB16_1555:
902 m = 0xf; break;
903 default:
904 BUG(); break;
905 }
906 } else {
907 switch (color_mode) {
908 case OMAP_DSS_COLOR_CLUT1:
909 m = 0x0; break;
910 case OMAP_DSS_COLOR_CLUT2:
911 m = 0x1; break;
912 case OMAP_DSS_COLOR_CLUT4:
913 m = 0x2; break;
914 case OMAP_DSS_COLOR_CLUT8:
915 m = 0x3; break;
916 case OMAP_DSS_COLOR_RGB12U:
917 m = 0x4; break;
918 case OMAP_DSS_COLOR_ARGB16:
919 m = 0x5; break;
920 case OMAP_DSS_COLOR_RGB16:
921 m = 0x6; break;
922 case OMAP_DSS_COLOR_ARGB16_1555:
923 m = 0x7; break;
924 case OMAP_DSS_COLOR_RGB24U:
925 m = 0x8; break;
926 case OMAP_DSS_COLOR_RGB24P:
927 m = 0x9; break;
928 case OMAP_DSS_COLOR_YUV2:
929 m = 0xa; break;
930 case OMAP_DSS_COLOR_UYVY:
931 m = 0xb; break;
932 case OMAP_DSS_COLOR_ARGB32:
933 m = 0xc; break;
934 case OMAP_DSS_COLOR_RGBA32:
935 m = 0xd; break;
936 case OMAP_DSS_COLOR_RGBX32:
937 m = 0xe; break;
938 case OMAP_DSS_COLOR_XRGB16_1555:
939 m = 0xf; break;
940 default:
941 BUG(); break;
942 }
80c39712
TV		 943 }
944
9b372c2d 945 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 946}
947
948static void _dispc_set_channel_out(enum omap_plane plane,
949 enum omap_channel channel)
950{
951 int shift;
952 u32 val;
2a205f34 953 int chan = 0, chan2 = 0;
80c39712
TV		 954
955 switch (plane) {
956 case OMAP_DSS_GFX:
957 shift = 8;
958 break;
959 case OMAP_DSS_VIDEO1:
960 case OMAP_DSS_VIDEO2:
961 shift = 16;
962 break;
963 default:
964 BUG();
965 return;
966 }
967
9b372c2d 968 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 969 if (dss_has_feature(FEAT_MGR_LCD2)) {
970 switch (channel) {
971 case OMAP_DSS_CHANNEL_LCD:
972 chan = 0;
973 chan2 = 0;
974 break;
975 case OMAP_DSS_CHANNEL_DIGIT:
976 chan = 1;
977 chan2 = 0;
978 break;
979 case OMAP_DSS_CHANNEL_LCD2:
980 chan = 0;
981 chan2 = 1;
982 break;
983 default:
984 BUG();
985 }
986
987 val = FLD_MOD(val, chan, shift, shift);
988 val = FLD_MOD(val, chan2, 31, 30);
989 } else {
990 val = FLD_MOD(val, channel, shift, shift);
991 }
9b372c2d 992 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 993}
994
995void dispc_set_burst_size(enum omap_plane plane,
996 enum omap_burst_size burst_size)
997{
998 int shift;
999 u32 val;
1000
1001 enable_clocks(1);
1002
1003 switch (plane) {
1004 case OMAP_DSS_GFX:
1005 shift = 6;
1006 break;
1007 case OMAP_DSS_VIDEO1:
1008 case OMAP_DSS_VIDEO2:
1009 shift = 14;
1010 break;
1011 default:
1012 BUG();
1013 return;
1014 }
1015
9b372c2d 1016 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1017 val = FLD_MOD(val, burst_size, shift+1, shift);
9b372c2d 1018 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1019
1020 enable_clocks(0);
1021}
1022
d3862610
M		 1023void dispc_enable_gamma_table(bool enable)
1024{
1025 /*
1026 * This is partially implemented to support only disabling of
1027 * the gamma table.
1028 */
1029 if (enable) {
1030 DSSWARN("Gamma table enabling for TV not yet supported");
1031 return;
1032 }
1033
1034 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1035}
1036
3c07cae2
TV		 1037void dispc_enable_cpr(enum omap_channel channel, bool enable)
1038{
1039 u16 reg;
1040
1041 if (channel == OMAP_DSS_CHANNEL_LCD)
1042 reg = DISPC_CONFIG;
1043 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1044 reg = DISPC_CONFIG2;
1045 else
1046 return;
1047
1048 REG_FLD_MOD(reg, enable, 15, 15);
1049}
1050
1051void dispc_set_cpr_coef(enum omap_channel channel,
1052 struct omap_dss_cpr_coefs *coefs)
1053{
1054 u32 coef_r, coef_g, coef_b;
1055
1056 if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2)
1057 return;
1058
1059 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1060 FLD_VAL(coefs->rb, 9, 0);
1061 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1062 FLD_VAL(coefs->gb, 9, 0);
1063 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1064 FLD_VAL(coefs->bb, 9, 0);
1065
1066 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1067 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1068 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1069}
1070
80c39712
TV		 1071static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1072{
1073 u32 val;
1074
1075 BUG_ON(plane == OMAP_DSS_GFX);
1076
9b372c2d 1077 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1078 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1079 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1080}
1081
1082void dispc_enable_replication(enum omap_plane plane, bool enable)
1083{
1084 int bit;
1085
1086 if (plane == OMAP_DSS_GFX)
1087 bit = 5;
1088 else
1089 bit = 10;
1090
1091 enable_clocks(1);
9b372c2d 1092 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
80c39712
TV		 1093 enable_clocks(0);
1094}
1095
64ba4f74 1096void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1097{
1098 u32 val;
1099 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1100 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1101 enable_clocks(1);
702d1448 1102 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1103 enable_clocks(0);
1104}
1105
1106void dispc_set_digit_size(u16 width, u16 height)
1107{
1108 u32 val;
1109 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1110 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1111 enable_clocks(1);
702d1448 1112 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1113 enable_clocks(0);
1114}
1115
1116static void dispc_read_plane_fifo_sizes(void)
1117{
80c39712
TV		 1118 u32 size;
1119 int plane;
a0acb557 1120 u8 start, end;
80c39712
TV		 1121
1122 enable_clocks(1);
1123
a0acb557 1124 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1125
a0acb557 1126 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
9b372c2d
AT		 1127 size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
1128 start, end);
80c39712
TV		 1129 dispc.fifo_size[plane] = size;
1130 }
1131
1132 enable_clocks(0);
1133}
1134
1135u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1136{
1137 return dispc.fifo_size[plane];
1138}
1139
1140void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1141{
a0acb557
AT		 1142 u8 hi_start, hi_end, lo_start, lo_end;
1143
9b372c2d
AT		 1144 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1145 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1146
80c39712
TV		 1147 enable_clocks(1);
1148
1149 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1150 plane,
9b372c2d
AT		 1151 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1152 lo_start, lo_end),
1153 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1154 hi_start, hi_end),
80c39712
TV		 1155 low, high);
1156
9b372c2d 1157 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1158 FLD_VAL(high, hi_start, hi_end) |
1159 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1160
1161 enable_clocks(0);
1162}
1163
1164void dispc_enable_fifomerge(bool enable)
1165{
1166 enable_clocks(1);
1167
1168 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1169 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1170
1171 enable_clocks(0);
1172}
1173
0d66cbb5
AJ		 1174static void _dispc_set_fir(enum omap_plane plane,
1175 int hinc, int vinc,
1176 enum omap_color_component color_comp)
80c39712
TV		 1177{
1178 u32 val;
80c39712 1179
0d66cbb5
AJ		 1180 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1181 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1182
0d66cbb5
AJ		 1183 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1184 &hinc_start, &hinc_end);
1185 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1186 &vinc_start, &vinc_end);
1187 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1188 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1189
0d66cbb5
AJ		 1190 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1191 } else {
1192 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1193 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1194 }
80c39712
TV		 1195}
1196
1197static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1198{
1199 u32 val;
87a7484b 1200 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1201
87a7484b
AT		 1202 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1203 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1204
1205 val = FLD_VAL(vaccu, vert_start, vert_end) |
1206 FLD_VAL(haccu, hor_start, hor_end);
1207
9b372c2d 1208 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1209}
1210
1211static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1212{
1213 u32 val;
87a7484b 1214 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1215
87a7484b
AT		 1216 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1217 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1218
1219 val = FLD_VAL(vaccu, vert_start, vert_end) |
1220 FLD_VAL(haccu, hor_start, hor_end);
1221
9b372c2d 1222 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1223}
1224
ab5ca071
AJ		 1225static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
1226{
1227 u32 val;
1228
1229 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1230 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1231}
1232
1233static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
1234{
1235 u32 val;
1236
1237 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1238 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1239}
80c39712 1240
0d66cbb5 1241static void _dispc_set_scale_param(enum omap_plane plane,
80c39712
TV		 1242 u16 orig_width, u16 orig_height,
1243 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1244 bool five_taps, u8 rotation,
1245 enum omap_color_component color_comp)
80c39712 1246{
0d66cbb5 1247 int fir_hinc, fir_vinc;
80c39712 1248 int hscaleup, vscaleup;
80c39712
TV		 1249
1250 hscaleup = orig_width <= out_width;
1251 vscaleup = orig_height <= out_height;
1252
0d66cbb5 1253 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
80c39712 1254
ed14a3ce
AJ		 1255 fir_hinc = 1024 * orig_width / out_width;
1256 fir_vinc = 1024 * orig_height / out_height;
80c39712 1257
0d66cbb5
AJ		 1258 _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1259}
1260
1261static void _dispc_set_scaling_common(enum omap_plane plane,
1262 u16 orig_width, u16 orig_height,
1263 u16 out_width, u16 out_height,
1264 bool ilace, bool five_taps,
1265 bool fieldmode, enum omap_color_mode color_mode,
1266 u8 rotation)
1267{
1268 int accu0 = 0;
1269 int accu1 = 0;
1270 u32 l;
80c39712 1271
0d66cbb5
AJ		 1272 _dispc_set_scale_param(plane, orig_width, orig_height,
1273 out_width, out_height, five_taps,
1274 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1275 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1276
87a7484b
AT		 1277 /* RESIZEENABLE and VERTICALTAPS */
1278 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1279 l |= (orig_width != out_width) ? (1 << 5) : 0;
1280 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1281 l |= five_taps ? (1 << 21) : 0;
80c39712 1282
87a7484b
AT		 1283 /* VRESIZECONF and HRESIZECONF */
1284 if (dss_has_feature(FEAT_RESIZECONF)) {
1285 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1286 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1287 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1288 }
80c39712 1289
87a7484b
AT		 1290 /* LINEBUFFERSPLIT */
1291 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1292 l &= ~(0x1 << 22);
1293 l |= five_taps ? (1 << 22) : 0;
1294 }
80c39712 1295
9b372c2d 1296 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1297
1298 /*
1299 * field 0 = even field = bottom field
1300 * field 1 = odd field = top field
1301 */
1302 if (ilace && !fieldmode) {
1303 accu1 = 0;
0d66cbb5 1304 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1305 if (accu0 >= 1024/2) {
1306 accu1 = 1024/2;
1307 accu0 -= accu1;
1308 }
1309 }
1310
1311 _dispc_set_vid_accu0(plane, 0, accu0);
1312 _dispc_set_vid_accu1(plane, 0, accu1);
1313}
1314
0d66cbb5
AJ		 1315static void _dispc_set_scaling_uv(enum omap_plane plane,
1316 u16 orig_width, u16 orig_height,
1317 u16 out_width, u16 out_height,
1318 bool ilace, bool five_taps,
1319 bool fieldmode, enum omap_color_mode color_mode,
1320 u8 rotation)
1321{
1322 int scale_x = out_width != orig_width;
1323 int scale_y = out_height != orig_height;
1324
1325 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1326 return;
1327 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1328 color_mode != OMAP_DSS_COLOR_UYVY &&
1329 color_mode != OMAP_DSS_COLOR_NV12)) {
1330 /* reset chroma resampling for RGB formats */
1331 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1332 return;
1333 }
1334 switch (color_mode) {
1335 case OMAP_DSS_COLOR_NV12:
1336 /* UV is subsampled by 2 vertically*/
1337 orig_height >>= 1;
1338 /* UV is subsampled by 2 horz.*/
1339 orig_width >>= 1;
1340 break;
1341 case OMAP_DSS_COLOR_YUV2:
1342 case OMAP_DSS_COLOR_UYVY:
1343 /*For YUV422 with 90/270 rotation,
1344 *we don't upsample chroma
1345 */
1346 if (rotation == OMAP_DSS_ROT_0 ||
1347 rotation == OMAP_DSS_ROT_180)
1348 /* UV is subsampled by 2 hrz*/
1349 orig_width >>= 1;
1350 /* must use FIR for YUV422 if rotated */
1351 if (rotation != OMAP_DSS_ROT_0)
1352 scale_x = scale_y = true;
1353 break;
1354 default:
1355 BUG();
1356 }
1357
1358 if (out_width != orig_width)
1359 scale_x = true;
1360 if (out_height != orig_height)
1361 scale_y = true;
1362
1363 _dispc_set_scale_param(plane, orig_width, orig_height,
1364 out_width, out_height, five_taps,
1365 rotation, DISPC_COLOR_COMPONENT_UV);
1366
1367 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1368 (scale_x || scale_y) ? 1 : 0, 8, 8);
1369 /* set H scaling */
1370 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1371 /* set V scaling */
1372 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1373
1374 _dispc_set_vid_accu2_0(plane, 0x80, 0);
1375 _dispc_set_vid_accu2_1(plane, 0x80, 0);
1376}
1377
1378static void _dispc_set_scaling(enum omap_plane plane,
1379 u16 orig_width, u16 orig_height,
1380 u16 out_width, u16 out_height,
1381 bool ilace, bool five_taps,
1382 bool fieldmode, enum omap_color_mode color_mode,
1383 u8 rotation)
1384{
1385 BUG_ON(plane == OMAP_DSS_GFX);
1386
1387 _dispc_set_scaling_common(plane,
1388 orig_width, orig_height,
1389 out_width, out_height,
1390 ilace, five_taps,
1391 fieldmode, color_mode,
1392 rotation);
1393
1394 _dispc_set_scaling_uv(plane,
1395 orig_width, orig_height,
1396 out_width, out_height,
1397 ilace, five_taps,
1398 fieldmode, color_mode,
1399 rotation);
1400}
1401
80c39712
TV		 1402static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1403 bool mirroring, enum omap_color_mode color_mode)
1404{
87a7484b
AT		 1405 bool row_repeat = false;
1406 int vidrot = 0;
1407
80c39712
TV		 1408 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1409 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1410
1411 if (mirroring) {
1412 switch (rotation) {
1413 case OMAP_DSS_ROT_0:
1414 vidrot = 2;
1415 break;
1416 case OMAP_DSS_ROT_90:
1417 vidrot = 1;
1418 break;
1419 case OMAP_DSS_ROT_180:
1420 vidrot = 0;
1421 break;
1422 case OMAP_DSS_ROT_270:
1423 vidrot = 3;
1424 break;
1425 }
1426 } else {
1427 switch (rotation) {
1428 case OMAP_DSS_ROT_0:
1429 vidrot = 0;
1430 break;
1431 case OMAP_DSS_ROT_90:
1432 vidrot = 1;
1433 break;
1434 case OMAP_DSS_ROT_180:
1435 vidrot = 2;
1436 break;
1437 case OMAP_DSS_ROT_270:
1438 vidrot = 3;
1439 break;
1440 }
1441 }
1442
80c39712 1443 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1444 row_repeat = true;
80c39712 1445 else
87a7484b 1446 row_repeat = false;
80c39712 1447 }
87a7484b 1448
9b372c2d 1449 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1450 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1451 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1452 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1453}
1454
1455static int color_mode_to_bpp(enum omap_color_mode color_mode)
1456{
1457 switch (color_mode) {
1458 case OMAP_DSS_COLOR_CLUT1:
1459 return 1;
1460 case OMAP_DSS_COLOR_CLUT2:
1461 return 2;
1462 case OMAP_DSS_COLOR_CLUT4:
1463 return 4;
1464 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1465 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1466 return 8;
1467 case OMAP_DSS_COLOR_RGB12U:
1468 case OMAP_DSS_COLOR_RGB16:
1469 case OMAP_DSS_COLOR_ARGB16:
1470 case OMAP_DSS_COLOR_YUV2:
1471 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1472 case OMAP_DSS_COLOR_RGBA16:
1473 case OMAP_DSS_COLOR_RGBX16:
1474 case OMAP_DSS_COLOR_ARGB16_1555:
1475 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1476 return 16;
1477 case OMAP_DSS_COLOR_RGB24P:
1478 return 24;
1479 case OMAP_DSS_COLOR_RGB24U:
1480 case OMAP_DSS_COLOR_ARGB32:
1481 case OMAP_DSS_COLOR_RGBA32:
1482 case OMAP_DSS_COLOR_RGBX32:
1483 return 32;
1484 default:
1485 BUG();
1486 }
1487}
1488
1489static s32 pixinc(int pixels, u8 ps)
1490{
1491 if (pixels == 1)
1492 return 1;
1493 else if (pixels > 1)
1494 return 1 + (pixels - 1) * ps;
1495 else if (pixels < 0)
1496 return 1 - (-pixels + 1) * ps;
1497 else
1498 BUG();
1499}
1500
1501static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1502 u16 screen_width,
1503 u16 width, u16 height,
1504 enum omap_color_mode color_mode, bool fieldmode,
1505 unsigned int field_offset,
1506 unsigned *offset0, unsigned *offset1,
1507 s32 *row_inc, s32 *pix_inc)
1508{
1509 u8 ps;
1510
1511 /* FIXME CLUT formats */
1512 switch (color_mode) {
1513 case OMAP_DSS_COLOR_CLUT1:
1514 case OMAP_DSS_COLOR_CLUT2:
1515 case OMAP_DSS_COLOR_CLUT4:
1516 case OMAP_DSS_COLOR_CLUT8:
1517 BUG();
1518 return;
1519 case OMAP_DSS_COLOR_YUV2:
1520 case OMAP_DSS_COLOR_UYVY:
1521 ps = 4;
1522 break;
1523 default:
1524 ps = color_mode_to_bpp(color_mode) / 8;
1525 break;
1526 }
1527
1528 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1529 width, height);
1530
1531 /*
1532 * field 0 = even field = bottom field
1533 * field 1 = odd field = top field
1534 */
1535 switch (rotation + mirror * 4) {
1536 case OMAP_DSS_ROT_0:
1537 case OMAP_DSS_ROT_180:
1538 /*
1539 * If the pixel format is YUV or UYVY divide the width
1540 * of the image by 2 for 0 and 180 degree rotation.
1541 */
1542 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1543 color_mode == OMAP_DSS_COLOR_UYVY)
1544 width = width >> 1;
1545 case OMAP_DSS_ROT_90:
1546 case OMAP_DSS_ROT_270:
1547 *offset1 = 0;
1548 if (field_offset)
1549 *offset0 = field_offset * screen_width * ps;
1550 else
1551 *offset0 = 0;
1552
1553 *row_inc = pixinc(1 + (screen_width - width) +
1554 (fieldmode ? screen_width : 0),
1555 ps);
1556 *pix_inc = pixinc(1, ps);
1557 break;
1558
1559 case OMAP_DSS_ROT_0 + 4:
1560 case OMAP_DSS_ROT_180 + 4:
1561 /* If the pixel format is YUV or UYVY divide the width
1562 * of the image by 2 for 0 degree and 180 degree
1563 */
1564 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1565 color_mode == OMAP_DSS_COLOR_UYVY)
1566 width = width >> 1;
1567 case OMAP_DSS_ROT_90 + 4:
1568 case OMAP_DSS_ROT_270 + 4:
1569 *offset1 = 0;
1570 if (field_offset)
1571 *offset0 = field_offset * screen_width * ps;
1572 else
1573 *offset0 = 0;
1574 *row_inc = pixinc(1 - (screen_width + width) -
1575 (fieldmode ? screen_width : 0),
1576 ps);
1577 *pix_inc = pixinc(1, ps);
1578 break;
1579
1580 default:
1581 BUG();
1582 }
1583}
1584
1585static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1586 u16 screen_width,
1587 u16 width, u16 height,
1588 enum omap_color_mode color_mode, bool fieldmode,
1589 unsigned int field_offset,
1590 unsigned *offset0, unsigned *offset1,
1591 s32 *row_inc, s32 *pix_inc)
1592{
1593 u8 ps;
1594 u16 fbw, fbh;
1595
1596 /* FIXME CLUT formats */
1597 switch (color_mode) {
1598 case OMAP_DSS_COLOR_CLUT1:
1599 case OMAP_DSS_COLOR_CLUT2:
1600 case OMAP_DSS_COLOR_CLUT4:
1601 case OMAP_DSS_COLOR_CLUT8:
1602 BUG();
1603 return;
1604 default:
1605 ps = color_mode_to_bpp(color_mode) / 8;
1606 break;
1607 }
1608
1609 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1610 width, height);
1611
1612 /* width & height are overlay sizes, convert to fb sizes */
1613
1614 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1615 fbw = width;
1616 fbh = height;
1617 } else {
1618 fbw = height;
1619 fbh = width;
1620 }
1621
1622 /*
1623 * field 0 = even field = bottom field
1624 * field 1 = odd field = top field
1625 */
1626 switch (rotation + mirror * 4) {
1627 case OMAP_DSS_ROT_0:
1628 *offset1 = 0;
1629 if (field_offset)
1630 *offset0 = *offset1 + field_offset * screen_width * ps;
1631 else
1632 *offset0 = *offset1;
1633 *row_inc = pixinc(1 + (screen_width - fbw) +
1634 (fieldmode ? screen_width : 0),
1635 ps);
1636 *pix_inc = pixinc(1, ps);
1637 break;
1638 case OMAP_DSS_ROT_90:
1639 *offset1 = screen_width * (fbh - 1) * ps;
1640 if (field_offset)
1641 *offset0 = *offset1 + field_offset * ps;
1642 else
1643 *offset0 = *offset1;
1644 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1645 (fieldmode ? 1 : 0), ps);
1646 *pix_inc = pixinc(-screen_width, ps);
1647 break;
1648 case OMAP_DSS_ROT_180:
1649 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1650 if (field_offset)
1651 *offset0 = *offset1 - field_offset * screen_width * ps;
1652 else
1653 *offset0 = *offset1;
1654 *row_inc = pixinc(-1 -
1655 (screen_width - fbw) -
1656 (fieldmode ? screen_width : 0),
1657 ps);
1658 *pix_inc = pixinc(-1, ps);
1659 break;
1660 case OMAP_DSS_ROT_270:
1661 *offset1 = (fbw - 1) * ps;
1662 if (field_offset)
1663 *offset0 = *offset1 - field_offset * ps;
1664 else
1665 *offset0 = *offset1;
1666 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1667 (fieldmode ? 1 : 0), ps);
1668 *pix_inc = pixinc(screen_width, ps);
1669 break;
1670
1671 /* mirroring */
1672 case OMAP_DSS_ROT_0 + 4:
1673 *offset1 = (fbw - 1) * ps;
1674 if (field_offset)
1675 *offset0 = *offset1 + field_offset * screen_width * ps;
1676 else
1677 *offset0 = *offset1;
1678 *row_inc = pixinc(screen_width * 2 - 1 +
1679 (fieldmode ? screen_width : 0),
1680 ps);
1681 *pix_inc = pixinc(-1, ps);
1682 break;
1683
1684 case OMAP_DSS_ROT_90 + 4:
1685 *offset1 = 0;
1686 if (field_offset)
1687 *offset0 = *offset1 + field_offset * ps;
1688 else
1689 *offset0 = *offset1;
1690 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1691 (fieldmode ? 1 : 0),
1692 ps);
1693 *pix_inc = pixinc(screen_width, ps);
1694 break;
1695
1696 case OMAP_DSS_ROT_180 + 4:
1697 *offset1 = screen_width * (fbh - 1) * ps;
1698 if (field_offset)
1699 *offset0 = *offset1 - field_offset * screen_width * ps;
1700 else
1701 *offset0 = *offset1;
1702 *row_inc = pixinc(1 - screen_width * 2 -
1703 (fieldmode ? screen_width : 0),
1704 ps);
1705 *pix_inc = pixinc(1, ps);
1706 break;
1707
1708 case OMAP_DSS_ROT_270 + 4:
1709 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1710 if (field_offset)
1711 *offset0 = *offset1 - field_offset * ps;
1712 else
1713 *offset0 = *offset1;
1714 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1715 (fieldmode ? 1 : 0),
1716 ps);
1717 *pix_inc = pixinc(-screen_width, ps);
1718 break;
1719
1720 default:
1721 BUG();
1722 }
1723}
1724
ff1b2cde
SS		 1725static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1726 u16 height, u16 out_width, u16 out_height,
1727 enum omap_color_mode color_mode)
80c39712
TV		 1728{
1729 u32 fclk = 0;
1730 /* FIXME venc pclk? */
ff1b2cde 1731 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1732
1733 if (height > out_height) {
1734 /* FIXME get real display PPL */
1735 unsigned int ppl = 800;
1736
1737 tmp = pclk * height * out_width;
1738 do_div(tmp, 2 * out_height * ppl);
1739 fclk = tmp;
1740
2d9c5597
VS		 1741 if (height > 2 * out_height) {
1742 if (ppl == out_width)
1743 return 0;
1744
80c39712
TV		 1745 tmp = pclk * (height - 2 * out_height) * out_width;
1746 do_div(tmp, 2 * out_height * (ppl - out_width));
1747 fclk = max(fclk, (u32) tmp);
1748 }
1749 }
1750
1751 if (width > out_width) {
1752 tmp = pclk * width;
1753 do_div(tmp, out_width);
1754 fclk = max(fclk, (u32) tmp);
1755
1756 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1757 fclk <<= 1;
1758 }
1759
1760 return fclk;
1761}
1762
ff1b2cde
SS		 1763static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1764 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1765{
1766 unsigned int hf, vf;
1767
1768 /*
1769 * FIXME how to determine the 'A' factor
1770 * for the no downscaling case ?
1771 */
1772
1773 if (width > 3 * out_width)
1774 hf = 4;
1775 else if (width > 2 * out_width)
1776 hf = 3;
1777 else if (width > out_width)
1778 hf = 2;
1779 else
1780 hf = 1;
1781
1782 if (height > out_height)
1783 vf = 2;
1784 else
1785 vf = 1;
1786
1787 /* FIXME venc pclk? */
ff1b2cde 1788 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1789}
1790
1791void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1792{
1793 enable_clocks(1);
1794 _dispc_set_channel_out(plane, channel_out);
1795 enable_clocks(0);
1796}
1797
1798static int _dispc_setup_plane(enum omap_plane plane,
1799 u32 paddr, u16 screen_width,
1800 u16 pos_x, u16 pos_y,
1801 u16 width, u16 height,
1802 u16 out_width, u16 out_height,
1803 enum omap_color_mode color_mode,
1804 bool ilace,
1805 enum omap_dss_rotation_type rotation_type,
1806 u8 rotation, int mirror,
18faa1b6 1807 u8 global_alpha, u8 pre_mult_alpha,
0d66cbb5 1808 enum omap_channel channel, u32 puv_addr)
80c39712
TV		 1809{
1810 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1811 bool five_taps = 0;
1812 bool fieldmode = 0;
1813 int cconv = 0;
1814 unsigned offset0, offset1;
1815 s32 row_inc;
1816 s32 pix_inc;
1817 u16 frame_height = height;
1818 unsigned int field_offset = 0;
1819
1820 if (paddr == 0)
1821 return -EINVAL;
1822
1823 if (ilace && height == out_height)
1824 fieldmode = 1;
1825
1826 if (ilace) {
1827 if (fieldmode)
1828 height /= 2;
1829 pos_y /= 2;
1830 out_height /= 2;
1831
1832 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1833 "out_height %d\n",
1834 height, pos_y, out_height);
1835 }
1836
8dad2ab6
AT		 1837 if (!dss_feat_color_mode_supported(plane, color_mode))
1838 return -EINVAL;
1839
80c39712
TV		 1840 if (plane == OMAP_DSS_GFX) {
1841 if (width != out_width || height != out_height)
1842 return -EINVAL;
80c39712
TV		 1843 } else {
1844 /* video plane */
1845
1846 unsigned long fclk = 0;
1847
1848 if (out_width < width / maxdownscale ||
1849 out_width > width * 8)
1850 return -EINVAL;
1851
1852 if (out_height < height / maxdownscale ||
1853 out_height > height * 8)
1854 return -EINVAL;
1855
8dad2ab6 1856 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
0d66cbb5
AJ		 1857 color_mode == OMAP_DSS_COLOR_UYVY ||
1858 color_mode == OMAP_DSS_COLOR_NV12)
80c39712 1859 cconv = 1;
80c39712
TV		 1860
1861 /* Must use 5-tap filter? */
1862 five_taps = height > out_height * 2;
1863
1864 if (!five_taps) {
18faa1b6
SS		 1865 fclk = calc_fclk(channel, width, height, out_width,
1866 out_height);
80c39712
TV		 1867
1868 /* Try 5-tap filter if 3-tap fclk is too high */
1869 if (cpu_is_omap34xx() && height > out_height &&
1870 fclk > dispc_fclk_rate())
1871 five_taps = true;
1872 }
1873
1874 if (width > (2048 >> five_taps)) {
1875 DSSERR("failed to set up scaling, fclk too low\n");
1876 return -EINVAL;
1877 }
1878
1879 if (five_taps)
18faa1b6
SS		 1880 fclk = calc_fclk_five_taps(channel, width, height,
1881 out_width, out_height, color_mode);
80c39712
TV		 1882
1883 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1884 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1885
2d9c5597 1886 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1887 DSSERR("failed to set up scaling, "
1888 "required fclk rate = %lu Hz, "
1889 "current fclk rate = %lu Hz\n",
1890 fclk, dispc_fclk_rate());
1891 return -EINVAL;
1892 }
1893 }
1894
1895 if (ilace && !fieldmode) {
1896 /*
1897 * when downscaling the bottom field may have to start several
1898 * source lines below the top field. Unfortunately ACCUI
1899 * registers will only hold the fractional part of the offset
1900 * so the integer part must be added to the base address of the
1901 * bottom field.
1902 */
1903 if (!height || height == out_height)
1904 field_offset = 0;
1905 else
1906 field_offset = height / out_height / 2;
1907 }
1908
1909 /* Fields are independent but interleaved in memory. */
1910 if (fieldmode)
1911 field_offset = 1;
1912
1913 if (rotation_type == OMAP_DSS_ROT_DMA)
1914 calc_dma_rotation_offset(rotation, mirror,
1915 screen_width, width, frame_height, color_mode,
1916 fieldmode, field_offset,
1917 &offset0, &offset1, &row_inc, &pix_inc);
1918 else
1919 calc_vrfb_rotation_offset(rotation, mirror,
1920 screen_width, width, frame_height, color_mode,
1921 fieldmode, field_offset,
1922 &offset0, &offset1, &row_inc, &pix_inc);
1923
1924 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1925 offset0, offset1, row_inc, pix_inc);
1926
1927 _dispc_set_color_mode(plane, color_mode);
1928
1929 _dispc_set_plane_ba0(plane, paddr + offset0);
1930 _dispc_set_plane_ba1(plane, paddr + offset1);
1931
0d66cbb5
AJ		 1932 if (OMAP_DSS_COLOR_NV12 == color_mode) {
1933 _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
1934 _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
1935 }
1936
1937
80c39712
TV		 1938 _dispc_set_row_inc(plane, row_inc);
1939 _dispc_set_pix_inc(plane, pix_inc);
1940
1941 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1942 out_width, out_height);
1943
1944 _dispc_set_plane_pos(plane, pos_x, pos_y);
1945
1946 _dispc_set_pic_size(plane, width, height);
1947
1948 if (plane != OMAP_DSS_GFX) {
1949 _dispc_set_scaling(plane, width, height,
1950 out_width, out_height,
0d66cbb5
AJ		 1951 ilace, five_taps, fieldmode,
1952 color_mode, rotation);
80c39712
TV		 1953 _dispc_set_vid_size(plane, out_width, out_height);
1954 _dispc_set_vid_color_conv(plane, cconv);
1955 }
1956
1957 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1958
fd28a390
R		 1959 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1960 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 1961
1962 return 0;
1963}
1964
1965static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1966{
9b372c2d 1967 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
80c39712
TV		 1968}
1969
1970static void dispc_disable_isr(void *data, u32 mask)
1971{
1972 struct completion *compl = data;
1973 complete(compl);
1974}
1975
2a205f34 1976static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1977{
2a205f34
SS		 1978 if (channel == OMAP_DSS_CHANNEL_LCD2)
1979 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1980 else
1981 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1982}
1983
2a205f34 1984static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1985{
1986 struct completion frame_done_completion;
1987 bool is_on;
1988 int r;
2a205f34 1989 u32 irq;
80c39712
TV		 1990
1991 enable_clocks(1);
1992
1993 /* When we disable LCD output, we need to wait until frame is done.
1994 * Otherwise the DSS is still working, and turning off the clocks
1995 * prevents DSS from going to OFF mode */
2a205f34
SS		 1996 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1997 REG_GET(DISPC_CONTROL2, 0, 0) :
1998 REG_GET(DISPC_CONTROL, 0, 0);
1999
2000 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2001 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2002
2003 if (!enable && is_on) {
2004 init_completion(&frame_done_completion);
2005
2006 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2007 &frame_done_completion, irq);
80c39712
TV		 2008
2009 if (r)
2010 DSSERR("failed to register FRAMEDONE isr\n");
2011 }
2012
2a205f34 2013 _enable_lcd_out(channel, enable);
80c39712
TV		 2014
2015 if (!enable && is_on) {
2016 if (!wait_for_completion_timeout(&frame_done_completion,
2017 msecs_to_jiffies(100)))
2018 DSSERR("timeout waiting for FRAME DONE\n");
2019
2020 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2021 &frame_done_completion, irq);
80c39712
TV		 2022
2023 if (r)
2024 DSSERR("failed to unregister FRAMEDONE isr\n");
2025 }
2026
2027 enable_clocks(0);
2028}
2029
2030static void _enable_digit_out(bool enable)
2031{
2032 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2033}
2034
a2faee84 2035static void dispc_enable_digit_out(bool enable)
80c39712
TV		 2036{
2037 struct completion frame_done_completion;
2038 int r;
2039
2040 enable_clocks(1);
2041
2042 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
2043 enable_clocks(0);
2044 return;
2045 }
2046
2047 if (enable) {
2048 unsigned long flags;
2049 /* When we enable digit output, we'll get an extra digit
2050 * sync lost interrupt, that we need to ignore */
2051 spin_lock_irqsave(&dispc.irq_lock, flags);
2052 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2053 _omap_dispc_set_irqs();
2054 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2055 }
2056
2057 /* When we disable digit output, we need to wait until fields are done.
2058 * Otherwise the DSS is still working, and turning off the clocks
2059 * prevents DSS from going to OFF mode. And when enabling, we need to
2060 * wait for the extra sync losts */
2061 init_completion(&frame_done_completion);
2062
2063 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2064 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
2065 if (r)
2066 DSSERR("failed to register EVSYNC isr\n");
2067
2068 _enable_digit_out(enable);
2069
2070 /* XXX I understand from TRM that we should only wait for the
2071 * current field to complete. But it seems we have to wait
2072 * for both fields */
2073 if (!wait_for_completion_timeout(&frame_done_completion,
2074 msecs_to_jiffies(100)))
2075 DSSERR("timeout waiting for EVSYNC\n");
2076
2077 if (!wait_for_completion_timeout(&frame_done_completion,
2078 msecs_to_jiffies(100)))
2079 DSSERR("timeout waiting for EVSYNC\n");
2080
2081 r = omap_dispc_unregister_isr(dispc_disable_isr,
2082 &frame_done_completion,
2083 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
2084 if (r)
2085 DSSERR("failed to unregister EVSYNC isr\n");
2086
2087 if (enable) {
2088 unsigned long flags;
2089 spin_lock_irqsave(&dispc.irq_lock, flags);
2090 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 2091 if (dss_has_feature(FEAT_MGR_LCD2))
2092 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 2093 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2094 _omap_dispc_set_irqs();
2095 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2096 }
2097
2098 enable_clocks(0);
2099}
2100
a2faee84
TV		 2101bool dispc_is_channel_enabled(enum omap_channel channel)
2102{
2103 if (channel == OMAP_DSS_CHANNEL_LCD)
2104 return !!REG_GET(DISPC_CONTROL, 0, 0);
2105 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2106 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2107 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2108 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2109 else
2110 BUG();
2111}
2112
2113void dispc_enable_channel(enum omap_channel channel, bool enable)
2114{
2a205f34
SS		 2115 if (channel == OMAP_DSS_CHANNEL_LCD ||
2116 channel == OMAP_DSS_CHANNEL_LCD2)
2117 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 2118 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2119 dispc_enable_digit_out(enable);
2120 else
2121 BUG();
2122}
2123
80c39712
TV		 2124void dispc_lcd_enable_signal_polarity(bool act_high)
2125{
6ced40bf
AT		 2126 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2127 return;
2128
80c39712
TV		 2129 enable_clocks(1);
2130 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2131 enable_clocks(0);
2132}
2133
2134void dispc_lcd_enable_signal(bool enable)
2135{
6ced40bf
AT		 2136 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2137 return;
2138
80c39712
TV		 2139 enable_clocks(1);
2140 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2141 enable_clocks(0);
2142}
2143
2144void dispc_pck_free_enable(bool enable)
2145{
6ced40bf
AT		 2146 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2147 return;
2148
80c39712
TV		 2149 enable_clocks(1);
2150 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2151 enable_clocks(0);
2152}
2153
64ba4f74 2154void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712
TV		 2155{
2156 enable_clocks(1);
2a205f34
SS		 2157 if (channel == OMAP_DSS_CHANNEL_LCD2)
2158 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2159 else
2160 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2161 enable_clocks(0);
2162}
2163
2164
64ba4f74
SS		 2165void dispc_set_lcd_display_type(enum omap_channel channel,
2166 enum omap_lcd_display_type type)
80c39712
TV		 2167{
2168 int mode;
2169
2170 switch (type) {
2171 case OMAP_DSS_LCD_DISPLAY_STN:
2172 mode = 0;
2173 break;
2174
2175 case OMAP_DSS_LCD_DISPLAY_TFT:
2176 mode = 1;
2177 break;
2178
2179 default:
2180 BUG();
2181 return;
2182 }
2183
2184 enable_clocks(1);
2a205f34
SS		 2185 if (channel == OMAP_DSS_CHANNEL_LCD2)
2186 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2187 else
2188 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2189 enable_clocks(0);
2190}
2191
2192void dispc_set_loadmode(enum omap_dss_load_mode mode)
2193{
2194 enable_clocks(1);
2195 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2196 enable_clocks(0);
2197}
2198
2199
2200void dispc_set_default_color(enum omap_channel channel, u32 color)
2201{
80c39712 2202 enable_clocks(1);
8613b000 2203 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2204 enable_clocks(0);
2205}
2206
2207u32 dispc_get_default_color(enum omap_channel channel)
2208{
80c39712
TV		 2209 u32 l;
2210
2211 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2212 channel != OMAP_DSS_CHANNEL_LCD &&
2213 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712
TV		 2214
2215 enable_clocks(1);
8613b000 2216 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2217 enable_clocks(0);
2218
2219 return l;
2220}
2221
2222void dispc_set_trans_key(enum omap_channel ch,
2223 enum omap_dss_trans_key_type type,
2224 u32 trans_key)
2225{
80c39712
TV		 2226 enable_clocks(1);
2227 if (ch == OMAP_DSS_CHANNEL_LCD)
2228 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2229 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2230 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2231 else /* OMAP_DSS_CHANNEL_LCD2 */
2232 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2233
8613b000 2234 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2235 enable_clocks(0);
2236}
2237
2238void dispc_get_trans_key(enum omap_channel ch,
2239 enum omap_dss_trans_key_type *type,
2240 u32 *trans_key)
2241{
80c39712
TV		 2242 enable_clocks(1);
2243 if (type) {
2244 if (ch == OMAP_DSS_CHANNEL_LCD)
2245 *type = REG_GET(DISPC_CONFIG, 11, 11);
2246 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2247 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2248 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2249 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2250 else
2251 BUG();
2252 }
2253
2254 if (trans_key)
8613b000 2255 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2256 enable_clocks(0);
2257}
2258
2259void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2260{
2261 enable_clocks(1);
2262 if (ch == OMAP_DSS_CHANNEL_LCD)
2263 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2264 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2265 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2266 else /* OMAP_DSS_CHANNEL_LCD2 */
2267 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2268 enable_clocks(0);
2269}
2270void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2271{
a0acb557 2272 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2273 return;
2274
2275 enable_clocks(1);
2276 if (ch == OMAP_DSS_CHANNEL_LCD)
2277 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2278 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2279 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2280 else /* OMAP_DSS_CHANNEL_LCD2 */
2281 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2282 enable_clocks(0);
2283}
2284bool dispc_alpha_blending_enabled(enum omap_channel ch)
2285{
2286 bool enabled;
2287
a0acb557 2288 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2289 return false;
2290
2291 enable_clocks(1);
2292 if (ch == OMAP_DSS_CHANNEL_LCD)
2293 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2294 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2295 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2296 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2297 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2298 else
2299 BUG();
2300 enable_clocks(0);
2301
2302 return enabled;
80c39712
TV		 2303}
2304
2305
2306bool dispc_trans_key_enabled(enum omap_channel ch)
2307{
2308 bool enabled;
2309
2310 enable_clocks(1);
2311 if (ch == OMAP_DSS_CHANNEL_LCD)
2312 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2313 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2314 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2315 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2316 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2317 else
2318 BUG();
2319 enable_clocks(0);
2320
2321 return enabled;
2322}
2323
2324
64ba4f74 2325void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2326{
2327 int code;
2328
2329 switch (data_lines) {
2330 case 12:
2331 code = 0;
2332 break;
2333 case 16:
2334 code = 1;
2335 break;
2336 case 18:
2337 code = 2;
2338 break;
2339 case 24:
2340 code = 3;
2341 break;
2342 default:
2343 BUG();
2344 return;
2345 }
2346
2347 enable_clocks(1);
2a205f34
SS		 2348 if (channel == OMAP_DSS_CHANNEL_LCD2)
2349 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2350 else
2351 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2352 enable_clocks(0);
2353}
2354
64ba4f74
SS		 2355void dispc_set_parallel_interface_mode(enum omap_channel channel,
2356 enum omap_parallel_interface_mode mode)
80c39712
TV		 2357{
2358 u32 l;
2359 int stallmode;
2360 int gpout0 = 1;
2361 int gpout1;
2362
2363 switch (mode) {
2364 case OMAP_DSS_PARALLELMODE_BYPASS:
2365 stallmode = 0;
2366 gpout1 = 1;
2367 break;
2368
2369 case OMAP_DSS_PARALLELMODE_RFBI:
2370 stallmode = 1;
2371 gpout1 = 0;
2372 break;
2373
2374 case OMAP_DSS_PARALLELMODE_DSI:
2375 stallmode = 1;
2376 gpout1 = 1;
2377 break;
2378
2379 default:
2380 BUG();
2381 return;
2382 }
2383
2384 enable_clocks(1);
2385
2a205f34
SS		 2386 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2387 l = dispc_read_reg(DISPC_CONTROL2);
2388 l = FLD_MOD(l, stallmode, 11, 11);
2389 dispc_write_reg(DISPC_CONTROL2, l);
2390 } else {
2391 l = dispc_read_reg(DISPC_CONTROL);
2392 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2393 l = FLD_MOD(l, gpout0, 15, 15);
2394 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2395 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2396 }
80c39712
TV		 2397
2398 enable_clocks(0);
2399}
2400
2401static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2402 int vsw, int vfp, int vbp)
2403{
2404 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2405 if (hsw < 1 || hsw > 64 ||
2406 hfp < 1 || hfp > 256 ||
2407 hbp < 1 || hbp > 256 ||
2408 vsw < 1 || vsw > 64 ||
2409 vfp < 0 || vfp > 255 ||
2410 vbp < 0 || vbp > 255)
2411 return false;
2412 } else {
2413 if (hsw < 1 || hsw > 256 ||
2414 hfp < 1 || hfp > 4096 ||
2415 hbp < 1 || hbp > 4096 ||
2416 vsw < 1 || vsw > 256 ||
2417 vfp < 0 || vfp > 4095 ||
2418 vbp < 0 || vbp > 4095)
2419 return false;
2420 }
2421
2422 return true;
2423}
2424
2425bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2426{
2427 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2428 timings->hbp, timings->vsw,
2429 timings->vfp, timings->vbp);
2430}
2431
64ba4f74
SS		 2432static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2433 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2434{
2435 u32 timing_h, timing_v;
2436
2437 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2438 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2439 FLD_VAL(hbp-1, 27, 20);
2440
2441 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2442 FLD_VAL(vbp, 27, 20);
2443 } else {
2444 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2445 FLD_VAL(hbp-1, 31, 20);
2446
2447 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2448 FLD_VAL(vbp, 31, 20);
2449 }
2450
2451 enable_clocks(1);
64ba4f74
SS		 2452 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2453 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2454 enable_clocks(0);
2455}
2456
2457/* change name to mode? */
64ba4f74
SS		 2458void dispc_set_lcd_timings(enum omap_channel channel,
2459 struct omap_video_timings *timings)
80c39712
TV		 2460{
2461 unsigned xtot, ytot;
2462 unsigned long ht, vt;
2463
2464 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2465 timings->hbp, timings->vsw,
2466 timings->vfp, timings->vbp))
2467 BUG();
2468
64ba4f74
SS		 2469 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2470 timings->hbp, timings->vsw, timings->vfp,
2471 timings->vbp);
80c39712 2472
64ba4f74 2473 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2474
2475 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2476 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2477
2478 ht = (timings->pixel_clock * 1000) / xtot;
2479 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2480
2a205f34
SS		 2481 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2482 timings->y_res);
80c39712
TV		 2483 DSSDBG("pck %u\n", timings->pixel_clock);
2484 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2485 timings->hsw, timings->hfp, timings->hbp,
2486 timings->vsw, timings->vfp, timings->vbp);
2487
2488 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2489}
2490
ff1b2cde
SS		 2491static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2492 u16 pck_div)
80c39712
TV		 2493{
2494 BUG_ON(lck_div < 1);
2495 BUG_ON(pck_div < 2);
2496
2497 enable_clocks(1);
ce7fa5eb 2498 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712
TV		 2499 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2500 enable_clocks(0);
2501}
2502
2a205f34
SS		 2503static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2504 int *pck_div)
80c39712
TV		 2505{
2506 u32 l;
ce7fa5eb 2507 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2508 *lck_div = FLD_GET(l, 23, 16);
2509 *pck_div = FLD_GET(l, 7, 0);
2510}
2511
2512unsigned long dispc_fclk_rate(void)
2513{
a72b64b9 2514 struct platform_device *dsidev;
80c39712
TV		 2515 unsigned long r = 0;
2516
66534e8e 2517 switch (dss_get_dispc_clk_source()) {
89a35e51 2518 case OMAP_DSS_CLK_SRC_FCK:
6af9cd14 2519 r = dss_clk_get_rate(DSS_CLK_FCK);
66534e8e 2520 break;
89a35e51 2521 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2522 dsidev = dsi_get_dsidev_from_id(0);
2523 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2524 break;
5a8b572d
AT		 2525 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2526 dsidev = dsi_get_dsidev_from_id(1);
2527 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2528 break;
66534e8e
TA		 2529 default:
2530 BUG();
2531 }
2532
80c39712
TV		 2533 return r;
2534}
2535
ff1b2cde 2536unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712 2537{
a72b64b9 2538 struct platform_device *dsidev;
80c39712
TV		 2539 int lcd;
2540 unsigned long r;
2541 u32 l;
2542
ce7fa5eb 2543 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2544
2545 lcd = FLD_GET(l, 23, 16);
2546
ea75159e 2547 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2548 case OMAP_DSS_CLK_SRC_FCK:
ea75159e
TA		 2549 r = dss_clk_get_rate(DSS_CLK_FCK);
2550 break;
89a35e51 2551 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2552 dsidev = dsi_get_dsidev_from_id(0);
2553 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2554 break;
5a8b572d
AT		 2555 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2556 dsidev = dsi_get_dsidev_from_id(1);
2557 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2558 break;
ea75159e
TA		 2559 default:
2560 BUG();
2561 }
80c39712
TV		 2562
2563 return r / lcd;
2564}
2565
ff1b2cde 2566unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712 2567{
ea75159e 2568 int pcd;
80c39712
TV		 2569 unsigned long r;
2570 u32 l;
2571
ce7fa5eb 2572 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2573
80c39712
TV		 2574 pcd = FLD_GET(l, 7, 0);
2575
ea75159e 2576 r = dispc_lclk_rate(channel);
80c39712 2577
ea75159e 2578 return r / pcd;
80c39712
TV		 2579}
2580
2581void dispc_dump_clocks(struct seq_file *s)
2582{
2583 int lcd, pcd;
0cf35df3 2584 u32 l;
89a35e51
AT		 2585 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2586 enum omap_dss_clk_source lcd_clk_src;
80c39712
TV		 2587
2588 enable_clocks(1);
2589
80c39712
TV		 2590 seq_printf(s, "- DISPC -\n");
2591
067a57e4
AT		 2592 seq_printf(s, "dispc fclk source = %s (%s)\n",
2593 dss_get_generic_clk_source_name(dispc_clk_src),
2594 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2595
2596 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2597
0cf35df3
MR		 2598 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2599 seq_printf(s, "- DISPC-CORE-CLK -\n");
2600 l = dispc_read_reg(DISPC_DIVISOR);
2601 lcd = FLD_GET(l, 23, 16);
2602
2603 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2604 (dispc_fclk_rate()/lcd), lcd);
2605 }
2a205f34
SS		 2606 seq_printf(s, "- LCD1 -\n");
2607
ea75159e
TA		 2608 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2609
2610 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2611 dss_get_generic_clk_source_name(lcd_clk_src),
2612 dss_feat_get_clk_source_name(lcd_clk_src));
2613
2a205f34
SS		 2614 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2615
ff1b2cde
SS		 2616 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2617 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2618 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2619 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2620 if (dss_has_feature(FEAT_MGR_LCD2)) {
2621 seq_printf(s, "- LCD2 -\n");
2622
ea75159e
TA		 2623 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2624
2625 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2626 dss_get_generic_clk_source_name(lcd_clk_src),
2627 dss_feat_get_clk_source_name(lcd_clk_src));
2628
2a205f34 2629 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2630
2a205f34
SS		 2631 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2632 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2633 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2634 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2635 }
80c39712
TV		 2636 enable_clocks(0);
2637}
2638
dfc0fd8d
TV		 2639#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2640void dispc_dump_irqs(struct seq_file *s)
2641{
2642 unsigned long flags;
2643 struct dispc_irq_stats stats;
2644
2645 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2646
2647 stats = dispc.irq_stats;
2648 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2649 dispc.irq_stats.last_reset = jiffies;
2650
2651 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2652
2653 seq_printf(s, "period %u ms\n",
2654 jiffies_to_msecs(jiffies - stats.last_reset));
2655
2656 seq_printf(s, "irqs %d\n", stats.irq_count);
2657#define PIS(x) \
2658 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2659
2660 PIS(FRAMEDONE);
2661 PIS(VSYNC);
2662 PIS(EVSYNC_EVEN);
2663 PIS(EVSYNC_ODD);
2664 PIS(ACBIAS_COUNT_STAT);
2665 PIS(PROG_LINE_NUM);
2666 PIS(GFX_FIFO_UNDERFLOW);
2667 PIS(GFX_END_WIN);
2668 PIS(PAL_GAMMA_MASK);
2669 PIS(OCP_ERR);
2670 PIS(VID1_FIFO_UNDERFLOW);
2671 PIS(VID1_END_WIN);
2672 PIS(VID2_FIFO_UNDERFLOW);
2673 PIS(VID2_END_WIN);
2674 PIS(SYNC_LOST);
2675 PIS(SYNC_LOST_DIGIT);
2676 PIS(WAKEUP);
2a205f34
SS		 2677 if (dss_has_feature(FEAT_MGR_LCD2)) {
2678 PIS(FRAMEDONE2);
2679 PIS(VSYNC2);
2680 PIS(ACBIAS_COUNT_STAT2);
2681 PIS(SYNC_LOST2);
2682 }
dfc0fd8d
TV		 2683#undef PIS
2684}
dfc0fd8d
TV		 2685#endif
2686
80c39712
TV		 2687void dispc_dump_regs(struct seq_file *s)
2688{
9b372c2d 2689#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2690
6af9cd14 2691 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2692
2693 DUMPREG(DISPC_REVISION);
2694 DUMPREG(DISPC_SYSCONFIG);
2695 DUMPREG(DISPC_SYSSTATUS);
2696 DUMPREG(DISPC_IRQSTATUS);
2697 DUMPREG(DISPC_IRQENABLE);
2698 DUMPREG(DISPC_CONTROL);
2699 DUMPREG(DISPC_CONFIG);
2700 DUMPREG(DISPC_CAPABLE);
702d1448
AT		 2701 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
2702 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
2703 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
2704 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712
TV		 2705 DUMPREG(DISPC_LINE_STATUS);
2706 DUMPREG(DISPC_LINE_NUMBER);
702d1448
AT		 2707 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
2708 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
2709 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
2710 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
332e9d70
TV		 2711 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2712 DUMPREG(DISPC_GLOBAL_ALPHA);
702d1448
AT		 2713 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
2714 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34
SS		 2715 if (dss_has_feature(FEAT_MGR_LCD2)) {
2716 DUMPREG(DISPC_CONTROL2);
2717 DUMPREG(DISPC_CONFIG2);
702d1448
AT		 2718 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
2719 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
2720 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
2721 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
2722 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
2723 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2724 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
2a205f34 2725 }
80c39712 2726
9b372c2d
AT		 2727 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
2728 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
2729 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
2730 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
2731 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
2732 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
2733 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
2734 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
2735 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
2736 DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
2737 DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
80c39712 2738
702d1448
AT		 2739 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
2740 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
2741 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 2742
332e9d70
TV		 2743 if (dss_has_feature(FEAT_CPR)) {
2744 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
2745 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
2746 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
2747 }
2a205f34 2748 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 2749 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
2750 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
2751 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 2752
332e9d70
TV		 2753 if (dss_has_feature(FEAT_CPR)) {
2754 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2755 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
2756 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
2757 }
2a205f34 2758 }
80c39712 2759
332e9d70
TV		 2760 if (dss_has_feature(FEAT_PRELOAD))
2761 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
9b372c2d
AT		 2762
2763 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
2764 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
2765 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
2766 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
2767 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
2768 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
2769 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
2770 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
2771 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
2772 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
2773 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
2774 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
2775 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
2776
2777 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
2778 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
2779 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
2780 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
2781 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
2782 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
2783 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
2784 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
2785 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
2786 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
2787 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
2788 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
2789 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
2790
2791 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
2792 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
2793 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
2794 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
2795 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
2796 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
2797 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
2798 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
2799 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
2800 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
2801 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
2802 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
2803 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
2804 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
2805 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
2806 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
2807 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
2808 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
2809 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
2810 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
2811 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
332e9d70
TV		 2812 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2813 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
2814 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
2815 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
2816 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
2817 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
2818 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
2819 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
2820 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
2821 }
9b372c2d 2822
ab5ca071
AJ		 2823 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2824 DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
2825 DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
2826 DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
2827 DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
2828 DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
2829
2830 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
2831 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
2832 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
2833 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
2834 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
2835 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
2836 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
2837 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));
2838
2839 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
2840 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
2841 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
2842 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
2843 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
2844 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
2845 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
2846 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));
2847
2848 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
2849 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
2850 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
2851 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
2852 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
2853 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
2854 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
2855 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
2856 }
2857 if (dss_has_feature(FEAT_ATTR2))
2858 DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
2859
2860
9b372c2d
AT		 2861 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
2862 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
2863 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
2864 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
2865 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
2866 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
2867 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
2868 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
2869 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
2870 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
2871 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
2872 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
2873 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
2874 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
2875 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
2876 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
2877 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
2878 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
2879 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
2880 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
2881 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
332e9d70
TV		 2882
2883 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2884 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
2885 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
2886 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
2887 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
2888 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
2889 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
2890 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
2891 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
2892 }
9b372c2d 2893
ab5ca071
AJ		 2894 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2895 DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
2896 DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
2897 DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
2898 DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
2899 DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
2900
2901 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
2902 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
2903 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
2904 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
2905 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
2906 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
2907 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
2908 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));
2909
2910 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
2911 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
2912 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
2913 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
2914 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
2915 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
2916 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
2917 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));
2918
2919 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
2920 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
2921 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
2922 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
2923 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
2924 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
2925 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
2926 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
2927 }
2928 if (dss_has_feature(FEAT_ATTR2))
2929 DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
2930
332e9d70
TV		 2931 if (dss_has_feature(FEAT_PRELOAD)) {
2932 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
2933 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
2934 }
80c39712 2935
6af9cd14 2936 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2937#undef DUMPREG
2938}
2939
ff1b2cde
SS		 2940static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2941 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2942{
2943 u32 l = 0;
2944
2945 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2946 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2947
2948 l |= FLD_VAL(onoff, 17, 17);
2949 l |= FLD_VAL(rf, 16, 16);
2950 l |= FLD_VAL(ieo, 15, 15);
2951 l |= FLD_VAL(ipc, 14, 14);
2952 l |= FLD_VAL(ihs, 13, 13);
2953 l |= FLD_VAL(ivs, 12, 12);
2954 l |= FLD_VAL(acbi, 11, 8);
2955 l |= FLD_VAL(acb, 7, 0);
2956
2957 enable_clocks(1);
ff1b2cde 2958 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2959 enable_clocks(0);
2960}
2961
ff1b2cde
SS		 2962void dispc_set_pol_freq(enum omap_channel channel,
2963 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2964{
ff1b2cde 2965 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2966 (config & OMAP_DSS_LCD_RF) != 0,
2967 (config & OMAP_DSS_LCD_IEO) != 0,
2968 (config & OMAP_DSS_LCD_IPC) != 0,
2969 (config & OMAP_DSS_LCD_IHS) != 0,
2970 (config & OMAP_DSS_LCD_IVS) != 0,
2971 acbi, acb);
2972}
2973
2974/* with fck as input clock rate, find dispc dividers that produce req_pck */
2975void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2976 struct dispc_clock_info *cinfo)
2977{
2978 u16 pcd_min = is_tft ? 2 : 3;
2979 unsigned long best_pck;
2980 u16 best_ld, cur_ld;
2981 u16 best_pd, cur_pd;
2982
2983 best_pck = 0;
2984 best_ld = 0;
2985 best_pd = 0;
2986
2987 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2988 unsigned long lck = fck / cur_ld;
2989
2990 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2991 unsigned long pck = lck / cur_pd;
2992 long old_delta = abs(best_pck - req_pck);
2993 long new_delta = abs(pck - req_pck);
2994
2995 if (best_pck == 0 || new_delta < old_delta) {
2996 best_pck = pck;
2997 best_ld = cur_ld;
2998 best_pd = cur_pd;
2999
3000 if (pck == req_pck)
3001 goto found;
3002 }
3003
3004 if (pck < req_pck)
3005 break;
3006 }
3007
3008 if (lck / pcd_min < req_pck)
3009 break;
3010 }
3011
3012found:
3013 cinfo->lck_div = best_ld;
3014 cinfo->pck_div = best_pd;
3015 cinfo->lck = fck / cinfo->lck_div;
3016 cinfo->pck = cinfo->lck / cinfo->pck_div;
3017}
3018
3019/* calculate clock rates using dividers in cinfo */
3020int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3021 struct dispc_clock_info *cinfo)
3022{
3023 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3024 return -EINVAL;
3025 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
3026 return -EINVAL;
3027
3028 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3029 cinfo->pck = cinfo->lck / cinfo->pck_div;
3030
3031 return 0;
3032}
3033
ff1b2cde
SS		 3034int dispc_set_clock_div(enum omap_channel channel,
3035 struct dispc_clock_info *cinfo)
80c39712
TV		 3036{
3037 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3038 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3039
ff1b2cde 3040 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3041
3042 return 0;
3043}
3044
ff1b2cde
SS		 3045int dispc_get_clock_div(enum omap_channel channel,
3046 struct dispc_clock_info *cinfo)
80c39712
TV		 3047{
3048 unsigned long fck;
3049
3050 fck = dispc_fclk_rate();
3051
ce7fa5eb
MR		 3052 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3053 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3054
3055 cinfo->lck = fck / cinfo->lck_div;
3056 cinfo->pck = cinfo->lck / cinfo->pck_div;
3057
3058 return 0;
3059}
3060
3061/* dispc.irq_lock has to be locked by the caller */
3062static void _omap_dispc_set_irqs(void)
3063{
3064 u32 mask;
3065 u32 old_mask;
3066 int i;
3067 struct omap_dispc_isr_data *isr_data;
3068
3069 mask = dispc.irq_error_mask;
3070
3071 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3072 isr_data = &dispc.registered_isr[i];
3073
3074 if (isr_data->isr == NULL)
3075 continue;
3076
3077 mask |= isr_data->mask;
3078 }
3079
3080 enable_clocks(1);
3081
3082 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3083 /* clear the irqstatus for newly enabled irqs */
3084 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3085
3086 dispc_write_reg(DISPC_IRQENABLE, mask);
3087
3088 enable_clocks(0);
3089}
3090
3091int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3092{
3093 int i;
3094 int ret;
3095 unsigned long flags;
3096 struct omap_dispc_isr_data *isr_data;
3097
3098 if (isr == NULL)
3099 return -EINVAL;
3100
3101 spin_lock_irqsave(&dispc.irq_lock, flags);
3102
3103 /* check for duplicate entry */
3104 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3105 isr_data = &dispc.registered_isr[i];
3106 if (isr_data->isr == isr && isr_data->arg == arg &&
3107 isr_data->mask == mask) {
3108 ret = -EINVAL;
3109 goto err;
3110 }
3111 }
3112
3113 isr_data = NULL;
3114 ret = -EBUSY;
3115
3116 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3117 isr_data = &dispc.registered_isr[i];
3118
3119 if (isr_data->isr != NULL)
3120 continue;
3121
3122 isr_data->isr = isr;
3123 isr_data->arg = arg;
3124 isr_data->mask = mask;
3125 ret = 0;
3126
3127 break;
3128 }
3129
b9cb0984
TV		 3130 if (ret)
3131 goto err;
3132
80c39712
TV		 3133 _omap_dispc_set_irqs();
3134
3135 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3136
3137 return 0;
3138err:
3139 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3140
3141 return ret;
3142}
3143EXPORT_SYMBOL(omap_dispc_register_isr);
3144
3145int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3146{
3147 int i;
3148 unsigned long flags;
3149 int ret = -EINVAL;
3150 struct omap_dispc_isr_data *isr_data;
3151
3152 spin_lock_irqsave(&dispc.irq_lock, flags);
3153
3154 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3155 isr_data = &dispc.registered_isr[i];
3156 if (isr_data->isr != isr || isr_data->arg != arg ||
3157 isr_data->mask != mask)
3158 continue;
3159
3160 /* found the correct isr */
3161
3162 isr_data->isr = NULL;
3163 isr_data->arg = NULL;
3164 isr_data->mask = 0;
3165
3166 ret = 0;
3167 break;
3168 }
3169
3170 if (ret == 0)
3171 _omap_dispc_set_irqs();
3172
3173 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3174
3175 return ret;
3176}
3177EXPORT_SYMBOL(omap_dispc_unregister_isr);
3178
3179#ifdef DEBUG
3180static void print_irq_status(u32 status)
3181{
3182 if ((status & dispc.irq_error_mask) == 0)
3183 return;
3184
3185 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3186
3187#define PIS(x) \
3188 if (status & DISPC_IRQ_##x) \
3189 printk(#x " ");
3190 PIS(GFX_FIFO_UNDERFLOW);
3191 PIS(OCP_ERR);
3192 PIS(VID1_FIFO_UNDERFLOW);
3193 PIS(VID2_FIFO_UNDERFLOW);
3194 PIS(SYNC_LOST);
3195 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3196 if (dss_has_feature(FEAT_MGR_LCD2))
3197 PIS(SYNC_LOST2);
80c39712
TV		 3198#undef PIS
3199
3200 printk("\n");
3201}
3202#endif
3203
3204/* Called from dss.c. Note that we don't touch clocks here,
3205 * but we presume they are on because we got an IRQ. However,
3206 * an irq handler may turn the clocks off, so we may not have
3207 * clock later in the function. */
affe360d 3208static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3209{
3210 int i;
affe360d 3211 u32 irqstatus, irqenable;
80c39712
TV		 3212 u32 handledirqs = 0;
3213 u32 unhandled_errors;
3214 struct omap_dispc_isr_data *isr_data;
3215 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3216
3217 spin_lock(&dispc.irq_lock);
3218
3219 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3220 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3221
3222 /* IRQ is not for us */
3223 if (!(irqstatus & irqenable)) {
3224 spin_unlock(&dispc.irq_lock);
3225 return IRQ_NONE;
3226 }
80c39712 3227
dfc0fd8d
TV		 3228#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3229 spin_lock(&dispc.irq_stats_lock);
3230 dispc.irq_stats.irq_count++;
3231 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3232 spin_unlock(&dispc.irq_stats_lock);
3233#endif
3234
80c39712
TV		 3235#ifdef DEBUG
3236 if (dss_debug)
3237 print_irq_status(irqstatus);
3238#endif
3239 /* Ack the interrupt. Do it here before clocks are possibly turned
3240 * off */
3241 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3242 /* flush posted write */
3243 dispc_read_reg(DISPC_IRQSTATUS);
3244
3245 /* make a copy and unlock, so that isrs can unregister
3246 * themselves */
3247 memcpy(registered_isr, dispc.registered_isr,
3248 sizeof(registered_isr));
3249
3250 spin_unlock(&dispc.irq_lock);
3251
3252 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3253 isr_data = &registered_isr[i];
3254
3255 if (!isr_data->isr)
3256 continue;
3257
3258 if (isr_data->mask & irqstatus) {
3259 isr_data->isr(isr_data->arg, irqstatus);
3260 handledirqs |= isr_data->mask;
3261 }
3262 }
3263
3264 spin_lock(&dispc.irq_lock);
3265
3266 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3267
3268 if (unhandled_errors) {
3269 dispc.error_irqs |= unhandled_errors;
3270
3271 dispc.irq_error_mask &= ~unhandled_errors;
3272 _omap_dispc_set_irqs();
3273
3274 schedule_work(&dispc.error_work);
3275 }
3276
3277 spin_unlock(&dispc.irq_lock);
affe360d 3278
3279 return IRQ_HANDLED;
80c39712
TV		 3280}
3281
3282static void dispc_error_worker(struct work_struct *work)
3283{
3284 int i;
3285 u32 errors;
3286 unsigned long flags;
3287
3288 spin_lock_irqsave(&dispc.irq_lock, flags);
3289 errors = dispc.error_irqs;
3290 dispc.error_irqs = 0;
3291 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3292
3293 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
3294 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
3295 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3296 struct omap_overlay *ovl;
3297 ovl = omap_dss_get_overlay(i);
3298
3299 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3300 continue;
3301
3302 if (ovl->id == 0) {
3303 dispc_enable_plane(ovl->id, 0);
3304 dispc_go(ovl->manager->id);
3305 mdelay(50);
3306 break;
3307 }
3308 }
3309 }
3310
3311 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3312 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3313 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3314 struct omap_overlay *ovl;
3315 ovl = omap_dss_get_overlay(i);
3316
3317 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3318 continue;
3319
3320 if (ovl->id == 1) {
3321 dispc_enable_plane(ovl->id, 0);
3322 dispc_go(ovl->manager->id);
3323 mdelay(50);
3324 break;
3325 }
3326 }
3327 }
3328
3329 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3330 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3331 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3332 struct omap_overlay *ovl;
3333 ovl = omap_dss_get_overlay(i);
3334
3335 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3336 continue;
3337
3338 if (ovl->id == 2) {
3339 dispc_enable_plane(ovl->id, 0);
3340 dispc_go(ovl->manager->id);
3341 mdelay(50);
3342 break;
3343 }
3344 }
3345 }
3346
3347 if (errors & DISPC_IRQ_SYNC_LOST) {
3348 struct omap_overlay_manager *manager = NULL;
3349 bool enable = false;
3350
3351 DSSERR("SYNC_LOST, disabling LCD\n");
3352
3353 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3354 struct omap_overlay_manager *mgr;
3355 mgr = omap_dss_get_overlay_manager(i);
3356
3357 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3358 manager = mgr;
3359 enable = mgr->device->state ==
3360 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3361 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3362 break;
3363 }
3364 }
3365
3366 if (manager) {
37ac60e4 3367 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3368 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3369 struct omap_overlay *ovl;
3370 ovl = omap_dss_get_overlay(i);
3371
3372 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3373 continue;
3374
3375 if (ovl->id != 0 && ovl->manager == manager)
3376 dispc_enable_plane(ovl->id, 0);
3377 }
3378
3379 dispc_go(manager->id);
3380 mdelay(50);
3381 if (enable)
37ac60e4 3382 dssdev->driver->enable(dssdev);
80c39712
TV		 3383 }
3384 }
3385
3386 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3387 struct omap_overlay_manager *manager = NULL;
3388 bool enable = false;
3389
3390 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3391
3392 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3393 struct omap_overlay_manager *mgr;
3394 mgr = omap_dss_get_overlay_manager(i);
3395
3396 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3397 manager = mgr;
3398 enable = mgr->device->state ==
3399 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3400 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3401 break;
3402 }
3403 }
3404
3405 if (manager) {
37ac60e4 3406 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3407 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3408 struct omap_overlay *ovl;
3409 ovl = omap_dss_get_overlay(i);
3410
3411 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3412 continue;
3413
3414 if (ovl->id != 0 && ovl->manager == manager)
3415 dispc_enable_plane(ovl->id, 0);
3416 }
3417
3418 dispc_go(manager->id);
3419 mdelay(50);
3420 if (enable)
37ac60e4 3421 dssdev->driver->enable(dssdev);
80c39712
TV		 3422 }
3423 }
3424
2a205f34
SS		 3425 if (errors & DISPC_IRQ_SYNC_LOST2) {
3426 struct omap_overlay_manager *manager = NULL;
3427 bool enable = false;
3428
3429 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3430
3431 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3432 struct omap_overlay_manager *mgr;
3433 mgr = omap_dss_get_overlay_manager(i);
3434
3435 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3436 manager = mgr;
3437 enable = mgr->device->state ==
3438 OMAP_DSS_DISPLAY_ACTIVE;
3439 mgr->device->driver->disable(mgr->device);
3440 break;
3441 }
3442 }
3443
3444 if (manager) {
3445 struct omap_dss_device *dssdev = manager->device;
3446 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3447 struct omap_overlay *ovl;
3448 ovl = omap_dss_get_overlay(i);
3449
3450 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3451 continue;
3452
3453 if (ovl->id != 0 && ovl->manager == manager)
3454 dispc_enable_plane(ovl->id, 0);
3455 }
3456
3457 dispc_go(manager->id);
3458 mdelay(50);
3459 if (enable)
3460 dssdev->driver->enable(dssdev);
3461 }
3462 }
3463
80c39712
TV		 3464 if (errors & DISPC_IRQ_OCP_ERR) {
3465 DSSERR("OCP_ERR\n");
3466 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3467 struct omap_overlay_manager *mgr;
3468 mgr = omap_dss_get_overlay_manager(i);
3469
3470 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3471 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3472 }
3473 }
3474
3475 spin_lock_irqsave(&dispc.irq_lock, flags);
3476 dispc.irq_error_mask |= errors;
3477 _omap_dispc_set_irqs();
3478 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3479}
3480
3481int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3482{
3483 void dispc_irq_wait_handler(void *data, u32 mask)
3484 {
3485 complete((struct completion *)data);
3486 }
3487
3488 int r;
3489 DECLARE_COMPLETION_ONSTACK(completion);
3490
3491 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3492 irqmask);
3493
3494 if (r)
3495 return r;
3496
3497 timeout = wait_for_completion_timeout(&completion, timeout);
3498
3499 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3500
3501 if (timeout == 0)
3502 return -ETIMEDOUT;
3503
3504 if (timeout == -ERESTARTSYS)
3505 return -ERESTARTSYS;
3506
3507 return 0;
3508}
3509
3510int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3511 unsigned long timeout)
3512{
3513 void dispc_irq_wait_handler(void *data, u32 mask)
3514 {
3515 complete((struct completion *)data);
3516 }
3517
3518 int r;
3519 DECLARE_COMPLETION_ONSTACK(completion);
3520
3521 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3522 irqmask);
3523
3524 if (r)
3525 return r;
3526
3527 timeout = wait_for_completion_interruptible_timeout(&completion,
3528 timeout);
3529
3530 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3531
3532 if (timeout == 0)
3533 return -ETIMEDOUT;
3534
3535 if (timeout == -ERESTARTSYS)
3536 return -ERESTARTSYS;
3537
3538 return 0;
3539}
3540
3541#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3542void dispc_fake_vsync_irq(void)
3543{
3544 u32 irqstatus = DISPC_IRQ_VSYNC;
3545 int i;
3546
ab83b14c 3547 WARN_ON(!in_interrupt());
80c39712
TV		 3548
3549 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3550 struct omap_dispc_isr_data *isr_data;
3551 isr_data = &dispc.registered_isr[i];
3552
3553 if (!isr_data->isr)
3554 continue;
3555
3556 if (isr_data->mask & irqstatus)
3557 isr_data->isr(isr_data->arg, irqstatus);
3558 }
80c39712
TV		 3559}
3560#endif
3561
3562static void _omap_dispc_initialize_irq(void)
3563{
3564 unsigned long flags;
3565
3566 spin_lock_irqsave(&dispc.irq_lock, flags);
3567
3568 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3569
3570 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3571 if (dss_has_feature(FEAT_MGR_LCD2))
3572 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3573
3574 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3575 * so clear it */
3576 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3577
3578 _omap_dispc_set_irqs();
3579
3580 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3581}
3582
3583void dispc_enable_sidle(void)
3584{
3585 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3586}
3587
3588void dispc_disable_sidle(void)
3589{
3590 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3591}
3592
3593static void _omap_dispc_initial_config(void)
3594{
3595 u32 l;
3596
3597 l = dispc_read_reg(DISPC_SYSCONFIG);
3598 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3599 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3600 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3601 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3602 dispc_write_reg(DISPC_SYSCONFIG, l);
3603
0cf35df3
MR		 3604 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3605 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3606 l = dispc_read_reg(DISPC_DIVISOR);
3607 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3608 l = FLD_MOD(l, 1, 0, 0);
3609 l = FLD_MOD(l, 1, 23, 16);
3610 dispc_write_reg(DISPC_DIVISOR, l);
3611 }
3612
80c39712 3613 /* FUNCGATED */
6ced40bf
AT		 3614 if (dss_has_feature(FEAT_FUNCGATED))
3615 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3616
3617 /* L3 firewall setting: enable access to OCM RAM */
3618 /* XXX this should be somewhere in plat-omap */
3619 if (cpu_is_omap24xx())
3620 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3621
3622 _dispc_setup_color_conv_coef();
3623
3624 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3625
3626 dispc_read_plane_fifo_sizes();
3627}
3628
80c39712
TV		 3629int dispc_enable_plane(enum omap_plane plane, bool enable)
3630{
3631 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3632
3633 enable_clocks(1);
3634 _dispc_enable_plane(plane, enable);
3635 enable_clocks(0);
3636
3637 return 0;
3638}
3639
3640int dispc_setup_plane(enum omap_plane plane,
3641 u32 paddr, u16 screen_width,
3642 u16 pos_x, u16 pos_y,
3643 u16 width, u16 height,
3644 u16 out_width, u16 out_height,
3645 enum omap_color_mode color_mode,
3646 bool ilace,
3647 enum omap_dss_rotation_type rotation_type,
fd28a390 3648 u8 rotation, bool mirror, u8 global_alpha,
0d66cbb5
AJ		 3649 u8 pre_mult_alpha, enum omap_channel channel,
3650 u32 puv_addr)
80c39712
TV		 3651{
3652 int r = 0;
3653
0d66cbb5 3654 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d, %d, %dx%d -> "
18faa1b6 3655 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
80c39712
TV		 3656 plane, paddr, screen_width, pos_x, pos_y,
3657 width, height,
3658 out_width, out_height,
3659 ilace, color_mode,
18faa1b6 3660 rotation, mirror, channel);
80c39712
TV		 3661
3662 enable_clocks(1);
3663
3664 r = _dispc_setup_plane(plane,
3665 paddr, screen_width,
3666 pos_x, pos_y,
3667 width, height,
3668 out_width, out_height,
3669 color_mode, ilace,
3670 rotation_type,
3671 rotation, mirror,
fd28a390 3672 global_alpha,
0d66cbb5
AJ		 3673 pre_mult_alpha,
3674 channel, puv_addr);
80c39712
TV		 3675
3676 enable_clocks(0);
3677
3678 return r;
3679}
060b6d9c
SG		 3680
3681/* DISPC HW IP initialisation */
3682static int omap_dispchw_probe(struct platform_device *pdev)
3683{
3684 u32 rev;
affe360d 3685 int r = 0;
ea9da36a
SG		 3686 struct resource *dispc_mem;
3687
060b6d9c
SG		 3688 dispc.pdev = pdev;
3689
3690 spin_lock_init(&dispc.irq_lock);
3691
3692#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3693 spin_lock_init(&dispc.irq_stats_lock);
3694 dispc.irq_stats.last_reset = jiffies;
3695#endif
3696
3697 INIT_WORK(&dispc.error_work, dispc_error_worker);
3698
ea9da36a
SG		 3699 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3700 if (!dispc_mem) {
3701 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3702 r = -EINVAL;
3703 goto fail0;
ea9da36a
SG		 3704 }
3705 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3706 if (!dispc.base) {
3707 DSSERR("can't ioremap DISPC\n");
affe360d 3708 r = -ENOMEM;
3709 goto fail0;
3710 }
3711 dispc.irq = platform_get_irq(dispc.pdev, 0);
3712 if (dispc.irq < 0) {
3713 DSSERR("platform_get_irq failed\n");
3714 r = -ENODEV;
3715 goto fail1;
3716 }
3717
3718 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3719 "OMAP DISPC", dispc.pdev);
3720 if (r < 0) {
3721 DSSERR("request_irq failed\n");
3722 goto fail1;
060b6d9c
SG		 3723 }
3724
3725 enable_clocks(1);
3726
3727 _omap_dispc_initial_config();
3728
3729 _omap_dispc_initialize_irq();
3730
3731 dispc_save_context();
3732
3733 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3734 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3735 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3736
3737 enable_clocks(0);
3738
3739 return 0;
affe360d 3740fail1:
3741 iounmap(dispc.base);
3742fail0:
3743 return r;
060b6d9c
SG		 3744}
3745
3746static int omap_dispchw_remove(struct platform_device *pdev)
3747{
affe360d 3748 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3749 iounmap(dispc.base);
3750 return 0;
3751}
3752
3753static struct platform_driver omap_dispchw_driver = {
3754 .probe = omap_dispchw_probe,
3755 .remove = omap_dispchw_remove,
3756 .driver = {
3757 .name = "omapdss_dispc",
3758 .owner = THIS_MODULE,
3759 },
3760};
3761
3762int dispc_init_platform_driver(void)
3763{
3764 return platform_driver_register(&omap_dispchw_driver);
3765}
3766
3767void dispc_uninit_platform_driver(void)
3768{
3769 return platform_driver_unregister(&omap_dispchw_driver);
3770}
Linux kernel - Deliverables
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