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video/omap: fix build dependencies
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
80c39712
TV		 38
39#include <plat/sram.h>
40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
66be8f6c
GI		 66struct dispc_h_coef {
67 s8 hc4;
68 s8 hc3;
69 u8 hc2;
70 s8 hc1;
71 s8 hc0;
72};
73
74struct dispc_v_coef {
75 s8 vc22;
76 s8 vc2;
77 u8 vc1;
78 s8 vc0;
79 s8 vc00;
80};
81
5ed8cf5b
TV		 82enum omap_burst_size {
83 BURST_SIZE_X2 = 0,
84 BURST_SIZE_X4 = 1,
85 BURST_SIZE_X8 = 2,
86};
87
80c39712
TV		 88#define REG_GET(idx, start, end) \
89 FLD_GET(dispc_read_reg(idx), start, end)
90
91#define REG_FLD_MOD(idx, val, start, end) \
92 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
93
dfc0fd8d
TV		 94struct dispc_irq_stats {
95 unsigned long last_reset;
96 unsigned irq_count;
97 unsigned irqs[32];
98};
99
80c39712 100static struct {
060b6d9c 101 struct platform_device *pdev;
80c39712 102 void __iomem *base;
4fbafaf3
TV		 103
104 int ctx_loss_cnt;
105
affe360d 106 int irq;
4fbafaf3 107 struct clk *dss_clk;
80c39712 108
e13a138b 109 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 110
111 spinlock_t irq_lock;
112 u32 irq_error_mask;
113 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
114 u32 error_irqs;
115 struct work_struct error_work;
116
49ea86f3 117 bool ctx_valid;
80c39712 118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 119
120#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
121 spinlock_t irq_stats_lock;
122 struct dispc_irq_stats irq_stats;
123#endif
80c39712
TV		 124} dispc;
125
0d66cbb5
AJ		 126enum omap_color_component {
127 /* used for all color formats for OMAP3 and earlier
128 * and for RGB and Y color component on OMAP4
129 */
130 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
131 /* used for UV component for
132 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
133 * color formats on OMAP4
134 */
135 DISPC_COLOR_COMPONENT_UV = 1 << 1,
136};
137
80c39712
TV		 138static void _omap_dispc_set_irqs(void);
139
55978cc2 140static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 141{
55978cc2 142 __raw_writel(val, dispc.base + idx);
80c39712
TV		 143}
144
55978cc2 145static inline u32 dispc_read_reg(const u16 idx)
80c39712 146{
55978cc2 147 return __raw_readl(dispc.base + idx);
80c39712
TV		 148}
149
49ea86f3
TV		 150static int dispc_get_ctx_loss_count(void)
151{
152 struct device *dev = &dispc.pdev->dev;
153 struct omap_display_platform_data *pdata = dev->platform_data;
154 struct omap_dss_board_info *board_data = pdata->board_data;
155 int cnt;
156
157 if (!board_data->get_context_loss_count)
158 return -ENOENT;
159
160 cnt = board_data->get_context_loss_count(dev);
161
162 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
163
164 return cnt;
165}
166
80c39712 167#define SR(reg) \
55978cc2 168 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 169#define RR(reg) \
55978cc2 170 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 171
4fbafaf3 172static void dispc_save_context(void)
80c39712 173{
c6104b8e 174 int i, j;
80c39712 175
4fbafaf3
TV		 176 DSSDBG("dispc_save_context\n");
177
80c39712
TV		 178 SR(IRQENABLE);
179 SR(CONTROL);
180 SR(CONFIG);
80c39712 181 SR(LINE_NUMBER);
332e9d70
TV		 182 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
183 SR(GLOBAL_ALPHA);
2a205f34
SS		 184 if (dss_has_feature(FEAT_MGR_LCD2)) {
185 SR(CONTROL2);
2a205f34
SS		 186 SR(CONFIG2);
187 }
80c39712 188
c6104b8e
AT		 189 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
190 SR(DEFAULT_COLOR(i));
191 SR(TRANS_COLOR(i));
192 SR(SIZE_MGR(i));
193 if (i == OMAP_DSS_CHANNEL_DIGIT)
194 continue;
195 SR(TIMING_H(i));
196 SR(TIMING_V(i));
197 SR(POL_FREQ(i));
198 SR(DIVISORo(i));
199
200 SR(DATA_CYCLE1(i));
201 SR(DATA_CYCLE2(i));
202 SR(DATA_CYCLE3(i));
203
332e9d70 204 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 205 SR(CPR_COEF_R(i));
206 SR(CPR_COEF_G(i));
207 SR(CPR_COEF_B(i));
332e9d70 208 }
2a205f34 209 }
80c39712 210
c6104b8e
AT		 211 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
212 SR(OVL_BA0(i));
213 SR(OVL_BA1(i));
214 SR(OVL_POSITION(i));
215 SR(OVL_SIZE(i));
216 SR(OVL_ATTRIBUTES(i));
217 SR(OVL_FIFO_THRESHOLD(i));
218 SR(OVL_ROW_INC(i));
219 SR(OVL_PIXEL_INC(i));
220 if (dss_has_feature(FEAT_PRELOAD))
221 SR(OVL_PRELOAD(i));
222 if (i == OMAP_DSS_GFX) {
223 SR(OVL_WINDOW_SKIP(i));
224 SR(OVL_TABLE_BA(i));
225 continue;
226 }
227 SR(OVL_FIR(i));
228 SR(OVL_PICTURE_SIZE(i));
229 SR(OVL_ACCU0(i));
230 SR(OVL_ACCU1(i));
9b372c2d 231
c6104b8e
AT		 232 for (j = 0; j < 8; j++)
233 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 234
c6104b8e
AT		 235 for (j = 0; j < 8; j++)
236 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 237
c6104b8e
AT		 238 for (j = 0; j < 5; j++)
239 SR(OVL_CONV_COEF(i, j));
ab5ca071 240
c6104b8e
AT		 241 if (dss_has_feature(FEAT_FIR_COEF_V)) {
242 for (j = 0; j < 8; j++)
243 SR(OVL_FIR_COEF_V(i, j));
244 }
9b372c2d 245
c6104b8e
AT		 246 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
247 SR(OVL_BA0_UV(i));
248 SR(OVL_BA1_UV(i));
249 SR(OVL_FIR2(i));
250 SR(OVL_ACCU2_0(i));
251 SR(OVL_ACCU2_1(i));
ab5ca071 252
c6104b8e
AT		 253 for (j = 0; j < 8; j++)
254 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 255
c6104b8e
AT		 256 for (j = 0; j < 8; j++)
257 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 258
c6104b8e
AT		 259 for (j = 0; j < 8; j++)
260 SR(OVL_FIR_COEF_V2(i, j));
261 }
262 if (dss_has_feature(FEAT_ATTR2))
263 SR(OVL_ATTRIBUTES2(i));
ab5ca071 264 }
0cf35df3
MR		 265
266 if (dss_has_feature(FEAT_CORE_CLK_DIV))
267 SR(DIVISOR);
49ea86f3
TV		 268
269 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
270 dispc.ctx_valid = true;
271
272 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 273}
274
4fbafaf3 275static void dispc_restore_context(void)
80c39712 276{
c6104b8e 277 int i, j, ctx;
4fbafaf3
TV		 278
279 DSSDBG("dispc_restore_context\n");
280
49ea86f3
TV		 281 if (!dispc.ctx_valid)
282 return;
283
284 ctx = dispc_get_ctx_loss_count();
285
286 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
287 return;
288
289 DSSDBG("ctx_loss_count: saved %d, current %d\n",
290 dispc.ctx_loss_cnt, ctx);
291
75c7d59d 292 /*RR(IRQENABLE);*/
80c39712
TV		 293 /*RR(CONTROL);*/
294 RR(CONFIG);
80c39712 295 RR(LINE_NUMBER);
332e9d70
TV		 296 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
297 RR(GLOBAL_ALPHA);
c6104b8e 298 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 299 RR(CONFIG2);
80c39712 300
c6104b8e
AT		 301 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
302 RR(DEFAULT_COLOR(i));
303 RR(TRANS_COLOR(i));
304 RR(SIZE_MGR(i));
305 if (i == OMAP_DSS_CHANNEL_DIGIT)
306 continue;
307 RR(TIMING_H(i));
308 RR(TIMING_V(i));
309 RR(POL_FREQ(i));
310 RR(DIVISORo(i));
311
312 RR(DATA_CYCLE1(i));
313 RR(DATA_CYCLE2(i));
314 RR(DATA_CYCLE3(i));
2a205f34 315
332e9d70 316 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 317 RR(CPR_COEF_R(i));
318 RR(CPR_COEF_G(i));
319 RR(CPR_COEF_B(i));
332e9d70 320 }
2a205f34 321 }
80c39712 322
c6104b8e
AT		 323 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
324 RR(OVL_BA0(i));
325 RR(OVL_BA1(i));
326 RR(OVL_POSITION(i));
327 RR(OVL_SIZE(i));
328 RR(OVL_ATTRIBUTES(i));
329 RR(OVL_FIFO_THRESHOLD(i));
330 RR(OVL_ROW_INC(i));
331 RR(OVL_PIXEL_INC(i));
332 if (dss_has_feature(FEAT_PRELOAD))
333 RR(OVL_PRELOAD(i));
334 if (i == OMAP_DSS_GFX) {
335 RR(OVL_WINDOW_SKIP(i));
336 RR(OVL_TABLE_BA(i));
337 continue;
338 }
339 RR(OVL_FIR(i));
340 RR(OVL_PICTURE_SIZE(i));
341 RR(OVL_ACCU0(i));
342 RR(OVL_ACCU1(i));
9b372c2d 343
c6104b8e
AT		 344 for (j = 0; j < 8; j++)
345 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 346
c6104b8e
AT		 347 for (j = 0; j < 8; j++)
348 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 349
c6104b8e
AT		 350 for (j = 0; j < 5; j++)
351 RR(OVL_CONV_COEF(i, j));
ab5ca071 352
c6104b8e
AT		 353 if (dss_has_feature(FEAT_FIR_COEF_V)) {
354 for (j = 0; j < 8; j++)
355 RR(OVL_FIR_COEF_V(i, j));
356 }
9b372c2d 357
c6104b8e
AT		 358 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
359 RR(OVL_BA0_UV(i));
360 RR(OVL_BA1_UV(i));
361 RR(OVL_FIR2(i));
362 RR(OVL_ACCU2_0(i));
363 RR(OVL_ACCU2_1(i));
ab5ca071 364
c6104b8e
AT		 365 for (j = 0; j < 8; j++)
366 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 367
c6104b8e
AT		 368 for (j = 0; j < 8; j++)
369 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 370
c6104b8e
AT		 371 for (j = 0; j < 8; j++)
372 RR(OVL_FIR_COEF_V2(i, j));
373 }
374 if (dss_has_feature(FEAT_ATTR2))
375 RR(OVL_ATTRIBUTES2(i));
ab5ca071 376 }
80c39712 377
0cf35df3
MR		 378 if (dss_has_feature(FEAT_CORE_CLK_DIV))
379 RR(DIVISOR);
380
80c39712
TV		 381 /* enable last, because LCD & DIGIT enable are here */
382 RR(CONTROL);
2a205f34
SS		 383 if (dss_has_feature(FEAT_MGR_LCD2))
384 RR(CONTROL2);
75c7d59d
VS		 385 /* clear spurious SYNC_LOST_DIGIT interrupts */
386 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
387
388 /*
389 * enable last so IRQs won't trigger before
390 * the context is fully restored
391 */
392 RR(IRQENABLE);
49ea86f3
TV		 393
394 DSSDBG("context restored\n");
80c39712
TV		 395}
396
397#undef SR
398#undef RR
399
4fbafaf3
TV		 400int dispc_runtime_get(void)
401{
402 int r;
403
404 DSSDBG("dispc_runtime_get\n");
405
406 r = pm_runtime_get_sync(&dispc.pdev->dev);
407 WARN_ON(r < 0);
408 return r < 0 ? r : 0;
409}
410
411void dispc_runtime_put(void)
412{
413 int r;
414
415 DSSDBG("dispc_runtime_put\n");
416
417 r = pm_runtime_put(&dispc.pdev->dev);
418 WARN_ON(r < 0);
80c39712
TV		 419}
420
dac57a05
AT		 421static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
422{
423 if (channel == OMAP_DSS_CHANNEL_LCD ||
424 channel == OMAP_DSS_CHANNEL_LCD2)
425 return true;
426 else
427 return false;
428}
4fbafaf3 429
c3dc6a7a
AT		 430static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
431{
432 struct omap_overlay_manager *mgr =
433 omap_dss_get_overlay_manager(channel);
434
435 return mgr ? mgr->device : NULL;
436}
437
26d9dd0d 438bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 439{
440 int bit;
441
dac57a05 442 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 443 bit = 5; /* GOLCD */
444 else
445 bit = 6; /* GODIGIT */
446
2a205f34
SS		 447 if (channel == OMAP_DSS_CHANNEL_LCD2)
448 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
449 else
450 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 451}
452
26d9dd0d 453void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 454{
455 int bit;
2a205f34 456 bool enable_bit, go_bit;
80c39712 457
dac57a05 458 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 459 bit = 0; /* LCDENABLE */
460 else
461 bit = 1; /* DIGITALENABLE */
462
463 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 464 if (channel == OMAP_DSS_CHANNEL_LCD2)
465 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
466 else
467 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
468
469 if (!enable_bit)
e6d80f95 470 return;
80c39712 471
dac57a05 472 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 473 bit = 5; /* GOLCD */
474 else
475 bit = 6; /* GODIGIT */
476
2a205f34
SS		 477 if (channel == OMAP_DSS_CHANNEL_LCD2)
478 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
479 else
480 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
481
482 if (go_bit) {
80c39712 483 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 484 return;
80c39712
TV		 485 }
486
2a205f34
SS		 487 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
488 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 489
2a205f34
SS		 490 if (channel == OMAP_DSS_CHANNEL_LCD2)
491 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
492 else
493 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 494}
495
f0e5caab 496static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 497{
9b372c2d 498 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 499}
500
f0e5caab 501static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 502{
9b372c2d 503 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 504}
505
f0e5caab 506static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 507{
9b372c2d 508 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 509}
510
f0e5caab 511static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 512{
513 BUG_ON(plane == OMAP_DSS_GFX);
514
515 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
516}
517
f0e5caab
TV		 518static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
519 u32 value)
ab5ca071
AJ		 520{
521 BUG_ON(plane == OMAP_DSS_GFX);
522
523 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
524}
525
f0e5caab 526static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 527{
528 BUG_ON(plane == OMAP_DSS_GFX);
529
530 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
531}
532
f0e5caab 533static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
0d66cbb5
AJ		 534 int vscaleup, int five_taps,
535 enum omap_color_component color_comp)
80c39712
TV		 536{
537 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 538 static const struct dispc_h_coef coef_hup[8] = {
539 { 0, 0, 128, 0, 0 },
540 { -1, 13, 124, -8, 0 },
541 { -2, 30, 112, -11, -1 },
542 { -5, 51, 95, -11, -2 },
543 { 0, -9, 73, 73, -9 },
544 { -2, -11, 95, 51, -5 },
545 { -1, -11, 112, 30, -2 },
546 { 0, -8, 124, 13, -1 },
80c39712
TV		 547 };
548
66be8f6c
GI		 549 /* Coefficients for vertical up-sampling */
550 static const struct dispc_v_coef coef_vup_3tap[8] = {
551 { 0, 0, 128, 0, 0 },
552 { 0, 3, 123, 2, 0 },
553 { 0, 12, 111, 5, 0 },
554 { 0, 32, 89, 7, 0 },
555 { 0, 0, 64, 64, 0 },
556 { 0, 7, 89, 32, 0 },
557 { 0, 5, 111, 12, 0 },
558 { 0, 2, 123, 3, 0 },
80c39712
TV		 559 };
560
66be8f6c
GI		 561 static const struct dispc_v_coef coef_vup_5tap[8] = {
562 { 0, 0, 128, 0, 0 },
563 { -1, 13, 124, -8, 0 },
564 { -2, 30, 112, -11, -1 },
565 { -5, 51, 95, -11, -2 },
566 { 0, -9, 73, 73, -9 },
567 { -2, -11, 95, 51, -5 },
568 { -1, -11, 112, 30, -2 },
569 { 0, -8, 124, 13, -1 },
80c39712
TV		 570 };
571
66be8f6c
GI		 572 /* Coefficients for horizontal down-sampling */
573 static const struct dispc_h_coef coef_hdown[8] = {
574 { 0, 36, 56, 36, 0 },
575 { 4, 40, 55, 31, -2 },
576 { 8, 44, 54, 27, -5 },
577 { 12, 48, 53, 22, -7 },
578 { -9, 17, 52, 51, 17 },
579 { -7, 22, 53, 48, 12 },
580 { -5, 27, 54, 44, 8 },
581 { -2, 31, 55, 40, 4 },
80c39712
TV		 582 };
583
66be8f6c
GI		 584 /* Coefficients for vertical down-sampling */
585 static const struct dispc_v_coef coef_vdown_3tap[8] = {
586 { 0, 36, 56, 36, 0 },
587 { 0, 40, 57, 31, 0 },
588 { 0, 45, 56, 27, 0 },
589 { 0, 50, 55, 23, 0 },
590 { 0, 18, 55, 55, 0 },
591 { 0, 23, 55, 50, 0 },
592 { 0, 27, 56, 45, 0 },
593 { 0, 31, 57, 40, 0 },
80c39712
TV		 594 };
595
66be8f6c
GI		 596 static const struct dispc_v_coef coef_vdown_5tap[8] = {
597 { 0, 36, 56, 36, 0 },
598 { 4, 40, 55, 31, -2 },
599 { 8, 44, 54, 27, -5 },
600 { 12, 48, 53, 22, -7 },
601 { -9, 17, 52, 51, 17 },
602 { -7, 22, 53, 48, 12 },
603 { -5, 27, 54, 44, 8 },
604 { -2, 31, 55, 40, 4 },
80c39712
TV		 605 };
606
66be8f6c
GI		 607 const struct dispc_h_coef *h_coef;
608 const struct dispc_v_coef *v_coef;
80c39712
TV		 609 int i;
610
611 if (hscaleup)
612 h_coef = coef_hup;
613 else
614 h_coef = coef_hdown;
615
66be8f6c
GI		 616 if (vscaleup)
617 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
618 else
619 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 620
621 for (i = 0; i < 8; i++) {
622 u32 h, hv;
623
66be8f6c
GI		 624 h = FLD_VAL(h_coef[i].hc0, 7, 0)
625 | FLD_VAL(h_coef[i].hc1, 15, 8)
626 | FLD_VAL(h_coef[i].hc2, 23, 16)
627 | FLD_VAL(h_coef[i].hc3, 31, 24);
628 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
629 | FLD_VAL(v_coef[i].vc0, 15, 8)
630 | FLD_VAL(v_coef[i].vc1, 23, 16)
631 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712 632
0d66cbb5 633 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 634 dispc_ovl_write_firh_reg(plane, i, h);
635 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 636 } else {
f0e5caab
TV		 637 dispc_ovl_write_firh2_reg(plane, i, h);
638 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 639 }
640
80c39712
TV		 641 }
642
66be8f6c
GI		 643 if (five_taps) {
644 for (i = 0; i < 8; i++) {
645 u32 v;
646 v = FLD_VAL(v_coef[i].vc00, 7, 0)
647 | FLD_VAL(v_coef[i].vc22, 15, 8);
0d66cbb5 648 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 649 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 650 else
f0e5caab 651 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 652 }
80c39712
TV		 653 }
654}
655
656static void _dispc_setup_color_conv_coef(void)
657{
ac01c29e 658 int i;
80c39712
TV		 659 const struct color_conv_coef {
660 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
661 int full_range;
662 } ctbl_bt601_5 = {
663 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
664 };
665
666 const struct color_conv_coef *ct;
667
668#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
669
670 ct = &ctbl_bt601_5;
671
ac01c29e
AT		 672 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
673 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
674 CVAL(ct->rcr, ct->ry));
675 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
676 CVAL(ct->gy, ct->rcb));
677 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
678 CVAL(ct->gcb, ct->gcr));
679 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
680 CVAL(ct->bcr, ct->by));
681 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
682 CVAL(0, ct->bcb));
683
684 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
685 11, 11);
686 }
80c39712
TV		 687
688#undef CVAL
80c39712
TV		 689}
690
691
f0e5caab 692static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 693{
9b372c2d 694 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 695}
696
f0e5caab 697static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 698{
9b372c2d 699 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 700}
701
f0e5caab 702static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 703{
704 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
705}
706
f0e5caab 707static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 708{
709 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
710}
711
f0e5caab 712static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 713{
80c39712 714 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 715
716 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 717}
718
f0e5caab 719static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 720{
80c39712 721 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 722
723 if (plane == OMAP_DSS_GFX)
724 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
725 else
726 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 727}
728
f0e5caab 729static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 730{
731 u32 val;
80c39712
TV		 732
733 BUG_ON(plane == OMAP_DSS_GFX);
734
735 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 736
737 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 738}
739
f0e5caab 740static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 741{
f6dc8150 742 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 743
f6dc8150 744 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 745 return;
746
9b372c2d 747 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 748}
749
f0e5caab 750static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 751{
fe3cc9d6
TV		 752 static const unsigned shifts[] = { 0, 8, 16, };
753 int shift;
f6dc8150 754 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 755
f6dc8150 756 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 757 return;
a0acb557 758
fe3cc9d6
TV		 759 shift = shifts[plane];
760 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 761}
762
f0e5caab 763static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 764{
9b372c2d 765 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 766}
767
f0e5caab 768static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 769{
9b372c2d 770 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 771}
772
f0e5caab 773static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 774 enum omap_color_mode color_mode)
775{
776 u32 m = 0;
f20e4220
AJ		 777 if (plane != OMAP_DSS_GFX) {
778 switch (color_mode) {
779 case OMAP_DSS_COLOR_NV12:
780 m = 0x0; break;
781 case OMAP_DSS_COLOR_RGB12U:
782 m = 0x1; break;
783 case OMAP_DSS_COLOR_RGBA16:
784 m = 0x2; break;
785 case OMAP_DSS_COLOR_RGBX16:
786 m = 0x4; break;
787 case OMAP_DSS_COLOR_ARGB16:
788 m = 0x5; break;
789 case OMAP_DSS_COLOR_RGB16:
790 m = 0x6; break;
791 case OMAP_DSS_COLOR_ARGB16_1555:
792 m = 0x7; break;
793 case OMAP_DSS_COLOR_RGB24U:
794 m = 0x8; break;
795 case OMAP_DSS_COLOR_RGB24P:
796 m = 0x9; break;
797 case OMAP_DSS_COLOR_YUV2:
798 m = 0xa; break;
799 case OMAP_DSS_COLOR_UYVY:
800 m = 0xb; break;
801 case OMAP_DSS_COLOR_ARGB32:
802 m = 0xc; break;
803 case OMAP_DSS_COLOR_RGBA32:
804 m = 0xd; break;
805 case OMAP_DSS_COLOR_RGBX32:
806 m = 0xe; break;
807 case OMAP_DSS_COLOR_XRGB16_1555:
808 m = 0xf; break;
809 default:
810 BUG(); break;
811 }
812 } else {
813 switch (color_mode) {
814 case OMAP_DSS_COLOR_CLUT1:
815 m = 0x0; break;
816 case OMAP_DSS_COLOR_CLUT2:
817 m = 0x1; break;
818 case OMAP_DSS_COLOR_CLUT4:
819 m = 0x2; break;
820 case OMAP_DSS_COLOR_CLUT8:
821 m = 0x3; break;
822 case OMAP_DSS_COLOR_RGB12U:
823 m = 0x4; break;
824 case OMAP_DSS_COLOR_ARGB16:
825 m = 0x5; break;
826 case OMAP_DSS_COLOR_RGB16:
827 m = 0x6; break;
828 case OMAP_DSS_COLOR_ARGB16_1555:
829 m = 0x7; break;
830 case OMAP_DSS_COLOR_RGB24U:
831 m = 0x8; break;
832 case OMAP_DSS_COLOR_RGB24P:
833 m = 0x9; break;
834 case OMAP_DSS_COLOR_YUV2:
835 m = 0xa; break;
836 case OMAP_DSS_COLOR_UYVY:
837 m = 0xb; break;
838 case OMAP_DSS_COLOR_ARGB32:
839 m = 0xc; break;
840 case OMAP_DSS_COLOR_RGBA32:
841 m = 0xd; break;
842 case OMAP_DSS_COLOR_RGBX32:
843 m = 0xe; break;
844 case OMAP_DSS_COLOR_XRGB16_1555:
845 m = 0xf; break;
846 default:
847 BUG(); break;
848 }
80c39712
TV		 849 }
850
9b372c2d 851 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 852}
853
f0e5caab 854static void dispc_ovl_set_channel_out(enum omap_plane plane,
80c39712
TV		 855 enum omap_channel channel)
856{
857 int shift;
858 u32 val;
2a205f34 859 int chan = 0, chan2 = 0;
80c39712
TV		 860
861 switch (plane) {
862 case OMAP_DSS_GFX:
863 shift = 8;
864 break;
865 case OMAP_DSS_VIDEO1:
866 case OMAP_DSS_VIDEO2:
867 shift = 16;
868 break;
869 default:
870 BUG();
871 return;
872 }
873
9b372c2d 874 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 875 if (dss_has_feature(FEAT_MGR_LCD2)) {
876 switch (channel) {
877 case OMAP_DSS_CHANNEL_LCD:
878 chan = 0;
879 chan2 = 0;
880 break;
881 case OMAP_DSS_CHANNEL_DIGIT:
882 chan = 1;
883 chan2 = 0;
884 break;
885 case OMAP_DSS_CHANNEL_LCD2:
886 chan = 0;
887 chan2 = 1;
888 break;
889 default:
890 BUG();
891 }
892
893 val = FLD_MOD(val, chan, shift, shift);
894 val = FLD_MOD(val, chan2, 31, 30);
895 } else {
896 val = FLD_MOD(val, channel, shift, shift);
897 }
9b372c2d 898 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 899}
900
f0e5caab 901static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 902 enum omap_burst_size burst_size)
903{
fe3cc9d6 904 static const unsigned shifts[] = { 6, 14, 14, };
80c39712 905 int shift;
80c39712 906
fe3cc9d6 907 shift = shifts[plane];
5ed8cf5b 908 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 909}
910
5ed8cf5b
TV		 911static void dispc_configure_burst_sizes(void)
912{
913 int i;
914 const int burst_size = BURST_SIZE_X8;
915
916 /* Configure burst size always to maximum size */
917 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 918 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 919}
920
f0e5caab 921u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 922{
923 unsigned unit = dss_feat_get_burst_size_unit();
924 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
925 return unit * 8;
926}
927
d3862610
M		 928void dispc_enable_gamma_table(bool enable)
929{
930 /*
931 * This is partially implemented to support only disabling of
932 * the gamma table.
933 */
934 if (enable) {
935 DSSWARN("Gamma table enabling for TV not yet supported");
936 return;
937 }
938
939 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
940}
941
26d9dd0d 942void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 943{
944 u16 reg;
945
946 if (channel == OMAP_DSS_CHANNEL_LCD)
947 reg = DISPC_CONFIG;
948 else if (channel == OMAP_DSS_CHANNEL_LCD2)
949 reg = DISPC_CONFIG2;
950 else
951 return;
952
953 REG_FLD_MOD(reg, enable, 15, 15);
954}
955
26d9dd0d 956void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 957 struct omap_dss_cpr_coefs *coefs)
958{
959 u32 coef_r, coef_g, coef_b;
960
dac57a05 961 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 962 return;
963
964 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
965 FLD_VAL(coefs->rb, 9, 0);
966 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
967 FLD_VAL(coefs->gb, 9, 0);
968 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
969 FLD_VAL(coefs->bb, 9, 0);
970
971 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
972 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
973 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
974}
975
f0e5caab 976static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 977{
978 u32 val;
979
980 BUG_ON(plane == OMAP_DSS_GFX);
981
9b372c2d 982 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 983 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 984 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 985}
986
c3d92529 987static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 988{
fe3cc9d6
TV		 989 static const unsigned shifts[] = { 5, 10, 10 };
990 int shift;
80c39712 991
fe3cc9d6
TV		 992 shift = shifts[plane];
993 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 994}
995
26d9dd0d 996void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 997{
998 u32 val;
999 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1000 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1001 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1002}
1003
1004void dispc_set_digit_size(u16 width, u16 height)
1005{
1006 u32 val;
1007 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1008 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1009 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1010}
1011
1012static void dispc_read_plane_fifo_sizes(void)
1013{
80c39712
TV		 1014 u32 size;
1015 int plane;
a0acb557 1016 u8 start, end;
5ed8cf5b
TV		 1017 u32 unit;
1018
1019 unit = dss_feat_get_buffer_size_unit();
80c39712 1020
a0acb557 1021 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1022
e13a138b 1023 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1024 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1025 size *= unit;
80c39712
TV		 1026 dispc.fifo_size[plane] = size;
1027 }
80c39712
TV		 1028}
1029
f0e5caab 1030u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1031{
1032 return dispc.fifo_size[plane];
1033}
1034
c3d92529
AT		 1035static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1036 u32 high)
80c39712 1037{
a0acb557 1038 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1039 u32 unit;
1040
1041 unit = dss_feat_get_buffer_size_unit();
1042
1043 WARN_ON(low % unit != 0);
1044 WARN_ON(high % unit != 0);
1045
1046 low /= unit;
1047 high /= unit;
a0acb557 1048
9b372c2d
AT		 1049 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1050 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1051
80c39712
TV		 1052 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1053 plane,
9b372c2d
AT		 1054 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1055 lo_start, lo_end),
1056 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1057 hi_start, hi_end),
80c39712
TV		 1058 low, high);
1059
9b372c2d 1060 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1061 FLD_VAL(high, hi_start, hi_end) |
1062 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1063}
1064
1065void dispc_enable_fifomerge(bool enable)
1066{
80c39712
TV		 1067 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1068 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1069}
1070
f0e5caab 1071static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1072 int hinc, int vinc,
1073 enum omap_color_component color_comp)
80c39712
TV		 1074{
1075 u32 val;
80c39712 1076
0d66cbb5
AJ		 1077 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1078 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1079
0d66cbb5
AJ		 1080 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1081 &hinc_start, &hinc_end);
1082 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1083 &vinc_start, &vinc_end);
1084 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1085 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1086
0d66cbb5
AJ		 1087 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1088 } else {
1089 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1090 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1091 }
80c39712
TV		 1092}
1093
f0e5caab 1094static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1095{
1096 u32 val;
87a7484b 1097 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1098
87a7484b
AT		 1099 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1100 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1101
1102 val = FLD_VAL(vaccu, vert_start, vert_end) |
1103 FLD_VAL(haccu, hor_start, hor_end);
1104
9b372c2d 1105 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1106}
1107
f0e5caab 1108static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1109{
1110 u32 val;
87a7484b 1111 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1112
87a7484b
AT		 1113 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1114 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1115
1116 val = FLD_VAL(vaccu, vert_start, vert_end) |
1117 FLD_VAL(haccu, hor_start, hor_end);
1118
9b372c2d 1119 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1120}
1121
f0e5caab
TV		 1122static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1123 int vaccu)
ab5ca071
AJ		 1124{
1125 u32 val;
1126
1127 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1128 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1129}
1130
f0e5caab
TV		 1131static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1132 int vaccu)
ab5ca071
AJ		 1133{
1134 u32 val;
1135
1136 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1137 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1138}
80c39712 1139
f0e5caab 1140static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1141 u16 orig_width, u16 orig_height,
1142 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1143 bool five_taps, u8 rotation,
1144 enum omap_color_component color_comp)
80c39712 1145{
0d66cbb5 1146 int fir_hinc, fir_vinc;
80c39712 1147 int hscaleup, vscaleup;
80c39712
TV		 1148
1149 hscaleup = orig_width <= out_width;
1150 vscaleup = orig_height <= out_height;
1151
f0e5caab
TV		 1152 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1153 color_comp);
80c39712 1154
ed14a3ce
AJ		 1155 fir_hinc = 1024 * orig_width / out_width;
1156 fir_vinc = 1024 * orig_height / out_height;
80c39712 1157
f0e5caab 1158 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1159}
1160
f0e5caab 1161static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1162 u16 orig_width, u16 orig_height,
1163 u16 out_width, u16 out_height,
1164 bool ilace, bool five_taps,
1165 bool fieldmode, enum omap_color_mode color_mode,
1166 u8 rotation)
1167{
1168 int accu0 = 0;
1169 int accu1 = 0;
1170 u32 l;
80c39712 1171
f0e5caab 1172 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1173 out_width, out_height, five_taps,
1174 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1175 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1176
87a7484b
AT		 1177 /* RESIZEENABLE and VERTICALTAPS */
1178 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1179 l |= (orig_width != out_width) ? (1 << 5) : 0;
1180 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1181 l |= five_taps ? (1 << 21) : 0;
80c39712 1182
87a7484b
AT		 1183 /* VRESIZECONF and HRESIZECONF */
1184 if (dss_has_feature(FEAT_RESIZECONF)) {
1185 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1186 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1187 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1188 }
80c39712 1189
87a7484b
AT		 1190 /* LINEBUFFERSPLIT */
1191 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1192 l &= ~(0x1 << 22);
1193 l |= five_taps ? (1 << 22) : 0;
1194 }
80c39712 1195
9b372c2d 1196 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1197
1198 /*
1199 * field 0 = even field = bottom field
1200 * field 1 = odd field = top field
1201 */
1202 if (ilace && !fieldmode) {
1203 accu1 = 0;
0d66cbb5 1204 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1205 if (accu0 >= 1024/2) {
1206 accu1 = 1024/2;
1207 accu0 -= accu1;
1208 }
1209 }
1210
f0e5caab
TV		 1211 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1212 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1213}
1214
f0e5caab 1215static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1216 u16 orig_width, u16 orig_height,
1217 u16 out_width, u16 out_height,
1218 bool ilace, bool five_taps,
1219 bool fieldmode, enum omap_color_mode color_mode,
1220 u8 rotation)
1221{
1222 int scale_x = out_width != orig_width;
1223 int scale_y = out_height != orig_height;
1224
1225 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1226 return;
1227 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1228 color_mode != OMAP_DSS_COLOR_UYVY &&
1229 color_mode != OMAP_DSS_COLOR_NV12)) {
1230 /* reset chroma resampling for RGB formats */
1231 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1232 return;
1233 }
1234 switch (color_mode) {
1235 case OMAP_DSS_COLOR_NV12:
1236 /* UV is subsampled by 2 vertically*/
1237 orig_height >>= 1;
1238 /* UV is subsampled by 2 horz.*/
1239 orig_width >>= 1;
1240 break;
1241 case OMAP_DSS_COLOR_YUV2:
1242 case OMAP_DSS_COLOR_UYVY:
1243 /*For YUV422 with 90/270 rotation,
1244 *we don't upsample chroma
1245 */
1246 if (rotation == OMAP_DSS_ROT_0 ||
1247 rotation == OMAP_DSS_ROT_180)
1248 /* UV is subsampled by 2 hrz*/
1249 orig_width >>= 1;
1250 /* must use FIR for YUV422 if rotated */
1251 if (rotation != OMAP_DSS_ROT_0)
1252 scale_x = scale_y = true;
1253 break;
1254 default:
1255 BUG();
1256 }
1257
1258 if (out_width != orig_width)
1259 scale_x = true;
1260 if (out_height != orig_height)
1261 scale_y = true;
1262
f0e5caab 1263 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1264 out_width, out_height, five_taps,
1265 rotation, DISPC_COLOR_COMPONENT_UV);
1266
1267 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1268 (scale_x || scale_y) ? 1 : 0, 8, 8);
1269 /* set H scaling */
1270 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1271 /* set V scaling */
1272 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1273
f0e5caab
TV		 1274 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1275 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
0d66cbb5
AJ		 1276}
1277
f0e5caab 1278static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1279 u16 orig_width, u16 orig_height,
1280 u16 out_width, u16 out_height,
1281 bool ilace, bool five_taps,
1282 bool fieldmode, enum omap_color_mode color_mode,
1283 u8 rotation)
1284{
1285 BUG_ON(plane == OMAP_DSS_GFX);
1286
f0e5caab 1287 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1288 orig_width, orig_height,
1289 out_width, out_height,
1290 ilace, five_taps,
1291 fieldmode, color_mode,
1292 rotation);
1293
f0e5caab 1294 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1295 orig_width, orig_height,
1296 out_width, out_height,
1297 ilace, five_taps,
1298 fieldmode, color_mode,
1299 rotation);
1300}
1301
f0e5caab 1302static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1303 bool mirroring, enum omap_color_mode color_mode)
1304{
87a7484b
AT		 1305 bool row_repeat = false;
1306 int vidrot = 0;
1307
80c39712
TV		 1308 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1309 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1310
1311 if (mirroring) {
1312 switch (rotation) {
1313 case OMAP_DSS_ROT_0:
1314 vidrot = 2;
1315 break;
1316 case OMAP_DSS_ROT_90:
1317 vidrot = 1;
1318 break;
1319 case OMAP_DSS_ROT_180:
1320 vidrot = 0;
1321 break;
1322 case OMAP_DSS_ROT_270:
1323 vidrot = 3;
1324 break;
1325 }
1326 } else {
1327 switch (rotation) {
1328 case OMAP_DSS_ROT_0:
1329 vidrot = 0;
1330 break;
1331 case OMAP_DSS_ROT_90:
1332 vidrot = 1;
1333 break;
1334 case OMAP_DSS_ROT_180:
1335 vidrot = 2;
1336 break;
1337 case OMAP_DSS_ROT_270:
1338 vidrot = 3;
1339 break;
1340 }
1341 }
1342
80c39712 1343 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1344 row_repeat = true;
80c39712 1345 else
87a7484b 1346 row_repeat = false;
80c39712 1347 }
87a7484b 1348
9b372c2d 1349 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1350 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1351 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1352 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1353}
1354
1355static int color_mode_to_bpp(enum omap_color_mode color_mode)
1356{
1357 switch (color_mode) {
1358 case OMAP_DSS_COLOR_CLUT1:
1359 return 1;
1360 case OMAP_DSS_COLOR_CLUT2:
1361 return 2;
1362 case OMAP_DSS_COLOR_CLUT4:
1363 return 4;
1364 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1365 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1366 return 8;
1367 case OMAP_DSS_COLOR_RGB12U:
1368 case OMAP_DSS_COLOR_RGB16:
1369 case OMAP_DSS_COLOR_ARGB16:
1370 case OMAP_DSS_COLOR_YUV2:
1371 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1372 case OMAP_DSS_COLOR_RGBA16:
1373 case OMAP_DSS_COLOR_RGBX16:
1374 case OMAP_DSS_COLOR_ARGB16_1555:
1375 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1376 return 16;
1377 case OMAP_DSS_COLOR_RGB24P:
1378 return 24;
1379 case OMAP_DSS_COLOR_RGB24U:
1380 case OMAP_DSS_COLOR_ARGB32:
1381 case OMAP_DSS_COLOR_RGBA32:
1382 case OMAP_DSS_COLOR_RGBX32:
1383 return 32;
1384 default:
1385 BUG();
1386 }
1387}
1388
1389static s32 pixinc(int pixels, u8 ps)
1390{
1391 if (pixels == 1)
1392 return 1;
1393 else if (pixels > 1)
1394 return 1 + (pixels - 1) * ps;
1395 else if (pixels < 0)
1396 return 1 - (-pixels + 1) * ps;
1397 else
1398 BUG();
1399}
1400
1401static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1402 u16 screen_width,
1403 u16 width, u16 height,
1404 enum omap_color_mode color_mode, bool fieldmode,
1405 unsigned int field_offset,
1406 unsigned *offset0, unsigned *offset1,
1407 s32 *row_inc, s32 *pix_inc)
1408{
1409 u8 ps;
1410
1411 /* FIXME CLUT formats */
1412 switch (color_mode) {
1413 case OMAP_DSS_COLOR_CLUT1:
1414 case OMAP_DSS_COLOR_CLUT2:
1415 case OMAP_DSS_COLOR_CLUT4:
1416 case OMAP_DSS_COLOR_CLUT8:
1417 BUG();
1418 return;
1419 case OMAP_DSS_COLOR_YUV2:
1420 case OMAP_DSS_COLOR_UYVY:
1421 ps = 4;
1422 break;
1423 default:
1424 ps = color_mode_to_bpp(color_mode) / 8;
1425 break;
1426 }
1427
1428 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1429 width, height);
1430
1431 /*
1432 * field 0 = even field = bottom field
1433 * field 1 = odd field = top field
1434 */
1435 switch (rotation + mirror * 4) {
1436 case OMAP_DSS_ROT_0:
1437 case OMAP_DSS_ROT_180:
1438 /*
1439 * If the pixel format is YUV or UYVY divide the width
1440 * of the image by 2 for 0 and 180 degree rotation.
1441 */
1442 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1443 color_mode == OMAP_DSS_COLOR_UYVY)
1444 width = width >> 1;
1445 case OMAP_DSS_ROT_90:
1446 case OMAP_DSS_ROT_270:
1447 *offset1 = 0;
1448 if (field_offset)
1449 *offset0 = field_offset * screen_width * ps;
1450 else
1451 *offset0 = 0;
1452
1453 *row_inc = pixinc(1 + (screen_width - width) +
1454 (fieldmode ? screen_width : 0),
1455 ps);
1456 *pix_inc = pixinc(1, ps);
1457 break;
1458
1459 case OMAP_DSS_ROT_0 + 4:
1460 case OMAP_DSS_ROT_180 + 4:
1461 /* If the pixel format is YUV or UYVY divide the width
1462 * of the image by 2 for 0 degree and 180 degree
1463 */
1464 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1465 color_mode == OMAP_DSS_COLOR_UYVY)
1466 width = width >> 1;
1467 case OMAP_DSS_ROT_90 + 4:
1468 case OMAP_DSS_ROT_270 + 4:
1469 *offset1 = 0;
1470 if (field_offset)
1471 *offset0 = field_offset * screen_width * ps;
1472 else
1473 *offset0 = 0;
1474 *row_inc = pixinc(1 - (screen_width + width) -
1475 (fieldmode ? screen_width : 0),
1476 ps);
1477 *pix_inc = pixinc(1, ps);
1478 break;
1479
1480 default:
1481 BUG();
1482 }
1483}
1484
1485static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1486 u16 screen_width,
1487 u16 width, u16 height,
1488 enum omap_color_mode color_mode, bool fieldmode,
1489 unsigned int field_offset,
1490 unsigned *offset0, unsigned *offset1,
1491 s32 *row_inc, s32 *pix_inc)
1492{
1493 u8 ps;
1494 u16 fbw, fbh;
1495
1496 /* FIXME CLUT formats */
1497 switch (color_mode) {
1498 case OMAP_DSS_COLOR_CLUT1:
1499 case OMAP_DSS_COLOR_CLUT2:
1500 case OMAP_DSS_COLOR_CLUT4:
1501 case OMAP_DSS_COLOR_CLUT8:
1502 BUG();
1503 return;
1504 default:
1505 ps = color_mode_to_bpp(color_mode) / 8;
1506 break;
1507 }
1508
1509 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1510 width, height);
1511
1512 /* width & height are overlay sizes, convert to fb sizes */
1513
1514 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1515 fbw = width;
1516 fbh = height;
1517 } else {
1518 fbw = height;
1519 fbh = width;
1520 }
1521
1522 /*
1523 * field 0 = even field = bottom field
1524 * field 1 = odd field = top field
1525 */
1526 switch (rotation + mirror * 4) {
1527 case OMAP_DSS_ROT_0:
1528 *offset1 = 0;
1529 if (field_offset)
1530 *offset0 = *offset1 + field_offset * screen_width * ps;
1531 else
1532 *offset0 = *offset1;
1533 *row_inc = pixinc(1 + (screen_width - fbw) +
1534 (fieldmode ? screen_width : 0),
1535 ps);
1536 *pix_inc = pixinc(1, ps);
1537 break;
1538 case OMAP_DSS_ROT_90:
1539 *offset1 = screen_width * (fbh - 1) * ps;
1540 if (field_offset)
1541 *offset0 = *offset1 + field_offset * ps;
1542 else
1543 *offset0 = *offset1;
1544 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1545 (fieldmode ? 1 : 0), ps);
1546 *pix_inc = pixinc(-screen_width, ps);
1547 break;
1548 case OMAP_DSS_ROT_180:
1549 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1550 if (field_offset)
1551 *offset0 = *offset1 - field_offset * screen_width * ps;
1552 else
1553 *offset0 = *offset1;
1554 *row_inc = pixinc(-1 -
1555 (screen_width - fbw) -
1556 (fieldmode ? screen_width : 0),
1557 ps);
1558 *pix_inc = pixinc(-1, ps);
1559 break;
1560 case OMAP_DSS_ROT_270:
1561 *offset1 = (fbw - 1) * ps;
1562 if (field_offset)
1563 *offset0 = *offset1 - field_offset * ps;
1564 else
1565 *offset0 = *offset1;
1566 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1567 (fieldmode ? 1 : 0), ps);
1568 *pix_inc = pixinc(screen_width, ps);
1569 break;
1570
1571 /* mirroring */
1572 case OMAP_DSS_ROT_0 + 4:
1573 *offset1 = (fbw - 1) * ps;
1574 if (field_offset)
1575 *offset0 = *offset1 + field_offset * screen_width * ps;
1576 else
1577 *offset0 = *offset1;
1578 *row_inc = pixinc(screen_width * 2 - 1 +
1579 (fieldmode ? screen_width : 0),
1580 ps);
1581 *pix_inc = pixinc(-1, ps);
1582 break;
1583
1584 case OMAP_DSS_ROT_90 + 4:
1585 *offset1 = 0;
1586 if (field_offset)
1587 *offset0 = *offset1 + field_offset * ps;
1588 else
1589 *offset0 = *offset1;
1590 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1591 (fieldmode ? 1 : 0),
1592 ps);
1593 *pix_inc = pixinc(screen_width, ps);
1594 break;
1595
1596 case OMAP_DSS_ROT_180 + 4:
1597 *offset1 = screen_width * (fbh - 1) * ps;
1598 if (field_offset)
1599 *offset0 = *offset1 - field_offset * screen_width * ps;
1600 else
1601 *offset0 = *offset1;
1602 *row_inc = pixinc(1 - screen_width * 2 -
1603 (fieldmode ? screen_width : 0),
1604 ps);
1605 *pix_inc = pixinc(1, ps);
1606 break;
1607
1608 case OMAP_DSS_ROT_270 + 4:
1609 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1610 if (field_offset)
1611 *offset0 = *offset1 - field_offset * ps;
1612 else
1613 *offset0 = *offset1;
1614 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1615 (fieldmode ? 1 : 0),
1616 ps);
1617 *pix_inc = pixinc(-screen_width, ps);
1618 break;
1619
1620 default:
1621 BUG();
1622 }
1623}
1624
ff1b2cde
SS		 1625static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1626 u16 height, u16 out_width, u16 out_height,
1627 enum omap_color_mode color_mode)
80c39712
TV		 1628{
1629 u32 fclk = 0;
26d9dd0d 1630 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1631
1632 if (height > out_height) {
ebdc5249
AT		 1633 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1634 unsigned int ppl = dssdev->panel.timings.x_res;
80c39712
TV		 1635
1636 tmp = pclk * height * out_width;
1637 do_div(tmp, 2 * out_height * ppl);
1638 fclk = tmp;
1639
2d9c5597
VS		 1640 if (height > 2 * out_height) {
1641 if (ppl == out_width)
1642 return 0;
1643
80c39712
TV		 1644 tmp = pclk * (height - 2 * out_height) * out_width;
1645 do_div(tmp, 2 * out_height * (ppl - out_width));
1646 fclk = max(fclk, (u32) tmp);
1647 }
1648 }
1649
1650 if (width > out_width) {
1651 tmp = pclk * width;
1652 do_div(tmp, out_width);
1653 fclk = max(fclk, (u32) tmp);
1654
1655 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1656 fclk <<= 1;
1657 }
1658
1659 return fclk;
1660}
1661
ff1b2cde
SS		 1662static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1663 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1664{
1665 unsigned int hf, vf;
1666
1667 /*
1668 * FIXME how to determine the 'A' factor
1669 * for the no downscaling case ?
1670 */
1671
1672 if (width > 3 * out_width)
1673 hf = 4;
1674 else if (width > 2 * out_width)
1675 hf = 3;
1676 else if (width > out_width)
1677 hf = 2;
1678 else
1679 hf = 1;
1680
1681 if (height > out_height)
1682 vf = 2;
1683 else
1684 vf = 1;
1685
26d9dd0d 1686 return dispc_mgr_pclk_rate(channel) * vf * hf;
80c39712
TV		 1687}
1688
79ad75f2
AT		 1689static int dispc_ovl_calc_scaling(enum omap_plane plane,
1690 enum omap_channel channel, u16 width, u16 height,
1691 u16 out_width, u16 out_height,
1692 enum omap_color_mode color_mode, bool *five_taps)
1693{
1694 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1695 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
79ad75f2
AT		 1696 unsigned long fclk = 0;
1697
1698 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
1699 if (width != out_width || height != out_height)
1700 return -EINVAL;
1701 else
1702 return 0;
1703 }
1704
1705 if (out_width < width / maxdownscale ||
1706 out_width > width * 8)
1707 return -EINVAL;
1708
1709 if (out_height < height / maxdownscale ||
1710 out_height > height * 8)
1711 return -EINVAL;
1712
1713 /* Must use 5-tap filter? */
1714 *five_taps = height > out_height * 2;
1715
1716 if (!*five_taps) {
1717 fclk = calc_fclk(channel, width, height, out_width,
1718 out_height);
1719
1720 /* Try 5-tap filter if 3-tap fclk is too high */
1721 if (cpu_is_omap34xx() && height > out_height &&
1722 fclk > dispc_fclk_rate())
1723 *five_taps = true;
1724 }
1725
1726 if (width > (2048 >> *five_taps)) {
1727 DSSERR("failed to set up scaling, fclk too low\n");
1728 return -EINVAL;
1729 }
1730
1731 if (*five_taps)
1732 fclk = calc_fclk_five_taps(channel, width, height,
1733 out_width, out_height, color_mode);
1734
1735 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1736 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1737
1738 if (!fclk || fclk > dispc_fclk_rate()) {
1739 DSSERR("failed to set up scaling, "
1740 "required fclk rate = %lu Hz, "
1741 "current fclk rate = %lu Hz\n",
1742 fclk, dispc_fclk_rate());
1743 return -EINVAL;
1744 }
1745
1746 return 0;
1747}
1748
a4273b7c 1749int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
c3d92529
AT		 1750 bool ilace, enum omap_channel channel, bool replication,
1751 u32 fifo_low, u32 fifo_high)
80c39712 1752{
79ad75f2
AT		 1753 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1754 bool five_taps = false;
80c39712 1755 bool fieldmode = 0;
79ad75f2 1756 int r, cconv = 0;
80c39712
TV		 1757 unsigned offset0, offset1;
1758 s32 row_inc;
1759 s32 pix_inc;
a4273b7c 1760 u16 frame_height = oi->height;
80c39712
TV		 1761 unsigned int field_offset = 0;
1762
a4273b7c 1763 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
c3d92529
AT		 1764 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1765 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1766 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1767 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1768 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
e6d80f95 1769
a4273b7c 1770 if (oi->paddr == 0)
80c39712
TV		 1771 return -EINVAL;
1772
a4273b7c 1773 if (ilace && oi->height == oi->out_height)
80c39712
TV		 1774 fieldmode = 1;
1775
1776 if (ilace) {
1777 if (fieldmode)
a4273b7c
AT		 1778 oi->height /= 2;
1779 oi->pos_y /= 2;
1780 oi->out_height /= 2;
80c39712
TV		 1781
1782 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1783 "out_height %d\n",
a4273b7c 1784 oi->height, oi->pos_y, oi->out_height);
80c39712
TV		 1785 }
1786
a4273b7c 1787 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 1788 return -EINVAL;
1789
79ad75f2
AT		 1790 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1791 oi->out_width, oi->out_height, oi->color_mode,
1792 &five_taps);
1793 if (r)
1794 return r;
80c39712 1795
79ad75f2
AT		 1796 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1797 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1798 oi->color_mode == OMAP_DSS_COLOR_NV12)
1799 cconv = 1;
80c39712
TV		 1800
1801 if (ilace && !fieldmode) {
1802 /*
1803 * when downscaling the bottom field may have to start several
1804 * source lines below the top field. Unfortunately ACCUI
1805 * registers will only hold the fractional part of the offset
1806 * so the integer part must be added to the base address of the
1807 * bottom field.
1808 */
a4273b7c 1809 if (!oi->height || oi->height == oi->out_height)
80c39712
TV		 1810 field_offset = 0;
1811 else
a4273b7c 1812 field_offset = oi->height / oi->out_height / 2;
80c39712
TV		 1813 }
1814
1815 /* Fields are independent but interleaved in memory. */
1816 if (fieldmode)
1817 field_offset = 1;
1818
a4273b7c
AT		 1819 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1820 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1821 oi->screen_width, oi->width, frame_height,
1822 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1823 &offset0, &offset1, &row_inc, &pix_inc);
1824 else
a4273b7c
AT		 1825 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1826 oi->screen_width, oi->width, frame_height,
1827 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1828 &offset0, &offset1, &row_inc, &pix_inc);
1829
1830 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1831 offset0, offset1, row_inc, pix_inc);
1832
a4273b7c 1833 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 1834
a4273b7c
AT		 1835 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1836 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 1837
a4273b7c
AT		 1838 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1839 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1840 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 1841 }
1842
1843
f0e5caab
TV		 1844 dispc_ovl_set_row_inc(plane, row_inc);
1845 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 1846
a4273b7c
AT		 1847 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1848 oi->height, oi->out_width, oi->out_height);
80c39712 1849
a4273b7c 1850 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 1851
a4273b7c 1852 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
80c39712 1853
79ad75f2 1854 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
a4273b7c
AT		 1855 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1856 oi->out_width, oi->out_height,
0d66cbb5 1857 ilace, five_taps, fieldmode,
a4273b7c
AT		 1858 oi->color_mode, oi->rotation);
1859 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
f0e5caab 1860 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 1861 }
1862
a4273b7c
AT		 1863 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1864 oi->color_mode);
80c39712 1865
a4273b7c
AT		 1866 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1867 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 1868
f0e5caab 1869 dispc_ovl_set_channel_out(plane, channel);
8fa8031c 1870
c3d92529
AT		 1871 dispc_ovl_enable_replication(plane, replication);
1872 dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1873
80c39712
TV		 1874 return 0;
1875}
1876
f0e5caab 1877int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 1878{
e6d80f95
TV		 1879 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1880
9b372c2d 1881 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 1882
1883 return 0;
80c39712
TV		 1884}
1885
1886static void dispc_disable_isr(void *data, u32 mask)
1887{
1888 struct completion *compl = data;
1889 complete(compl);
1890}
1891
2a205f34 1892static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1893{
2a205f34
SS		 1894 if (channel == OMAP_DSS_CHANNEL_LCD2)
1895 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1896 else
1897 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1898}
1899
26d9dd0d 1900static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1901{
1902 struct completion frame_done_completion;
1903 bool is_on;
1904 int r;
2a205f34 1905 u32 irq;
80c39712 1906
80c39712
TV		 1907 /* When we disable LCD output, we need to wait until frame is done.
1908 * Otherwise the DSS is still working, and turning off the clocks
1909 * prevents DSS from going to OFF mode */
2a205f34
SS		 1910 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1911 REG_GET(DISPC_CONTROL2, 0, 0) :
1912 REG_GET(DISPC_CONTROL, 0, 0);
1913
1914 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1915 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1916
1917 if (!enable && is_on) {
1918 init_completion(&frame_done_completion);
1919
1920 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1921 &frame_done_completion, irq);
80c39712
TV		 1922
1923 if (r)
1924 DSSERR("failed to register FRAMEDONE isr\n");
1925 }
1926
2a205f34 1927 _enable_lcd_out(channel, enable);
80c39712
TV		 1928
1929 if (!enable && is_on) {
1930 if (!wait_for_completion_timeout(&frame_done_completion,
1931 msecs_to_jiffies(100)))
1932 DSSERR("timeout waiting for FRAME DONE\n");
1933
1934 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1935 &frame_done_completion, irq);
80c39712
TV		 1936
1937 if (r)
1938 DSSERR("failed to unregister FRAMEDONE isr\n");
1939 }
80c39712
TV		 1940}
1941
1942static void _enable_digit_out(bool enable)
1943{
1944 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1945}
1946
26d9dd0d 1947static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 1948{
1949 struct completion frame_done_completion;
e82b090b
TV		 1950 enum dss_hdmi_venc_clk_source_select src;
1951 int r, i;
1952 u32 irq_mask;
1953 int num_irqs;
80c39712 1954
e6d80f95 1955 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 1956 return;
80c39712 1957
e82b090b
TV		 1958 src = dss_get_hdmi_venc_clk_source();
1959
80c39712
TV		 1960 if (enable) {
1961 unsigned long flags;
1962 /* When we enable digit output, we'll get an extra digit
1963 * sync lost interrupt, that we need to ignore */
1964 spin_lock_irqsave(&dispc.irq_lock, flags);
1965 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1966 _omap_dispc_set_irqs();
1967 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1968 }
1969
1970 /* When we disable digit output, we need to wait until fields are done.
1971 * Otherwise the DSS is still working, and turning off the clocks
1972 * prevents DSS from going to OFF mode. And when enabling, we need to
1973 * wait for the extra sync losts */
1974 init_completion(&frame_done_completion);
1975
e82b090b
TV		 1976 if (src == DSS_HDMI_M_PCLK && enable == false) {
1977 irq_mask = DISPC_IRQ_FRAMEDONETV;
1978 num_irqs = 1;
1979 } else {
1980 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
1981 /* XXX I understand from TRM that we should only wait for the
1982 * current field to complete. But it seems we have to wait for
1983 * both fields */
1984 num_irqs = 2;
1985 }
1986
80c39712 1987 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 1988 irq_mask);
80c39712 1989 if (r)
e82b090b 1990 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 1991
1992 _enable_digit_out(enable);
1993
e82b090b
TV		 1994 for (i = 0; i < num_irqs; ++i) {
1995 if (!wait_for_completion_timeout(&frame_done_completion,
1996 msecs_to_jiffies(100)))
1997 DSSERR("timeout waiting for digit out to %s\n",
1998 enable ? "start" : "stop");
1999 }
80c39712 2000
e82b090b
TV		 2001 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2002 irq_mask);
80c39712 2003 if (r)
e82b090b 2004 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2005
2006 if (enable) {
2007 unsigned long flags;
2008 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2009 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2010 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2011 _omap_dispc_set_irqs();
2012 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2013 }
80c39712
TV		 2014}
2015
26d9dd0d 2016bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2017{
2018 if (channel == OMAP_DSS_CHANNEL_LCD)
2019 return !!REG_GET(DISPC_CONTROL, 0, 0);
2020 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2021 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2022 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2023 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2024 else
2025 BUG();
2026}
2027
26d9dd0d 2028void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2029{
dac57a05 2030 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2031 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2032 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2033 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2034 else
2035 BUG();
2036}
2037
80c39712
TV		 2038void dispc_lcd_enable_signal_polarity(bool act_high)
2039{
6ced40bf
AT		 2040 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2041 return;
2042
80c39712 2043 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2044}
2045
2046void dispc_lcd_enable_signal(bool enable)
2047{
6ced40bf
AT		 2048 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2049 return;
2050
80c39712 2051 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2052}
2053
2054void dispc_pck_free_enable(bool enable)
2055{
6ced40bf
AT		 2056 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2057 return;
2058
80c39712 2059 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2060}
2061
26d9dd0d 2062void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2063{
2a205f34
SS		 2064 if (channel == OMAP_DSS_CHANNEL_LCD2)
2065 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2066 else
2067 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2068}
2069
2070
26d9dd0d 2071void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2072 enum omap_lcd_display_type type)
80c39712
TV		 2073{
2074 int mode;
2075
2076 switch (type) {
2077 case OMAP_DSS_LCD_DISPLAY_STN:
2078 mode = 0;
2079 break;
2080
2081 case OMAP_DSS_LCD_DISPLAY_TFT:
2082 mode = 1;
2083 break;
2084
2085 default:
2086 BUG();
2087 return;
2088 }
2089
2a205f34
SS		 2090 if (channel == OMAP_DSS_CHANNEL_LCD2)
2091 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2092 else
2093 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2094}
2095
2096void dispc_set_loadmode(enum omap_dss_load_mode mode)
2097{
80c39712 2098 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2099}
2100
2101
26d9dd0d 2102void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2103{
8613b000 2104 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2105}
2106
26d9dd0d 2107u32 dispc_mgr_get_default_color(enum omap_channel channel)
80c39712 2108{
80c39712
TV		 2109 u32 l;
2110
2111 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2112 channel != OMAP_DSS_CHANNEL_LCD &&
2113 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712 2114
8613b000 2115 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2116
2117 return l;
2118}
2119
26d9dd0d 2120void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2121 enum omap_dss_trans_key_type type,
2122 u32 trans_key)
2123{
80c39712
TV		 2124 if (ch == OMAP_DSS_CHANNEL_LCD)
2125 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2126 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2127 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2128 else /* OMAP_DSS_CHANNEL_LCD2 */
2129 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2130
8613b000 2131 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2132}
2133
26d9dd0d 2134void dispc_mgr_get_trans_key(enum omap_channel ch,
80c39712
TV		 2135 enum omap_dss_trans_key_type *type,
2136 u32 *trans_key)
2137{
80c39712
TV		 2138 if (type) {
2139 if (ch == OMAP_DSS_CHANNEL_LCD)
2140 *type = REG_GET(DISPC_CONFIG, 11, 11);
2141 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2142 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2143 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2144 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2145 else
2146 BUG();
2147 }
2148
2149 if (trans_key)
8613b000 2150 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2151}
2152
26d9dd0d 2153void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2154{
80c39712
TV		 2155 if (ch == OMAP_DSS_CHANNEL_LCD)
2156 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2157 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2158 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2159 else /* OMAP_DSS_CHANNEL_LCD2 */
2160 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2161}
26d9dd0d 2162void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable)
80c39712 2163{
a0acb557 2164 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2165 return;
2166
80c39712
TV		 2167 if (ch == OMAP_DSS_CHANNEL_LCD)
2168 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2169 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2170 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2171 else /* OMAP_DSS_CHANNEL_LCD2 */
2172 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712 2173}
26d9dd0d 2174bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch)
80c39712
TV		 2175{
2176 bool enabled;
2177
a0acb557 2178 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2179 return false;
2180
80c39712
TV		 2181 if (ch == OMAP_DSS_CHANNEL_LCD)
2182 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2183 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2184 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2185 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2186 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2187 else
2188 BUG();
80c39712
TV		 2189
2190 return enabled;
80c39712
TV		 2191}
2192
2193
26d9dd0d 2194bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
80c39712
TV		 2195{
2196 bool enabled;
2197
80c39712
TV		 2198 if (ch == OMAP_DSS_CHANNEL_LCD)
2199 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2200 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2201 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2202 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2203 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2204 else
2205 BUG();
80c39712
TV		 2206
2207 return enabled;
2208}
2209
2210
26d9dd0d 2211void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2212{
2213 int code;
2214
2215 switch (data_lines) {
2216 case 12:
2217 code = 0;
2218 break;
2219 case 16:
2220 code = 1;
2221 break;
2222 case 18:
2223 code = 2;
2224 break;
2225 case 24:
2226 code = 3;
2227 break;
2228 default:
2229 BUG();
2230 return;
2231 }
2232
2a205f34
SS		 2233 if (channel == OMAP_DSS_CHANNEL_LCD2)
2234 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2235 else
2236 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2237}
2238
569969d6 2239void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2240{
2241 u32 l;
569969d6 2242 int gpout0, gpout1;
80c39712
TV		 2243
2244 switch (mode) {
569969d6
AT		 2245 case DSS_IO_PAD_MODE_RESET:
2246 gpout0 = 0;
2247 gpout1 = 0;
80c39712 2248 break;
569969d6
AT		 2249 case DSS_IO_PAD_MODE_RFBI:
2250 gpout0 = 1;
80c39712
TV		 2251 gpout1 = 0;
2252 break;
569969d6
AT		 2253 case DSS_IO_PAD_MODE_BYPASS:
2254 gpout0 = 1;
80c39712
TV		 2255 gpout1 = 1;
2256 break;
80c39712
TV		 2257 default:
2258 BUG();
2259 return;
2260 }
2261
569969d6
AT		 2262 l = dispc_read_reg(DISPC_CONTROL);
2263 l = FLD_MOD(l, gpout0, 15, 15);
2264 l = FLD_MOD(l, gpout1, 16, 16);
2265 dispc_write_reg(DISPC_CONTROL, l);
2266}
2267
2268void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2269{
2270 if (channel == OMAP_DSS_CHANNEL_LCD2)
2271 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2272 else
2273 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2274}
2275
2276static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2277 int vsw, int vfp, int vbp)
2278{
2279 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2280 if (hsw < 1 || hsw > 64 ||
2281 hfp < 1 || hfp > 256 ||
2282 hbp < 1 || hbp > 256 ||
2283 vsw < 1 || vsw > 64 ||
2284 vfp < 0 || vfp > 255 ||
2285 vbp < 0 || vbp > 255)
2286 return false;
2287 } else {
2288 if (hsw < 1 || hsw > 256 ||
2289 hfp < 1 || hfp > 4096 ||
2290 hbp < 1 || hbp > 4096 ||
2291 vsw < 1 || vsw > 256 ||
2292 vfp < 0 || vfp > 4095 ||
2293 vbp < 0 || vbp > 4095)
2294 return false;
2295 }
2296
2297 return true;
2298}
2299
2300bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2301{
2302 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2303 timings->hbp, timings->vsw,
2304 timings->vfp, timings->vbp);
2305}
2306
26d9dd0d 2307static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2308 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2309{
2310 u32 timing_h, timing_v;
2311
2312 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2313 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2314 FLD_VAL(hbp-1, 27, 20);
2315
2316 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2317 FLD_VAL(vbp, 27, 20);
2318 } else {
2319 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2320 FLD_VAL(hbp-1, 31, 20);
2321
2322 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2323 FLD_VAL(vbp, 31, 20);
2324 }
2325
64ba4f74
SS		 2326 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2327 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2328}
2329
2330/* change name to mode? */
26d9dd0d 2331void dispc_mgr_set_lcd_timings(enum omap_channel channel,
64ba4f74 2332 struct omap_video_timings *timings)
80c39712
TV		 2333{
2334 unsigned xtot, ytot;
2335 unsigned long ht, vt;
2336
2337 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2338 timings->hbp, timings->vsw,
2339 timings->vfp, timings->vbp))
2340 BUG();
2341
26d9dd0d 2342 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
64ba4f74
SS		 2343 timings->hbp, timings->vsw, timings->vfp,
2344 timings->vbp);
80c39712 2345
26d9dd0d 2346 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2347
2348 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2349 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2350
2351 ht = (timings->pixel_clock * 1000) / xtot;
2352 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2353
2a205f34
SS		 2354 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2355 timings->y_res);
80c39712
TV		 2356 DSSDBG("pck %u\n", timings->pixel_clock);
2357 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2358 timings->hsw, timings->hfp, timings->hbp,
2359 timings->vsw, timings->vfp, timings->vbp);
2360
2361 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2362}
2363
26d9dd0d 2364static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2365 u16 pck_div)
80c39712
TV		 2366{
2367 BUG_ON(lck_div < 1);
9eaaf207 2368 BUG_ON(pck_div < 1);
80c39712 2369
ce7fa5eb 2370 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2371 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2372}
2373
26d9dd0d 2374static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2375 int *pck_div)
80c39712
TV		 2376{
2377 u32 l;
ce7fa5eb 2378 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2379 *lck_div = FLD_GET(l, 23, 16);
2380 *pck_div = FLD_GET(l, 7, 0);
2381}
2382
2383unsigned long dispc_fclk_rate(void)
2384{
a72b64b9 2385 struct platform_device *dsidev;
80c39712
TV		 2386 unsigned long r = 0;
2387
66534e8e 2388 switch (dss_get_dispc_clk_source()) {
89a35e51 2389 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2390 r = clk_get_rate(dispc.dss_clk);
66534e8e 2391 break;
89a35e51 2392 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2393 dsidev = dsi_get_dsidev_from_id(0);
2394 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2395 break;
5a8b572d
AT		 2396 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2397 dsidev = dsi_get_dsidev_from_id(1);
2398 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2399 break;
66534e8e
TA		 2400 default:
2401 BUG();
2402 }
2403
80c39712
TV		 2404 return r;
2405}
2406
26d9dd0d 2407unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2408{
a72b64b9 2409 struct platform_device *dsidev;
80c39712
TV		 2410 int lcd;
2411 unsigned long r;
2412 u32 l;
2413
ce7fa5eb 2414 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2415
2416 lcd = FLD_GET(l, 23, 16);
2417
ea75159e 2418 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2419 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2420 r = clk_get_rate(dispc.dss_clk);
ea75159e 2421 break;
89a35e51 2422 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2423 dsidev = dsi_get_dsidev_from_id(0);
2424 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2425 break;
5a8b572d
AT		 2426 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2427 dsidev = dsi_get_dsidev_from_id(1);
2428 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2429 break;
ea75159e
TA		 2430 default:
2431 BUG();
2432 }
80c39712
TV		 2433
2434 return r / lcd;
2435}
2436
26d9dd0d 2437unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2438{
80c39712 2439 unsigned long r;
80c39712 2440
c3dc6a7a
AT		 2441 if (dispc_mgr_is_lcd(channel)) {
2442 int pcd;
2443 u32 l;
80c39712 2444
c3dc6a7a 2445 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2446
c3dc6a7a 2447 pcd = FLD_GET(l, 7, 0);
80c39712 2448
c3dc6a7a
AT		 2449 r = dispc_mgr_lclk_rate(channel);
2450
2451 return r / pcd;
2452 } else {
2453 struct omap_dss_device *dssdev =
2454 dispc_mgr_get_device(channel);
2455
2456 switch (dssdev->type) {
2457 case OMAP_DISPLAY_TYPE_VENC:
2458 return venc_get_pixel_clock();
2459 case OMAP_DISPLAY_TYPE_HDMI:
2460 return hdmi_get_pixel_clock();
2461 default:
2462 BUG();
2463 }
2464 }
80c39712
TV		 2465}
2466
2467void dispc_dump_clocks(struct seq_file *s)
2468{
2469 int lcd, pcd;
0cf35df3 2470 u32 l;
89a35e51
AT		 2471 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2472 enum omap_dss_clk_source lcd_clk_src;
80c39712 2473
4fbafaf3
TV		 2474 if (dispc_runtime_get())
2475 return;
80c39712 2476
80c39712
TV		 2477 seq_printf(s, "- DISPC -\n");
2478
067a57e4
AT		 2479 seq_printf(s, "dispc fclk source = %s (%s)\n",
2480 dss_get_generic_clk_source_name(dispc_clk_src),
2481 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2482
2483 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2484
0cf35df3
MR		 2485 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2486 seq_printf(s, "- DISPC-CORE-CLK -\n");
2487 l = dispc_read_reg(DISPC_DIVISOR);
2488 lcd = FLD_GET(l, 23, 16);
2489
2490 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2491 (dispc_fclk_rate()/lcd), lcd);
2492 }
2a205f34
SS		 2493 seq_printf(s, "- LCD1 -\n");
2494
ea75159e
TA		 2495 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2496
2497 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2498 dss_get_generic_clk_source_name(lcd_clk_src),
2499 dss_feat_get_clk_source_name(lcd_clk_src));
2500
26d9dd0d 2501 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2502
ff1b2cde 2503 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2504 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2505 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2506 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2507 if (dss_has_feature(FEAT_MGR_LCD2)) {
2508 seq_printf(s, "- LCD2 -\n");
2509
ea75159e
TA		 2510 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2511
2512 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2513 dss_get_generic_clk_source_name(lcd_clk_src),
2514 dss_feat_get_clk_source_name(lcd_clk_src));
2515
26d9dd0d 2516 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2517
2a205f34 2518 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2519 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2520 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2521 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2522 }
4fbafaf3
TV		 2523
2524 dispc_runtime_put();
80c39712
TV		 2525}
2526
dfc0fd8d
TV		 2527#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2528void dispc_dump_irqs(struct seq_file *s)
2529{
2530 unsigned long flags;
2531 struct dispc_irq_stats stats;
2532
2533 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2534
2535 stats = dispc.irq_stats;
2536 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2537 dispc.irq_stats.last_reset = jiffies;
2538
2539 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2540
2541 seq_printf(s, "period %u ms\n",
2542 jiffies_to_msecs(jiffies - stats.last_reset));
2543
2544 seq_printf(s, "irqs %d\n", stats.irq_count);
2545#define PIS(x) \
2546 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2547
2548 PIS(FRAMEDONE);
2549 PIS(VSYNC);
2550 PIS(EVSYNC_EVEN);
2551 PIS(EVSYNC_ODD);
2552 PIS(ACBIAS_COUNT_STAT);
2553 PIS(PROG_LINE_NUM);
2554 PIS(GFX_FIFO_UNDERFLOW);
2555 PIS(GFX_END_WIN);
2556 PIS(PAL_GAMMA_MASK);
2557 PIS(OCP_ERR);
2558 PIS(VID1_FIFO_UNDERFLOW);
2559 PIS(VID1_END_WIN);
2560 PIS(VID2_FIFO_UNDERFLOW);
2561 PIS(VID2_END_WIN);
2562 PIS(SYNC_LOST);
2563 PIS(SYNC_LOST_DIGIT);
2564 PIS(WAKEUP);
2a205f34
SS		 2565 if (dss_has_feature(FEAT_MGR_LCD2)) {
2566 PIS(FRAMEDONE2);
2567 PIS(VSYNC2);
2568 PIS(ACBIAS_COUNT_STAT2);
2569 PIS(SYNC_LOST2);
2570 }
dfc0fd8d
TV		 2571#undef PIS
2572}
dfc0fd8d
TV		 2573#endif
2574
80c39712
TV		 2575void dispc_dump_regs(struct seq_file *s)
2576{
4dd2da15
AT		 2577 int i, j;
2578 const char *mgr_names[] = {
2579 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2580 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2581 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2582 };
2583 const char *ovl_names[] = {
2584 [OMAP_DSS_GFX] = "GFX",
2585 [OMAP_DSS_VIDEO1] = "VID1",
2586 [OMAP_DSS_VIDEO2] = "VID2",
2587 };
2588 const char **p_names;
2589
9b372c2d 2590#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2591
4fbafaf3
TV		 2592 if (dispc_runtime_get())
2593 return;
80c39712 2594
5010be80 2595 /* DISPC common registers */
80c39712
TV		 2596 DUMPREG(DISPC_REVISION);
2597 DUMPREG(DISPC_SYSCONFIG);
2598 DUMPREG(DISPC_SYSSTATUS);
2599 DUMPREG(DISPC_IRQSTATUS);
2600 DUMPREG(DISPC_IRQENABLE);
2601 DUMPREG(DISPC_CONTROL);
2602 DUMPREG(DISPC_CONFIG);
2603 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2604 DUMPREG(DISPC_LINE_STATUS);
2605 DUMPREG(DISPC_LINE_NUMBER);
332e9d70
TV		 2606 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2607 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2608 if (dss_has_feature(FEAT_MGR_LCD2)) {
2609 DUMPREG(DISPC_CONTROL2);
2610 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2611 }
2612
2613#undef DUMPREG
2614
2615#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2616#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2617 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2618 dispc_read_reg(DISPC_REG(i, r)))
2619
4dd2da15 2620 p_names = mgr_names;
5010be80 2621
4dd2da15
AT		 2622 /* DISPC channel specific registers */
2623 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2624 DUMPREG(i, DISPC_DEFAULT_COLOR);
2625 DUMPREG(i, DISPC_TRANS_COLOR);
2626 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2627
4dd2da15
AT		 2628 if (i == OMAP_DSS_CHANNEL_DIGIT)
2629 continue;
5010be80 2630
4dd2da15
AT		 2631 DUMPREG(i, DISPC_DEFAULT_COLOR);
2632 DUMPREG(i, DISPC_TRANS_COLOR);
2633 DUMPREG(i, DISPC_TIMING_H);
2634 DUMPREG(i, DISPC_TIMING_V);
2635 DUMPREG(i, DISPC_POL_FREQ);
2636 DUMPREG(i, DISPC_DIVISORo);
2637 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2638
4dd2da15
AT		 2639 DUMPREG(i, DISPC_DATA_CYCLE1);
2640 DUMPREG(i, DISPC_DATA_CYCLE2);
2641 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2642
332e9d70 2643 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2644 DUMPREG(i, DISPC_CPR_COEF_R);
2645 DUMPREG(i, DISPC_CPR_COEF_G);
2646 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2647 }
2a205f34 2648 }
80c39712 2649
4dd2da15
AT		 2650 p_names = ovl_names;
2651
2652 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2653 DUMPREG(i, DISPC_OVL_BA0);
2654 DUMPREG(i, DISPC_OVL_BA1);
2655 DUMPREG(i, DISPC_OVL_POSITION);
2656 DUMPREG(i, DISPC_OVL_SIZE);
2657 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2658 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2659 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2660 DUMPREG(i, DISPC_OVL_ROW_INC);
2661 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2662 if (dss_has_feature(FEAT_PRELOAD))
2663 DUMPREG(i, DISPC_OVL_PRELOAD);
2664
2665 if (i == OMAP_DSS_GFX) {
2666 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2667 DUMPREG(i, DISPC_OVL_TABLE_BA);
2668 continue;
2669 }
2670
2671 DUMPREG(i, DISPC_OVL_FIR);
2672 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2673 DUMPREG(i, DISPC_OVL_ACCU0);
2674 DUMPREG(i, DISPC_OVL_ACCU1);
2675 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2676 DUMPREG(i, DISPC_OVL_BA0_UV);
2677 DUMPREG(i, DISPC_OVL_BA1_UV);
2678 DUMPREG(i, DISPC_OVL_FIR2);
2679 DUMPREG(i, DISPC_OVL_ACCU2_0);
2680 DUMPREG(i, DISPC_OVL_ACCU2_1);
2681 }
2682 if (dss_has_feature(FEAT_ATTR2))
2683 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2684 if (dss_has_feature(FEAT_PRELOAD))
2685 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2686 }
5010be80
AT		 2687
2688#undef DISPC_REG
2689#undef DUMPREG
2690
2691#define DISPC_REG(plane, name, i) name(plane, i)
2692#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2693 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2694 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2695 dispc_read_reg(DISPC_REG(plane, name, i)))
2696
4dd2da15 2697 /* Video pipeline coefficient registers */
332e9d70 2698
4dd2da15
AT		 2699 /* start from OMAP_DSS_VIDEO1 */
2700 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2701 for (j = 0; j < 8; j++)
2702 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2703
4dd2da15
AT		 2704 for (j = 0; j < 8; j++)
2705 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2706
4dd2da15
AT		 2707 for (j = 0; j < 5; j++)
2708 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2709
4dd2da15
AT		 2710 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2711 for (j = 0; j < 8; j++)
2712 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2713 }
2714
2715 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2716 for (j = 0; j < 8; j++)
2717 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2718
2719 for (j = 0; j < 8; j++)
2720 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2721
2722 for (j = 0; j < 8; j++)
2723 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2724 }
332e9d70 2725 }
80c39712 2726
4fbafaf3 2727 dispc_runtime_put();
5010be80
AT		 2728
2729#undef DISPC_REG
80c39712
TV		 2730#undef DUMPREG
2731}
2732
26d9dd0d
TV		 2733static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2734 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2735 u8 acb)
80c39712
TV		 2736{
2737 u32 l = 0;
2738
2739 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2740 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2741
2742 l |= FLD_VAL(onoff, 17, 17);
2743 l |= FLD_VAL(rf, 16, 16);
2744 l |= FLD_VAL(ieo, 15, 15);
2745 l |= FLD_VAL(ipc, 14, 14);
2746 l |= FLD_VAL(ihs, 13, 13);
2747 l |= FLD_VAL(ivs, 12, 12);
2748 l |= FLD_VAL(acbi, 11, 8);
2749 l |= FLD_VAL(acb, 7, 0);
2750
ff1b2cde 2751 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2752}
2753
26d9dd0d 2754void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 2755 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2756{
26d9dd0d 2757 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2758 (config & OMAP_DSS_LCD_RF) != 0,
2759 (config & OMAP_DSS_LCD_IEO) != 0,
2760 (config & OMAP_DSS_LCD_IPC) != 0,
2761 (config & OMAP_DSS_LCD_IHS) != 0,
2762 (config & OMAP_DSS_LCD_IVS) != 0,
2763 acbi, acb);
2764}
2765
2766/* with fck as input clock rate, find dispc dividers that produce req_pck */
2767void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2768 struct dispc_clock_info *cinfo)
2769{
9eaaf207 2770 u16 pcd_min, pcd_max;
80c39712
TV		 2771 unsigned long best_pck;
2772 u16 best_ld, cur_ld;
2773 u16 best_pd, cur_pd;
2774
9eaaf207
TV		 2775 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2776 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2777
2778 if (!is_tft)
2779 pcd_min = 3;
2780
80c39712
TV		 2781 best_pck = 0;
2782 best_ld = 0;
2783 best_pd = 0;
2784
2785 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2786 unsigned long lck = fck / cur_ld;
2787
9eaaf207 2788 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 2789 unsigned long pck = lck / cur_pd;
2790 long old_delta = abs(best_pck - req_pck);
2791 long new_delta = abs(pck - req_pck);
2792
2793 if (best_pck == 0 || new_delta < old_delta) {
2794 best_pck = pck;
2795 best_ld = cur_ld;
2796 best_pd = cur_pd;
2797
2798 if (pck == req_pck)
2799 goto found;
2800 }
2801
2802 if (pck < req_pck)
2803 break;
2804 }
2805
2806 if (lck / pcd_min < req_pck)
2807 break;
2808 }
2809
2810found:
2811 cinfo->lck_div = best_ld;
2812 cinfo->pck_div = best_pd;
2813 cinfo->lck = fck / cinfo->lck_div;
2814 cinfo->pck = cinfo->lck / cinfo->pck_div;
2815}
2816
2817/* calculate clock rates using dividers in cinfo */
2818int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2819 struct dispc_clock_info *cinfo)
2820{
2821 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2822 return -EINVAL;
9eaaf207 2823 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 2824 return -EINVAL;
2825
2826 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2827 cinfo->pck = cinfo->lck / cinfo->pck_div;
2828
2829 return 0;
2830}
2831
26d9dd0d 2832int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 2833 struct dispc_clock_info *cinfo)
80c39712
TV		 2834{
2835 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2836 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2837
26d9dd0d 2838 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2839
2840 return 0;
2841}
2842
26d9dd0d 2843int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 2844 struct dispc_clock_info *cinfo)
80c39712
TV		 2845{
2846 unsigned long fck;
2847
2848 fck = dispc_fclk_rate();
2849
ce7fa5eb
MR		 2850 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2851 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2852
2853 cinfo->lck = fck / cinfo->lck_div;
2854 cinfo->pck = cinfo->lck / cinfo->pck_div;
2855
2856 return 0;
2857}
2858
2859/* dispc.irq_lock has to be locked by the caller */
2860static void _omap_dispc_set_irqs(void)
2861{
2862 u32 mask;
2863 u32 old_mask;
2864 int i;
2865 struct omap_dispc_isr_data *isr_data;
2866
2867 mask = dispc.irq_error_mask;
2868
2869 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2870 isr_data = &dispc.registered_isr[i];
2871
2872 if (isr_data->isr == NULL)
2873 continue;
2874
2875 mask |= isr_data->mask;
2876 }
2877
80c39712
TV		 2878 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2879 /* clear the irqstatus for newly enabled irqs */
2880 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2881
2882 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 2883}
2884
2885int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2886{
2887 int i;
2888 int ret;
2889 unsigned long flags;
2890 struct omap_dispc_isr_data *isr_data;
2891
2892 if (isr == NULL)
2893 return -EINVAL;
2894
2895 spin_lock_irqsave(&dispc.irq_lock, flags);
2896
2897 /* check for duplicate entry */
2898 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2899 isr_data = &dispc.registered_isr[i];
2900 if (isr_data->isr == isr && isr_data->arg == arg &&
2901 isr_data->mask == mask) {
2902 ret = -EINVAL;
2903 goto err;
2904 }
2905 }
2906
2907 isr_data = NULL;
2908 ret = -EBUSY;
2909
2910 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2911 isr_data = &dispc.registered_isr[i];
2912
2913 if (isr_data->isr != NULL)
2914 continue;
2915
2916 isr_data->isr = isr;
2917 isr_data->arg = arg;
2918 isr_data->mask = mask;
2919 ret = 0;
2920
2921 break;
2922 }
2923
b9cb0984
TV		 2924 if (ret)
2925 goto err;
2926
80c39712
TV		 2927 _omap_dispc_set_irqs();
2928
2929 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2930
2931 return 0;
2932err:
2933 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2934
2935 return ret;
2936}
2937EXPORT_SYMBOL(omap_dispc_register_isr);
2938
2939int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2940{
2941 int i;
2942 unsigned long flags;
2943 int ret = -EINVAL;
2944 struct omap_dispc_isr_data *isr_data;
2945
2946 spin_lock_irqsave(&dispc.irq_lock, flags);
2947
2948 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2949 isr_data = &dispc.registered_isr[i];
2950 if (isr_data->isr != isr || isr_data->arg != arg ||
2951 isr_data->mask != mask)
2952 continue;
2953
2954 /* found the correct isr */
2955
2956 isr_data->isr = NULL;
2957 isr_data->arg = NULL;
2958 isr_data->mask = 0;
2959
2960 ret = 0;
2961 break;
2962 }
2963
2964 if (ret == 0)
2965 _omap_dispc_set_irqs();
2966
2967 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2968
2969 return ret;
2970}
2971EXPORT_SYMBOL(omap_dispc_unregister_isr);
2972
2973#ifdef DEBUG
2974static void print_irq_status(u32 status)
2975{
2976 if ((status & dispc.irq_error_mask) == 0)
2977 return;
2978
2979 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2980
2981#define PIS(x) \
2982 if (status & DISPC_IRQ_##x) \
2983 printk(#x " ");
2984 PIS(GFX_FIFO_UNDERFLOW);
2985 PIS(OCP_ERR);
2986 PIS(VID1_FIFO_UNDERFLOW);
2987 PIS(VID2_FIFO_UNDERFLOW);
2988 PIS(SYNC_LOST);
2989 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 2990 if (dss_has_feature(FEAT_MGR_LCD2))
2991 PIS(SYNC_LOST2);
80c39712
TV		 2992#undef PIS
2993
2994 printk("\n");
2995}
2996#endif
2997
2998/* Called from dss.c. Note that we don't touch clocks here,
2999 * but we presume they are on because we got an IRQ. However,
3000 * an irq handler may turn the clocks off, so we may not have
3001 * clock later in the function. */
affe360d 3002static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3003{
3004 int i;
affe360d 3005 u32 irqstatus, irqenable;
80c39712
TV		 3006 u32 handledirqs = 0;
3007 u32 unhandled_errors;
3008 struct omap_dispc_isr_data *isr_data;
3009 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3010
3011 spin_lock(&dispc.irq_lock);
3012
3013 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3014 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3015
3016 /* IRQ is not for us */
3017 if (!(irqstatus & irqenable)) {
3018 spin_unlock(&dispc.irq_lock);
3019 return IRQ_NONE;
3020 }
80c39712 3021
dfc0fd8d
TV		 3022#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3023 spin_lock(&dispc.irq_stats_lock);
3024 dispc.irq_stats.irq_count++;
3025 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3026 spin_unlock(&dispc.irq_stats_lock);
3027#endif
3028
80c39712
TV		 3029#ifdef DEBUG
3030 if (dss_debug)
3031 print_irq_status(irqstatus);
3032#endif
3033 /* Ack the interrupt. Do it here before clocks are possibly turned
3034 * off */
3035 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3036 /* flush posted write */
3037 dispc_read_reg(DISPC_IRQSTATUS);
3038
3039 /* make a copy and unlock, so that isrs can unregister
3040 * themselves */
3041 memcpy(registered_isr, dispc.registered_isr,
3042 sizeof(registered_isr));
3043
3044 spin_unlock(&dispc.irq_lock);
3045
3046 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3047 isr_data = &registered_isr[i];
3048
3049 if (!isr_data->isr)
3050 continue;
3051
3052 if (isr_data->mask & irqstatus) {
3053 isr_data->isr(isr_data->arg, irqstatus);
3054 handledirqs |= isr_data->mask;
3055 }
3056 }
3057
3058 spin_lock(&dispc.irq_lock);
3059
3060 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3061
3062 if (unhandled_errors) {
3063 dispc.error_irqs |= unhandled_errors;
3064
3065 dispc.irq_error_mask &= ~unhandled_errors;
3066 _omap_dispc_set_irqs();
3067
3068 schedule_work(&dispc.error_work);
3069 }
3070
3071 spin_unlock(&dispc.irq_lock);
affe360d 3072
3073 return IRQ_HANDLED;
80c39712
TV		 3074}
3075
3076static void dispc_error_worker(struct work_struct *work)
3077{
3078 int i;
3079 u32 errors;
3080 unsigned long flags;
fe3cc9d6
TV		 3081 static const unsigned fifo_underflow_bits[] = {
3082 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3083 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3084 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3085 };
3086
3087 static const unsigned sync_lost_bits[] = {
3088 DISPC_IRQ_SYNC_LOST,
3089 DISPC_IRQ_SYNC_LOST_DIGIT,
3090 DISPC_IRQ_SYNC_LOST2,
3091 };
80c39712
TV		 3092
3093 spin_lock_irqsave(&dispc.irq_lock, flags);
3094 errors = dispc.error_irqs;
3095 dispc.error_irqs = 0;
3096 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3097
13eae1f9
DZ		 3098 dispc_runtime_get();
3099
fe3cc9d6
TV		 3100 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3101 struct omap_overlay *ovl;
3102 unsigned bit;
80c39712 3103
fe3cc9d6
TV		 3104 ovl = omap_dss_get_overlay(i);
3105 bit = fifo_underflow_bits[i];
80c39712 3106
fe3cc9d6
TV		 3107 if (bit & errors) {
3108 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3109 ovl->name);
f0e5caab 3110 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3111 dispc_mgr_go(ovl->manager->id);
80c39712 3112 mdelay(50);
80c39712
TV		 3113 }
3114 }
3115
fe3cc9d6
TV		 3116 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3117 struct omap_overlay_manager *mgr;
3118 unsigned bit;
80c39712 3119
fe3cc9d6
TV		 3120 mgr = omap_dss_get_overlay_manager(i);
3121 bit = sync_lost_bits[i];
80c39712 3122
fe3cc9d6
TV		 3123 if (bit & errors) {
3124 struct omap_dss_device *dssdev = mgr->device;
3125 bool enable;
80c39712 3126
fe3cc9d6
TV		 3127 DSSERR("SYNC_LOST on channel %s, restarting the output "
3128 "with video overlays disabled\n",
3129 mgr->name);
2a205f34 3130
fe3cc9d6
TV		 3131 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3132 dssdev->driver->disable(dssdev);
2a205f34 3133
2a205f34
SS		 3134 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3135 struct omap_overlay *ovl;
3136 ovl = omap_dss_get_overlay(i);
3137
fe3cc9d6
TV		 3138 if (ovl->id != OMAP_DSS_GFX &&
3139 ovl->manager == mgr)
f0e5caab 3140 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3141 }
3142
26d9dd0d 3143 dispc_mgr_go(mgr->id);
2a205f34 3144 mdelay(50);
fe3cc9d6 3145
2a205f34
SS		 3146 if (enable)
3147 dssdev->driver->enable(dssdev);
3148 }
3149 }
3150
80c39712
TV		 3151 if (errors & DISPC_IRQ_OCP_ERR) {
3152 DSSERR("OCP_ERR\n");
3153 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3154 struct omap_overlay_manager *mgr;
3155 mgr = omap_dss_get_overlay_manager(i);
4a9e78ab 3156 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3157 }
3158 }
3159
3160 spin_lock_irqsave(&dispc.irq_lock, flags);
3161 dispc.irq_error_mask |= errors;
3162 _omap_dispc_set_irqs();
3163 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3164
3165 dispc_runtime_put();
80c39712
TV		 3166}
3167
3168int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3169{
3170 void dispc_irq_wait_handler(void *data, u32 mask)
3171 {
3172 complete((struct completion *)data);
3173 }
3174
3175 int r;
3176 DECLARE_COMPLETION_ONSTACK(completion);
3177
3178 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3179 irqmask);
3180
3181 if (r)
3182 return r;
3183
3184 timeout = wait_for_completion_timeout(&completion, timeout);
3185
3186 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3187
3188 if (timeout == 0)
3189 return -ETIMEDOUT;
3190
3191 if (timeout == -ERESTARTSYS)
3192 return -ERESTARTSYS;
3193
3194 return 0;
3195}
3196
3197int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3198 unsigned long timeout)
3199{
3200 void dispc_irq_wait_handler(void *data, u32 mask)
3201 {
3202 complete((struct completion *)data);
3203 }
3204
3205 int r;
3206 DECLARE_COMPLETION_ONSTACK(completion);
3207
3208 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3209 irqmask);
3210
3211 if (r)
3212 return r;
3213
3214 timeout = wait_for_completion_interruptible_timeout(&completion,
3215 timeout);
3216
3217 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3218
3219 if (timeout == 0)
3220 return -ETIMEDOUT;
3221
3222 if (timeout == -ERESTARTSYS)
3223 return -ERESTARTSYS;
3224
3225 return 0;
3226}
3227
3228#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3229void dispc_fake_vsync_irq(void)
3230{
3231 u32 irqstatus = DISPC_IRQ_VSYNC;
3232 int i;
3233
ab83b14c 3234 WARN_ON(!in_interrupt());
80c39712
TV		 3235
3236 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3237 struct omap_dispc_isr_data *isr_data;
3238 isr_data = &dispc.registered_isr[i];
3239
3240 if (!isr_data->isr)
3241 continue;
3242
3243 if (isr_data->mask & irqstatus)
3244 isr_data->isr(isr_data->arg, irqstatus);
3245 }
80c39712
TV		 3246}
3247#endif
3248
3249static void _omap_dispc_initialize_irq(void)
3250{
3251 unsigned long flags;
3252
3253 spin_lock_irqsave(&dispc.irq_lock, flags);
3254
3255 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3256
3257 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3258 if (dss_has_feature(FEAT_MGR_LCD2))
3259 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3260
3261 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3262 * so clear it */
3263 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3264
3265 _omap_dispc_set_irqs();
3266
3267 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3268}
3269
3270void dispc_enable_sidle(void)
3271{
3272 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3273}
3274
3275void dispc_disable_sidle(void)
3276{
3277 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3278}
3279
3280static void _omap_dispc_initial_config(void)
3281{
3282 u32 l;
3283
0cf35df3
MR		 3284 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3285 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3286 l = dispc_read_reg(DISPC_DIVISOR);
3287 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3288 l = FLD_MOD(l, 1, 0, 0);
3289 l = FLD_MOD(l, 1, 23, 16);
3290 dispc_write_reg(DISPC_DIVISOR, l);
3291 }
3292
80c39712 3293 /* FUNCGATED */
6ced40bf
AT		 3294 if (dss_has_feature(FEAT_FUNCGATED))
3295 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3296
3297 /* L3 firewall setting: enable access to OCM RAM */
3298 /* XXX this should be somewhere in plat-omap */
3299 if (cpu_is_omap24xx())
3300 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3301
3302 _dispc_setup_color_conv_coef();
3303
3304 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3305
3306 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3307
3308 dispc_configure_burst_sizes();
80c39712
TV		 3309}
3310
060b6d9c
SG		 3311/* DISPC HW IP initialisation */
3312static int omap_dispchw_probe(struct platform_device *pdev)
3313{
3314 u32 rev;
affe360d 3315 int r = 0;
ea9da36a 3316 struct resource *dispc_mem;
4fbafaf3 3317 struct clk *clk;
ea9da36a 3318
060b6d9c
SG		 3319 dispc.pdev = pdev;
3320
4fbafaf3
TV		 3321 clk = clk_get(&pdev->dev, "fck");
3322 if (IS_ERR(clk)) {
3323 DSSERR("can't get fck\n");
3324 r = PTR_ERR(clk);
3325 goto err_get_clk;
3326 }
3327
3328 dispc.dss_clk = clk;
3329
060b6d9c
SG		 3330 spin_lock_init(&dispc.irq_lock);
3331
3332#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3333 spin_lock_init(&dispc.irq_stats_lock);
3334 dispc.irq_stats.last_reset = jiffies;
3335#endif
3336
3337 INIT_WORK(&dispc.error_work, dispc_error_worker);
3338
ea9da36a
SG		 3339 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3340 if (!dispc_mem) {
3341 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3342 r = -EINVAL;
4fbafaf3 3343 goto err_ioremap;
ea9da36a
SG		 3344 }
3345 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3346 if (!dispc.base) {
3347 DSSERR("can't ioremap DISPC\n");
affe360d 3348 r = -ENOMEM;
4fbafaf3 3349 goto err_ioremap;
affe360d 3350 }
3351 dispc.irq = platform_get_irq(dispc.pdev, 0);
3352 if (dispc.irq < 0) {
3353 DSSERR("platform_get_irq failed\n");
3354 r = -ENODEV;
4fbafaf3 3355 goto err_irq;
affe360d 3356 }
3357
3358 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3359 "OMAP DISPC", dispc.pdev);
3360 if (r < 0) {
3361 DSSERR("request_irq failed\n");
4fbafaf3 3362 goto err_irq;
060b6d9c
SG		 3363 }
3364
4fbafaf3
TV		 3365 pm_runtime_enable(&pdev->dev);
3366
3367 r = dispc_runtime_get();
3368 if (r)
3369 goto err_runtime_get;
060b6d9c
SG		 3370
3371 _omap_dispc_initial_config();
3372
3373 _omap_dispc_initialize_irq();
3374
060b6d9c 3375 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3376 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3377 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3378
4fbafaf3 3379 dispc_runtime_put();
060b6d9c
SG		 3380
3381 return 0;
4fbafaf3
TV		 3382
3383err_runtime_get:
3384 pm_runtime_disable(&pdev->dev);
3385 free_irq(dispc.irq, dispc.pdev);
3386err_irq:
affe360d 3387 iounmap(dispc.base);
4fbafaf3
TV		 3388err_ioremap:
3389 clk_put(dispc.dss_clk);
3390err_get_clk:
affe360d 3391 return r;
060b6d9c
SG		 3392}
3393
3394static int omap_dispchw_remove(struct platform_device *pdev)
3395{
4fbafaf3
TV		 3396 pm_runtime_disable(&pdev->dev);
3397
3398 clk_put(dispc.dss_clk);
3399
affe360d 3400 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3401 iounmap(dispc.base);
3402 return 0;
3403}
3404
4fbafaf3
TV		 3405static int dispc_runtime_suspend(struct device *dev)
3406{
3407 dispc_save_context();
4fbafaf3
TV		 3408 dss_runtime_put();
3409
3410 return 0;
3411}
3412
3413static int dispc_runtime_resume(struct device *dev)
3414{
3415 int r;
3416
3417 r = dss_runtime_get();
3418 if (r < 0)
3419 return r;
3420
49ea86f3 3421 dispc_restore_context();
4fbafaf3
TV		 3422
3423 return 0;
3424}
3425
3426static const struct dev_pm_ops dispc_pm_ops = {
3427 .runtime_suspend = dispc_runtime_suspend,
3428 .runtime_resume = dispc_runtime_resume,
3429};
3430
060b6d9c
SG		 3431static struct platform_driver omap_dispchw_driver = {
3432 .probe = omap_dispchw_probe,
3433 .remove = omap_dispchw_remove,
3434 .driver = {
3435 .name = "omapdss_dispc",
3436 .owner = THIS_MODULE,
4fbafaf3 3437 .pm = &dispc_pm_ops,
060b6d9c
SG		 3438 },
3439};
3440
3441int dispc_init_platform_driver(void)
3442{
3443 return platform_driver_register(&omap_dispchw_driver);
3444}
3445
3446void dispc_uninit_platform_driver(void)
3447{
3448 return platform_driver_unregister(&omap_dispchw_driver);
3449}
Linux kernel - Deliverables
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