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OMAP: DSS2: Remove ctx loss count from dss.c
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
80c39712
TV		 38
39#include <plat/sram.h>
40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
66be8f6c
GI		 66struct dispc_h_coef {
67 s8 hc4;
68 s8 hc3;
69 u8 hc2;
70 s8 hc1;
71 s8 hc0;
72};
73
74struct dispc_v_coef {
75 s8 vc22;
76 s8 vc2;
77 u8 vc1;
78 s8 vc0;
79 s8 vc00;
80};
81
5ed8cf5b
TV		 82enum omap_burst_size {
83 BURST_SIZE_X2 = 0,
84 BURST_SIZE_X4 = 1,
85 BURST_SIZE_X8 = 2,
86};
87
80c39712
TV		 88#define REG_GET(idx, start, end) \
89 FLD_GET(dispc_read_reg(idx), start, end)
90
91#define REG_FLD_MOD(idx, val, start, end) \
92 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
93
dfc0fd8d
TV		 94struct dispc_irq_stats {
95 unsigned long last_reset;
96 unsigned irq_count;
97 unsigned irqs[32];
98};
99
80c39712 100static struct {
060b6d9c 101 struct platform_device *pdev;
80c39712 102 void __iomem *base;
4fbafaf3
TV		 103
104 int ctx_loss_cnt;
105
affe360d 106 int irq;
4fbafaf3 107 struct clk *dss_clk;
80c39712
TV		 108
109 u32 fifo_size[3];
110
111 spinlock_t irq_lock;
112 u32 irq_error_mask;
113 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
114 u32 error_irqs;
115 struct work_struct error_work;
116
117 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 118
119#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
120 spinlock_t irq_stats_lock;
121 struct dispc_irq_stats irq_stats;
122#endif
80c39712
TV		 123} dispc;
124
0d66cbb5
AJ		 125enum omap_color_component {
126 /* used for all color formats for OMAP3 and earlier
127 * and for RGB and Y color component on OMAP4
128 */
129 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
130 /* used for UV component for
131 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
132 * color formats on OMAP4
133 */
134 DISPC_COLOR_COMPONENT_UV = 1 << 1,
135};
136
80c39712
TV		 137static void _omap_dispc_set_irqs(void);
138
55978cc2 139static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 140{
55978cc2 141 __raw_writel(val, dispc.base + idx);
80c39712
TV		 142}
143
55978cc2 144static inline u32 dispc_read_reg(const u16 idx)
80c39712 145{
55978cc2 146 return __raw_readl(dispc.base + idx);
80c39712
TV		 147}
148
149#define SR(reg) \
55978cc2 150 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 151#define RR(reg) \
55978cc2 152 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 153
4fbafaf3 154static void dispc_save_context(void)
80c39712 155{
5719d35c 156 int i;
80c39712 157
4fbafaf3
TV		 158 DSSDBG("dispc_save_context\n");
159
80c39712
TV		 160 SR(IRQENABLE);
161 SR(CONTROL);
162 SR(CONFIG);
702d1448
AT		 163 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
164 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
165 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
166 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712 167 SR(LINE_NUMBER);
702d1448
AT		 168 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
169 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
170 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
171 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
332e9d70
TV		 172 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
173 SR(GLOBAL_ALPHA);
702d1448
AT		 174 SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
175 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34
SS		 176 if (dss_has_feature(FEAT_MGR_LCD2)) {
177 SR(CONTROL2);
702d1448
AT		 178 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
179 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
180 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
181 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
182 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
183 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
184 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2a205f34
SS		 185 SR(CONFIG2);
186 }
80c39712 187
9b372c2d
AT		 188 SR(OVL_BA0(OMAP_DSS_GFX));
189 SR(OVL_BA1(OMAP_DSS_GFX));
190 SR(OVL_POSITION(OMAP_DSS_GFX));
191 SR(OVL_SIZE(OMAP_DSS_GFX));
192 SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
193 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
194 SR(OVL_ROW_INC(OMAP_DSS_GFX));
195 SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
196 SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
197 SR(OVL_TABLE_BA(OMAP_DSS_GFX));
80c39712 198
702d1448
AT		 199 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
200 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
201 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 202
332e9d70
TV		 203 if (dss_has_feature(FEAT_CPR)) {
204 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
205 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
206 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
207 }
2a205f34 208 if (dss_has_feature(FEAT_MGR_LCD2)) {
332e9d70
TV		 209 if (dss_has_feature(FEAT_CPR)) {
210 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
211 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
212 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
213 }
2a205f34 214
702d1448
AT		 215 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
216 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
217 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 218 }
80c39712 219
332e9d70
TV		 220 if (dss_has_feature(FEAT_PRELOAD))
221 SR(OVL_PRELOAD(OMAP_DSS_GFX));
80c39712
TV		 222
223 /* VID1 */
9b372c2d
AT		 224 SR(OVL_BA0(OMAP_DSS_VIDEO1));
225 SR(OVL_BA1(OMAP_DSS_VIDEO1));
226 SR(OVL_POSITION(OMAP_DSS_VIDEO1));
227 SR(OVL_SIZE(OMAP_DSS_VIDEO1));
228 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
229 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
230 SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
231 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
232 SR(OVL_FIR(OMAP_DSS_VIDEO1));
233 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
234 SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
235 SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
236
5719d35c
AJ		 237 for (i = 0; i < 8; i++)
238 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
239
240 for (i = 0; i < 8; i++)
241 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
242
243 for (i = 0; i < 5; i++)
244 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
245
332e9d70
TV		 246 if (dss_has_feature(FEAT_FIR_COEF_V)) {
247 for (i = 0; i < 8; i++)
248 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
249 }
9b372c2d 250
ab5ca071
AJ		 251 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
252 SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
253 SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
254 SR(OVL_FIR2(OMAP_DSS_VIDEO1));
255 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
256 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
257
258 for (i = 0; i < 8; i++)
259 SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
260
261 for (i = 0; i < 8; i++)
262 SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
263
264 for (i = 0; i < 8; i++)
265 SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
266 }
267 if (dss_has_feature(FEAT_ATTR2))
268 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
269
332e9d70
TV		 270 if (dss_has_feature(FEAT_PRELOAD))
271 SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
80c39712
TV		 272
273 /* VID2 */
9b372c2d
AT		 274 SR(OVL_BA0(OMAP_DSS_VIDEO2));
275 SR(OVL_BA1(OMAP_DSS_VIDEO2));
276 SR(OVL_POSITION(OMAP_DSS_VIDEO2));
277 SR(OVL_SIZE(OMAP_DSS_VIDEO2));
278 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
279 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
280 SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
281 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
282 SR(OVL_FIR(OMAP_DSS_VIDEO2));
283 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
284 SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
285 SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
286
5719d35c
AJ		 287 for (i = 0; i < 8; i++)
288 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
289
290 for (i = 0; i < 8; i++)
291 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
292
293 for (i = 0; i < 5; i++)
294 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
295
332e9d70
TV		 296 if (dss_has_feature(FEAT_FIR_COEF_V)) {
297 for (i = 0; i < 8; i++)
298 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
299 }
9b372c2d 300
ab5ca071
AJ		 301 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
302 SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
303 SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
304 SR(OVL_FIR2(OMAP_DSS_VIDEO2));
305 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
306 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
307
308 for (i = 0; i < 8; i++)
309 SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
310
311 for (i = 0; i < 8; i++)
312 SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
313
314 for (i = 0; i < 8; i++)
315 SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
316 }
317 if (dss_has_feature(FEAT_ATTR2))
318 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
319
332e9d70
TV		 320 if (dss_has_feature(FEAT_PRELOAD))
321 SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
0cf35df3
MR		 322
323 if (dss_has_feature(FEAT_CORE_CLK_DIV))
324 SR(DIVISOR);
80c39712
TV		 325}
326
4fbafaf3 327static void dispc_restore_context(void)
80c39712 328{
5719d35c 329 int i;
4fbafaf3
TV		 330
331 DSSDBG("dispc_restore_context\n");
332
75c7d59d 333 /*RR(IRQENABLE);*/
80c39712
TV		 334 /*RR(CONTROL);*/
335 RR(CONFIG);
702d1448
AT		 336 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
337 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
338 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
339 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712 340 RR(LINE_NUMBER);
702d1448
AT		 341 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
342 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
343 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
344 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
332e9d70
TV		 345 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
346 RR(GLOBAL_ALPHA);
702d1448
AT		 347 RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
348 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34 349 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 350 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
351 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
352 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
353 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
354 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
355 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
356 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2a205f34
SS		 357 RR(CONFIG2);
358 }
80c39712 359
9b372c2d
AT		 360 RR(OVL_BA0(OMAP_DSS_GFX));
361 RR(OVL_BA1(OMAP_DSS_GFX));
362 RR(OVL_POSITION(OMAP_DSS_GFX));
363 RR(OVL_SIZE(OMAP_DSS_GFX));
364 RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
365 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
366 RR(OVL_ROW_INC(OMAP_DSS_GFX));
367 RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
368 RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
369 RR(OVL_TABLE_BA(OMAP_DSS_GFX));
370
80c39712 371
702d1448
AT		 372 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
373 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
374 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 375
332e9d70
TV		 376 if (dss_has_feature(FEAT_CPR)) {
377 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
378 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
379 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
380 }
2a205f34 381 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 382 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
383 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
384 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 385
332e9d70
TV		 386 if (dss_has_feature(FEAT_CPR)) {
387 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
388 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
389 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
390 }
2a205f34 391 }
80c39712 392
332e9d70
TV		 393 if (dss_has_feature(FEAT_PRELOAD))
394 RR(OVL_PRELOAD(OMAP_DSS_GFX));
80c39712
TV		 395
396 /* VID1 */
9b372c2d
AT		 397 RR(OVL_BA0(OMAP_DSS_VIDEO1));
398 RR(OVL_BA1(OMAP_DSS_VIDEO1));
399 RR(OVL_POSITION(OMAP_DSS_VIDEO1));
400 RR(OVL_SIZE(OMAP_DSS_VIDEO1));
401 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
402 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
403 RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
404 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
405 RR(OVL_FIR(OMAP_DSS_VIDEO1));
406 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
407 RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
408 RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
409
5719d35c
AJ		 410 for (i = 0; i < 8; i++)
411 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
412
413 for (i = 0; i < 8; i++)
414 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
415
416 for (i = 0; i < 5; i++)
417 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
418
332e9d70
TV		 419 if (dss_has_feature(FEAT_FIR_COEF_V)) {
420 for (i = 0; i < 8; i++)
421 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
422 }
9b372c2d 423
ab5ca071
AJ		 424 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
425 RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
426 RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
427 RR(OVL_FIR2(OMAP_DSS_VIDEO1));
428 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
429 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
430
431 for (i = 0; i < 8; i++)
432 RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
433
434 for (i = 0; i < 8; i++)
435 RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
436
437 for (i = 0; i < 8; i++)
438 RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
439 }
440 if (dss_has_feature(FEAT_ATTR2))
441 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
442
332e9d70
TV		 443 if (dss_has_feature(FEAT_PRELOAD))
444 RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
80c39712
TV		 445
446 /* VID2 */
9b372c2d
AT		 447 RR(OVL_BA0(OMAP_DSS_VIDEO2));
448 RR(OVL_BA1(OMAP_DSS_VIDEO2));
449 RR(OVL_POSITION(OMAP_DSS_VIDEO2));
450 RR(OVL_SIZE(OMAP_DSS_VIDEO2));
451 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
452 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
453 RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
454 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
455 RR(OVL_FIR(OMAP_DSS_VIDEO2));
456 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
457 RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
458 RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
459
5719d35c
AJ		 460 for (i = 0; i < 8; i++)
461 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
462
463 for (i = 0; i < 8; i++)
464 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
465
466 for (i = 0; i < 5; i++)
467 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
468
332e9d70
TV		 469 if (dss_has_feature(FEAT_FIR_COEF_V)) {
470 for (i = 0; i < 8; i++)
471 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
472 }
9b372c2d 473
ab5ca071
AJ		 474 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
475 RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
476 RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
477 RR(OVL_FIR2(OMAP_DSS_VIDEO2));
478 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
479 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
480
481 for (i = 0; i < 8; i++)
482 RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
483
484 for (i = 0; i < 8; i++)
485 RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
486
487 for (i = 0; i < 8; i++)
488 RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
489 }
490 if (dss_has_feature(FEAT_ATTR2))
491 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
492
332e9d70
TV		 493 if (dss_has_feature(FEAT_PRELOAD))
494 RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
80c39712 495
0cf35df3
MR		 496 if (dss_has_feature(FEAT_CORE_CLK_DIV))
497 RR(DIVISOR);
498
80c39712
TV		 499 /* enable last, because LCD & DIGIT enable are here */
500 RR(CONTROL);
2a205f34
SS		 501 if (dss_has_feature(FEAT_MGR_LCD2))
502 RR(CONTROL2);
75c7d59d
VS		 503 /* clear spurious SYNC_LOST_DIGIT interrupts */
504 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
505
506 /*
507 * enable last so IRQs won't trigger before
508 * the context is fully restored
509 */
510 RR(IRQENABLE);
80c39712
TV		 511}
512
513#undef SR
514#undef RR
515
4fbafaf3 516static void dispc_init_ctx_loss_count(void)
80c39712 517{
4fbafaf3
TV		 518 struct device *dev = &dispc.pdev->dev;
519 struct omap_display_platform_data *pdata = dev->platform_data;
520 struct omap_dss_board_info *board_data = pdata->board_data;
521 int cnt = 0;
522
523 /*
524 * get_context_loss_count returns negative on error. We'll ignore the
525 * error and store the error to ctx_loss_cnt, which will cause
526 * dispc_need_ctx_restore() call to return true.
527 */
528
529 if (board_data->get_context_loss_count)
530 cnt = board_data->get_context_loss_count(dev);
531
532 WARN_ON(cnt < 0);
533
534 dispc.ctx_loss_cnt = cnt;
535
536 DSSDBG("initial ctx_loss_cnt %u\n", cnt);
537}
538
539static bool dispc_need_ctx_restore(void)
540{
541 struct device *dev = &dispc.pdev->dev;
542 struct omap_display_platform_data *pdata = dev->platform_data;
543 struct omap_dss_board_info *board_data = pdata->board_data;
544 int cnt;
545
546 /*
547 * If get_context_loss_count is not available, assume that we need
548 * context restore always.
549 */
550 if (!board_data->get_context_loss_count)
551 return true;
552
553 cnt = board_data->get_context_loss_count(dev);
554 if (cnt < 0) {
555 dev_err(dev, "getting context loss count failed, will force "
556 "context restore\n");
557 dispc.ctx_loss_cnt = cnt;
558 return true;
559 }
560
561 if (cnt == dispc.ctx_loss_cnt)
562 return false;
563
564 DSSDBG("ctx_loss_cnt %d -> %d\n", dispc.ctx_loss_cnt, cnt);
565 dispc.ctx_loss_cnt = cnt;
566
567 return true;
568}
569
570int dispc_runtime_get(void)
571{
572 int r;
573
574 DSSDBG("dispc_runtime_get\n");
575
576 r = pm_runtime_get_sync(&dispc.pdev->dev);
577 WARN_ON(r < 0);
578 return r < 0 ? r : 0;
579}
580
581void dispc_runtime_put(void)
582{
583 int r;
584
585 DSSDBG("dispc_runtime_put\n");
586
587 r = pm_runtime_put(&dispc.pdev->dev);
588 WARN_ON(r < 0);
80c39712
TV		 589}
590
4fbafaf3 591
80c39712
TV		 592bool dispc_go_busy(enum omap_channel channel)
593{
594 int bit;
595
2a205f34
SS		 596 if (channel == OMAP_DSS_CHANNEL_LCD ||
597 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 598 bit = 5; /* GOLCD */
599 else
600 bit = 6; /* GODIGIT */
601
2a205f34
SS		 602 if (channel == OMAP_DSS_CHANNEL_LCD2)
603 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
604 else
605 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 606}
607
608void dispc_go(enum omap_channel channel)
609{
610 int bit;
2a205f34 611 bool enable_bit, go_bit;
80c39712 612
2a205f34
SS		 613 if (channel == OMAP_DSS_CHANNEL_LCD ||
614 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 615 bit = 0; /* LCDENABLE */
616 else
617 bit = 1; /* DIGITALENABLE */
618
619 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 620 if (channel == OMAP_DSS_CHANNEL_LCD2)
621 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
622 else
623 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
624
625 if (!enable_bit)
e6d80f95 626 return;
80c39712 627
2a205f34
SS		 628 if (channel == OMAP_DSS_CHANNEL_LCD ||
629 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 630 bit = 5; /* GOLCD */
631 else
632 bit = 6; /* GODIGIT */
633
2a205f34
SS		 634 if (channel == OMAP_DSS_CHANNEL_LCD2)
635 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
636 else
637 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
638
639 if (go_bit) {
80c39712 640 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 641 return;
80c39712
TV		 642 }
643
2a205f34
SS		 644 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
645 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 646
2a205f34
SS		 647 if (channel == OMAP_DSS_CHANNEL_LCD2)
648 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
649 else
650 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 651}
652
653static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
654{
9b372c2d 655 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 656}
657
658static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
659{
9b372c2d 660 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 661}
662
663static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
664{
9b372c2d 665 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 666}
667
ab5ca071
AJ		 668static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
669{
670 BUG_ON(plane == OMAP_DSS_GFX);
671
672 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
673}
674
675static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
676{
677 BUG_ON(plane == OMAP_DSS_GFX);
678
679 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
680}
681
682static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
683{
684 BUG_ON(plane == OMAP_DSS_GFX);
685
686 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
687}
688
80c39712 689static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
0d66cbb5
AJ		 690 int vscaleup, int five_taps,
691 enum omap_color_component color_comp)
80c39712
TV		 692{
693 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 694 static const struct dispc_h_coef coef_hup[8] = {
695 { 0, 0, 128, 0, 0 },
696 { -1, 13, 124, -8, 0 },
697 { -2, 30, 112, -11, -1 },
698 { -5, 51, 95, -11, -2 },
699 { 0, -9, 73, 73, -9 },
700 { -2, -11, 95, 51, -5 },
701 { -1, -11, 112, 30, -2 },
702 { 0, -8, 124, 13, -1 },
80c39712
TV		 703 };
704
66be8f6c
GI		 705 /* Coefficients for vertical up-sampling */
706 static const struct dispc_v_coef coef_vup_3tap[8] = {
707 { 0, 0, 128, 0, 0 },
708 { 0, 3, 123, 2, 0 },
709 { 0, 12, 111, 5, 0 },
710 { 0, 32, 89, 7, 0 },
711 { 0, 0, 64, 64, 0 },
712 { 0, 7, 89, 32, 0 },
713 { 0, 5, 111, 12, 0 },
714 { 0, 2, 123, 3, 0 },
80c39712
TV		 715 };
716
66be8f6c
GI		 717 static const struct dispc_v_coef coef_vup_5tap[8] = {
718 { 0, 0, 128, 0, 0 },
719 { -1, 13, 124, -8, 0 },
720 { -2, 30, 112, -11, -1 },
721 { -5, 51, 95, -11, -2 },
722 { 0, -9, 73, 73, -9 },
723 { -2, -11, 95, 51, -5 },
724 { -1, -11, 112, 30, -2 },
725 { 0, -8, 124, 13, -1 },
80c39712
TV		 726 };
727
66be8f6c
GI		 728 /* Coefficients for horizontal down-sampling */
729 static const struct dispc_h_coef coef_hdown[8] = {
730 { 0, 36, 56, 36, 0 },
731 { 4, 40, 55, 31, -2 },
732 { 8, 44, 54, 27, -5 },
733 { 12, 48, 53, 22, -7 },
734 { -9, 17, 52, 51, 17 },
735 { -7, 22, 53, 48, 12 },
736 { -5, 27, 54, 44, 8 },
737 { -2, 31, 55, 40, 4 },
80c39712
TV		 738 };
739
66be8f6c
GI		 740 /* Coefficients for vertical down-sampling */
741 static const struct dispc_v_coef coef_vdown_3tap[8] = {
742 { 0, 36, 56, 36, 0 },
743 { 0, 40, 57, 31, 0 },
744 { 0, 45, 56, 27, 0 },
745 { 0, 50, 55, 23, 0 },
746 { 0, 18, 55, 55, 0 },
747 { 0, 23, 55, 50, 0 },
748 { 0, 27, 56, 45, 0 },
749 { 0, 31, 57, 40, 0 },
80c39712
TV		 750 };
751
66be8f6c
GI		 752 static const struct dispc_v_coef coef_vdown_5tap[8] = {
753 { 0, 36, 56, 36, 0 },
754 { 4, 40, 55, 31, -2 },
755 { 8, 44, 54, 27, -5 },
756 { 12, 48, 53, 22, -7 },
757 { -9, 17, 52, 51, 17 },
758 { -7, 22, 53, 48, 12 },
759 { -5, 27, 54, 44, 8 },
760 { -2, 31, 55, 40, 4 },
80c39712
TV		 761 };
762
66be8f6c
GI		 763 const struct dispc_h_coef *h_coef;
764 const struct dispc_v_coef *v_coef;
80c39712
TV		 765 int i;
766
767 if (hscaleup)
768 h_coef = coef_hup;
769 else
770 h_coef = coef_hdown;
771
66be8f6c
GI		 772 if (vscaleup)
773 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
774 else
775 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 776
777 for (i = 0; i < 8; i++) {
778 u32 h, hv;
779
66be8f6c
GI		 780 h = FLD_VAL(h_coef[i].hc0, 7, 0)
781 | FLD_VAL(h_coef[i].hc1, 15, 8)
782 | FLD_VAL(h_coef[i].hc2, 23, 16)
783 | FLD_VAL(h_coef[i].hc3, 31, 24);
784 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
785 | FLD_VAL(v_coef[i].vc0, 15, 8)
786 | FLD_VAL(v_coef[i].vc1, 23, 16)
787 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712 788
0d66cbb5
AJ		 789 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
790 _dispc_write_firh_reg(plane, i, h);
791 _dispc_write_firhv_reg(plane, i, hv);
792 } else {
793 _dispc_write_firh2_reg(plane, i, h);
794 _dispc_write_firhv2_reg(plane, i, hv);
795 }
796
80c39712
TV		 797 }
798
66be8f6c
GI		 799 if (five_taps) {
800 for (i = 0; i < 8; i++) {
801 u32 v;
802 v = FLD_VAL(v_coef[i].vc00, 7, 0)
803 | FLD_VAL(v_coef[i].vc22, 15, 8);
0d66cbb5
AJ		 804 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
805 _dispc_write_firv_reg(plane, i, v);
806 else
807 _dispc_write_firv2_reg(plane, i, v);
66be8f6c 808 }
80c39712
TV		 809 }
810}
811
812static void _dispc_setup_color_conv_coef(void)
813{
814 const struct color_conv_coef {
815 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
816 int full_range;
817 } ctbl_bt601_5 = {
818 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
819 };
820
821 const struct color_conv_coef *ct;
822
823#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
824
825 ct = &ctbl_bt601_5;
826
9b372c2d
AT		 827 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
828 CVAL(ct->rcr, ct->ry));
829 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
830 CVAL(ct->gy, ct->rcb));
831 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
832 CVAL(ct->gcb, ct->gcr));
833 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
834 CVAL(ct->bcr, ct->by));
835 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
836 CVAL(0, ct->bcb));
837
838 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
839 CVAL(ct->rcr, ct->ry));
840 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
841 CVAL(ct->gy, ct->rcb));
842 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
843 CVAL(ct->gcb, ct->gcr));
844 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
845 CVAL(ct->bcr, ct->by));
846 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
847 CVAL(0, ct->bcb));
80c39712
TV		 848
849#undef CVAL
850
9b372c2d
AT		 851 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
852 ct->full_range, 11, 11);
853 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
854 ct->full_range, 11, 11);
80c39712
TV		 855}
856
857
858static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
859{
9b372c2d 860 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 861}
862
863static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
864{
9b372c2d 865 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 866}
867
ab5ca071
AJ		 868static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
869{
870 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
871}
872
873static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
874{
875 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
876}
877
80c39712
TV		 878static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
879{
80c39712 880 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 881
882 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 883}
884
885static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
886{
80c39712 887 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 888
889 if (plane == OMAP_DSS_GFX)
890 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
891 else
892 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 893}
894
895static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
896{
897 u32 val;
80c39712
TV		 898
899 BUG_ON(plane == OMAP_DSS_GFX);
900
901 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 902
903 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 904}
905
fd28a390
R		 906static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
907{
908 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
909 return;
910
911 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
912 plane == OMAP_DSS_VIDEO1)
913 return;
914
9b372c2d 915 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 916}
917
80c39712
TV		 918static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
919{
a0acb557 920 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 921 return;
922
fd28a390
R		 923 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
924 plane == OMAP_DSS_VIDEO1)
925 return;
a0acb557 926
80c39712
TV		 927 if (plane == OMAP_DSS_GFX)
928 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
929 else if (plane == OMAP_DSS_VIDEO2)
930 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
931}
932
933static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
934{
9b372c2d 935 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 936}
937
938static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
939{
9b372c2d 940 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 941}
942
943static void _dispc_set_color_mode(enum omap_plane plane,
944 enum omap_color_mode color_mode)
945{
946 u32 m = 0;
f20e4220
AJ		 947 if (plane != OMAP_DSS_GFX) {
948 switch (color_mode) {
949 case OMAP_DSS_COLOR_NV12:
950 m = 0x0; break;
951 case OMAP_DSS_COLOR_RGB12U:
952 m = 0x1; break;
953 case OMAP_DSS_COLOR_RGBA16:
954 m = 0x2; break;
955 case OMAP_DSS_COLOR_RGBX16:
956 m = 0x4; break;
957 case OMAP_DSS_COLOR_ARGB16:
958 m = 0x5; break;
959 case OMAP_DSS_COLOR_RGB16:
960 m = 0x6; break;
961 case OMAP_DSS_COLOR_ARGB16_1555:
962 m = 0x7; break;
963 case OMAP_DSS_COLOR_RGB24U:
964 m = 0x8; break;
965 case OMAP_DSS_COLOR_RGB24P:
966 m = 0x9; break;
967 case OMAP_DSS_COLOR_YUV2:
968 m = 0xa; break;
969 case OMAP_DSS_COLOR_UYVY:
970 m = 0xb; break;
971 case OMAP_DSS_COLOR_ARGB32:
972 m = 0xc; break;
973 case OMAP_DSS_COLOR_RGBA32:
974 m = 0xd; break;
975 case OMAP_DSS_COLOR_RGBX32:
976 m = 0xe; break;
977 case OMAP_DSS_COLOR_XRGB16_1555:
978 m = 0xf; break;
979 default:
980 BUG(); break;
981 }
982 } else {
983 switch (color_mode) {
984 case OMAP_DSS_COLOR_CLUT1:
985 m = 0x0; break;
986 case OMAP_DSS_COLOR_CLUT2:
987 m = 0x1; break;
988 case OMAP_DSS_COLOR_CLUT4:
989 m = 0x2; break;
990 case OMAP_DSS_COLOR_CLUT8:
991 m = 0x3; break;
992 case OMAP_DSS_COLOR_RGB12U:
993 m = 0x4; break;
994 case OMAP_DSS_COLOR_ARGB16:
995 m = 0x5; break;
996 case OMAP_DSS_COLOR_RGB16:
997 m = 0x6; break;
998 case OMAP_DSS_COLOR_ARGB16_1555:
999 m = 0x7; break;
1000 case OMAP_DSS_COLOR_RGB24U:
1001 m = 0x8; break;
1002 case OMAP_DSS_COLOR_RGB24P:
1003 m = 0x9; break;
1004 case OMAP_DSS_COLOR_YUV2:
1005 m = 0xa; break;
1006 case OMAP_DSS_COLOR_UYVY:
1007 m = 0xb; break;
1008 case OMAP_DSS_COLOR_ARGB32:
1009 m = 0xc; break;
1010 case OMAP_DSS_COLOR_RGBA32:
1011 m = 0xd; break;
1012 case OMAP_DSS_COLOR_RGBX32:
1013 m = 0xe; break;
1014 case OMAP_DSS_COLOR_XRGB16_1555:
1015 m = 0xf; break;
1016 default:
1017 BUG(); break;
1018 }
80c39712
TV		 1019 }
1020
9b372c2d 1021 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 1022}
1023
e6d80f95 1024void dispc_set_channel_out(enum omap_plane plane,
80c39712
TV		 1025 enum omap_channel channel)
1026{
1027 int shift;
1028 u32 val;
2a205f34 1029 int chan = 0, chan2 = 0;
80c39712
TV		 1030
1031 switch (plane) {
1032 case OMAP_DSS_GFX:
1033 shift = 8;
1034 break;
1035 case OMAP_DSS_VIDEO1:
1036 case OMAP_DSS_VIDEO2:
1037 shift = 16;
1038 break;
1039 default:
1040 BUG();
1041 return;
1042 }
1043
9b372c2d 1044 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 1045 if (dss_has_feature(FEAT_MGR_LCD2)) {
1046 switch (channel) {
1047 case OMAP_DSS_CHANNEL_LCD:
1048 chan = 0;
1049 chan2 = 0;
1050 break;
1051 case OMAP_DSS_CHANNEL_DIGIT:
1052 chan = 1;
1053 chan2 = 0;
1054 break;
1055 case OMAP_DSS_CHANNEL_LCD2:
1056 chan = 0;
1057 chan2 = 1;
1058 break;
1059 default:
1060 BUG();
1061 }
1062
1063 val = FLD_MOD(val, chan, shift, shift);
1064 val = FLD_MOD(val, chan2, 31, 30);
1065 } else {
1066 val = FLD_MOD(val, channel, shift, shift);
1067 }
9b372c2d 1068 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1069}
1070
5ed8cf5b 1071static void dispc_set_burst_size(enum omap_plane plane,
80c39712
TV		 1072 enum omap_burst_size burst_size)
1073{
1074 int shift;
80c39712 1075
80c39712
TV		 1076 switch (plane) {
1077 case OMAP_DSS_GFX:
1078 shift = 6;
1079 break;
1080 case OMAP_DSS_VIDEO1:
1081 case OMAP_DSS_VIDEO2:
1082 shift = 14;
1083 break;
1084 default:
1085 BUG();
1086 return;
1087 }
1088
5ed8cf5b 1089 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1090}
1091
5ed8cf5b
TV		 1092static void dispc_configure_burst_sizes(void)
1093{
1094 int i;
1095 const int burst_size = BURST_SIZE_X8;
1096
1097 /* Configure burst size always to maximum size */
1098 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1099 dispc_set_burst_size(i, burst_size);
1100}
1101
1102u32 dispc_get_burst_size(enum omap_plane plane)
1103{
1104 unsigned unit = dss_feat_get_burst_size_unit();
1105 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1106 return unit * 8;
1107}
1108
d3862610
M		 1109void dispc_enable_gamma_table(bool enable)
1110{
1111 /*
1112 * This is partially implemented to support only disabling of
1113 * the gamma table.
1114 */
1115 if (enable) {
1116 DSSWARN("Gamma table enabling for TV not yet supported");
1117 return;
1118 }
1119
1120 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1121}
1122
3c07cae2
TV		 1123void dispc_enable_cpr(enum omap_channel channel, bool enable)
1124{
1125 u16 reg;
1126
1127 if (channel == OMAP_DSS_CHANNEL_LCD)
1128 reg = DISPC_CONFIG;
1129 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1130 reg = DISPC_CONFIG2;
1131 else
1132 return;
1133
1134 REG_FLD_MOD(reg, enable, 15, 15);
1135}
1136
1137void dispc_set_cpr_coef(enum omap_channel channel,
1138 struct omap_dss_cpr_coefs *coefs)
1139{
1140 u32 coef_r, coef_g, coef_b;
1141
1142 if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2)
1143 return;
1144
1145 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1146 FLD_VAL(coefs->rb, 9, 0);
1147 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1148 FLD_VAL(coefs->gb, 9, 0);
1149 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1150 FLD_VAL(coefs->bb, 9, 0);
1151
1152 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1153 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1154 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1155}
1156
80c39712
TV		 1157static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1158{
1159 u32 val;
1160
1161 BUG_ON(plane == OMAP_DSS_GFX);
1162
9b372c2d 1163 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1164 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1165 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1166}
1167
1168void dispc_enable_replication(enum omap_plane plane, bool enable)
1169{
1170 int bit;
1171
1172 if (plane == OMAP_DSS_GFX)
1173 bit = 5;
1174 else
1175 bit = 10;
1176
9b372c2d 1177 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
80c39712
TV		 1178}
1179
64ba4f74 1180void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1181{
1182 u32 val;
1183 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1184 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1185 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1186}
1187
1188void dispc_set_digit_size(u16 width, u16 height)
1189{
1190 u32 val;
1191 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1192 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1193 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1194}
1195
1196static void dispc_read_plane_fifo_sizes(void)
1197{
80c39712
TV		 1198 u32 size;
1199 int plane;
a0acb557 1200 u8 start, end;
5ed8cf5b
TV		 1201 u32 unit;
1202
1203 unit = dss_feat_get_buffer_size_unit();
80c39712 1204
a0acb557 1205 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1206
a0acb557 1207 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
5ed8cf5b
TV		 1208 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1209 size *= unit;
80c39712
TV		 1210 dispc.fifo_size[plane] = size;
1211 }
80c39712
TV		 1212}
1213
1214u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1215{
1216 return dispc.fifo_size[plane];
1217}
1218
5ed8cf5b 1219void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1220{
a0acb557 1221 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1222 u32 unit;
1223
1224 unit = dss_feat_get_buffer_size_unit();
1225
1226 WARN_ON(low % unit != 0);
1227 WARN_ON(high % unit != 0);
1228
1229 low /= unit;
1230 high /= unit;
a0acb557 1231
9b372c2d
AT		 1232 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1233 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1234
80c39712
TV		 1235 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1236 plane,
9b372c2d
AT		 1237 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1238 lo_start, lo_end),
1239 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1240 hi_start, hi_end),
80c39712
TV		 1241 low, high);
1242
9b372c2d 1243 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1244 FLD_VAL(high, hi_start, hi_end) |
1245 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1246}
1247
1248void dispc_enable_fifomerge(bool enable)
1249{
80c39712
TV		 1250 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1251 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1252}
1253
0d66cbb5
AJ		 1254static void _dispc_set_fir(enum omap_plane plane,
1255 int hinc, int vinc,
1256 enum omap_color_component color_comp)
80c39712
TV		 1257{
1258 u32 val;
80c39712 1259
0d66cbb5
AJ		 1260 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1261 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1262
0d66cbb5
AJ		 1263 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1264 &hinc_start, &hinc_end);
1265 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1266 &vinc_start, &vinc_end);
1267 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1268 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1269
0d66cbb5
AJ		 1270 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1271 } else {
1272 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1273 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1274 }
80c39712
TV		 1275}
1276
1277static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1278{
1279 u32 val;
87a7484b 1280 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1281
87a7484b
AT		 1282 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1283 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1284
1285 val = FLD_VAL(vaccu, vert_start, vert_end) |
1286 FLD_VAL(haccu, hor_start, hor_end);
1287
9b372c2d 1288 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1289}
1290
1291static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1292{
1293 u32 val;
87a7484b 1294 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1295
87a7484b
AT		 1296 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1297 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1298
1299 val = FLD_VAL(vaccu, vert_start, vert_end) |
1300 FLD_VAL(haccu, hor_start, hor_end);
1301
9b372c2d 1302 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1303}
1304
ab5ca071
AJ		 1305static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
1306{
1307 u32 val;
1308
1309 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1310 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1311}
1312
1313static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
1314{
1315 u32 val;
1316
1317 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1318 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1319}
80c39712 1320
0d66cbb5 1321static void _dispc_set_scale_param(enum omap_plane plane,
80c39712
TV		 1322 u16 orig_width, u16 orig_height,
1323 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1324 bool five_taps, u8 rotation,
1325 enum omap_color_component color_comp)
80c39712 1326{
0d66cbb5 1327 int fir_hinc, fir_vinc;
80c39712 1328 int hscaleup, vscaleup;
80c39712
TV		 1329
1330 hscaleup = orig_width <= out_width;
1331 vscaleup = orig_height <= out_height;
1332
0d66cbb5 1333 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
80c39712 1334
ed14a3ce
AJ		 1335 fir_hinc = 1024 * orig_width / out_width;
1336 fir_vinc = 1024 * orig_height / out_height;
80c39712 1337
0d66cbb5
AJ		 1338 _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1339}
1340
1341static void _dispc_set_scaling_common(enum omap_plane plane,
1342 u16 orig_width, u16 orig_height,
1343 u16 out_width, u16 out_height,
1344 bool ilace, bool five_taps,
1345 bool fieldmode, enum omap_color_mode color_mode,
1346 u8 rotation)
1347{
1348 int accu0 = 0;
1349 int accu1 = 0;
1350 u32 l;
80c39712 1351
0d66cbb5
AJ		 1352 _dispc_set_scale_param(plane, orig_width, orig_height,
1353 out_width, out_height, five_taps,
1354 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1355 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1356
87a7484b
AT		 1357 /* RESIZEENABLE and VERTICALTAPS */
1358 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1359 l |= (orig_width != out_width) ? (1 << 5) : 0;
1360 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1361 l |= five_taps ? (1 << 21) : 0;
80c39712 1362
87a7484b
AT		 1363 /* VRESIZECONF and HRESIZECONF */
1364 if (dss_has_feature(FEAT_RESIZECONF)) {
1365 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1366 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1367 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1368 }
80c39712 1369
87a7484b
AT		 1370 /* LINEBUFFERSPLIT */
1371 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1372 l &= ~(0x1 << 22);
1373 l |= five_taps ? (1 << 22) : 0;
1374 }
80c39712 1375
9b372c2d 1376 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1377
1378 /*
1379 * field 0 = even field = bottom field
1380 * field 1 = odd field = top field
1381 */
1382 if (ilace && !fieldmode) {
1383 accu1 = 0;
0d66cbb5 1384 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1385 if (accu0 >= 1024/2) {
1386 accu1 = 1024/2;
1387 accu0 -= accu1;
1388 }
1389 }
1390
1391 _dispc_set_vid_accu0(plane, 0, accu0);
1392 _dispc_set_vid_accu1(plane, 0, accu1);
1393}
1394
0d66cbb5
AJ		 1395static void _dispc_set_scaling_uv(enum omap_plane plane,
1396 u16 orig_width, u16 orig_height,
1397 u16 out_width, u16 out_height,
1398 bool ilace, bool five_taps,
1399 bool fieldmode, enum omap_color_mode color_mode,
1400 u8 rotation)
1401{
1402 int scale_x = out_width != orig_width;
1403 int scale_y = out_height != orig_height;
1404
1405 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1406 return;
1407 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1408 color_mode != OMAP_DSS_COLOR_UYVY &&
1409 color_mode != OMAP_DSS_COLOR_NV12)) {
1410 /* reset chroma resampling for RGB formats */
1411 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1412 return;
1413 }
1414 switch (color_mode) {
1415 case OMAP_DSS_COLOR_NV12:
1416 /* UV is subsampled by 2 vertically*/
1417 orig_height >>= 1;
1418 /* UV is subsampled by 2 horz.*/
1419 orig_width >>= 1;
1420 break;
1421 case OMAP_DSS_COLOR_YUV2:
1422 case OMAP_DSS_COLOR_UYVY:
1423 /*For YUV422 with 90/270 rotation,
1424 *we don't upsample chroma
1425 */
1426 if (rotation == OMAP_DSS_ROT_0 ||
1427 rotation == OMAP_DSS_ROT_180)
1428 /* UV is subsampled by 2 hrz*/
1429 orig_width >>= 1;
1430 /* must use FIR for YUV422 if rotated */
1431 if (rotation != OMAP_DSS_ROT_0)
1432 scale_x = scale_y = true;
1433 break;
1434 default:
1435 BUG();
1436 }
1437
1438 if (out_width != orig_width)
1439 scale_x = true;
1440 if (out_height != orig_height)
1441 scale_y = true;
1442
1443 _dispc_set_scale_param(plane, orig_width, orig_height,
1444 out_width, out_height, five_taps,
1445 rotation, DISPC_COLOR_COMPONENT_UV);
1446
1447 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1448 (scale_x || scale_y) ? 1 : 0, 8, 8);
1449 /* set H scaling */
1450 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1451 /* set V scaling */
1452 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1453
1454 _dispc_set_vid_accu2_0(plane, 0x80, 0);
1455 _dispc_set_vid_accu2_1(plane, 0x80, 0);
1456}
1457
1458static void _dispc_set_scaling(enum omap_plane plane,
1459 u16 orig_width, u16 orig_height,
1460 u16 out_width, u16 out_height,
1461 bool ilace, bool five_taps,
1462 bool fieldmode, enum omap_color_mode color_mode,
1463 u8 rotation)
1464{
1465 BUG_ON(plane == OMAP_DSS_GFX);
1466
1467 _dispc_set_scaling_common(plane,
1468 orig_width, orig_height,
1469 out_width, out_height,
1470 ilace, five_taps,
1471 fieldmode, color_mode,
1472 rotation);
1473
1474 _dispc_set_scaling_uv(plane,
1475 orig_width, orig_height,
1476 out_width, out_height,
1477 ilace, five_taps,
1478 fieldmode, color_mode,
1479 rotation);
1480}
1481
80c39712
TV		 1482static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1483 bool mirroring, enum omap_color_mode color_mode)
1484{
87a7484b
AT		 1485 bool row_repeat = false;
1486 int vidrot = 0;
1487
80c39712
TV		 1488 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1489 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1490
1491 if (mirroring) {
1492 switch (rotation) {
1493 case OMAP_DSS_ROT_0:
1494 vidrot = 2;
1495 break;
1496 case OMAP_DSS_ROT_90:
1497 vidrot = 1;
1498 break;
1499 case OMAP_DSS_ROT_180:
1500 vidrot = 0;
1501 break;
1502 case OMAP_DSS_ROT_270:
1503 vidrot = 3;
1504 break;
1505 }
1506 } else {
1507 switch (rotation) {
1508 case OMAP_DSS_ROT_0:
1509 vidrot = 0;
1510 break;
1511 case OMAP_DSS_ROT_90:
1512 vidrot = 1;
1513 break;
1514 case OMAP_DSS_ROT_180:
1515 vidrot = 2;
1516 break;
1517 case OMAP_DSS_ROT_270:
1518 vidrot = 3;
1519 break;
1520 }
1521 }
1522
80c39712 1523 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1524 row_repeat = true;
80c39712 1525 else
87a7484b 1526 row_repeat = false;
80c39712 1527 }
87a7484b 1528
9b372c2d 1529 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1530 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1531 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1532 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1533}
1534
1535static int color_mode_to_bpp(enum omap_color_mode color_mode)
1536{
1537 switch (color_mode) {
1538 case OMAP_DSS_COLOR_CLUT1:
1539 return 1;
1540 case OMAP_DSS_COLOR_CLUT2:
1541 return 2;
1542 case OMAP_DSS_COLOR_CLUT4:
1543 return 4;
1544 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1545 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1546 return 8;
1547 case OMAP_DSS_COLOR_RGB12U:
1548 case OMAP_DSS_COLOR_RGB16:
1549 case OMAP_DSS_COLOR_ARGB16:
1550 case OMAP_DSS_COLOR_YUV2:
1551 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1552 case OMAP_DSS_COLOR_RGBA16:
1553 case OMAP_DSS_COLOR_RGBX16:
1554 case OMAP_DSS_COLOR_ARGB16_1555:
1555 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1556 return 16;
1557 case OMAP_DSS_COLOR_RGB24P:
1558 return 24;
1559 case OMAP_DSS_COLOR_RGB24U:
1560 case OMAP_DSS_COLOR_ARGB32:
1561 case OMAP_DSS_COLOR_RGBA32:
1562 case OMAP_DSS_COLOR_RGBX32:
1563 return 32;
1564 default:
1565 BUG();
1566 }
1567}
1568
1569static s32 pixinc(int pixels, u8 ps)
1570{
1571 if (pixels == 1)
1572 return 1;
1573 else if (pixels > 1)
1574 return 1 + (pixels - 1) * ps;
1575 else if (pixels < 0)
1576 return 1 - (-pixels + 1) * ps;
1577 else
1578 BUG();
1579}
1580
1581static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1582 u16 screen_width,
1583 u16 width, u16 height,
1584 enum omap_color_mode color_mode, bool fieldmode,
1585 unsigned int field_offset,
1586 unsigned *offset0, unsigned *offset1,
1587 s32 *row_inc, s32 *pix_inc)
1588{
1589 u8 ps;
1590
1591 /* FIXME CLUT formats */
1592 switch (color_mode) {
1593 case OMAP_DSS_COLOR_CLUT1:
1594 case OMAP_DSS_COLOR_CLUT2:
1595 case OMAP_DSS_COLOR_CLUT4:
1596 case OMAP_DSS_COLOR_CLUT8:
1597 BUG();
1598 return;
1599 case OMAP_DSS_COLOR_YUV2:
1600 case OMAP_DSS_COLOR_UYVY:
1601 ps = 4;
1602 break;
1603 default:
1604 ps = color_mode_to_bpp(color_mode) / 8;
1605 break;
1606 }
1607
1608 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1609 width, height);
1610
1611 /*
1612 * field 0 = even field = bottom field
1613 * field 1 = odd field = top field
1614 */
1615 switch (rotation + mirror * 4) {
1616 case OMAP_DSS_ROT_0:
1617 case OMAP_DSS_ROT_180:
1618 /*
1619 * If the pixel format is YUV or UYVY divide the width
1620 * of the image by 2 for 0 and 180 degree rotation.
1621 */
1622 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1623 color_mode == OMAP_DSS_COLOR_UYVY)
1624 width = width >> 1;
1625 case OMAP_DSS_ROT_90:
1626 case OMAP_DSS_ROT_270:
1627 *offset1 = 0;
1628 if (field_offset)
1629 *offset0 = field_offset * screen_width * ps;
1630 else
1631 *offset0 = 0;
1632
1633 *row_inc = pixinc(1 + (screen_width - width) +
1634 (fieldmode ? screen_width : 0),
1635 ps);
1636 *pix_inc = pixinc(1, ps);
1637 break;
1638
1639 case OMAP_DSS_ROT_0 + 4:
1640 case OMAP_DSS_ROT_180 + 4:
1641 /* If the pixel format is YUV or UYVY divide the width
1642 * of the image by 2 for 0 degree and 180 degree
1643 */
1644 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1645 color_mode == OMAP_DSS_COLOR_UYVY)
1646 width = width >> 1;
1647 case OMAP_DSS_ROT_90 + 4:
1648 case OMAP_DSS_ROT_270 + 4:
1649 *offset1 = 0;
1650 if (field_offset)
1651 *offset0 = field_offset * screen_width * ps;
1652 else
1653 *offset0 = 0;
1654 *row_inc = pixinc(1 - (screen_width + width) -
1655 (fieldmode ? screen_width : 0),
1656 ps);
1657 *pix_inc = pixinc(1, ps);
1658 break;
1659
1660 default:
1661 BUG();
1662 }
1663}
1664
1665static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1666 u16 screen_width,
1667 u16 width, u16 height,
1668 enum omap_color_mode color_mode, bool fieldmode,
1669 unsigned int field_offset,
1670 unsigned *offset0, unsigned *offset1,
1671 s32 *row_inc, s32 *pix_inc)
1672{
1673 u8 ps;
1674 u16 fbw, fbh;
1675
1676 /* FIXME CLUT formats */
1677 switch (color_mode) {
1678 case OMAP_DSS_COLOR_CLUT1:
1679 case OMAP_DSS_COLOR_CLUT2:
1680 case OMAP_DSS_COLOR_CLUT4:
1681 case OMAP_DSS_COLOR_CLUT8:
1682 BUG();
1683 return;
1684 default:
1685 ps = color_mode_to_bpp(color_mode) / 8;
1686 break;
1687 }
1688
1689 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1690 width, height);
1691
1692 /* width & height are overlay sizes, convert to fb sizes */
1693
1694 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1695 fbw = width;
1696 fbh = height;
1697 } else {
1698 fbw = height;
1699 fbh = width;
1700 }
1701
1702 /*
1703 * field 0 = even field = bottom field
1704 * field 1 = odd field = top field
1705 */
1706 switch (rotation + mirror * 4) {
1707 case OMAP_DSS_ROT_0:
1708 *offset1 = 0;
1709 if (field_offset)
1710 *offset0 = *offset1 + field_offset * screen_width * ps;
1711 else
1712 *offset0 = *offset1;
1713 *row_inc = pixinc(1 + (screen_width - fbw) +
1714 (fieldmode ? screen_width : 0),
1715 ps);
1716 *pix_inc = pixinc(1, ps);
1717 break;
1718 case OMAP_DSS_ROT_90:
1719 *offset1 = screen_width * (fbh - 1) * ps;
1720 if (field_offset)
1721 *offset0 = *offset1 + field_offset * ps;
1722 else
1723 *offset0 = *offset1;
1724 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1725 (fieldmode ? 1 : 0), ps);
1726 *pix_inc = pixinc(-screen_width, ps);
1727 break;
1728 case OMAP_DSS_ROT_180:
1729 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1730 if (field_offset)
1731 *offset0 = *offset1 - field_offset * screen_width * ps;
1732 else
1733 *offset0 = *offset1;
1734 *row_inc = pixinc(-1 -
1735 (screen_width - fbw) -
1736 (fieldmode ? screen_width : 0),
1737 ps);
1738 *pix_inc = pixinc(-1, ps);
1739 break;
1740 case OMAP_DSS_ROT_270:
1741 *offset1 = (fbw - 1) * ps;
1742 if (field_offset)
1743 *offset0 = *offset1 - field_offset * ps;
1744 else
1745 *offset0 = *offset1;
1746 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1747 (fieldmode ? 1 : 0), ps);
1748 *pix_inc = pixinc(screen_width, ps);
1749 break;
1750
1751 /* mirroring */
1752 case OMAP_DSS_ROT_0 + 4:
1753 *offset1 = (fbw - 1) * ps;
1754 if (field_offset)
1755 *offset0 = *offset1 + field_offset * screen_width * ps;
1756 else
1757 *offset0 = *offset1;
1758 *row_inc = pixinc(screen_width * 2 - 1 +
1759 (fieldmode ? screen_width : 0),
1760 ps);
1761 *pix_inc = pixinc(-1, ps);
1762 break;
1763
1764 case OMAP_DSS_ROT_90 + 4:
1765 *offset1 = 0;
1766 if (field_offset)
1767 *offset0 = *offset1 + field_offset * ps;
1768 else
1769 *offset0 = *offset1;
1770 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1771 (fieldmode ? 1 : 0),
1772 ps);
1773 *pix_inc = pixinc(screen_width, ps);
1774 break;
1775
1776 case OMAP_DSS_ROT_180 + 4:
1777 *offset1 = screen_width * (fbh - 1) * ps;
1778 if (field_offset)
1779 *offset0 = *offset1 - field_offset * screen_width * ps;
1780 else
1781 *offset0 = *offset1;
1782 *row_inc = pixinc(1 - screen_width * 2 -
1783 (fieldmode ? screen_width : 0),
1784 ps);
1785 *pix_inc = pixinc(1, ps);
1786 break;
1787
1788 case OMAP_DSS_ROT_270 + 4:
1789 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1790 if (field_offset)
1791 *offset0 = *offset1 - field_offset * ps;
1792 else
1793 *offset0 = *offset1;
1794 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1795 (fieldmode ? 1 : 0),
1796 ps);
1797 *pix_inc = pixinc(-screen_width, ps);
1798 break;
1799
1800 default:
1801 BUG();
1802 }
1803}
1804
ff1b2cde
SS		 1805static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1806 u16 height, u16 out_width, u16 out_height,
1807 enum omap_color_mode color_mode)
80c39712
TV		 1808{
1809 u32 fclk = 0;
1810 /* FIXME venc pclk? */
ff1b2cde 1811 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1812
1813 if (height > out_height) {
1814 /* FIXME get real display PPL */
1815 unsigned int ppl = 800;
1816
1817 tmp = pclk * height * out_width;
1818 do_div(tmp, 2 * out_height * ppl);
1819 fclk = tmp;
1820
2d9c5597
VS		 1821 if (height > 2 * out_height) {
1822 if (ppl == out_width)
1823 return 0;
1824
80c39712
TV		 1825 tmp = pclk * (height - 2 * out_height) * out_width;
1826 do_div(tmp, 2 * out_height * (ppl - out_width));
1827 fclk = max(fclk, (u32) tmp);
1828 }
1829 }
1830
1831 if (width > out_width) {
1832 tmp = pclk * width;
1833 do_div(tmp, out_width);
1834 fclk = max(fclk, (u32) tmp);
1835
1836 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1837 fclk <<= 1;
1838 }
1839
1840 return fclk;
1841}
1842
ff1b2cde
SS		 1843static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1844 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1845{
1846 unsigned int hf, vf;
1847
1848 /*
1849 * FIXME how to determine the 'A' factor
1850 * for the no downscaling case ?
1851 */
1852
1853 if (width > 3 * out_width)
1854 hf = 4;
1855 else if (width > 2 * out_width)
1856 hf = 3;
1857 else if (width > out_width)
1858 hf = 2;
1859 else
1860 hf = 1;
1861
1862 if (height > out_height)
1863 vf = 2;
1864 else
1865 vf = 1;
1866
1867 /* FIXME venc pclk? */
ff1b2cde 1868 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1869}
1870
e6d80f95 1871int dispc_setup_plane(enum omap_plane plane,
80c39712
TV		 1872 u32 paddr, u16 screen_width,
1873 u16 pos_x, u16 pos_y,
1874 u16 width, u16 height,
1875 u16 out_width, u16 out_height,
1876 enum omap_color_mode color_mode,
1877 bool ilace,
1878 enum omap_dss_rotation_type rotation_type,
e6d80f95 1879 u8 rotation, bool mirror,
18faa1b6 1880 u8 global_alpha, u8 pre_mult_alpha,
0d66cbb5 1881 enum omap_channel channel, u32 puv_addr)
80c39712
TV		 1882{
1883 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1884 bool five_taps = 0;
1885 bool fieldmode = 0;
1886 int cconv = 0;
1887 unsigned offset0, offset1;
1888 s32 row_inc;
1889 s32 pix_inc;
1890 u16 frame_height = height;
1891 unsigned int field_offset = 0;
1892
e6d80f95
TV		 1893 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
1894 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
1895 plane, paddr, screen_width, pos_x, pos_y,
1896 width, height,
1897 out_width, out_height,
1898 ilace, color_mode,
1899 rotation, mirror, channel);
1900
80c39712
TV		 1901 if (paddr == 0)
1902 return -EINVAL;
1903
1904 if (ilace && height == out_height)
1905 fieldmode = 1;
1906
1907 if (ilace) {
1908 if (fieldmode)
1909 height /= 2;
1910 pos_y /= 2;
1911 out_height /= 2;
1912
1913 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1914 "out_height %d\n",
1915 height, pos_y, out_height);
1916 }
1917
8dad2ab6
AT		 1918 if (!dss_feat_color_mode_supported(plane, color_mode))
1919 return -EINVAL;
1920
80c39712
TV		 1921 if (plane == OMAP_DSS_GFX) {
1922 if (width != out_width || height != out_height)
1923 return -EINVAL;
80c39712
TV		 1924 } else {
1925 /* video plane */
1926
1927 unsigned long fclk = 0;
1928
1929 if (out_width < width / maxdownscale ||
1930 out_width > width * 8)
1931 return -EINVAL;
1932
1933 if (out_height < height / maxdownscale ||
1934 out_height > height * 8)
1935 return -EINVAL;
1936
8dad2ab6 1937 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
0d66cbb5
AJ		 1938 color_mode == OMAP_DSS_COLOR_UYVY ||
1939 color_mode == OMAP_DSS_COLOR_NV12)
80c39712 1940 cconv = 1;
80c39712
TV		 1941
1942 /* Must use 5-tap filter? */
1943 five_taps = height > out_height * 2;
1944
1945 if (!five_taps) {
18faa1b6
SS		 1946 fclk = calc_fclk(channel, width, height, out_width,
1947 out_height);
80c39712
TV		 1948
1949 /* Try 5-tap filter if 3-tap fclk is too high */
1950 if (cpu_is_omap34xx() && height > out_height &&
1951 fclk > dispc_fclk_rate())
1952 five_taps = true;
1953 }
1954
1955 if (width > (2048 >> five_taps)) {
1956 DSSERR("failed to set up scaling, fclk too low\n");
1957 return -EINVAL;
1958 }
1959
1960 if (five_taps)
18faa1b6
SS		 1961 fclk = calc_fclk_five_taps(channel, width, height,
1962 out_width, out_height, color_mode);
80c39712
TV		 1963
1964 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1965 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1966
2d9c5597 1967 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1968 DSSERR("failed to set up scaling, "
1969 "required fclk rate = %lu Hz, "
1970 "current fclk rate = %lu Hz\n",
1971 fclk, dispc_fclk_rate());
1972 return -EINVAL;
1973 }
1974 }
1975
1976 if (ilace && !fieldmode) {
1977 /*
1978 * when downscaling the bottom field may have to start several
1979 * source lines below the top field. Unfortunately ACCUI
1980 * registers will only hold the fractional part of the offset
1981 * so the integer part must be added to the base address of the
1982 * bottom field.
1983 */
1984 if (!height || height == out_height)
1985 field_offset = 0;
1986 else
1987 field_offset = height / out_height / 2;
1988 }
1989
1990 /* Fields are independent but interleaved in memory. */
1991 if (fieldmode)
1992 field_offset = 1;
1993
1994 if (rotation_type == OMAP_DSS_ROT_DMA)
1995 calc_dma_rotation_offset(rotation, mirror,
1996 screen_width, width, frame_height, color_mode,
1997 fieldmode, field_offset,
1998 &offset0, &offset1, &row_inc, &pix_inc);
1999 else
2000 calc_vrfb_rotation_offset(rotation, mirror,
2001 screen_width, width, frame_height, color_mode,
2002 fieldmode, field_offset,
2003 &offset0, &offset1, &row_inc, &pix_inc);
2004
2005 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2006 offset0, offset1, row_inc, pix_inc);
2007
2008 _dispc_set_color_mode(plane, color_mode);
2009
2010 _dispc_set_plane_ba0(plane, paddr + offset0);
2011 _dispc_set_plane_ba1(plane, paddr + offset1);
2012
0d66cbb5
AJ		 2013 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2014 _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
2015 _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
2016 }
2017
2018
80c39712
TV		 2019 _dispc_set_row_inc(plane, row_inc);
2020 _dispc_set_pix_inc(plane, pix_inc);
2021
2022 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
2023 out_width, out_height);
2024
2025 _dispc_set_plane_pos(plane, pos_x, pos_y);
2026
2027 _dispc_set_pic_size(plane, width, height);
2028
2029 if (plane != OMAP_DSS_GFX) {
2030 _dispc_set_scaling(plane, width, height,
2031 out_width, out_height,
0d66cbb5
AJ		 2032 ilace, five_taps, fieldmode,
2033 color_mode, rotation);
80c39712
TV		 2034 _dispc_set_vid_size(plane, out_width, out_height);
2035 _dispc_set_vid_color_conv(plane, cconv);
2036 }
2037
2038 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
2039
fd28a390
R		 2040 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
2041 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 2042
2043 return 0;
2044}
2045
e6d80f95 2046int dispc_enable_plane(enum omap_plane plane, bool enable)
80c39712 2047{
e6d80f95
TV		 2048 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2049
9b372c2d 2050 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2051
2052 return 0;
80c39712
TV		 2053}
2054
2055static void dispc_disable_isr(void *data, u32 mask)
2056{
2057 struct completion *compl = data;
2058 complete(compl);
2059}
2060
2a205f34 2061static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2062{
2a205f34
SS		 2063 if (channel == OMAP_DSS_CHANNEL_LCD2)
2064 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
2065 else
2066 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 2067}
2068
2a205f34 2069static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2070{
2071 struct completion frame_done_completion;
2072 bool is_on;
2073 int r;
2a205f34 2074 u32 irq;
80c39712 2075
80c39712
TV		 2076 /* When we disable LCD output, we need to wait until frame is done.
2077 * Otherwise the DSS is still working, and turning off the clocks
2078 * prevents DSS from going to OFF mode */
2a205f34
SS		 2079 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2080 REG_GET(DISPC_CONTROL2, 0, 0) :
2081 REG_GET(DISPC_CONTROL, 0, 0);
2082
2083 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2084 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2085
2086 if (!enable && is_on) {
2087 init_completion(&frame_done_completion);
2088
2089 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2090 &frame_done_completion, irq);
80c39712
TV		 2091
2092 if (r)
2093 DSSERR("failed to register FRAMEDONE isr\n");
2094 }
2095
2a205f34 2096 _enable_lcd_out(channel, enable);
80c39712
TV		 2097
2098 if (!enable && is_on) {
2099 if (!wait_for_completion_timeout(&frame_done_completion,
2100 msecs_to_jiffies(100)))
2101 DSSERR("timeout waiting for FRAME DONE\n");
2102
2103 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2104 &frame_done_completion, irq);
80c39712
TV		 2105
2106 if (r)
2107 DSSERR("failed to unregister FRAMEDONE isr\n");
2108 }
80c39712
TV		 2109}
2110
2111static void _enable_digit_out(bool enable)
2112{
2113 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2114}
2115
a2faee84 2116static void dispc_enable_digit_out(bool enable)
80c39712
TV		 2117{
2118 struct completion frame_done_completion;
2119 int r;
2120
e6d80f95 2121 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2122 return;
80c39712
TV		 2123
2124 if (enable) {
2125 unsigned long flags;
2126 /* When we enable digit output, we'll get an extra digit
2127 * sync lost interrupt, that we need to ignore */
2128 spin_lock_irqsave(&dispc.irq_lock, flags);
2129 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2130 _omap_dispc_set_irqs();
2131 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2132 }
2133
2134 /* When we disable digit output, we need to wait until fields are done.
2135 * Otherwise the DSS is still working, and turning off the clocks
2136 * prevents DSS from going to OFF mode. And when enabling, we need to
2137 * wait for the extra sync losts */
2138 init_completion(&frame_done_completion);
2139
2140 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2141 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
2142 if (r)
2143 DSSERR("failed to register EVSYNC isr\n");
2144
2145 _enable_digit_out(enable);
2146
2147 /* XXX I understand from TRM that we should only wait for the
2148 * current field to complete. But it seems we have to wait
2149 * for both fields */
2150 if (!wait_for_completion_timeout(&frame_done_completion,
2151 msecs_to_jiffies(100)))
2152 DSSERR("timeout waiting for EVSYNC\n");
2153
2154 if (!wait_for_completion_timeout(&frame_done_completion,
2155 msecs_to_jiffies(100)))
2156 DSSERR("timeout waiting for EVSYNC\n");
2157
2158 r = omap_dispc_unregister_isr(dispc_disable_isr,
2159 &frame_done_completion,
2160 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
2161 if (r)
2162 DSSERR("failed to unregister EVSYNC isr\n");
2163
2164 if (enable) {
2165 unsigned long flags;
2166 spin_lock_irqsave(&dispc.irq_lock, flags);
2167 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 2168 if (dss_has_feature(FEAT_MGR_LCD2))
2169 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 2170 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2171 _omap_dispc_set_irqs();
2172 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2173 }
80c39712
TV		 2174}
2175
a2faee84
TV		 2176bool dispc_is_channel_enabled(enum omap_channel channel)
2177{
2178 if (channel == OMAP_DSS_CHANNEL_LCD)
2179 return !!REG_GET(DISPC_CONTROL, 0, 0);
2180 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2181 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2182 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2183 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2184 else
2185 BUG();
2186}
2187
2188void dispc_enable_channel(enum omap_channel channel, bool enable)
2189{
2a205f34
SS		 2190 if (channel == OMAP_DSS_CHANNEL_LCD ||
2191 channel == OMAP_DSS_CHANNEL_LCD2)
2192 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 2193 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2194 dispc_enable_digit_out(enable);
2195 else
2196 BUG();
2197}
2198
80c39712
TV		 2199void dispc_lcd_enable_signal_polarity(bool act_high)
2200{
6ced40bf
AT		 2201 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2202 return;
2203
80c39712 2204 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2205}
2206
2207void dispc_lcd_enable_signal(bool enable)
2208{
6ced40bf
AT		 2209 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2210 return;
2211
80c39712 2212 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2213}
2214
2215void dispc_pck_free_enable(bool enable)
2216{
6ced40bf
AT		 2217 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2218 return;
2219
80c39712 2220 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2221}
2222
64ba4f74 2223void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2224{
2a205f34
SS		 2225 if (channel == OMAP_DSS_CHANNEL_LCD2)
2226 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2227 else
2228 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2229}
2230
2231
64ba4f74
SS		 2232void dispc_set_lcd_display_type(enum omap_channel channel,
2233 enum omap_lcd_display_type type)
80c39712
TV		 2234{
2235 int mode;
2236
2237 switch (type) {
2238 case OMAP_DSS_LCD_DISPLAY_STN:
2239 mode = 0;
2240 break;
2241
2242 case OMAP_DSS_LCD_DISPLAY_TFT:
2243 mode = 1;
2244 break;
2245
2246 default:
2247 BUG();
2248 return;
2249 }
2250
2a205f34
SS		 2251 if (channel == OMAP_DSS_CHANNEL_LCD2)
2252 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2253 else
2254 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2255}
2256
2257void dispc_set_loadmode(enum omap_dss_load_mode mode)
2258{
80c39712 2259 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2260}
2261
2262
2263void dispc_set_default_color(enum omap_channel channel, u32 color)
2264{
8613b000 2265 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2266}
2267
2268u32 dispc_get_default_color(enum omap_channel channel)
2269{
80c39712
TV		 2270 u32 l;
2271
2272 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2273 channel != OMAP_DSS_CHANNEL_LCD &&
2274 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712 2275
8613b000 2276 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2277
2278 return l;
2279}
2280
2281void dispc_set_trans_key(enum omap_channel ch,
2282 enum omap_dss_trans_key_type type,
2283 u32 trans_key)
2284{
80c39712
TV		 2285 if (ch == OMAP_DSS_CHANNEL_LCD)
2286 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2287 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2288 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2289 else /* OMAP_DSS_CHANNEL_LCD2 */
2290 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2291
8613b000 2292 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2293}
2294
2295void dispc_get_trans_key(enum omap_channel ch,
2296 enum omap_dss_trans_key_type *type,
2297 u32 *trans_key)
2298{
80c39712
TV		 2299 if (type) {
2300 if (ch == OMAP_DSS_CHANNEL_LCD)
2301 *type = REG_GET(DISPC_CONFIG, 11, 11);
2302 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2303 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2304 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2305 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2306 else
2307 BUG();
2308 }
2309
2310 if (trans_key)
8613b000 2311 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2312}
2313
2314void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2315{
80c39712
TV		 2316 if (ch == OMAP_DSS_CHANNEL_LCD)
2317 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2318 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2319 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2320 else /* OMAP_DSS_CHANNEL_LCD2 */
2321 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2322}
2323void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2324{
a0acb557 2325 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2326 return;
2327
80c39712
TV		 2328 if (ch == OMAP_DSS_CHANNEL_LCD)
2329 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2330 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2331 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2332 else /* OMAP_DSS_CHANNEL_LCD2 */
2333 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2334}
2335bool dispc_alpha_blending_enabled(enum omap_channel ch)
2336{
2337 bool enabled;
2338
a0acb557 2339 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2340 return false;
2341
80c39712
TV		 2342 if (ch == OMAP_DSS_CHANNEL_LCD)
2343 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2344 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2345 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2346 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2347 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2348 else
2349 BUG();
80c39712
TV		 2350
2351 return enabled;
80c39712
TV		 2352}
2353
2354
2355bool dispc_trans_key_enabled(enum omap_channel ch)
2356{
2357 bool enabled;
2358
80c39712
TV		 2359 if (ch == OMAP_DSS_CHANNEL_LCD)
2360 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2361 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2362 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2363 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2364 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2365 else
2366 BUG();
80c39712
TV		 2367
2368 return enabled;
2369}
2370
2371
64ba4f74 2372void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2373{
2374 int code;
2375
2376 switch (data_lines) {
2377 case 12:
2378 code = 0;
2379 break;
2380 case 16:
2381 code = 1;
2382 break;
2383 case 18:
2384 code = 2;
2385 break;
2386 case 24:
2387 code = 3;
2388 break;
2389 default:
2390 BUG();
2391 return;
2392 }
2393
2a205f34
SS		 2394 if (channel == OMAP_DSS_CHANNEL_LCD2)
2395 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2396 else
2397 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2398}
2399
64ba4f74
SS		 2400void dispc_set_parallel_interface_mode(enum omap_channel channel,
2401 enum omap_parallel_interface_mode mode)
80c39712
TV		 2402{
2403 u32 l;
2404 int stallmode;
2405 int gpout0 = 1;
2406 int gpout1;
2407
2408 switch (mode) {
2409 case OMAP_DSS_PARALLELMODE_BYPASS:
2410 stallmode = 0;
2411 gpout1 = 1;
2412 break;
2413
2414 case OMAP_DSS_PARALLELMODE_RFBI:
2415 stallmode = 1;
2416 gpout1 = 0;
2417 break;
2418
2419 case OMAP_DSS_PARALLELMODE_DSI:
2420 stallmode = 1;
2421 gpout1 = 1;
2422 break;
2423
2424 default:
2425 BUG();
2426 return;
2427 }
2428
2a205f34
SS		 2429 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2430 l = dispc_read_reg(DISPC_CONTROL2);
2431 l = FLD_MOD(l, stallmode, 11, 11);
2432 dispc_write_reg(DISPC_CONTROL2, l);
2433 } else {
2434 l = dispc_read_reg(DISPC_CONTROL);
2435 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2436 l = FLD_MOD(l, gpout0, 15, 15);
2437 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2438 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2439 }
80c39712
TV		 2440}
2441
2442static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2443 int vsw, int vfp, int vbp)
2444{
2445 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2446 if (hsw < 1 || hsw > 64 ||
2447 hfp < 1 || hfp > 256 ||
2448 hbp < 1 || hbp > 256 ||
2449 vsw < 1 || vsw > 64 ||
2450 vfp < 0 || vfp > 255 ||
2451 vbp < 0 || vbp > 255)
2452 return false;
2453 } else {
2454 if (hsw < 1 || hsw > 256 ||
2455 hfp < 1 || hfp > 4096 ||
2456 hbp < 1 || hbp > 4096 ||
2457 vsw < 1 || vsw > 256 ||
2458 vfp < 0 || vfp > 4095 ||
2459 vbp < 0 || vbp > 4095)
2460 return false;
2461 }
2462
2463 return true;
2464}
2465
2466bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2467{
2468 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2469 timings->hbp, timings->vsw,
2470 timings->vfp, timings->vbp);
2471}
2472
64ba4f74
SS		 2473static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2474 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2475{
2476 u32 timing_h, timing_v;
2477
2478 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2479 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2480 FLD_VAL(hbp-1, 27, 20);
2481
2482 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2483 FLD_VAL(vbp, 27, 20);
2484 } else {
2485 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2486 FLD_VAL(hbp-1, 31, 20);
2487
2488 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2489 FLD_VAL(vbp, 31, 20);
2490 }
2491
64ba4f74
SS		 2492 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2493 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2494}
2495
2496/* change name to mode? */
64ba4f74
SS		 2497void dispc_set_lcd_timings(enum omap_channel channel,
2498 struct omap_video_timings *timings)
80c39712
TV		 2499{
2500 unsigned xtot, ytot;
2501 unsigned long ht, vt;
2502
2503 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2504 timings->hbp, timings->vsw,
2505 timings->vfp, timings->vbp))
2506 BUG();
2507
64ba4f74
SS		 2508 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2509 timings->hbp, timings->vsw, timings->vfp,
2510 timings->vbp);
80c39712 2511
64ba4f74 2512 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2513
2514 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2515 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2516
2517 ht = (timings->pixel_clock * 1000) / xtot;
2518 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2519
2a205f34
SS		 2520 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2521 timings->y_res);
80c39712
TV		 2522 DSSDBG("pck %u\n", timings->pixel_clock);
2523 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2524 timings->hsw, timings->hfp, timings->hbp,
2525 timings->vsw, timings->vfp, timings->vbp);
2526
2527 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2528}
2529
ff1b2cde
SS		 2530static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2531 u16 pck_div)
80c39712
TV		 2532{
2533 BUG_ON(lck_div < 1);
2534 BUG_ON(pck_div < 2);
2535
ce7fa5eb 2536 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2537 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2538}
2539
2a205f34
SS		 2540static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2541 int *pck_div)
80c39712
TV		 2542{
2543 u32 l;
ce7fa5eb 2544 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2545 *lck_div = FLD_GET(l, 23, 16);
2546 *pck_div = FLD_GET(l, 7, 0);
2547}
2548
2549unsigned long dispc_fclk_rate(void)
2550{
a72b64b9 2551 struct platform_device *dsidev;
80c39712
TV		 2552 unsigned long r = 0;
2553
66534e8e 2554 switch (dss_get_dispc_clk_source()) {
89a35e51 2555 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2556 r = clk_get_rate(dispc.dss_clk);
66534e8e 2557 break;
89a35e51 2558 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2559 dsidev = dsi_get_dsidev_from_id(0);
2560 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2561 break;
5a8b572d
AT		 2562 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2563 dsidev = dsi_get_dsidev_from_id(1);
2564 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2565 break;
66534e8e
TA		 2566 default:
2567 BUG();
2568 }
2569
80c39712
TV		 2570 return r;
2571}
2572
ff1b2cde 2573unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712 2574{
a72b64b9 2575 struct platform_device *dsidev;
80c39712
TV		 2576 int lcd;
2577 unsigned long r;
2578 u32 l;
2579
ce7fa5eb 2580 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2581
2582 lcd = FLD_GET(l, 23, 16);
2583
ea75159e 2584 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2585 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2586 r = clk_get_rate(dispc.dss_clk);
ea75159e 2587 break;
89a35e51 2588 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2589 dsidev = dsi_get_dsidev_from_id(0);
2590 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2591 break;
5a8b572d
AT		 2592 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2593 dsidev = dsi_get_dsidev_from_id(1);
2594 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2595 break;
ea75159e
TA		 2596 default:
2597 BUG();
2598 }
80c39712
TV		 2599
2600 return r / lcd;
2601}
2602
ff1b2cde 2603unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712 2604{
ea75159e 2605 int pcd;
80c39712
TV		 2606 unsigned long r;
2607 u32 l;
2608
ce7fa5eb 2609 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2610
80c39712
TV		 2611 pcd = FLD_GET(l, 7, 0);
2612
ea75159e 2613 r = dispc_lclk_rate(channel);
80c39712 2614
ea75159e 2615 return r / pcd;
80c39712
TV		 2616}
2617
2618void dispc_dump_clocks(struct seq_file *s)
2619{
2620 int lcd, pcd;
0cf35df3 2621 u32 l;
89a35e51
AT		 2622 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2623 enum omap_dss_clk_source lcd_clk_src;
80c39712 2624
4fbafaf3
TV		 2625 if (dispc_runtime_get())
2626 return;
80c39712 2627
80c39712
TV		 2628 seq_printf(s, "- DISPC -\n");
2629
067a57e4
AT		 2630 seq_printf(s, "dispc fclk source = %s (%s)\n",
2631 dss_get_generic_clk_source_name(dispc_clk_src),
2632 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2633
2634 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2635
0cf35df3
MR		 2636 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2637 seq_printf(s, "- DISPC-CORE-CLK -\n");
2638 l = dispc_read_reg(DISPC_DIVISOR);
2639 lcd = FLD_GET(l, 23, 16);
2640
2641 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2642 (dispc_fclk_rate()/lcd), lcd);
2643 }
2a205f34
SS		 2644 seq_printf(s, "- LCD1 -\n");
2645
ea75159e
TA		 2646 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2647
2648 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2649 dss_get_generic_clk_source_name(lcd_clk_src),
2650 dss_feat_get_clk_source_name(lcd_clk_src));
2651
2a205f34
SS		 2652 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2653
ff1b2cde
SS		 2654 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2655 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2656 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2657 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2658 if (dss_has_feature(FEAT_MGR_LCD2)) {
2659 seq_printf(s, "- LCD2 -\n");
2660
ea75159e
TA		 2661 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2662
2663 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2664 dss_get_generic_clk_source_name(lcd_clk_src),
2665 dss_feat_get_clk_source_name(lcd_clk_src));
2666
2a205f34 2667 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2668
2a205f34
SS		 2669 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2670 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2671 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2672 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2673 }
4fbafaf3
TV		 2674
2675 dispc_runtime_put();
80c39712
TV		 2676}
2677
dfc0fd8d
TV		 2678#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2679void dispc_dump_irqs(struct seq_file *s)
2680{
2681 unsigned long flags;
2682 struct dispc_irq_stats stats;
2683
2684 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2685
2686 stats = dispc.irq_stats;
2687 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2688 dispc.irq_stats.last_reset = jiffies;
2689
2690 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2691
2692 seq_printf(s, "period %u ms\n",
2693 jiffies_to_msecs(jiffies - stats.last_reset));
2694
2695 seq_printf(s, "irqs %d\n", stats.irq_count);
2696#define PIS(x) \
2697 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2698
2699 PIS(FRAMEDONE);
2700 PIS(VSYNC);
2701 PIS(EVSYNC_EVEN);
2702 PIS(EVSYNC_ODD);
2703 PIS(ACBIAS_COUNT_STAT);
2704 PIS(PROG_LINE_NUM);
2705 PIS(GFX_FIFO_UNDERFLOW);
2706 PIS(GFX_END_WIN);
2707 PIS(PAL_GAMMA_MASK);
2708 PIS(OCP_ERR);
2709 PIS(VID1_FIFO_UNDERFLOW);
2710 PIS(VID1_END_WIN);
2711 PIS(VID2_FIFO_UNDERFLOW);
2712 PIS(VID2_END_WIN);
2713 PIS(SYNC_LOST);
2714 PIS(SYNC_LOST_DIGIT);
2715 PIS(WAKEUP);
2a205f34
SS		 2716 if (dss_has_feature(FEAT_MGR_LCD2)) {
2717 PIS(FRAMEDONE2);
2718 PIS(VSYNC2);
2719 PIS(ACBIAS_COUNT_STAT2);
2720 PIS(SYNC_LOST2);
2721 }
dfc0fd8d
TV		 2722#undef PIS
2723}
dfc0fd8d
TV		 2724#endif
2725
80c39712
TV		 2726void dispc_dump_regs(struct seq_file *s)
2727{
9b372c2d 2728#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2729
4fbafaf3
TV		 2730 if (dispc_runtime_get())
2731 return;
80c39712
TV		 2732
2733 DUMPREG(DISPC_REVISION);
2734 DUMPREG(DISPC_SYSCONFIG);
2735 DUMPREG(DISPC_SYSSTATUS);
2736 DUMPREG(DISPC_IRQSTATUS);
2737 DUMPREG(DISPC_IRQENABLE);
2738 DUMPREG(DISPC_CONTROL);
2739 DUMPREG(DISPC_CONFIG);
2740 DUMPREG(DISPC_CAPABLE);
702d1448
AT		 2741 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
2742 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
2743 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
2744 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712
TV		 2745 DUMPREG(DISPC_LINE_STATUS);
2746 DUMPREG(DISPC_LINE_NUMBER);
702d1448
AT		 2747 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
2748 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
2749 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
2750 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
332e9d70
TV		 2751 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2752 DUMPREG(DISPC_GLOBAL_ALPHA);
702d1448
AT		 2753 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
2754 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34
SS		 2755 if (dss_has_feature(FEAT_MGR_LCD2)) {
2756 DUMPREG(DISPC_CONTROL2);
2757 DUMPREG(DISPC_CONFIG2);
702d1448
AT		 2758 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
2759 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
2760 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
2761 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
2762 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
2763 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2764 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
2a205f34 2765 }
80c39712 2766
9b372c2d
AT		 2767 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
2768 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
2769 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
2770 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
2771 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
2772 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
2773 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
2774 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
2775 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
2776 DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
2777 DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
80c39712 2778
702d1448
AT		 2779 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
2780 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
2781 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 2782
332e9d70
TV		 2783 if (dss_has_feature(FEAT_CPR)) {
2784 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
2785 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
2786 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
2787 }
2a205f34 2788 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 2789 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
2790 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
2791 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 2792
332e9d70
TV		 2793 if (dss_has_feature(FEAT_CPR)) {
2794 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2795 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
2796 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
2797 }
2a205f34 2798 }
80c39712 2799
332e9d70
TV		 2800 if (dss_has_feature(FEAT_PRELOAD))
2801 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
9b372c2d
AT		 2802
2803 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
2804 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
2805 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
2806 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
2807 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
2808 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
2809 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
2810 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
2811 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
2812 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
2813 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
2814 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
2815 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
2816
2817 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
2818 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
2819 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
2820 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
2821 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
2822 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
2823 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
2824 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
2825 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
2826 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
2827 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
2828 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
2829 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
2830
2831 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
2832 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
2833 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
2834 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
2835 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
2836 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
2837 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
2838 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
2839 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
2840 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
2841 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
2842 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
2843 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
2844 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
2845 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
2846 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
2847 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
2848 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
2849 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
2850 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
2851 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
332e9d70
TV		 2852 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2853 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
2854 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
2855 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
2856 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
2857 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
2858 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
2859 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
2860 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
2861 }
9b372c2d 2862
ab5ca071
AJ		 2863 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2864 DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
2865 DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
2866 DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
2867 DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
2868 DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
2869
2870 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
2871 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
2872 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
2873 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
2874 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
2875 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
2876 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
2877 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));
2878
2879 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
2880 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
2881 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
2882 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
2883 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
2884 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
2885 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
2886 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));
2887
2888 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
2889 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
2890 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
2891 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
2892 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
2893 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
2894 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
2895 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
2896 }
2897 if (dss_has_feature(FEAT_ATTR2))
2898 DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
2899
2900
9b372c2d
AT		 2901 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
2902 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
2903 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
2904 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
2905 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
2906 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
2907 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
2908 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
2909 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
2910 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
2911 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
2912 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
2913 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
2914 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
2915 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
2916 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
2917 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
2918 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
2919 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
2920 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
2921 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
332e9d70
TV		 2922
2923 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2924 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
2925 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
2926 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
2927 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
2928 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
2929 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
2930 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
2931 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
2932 }
9b372c2d 2933
ab5ca071
AJ		 2934 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2935 DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
2936 DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
2937 DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
2938 DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
2939 DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
2940
2941 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
2942 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
2943 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
2944 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
2945 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
2946 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
2947 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
2948 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));
2949
2950 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
2951 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
2952 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
2953 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
2954 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
2955 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
2956 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
2957 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));
2958
2959 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
2960 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
2961 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
2962 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
2963 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
2964 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
2965 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
2966 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
2967 }
2968 if (dss_has_feature(FEAT_ATTR2))
2969 DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
2970
332e9d70
TV		 2971 if (dss_has_feature(FEAT_PRELOAD)) {
2972 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
2973 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
2974 }
80c39712 2975
4fbafaf3 2976 dispc_runtime_put();
80c39712
TV		 2977#undef DUMPREG
2978}
2979
ff1b2cde
SS		 2980static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2981 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2982{
2983 u32 l = 0;
2984
2985 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2986 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2987
2988 l |= FLD_VAL(onoff, 17, 17);
2989 l |= FLD_VAL(rf, 16, 16);
2990 l |= FLD_VAL(ieo, 15, 15);
2991 l |= FLD_VAL(ipc, 14, 14);
2992 l |= FLD_VAL(ihs, 13, 13);
2993 l |= FLD_VAL(ivs, 12, 12);
2994 l |= FLD_VAL(acbi, 11, 8);
2995 l |= FLD_VAL(acb, 7, 0);
2996
ff1b2cde 2997 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2998}
2999
ff1b2cde
SS		 3000void dispc_set_pol_freq(enum omap_channel channel,
3001 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 3002{
ff1b2cde 3003 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 3004 (config & OMAP_DSS_LCD_RF) != 0,
3005 (config & OMAP_DSS_LCD_IEO) != 0,
3006 (config & OMAP_DSS_LCD_IPC) != 0,
3007 (config & OMAP_DSS_LCD_IHS) != 0,
3008 (config & OMAP_DSS_LCD_IVS) != 0,
3009 acbi, acb);
3010}
3011
3012/* with fck as input clock rate, find dispc dividers that produce req_pck */
3013void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3014 struct dispc_clock_info *cinfo)
3015{
3016 u16 pcd_min = is_tft ? 2 : 3;
3017 unsigned long best_pck;
3018 u16 best_ld, cur_ld;
3019 u16 best_pd, cur_pd;
3020
3021 best_pck = 0;
3022 best_ld = 0;
3023 best_pd = 0;
3024
3025 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3026 unsigned long lck = fck / cur_ld;
3027
3028 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
3029 unsigned long pck = lck / cur_pd;
3030 long old_delta = abs(best_pck - req_pck);
3031 long new_delta = abs(pck - req_pck);
3032
3033 if (best_pck == 0 || new_delta < old_delta) {
3034 best_pck = pck;
3035 best_ld = cur_ld;
3036 best_pd = cur_pd;
3037
3038 if (pck == req_pck)
3039 goto found;
3040 }
3041
3042 if (pck < req_pck)
3043 break;
3044 }
3045
3046 if (lck / pcd_min < req_pck)
3047 break;
3048 }
3049
3050found:
3051 cinfo->lck_div = best_ld;
3052 cinfo->pck_div = best_pd;
3053 cinfo->lck = fck / cinfo->lck_div;
3054 cinfo->pck = cinfo->lck / cinfo->pck_div;
3055}
3056
3057/* calculate clock rates using dividers in cinfo */
3058int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3059 struct dispc_clock_info *cinfo)
3060{
3061 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3062 return -EINVAL;
3063 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
3064 return -EINVAL;
3065
3066 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3067 cinfo->pck = cinfo->lck / cinfo->pck_div;
3068
3069 return 0;
3070}
3071
ff1b2cde
SS		 3072int dispc_set_clock_div(enum omap_channel channel,
3073 struct dispc_clock_info *cinfo)
80c39712
TV		 3074{
3075 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3076 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3077
ff1b2cde 3078 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3079
3080 return 0;
3081}
3082
ff1b2cde
SS		 3083int dispc_get_clock_div(enum omap_channel channel,
3084 struct dispc_clock_info *cinfo)
80c39712
TV		 3085{
3086 unsigned long fck;
3087
3088 fck = dispc_fclk_rate();
3089
ce7fa5eb
MR		 3090 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3091 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3092
3093 cinfo->lck = fck / cinfo->lck_div;
3094 cinfo->pck = cinfo->lck / cinfo->pck_div;
3095
3096 return 0;
3097}
3098
3099/* dispc.irq_lock has to be locked by the caller */
3100static void _omap_dispc_set_irqs(void)
3101{
3102 u32 mask;
3103 u32 old_mask;
3104 int i;
3105 struct omap_dispc_isr_data *isr_data;
3106
3107 mask = dispc.irq_error_mask;
3108
3109 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3110 isr_data = &dispc.registered_isr[i];
3111
3112 if (isr_data->isr == NULL)
3113 continue;
3114
3115 mask |= isr_data->mask;
3116 }
3117
80c39712
TV		 3118 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3119 /* clear the irqstatus for newly enabled irqs */
3120 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3121
3122 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3123}
3124
3125int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3126{
3127 int i;
3128 int ret;
3129 unsigned long flags;
3130 struct omap_dispc_isr_data *isr_data;
3131
3132 if (isr == NULL)
3133 return -EINVAL;
3134
3135 spin_lock_irqsave(&dispc.irq_lock, flags);
3136
3137 /* check for duplicate entry */
3138 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3139 isr_data = &dispc.registered_isr[i];
3140 if (isr_data->isr == isr && isr_data->arg == arg &&
3141 isr_data->mask == mask) {
3142 ret = -EINVAL;
3143 goto err;
3144 }
3145 }
3146
3147 isr_data = NULL;
3148 ret = -EBUSY;
3149
3150 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3151 isr_data = &dispc.registered_isr[i];
3152
3153 if (isr_data->isr != NULL)
3154 continue;
3155
3156 isr_data->isr = isr;
3157 isr_data->arg = arg;
3158 isr_data->mask = mask;
3159 ret = 0;
3160
3161 break;
3162 }
3163
b9cb0984
TV		 3164 if (ret)
3165 goto err;
3166
80c39712
TV		 3167 _omap_dispc_set_irqs();
3168
3169 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3170
3171 return 0;
3172err:
3173 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3174
3175 return ret;
3176}
3177EXPORT_SYMBOL(omap_dispc_register_isr);
3178
3179int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3180{
3181 int i;
3182 unsigned long flags;
3183 int ret = -EINVAL;
3184 struct omap_dispc_isr_data *isr_data;
3185
3186 spin_lock_irqsave(&dispc.irq_lock, flags);
3187
3188 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3189 isr_data = &dispc.registered_isr[i];
3190 if (isr_data->isr != isr || isr_data->arg != arg ||
3191 isr_data->mask != mask)
3192 continue;
3193
3194 /* found the correct isr */
3195
3196 isr_data->isr = NULL;
3197 isr_data->arg = NULL;
3198 isr_data->mask = 0;
3199
3200 ret = 0;
3201 break;
3202 }
3203
3204 if (ret == 0)
3205 _omap_dispc_set_irqs();
3206
3207 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3208
3209 return ret;
3210}
3211EXPORT_SYMBOL(omap_dispc_unregister_isr);
3212
3213#ifdef DEBUG
3214static void print_irq_status(u32 status)
3215{
3216 if ((status & dispc.irq_error_mask) == 0)
3217 return;
3218
3219 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3220
3221#define PIS(x) \
3222 if (status & DISPC_IRQ_##x) \
3223 printk(#x " ");
3224 PIS(GFX_FIFO_UNDERFLOW);
3225 PIS(OCP_ERR);
3226 PIS(VID1_FIFO_UNDERFLOW);
3227 PIS(VID2_FIFO_UNDERFLOW);
3228 PIS(SYNC_LOST);
3229 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3230 if (dss_has_feature(FEAT_MGR_LCD2))
3231 PIS(SYNC_LOST2);
80c39712
TV		 3232#undef PIS
3233
3234 printk("\n");
3235}
3236#endif
3237
3238/* Called from dss.c. Note that we don't touch clocks here,
3239 * but we presume they are on because we got an IRQ. However,
3240 * an irq handler may turn the clocks off, so we may not have
3241 * clock later in the function. */
affe360d 3242static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3243{
3244 int i;
affe360d 3245 u32 irqstatus, irqenable;
80c39712
TV		 3246 u32 handledirqs = 0;
3247 u32 unhandled_errors;
3248 struct omap_dispc_isr_data *isr_data;
3249 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3250
3251 spin_lock(&dispc.irq_lock);
3252
3253 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3254 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3255
3256 /* IRQ is not for us */
3257 if (!(irqstatus & irqenable)) {
3258 spin_unlock(&dispc.irq_lock);
3259 return IRQ_NONE;
3260 }
80c39712 3261
dfc0fd8d
TV		 3262#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3263 spin_lock(&dispc.irq_stats_lock);
3264 dispc.irq_stats.irq_count++;
3265 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3266 spin_unlock(&dispc.irq_stats_lock);
3267#endif
3268
80c39712
TV		 3269#ifdef DEBUG
3270 if (dss_debug)
3271 print_irq_status(irqstatus);
3272#endif
3273 /* Ack the interrupt. Do it here before clocks are possibly turned
3274 * off */
3275 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3276 /* flush posted write */
3277 dispc_read_reg(DISPC_IRQSTATUS);
3278
3279 /* make a copy and unlock, so that isrs can unregister
3280 * themselves */
3281 memcpy(registered_isr, dispc.registered_isr,
3282 sizeof(registered_isr));
3283
3284 spin_unlock(&dispc.irq_lock);
3285
3286 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3287 isr_data = &registered_isr[i];
3288
3289 if (!isr_data->isr)
3290 continue;
3291
3292 if (isr_data->mask & irqstatus) {
3293 isr_data->isr(isr_data->arg, irqstatus);
3294 handledirqs |= isr_data->mask;
3295 }
3296 }
3297
3298 spin_lock(&dispc.irq_lock);
3299
3300 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3301
3302 if (unhandled_errors) {
3303 dispc.error_irqs |= unhandled_errors;
3304
3305 dispc.irq_error_mask &= ~unhandled_errors;
3306 _omap_dispc_set_irqs();
3307
3308 schedule_work(&dispc.error_work);
3309 }
3310
3311 spin_unlock(&dispc.irq_lock);
affe360d 3312
3313 return IRQ_HANDLED;
80c39712
TV		 3314}
3315
3316static void dispc_error_worker(struct work_struct *work)
3317{
3318 int i;
3319 u32 errors;
3320 unsigned long flags;
3321
3322 spin_lock_irqsave(&dispc.irq_lock, flags);
3323 errors = dispc.error_irqs;
3324 dispc.error_irqs = 0;
3325 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3326
3327 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
3328 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
3329 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3330 struct omap_overlay *ovl;
3331 ovl = omap_dss_get_overlay(i);
3332
3333 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3334 continue;
3335
3336 if (ovl->id == 0) {
3337 dispc_enable_plane(ovl->id, 0);
3338 dispc_go(ovl->manager->id);
3339 mdelay(50);
3340 break;
3341 }
3342 }
3343 }
3344
3345 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3346 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3347 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3348 struct omap_overlay *ovl;
3349 ovl = omap_dss_get_overlay(i);
3350
3351 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3352 continue;
3353
3354 if (ovl->id == 1) {
3355 dispc_enable_plane(ovl->id, 0);
3356 dispc_go(ovl->manager->id);
3357 mdelay(50);
3358 break;
3359 }
3360 }
3361 }
3362
3363 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3364 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3365 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3366 struct omap_overlay *ovl;
3367 ovl = omap_dss_get_overlay(i);
3368
3369 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3370 continue;
3371
3372 if (ovl->id == 2) {
3373 dispc_enable_plane(ovl->id, 0);
3374 dispc_go(ovl->manager->id);
3375 mdelay(50);
3376 break;
3377 }
3378 }
3379 }
3380
3381 if (errors & DISPC_IRQ_SYNC_LOST) {
3382 struct omap_overlay_manager *manager = NULL;
3383 bool enable = false;
3384
3385 DSSERR("SYNC_LOST, disabling LCD\n");
3386
3387 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3388 struct omap_overlay_manager *mgr;
3389 mgr = omap_dss_get_overlay_manager(i);
3390
3391 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3392 manager = mgr;
3393 enable = mgr->device->state ==
3394 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3395 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3396 break;
3397 }
3398 }
3399
3400 if (manager) {
37ac60e4 3401 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3402 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3403 struct omap_overlay *ovl;
3404 ovl = omap_dss_get_overlay(i);
3405
3406 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3407 continue;
3408
3409 if (ovl->id != 0 && ovl->manager == manager)
3410 dispc_enable_plane(ovl->id, 0);
3411 }
3412
3413 dispc_go(manager->id);
3414 mdelay(50);
3415 if (enable)
37ac60e4 3416 dssdev->driver->enable(dssdev);
80c39712
TV		 3417 }
3418 }
3419
3420 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3421 struct omap_overlay_manager *manager = NULL;
3422 bool enable = false;
3423
3424 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3425
3426 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3427 struct omap_overlay_manager *mgr;
3428 mgr = omap_dss_get_overlay_manager(i);
3429
3430 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3431 manager = mgr;
3432 enable = mgr->device->state ==
3433 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3434 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3435 break;
3436 }
3437 }
3438
3439 if (manager) {
37ac60e4 3440 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3441 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3442 struct omap_overlay *ovl;
3443 ovl = omap_dss_get_overlay(i);
3444
3445 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3446 continue;
3447
3448 if (ovl->id != 0 && ovl->manager == manager)
3449 dispc_enable_plane(ovl->id, 0);
3450 }
3451
3452 dispc_go(manager->id);
3453 mdelay(50);
3454 if (enable)
37ac60e4 3455 dssdev->driver->enable(dssdev);
80c39712
TV		 3456 }
3457 }
3458
2a205f34
SS		 3459 if (errors & DISPC_IRQ_SYNC_LOST2) {
3460 struct omap_overlay_manager *manager = NULL;
3461 bool enable = false;
3462
3463 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3464
3465 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3466 struct omap_overlay_manager *mgr;
3467 mgr = omap_dss_get_overlay_manager(i);
3468
3469 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3470 manager = mgr;
3471 enable = mgr->device->state ==
3472 OMAP_DSS_DISPLAY_ACTIVE;
3473 mgr->device->driver->disable(mgr->device);
3474 break;
3475 }
3476 }
3477
3478 if (manager) {
3479 struct omap_dss_device *dssdev = manager->device;
3480 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3481 struct omap_overlay *ovl;
3482 ovl = omap_dss_get_overlay(i);
3483
3484 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3485 continue;
3486
3487 if (ovl->id != 0 && ovl->manager == manager)
3488 dispc_enable_plane(ovl->id, 0);
3489 }
3490
3491 dispc_go(manager->id);
3492 mdelay(50);
3493 if (enable)
3494 dssdev->driver->enable(dssdev);
3495 }
3496 }
3497
80c39712
TV		 3498 if (errors & DISPC_IRQ_OCP_ERR) {
3499 DSSERR("OCP_ERR\n");
3500 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3501 struct omap_overlay_manager *mgr;
3502 mgr = omap_dss_get_overlay_manager(i);
3503
3504 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3505 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3506 }
3507 }
3508
3509 spin_lock_irqsave(&dispc.irq_lock, flags);
3510 dispc.irq_error_mask |= errors;
3511 _omap_dispc_set_irqs();
3512 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3513}
3514
3515int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3516{
3517 void dispc_irq_wait_handler(void *data, u32 mask)
3518 {
3519 complete((struct completion *)data);
3520 }
3521
3522 int r;
3523 DECLARE_COMPLETION_ONSTACK(completion);
3524
3525 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3526 irqmask);
3527
3528 if (r)
3529 return r;
3530
3531 timeout = wait_for_completion_timeout(&completion, timeout);
3532
3533 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3534
3535 if (timeout == 0)
3536 return -ETIMEDOUT;
3537
3538 if (timeout == -ERESTARTSYS)
3539 return -ERESTARTSYS;
3540
3541 return 0;
3542}
3543
3544int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3545 unsigned long timeout)
3546{
3547 void dispc_irq_wait_handler(void *data, u32 mask)
3548 {
3549 complete((struct completion *)data);
3550 }
3551
3552 int r;
3553 DECLARE_COMPLETION_ONSTACK(completion);
3554
3555 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3556 irqmask);
3557
3558 if (r)
3559 return r;
3560
3561 timeout = wait_for_completion_interruptible_timeout(&completion,
3562 timeout);
3563
3564 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3565
3566 if (timeout == 0)
3567 return -ETIMEDOUT;
3568
3569 if (timeout == -ERESTARTSYS)
3570 return -ERESTARTSYS;
3571
3572 return 0;
3573}
3574
3575#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3576void dispc_fake_vsync_irq(void)
3577{
3578 u32 irqstatus = DISPC_IRQ_VSYNC;
3579 int i;
3580
ab83b14c 3581 WARN_ON(!in_interrupt());
80c39712
TV		 3582
3583 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3584 struct omap_dispc_isr_data *isr_data;
3585 isr_data = &dispc.registered_isr[i];
3586
3587 if (!isr_data->isr)
3588 continue;
3589
3590 if (isr_data->mask & irqstatus)
3591 isr_data->isr(isr_data->arg, irqstatus);
3592 }
80c39712
TV		 3593}
3594#endif
3595
3596static void _omap_dispc_initialize_irq(void)
3597{
3598 unsigned long flags;
3599
3600 spin_lock_irqsave(&dispc.irq_lock, flags);
3601
3602 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3603
3604 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3605 if (dss_has_feature(FEAT_MGR_LCD2))
3606 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3607
3608 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3609 * so clear it */
3610 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3611
3612 _omap_dispc_set_irqs();
3613
3614 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3615}
3616
3617void dispc_enable_sidle(void)
3618{
3619 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3620}
3621
3622void dispc_disable_sidle(void)
3623{
3624 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3625}
3626
3627static void _omap_dispc_initial_config(void)
3628{
3629 u32 l;
3630
0cf35df3
MR		 3631 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3632 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3633 l = dispc_read_reg(DISPC_DIVISOR);
3634 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3635 l = FLD_MOD(l, 1, 0, 0);
3636 l = FLD_MOD(l, 1, 23, 16);
3637 dispc_write_reg(DISPC_DIVISOR, l);
3638 }
3639
80c39712 3640 /* FUNCGATED */
6ced40bf
AT		 3641 if (dss_has_feature(FEAT_FUNCGATED))
3642 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3643
3644 /* L3 firewall setting: enable access to OCM RAM */
3645 /* XXX this should be somewhere in plat-omap */
3646 if (cpu_is_omap24xx())
3647 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3648
3649 _dispc_setup_color_conv_coef();
3650
3651 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3652
3653 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3654
3655 dispc_configure_burst_sizes();
80c39712
TV		 3656}
3657
060b6d9c
SG		 3658/* DISPC HW IP initialisation */
3659static int omap_dispchw_probe(struct platform_device *pdev)
3660{
3661 u32 rev;
affe360d 3662 int r = 0;
ea9da36a 3663 struct resource *dispc_mem;
4fbafaf3 3664 struct clk *clk;
ea9da36a 3665
060b6d9c
SG		 3666 dispc.pdev = pdev;
3667
4fbafaf3
TV		 3668 clk = clk_get(&pdev->dev, "fck");
3669 if (IS_ERR(clk)) {
3670 DSSERR("can't get fck\n");
3671 r = PTR_ERR(clk);
3672 goto err_get_clk;
3673 }
3674
3675 dispc.dss_clk = clk;
3676
060b6d9c
SG		 3677 spin_lock_init(&dispc.irq_lock);
3678
3679#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3680 spin_lock_init(&dispc.irq_stats_lock);
3681 dispc.irq_stats.last_reset = jiffies;
3682#endif
3683
3684 INIT_WORK(&dispc.error_work, dispc_error_worker);
3685
ea9da36a
SG		 3686 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3687 if (!dispc_mem) {
3688 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3689 r = -EINVAL;
4fbafaf3 3690 goto err_ioremap;
ea9da36a
SG		 3691 }
3692 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3693 if (!dispc.base) {
3694 DSSERR("can't ioremap DISPC\n");
affe360d 3695 r = -ENOMEM;
4fbafaf3 3696 goto err_ioremap;
affe360d 3697 }
3698 dispc.irq = platform_get_irq(dispc.pdev, 0);
3699 if (dispc.irq < 0) {
3700 DSSERR("platform_get_irq failed\n");
3701 r = -ENODEV;
4fbafaf3 3702 goto err_irq;
affe360d 3703 }
3704
3705 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3706 "OMAP DISPC", dispc.pdev);
3707 if (r < 0) {
3708 DSSERR("request_irq failed\n");
4fbafaf3 3709 goto err_irq;
060b6d9c
SG		 3710 }
3711
4fbafaf3
TV		 3712 dispc_init_ctx_loss_count();
3713
3714 pm_runtime_enable(&pdev->dev);
3715
3716 r = dispc_runtime_get();
3717 if (r)
3718 goto err_runtime_get;
060b6d9c
SG		 3719
3720 _omap_dispc_initial_config();
3721
3722 _omap_dispc_initialize_irq();
3723
060b6d9c 3724 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3725 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3726 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3727
4fbafaf3 3728 dispc_runtime_put();
060b6d9c
SG		 3729
3730 return 0;
4fbafaf3
TV		 3731
3732err_runtime_get:
3733 pm_runtime_disable(&pdev->dev);
3734 free_irq(dispc.irq, dispc.pdev);
3735err_irq:
affe360d 3736 iounmap(dispc.base);
4fbafaf3
TV		 3737err_ioremap:
3738 clk_put(dispc.dss_clk);
3739err_get_clk:
affe360d 3740 return r;
060b6d9c
SG		 3741}
3742
3743static int omap_dispchw_remove(struct platform_device *pdev)
3744{
4fbafaf3
TV		 3745 pm_runtime_disable(&pdev->dev);
3746
3747 clk_put(dispc.dss_clk);
3748
affe360d 3749 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3750 iounmap(dispc.base);
3751 return 0;
3752}
3753
4fbafaf3
TV		 3754static int dispc_runtime_suspend(struct device *dev)
3755{
3756 dispc_save_context();
3757 clk_disable(dispc.dss_clk);
3758 dss_runtime_put();
3759
3760 return 0;
3761}
3762
3763static int dispc_runtime_resume(struct device *dev)
3764{
3765 int r;
3766
3767 r = dss_runtime_get();
3768 if (r < 0)
3769 return r;
3770
3771 clk_enable(dispc.dss_clk);
3772 if (dispc_need_ctx_restore())
3773 dispc_restore_context();
3774
3775 return 0;
3776}
3777
3778static const struct dev_pm_ops dispc_pm_ops = {
3779 .runtime_suspend = dispc_runtime_suspend,
3780 .runtime_resume = dispc_runtime_resume,
3781};
3782
060b6d9c
SG		 3783static struct platform_driver omap_dispchw_driver = {
3784 .probe = omap_dispchw_probe,
3785 .remove = omap_dispchw_remove,
3786 .driver = {
3787 .name = "omapdss_dispc",
3788 .owner = THIS_MODULE,
4fbafaf3 3789 .pm = &dispc_pm_ops,
060b6d9c
SG		 3790 },
3791};
3792
3793int dispc_init_platform_driver(void)
3794{
3795 return platform_driver_register(&omap_dispchw_driver);
3796}
3797
3798void dispc_uninit_platform_driver(void)
3799{
3800 return platform_driver_unregister(&omap_dispchw_driver);
3801}
Linux kernel - Deliverables
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