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ARM: OMAP2+ Add Primview displays to panel-generic
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
80c39712
TV		 122static void _omap_dispc_set_irqs(void);
123
55978cc2 124static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 125{
55978cc2 126 __raw_writel(val, dispc.base + idx);
80c39712
TV		 127}
128
55978cc2 129static inline u32 dispc_read_reg(const u16 idx)
80c39712 130{
55978cc2 131 return __raw_readl(dispc.base + idx);
80c39712
TV		 132}
133
49ea86f3
TV		 134static int dispc_get_ctx_loss_count(void)
135{
136 struct device *dev = &dispc.pdev->dev;
137 struct omap_display_platform_data *pdata = dev->platform_data;
138 struct omap_dss_board_info *board_data = pdata->board_data;
139 int cnt;
140
141 if (!board_data->get_context_loss_count)
142 return -ENOENT;
143
144 cnt = board_data->get_context_loss_count(dev);
145
146 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
147
148 return cnt;
149}
150
80c39712 151#define SR(reg) \
55978cc2 152 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 153#define RR(reg) \
55978cc2 154 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 155
4fbafaf3 156static void dispc_save_context(void)
80c39712 157{
c6104b8e 158 int i, j;
80c39712 159
4fbafaf3
TV		 160 DSSDBG("dispc_save_context\n");
161
80c39712
TV		 162 SR(IRQENABLE);
163 SR(CONTROL);
164 SR(CONFIG);
80c39712 165 SR(LINE_NUMBER);
11354dd5
AT		 166 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
167 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 168 SR(GLOBAL_ALPHA);
2a205f34
SS		 169 if (dss_has_feature(FEAT_MGR_LCD2)) {
170 SR(CONTROL2);
2a205f34
SS		 171 SR(CONFIG2);
172 }
80c39712 173
c6104b8e
AT		 174 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
175 SR(DEFAULT_COLOR(i));
176 SR(TRANS_COLOR(i));
177 SR(SIZE_MGR(i));
178 if (i == OMAP_DSS_CHANNEL_DIGIT)
179 continue;
180 SR(TIMING_H(i));
181 SR(TIMING_V(i));
182 SR(POL_FREQ(i));
183 SR(DIVISORo(i));
184
185 SR(DATA_CYCLE1(i));
186 SR(DATA_CYCLE2(i));
187 SR(DATA_CYCLE3(i));
188
332e9d70 189 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 190 SR(CPR_COEF_R(i));
191 SR(CPR_COEF_G(i));
192 SR(CPR_COEF_B(i));
332e9d70 193 }
2a205f34 194 }
80c39712 195
c6104b8e
AT		 196 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
197 SR(OVL_BA0(i));
198 SR(OVL_BA1(i));
199 SR(OVL_POSITION(i));
200 SR(OVL_SIZE(i));
201 SR(OVL_ATTRIBUTES(i));
202 SR(OVL_FIFO_THRESHOLD(i));
203 SR(OVL_ROW_INC(i));
204 SR(OVL_PIXEL_INC(i));
205 if (dss_has_feature(FEAT_PRELOAD))
206 SR(OVL_PRELOAD(i));
207 if (i == OMAP_DSS_GFX) {
208 SR(OVL_WINDOW_SKIP(i));
209 SR(OVL_TABLE_BA(i));
210 continue;
211 }
212 SR(OVL_FIR(i));
213 SR(OVL_PICTURE_SIZE(i));
214 SR(OVL_ACCU0(i));
215 SR(OVL_ACCU1(i));
9b372c2d 216
c6104b8e
AT		 217 for (j = 0; j < 8; j++)
218 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 219
c6104b8e
AT		 220 for (j = 0; j < 8; j++)
221 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 222
c6104b8e
AT		 223 for (j = 0; j < 5; j++)
224 SR(OVL_CONV_COEF(i, j));
ab5ca071 225
c6104b8e
AT		 226 if (dss_has_feature(FEAT_FIR_COEF_V)) {
227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V(i, j));
229 }
9b372c2d 230
c6104b8e
AT		 231 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
232 SR(OVL_BA0_UV(i));
233 SR(OVL_BA1_UV(i));
234 SR(OVL_FIR2(i));
235 SR(OVL_ACCU2_0(i));
236 SR(OVL_ACCU2_1(i));
ab5ca071 237
c6104b8e
AT		 238 for (j = 0; j < 8; j++)
239 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 240
c6104b8e
AT		 241 for (j = 0; j < 8; j++)
242 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 243
c6104b8e
AT		 244 for (j = 0; j < 8; j++)
245 SR(OVL_FIR_COEF_V2(i, j));
246 }
247 if (dss_has_feature(FEAT_ATTR2))
248 SR(OVL_ATTRIBUTES2(i));
ab5ca071 249 }
0cf35df3
MR		 250
251 if (dss_has_feature(FEAT_CORE_CLK_DIV))
252 SR(DIVISOR);
49ea86f3
TV		 253
254 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
255 dispc.ctx_valid = true;
256
257 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 258}
259
4fbafaf3 260static void dispc_restore_context(void)
80c39712 261{
c6104b8e 262 int i, j, ctx;
4fbafaf3
TV		 263
264 DSSDBG("dispc_restore_context\n");
265
49ea86f3
TV		 266 if (!dispc.ctx_valid)
267 return;
268
269 ctx = dispc_get_ctx_loss_count();
270
271 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
272 return;
273
274 DSSDBG("ctx_loss_count: saved %d, current %d\n",
275 dispc.ctx_loss_cnt, ctx);
276
75c7d59d 277 /*RR(IRQENABLE);*/
80c39712
TV		 278 /*RR(CONTROL);*/
279 RR(CONFIG);
80c39712 280 RR(LINE_NUMBER);
11354dd5
AT		 281 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
282 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 283 RR(GLOBAL_ALPHA);
c6104b8e 284 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 285 RR(CONFIG2);
80c39712 286
c6104b8e
AT		 287 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
288 RR(DEFAULT_COLOR(i));
289 RR(TRANS_COLOR(i));
290 RR(SIZE_MGR(i));
291 if (i == OMAP_DSS_CHANNEL_DIGIT)
292 continue;
293 RR(TIMING_H(i));
294 RR(TIMING_V(i));
295 RR(POL_FREQ(i));
296 RR(DIVISORo(i));
297
298 RR(DATA_CYCLE1(i));
299 RR(DATA_CYCLE2(i));
300 RR(DATA_CYCLE3(i));
2a205f34 301
332e9d70 302 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 303 RR(CPR_COEF_R(i));
304 RR(CPR_COEF_G(i));
305 RR(CPR_COEF_B(i));
332e9d70 306 }
2a205f34 307 }
80c39712 308
c6104b8e
AT		 309 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
310 RR(OVL_BA0(i));
311 RR(OVL_BA1(i));
312 RR(OVL_POSITION(i));
313 RR(OVL_SIZE(i));
314 RR(OVL_ATTRIBUTES(i));
315 RR(OVL_FIFO_THRESHOLD(i));
316 RR(OVL_ROW_INC(i));
317 RR(OVL_PIXEL_INC(i));
318 if (dss_has_feature(FEAT_PRELOAD))
319 RR(OVL_PRELOAD(i));
320 if (i == OMAP_DSS_GFX) {
321 RR(OVL_WINDOW_SKIP(i));
322 RR(OVL_TABLE_BA(i));
323 continue;
324 }
325 RR(OVL_FIR(i));
326 RR(OVL_PICTURE_SIZE(i));
327 RR(OVL_ACCU0(i));
328 RR(OVL_ACCU1(i));
9b372c2d 329
c6104b8e
AT		 330 for (j = 0; j < 8; j++)
331 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 332
c6104b8e
AT		 333 for (j = 0; j < 8; j++)
334 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 335
c6104b8e
AT		 336 for (j = 0; j < 5; j++)
337 RR(OVL_CONV_COEF(i, j));
ab5ca071 338
c6104b8e
AT		 339 if (dss_has_feature(FEAT_FIR_COEF_V)) {
340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V(i, j));
342 }
9b372c2d 343
c6104b8e
AT		 344 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
345 RR(OVL_BA0_UV(i));
346 RR(OVL_BA1_UV(i));
347 RR(OVL_FIR2(i));
348 RR(OVL_ACCU2_0(i));
349 RR(OVL_ACCU2_1(i));
ab5ca071 350
c6104b8e
AT		 351 for (j = 0; j < 8; j++)
352 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 353
c6104b8e
AT		 354 for (j = 0; j < 8; j++)
355 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 356
c6104b8e
AT		 357 for (j = 0; j < 8; j++)
358 RR(OVL_FIR_COEF_V2(i, j));
359 }
360 if (dss_has_feature(FEAT_ATTR2))
361 RR(OVL_ATTRIBUTES2(i));
ab5ca071 362 }
80c39712 363
0cf35df3
MR		 364 if (dss_has_feature(FEAT_CORE_CLK_DIV))
365 RR(DIVISOR);
366
80c39712
TV		 367 /* enable last, because LCD & DIGIT enable are here */
368 RR(CONTROL);
2a205f34
SS		 369 if (dss_has_feature(FEAT_MGR_LCD2))
370 RR(CONTROL2);
75c7d59d
VS		 371 /* clear spurious SYNC_LOST_DIGIT interrupts */
372 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
373
374 /*
375 * enable last so IRQs won't trigger before
376 * the context is fully restored
377 */
378 RR(IRQENABLE);
49ea86f3
TV		 379
380 DSSDBG("context restored\n");
80c39712
TV		 381}
382
383#undef SR
384#undef RR
385
4fbafaf3
TV		 386int dispc_runtime_get(void)
387{
388 int r;
389
390 DSSDBG("dispc_runtime_get\n");
391
392 r = pm_runtime_get_sync(&dispc.pdev->dev);
393 WARN_ON(r < 0);
394 return r < 0 ? r : 0;
395}
396
397void dispc_runtime_put(void)
398{
399 int r;
400
401 DSSDBG("dispc_runtime_put\n");
402
0eaf9f52 403 r = pm_runtime_put_sync(&dispc.pdev->dev);
4fbafaf3 404 WARN_ON(r < 0);
80c39712
TV		 405}
406
dac57a05
AT		 407static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
408{
409 if (channel == OMAP_DSS_CHANNEL_LCD ||
410 channel == OMAP_DSS_CHANNEL_LCD2)
411 return true;
412 else
413 return false;
414}
4fbafaf3 415
c3dc6a7a
AT		 416static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
417{
418 struct omap_overlay_manager *mgr =
419 omap_dss_get_overlay_manager(channel);
420
421 return mgr ? mgr->device : NULL;
422}
423
3dcec4d6
TV		 424u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
425{
426 switch (channel) {
427 case OMAP_DSS_CHANNEL_LCD:
428 return DISPC_IRQ_VSYNC;
429 case OMAP_DSS_CHANNEL_LCD2:
430 return DISPC_IRQ_VSYNC2;
431 case OMAP_DSS_CHANNEL_DIGIT:
432 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
433 default:
434 BUG();
435 }
436}
437
7d1365c9
TV		 438u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
439{
440 switch (channel) {
441 case OMAP_DSS_CHANNEL_LCD:
442 return DISPC_IRQ_FRAMEDONE;
443 case OMAP_DSS_CHANNEL_LCD2:
444 return DISPC_IRQ_FRAMEDONE2;
445 case OMAP_DSS_CHANNEL_DIGIT:
446 return 0;
447 default:
448 BUG();
449 }
450}
451
26d9dd0d 452bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 453{
454 int bit;
455
dac57a05 456 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 457 bit = 5; /* GOLCD */
458 else
459 bit = 6; /* GODIGIT */
460
2a205f34
SS		 461 if (channel == OMAP_DSS_CHANNEL_LCD2)
462 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
463 else
464 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 465}
466
26d9dd0d 467void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 468{
469 int bit;
2a205f34 470 bool enable_bit, go_bit;
80c39712 471
dac57a05 472 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 473 bit = 0; /* LCDENABLE */
474 else
475 bit = 1; /* DIGITALENABLE */
476
477 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 478 if (channel == OMAP_DSS_CHANNEL_LCD2)
479 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
480 else
481 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
482
483 if (!enable_bit)
e6d80f95 484 return;
80c39712 485
dac57a05 486 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 487 bit = 5; /* GOLCD */
488 else
489 bit = 6; /* GODIGIT */
490
2a205f34
SS		 491 if (channel == OMAP_DSS_CHANNEL_LCD2)
492 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
493 else
494 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
495
496 if (go_bit) {
80c39712 497 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 498 return;
80c39712
TV		 499 }
500
2a205f34
SS		 501 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
502 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 503
2a205f34
SS		 504 if (channel == OMAP_DSS_CHANNEL_LCD2)
505 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
506 else
507 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 508}
509
f0e5caab 510static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 511{
9b372c2d 512 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 513}
514
f0e5caab 515static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 516{
9b372c2d 517 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 518}
519
f0e5caab 520static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 521{
9b372c2d 522 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 523}
524
f0e5caab 525static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 526{
527 BUG_ON(plane == OMAP_DSS_GFX);
528
529 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
530}
531
f0e5caab
TV		 532static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
533 u32 value)
ab5ca071
AJ		 534{
535 BUG_ON(plane == OMAP_DSS_GFX);
536
537 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
538}
539
f0e5caab 540static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 541{
542 BUG_ON(plane == OMAP_DSS_GFX);
543
544 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
545}
546
debd9074
CM		 547static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
548 int fir_vinc, int five_taps,
549 enum omap_color_component color_comp)
80c39712 550{
debd9074 551 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 552 int i;
553
debd9074
CM		 554 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
555 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 556
557 for (i = 0; i < 8; i++) {
558 u32 h, hv;
559
debd9074
CM		 560 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
561 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
562 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
563 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
564 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
565 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
566 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
567 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 568
0d66cbb5 569 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 570 dispc_ovl_write_firh_reg(plane, i, h);
571 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 572 } else {
f0e5caab
TV		 573 dispc_ovl_write_firh2_reg(plane, i, h);
574 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 575 }
576
80c39712
TV		 577 }
578
66be8f6c
GI		 579 if (five_taps) {
580 for (i = 0; i < 8; i++) {
581 u32 v;
debd9074
CM		 582 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
583 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 584 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 585 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 586 else
f0e5caab 587 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 588 }
80c39712
TV		 589 }
590}
591
592static void _dispc_setup_color_conv_coef(void)
593{
ac01c29e 594 int i;
80c39712
TV		 595 const struct color_conv_coef {
596 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
597 int full_range;
598 } ctbl_bt601_5 = {
599 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
600 };
601
602 const struct color_conv_coef *ct;
603
604#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
605
606 ct = &ctbl_bt601_5;
607
ac01c29e
AT		 608 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
609 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
610 CVAL(ct->rcr, ct->ry));
611 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
612 CVAL(ct->gy, ct->rcb));
613 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
614 CVAL(ct->gcb, ct->gcr));
615 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
616 CVAL(ct->bcr, ct->by));
617 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
618 CVAL(0, ct->bcb));
619
620 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
621 11, 11);
622 }
80c39712
TV		 623
624#undef CVAL
80c39712
TV		 625}
626
627
f0e5caab 628static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 629{
9b372c2d 630 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 631}
632
f0e5caab 633static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 634{
9b372c2d 635 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 636}
637
f0e5caab 638static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 639{
640 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
641}
642
f0e5caab 643static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 644{
645 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
646}
647
f0e5caab 648static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 649{
80c39712 650 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 651
652 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 653}
654
f0e5caab 655static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 656{
80c39712 657 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 658
659 if (plane == OMAP_DSS_GFX)
660 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
661 else
662 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 663}
664
f0e5caab 665static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 666{
667 u32 val;
80c39712
TV		 668
669 BUG_ON(plane == OMAP_DSS_GFX);
670
671 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 672
673 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 674}
675
54128701
AT		 676static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
677{
678 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
679
680 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
681 return;
682
683 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
684}
685
686static void dispc_ovl_enable_zorder_planes(void)
687{
688 int i;
689
690 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
691 return;
692
693 for (i = 0; i < dss_feat_get_num_ovls(); i++)
694 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
695}
696
f0e5caab 697static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 698{
f6dc8150 699 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 700
f6dc8150 701 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 702 return;
703
9b372c2d 704 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 705}
706
f0e5caab 707static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 708{
b8c095b4 709 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 710 int shift;
f6dc8150 711 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 712
f6dc8150 713 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 714 return;
a0acb557 715
fe3cc9d6
TV		 716 shift = shifts[plane];
717 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 718}
719
f0e5caab 720static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 721{
9b372c2d 722 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 723}
724
f0e5caab 725static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 726{
9b372c2d 727 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 728}
729
f0e5caab 730static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 731 enum omap_color_mode color_mode)
732{
733 u32 m = 0;
f20e4220
AJ		 734 if (plane != OMAP_DSS_GFX) {
735 switch (color_mode) {
736 case OMAP_DSS_COLOR_NV12:
737 m = 0x0; break;
08f3267e 738 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 739 m = 0x1; break;
740 case OMAP_DSS_COLOR_RGBA16:
741 m = 0x2; break;
08f3267e 742 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 743 m = 0x4; break;
744 case OMAP_DSS_COLOR_ARGB16:
745 m = 0x5; break;
746 case OMAP_DSS_COLOR_RGB16:
747 m = 0x6; break;
748 case OMAP_DSS_COLOR_ARGB16_1555:
749 m = 0x7; break;
750 case OMAP_DSS_COLOR_RGB24U:
751 m = 0x8; break;
752 case OMAP_DSS_COLOR_RGB24P:
753 m = 0x9; break;
754 case OMAP_DSS_COLOR_YUV2:
755 m = 0xa; break;
756 case OMAP_DSS_COLOR_UYVY:
757 m = 0xb; break;
758 case OMAP_DSS_COLOR_ARGB32:
759 m = 0xc; break;
760 case OMAP_DSS_COLOR_RGBA32:
761 m = 0xd; break;
762 case OMAP_DSS_COLOR_RGBX32:
763 m = 0xe; break;
764 case OMAP_DSS_COLOR_XRGB16_1555:
765 m = 0xf; break;
766 default:
767 BUG(); break;
768 }
769 } else {
770 switch (color_mode) {
771 case OMAP_DSS_COLOR_CLUT1:
772 m = 0x0; break;
773 case OMAP_DSS_COLOR_CLUT2:
774 m = 0x1; break;
775 case OMAP_DSS_COLOR_CLUT4:
776 m = 0x2; break;
777 case OMAP_DSS_COLOR_CLUT8:
778 m = 0x3; break;
779 case OMAP_DSS_COLOR_RGB12U:
780 m = 0x4; break;
781 case OMAP_DSS_COLOR_ARGB16:
782 m = 0x5; break;
783 case OMAP_DSS_COLOR_RGB16:
784 m = 0x6; break;
785 case OMAP_DSS_COLOR_ARGB16_1555:
786 m = 0x7; break;
787 case OMAP_DSS_COLOR_RGB24U:
788 m = 0x8; break;
789 case OMAP_DSS_COLOR_RGB24P:
790 m = 0x9; break;
08f3267e 791 case OMAP_DSS_COLOR_RGBX16:
f20e4220 792 m = 0xa; break;
08f3267e 793 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 794 m = 0xb; break;
795 case OMAP_DSS_COLOR_ARGB32:
796 m = 0xc; break;
797 case OMAP_DSS_COLOR_RGBA32:
798 m = 0xd; break;
799 case OMAP_DSS_COLOR_RGBX32:
800 m = 0xe; break;
801 case OMAP_DSS_COLOR_XRGB16_1555:
802 m = 0xf; break;
803 default:
804 BUG(); break;
805 }
80c39712
TV		 806 }
807
9b372c2d 808 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 809}
810
f427984e 811void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 812{
813 int shift;
814 u32 val;
2a205f34 815 int chan = 0, chan2 = 0;
80c39712
TV		 816
817 switch (plane) {
818 case OMAP_DSS_GFX:
819 shift = 8;
820 break;
821 case OMAP_DSS_VIDEO1:
822 case OMAP_DSS_VIDEO2:
b8c095b4 823 case OMAP_DSS_VIDEO3:
80c39712
TV		 824 shift = 16;
825 break;
826 default:
827 BUG();
828 return;
829 }
830
9b372c2d 831 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 832 if (dss_has_feature(FEAT_MGR_LCD2)) {
833 switch (channel) {
834 case OMAP_DSS_CHANNEL_LCD:
835 chan = 0;
836 chan2 = 0;
837 break;
838 case OMAP_DSS_CHANNEL_DIGIT:
839 chan = 1;
840 chan2 = 0;
841 break;
842 case OMAP_DSS_CHANNEL_LCD2:
843 chan = 0;
844 chan2 = 1;
845 break;
846 default:
847 BUG();
848 }
849
850 val = FLD_MOD(val, chan, shift, shift);
851 val = FLD_MOD(val, chan2, 31, 30);
852 } else {
853 val = FLD_MOD(val, channel, shift, shift);
854 }
9b372c2d 855 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 856}
857
2cc5d1af
TV		 858static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
859{
860 int shift;
861 u32 val;
862 enum omap_channel channel;
863
864 switch (plane) {
865 case OMAP_DSS_GFX:
866 shift = 8;
867 break;
868 case OMAP_DSS_VIDEO1:
869 case OMAP_DSS_VIDEO2:
870 case OMAP_DSS_VIDEO3:
871 shift = 16;
872 break;
873 default:
874 BUG();
875 }
876
877 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
878
879 if (dss_has_feature(FEAT_MGR_LCD2)) {
880 if (FLD_GET(val, 31, 30) == 0)
881 channel = FLD_GET(val, shift, shift);
882 else
883 channel = OMAP_DSS_CHANNEL_LCD2;
884 } else {
885 channel = FLD_GET(val, shift, shift);
886 }
887
888 return channel;
889}
890
f0e5caab 891static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 892 enum omap_burst_size burst_size)
893{
b8c095b4 894 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 895 int shift;
80c39712 896
fe3cc9d6 897 shift = shifts[plane];
5ed8cf5b 898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 899}
900
5ed8cf5b
TV		 901static void dispc_configure_burst_sizes(void)
902{
903 int i;
904 const int burst_size = BURST_SIZE_X8;
905
906 /* Configure burst size always to maximum size */
907 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 908 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 909}
910
83fa2f2e 911static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 912{
913 unsigned unit = dss_feat_get_burst_size_unit();
914 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
915 return unit * 8;
916}
917
d3862610
M		 918void dispc_enable_gamma_table(bool enable)
919{
920 /*
921 * This is partially implemented to support only disabling of
922 * the gamma table.
923 */
924 if (enable) {
925 DSSWARN("Gamma table enabling for TV not yet supported");
926 return;
927 }
928
929 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
930}
931
c64dca40 932static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 933{
934 u16 reg;
935
936 if (channel == OMAP_DSS_CHANNEL_LCD)
937 reg = DISPC_CONFIG;
938 else if (channel == OMAP_DSS_CHANNEL_LCD2)
939 reg = DISPC_CONFIG2;
940 else
941 return;
942
943 REG_FLD_MOD(reg, enable, 15, 15);
944}
945
c64dca40 946static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 947 struct omap_dss_cpr_coefs *coefs)
948{
949 u32 coef_r, coef_g, coef_b;
950
dac57a05 951 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 952 return;
953
954 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
955 FLD_VAL(coefs->rb, 9, 0);
956 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
957 FLD_VAL(coefs->gb, 9, 0);
958 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
959 FLD_VAL(coefs->bb, 9, 0);
960
961 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
962 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
963 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
964}
965
f0e5caab 966static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 967{
968 u32 val;
969
970 BUG_ON(plane == OMAP_DSS_GFX);
971
9b372c2d 972 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 973 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 974 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 975}
976
c3d92529 977static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 978{
b8c095b4 979 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 980 int shift;
80c39712 981
fe3cc9d6
TV		 982 shift = shifts[plane];
983 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 984}
985
8f366162 986static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 987 u16 height)
80c39712
TV		 988{
989 u32 val;
80c39712 990
80c39712 991 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 992 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 993}
994
995static void dispc_read_plane_fifo_sizes(void)
996{
80c39712
TV		 997 u32 size;
998 int plane;
a0acb557 999 u8 start, end;
5ed8cf5b
TV		 1000 u32 unit;
1001
1002 unit = dss_feat_get_buffer_size_unit();
80c39712 1003
a0acb557 1004 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1005
e13a138b 1006 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1007 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1008 size *= unit;
80c39712
TV		 1009 dispc.fifo_size[plane] = size;
1010 }
80c39712
TV		 1011}
1012
83fa2f2e 1013static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1014{
1015 return dispc.fifo_size[plane];
1016}
1017
6f04e1bf 1018void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1019{
a0acb557 1020 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1021 u32 unit;
1022
1023 unit = dss_feat_get_buffer_size_unit();
1024
1025 WARN_ON(low % unit != 0);
1026 WARN_ON(high % unit != 0);
1027
1028 low /= unit;
1029 high /= unit;
a0acb557 1030
9b372c2d
AT		 1031 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1032 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1033
3cb5d966 1034 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1035 plane,
9b372c2d 1036 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1037 lo_start, lo_end) * unit,
9b372c2d 1038 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1039 hi_start, hi_end) * unit,
1040 low * unit, high * unit);
80c39712 1041
9b372c2d 1042 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1043 FLD_VAL(high, hi_start, hi_end) |
1044 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1045}
1046
1047void dispc_enable_fifomerge(bool enable)
1048{
e6b0f884
TV		 1049 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1050 WARN_ON(enable);
1051 return;
1052 }
1053
80c39712
TV		 1054 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1055 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1056}
1057
83fa2f2e
TV		 1058void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1059 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
1060{
1061 /*
1062 * All sizes are in bytes. Both the buffer and burst are made of
1063 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1064 */
1065
1066 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1067 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1068 int i;
83fa2f2e
TV		 1069
1070 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1071 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1072
e0e405b9
TV		 1073 if (use_fifomerge) {
1074 total_fifo_size = 0;
1075 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1076 total_fifo_size += dispc_ovl_get_fifo_size(i);
1077 } else {
1078 total_fifo_size = ovl_fifo_size;
1079 }
1080
1081 /*
1082 * We use the same low threshold for both fifomerge and non-fifomerge
1083 * cases, but for fifomerge we calculate the high threshold using the
1084 * combined fifo size
1085 */
1086
1087 if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1088 *fifo_low = ovl_fifo_size - burst_size * 2;
1089 *fifo_high = total_fifo_size - burst_size;
1090 } else {
1091 *fifo_low = ovl_fifo_size - burst_size;
1092 *fifo_high = total_fifo_size - buf_unit;
1093 }
83fa2f2e
TV		 1094}
1095
f0e5caab 1096static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1097 int hinc, int vinc,
1098 enum omap_color_component color_comp)
80c39712
TV		 1099{
1100 u32 val;
80c39712 1101
0d66cbb5
AJ		 1102 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1103 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1104
0d66cbb5
AJ		 1105 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1106 &hinc_start, &hinc_end);
1107 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1108 &vinc_start, &vinc_end);
1109 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1110 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1111
0d66cbb5
AJ		 1112 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1113 } else {
1114 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1115 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1116 }
80c39712
TV		 1117}
1118
f0e5caab 1119static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1120{
1121 u32 val;
87a7484b 1122 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1123
87a7484b
AT		 1124 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1125 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1126
1127 val = FLD_VAL(vaccu, vert_start, vert_end) |
1128 FLD_VAL(haccu, hor_start, hor_end);
1129
9b372c2d 1130 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1131}
1132
f0e5caab 1133static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1134{
1135 u32 val;
87a7484b 1136 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1137
87a7484b
AT		 1138 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1139 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1140
1141 val = FLD_VAL(vaccu, vert_start, vert_end) |
1142 FLD_VAL(haccu, hor_start, hor_end);
1143
9b372c2d 1144 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1145}
1146
f0e5caab
TV		 1147static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1148 int vaccu)
ab5ca071
AJ		 1149{
1150 u32 val;
1151
1152 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1153 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1154}
1155
f0e5caab
TV		 1156static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1157 int vaccu)
ab5ca071
AJ		 1158{
1159 u32 val;
1160
1161 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1162 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1163}
80c39712 1164
f0e5caab 1165static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1166 u16 orig_width, u16 orig_height,
1167 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1168 bool five_taps, u8 rotation,
1169 enum omap_color_component color_comp)
80c39712 1170{
0d66cbb5 1171 int fir_hinc, fir_vinc;
80c39712 1172
ed14a3ce
AJ		 1173 fir_hinc = 1024 * orig_width / out_width;
1174 fir_vinc = 1024 * orig_height / out_height;
80c39712 1175
debd9074
CM		 1176 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1177 color_comp);
f0e5caab 1178 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1179}
1180
f0e5caab 1181static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1182 u16 orig_width, u16 orig_height,
1183 u16 out_width, u16 out_height,
1184 bool ilace, bool five_taps,
1185 bool fieldmode, enum omap_color_mode color_mode,
1186 u8 rotation)
1187{
1188 int accu0 = 0;
1189 int accu1 = 0;
1190 u32 l;
80c39712 1191
f0e5caab 1192 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1193 out_width, out_height, five_taps,
1194 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1195 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1196
87a7484b
AT		 1197 /* RESIZEENABLE and VERTICALTAPS */
1198 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1199 l |= (orig_width != out_width) ? (1 << 5) : 0;
1200 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1201 l |= five_taps ? (1 << 21) : 0;
80c39712 1202
87a7484b
AT		 1203 /* VRESIZECONF and HRESIZECONF */
1204 if (dss_has_feature(FEAT_RESIZECONF)) {
1205 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1206 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1207 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1208 }
80c39712 1209
87a7484b
AT		 1210 /* LINEBUFFERSPLIT */
1211 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1212 l &= ~(0x1 << 22);
1213 l |= five_taps ? (1 << 22) : 0;
1214 }
80c39712 1215
9b372c2d 1216 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1217
1218 /*
1219 * field 0 = even field = bottom field
1220 * field 1 = odd field = top field
1221 */
1222 if (ilace && !fieldmode) {
1223 accu1 = 0;
0d66cbb5 1224 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1225 if (accu0 >= 1024/2) {
1226 accu1 = 1024/2;
1227 accu0 -= accu1;
1228 }
1229 }
1230
f0e5caab
TV		 1231 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1232 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1233}
1234
f0e5caab 1235static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1236 u16 orig_width, u16 orig_height,
1237 u16 out_width, u16 out_height,
1238 bool ilace, bool five_taps,
1239 bool fieldmode, enum omap_color_mode color_mode,
1240 u8 rotation)
1241{
1242 int scale_x = out_width != orig_width;
1243 int scale_y = out_height != orig_height;
1244
1245 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1246 return;
1247 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1248 color_mode != OMAP_DSS_COLOR_UYVY &&
1249 color_mode != OMAP_DSS_COLOR_NV12)) {
1250 /* reset chroma resampling for RGB formats */
1251 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1252 return;
1253 }
1254 switch (color_mode) {
1255 case OMAP_DSS_COLOR_NV12:
1256 /* UV is subsampled by 2 vertically*/
1257 orig_height >>= 1;
1258 /* UV is subsampled by 2 horz.*/
1259 orig_width >>= 1;
1260 break;
1261 case OMAP_DSS_COLOR_YUV2:
1262 case OMAP_DSS_COLOR_UYVY:
1263 /*For YUV422 with 90/270 rotation,
1264 *we don't upsample chroma
1265 */
1266 if (rotation == OMAP_DSS_ROT_0 ||
1267 rotation == OMAP_DSS_ROT_180)
1268 /* UV is subsampled by 2 hrz*/
1269 orig_width >>= 1;
1270 /* must use FIR for YUV422 if rotated */
1271 if (rotation != OMAP_DSS_ROT_0)
1272 scale_x = scale_y = true;
1273 break;
1274 default:
1275 BUG();
1276 }
1277
1278 if (out_width != orig_width)
1279 scale_x = true;
1280 if (out_height != orig_height)
1281 scale_y = true;
1282
f0e5caab 1283 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1284 out_width, out_height, five_taps,
1285 rotation, DISPC_COLOR_COMPONENT_UV);
1286
1287 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1288 (scale_x || scale_y) ? 1 : 0, 8, 8);
1289 /* set H scaling */
1290 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1291 /* set V scaling */
1292 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1293
f0e5caab
TV		 1294 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1295 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
0d66cbb5
AJ		 1296}
1297
f0e5caab 1298static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1299 u16 orig_width, u16 orig_height,
1300 u16 out_width, u16 out_height,
1301 bool ilace, bool five_taps,
1302 bool fieldmode, enum omap_color_mode color_mode,
1303 u8 rotation)
1304{
1305 BUG_ON(plane == OMAP_DSS_GFX);
1306
f0e5caab 1307 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1308 orig_width, orig_height,
1309 out_width, out_height,
1310 ilace, five_taps,
1311 fieldmode, color_mode,
1312 rotation);
1313
f0e5caab 1314 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1315 orig_width, orig_height,
1316 out_width, out_height,
1317 ilace, five_taps,
1318 fieldmode, color_mode,
1319 rotation);
1320}
1321
f0e5caab 1322static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1323 bool mirroring, enum omap_color_mode color_mode)
1324{
87a7484b
AT		 1325 bool row_repeat = false;
1326 int vidrot = 0;
1327
80c39712
TV		 1328 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1329 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1330
1331 if (mirroring) {
1332 switch (rotation) {
1333 case OMAP_DSS_ROT_0:
1334 vidrot = 2;
1335 break;
1336 case OMAP_DSS_ROT_90:
1337 vidrot = 1;
1338 break;
1339 case OMAP_DSS_ROT_180:
1340 vidrot = 0;
1341 break;
1342 case OMAP_DSS_ROT_270:
1343 vidrot = 3;
1344 break;
1345 }
1346 } else {
1347 switch (rotation) {
1348 case OMAP_DSS_ROT_0:
1349 vidrot = 0;
1350 break;
1351 case OMAP_DSS_ROT_90:
1352 vidrot = 1;
1353 break;
1354 case OMAP_DSS_ROT_180:
1355 vidrot = 2;
1356 break;
1357 case OMAP_DSS_ROT_270:
1358 vidrot = 3;
1359 break;
1360 }
1361 }
1362
80c39712 1363 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1364 row_repeat = true;
80c39712 1365 else
87a7484b 1366 row_repeat = false;
80c39712 1367 }
87a7484b 1368
9b372c2d 1369 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1370 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1371 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1372 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1373}
1374
1375static int color_mode_to_bpp(enum omap_color_mode color_mode)
1376{
1377 switch (color_mode) {
1378 case OMAP_DSS_COLOR_CLUT1:
1379 return 1;
1380 case OMAP_DSS_COLOR_CLUT2:
1381 return 2;
1382 case OMAP_DSS_COLOR_CLUT4:
1383 return 4;
1384 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1385 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1386 return 8;
1387 case OMAP_DSS_COLOR_RGB12U:
1388 case OMAP_DSS_COLOR_RGB16:
1389 case OMAP_DSS_COLOR_ARGB16:
1390 case OMAP_DSS_COLOR_YUV2:
1391 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1392 case OMAP_DSS_COLOR_RGBA16:
1393 case OMAP_DSS_COLOR_RGBX16:
1394 case OMAP_DSS_COLOR_ARGB16_1555:
1395 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1396 return 16;
1397 case OMAP_DSS_COLOR_RGB24P:
1398 return 24;
1399 case OMAP_DSS_COLOR_RGB24U:
1400 case OMAP_DSS_COLOR_ARGB32:
1401 case OMAP_DSS_COLOR_RGBA32:
1402 case OMAP_DSS_COLOR_RGBX32:
1403 return 32;
1404 default:
1405 BUG();
1406 }
1407}
1408
1409static s32 pixinc(int pixels, u8 ps)
1410{
1411 if (pixels == 1)
1412 return 1;
1413 else if (pixels > 1)
1414 return 1 + (pixels - 1) * ps;
1415 else if (pixels < 0)
1416 return 1 - (-pixels + 1) * ps;
1417 else
1418 BUG();
1419}
1420
1421static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1422 u16 screen_width,
1423 u16 width, u16 height,
1424 enum omap_color_mode color_mode, bool fieldmode,
1425 unsigned int field_offset,
1426 unsigned *offset0, unsigned *offset1,
1427 s32 *row_inc, s32 *pix_inc)
1428{
1429 u8 ps;
1430
1431 /* FIXME CLUT formats */
1432 switch (color_mode) {
1433 case OMAP_DSS_COLOR_CLUT1:
1434 case OMAP_DSS_COLOR_CLUT2:
1435 case OMAP_DSS_COLOR_CLUT4:
1436 case OMAP_DSS_COLOR_CLUT8:
1437 BUG();
1438 return;
1439 case OMAP_DSS_COLOR_YUV2:
1440 case OMAP_DSS_COLOR_UYVY:
1441 ps = 4;
1442 break;
1443 default:
1444 ps = color_mode_to_bpp(color_mode) / 8;
1445 break;
1446 }
1447
1448 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1449 width, height);
1450
1451 /*
1452 * field 0 = even field = bottom field
1453 * field 1 = odd field = top field
1454 */
1455 switch (rotation + mirror * 4) {
1456 case OMAP_DSS_ROT_0:
1457 case OMAP_DSS_ROT_180:
1458 /*
1459 * If the pixel format is YUV or UYVY divide the width
1460 * of the image by 2 for 0 and 180 degree rotation.
1461 */
1462 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1463 color_mode == OMAP_DSS_COLOR_UYVY)
1464 width = width >> 1;
1465 case OMAP_DSS_ROT_90:
1466 case OMAP_DSS_ROT_270:
1467 *offset1 = 0;
1468 if (field_offset)
1469 *offset0 = field_offset * screen_width * ps;
1470 else
1471 *offset0 = 0;
1472
1473 *row_inc = pixinc(1 + (screen_width - width) +
1474 (fieldmode ? screen_width : 0),
1475 ps);
1476 *pix_inc = pixinc(1, ps);
1477 break;
1478
1479 case OMAP_DSS_ROT_0 + 4:
1480 case OMAP_DSS_ROT_180 + 4:
1481 /* If the pixel format is YUV or UYVY divide the width
1482 * of the image by 2 for 0 degree and 180 degree
1483 */
1484 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1485 color_mode == OMAP_DSS_COLOR_UYVY)
1486 width = width >> 1;
1487 case OMAP_DSS_ROT_90 + 4:
1488 case OMAP_DSS_ROT_270 + 4:
1489 *offset1 = 0;
1490 if (field_offset)
1491 *offset0 = field_offset * screen_width * ps;
1492 else
1493 *offset0 = 0;
1494 *row_inc = pixinc(1 - (screen_width + width) -
1495 (fieldmode ? screen_width : 0),
1496 ps);
1497 *pix_inc = pixinc(1, ps);
1498 break;
1499
1500 default:
1501 BUG();
1502 }
1503}
1504
1505static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1506 u16 screen_width,
1507 u16 width, u16 height,
1508 enum omap_color_mode color_mode, bool fieldmode,
1509 unsigned int field_offset,
1510 unsigned *offset0, unsigned *offset1,
1511 s32 *row_inc, s32 *pix_inc)
1512{
1513 u8 ps;
1514 u16 fbw, fbh;
1515
1516 /* FIXME CLUT formats */
1517 switch (color_mode) {
1518 case OMAP_DSS_COLOR_CLUT1:
1519 case OMAP_DSS_COLOR_CLUT2:
1520 case OMAP_DSS_COLOR_CLUT4:
1521 case OMAP_DSS_COLOR_CLUT8:
1522 BUG();
1523 return;
1524 default:
1525 ps = color_mode_to_bpp(color_mode) / 8;
1526 break;
1527 }
1528
1529 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1530 width, height);
1531
1532 /* width & height are overlay sizes, convert to fb sizes */
1533
1534 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1535 fbw = width;
1536 fbh = height;
1537 } else {
1538 fbw = height;
1539 fbh = width;
1540 }
1541
1542 /*
1543 * field 0 = even field = bottom field
1544 * field 1 = odd field = top field
1545 */
1546 switch (rotation + mirror * 4) {
1547 case OMAP_DSS_ROT_0:
1548 *offset1 = 0;
1549 if (field_offset)
1550 *offset0 = *offset1 + field_offset * screen_width * ps;
1551 else
1552 *offset0 = *offset1;
1553 *row_inc = pixinc(1 + (screen_width - fbw) +
1554 (fieldmode ? screen_width : 0),
1555 ps);
1556 *pix_inc = pixinc(1, ps);
1557 break;
1558 case OMAP_DSS_ROT_90:
1559 *offset1 = screen_width * (fbh - 1) * ps;
1560 if (field_offset)
1561 *offset0 = *offset1 + field_offset * ps;
1562 else
1563 *offset0 = *offset1;
1564 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1565 (fieldmode ? 1 : 0), ps);
1566 *pix_inc = pixinc(-screen_width, ps);
1567 break;
1568 case OMAP_DSS_ROT_180:
1569 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1570 if (field_offset)
1571 *offset0 = *offset1 - field_offset * screen_width * ps;
1572 else
1573 *offset0 = *offset1;
1574 *row_inc = pixinc(-1 -
1575 (screen_width - fbw) -
1576 (fieldmode ? screen_width : 0),
1577 ps);
1578 *pix_inc = pixinc(-1, ps);
1579 break;
1580 case OMAP_DSS_ROT_270:
1581 *offset1 = (fbw - 1) * ps;
1582 if (field_offset)
1583 *offset0 = *offset1 - field_offset * ps;
1584 else
1585 *offset0 = *offset1;
1586 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1587 (fieldmode ? 1 : 0), ps);
1588 *pix_inc = pixinc(screen_width, ps);
1589 break;
1590
1591 /* mirroring */
1592 case OMAP_DSS_ROT_0 + 4:
1593 *offset1 = (fbw - 1) * ps;
1594 if (field_offset)
1595 *offset0 = *offset1 + field_offset * screen_width * ps;
1596 else
1597 *offset0 = *offset1;
1598 *row_inc = pixinc(screen_width * 2 - 1 +
1599 (fieldmode ? screen_width : 0),
1600 ps);
1601 *pix_inc = pixinc(-1, ps);
1602 break;
1603
1604 case OMAP_DSS_ROT_90 + 4:
1605 *offset1 = 0;
1606 if (field_offset)
1607 *offset0 = *offset1 + field_offset * ps;
1608 else
1609 *offset0 = *offset1;
1610 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1611 (fieldmode ? 1 : 0),
1612 ps);
1613 *pix_inc = pixinc(screen_width, ps);
1614 break;
1615
1616 case OMAP_DSS_ROT_180 + 4:
1617 *offset1 = screen_width * (fbh - 1) * ps;
1618 if (field_offset)
1619 *offset0 = *offset1 - field_offset * screen_width * ps;
1620 else
1621 *offset0 = *offset1;
1622 *row_inc = pixinc(1 - screen_width * 2 -
1623 (fieldmode ? screen_width : 0),
1624 ps);
1625 *pix_inc = pixinc(1, ps);
1626 break;
1627
1628 case OMAP_DSS_ROT_270 + 4:
1629 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1630 if (field_offset)
1631 *offset0 = *offset1 - field_offset * ps;
1632 else
1633 *offset0 = *offset1;
1634 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1635 (fieldmode ? 1 : 0),
1636 ps);
1637 *pix_inc = pixinc(-screen_width, ps);
1638 break;
1639
1640 default:
1641 BUG();
1642 }
1643}
1644
ff1b2cde
SS		 1645static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1646 u16 height, u16 out_width, u16 out_height,
1647 enum omap_color_mode color_mode)
80c39712
TV		 1648{
1649 u32 fclk = 0;
26d9dd0d 1650 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1651
7282f1b7
CM		 1652 if (height <= out_height && width <= out_width)
1653 return (unsigned long) pclk;
1654
80c39712 1655 if (height > out_height) {
ebdc5249
AT		 1656 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1657 unsigned int ppl = dssdev->panel.timings.x_res;
80c39712
TV		 1658
1659 tmp = pclk * height * out_width;
1660 do_div(tmp, 2 * out_height * ppl);
1661 fclk = tmp;
1662
2d9c5597
VS		 1663 if (height > 2 * out_height) {
1664 if (ppl == out_width)
1665 return 0;
1666
80c39712
TV		 1667 tmp = pclk * (height - 2 * out_height) * out_width;
1668 do_div(tmp, 2 * out_height * (ppl - out_width));
1669 fclk = max(fclk, (u32) tmp);
1670 }
1671 }
1672
1673 if (width > out_width) {
1674 tmp = pclk * width;
1675 do_div(tmp, out_width);
1676 fclk = max(fclk, (u32) tmp);
1677
1678 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1679 fclk <<= 1;
1680 }
1681
1682 return fclk;
1683}
1684
ff1b2cde
SS		 1685static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1686 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1687{
1688 unsigned int hf, vf;
79ee89cd 1689 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1690
1691 /*
1692 * FIXME how to determine the 'A' factor
1693 * for the no downscaling case ?
1694 */
1695
1696 if (width > 3 * out_width)
1697 hf = 4;
1698 else if (width > 2 * out_width)
1699 hf = 3;
1700 else if (width > out_width)
1701 hf = 2;
1702 else
1703 hf = 1;
1704
1705 if (height > out_height)
1706 vf = 2;
1707 else
1708 vf = 1;
1709
7282f1b7
CM		 1710 if (cpu_is_omap24xx()) {
1711 if (vf > 1 && hf > 1)
79ee89cd 1712 return pclk * 4;
7282f1b7 1713 else
79ee89cd 1714 return pclk * 2;
7282f1b7 1715 } else if (cpu_is_omap34xx()) {
79ee89cd 1716 return pclk * vf * hf;
7282f1b7 1717 } else {
79ee89cd
AT		 1718 if (hf > 1)
1719 return DIV_ROUND_UP(pclk, out_width) * width;
1720 else
1721 return pclk;
7282f1b7 1722 }
80c39712
TV		 1723}
1724
79ad75f2
AT		 1725static int dispc_ovl_calc_scaling(enum omap_plane plane,
1726 enum omap_channel channel, u16 width, u16 height,
1727 u16 out_width, u16 out_height,
1728 enum omap_color_mode color_mode, bool *five_taps)
1729{
1730 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1731 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1732 const int maxsinglelinewidth =
1733 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
79ad75f2
AT		 1734 unsigned long fclk = 0;
1735
f95cb5eb
TV		 1736 if (width == out_width && height == out_height)
1737 return 0;
1738
1739 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1740 return -EINVAL;
79ad75f2
AT		 1741
1742 if (out_width < width / maxdownscale ||
1743 out_width > width * 8)
1744 return -EINVAL;
1745
1746 if (out_height < height / maxdownscale ||
1747 out_height > height * 8)
1748 return -EINVAL;
1749
7282f1b7
CM		 1750 if (cpu_is_omap24xx()) {
1751 if (width > maxsinglelinewidth)
1752 DSSERR("Cannot scale max input width exceeded");
1753 *five_taps = false;
1754 fclk = calc_fclk(channel, width, height, out_width,
1755 out_height);
1756 } else if (cpu_is_omap34xx()) {
1757 if (width > (maxsinglelinewidth * 2)) {
1758 DSSERR("Cannot setup scaling");
1759 DSSERR("width exceeds maximum width possible");
1760 return -EINVAL;
1761 }
1762 fclk = calc_fclk_five_taps(channel, width, height, out_width,
1763 out_height, color_mode);
1764 if (width > maxsinglelinewidth) {
1765 if (height > out_height && height < out_height * 2)
1766 *five_taps = false;
1767 else {
1768 DSSERR("cannot setup scaling with five taps");
1769 return -EINVAL;
1770 }
1771 }
1772 if (!*five_taps)
1773 fclk = calc_fclk(channel, width, height, out_width,
1774 out_height);
1775 } else {
1776 if (width > maxsinglelinewidth) {
1777 DSSERR("Cannot scale width exceeds max line width");
1778 return -EINVAL;
1779 }
79ad75f2
AT		 1780 fclk = calc_fclk(channel, width, height, out_width,
1781 out_height);
79ad75f2
AT		 1782 }
1783
79ad75f2
AT		 1784 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1785 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1786
1787 if (!fclk || fclk > dispc_fclk_rate()) {
1788 DSSERR("failed to set up scaling, "
1789 "required fclk rate = %lu Hz, "
1790 "current fclk rate = %lu Hz\n",
1791 fclk, dispc_fclk_rate());
1792 return -EINVAL;
1793 }
1794
1795 return 0;
1796}
1797
a4273b7c 1798int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
2cc5d1af 1799 bool ilace, bool replication)
80c39712 1800{
79ad75f2 1801 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 1802 bool five_taps = true;
80c39712 1803 bool fieldmode = 0;
79ad75f2 1804 int r, cconv = 0;
80c39712
TV		 1805 unsigned offset0, offset1;
1806 s32 row_inc;
1807 s32 pix_inc;
a4273b7c 1808 u16 frame_height = oi->height;
80c39712 1809 unsigned int field_offset = 0;
cf073668 1810 u16 outw, outh;
2cc5d1af
TV		 1811 enum omap_channel channel;
1812
1813 channel = dispc_ovl_get_channel_out(plane);
80c39712 1814
a4273b7c 1815 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 1816 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
1817 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 1818 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1819 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 1820 oi->mirror, ilace, channel, replication);
e6d80f95 1821
a4273b7c 1822 if (oi->paddr == 0)
80c39712
TV		 1823 return -EINVAL;
1824
cf073668
TV		 1825 outw = oi->out_width == 0 ? oi->width : oi->out_width;
1826 outh = oi->out_height == 0 ? oi->height : oi->out_height;
1827
1828 if (ilace && oi->height == outh)
80c39712
TV		 1829 fieldmode = 1;
1830
1831 if (ilace) {
1832 if (fieldmode)
a4273b7c
AT		 1833 oi->height /= 2;
1834 oi->pos_y /= 2;
cf073668 1835 outh /= 2;
80c39712
TV		 1836
1837 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1838 "out_height %d\n",
cf073668 1839 oi->height, oi->pos_y, outh);
80c39712
TV		 1840 }
1841
a4273b7c 1842 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 1843 return -EINVAL;
1844
79ad75f2 1845 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
cf073668 1846 outw, outh, oi->color_mode,
79ad75f2
AT		 1847 &five_taps);
1848 if (r)
1849 return r;
80c39712 1850
79ad75f2
AT		 1851 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1852 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1853 oi->color_mode == OMAP_DSS_COLOR_NV12)
1854 cconv = 1;
80c39712
TV		 1855
1856 if (ilace && !fieldmode) {
1857 /*
1858 * when downscaling the bottom field may have to start several
1859 * source lines below the top field. Unfortunately ACCUI
1860 * registers will only hold the fractional part of the offset
1861 * so the integer part must be added to the base address of the
1862 * bottom field.
1863 */
cf073668 1864 if (!oi->height || oi->height == outh)
80c39712
TV		 1865 field_offset = 0;
1866 else
cf073668 1867 field_offset = oi->height / outh / 2;
80c39712
TV		 1868 }
1869
1870 /* Fields are independent but interleaved in memory. */
1871 if (fieldmode)
1872 field_offset = 1;
1873
a4273b7c
AT		 1874 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1875 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1876 oi->screen_width, oi->width, frame_height,
1877 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1878 &offset0, &offset1, &row_inc, &pix_inc);
1879 else
a4273b7c
AT		 1880 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1881 oi->screen_width, oi->width, frame_height,
1882 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1883 &offset0, &offset1, &row_inc, &pix_inc);
1884
1885 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1886 offset0, offset1, row_inc, pix_inc);
1887
a4273b7c 1888 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 1889
a4273b7c
AT		 1890 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1891 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 1892
a4273b7c
AT		 1893 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1894 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1895 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 1896 }
1897
1898
f0e5caab
TV		 1899 dispc_ovl_set_row_inc(plane, row_inc);
1900 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 1901
a4273b7c 1902 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
cf073668 1903 oi->height, outw, outh);
80c39712 1904
a4273b7c 1905 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 1906
a4273b7c 1907 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
80c39712 1908
79ad75f2 1909 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
a4273b7c 1910 dispc_ovl_set_scaling(plane, oi->width, oi->height,
cf073668 1911 outw, outh,
0d66cbb5 1912 ilace, five_taps, fieldmode,
a4273b7c 1913 oi->color_mode, oi->rotation);
cf073668 1914 dispc_ovl_set_vid_size(plane, outw, outh);
f0e5caab 1915 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 1916 }
1917
a4273b7c
AT		 1918 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1919 oi->color_mode);
80c39712 1920
54128701 1921 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 1922 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1923 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 1924
c3d92529 1925 dispc_ovl_enable_replication(plane, replication);
c3d92529 1926
80c39712
TV		 1927 return 0;
1928}
1929
f0e5caab 1930int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 1931{
e6d80f95
TV		 1932 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1933
9b372c2d 1934 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 1935
1936 return 0;
80c39712
TV		 1937}
1938
1939static void dispc_disable_isr(void *data, u32 mask)
1940{
1941 struct completion *compl = data;
1942 complete(compl);
1943}
1944
2a205f34 1945static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1946{
b6a44e77 1947 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 1948 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 1949 /* flush posted write */
1950 dispc_read_reg(DISPC_CONTROL2);
1951 } else {
2a205f34 1952 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 1953 dispc_read_reg(DISPC_CONTROL);
1954 }
80c39712
TV		 1955}
1956
26d9dd0d 1957static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1958{
1959 struct completion frame_done_completion;
1960 bool is_on;
1961 int r;
2a205f34 1962 u32 irq;
80c39712 1963
80c39712
TV		 1964 /* When we disable LCD output, we need to wait until frame is done.
1965 * Otherwise the DSS is still working, and turning off the clocks
1966 * prevents DSS from going to OFF mode */
2a205f34
SS		 1967 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1968 REG_GET(DISPC_CONTROL2, 0, 0) :
1969 REG_GET(DISPC_CONTROL, 0, 0);
1970
1971 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1972 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1973
1974 if (!enable && is_on) {
1975 init_completion(&frame_done_completion);
1976
1977 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1978 &frame_done_completion, irq);
80c39712
TV		 1979
1980 if (r)
1981 DSSERR("failed to register FRAMEDONE isr\n");
1982 }
1983
2a205f34 1984 _enable_lcd_out(channel, enable);
80c39712
TV		 1985
1986 if (!enable && is_on) {
1987 if (!wait_for_completion_timeout(&frame_done_completion,
1988 msecs_to_jiffies(100)))
1989 DSSERR("timeout waiting for FRAME DONE\n");
1990
1991 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1992 &frame_done_completion, irq);
80c39712
TV		 1993
1994 if (r)
1995 DSSERR("failed to unregister FRAMEDONE isr\n");
1996 }
80c39712
TV		 1997}
1998
1999static void _enable_digit_out(bool enable)
2000{
2001 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2002 /* flush posted write */
2003 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2004}
2005
26d9dd0d 2006static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2007{
2008 struct completion frame_done_completion;
e82b090b
TV		 2009 enum dss_hdmi_venc_clk_source_select src;
2010 int r, i;
2011 u32 irq_mask;
2012 int num_irqs;
80c39712 2013
e6d80f95 2014 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2015 return;
80c39712 2016
e82b090b
TV		 2017 src = dss_get_hdmi_venc_clk_source();
2018
80c39712
TV		 2019 if (enable) {
2020 unsigned long flags;
2021 /* When we enable digit output, we'll get an extra digit
2022 * sync lost interrupt, that we need to ignore */
2023 spin_lock_irqsave(&dispc.irq_lock, flags);
2024 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2025 _omap_dispc_set_irqs();
2026 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2027 }
2028
2029 /* When we disable digit output, we need to wait until fields are done.
2030 * Otherwise the DSS is still working, and turning off the clocks
2031 * prevents DSS from going to OFF mode. And when enabling, we need to
2032 * wait for the extra sync losts */
2033 init_completion(&frame_done_completion);
2034
e82b090b
TV		 2035 if (src == DSS_HDMI_M_PCLK && enable == false) {
2036 irq_mask = DISPC_IRQ_FRAMEDONETV;
2037 num_irqs = 1;
2038 } else {
2039 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2040 /* XXX I understand from TRM that we should only wait for the
2041 * current field to complete. But it seems we have to wait for
2042 * both fields */
2043 num_irqs = 2;
2044 }
2045
80c39712 2046 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2047 irq_mask);
80c39712 2048 if (r)
e82b090b 2049 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2050
2051 _enable_digit_out(enable);
2052
e82b090b
TV		 2053 for (i = 0; i < num_irqs; ++i) {
2054 if (!wait_for_completion_timeout(&frame_done_completion,
2055 msecs_to_jiffies(100)))
2056 DSSERR("timeout waiting for digit out to %s\n",
2057 enable ? "start" : "stop");
2058 }
80c39712 2059
e82b090b
TV		 2060 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2061 irq_mask);
80c39712 2062 if (r)
e82b090b 2063 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2064
2065 if (enable) {
2066 unsigned long flags;
2067 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2068 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2069 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2070 _omap_dispc_set_irqs();
2071 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2072 }
80c39712
TV		 2073}
2074
26d9dd0d 2075bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2076{
2077 if (channel == OMAP_DSS_CHANNEL_LCD)
2078 return !!REG_GET(DISPC_CONTROL, 0, 0);
2079 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2080 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2081 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2082 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2083 else
2084 BUG();
2085}
2086
26d9dd0d 2087void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2088{
dac57a05 2089 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2090 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2091 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2092 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2093 else
2094 BUG();
2095}
2096
80c39712
TV		 2097void dispc_lcd_enable_signal_polarity(bool act_high)
2098{
6ced40bf
AT		 2099 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2100 return;
2101
80c39712 2102 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2103}
2104
2105void dispc_lcd_enable_signal(bool enable)
2106{
6ced40bf
AT		 2107 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2108 return;
2109
80c39712 2110 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2111}
2112
2113void dispc_pck_free_enable(bool enable)
2114{
6ced40bf
AT		 2115 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2116 return;
2117
80c39712 2118 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2119}
2120
26d9dd0d 2121void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2122{
2a205f34
SS		 2123 if (channel == OMAP_DSS_CHANNEL_LCD2)
2124 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2125 else
2126 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2127}
2128
2129
26d9dd0d 2130void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2131 enum omap_lcd_display_type type)
80c39712
TV		 2132{
2133 int mode;
2134
2135 switch (type) {
2136 case OMAP_DSS_LCD_DISPLAY_STN:
2137 mode = 0;
2138 break;
2139
2140 case OMAP_DSS_LCD_DISPLAY_TFT:
2141 mode = 1;
2142 break;
2143
2144 default:
2145 BUG();
2146 return;
2147 }
2148
2a205f34
SS		 2149 if (channel == OMAP_DSS_CHANNEL_LCD2)
2150 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2151 else
2152 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2153}
2154
2155void dispc_set_loadmode(enum omap_dss_load_mode mode)
2156{
80c39712 2157 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2158}
2159
2160
c64dca40 2161static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2162{
8613b000 2163 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2164}
2165
c64dca40 2166static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2167 enum omap_dss_trans_key_type type,
2168 u32 trans_key)
2169{
80c39712
TV		 2170 if (ch == OMAP_DSS_CHANNEL_LCD)
2171 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2172 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2173 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2174 else /* OMAP_DSS_CHANNEL_LCD2 */
2175 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2176
8613b000 2177 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2178}
2179
c64dca40 2180static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2181{
80c39712
TV		 2182 if (ch == OMAP_DSS_CHANNEL_LCD)
2183 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2184 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2185 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2186 else /* OMAP_DSS_CHANNEL_LCD2 */
2187 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2188}
11354dd5 2189
c64dca40
TV		 2190static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2191 bool enable)
80c39712 2192{
11354dd5 2193 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2194 return;
2195
80c39712
TV		 2196 if (ch == OMAP_DSS_CHANNEL_LCD)
2197 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2198 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2199 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2200}
11354dd5 2201
c64dca40
TV		 2202void dispc_mgr_setup(enum omap_channel channel,
2203 struct omap_overlay_manager_info *info)
2204{
2205 dispc_mgr_set_default_color(channel, info->default_color);
2206 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2207 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2208 dispc_mgr_enable_alpha_fixed_zorder(channel,
2209 info->partial_alpha_enabled);
2210 if (dss_has_feature(FEAT_CPR)) {
2211 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2212 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2213 }
2214}
80c39712 2215
26d9dd0d 2216void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2217{
2218 int code;
2219
2220 switch (data_lines) {
2221 case 12:
2222 code = 0;
2223 break;
2224 case 16:
2225 code = 1;
2226 break;
2227 case 18:
2228 code = 2;
2229 break;
2230 case 24:
2231 code = 3;
2232 break;
2233 default:
2234 BUG();
2235 return;
2236 }
2237
2a205f34
SS		 2238 if (channel == OMAP_DSS_CHANNEL_LCD2)
2239 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2240 else
2241 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2242}
2243
569969d6 2244void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2245{
2246 u32 l;
569969d6 2247 int gpout0, gpout1;
80c39712
TV		 2248
2249 switch (mode) {
569969d6
AT		 2250 case DSS_IO_PAD_MODE_RESET:
2251 gpout0 = 0;
2252 gpout1 = 0;
80c39712 2253 break;
569969d6
AT		 2254 case DSS_IO_PAD_MODE_RFBI:
2255 gpout0 = 1;
80c39712
TV		 2256 gpout1 = 0;
2257 break;
569969d6
AT		 2258 case DSS_IO_PAD_MODE_BYPASS:
2259 gpout0 = 1;
80c39712
TV		 2260 gpout1 = 1;
2261 break;
80c39712
TV		 2262 default:
2263 BUG();
2264 return;
2265 }
2266
569969d6
AT		 2267 l = dispc_read_reg(DISPC_CONTROL);
2268 l = FLD_MOD(l, gpout0, 15, 15);
2269 l = FLD_MOD(l, gpout1, 16, 16);
2270 dispc_write_reg(DISPC_CONTROL, l);
2271}
2272
2273void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2274{
2275 if (channel == OMAP_DSS_CHANNEL_LCD2)
2276 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2277 else
2278 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2279}
2280
8f366162
AT		 2281static bool _dispc_mgr_size_ok(u16 width, u16 height)
2282{
2283 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2284 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2285}
2286
80c39712
TV		 2287static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2288 int vsw, int vfp, int vbp)
2289{
2290 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2291 if (hsw < 1 || hsw > 64 ||
2292 hfp < 1 || hfp > 256 ||
2293 hbp < 1 || hbp > 256 ||
2294 vsw < 1 || vsw > 64 ||
2295 vfp < 0 || vfp > 255 ||
2296 vbp < 0 || vbp > 255)
2297 return false;
2298 } else {
2299 if (hsw < 1 || hsw > 256 ||
2300 hfp < 1 || hfp > 4096 ||
2301 hbp < 1 || hbp > 4096 ||
2302 vsw < 1 || vsw > 256 ||
2303 vfp < 0 || vfp > 4095 ||
2304 vbp < 0 || vbp > 4095)
2305 return false;
2306 }
2307
2308 return true;
2309}
2310
8f366162
AT		 2311bool dispc_mgr_timings_ok(enum omap_channel channel,
2312 struct omap_video_timings *timings)
80c39712 2313{
8f366162
AT		 2314 bool timings_ok;
2315
2316 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2317
2318 if (dispc_mgr_is_lcd(channel))
2319 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2320 timings->hfp, timings->hbp,
2321 timings->vsw, timings->vfp,
2322 timings->vbp);
2323
2324 return timings_ok;
80c39712
TV		 2325}
2326
26d9dd0d 2327static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2328 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2329{
2330 u32 timing_h, timing_v;
2331
2332 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2333 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2334 FLD_VAL(hbp-1, 27, 20);
2335
2336 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2337 FLD_VAL(vbp, 27, 20);
2338 } else {
2339 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2340 FLD_VAL(hbp-1, 31, 20);
2341
2342 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2343 FLD_VAL(vbp, 31, 20);
2344 }
2345
64ba4f74
SS		 2346 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2347 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2348}
2349
2350/* change name to mode? */
c51d921a 2351void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2352 struct omap_video_timings *timings)
80c39712
TV		 2353{
2354 unsigned xtot, ytot;
2355 unsigned long ht, vt;
2356
c51d921a
AT		 2357 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2358 timings->y_res);
80c39712 2359
8f366162
AT		 2360 if (!dispc_mgr_timings_ok(channel, timings))
2361 BUG();
80c39712 2362
8f366162 2363 if (dispc_mgr_is_lcd(channel)) {
c51d921a
AT		 2364 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2365 timings->hbp, timings->vsw, timings->vfp,
2366 timings->vbp);
80c39712 2367
c51d921a
AT		 2368 xtot = timings->x_res + timings->hfp + timings->hsw +
2369 timings->hbp;
2370 ytot = timings->y_res + timings->vfp + timings->vsw +
2371 timings->vbp;
80c39712 2372
c51d921a
AT		 2373 ht = (timings->pixel_clock * 1000) / xtot;
2374 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2375
2376 DSSDBG("pck %u\n", timings->pixel_clock);
2377 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
80c39712
TV		 2378 timings->hsw, timings->hfp, timings->hbp,
2379 timings->vsw, timings->vfp, timings->vbp);
2380
c51d921a 2381 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
c51d921a 2382 }
8f366162
AT		 2383
2384 dispc_mgr_set_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2385}
2386
26d9dd0d 2387static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2388 u16 pck_div)
80c39712
TV		 2389{
2390 BUG_ON(lck_div < 1);
9eaaf207 2391 BUG_ON(pck_div < 1);
80c39712 2392
ce7fa5eb 2393 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2394 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2395}
2396
26d9dd0d 2397static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2398 int *pck_div)
80c39712
TV		 2399{
2400 u32 l;
ce7fa5eb 2401 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2402 *lck_div = FLD_GET(l, 23, 16);
2403 *pck_div = FLD_GET(l, 7, 0);
2404}
2405
2406unsigned long dispc_fclk_rate(void)
2407{
a72b64b9 2408 struct platform_device *dsidev;
80c39712
TV		 2409 unsigned long r = 0;
2410
66534e8e 2411 switch (dss_get_dispc_clk_source()) {
89a35e51 2412 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2413 r = clk_get_rate(dispc.dss_clk);
66534e8e 2414 break;
89a35e51 2415 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2416 dsidev = dsi_get_dsidev_from_id(0);
2417 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2418 break;
5a8b572d
AT		 2419 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2420 dsidev = dsi_get_dsidev_from_id(1);
2421 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2422 break;
66534e8e
TA		 2423 default:
2424 BUG();
2425 }
2426
80c39712
TV		 2427 return r;
2428}
2429
26d9dd0d 2430unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2431{
a72b64b9 2432 struct platform_device *dsidev;
80c39712
TV		 2433 int lcd;
2434 unsigned long r;
2435 u32 l;
2436
ce7fa5eb 2437 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2438
2439 lcd = FLD_GET(l, 23, 16);
2440
ea75159e 2441 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2442 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2443 r = clk_get_rate(dispc.dss_clk);
ea75159e 2444 break;
89a35e51 2445 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2446 dsidev = dsi_get_dsidev_from_id(0);
2447 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2448 break;
5a8b572d
AT		 2449 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2450 dsidev = dsi_get_dsidev_from_id(1);
2451 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2452 break;
ea75159e
TA		 2453 default:
2454 BUG();
2455 }
80c39712
TV		 2456
2457 return r / lcd;
2458}
2459
26d9dd0d 2460unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2461{
80c39712 2462 unsigned long r;
80c39712 2463
c3dc6a7a
AT		 2464 if (dispc_mgr_is_lcd(channel)) {
2465 int pcd;
2466 u32 l;
80c39712 2467
c3dc6a7a 2468 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2469
c3dc6a7a 2470 pcd = FLD_GET(l, 7, 0);
80c39712 2471
c3dc6a7a
AT		 2472 r = dispc_mgr_lclk_rate(channel);
2473
2474 return r / pcd;
2475 } else {
2476 struct omap_dss_device *dssdev =
2477 dispc_mgr_get_device(channel);
2478
2479 switch (dssdev->type) {
2480 case OMAP_DISPLAY_TYPE_VENC:
2481 return venc_get_pixel_clock();
2482 case OMAP_DISPLAY_TYPE_HDMI:
2483 return hdmi_get_pixel_clock();
2484 default:
2485 BUG();
2486 }
2487 }
80c39712
TV		 2488}
2489
2490void dispc_dump_clocks(struct seq_file *s)
2491{
2492 int lcd, pcd;
0cf35df3 2493 u32 l;
89a35e51
AT		 2494 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2495 enum omap_dss_clk_source lcd_clk_src;
80c39712 2496
4fbafaf3
TV		 2497 if (dispc_runtime_get())
2498 return;
80c39712 2499
80c39712
TV		 2500 seq_printf(s, "- DISPC -\n");
2501
067a57e4
AT		 2502 seq_printf(s, "dispc fclk source = %s (%s)\n",
2503 dss_get_generic_clk_source_name(dispc_clk_src),
2504 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2505
2506 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2507
0cf35df3
MR		 2508 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2509 seq_printf(s, "- DISPC-CORE-CLK -\n");
2510 l = dispc_read_reg(DISPC_DIVISOR);
2511 lcd = FLD_GET(l, 23, 16);
2512
2513 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2514 (dispc_fclk_rate()/lcd), lcd);
2515 }
2a205f34
SS		 2516 seq_printf(s, "- LCD1 -\n");
2517
ea75159e
TA		 2518 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2519
2520 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2521 dss_get_generic_clk_source_name(lcd_clk_src),
2522 dss_feat_get_clk_source_name(lcd_clk_src));
2523
26d9dd0d 2524 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2525
ff1b2cde 2526 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2527 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2528 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2529 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2530 if (dss_has_feature(FEAT_MGR_LCD2)) {
2531 seq_printf(s, "- LCD2 -\n");
2532
ea75159e
TA		 2533 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2534
2535 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2536 dss_get_generic_clk_source_name(lcd_clk_src),
2537 dss_feat_get_clk_source_name(lcd_clk_src));
2538
26d9dd0d 2539 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2540
2a205f34 2541 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2542 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2543 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2544 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2545 }
4fbafaf3
TV		 2546
2547 dispc_runtime_put();
80c39712
TV		 2548}
2549
dfc0fd8d
TV		 2550#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2551void dispc_dump_irqs(struct seq_file *s)
2552{
2553 unsigned long flags;
2554 struct dispc_irq_stats stats;
2555
2556 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2557
2558 stats = dispc.irq_stats;
2559 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2560 dispc.irq_stats.last_reset = jiffies;
2561
2562 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2563
2564 seq_printf(s, "period %u ms\n",
2565 jiffies_to_msecs(jiffies - stats.last_reset));
2566
2567 seq_printf(s, "irqs %d\n", stats.irq_count);
2568#define PIS(x) \
2569 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2570
2571 PIS(FRAMEDONE);
2572 PIS(VSYNC);
2573 PIS(EVSYNC_EVEN);
2574 PIS(EVSYNC_ODD);
2575 PIS(ACBIAS_COUNT_STAT);
2576 PIS(PROG_LINE_NUM);
2577 PIS(GFX_FIFO_UNDERFLOW);
2578 PIS(GFX_END_WIN);
2579 PIS(PAL_GAMMA_MASK);
2580 PIS(OCP_ERR);
2581 PIS(VID1_FIFO_UNDERFLOW);
2582 PIS(VID1_END_WIN);
2583 PIS(VID2_FIFO_UNDERFLOW);
2584 PIS(VID2_END_WIN);
b8c095b4
AT		 2585 if (dss_feat_get_num_ovls() > 3) {
2586 PIS(VID3_FIFO_UNDERFLOW);
2587 PIS(VID3_END_WIN);
2588 }
dfc0fd8d
TV		 2589 PIS(SYNC_LOST);
2590 PIS(SYNC_LOST_DIGIT);
2591 PIS(WAKEUP);
2a205f34
SS		 2592 if (dss_has_feature(FEAT_MGR_LCD2)) {
2593 PIS(FRAMEDONE2);
2594 PIS(VSYNC2);
2595 PIS(ACBIAS_COUNT_STAT2);
2596 PIS(SYNC_LOST2);
2597 }
dfc0fd8d
TV		 2598#undef PIS
2599}
dfc0fd8d
TV		 2600#endif
2601
80c39712
TV		 2602void dispc_dump_regs(struct seq_file *s)
2603{
4dd2da15
AT		 2604 int i, j;
2605 const char *mgr_names[] = {
2606 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2607 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2608 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2609 };
2610 const char *ovl_names[] = {
2611 [OMAP_DSS_GFX] = "GFX",
2612 [OMAP_DSS_VIDEO1] = "VID1",
2613 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2614 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2615 };
2616 const char **p_names;
2617
9b372c2d 2618#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2619
4fbafaf3
TV		 2620 if (dispc_runtime_get())
2621 return;
80c39712 2622
5010be80 2623 /* DISPC common registers */
80c39712
TV		 2624 DUMPREG(DISPC_REVISION);
2625 DUMPREG(DISPC_SYSCONFIG);
2626 DUMPREG(DISPC_SYSSTATUS);
2627 DUMPREG(DISPC_IRQSTATUS);
2628 DUMPREG(DISPC_IRQENABLE);
2629 DUMPREG(DISPC_CONTROL);
2630 DUMPREG(DISPC_CONFIG);
2631 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2632 DUMPREG(DISPC_LINE_STATUS);
2633 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2634 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2635 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2636 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2637 if (dss_has_feature(FEAT_MGR_LCD2)) {
2638 DUMPREG(DISPC_CONTROL2);
2639 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2640 }
2641
2642#undef DUMPREG
2643
2644#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2645#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2646 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2647 dispc_read_reg(DISPC_REG(i, r)))
2648
4dd2da15 2649 p_names = mgr_names;
5010be80 2650
4dd2da15
AT		 2651 /* DISPC channel specific registers */
2652 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2653 DUMPREG(i, DISPC_DEFAULT_COLOR);
2654 DUMPREG(i, DISPC_TRANS_COLOR);
2655 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2656
4dd2da15
AT		 2657 if (i == OMAP_DSS_CHANNEL_DIGIT)
2658 continue;
5010be80 2659
4dd2da15
AT		 2660 DUMPREG(i, DISPC_DEFAULT_COLOR);
2661 DUMPREG(i, DISPC_TRANS_COLOR);
2662 DUMPREG(i, DISPC_TIMING_H);
2663 DUMPREG(i, DISPC_TIMING_V);
2664 DUMPREG(i, DISPC_POL_FREQ);
2665 DUMPREG(i, DISPC_DIVISORo);
2666 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2667
4dd2da15
AT		 2668 DUMPREG(i, DISPC_DATA_CYCLE1);
2669 DUMPREG(i, DISPC_DATA_CYCLE2);
2670 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2671
332e9d70 2672 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2673 DUMPREG(i, DISPC_CPR_COEF_R);
2674 DUMPREG(i, DISPC_CPR_COEF_G);
2675 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2676 }
2a205f34 2677 }
80c39712 2678
4dd2da15
AT		 2679 p_names = ovl_names;
2680
2681 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2682 DUMPREG(i, DISPC_OVL_BA0);
2683 DUMPREG(i, DISPC_OVL_BA1);
2684 DUMPREG(i, DISPC_OVL_POSITION);
2685 DUMPREG(i, DISPC_OVL_SIZE);
2686 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2687 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2688 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2689 DUMPREG(i, DISPC_OVL_ROW_INC);
2690 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2691 if (dss_has_feature(FEAT_PRELOAD))
2692 DUMPREG(i, DISPC_OVL_PRELOAD);
2693
2694 if (i == OMAP_DSS_GFX) {
2695 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2696 DUMPREG(i, DISPC_OVL_TABLE_BA);
2697 continue;
2698 }
2699
2700 DUMPREG(i, DISPC_OVL_FIR);
2701 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2702 DUMPREG(i, DISPC_OVL_ACCU0);
2703 DUMPREG(i, DISPC_OVL_ACCU1);
2704 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2705 DUMPREG(i, DISPC_OVL_BA0_UV);
2706 DUMPREG(i, DISPC_OVL_BA1_UV);
2707 DUMPREG(i, DISPC_OVL_FIR2);
2708 DUMPREG(i, DISPC_OVL_ACCU2_0);
2709 DUMPREG(i, DISPC_OVL_ACCU2_1);
2710 }
2711 if (dss_has_feature(FEAT_ATTR2))
2712 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2713 if (dss_has_feature(FEAT_PRELOAD))
2714 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2715 }
5010be80
AT		 2716
2717#undef DISPC_REG
2718#undef DUMPREG
2719
2720#define DISPC_REG(plane, name, i) name(plane, i)
2721#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2722 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2723 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2724 dispc_read_reg(DISPC_REG(plane, name, i)))
2725
4dd2da15 2726 /* Video pipeline coefficient registers */
332e9d70 2727
4dd2da15
AT		 2728 /* start from OMAP_DSS_VIDEO1 */
2729 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2730 for (j = 0; j < 8; j++)
2731 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2732
4dd2da15
AT		 2733 for (j = 0; j < 8; j++)
2734 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2735
4dd2da15
AT		 2736 for (j = 0; j < 5; j++)
2737 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2738
4dd2da15
AT		 2739 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2740 for (j = 0; j < 8; j++)
2741 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2742 }
2743
2744 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2745 for (j = 0; j < 8; j++)
2746 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2747
2748 for (j = 0; j < 8; j++)
2749 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2750
2751 for (j = 0; j < 8; j++)
2752 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2753 }
332e9d70 2754 }
80c39712 2755
4fbafaf3 2756 dispc_runtime_put();
5010be80
AT		 2757
2758#undef DISPC_REG
80c39712
TV		 2759#undef DUMPREG
2760}
2761
26d9dd0d
TV		 2762static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2763 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2764 u8 acb)
80c39712
TV		 2765{
2766 u32 l = 0;
2767
2768 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2769 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2770
2771 l |= FLD_VAL(onoff, 17, 17);
2772 l |= FLD_VAL(rf, 16, 16);
2773 l |= FLD_VAL(ieo, 15, 15);
2774 l |= FLD_VAL(ipc, 14, 14);
2775 l |= FLD_VAL(ihs, 13, 13);
2776 l |= FLD_VAL(ivs, 12, 12);
2777 l |= FLD_VAL(acbi, 11, 8);
2778 l |= FLD_VAL(acb, 7, 0);
2779
ff1b2cde 2780 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2781}
2782
26d9dd0d 2783void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 2784 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2785{
26d9dd0d 2786 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2787 (config & OMAP_DSS_LCD_RF) != 0,
2788 (config & OMAP_DSS_LCD_IEO) != 0,
2789 (config & OMAP_DSS_LCD_IPC) != 0,
2790 (config & OMAP_DSS_LCD_IHS) != 0,
2791 (config & OMAP_DSS_LCD_IVS) != 0,
2792 acbi, acb);
2793}
2794
2795/* with fck as input clock rate, find dispc dividers that produce req_pck */
2796void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2797 struct dispc_clock_info *cinfo)
2798{
9eaaf207 2799 u16 pcd_min, pcd_max;
80c39712
TV		 2800 unsigned long best_pck;
2801 u16 best_ld, cur_ld;
2802 u16 best_pd, cur_pd;
2803
9eaaf207
TV		 2804 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2805 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2806
2807 if (!is_tft)
2808 pcd_min = 3;
2809
80c39712
TV		 2810 best_pck = 0;
2811 best_ld = 0;
2812 best_pd = 0;
2813
2814 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2815 unsigned long lck = fck / cur_ld;
2816
9eaaf207 2817 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 2818 unsigned long pck = lck / cur_pd;
2819 long old_delta = abs(best_pck - req_pck);
2820 long new_delta = abs(pck - req_pck);
2821
2822 if (best_pck == 0 || new_delta < old_delta) {
2823 best_pck = pck;
2824 best_ld = cur_ld;
2825 best_pd = cur_pd;
2826
2827 if (pck == req_pck)
2828 goto found;
2829 }
2830
2831 if (pck < req_pck)
2832 break;
2833 }
2834
2835 if (lck / pcd_min < req_pck)
2836 break;
2837 }
2838
2839found:
2840 cinfo->lck_div = best_ld;
2841 cinfo->pck_div = best_pd;
2842 cinfo->lck = fck / cinfo->lck_div;
2843 cinfo->pck = cinfo->lck / cinfo->pck_div;
2844}
2845
2846/* calculate clock rates using dividers in cinfo */
2847int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2848 struct dispc_clock_info *cinfo)
2849{
2850 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2851 return -EINVAL;
9eaaf207 2852 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 2853 return -EINVAL;
2854
2855 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2856 cinfo->pck = cinfo->lck / cinfo->pck_div;
2857
2858 return 0;
2859}
2860
26d9dd0d 2861int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 2862 struct dispc_clock_info *cinfo)
80c39712
TV		 2863{
2864 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2865 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2866
26d9dd0d 2867 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2868
2869 return 0;
2870}
2871
26d9dd0d 2872int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 2873 struct dispc_clock_info *cinfo)
80c39712
TV		 2874{
2875 unsigned long fck;
2876
2877 fck = dispc_fclk_rate();
2878
ce7fa5eb
MR		 2879 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2880 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2881
2882 cinfo->lck = fck / cinfo->lck_div;
2883 cinfo->pck = cinfo->lck / cinfo->pck_div;
2884
2885 return 0;
2886}
2887
2888/* dispc.irq_lock has to be locked by the caller */
2889static void _omap_dispc_set_irqs(void)
2890{
2891 u32 mask;
2892 u32 old_mask;
2893 int i;
2894 struct omap_dispc_isr_data *isr_data;
2895
2896 mask = dispc.irq_error_mask;
2897
2898 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2899 isr_data = &dispc.registered_isr[i];
2900
2901 if (isr_data->isr == NULL)
2902 continue;
2903
2904 mask |= isr_data->mask;
2905 }
2906
80c39712
TV		 2907 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2908 /* clear the irqstatus for newly enabled irqs */
2909 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2910
2911 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 2912}
2913
2914int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2915{
2916 int i;
2917 int ret;
2918 unsigned long flags;
2919 struct omap_dispc_isr_data *isr_data;
2920
2921 if (isr == NULL)
2922 return -EINVAL;
2923
2924 spin_lock_irqsave(&dispc.irq_lock, flags);
2925
2926 /* check for duplicate entry */
2927 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2928 isr_data = &dispc.registered_isr[i];
2929 if (isr_data->isr == isr && isr_data->arg == arg &&
2930 isr_data->mask == mask) {
2931 ret = -EINVAL;
2932 goto err;
2933 }
2934 }
2935
2936 isr_data = NULL;
2937 ret = -EBUSY;
2938
2939 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2940 isr_data = &dispc.registered_isr[i];
2941
2942 if (isr_data->isr != NULL)
2943 continue;
2944
2945 isr_data->isr = isr;
2946 isr_data->arg = arg;
2947 isr_data->mask = mask;
2948 ret = 0;
2949
2950 break;
2951 }
2952
b9cb0984
TV		 2953 if (ret)
2954 goto err;
2955
80c39712
TV		 2956 _omap_dispc_set_irqs();
2957
2958 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2959
2960 return 0;
2961err:
2962 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2963
2964 return ret;
2965}
2966EXPORT_SYMBOL(omap_dispc_register_isr);
2967
2968int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2969{
2970 int i;
2971 unsigned long flags;
2972 int ret = -EINVAL;
2973 struct omap_dispc_isr_data *isr_data;
2974
2975 spin_lock_irqsave(&dispc.irq_lock, flags);
2976
2977 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2978 isr_data = &dispc.registered_isr[i];
2979 if (isr_data->isr != isr || isr_data->arg != arg ||
2980 isr_data->mask != mask)
2981 continue;
2982
2983 /* found the correct isr */
2984
2985 isr_data->isr = NULL;
2986 isr_data->arg = NULL;
2987 isr_data->mask = 0;
2988
2989 ret = 0;
2990 break;
2991 }
2992
2993 if (ret == 0)
2994 _omap_dispc_set_irqs();
2995
2996 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2997
2998 return ret;
2999}
3000EXPORT_SYMBOL(omap_dispc_unregister_isr);
3001
3002#ifdef DEBUG
3003static void print_irq_status(u32 status)
3004{
3005 if ((status & dispc.irq_error_mask) == 0)
3006 return;
3007
3008 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3009
3010#define PIS(x) \
3011 if (status & DISPC_IRQ_##x) \
3012 printk(#x " ");
3013 PIS(GFX_FIFO_UNDERFLOW);
3014 PIS(OCP_ERR);
3015 PIS(VID1_FIFO_UNDERFLOW);
3016 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3017 if (dss_feat_get_num_ovls() > 3)
3018 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3019 PIS(SYNC_LOST);
3020 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3021 if (dss_has_feature(FEAT_MGR_LCD2))
3022 PIS(SYNC_LOST2);
80c39712
TV		 3023#undef PIS
3024
3025 printk("\n");
3026}
3027#endif
3028
3029/* Called from dss.c. Note that we don't touch clocks here,
3030 * but we presume they are on because we got an IRQ. However,
3031 * an irq handler may turn the clocks off, so we may not have
3032 * clock later in the function. */
affe360d 3033static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3034{
3035 int i;
affe360d 3036 u32 irqstatus, irqenable;
80c39712
TV		 3037 u32 handledirqs = 0;
3038 u32 unhandled_errors;
3039 struct omap_dispc_isr_data *isr_data;
3040 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3041
3042 spin_lock(&dispc.irq_lock);
3043
3044 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3045 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3046
3047 /* IRQ is not for us */
3048 if (!(irqstatus & irqenable)) {
3049 spin_unlock(&dispc.irq_lock);
3050 return IRQ_NONE;
3051 }
80c39712 3052
dfc0fd8d
TV		 3053#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3054 spin_lock(&dispc.irq_stats_lock);
3055 dispc.irq_stats.irq_count++;
3056 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3057 spin_unlock(&dispc.irq_stats_lock);
3058#endif
3059
80c39712
TV		 3060#ifdef DEBUG
3061 if (dss_debug)
3062 print_irq_status(irqstatus);
3063#endif
3064 /* Ack the interrupt. Do it here before clocks are possibly turned
3065 * off */
3066 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3067 /* flush posted write */
3068 dispc_read_reg(DISPC_IRQSTATUS);
3069
3070 /* make a copy and unlock, so that isrs can unregister
3071 * themselves */
3072 memcpy(registered_isr, dispc.registered_isr,
3073 sizeof(registered_isr));
3074
3075 spin_unlock(&dispc.irq_lock);
3076
3077 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3078 isr_data = &registered_isr[i];
3079
3080 if (!isr_data->isr)
3081 continue;
3082
3083 if (isr_data->mask & irqstatus) {
3084 isr_data->isr(isr_data->arg, irqstatus);
3085 handledirqs |= isr_data->mask;
3086 }
3087 }
3088
3089 spin_lock(&dispc.irq_lock);
3090
3091 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3092
3093 if (unhandled_errors) {
3094 dispc.error_irqs |= unhandled_errors;
3095
3096 dispc.irq_error_mask &= ~unhandled_errors;
3097 _omap_dispc_set_irqs();
3098
3099 schedule_work(&dispc.error_work);
3100 }
3101
3102 spin_unlock(&dispc.irq_lock);
affe360d 3103
3104 return IRQ_HANDLED;
80c39712
TV		 3105}
3106
3107static void dispc_error_worker(struct work_struct *work)
3108{
3109 int i;
3110 u32 errors;
3111 unsigned long flags;
fe3cc9d6
TV		 3112 static const unsigned fifo_underflow_bits[] = {
3113 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3114 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3115 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3116 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3117 };
3118
3119 static const unsigned sync_lost_bits[] = {
3120 DISPC_IRQ_SYNC_LOST,
3121 DISPC_IRQ_SYNC_LOST_DIGIT,
3122 DISPC_IRQ_SYNC_LOST2,
3123 };
80c39712
TV		 3124
3125 spin_lock_irqsave(&dispc.irq_lock, flags);
3126 errors = dispc.error_irqs;
3127 dispc.error_irqs = 0;
3128 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3129
13eae1f9
DZ		 3130 dispc_runtime_get();
3131
fe3cc9d6
TV		 3132 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3133 struct omap_overlay *ovl;
3134 unsigned bit;
80c39712 3135
fe3cc9d6
TV		 3136 ovl = omap_dss_get_overlay(i);
3137 bit = fifo_underflow_bits[i];
80c39712 3138
fe3cc9d6
TV		 3139 if (bit & errors) {
3140 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3141 ovl->name);
f0e5caab 3142 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3143 dispc_mgr_go(ovl->manager->id);
80c39712 3144 mdelay(50);
80c39712
TV		 3145 }
3146 }
3147
fe3cc9d6
TV		 3148 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3149 struct omap_overlay_manager *mgr;
3150 unsigned bit;
80c39712 3151
fe3cc9d6
TV		 3152 mgr = omap_dss_get_overlay_manager(i);
3153 bit = sync_lost_bits[i];
80c39712 3154
fe3cc9d6
TV		 3155 if (bit & errors) {
3156 struct omap_dss_device *dssdev = mgr->device;
3157 bool enable;
80c39712 3158
fe3cc9d6
TV		 3159 DSSERR("SYNC_LOST on channel %s, restarting the output "
3160 "with video overlays disabled\n",
3161 mgr->name);
2a205f34 3162
fe3cc9d6
TV		 3163 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3164 dssdev->driver->disable(dssdev);
2a205f34 3165
2a205f34
SS		 3166 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3167 struct omap_overlay *ovl;
3168 ovl = omap_dss_get_overlay(i);
3169
fe3cc9d6
TV		 3170 if (ovl->id != OMAP_DSS_GFX &&
3171 ovl->manager == mgr)
f0e5caab 3172 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3173 }
3174
26d9dd0d 3175 dispc_mgr_go(mgr->id);
2a205f34 3176 mdelay(50);
fe3cc9d6 3177
2a205f34
SS		 3178 if (enable)
3179 dssdev->driver->enable(dssdev);
3180 }
3181 }
3182
80c39712
TV		 3183 if (errors & DISPC_IRQ_OCP_ERR) {
3184 DSSERR("OCP_ERR\n");
3185 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3186 struct omap_overlay_manager *mgr;
3187 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3188 if (mgr->device && mgr->device->driver)
3189 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3190 }
3191 }
3192
3193 spin_lock_irqsave(&dispc.irq_lock, flags);
3194 dispc.irq_error_mask |= errors;
3195 _omap_dispc_set_irqs();
3196 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3197
3198 dispc_runtime_put();
80c39712
TV		 3199}
3200
3201int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3202{
3203 void dispc_irq_wait_handler(void *data, u32 mask)
3204 {
3205 complete((struct completion *)data);
3206 }
3207
3208 int r;
3209 DECLARE_COMPLETION_ONSTACK(completion);
3210
3211 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3212 irqmask);
3213
3214 if (r)
3215 return r;
3216
3217 timeout = wait_for_completion_timeout(&completion, timeout);
3218
3219 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3220
3221 if (timeout == 0)
3222 return -ETIMEDOUT;
3223
3224 if (timeout == -ERESTARTSYS)
3225 return -ERESTARTSYS;
3226
3227 return 0;
3228}
3229
3230int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3231 unsigned long timeout)
3232{
3233 void dispc_irq_wait_handler(void *data, u32 mask)
3234 {
3235 complete((struct completion *)data);
3236 }
3237
3238 int r;
3239 DECLARE_COMPLETION_ONSTACK(completion);
3240
3241 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3242 irqmask);
3243
3244 if (r)
3245 return r;
3246
3247 timeout = wait_for_completion_interruptible_timeout(&completion,
3248 timeout);
3249
3250 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3251
3252 if (timeout == 0)
3253 return -ETIMEDOUT;
3254
3255 if (timeout == -ERESTARTSYS)
3256 return -ERESTARTSYS;
3257
3258 return 0;
3259}
3260
3261#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3262void dispc_fake_vsync_irq(void)
3263{
3264 u32 irqstatus = DISPC_IRQ_VSYNC;
3265 int i;
3266
ab83b14c 3267 WARN_ON(!in_interrupt());
80c39712
TV		 3268
3269 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3270 struct omap_dispc_isr_data *isr_data;
3271 isr_data = &dispc.registered_isr[i];
3272
3273 if (!isr_data->isr)
3274 continue;
3275
3276 if (isr_data->mask & irqstatus)
3277 isr_data->isr(isr_data->arg, irqstatus);
3278 }
80c39712
TV		 3279}
3280#endif
3281
3282static void _omap_dispc_initialize_irq(void)
3283{
3284 unsigned long flags;
3285
3286 spin_lock_irqsave(&dispc.irq_lock, flags);
3287
3288 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3289
3290 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3291 if (dss_has_feature(FEAT_MGR_LCD2))
3292 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3293 if (dss_feat_get_num_ovls() > 3)
3294 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3295
3296 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3297 * so clear it */
3298 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3299
3300 _omap_dispc_set_irqs();
3301
3302 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3303}
3304
3305void dispc_enable_sidle(void)
3306{
3307 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3308}
3309
3310void dispc_disable_sidle(void)
3311{
3312 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3313}
3314
3315static void _omap_dispc_initial_config(void)
3316{
3317 u32 l;
3318
0cf35df3
MR		 3319 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3320 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3321 l = dispc_read_reg(DISPC_DIVISOR);
3322 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3323 l = FLD_MOD(l, 1, 0, 0);
3324 l = FLD_MOD(l, 1, 23, 16);
3325 dispc_write_reg(DISPC_DIVISOR, l);
3326 }
3327
80c39712 3328 /* FUNCGATED */
6ced40bf
AT		 3329 if (dss_has_feature(FEAT_FUNCGATED))
3330 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3331
80c39712
TV		 3332 _dispc_setup_color_conv_coef();
3333
3334 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3335
3336 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3337
3338 dispc_configure_burst_sizes();
54128701
AT		 3339
3340 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3341}
3342
060b6d9c
SG		 3343/* DISPC HW IP initialisation */
3344static int omap_dispchw_probe(struct platform_device *pdev)
3345{
3346 u32 rev;
affe360d 3347 int r = 0;
ea9da36a 3348 struct resource *dispc_mem;
4fbafaf3 3349 struct clk *clk;
ea9da36a 3350
060b6d9c
SG		 3351 dispc.pdev = pdev;
3352
3353 spin_lock_init(&dispc.irq_lock);
3354
3355#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3356 spin_lock_init(&dispc.irq_stats_lock);
3357 dispc.irq_stats.last_reset = jiffies;
3358#endif
3359
3360 INIT_WORK(&dispc.error_work, dispc_error_worker);
3361
ea9da36a
SG		 3362 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3363 if (!dispc_mem) {
3364 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3365 return -EINVAL;
ea9da36a 3366 }
cd3b3449 3367
6e2a14d2
JL		 3368 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3369 resource_size(dispc_mem));
060b6d9c
SG		 3370 if (!dispc.base) {
3371 DSSERR("can't ioremap DISPC\n");
cd3b3449 3372 return -ENOMEM;
affe360d 3373 }
cd3b3449 3374
affe360d 3375 dispc.irq = platform_get_irq(dispc.pdev, 0);
3376 if (dispc.irq < 0) {
3377 DSSERR("platform_get_irq failed\n");
cd3b3449 3378 return -ENODEV;
affe360d 3379 }
3380
6e2a14d2
JL		 3381 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3382 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3383 if (r < 0) {
3384 DSSERR("request_irq failed\n");
cd3b3449
TV		 3385 return r;
3386 }
3387
3388 clk = clk_get(&pdev->dev, "fck");
3389 if (IS_ERR(clk)) {
3390 DSSERR("can't get fck\n");
3391 r = PTR_ERR(clk);
3392 return r;
060b6d9c
SG		 3393 }
3394
cd3b3449
TV		 3395 dispc.dss_clk = clk;
3396
4fbafaf3
TV		 3397 pm_runtime_enable(&pdev->dev);
3398
3399 r = dispc_runtime_get();
3400 if (r)
3401 goto err_runtime_get;
060b6d9c
SG		 3402
3403 _omap_dispc_initial_config();
3404
3405 _omap_dispc_initialize_irq();
3406
060b6d9c 3407 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3408 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3409 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3410
4fbafaf3 3411 dispc_runtime_put();
060b6d9c
SG		 3412
3413 return 0;
4fbafaf3
TV		 3414
3415err_runtime_get:
3416 pm_runtime_disable(&pdev->dev);
4fbafaf3 3417 clk_put(dispc.dss_clk);
affe360d 3418 return r;
060b6d9c
SG		 3419}
3420
3421static int omap_dispchw_remove(struct platform_device *pdev)
3422{
4fbafaf3
TV		 3423 pm_runtime_disable(&pdev->dev);
3424
3425 clk_put(dispc.dss_clk);
3426
060b6d9c
SG		 3427 return 0;
3428}
3429
4fbafaf3
TV		 3430static int dispc_runtime_suspend(struct device *dev)
3431{
3432 dispc_save_context();
4fbafaf3
TV		 3433 dss_runtime_put();
3434
3435 return 0;
3436}
3437
3438static int dispc_runtime_resume(struct device *dev)
3439{
3440 int r;
3441
3442 r = dss_runtime_get();
3443 if (r < 0)
3444 return r;
3445
49ea86f3 3446 dispc_restore_context();
4fbafaf3
TV		 3447
3448 return 0;
3449}
3450
3451static const struct dev_pm_ops dispc_pm_ops = {
3452 .runtime_suspend = dispc_runtime_suspend,
3453 .runtime_resume = dispc_runtime_resume,
3454};
3455
060b6d9c
SG		 3456static struct platform_driver omap_dispchw_driver = {
3457 .probe = omap_dispchw_probe,
3458 .remove = omap_dispchw_remove,
3459 .driver = {
3460 .name = "omapdss_dispc",
3461 .owner = THIS_MODULE,
4fbafaf3 3462 .pm = &dispc_pm_ops,
060b6d9c
SG		 3463 },
3464};
3465
3466int dispc_init_platform_driver(void)
3467{
3468 return platform_driver_register(&omap_dispchw_driver);
3469}
3470
3471void dispc_uninit_platform_driver(void)
3472{
3473 return platform_driver_unregister(&omap_dispchw_driver);
3474}
Linux kernel - Deliverables
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