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OMAPDSS: use platform_driver_probe for dsi/hdmi/rfbi/venc/dpi/sdi
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
80c39712
TV		 122static void _omap_dispc_set_irqs(void);
123
55978cc2 124static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 125{
55978cc2 126 __raw_writel(val, dispc.base + idx);
80c39712
TV		 127}
128
55978cc2 129static inline u32 dispc_read_reg(const u16 idx)
80c39712 130{
55978cc2 131 return __raw_readl(dispc.base + idx);
80c39712
TV		 132}
133
134#define SR(reg) \
55978cc2 135 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 136#define RR(reg) \
55978cc2 137 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 138
4fbafaf3 139static void dispc_save_context(void)
80c39712 140{
c6104b8e 141 int i, j;
80c39712 142
4fbafaf3
TV		 143 DSSDBG("dispc_save_context\n");
144
80c39712
TV		 145 SR(IRQENABLE);
146 SR(CONTROL);
147 SR(CONFIG);
80c39712 148 SR(LINE_NUMBER);
11354dd5
AT		 149 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
150 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 151 SR(GLOBAL_ALPHA);
2a205f34
SS		 152 if (dss_has_feature(FEAT_MGR_LCD2)) {
153 SR(CONTROL2);
2a205f34
SS		 154 SR(CONFIG2);
155 }
80c39712 156
c6104b8e
AT		 157 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
158 SR(DEFAULT_COLOR(i));
159 SR(TRANS_COLOR(i));
160 SR(SIZE_MGR(i));
161 if (i == OMAP_DSS_CHANNEL_DIGIT)
162 continue;
163 SR(TIMING_H(i));
164 SR(TIMING_V(i));
165 SR(POL_FREQ(i));
166 SR(DIVISORo(i));
167
168 SR(DATA_CYCLE1(i));
169 SR(DATA_CYCLE2(i));
170 SR(DATA_CYCLE3(i));
171
332e9d70 172 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 173 SR(CPR_COEF_R(i));
174 SR(CPR_COEF_G(i));
175 SR(CPR_COEF_B(i));
332e9d70 176 }
2a205f34 177 }
80c39712 178
c6104b8e
AT		 179 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
180 SR(OVL_BA0(i));
181 SR(OVL_BA1(i));
182 SR(OVL_POSITION(i));
183 SR(OVL_SIZE(i));
184 SR(OVL_ATTRIBUTES(i));
185 SR(OVL_FIFO_THRESHOLD(i));
186 SR(OVL_ROW_INC(i));
187 SR(OVL_PIXEL_INC(i));
188 if (dss_has_feature(FEAT_PRELOAD))
189 SR(OVL_PRELOAD(i));
190 if (i == OMAP_DSS_GFX) {
191 SR(OVL_WINDOW_SKIP(i));
192 SR(OVL_TABLE_BA(i));
193 continue;
194 }
195 SR(OVL_FIR(i));
196 SR(OVL_PICTURE_SIZE(i));
197 SR(OVL_ACCU0(i));
198 SR(OVL_ACCU1(i));
9b372c2d 199
c6104b8e
AT		 200 for (j = 0; j < 8; j++)
201 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 202
c6104b8e
AT		 203 for (j = 0; j < 8; j++)
204 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 205
c6104b8e
AT		 206 for (j = 0; j < 5; j++)
207 SR(OVL_CONV_COEF(i, j));
ab5ca071 208
c6104b8e
AT		 209 if (dss_has_feature(FEAT_FIR_COEF_V)) {
210 for (j = 0; j < 8; j++)
211 SR(OVL_FIR_COEF_V(i, j));
212 }
9b372c2d 213
c6104b8e
AT		 214 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
215 SR(OVL_BA0_UV(i));
216 SR(OVL_BA1_UV(i));
217 SR(OVL_FIR2(i));
218 SR(OVL_ACCU2_0(i));
219 SR(OVL_ACCU2_1(i));
ab5ca071 220
c6104b8e
AT		 221 for (j = 0; j < 8; j++)
222 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 223
c6104b8e
AT		 224 for (j = 0; j < 8; j++)
225 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 226
c6104b8e
AT		 227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V2(i, j));
229 }
230 if (dss_has_feature(FEAT_ATTR2))
231 SR(OVL_ATTRIBUTES2(i));
ab5ca071 232 }
0cf35df3
MR		 233
234 if (dss_has_feature(FEAT_CORE_CLK_DIV))
235 SR(DIVISOR);
49ea86f3 236
00928eaf 237 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 238 dispc.ctx_valid = true;
239
240 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 241}
242
4fbafaf3 243static void dispc_restore_context(void)
80c39712 244{
c6104b8e 245 int i, j, ctx;
4fbafaf3
TV		 246
247 DSSDBG("dispc_restore_context\n");
248
49ea86f3
TV		 249 if (!dispc.ctx_valid)
250 return;
251
00928eaf 252 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 253
254 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
255 return;
256
257 DSSDBG("ctx_loss_count: saved %d, current %d\n",
258 dispc.ctx_loss_cnt, ctx);
259
75c7d59d 260 /*RR(IRQENABLE);*/
80c39712
TV		 261 /*RR(CONTROL);*/
262 RR(CONFIG);
80c39712 263 RR(LINE_NUMBER);
11354dd5
AT		 264 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
265 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 266 RR(GLOBAL_ALPHA);
c6104b8e 267 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 268 RR(CONFIG2);
80c39712 269
c6104b8e
AT		 270 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
271 RR(DEFAULT_COLOR(i));
272 RR(TRANS_COLOR(i));
273 RR(SIZE_MGR(i));
274 if (i == OMAP_DSS_CHANNEL_DIGIT)
275 continue;
276 RR(TIMING_H(i));
277 RR(TIMING_V(i));
278 RR(POL_FREQ(i));
279 RR(DIVISORo(i));
280
281 RR(DATA_CYCLE1(i));
282 RR(DATA_CYCLE2(i));
283 RR(DATA_CYCLE3(i));
2a205f34 284
332e9d70 285 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 286 RR(CPR_COEF_R(i));
287 RR(CPR_COEF_G(i));
288 RR(CPR_COEF_B(i));
332e9d70 289 }
2a205f34 290 }
80c39712 291
c6104b8e
AT		 292 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
293 RR(OVL_BA0(i));
294 RR(OVL_BA1(i));
295 RR(OVL_POSITION(i));
296 RR(OVL_SIZE(i));
297 RR(OVL_ATTRIBUTES(i));
298 RR(OVL_FIFO_THRESHOLD(i));
299 RR(OVL_ROW_INC(i));
300 RR(OVL_PIXEL_INC(i));
301 if (dss_has_feature(FEAT_PRELOAD))
302 RR(OVL_PRELOAD(i));
303 if (i == OMAP_DSS_GFX) {
304 RR(OVL_WINDOW_SKIP(i));
305 RR(OVL_TABLE_BA(i));
306 continue;
307 }
308 RR(OVL_FIR(i));
309 RR(OVL_PICTURE_SIZE(i));
310 RR(OVL_ACCU0(i));
311 RR(OVL_ACCU1(i));
9b372c2d 312
c6104b8e
AT		 313 for (j = 0; j < 8; j++)
314 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 315
c6104b8e
AT		 316 for (j = 0; j < 8; j++)
317 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 318
c6104b8e
AT		 319 for (j = 0; j < 5; j++)
320 RR(OVL_CONV_COEF(i, j));
ab5ca071 321
c6104b8e
AT		 322 if (dss_has_feature(FEAT_FIR_COEF_V)) {
323 for (j = 0; j < 8; j++)
324 RR(OVL_FIR_COEF_V(i, j));
325 }
9b372c2d 326
c6104b8e
AT		 327 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
328 RR(OVL_BA0_UV(i));
329 RR(OVL_BA1_UV(i));
330 RR(OVL_FIR2(i));
331 RR(OVL_ACCU2_0(i));
332 RR(OVL_ACCU2_1(i));
ab5ca071 333
c6104b8e
AT		 334 for (j = 0; j < 8; j++)
335 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 336
c6104b8e
AT		 337 for (j = 0; j < 8; j++)
338 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 339
c6104b8e
AT		 340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V2(i, j));
342 }
343 if (dss_has_feature(FEAT_ATTR2))
344 RR(OVL_ATTRIBUTES2(i));
ab5ca071 345 }
80c39712 346
0cf35df3
MR		 347 if (dss_has_feature(FEAT_CORE_CLK_DIV))
348 RR(DIVISOR);
349
80c39712
TV		 350 /* enable last, because LCD & DIGIT enable are here */
351 RR(CONTROL);
2a205f34
SS		 352 if (dss_has_feature(FEAT_MGR_LCD2))
353 RR(CONTROL2);
75c7d59d
VS		 354 /* clear spurious SYNC_LOST_DIGIT interrupts */
355 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
356
357 /*
358 * enable last so IRQs won't trigger before
359 * the context is fully restored
360 */
361 RR(IRQENABLE);
49ea86f3
TV		 362
363 DSSDBG("context restored\n");
80c39712
TV		 364}
365
366#undef SR
367#undef RR
368
4fbafaf3
TV		 369int dispc_runtime_get(void)
370{
371 int r;
372
373 DSSDBG("dispc_runtime_get\n");
374
375 r = pm_runtime_get_sync(&dispc.pdev->dev);
376 WARN_ON(r < 0);
377 return r < 0 ? r : 0;
378}
379
380void dispc_runtime_put(void)
381{
382 int r;
383
384 DSSDBG("dispc_runtime_put\n");
385
0eaf9f52 386 r = pm_runtime_put_sync(&dispc.pdev->dev);
4fbafaf3 387 WARN_ON(r < 0);
80c39712
TV		 388}
389
dac57a05
AT		 390static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
391{
392 if (channel == OMAP_DSS_CHANNEL_LCD ||
393 channel == OMAP_DSS_CHANNEL_LCD2)
394 return true;
395 else
396 return false;
397}
4fbafaf3 398
3dcec4d6
TV		 399u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
400{
401 switch (channel) {
402 case OMAP_DSS_CHANNEL_LCD:
403 return DISPC_IRQ_VSYNC;
404 case OMAP_DSS_CHANNEL_LCD2:
405 return DISPC_IRQ_VSYNC2;
406 case OMAP_DSS_CHANNEL_DIGIT:
407 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
408 default:
409 BUG();
410 }
411}
412
7d1365c9
TV		 413u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
414{
415 switch (channel) {
416 case OMAP_DSS_CHANNEL_LCD:
417 return DISPC_IRQ_FRAMEDONE;
418 case OMAP_DSS_CHANNEL_LCD2:
419 return DISPC_IRQ_FRAMEDONE2;
420 case OMAP_DSS_CHANNEL_DIGIT:
421 return 0;
422 default:
423 BUG();
424 }
425}
426
26d9dd0d 427bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 428{
429 int bit;
430
dac57a05 431 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 432 bit = 5; /* GOLCD */
433 else
434 bit = 6; /* GODIGIT */
435
2a205f34
SS		 436 if (channel == OMAP_DSS_CHANNEL_LCD2)
437 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
438 else
439 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 440}
441
26d9dd0d 442void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 443{
444 int bit;
2a205f34 445 bool enable_bit, go_bit;
80c39712 446
dac57a05 447 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 448 bit = 0; /* LCDENABLE */
449 else
450 bit = 1; /* DIGITALENABLE */
451
452 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 453 if (channel == OMAP_DSS_CHANNEL_LCD2)
454 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
455 else
456 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
457
458 if (!enable_bit)
e6d80f95 459 return;
80c39712 460
dac57a05 461 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 462 bit = 5; /* GOLCD */
463 else
464 bit = 6; /* GODIGIT */
465
2a205f34
SS		 466 if (channel == OMAP_DSS_CHANNEL_LCD2)
467 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
468 else
469 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
470
471 if (go_bit) {
80c39712 472 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 473 return;
80c39712
TV		 474 }
475
2a205f34
SS		 476 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
477 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 478
2a205f34
SS		 479 if (channel == OMAP_DSS_CHANNEL_LCD2)
480 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
481 else
482 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 483}
484
f0e5caab 485static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 486{
9b372c2d 487 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 488}
489
f0e5caab 490static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 491{
9b372c2d 492 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 493}
494
f0e5caab 495static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 496{
9b372c2d 497 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 498}
499
f0e5caab 500static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 501{
502 BUG_ON(plane == OMAP_DSS_GFX);
503
504 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
505}
506
f0e5caab
TV		 507static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
508 u32 value)
ab5ca071
AJ		 509{
510 BUG_ON(plane == OMAP_DSS_GFX);
511
512 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
513}
514
f0e5caab 515static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 516{
517 BUG_ON(plane == OMAP_DSS_GFX);
518
519 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
520}
521
debd9074
CM		 522static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
523 int fir_vinc, int five_taps,
524 enum omap_color_component color_comp)
80c39712 525{
debd9074 526 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 527 int i;
528
debd9074
CM		 529 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
530 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 531
532 for (i = 0; i < 8; i++) {
533 u32 h, hv;
534
debd9074
CM		 535 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
536 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
537 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
538 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
539 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
540 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
541 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
542 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 543
0d66cbb5 544 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 545 dispc_ovl_write_firh_reg(plane, i, h);
546 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 547 } else {
f0e5caab
TV		 548 dispc_ovl_write_firh2_reg(plane, i, h);
549 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 550 }
551
80c39712
TV		 552 }
553
66be8f6c
GI		 554 if (five_taps) {
555 for (i = 0; i < 8; i++) {
556 u32 v;
debd9074
CM		 557 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
558 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 559 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 560 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 561 else
f0e5caab 562 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 563 }
80c39712
TV		 564 }
565}
566
567static void _dispc_setup_color_conv_coef(void)
568{
ac01c29e 569 int i;
80c39712
TV		 570 const struct color_conv_coef {
571 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
572 int full_range;
573 } ctbl_bt601_5 = {
574 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
575 };
576
577 const struct color_conv_coef *ct;
578
579#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
580
581 ct = &ctbl_bt601_5;
582
ac01c29e
AT		 583 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
584 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
585 CVAL(ct->rcr, ct->ry));
586 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
587 CVAL(ct->gy, ct->rcb));
588 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
589 CVAL(ct->gcb, ct->gcr));
590 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
591 CVAL(ct->bcr, ct->by));
592 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
593 CVAL(0, ct->bcb));
594
595 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
596 11, 11);
597 }
80c39712
TV		 598
599#undef CVAL
80c39712
TV		 600}
601
602
f0e5caab 603static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 604{
9b372c2d 605 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 606}
607
f0e5caab 608static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 609{
9b372c2d 610 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 611}
612
f0e5caab 613static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 614{
615 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
616}
617
f0e5caab 618static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 619{
620 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
621}
622
f0e5caab 623static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 624{
80c39712 625 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 626
627 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 628}
629
f0e5caab 630static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 631{
80c39712 632 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 633
634 if (plane == OMAP_DSS_GFX)
635 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
636 else
637 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 638}
639
f0e5caab 640static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 641{
642 u32 val;
80c39712
TV		 643
644 BUG_ON(plane == OMAP_DSS_GFX);
645
646 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 647
648 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 649}
650
54128701
AT		 651static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
652{
653 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
654
655 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
656 return;
657
658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
659}
660
661static void dispc_ovl_enable_zorder_planes(void)
662{
663 int i;
664
665 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
666 return;
667
668 for (i = 0; i < dss_feat_get_num_ovls(); i++)
669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
670}
671
f0e5caab 672static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 673{
f6dc8150 674 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 675
f6dc8150 676 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 677 return;
678
9b372c2d 679 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 680}
681
f0e5caab 682static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 683{
b8c095b4 684 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 685 int shift;
f6dc8150 686 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 687
f6dc8150 688 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 689 return;
a0acb557 690
fe3cc9d6
TV		 691 shift = shifts[plane];
692 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 693}
694
f0e5caab 695static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 696{
9b372c2d 697 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 698}
699
f0e5caab 700static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 701{
9b372c2d 702 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 703}
704
f0e5caab 705static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 706 enum omap_color_mode color_mode)
707{
708 u32 m = 0;
f20e4220
AJ		 709 if (plane != OMAP_DSS_GFX) {
710 switch (color_mode) {
711 case OMAP_DSS_COLOR_NV12:
712 m = 0x0; break;
08f3267e 713 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 714 m = 0x1; break;
715 case OMAP_DSS_COLOR_RGBA16:
716 m = 0x2; break;
08f3267e 717 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 718 m = 0x4; break;
719 case OMAP_DSS_COLOR_ARGB16:
720 m = 0x5; break;
721 case OMAP_DSS_COLOR_RGB16:
722 m = 0x6; break;
723 case OMAP_DSS_COLOR_ARGB16_1555:
724 m = 0x7; break;
725 case OMAP_DSS_COLOR_RGB24U:
726 m = 0x8; break;
727 case OMAP_DSS_COLOR_RGB24P:
728 m = 0x9; break;
729 case OMAP_DSS_COLOR_YUV2:
730 m = 0xa; break;
731 case OMAP_DSS_COLOR_UYVY:
732 m = 0xb; break;
733 case OMAP_DSS_COLOR_ARGB32:
734 m = 0xc; break;
735 case OMAP_DSS_COLOR_RGBA32:
736 m = 0xd; break;
737 case OMAP_DSS_COLOR_RGBX32:
738 m = 0xe; break;
739 case OMAP_DSS_COLOR_XRGB16_1555:
740 m = 0xf; break;
741 default:
742 BUG(); break;
743 }
744 } else {
745 switch (color_mode) {
746 case OMAP_DSS_COLOR_CLUT1:
747 m = 0x0; break;
748 case OMAP_DSS_COLOR_CLUT2:
749 m = 0x1; break;
750 case OMAP_DSS_COLOR_CLUT4:
751 m = 0x2; break;
752 case OMAP_DSS_COLOR_CLUT8:
753 m = 0x3; break;
754 case OMAP_DSS_COLOR_RGB12U:
755 m = 0x4; break;
756 case OMAP_DSS_COLOR_ARGB16:
757 m = 0x5; break;
758 case OMAP_DSS_COLOR_RGB16:
759 m = 0x6; break;
760 case OMAP_DSS_COLOR_ARGB16_1555:
761 m = 0x7; break;
762 case OMAP_DSS_COLOR_RGB24U:
763 m = 0x8; break;
764 case OMAP_DSS_COLOR_RGB24P:
765 m = 0x9; break;
08f3267e 766 case OMAP_DSS_COLOR_RGBX16:
f20e4220 767 m = 0xa; break;
08f3267e 768 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 769 m = 0xb; break;
770 case OMAP_DSS_COLOR_ARGB32:
771 m = 0xc; break;
772 case OMAP_DSS_COLOR_RGBA32:
773 m = 0xd; break;
774 case OMAP_DSS_COLOR_RGBX32:
775 m = 0xe; break;
776 case OMAP_DSS_COLOR_XRGB16_1555:
777 m = 0xf; break;
778 default:
779 BUG(); break;
780 }
80c39712
TV		 781 }
782
9b372c2d 783 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 784}
785
f427984e 786void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 787{
788 int shift;
789 u32 val;
2a205f34 790 int chan = 0, chan2 = 0;
80c39712
TV		 791
792 switch (plane) {
793 case OMAP_DSS_GFX:
794 shift = 8;
795 break;
796 case OMAP_DSS_VIDEO1:
797 case OMAP_DSS_VIDEO2:
b8c095b4 798 case OMAP_DSS_VIDEO3:
80c39712
TV		 799 shift = 16;
800 break;
801 default:
802 BUG();
803 return;
804 }
805
9b372c2d 806 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 807 if (dss_has_feature(FEAT_MGR_LCD2)) {
808 switch (channel) {
809 case OMAP_DSS_CHANNEL_LCD:
810 chan = 0;
811 chan2 = 0;
812 break;
813 case OMAP_DSS_CHANNEL_DIGIT:
814 chan = 1;
815 chan2 = 0;
816 break;
817 case OMAP_DSS_CHANNEL_LCD2:
818 chan = 0;
819 chan2 = 1;
820 break;
821 default:
822 BUG();
823 }
824
825 val = FLD_MOD(val, chan, shift, shift);
826 val = FLD_MOD(val, chan2, 31, 30);
827 } else {
828 val = FLD_MOD(val, channel, shift, shift);
829 }
9b372c2d 830 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 831}
832
2cc5d1af
TV		 833static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
834{
835 int shift;
836 u32 val;
837 enum omap_channel channel;
838
839 switch (plane) {
840 case OMAP_DSS_GFX:
841 shift = 8;
842 break;
843 case OMAP_DSS_VIDEO1:
844 case OMAP_DSS_VIDEO2:
845 case OMAP_DSS_VIDEO3:
846 shift = 16;
847 break;
848 default:
849 BUG();
850 }
851
852 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
853
854 if (dss_has_feature(FEAT_MGR_LCD2)) {
855 if (FLD_GET(val, 31, 30) == 0)
856 channel = FLD_GET(val, shift, shift);
857 else
858 channel = OMAP_DSS_CHANNEL_LCD2;
859 } else {
860 channel = FLD_GET(val, shift, shift);
861 }
862
863 return channel;
864}
865
f0e5caab 866static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 867 enum omap_burst_size burst_size)
868{
b8c095b4 869 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 870 int shift;
80c39712 871
fe3cc9d6 872 shift = shifts[plane];
5ed8cf5b 873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 874}
875
5ed8cf5b
TV		 876static void dispc_configure_burst_sizes(void)
877{
878 int i;
879 const int burst_size = BURST_SIZE_X8;
880
881 /* Configure burst size always to maximum size */
882 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 883 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 884}
885
83fa2f2e 886static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 887{
888 unsigned unit = dss_feat_get_burst_size_unit();
889 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
890 return unit * 8;
891}
892
d3862610
M		 893void dispc_enable_gamma_table(bool enable)
894{
895 /*
896 * This is partially implemented to support only disabling of
897 * the gamma table.
898 */
899 if (enable) {
900 DSSWARN("Gamma table enabling for TV not yet supported");
901 return;
902 }
903
904 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
905}
906
c64dca40 907static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 908{
909 u16 reg;
910
911 if (channel == OMAP_DSS_CHANNEL_LCD)
912 reg = DISPC_CONFIG;
913 else if (channel == OMAP_DSS_CHANNEL_LCD2)
914 reg = DISPC_CONFIG2;
915 else
916 return;
917
918 REG_FLD_MOD(reg, enable, 15, 15);
919}
920
c64dca40 921static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 922 struct omap_dss_cpr_coefs *coefs)
923{
924 u32 coef_r, coef_g, coef_b;
925
dac57a05 926 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 927 return;
928
929 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
930 FLD_VAL(coefs->rb, 9, 0);
931 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
932 FLD_VAL(coefs->gb, 9, 0);
933 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
934 FLD_VAL(coefs->bb, 9, 0);
935
936 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
937 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
938 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
939}
940
f0e5caab 941static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 942{
943 u32 val;
944
945 BUG_ON(plane == OMAP_DSS_GFX);
946
9b372c2d 947 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 948 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 949 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 950}
951
c3d92529 952static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 953{
b8c095b4 954 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 955 int shift;
80c39712 956
fe3cc9d6
TV		 957 shift = shifts[plane];
958 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 959}
960
8f366162 961static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 962 u16 height)
80c39712
TV		 963{
964 u32 val;
80c39712 965
80c39712 966 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 967 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 968}
969
970static void dispc_read_plane_fifo_sizes(void)
971{
80c39712
TV		 972 u32 size;
973 int plane;
a0acb557 974 u8 start, end;
5ed8cf5b
TV		 975 u32 unit;
976
977 unit = dss_feat_get_buffer_size_unit();
80c39712 978
a0acb557 979 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 980
e13a138b 981 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 982 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
983 size *= unit;
80c39712
TV		 984 dispc.fifo_size[plane] = size;
985 }
80c39712
TV		 986}
987
83fa2f2e 988static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 989{
990 return dispc.fifo_size[plane];
991}
992
6f04e1bf 993void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 994{
a0acb557 995 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 996 u32 unit;
997
998 unit = dss_feat_get_buffer_size_unit();
999
1000 WARN_ON(low % unit != 0);
1001 WARN_ON(high % unit != 0);
1002
1003 low /= unit;
1004 high /= unit;
a0acb557 1005
9b372c2d
AT		 1006 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1007 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1008
3cb5d966 1009 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1010 plane,
9b372c2d 1011 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1012 lo_start, lo_end) * unit,
9b372c2d 1013 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1014 hi_start, hi_end) * unit,
1015 low * unit, high * unit);
80c39712 1016
9b372c2d 1017 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1018 FLD_VAL(high, hi_start, hi_end) |
1019 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1020}
1021
1022void dispc_enable_fifomerge(bool enable)
1023{
e6b0f884
TV		 1024 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1025 WARN_ON(enable);
1026 return;
1027 }
1028
80c39712
TV		 1029 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1030 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1031}
1032
83fa2f2e
TV		 1033void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1034 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
1035{
1036 /*
1037 * All sizes are in bytes. Both the buffer and burst are made of
1038 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1039 */
1040
1041 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1042 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1043 int i;
83fa2f2e
TV		 1044
1045 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1046 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1047
e0e405b9
TV		 1048 if (use_fifomerge) {
1049 total_fifo_size = 0;
1050 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1051 total_fifo_size += dispc_ovl_get_fifo_size(i);
1052 } else {
1053 total_fifo_size = ovl_fifo_size;
1054 }
1055
1056 /*
1057 * We use the same low threshold for both fifomerge and non-fifomerge
1058 * cases, but for fifomerge we calculate the high threshold using the
1059 * combined fifo size
1060 */
1061
1062 if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1063 *fifo_low = ovl_fifo_size - burst_size * 2;
1064 *fifo_high = total_fifo_size - burst_size;
1065 } else {
1066 *fifo_low = ovl_fifo_size - burst_size;
1067 *fifo_high = total_fifo_size - buf_unit;
1068 }
83fa2f2e
TV		 1069}
1070
f0e5caab 1071static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1072 int hinc, int vinc,
1073 enum omap_color_component color_comp)
80c39712
TV		 1074{
1075 u32 val;
80c39712 1076
0d66cbb5
AJ		 1077 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1078 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1079
0d66cbb5
AJ		 1080 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1081 &hinc_start, &hinc_end);
1082 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1083 &vinc_start, &vinc_end);
1084 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1085 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1086
0d66cbb5
AJ		 1087 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1088 } else {
1089 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1090 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1091 }
80c39712
TV		 1092}
1093
f0e5caab 1094static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1095{
1096 u32 val;
87a7484b 1097 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1098
87a7484b
AT		 1099 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1100 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1101
1102 val = FLD_VAL(vaccu, vert_start, vert_end) |
1103 FLD_VAL(haccu, hor_start, hor_end);
1104
9b372c2d 1105 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1106}
1107
f0e5caab 1108static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1109{
1110 u32 val;
87a7484b 1111 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1112
87a7484b
AT		 1113 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1114 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1115
1116 val = FLD_VAL(vaccu, vert_start, vert_end) |
1117 FLD_VAL(haccu, hor_start, hor_end);
1118
9b372c2d 1119 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1120}
1121
f0e5caab
TV		 1122static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1123 int vaccu)
ab5ca071
AJ		 1124{
1125 u32 val;
1126
1127 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1128 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1129}
1130
f0e5caab
TV		 1131static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1132 int vaccu)
ab5ca071
AJ		 1133{
1134 u32 val;
1135
1136 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1137 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1138}
80c39712 1139
f0e5caab 1140static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1141 u16 orig_width, u16 orig_height,
1142 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1143 bool five_taps, u8 rotation,
1144 enum omap_color_component color_comp)
80c39712 1145{
0d66cbb5 1146 int fir_hinc, fir_vinc;
80c39712 1147
ed14a3ce
AJ		 1148 fir_hinc = 1024 * orig_width / out_width;
1149 fir_vinc = 1024 * orig_height / out_height;
80c39712 1150
debd9074
CM		 1151 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1152 color_comp);
f0e5caab 1153 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1154}
1155
f0e5caab 1156static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1157 u16 orig_width, u16 orig_height,
1158 u16 out_width, u16 out_height,
1159 bool ilace, bool five_taps,
1160 bool fieldmode, enum omap_color_mode color_mode,
1161 u8 rotation)
1162{
1163 int accu0 = 0;
1164 int accu1 = 0;
1165 u32 l;
80c39712 1166
f0e5caab 1167 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1168 out_width, out_height, five_taps,
1169 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1170 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1171
87a7484b
AT		 1172 /* RESIZEENABLE and VERTICALTAPS */
1173 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1174 l |= (orig_width != out_width) ? (1 << 5) : 0;
1175 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1176 l |= five_taps ? (1 << 21) : 0;
80c39712 1177
87a7484b
AT		 1178 /* VRESIZECONF and HRESIZECONF */
1179 if (dss_has_feature(FEAT_RESIZECONF)) {
1180 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1181 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1182 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1183 }
80c39712 1184
87a7484b
AT		 1185 /* LINEBUFFERSPLIT */
1186 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1187 l &= ~(0x1 << 22);
1188 l |= five_taps ? (1 << 22) : 0;
1189 }
80c39712 1190
9b372c2d 1191 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1192
1193 /*
1194 * field 0 = even field = bottom field
1195 * field 1 = odd field = top field
1196 */
1197 if (ilace && !fieldmode) {
1198 accu1 = 0;
0d66cbb5 1199 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1200 if (accu0 >= 1024/2) {
1201 accu1 = 1024/2;
1202 accu0 -= accu1;
1203 }
1204 }
1205
f0e5caab
TV		 1206 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1207 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1208}
1209
f0e5caab 1210static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1211 u16 orig_width, u16 orig_height,
1212 u16 out_width, u16 out_height,
1213 bool ilace, bool five_taps,
1214 bool fieldmode, enum omap_color_mode color_mode,
1215 u8 rotation)
1216{
1217 int scale_x = out_width != orig_width;
1218 int scale_y = out_height != orig_height;
1219
1220 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1221 return;
1222 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1223 color_mode != OMAP_DSS_COLOR_UYVY &&
1224 color_mode != OMAP_DSS_COLOR_NV12)) {
1225 /* reset chroma resampling for RGB formats */
1226 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1227 return;
1228 }
1229 switch (color_mode) {
1230 case OMAP_DSS_COLOR_NV12:
1231 /* UV is subsampled by 2 vertically*/
1232 orig_height >>= 1;
1233 /* UV is subsampled by 2 horz.*/
1234 orig_width >>= 1;
1235 break;
1236 case OMAP_DSS_COLOR_YUV2:
1237 case OMAP_DSS_COLOR_UYVY:
1238 /*For YUV422 with 90/270 rotation,
1239 *we don't upsample chroma
1240 */
1241 if (rotation == OMAP_DSS_ROT_0 ||
1242 rotation == OMAP_DSS_ROT_180)
1243 /* UV is subsampled by 2 hrz*/
1244 orig_width >>= 1;
1245 /* must use FIR for YUV422 if rotated */
1246 if (rotation != OMAP_DSS_ROT_0)
1247 scale_x = scale_y = true;
1248 break;
1249 default:
1250 BUG();
1251 }
1252
1253 if (out_width != orig_width)
1254 scale_x = true;
1255 if (out_height != orig_height)
1256 scale_y = true;
1257
f0e5caab 1258 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1259 out_width, out_height, five_taps,
1260 rotation, DISPC_COLOR_COMPONENT_UV);
1261
1262 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1263 (scale_x || scale_y) ? 1 : 0, 8, 8);
1264 /* set H scaling */
1265 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1266 /* set V scaling */
1267 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1268
f0e5caab
TV		 1269 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1270 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
0d66cbb5
AJ		 1271}
1272
f0e5caab 1273static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1274 u16 orig_width, u16 orig_height,
1275 u16 out_width, u16 out_height,
1276 bool ilace, bool five_taps,
1277 bool fieldmode, enum omap_color_mode color_mode,
1278 u8 rotation)
1279{
1280 BUG_ON(plane == OMAP_DSS_GFX);
1281
f0e5caab 1282 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1283 orig_width, orig_height,
1284 out_width, out_height,
1285 ilace, five_taps,
1286 fieldmode, color_mode,
1287 rotation);
1288
f0e5caab 1289 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1290 orig_width, orig_height,
1291 out_width, out_height,
1292 ilace, five_taps,
1293 fieldmode, color_mode,
1294 rotation);
1295}
1296
f0e5caab 1297static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1298 bool mirroring, enum omap_color_mode color_mode)
1299{
87a7484b
AT		 1300 bool row_repeat = false;
1301 int vidrot = 0;
1302
80c39712
TV		 1303 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1304 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1305
1306 if (mirroring) {
1307 switch (rotation) {
1308 case OMAP_DSS_ROT_0:
1309 vidrot = 2;
1310 break;
1311 case OMAP_DSS_ROT_90:
1312 vidrot = 1;
1313 break;
1314 case OMAP_DSS_ROT_180:
1315 vidrot = 0;
1316 break;
1317 case OMAP_DSS_ROT_270:
1318 vidrot = 3;
1319 break;
1320 }
1321 } else {
1322 switch (rotation) {
1323 case OMAP_DSS_ROT_0:
1324 vidrot = 0;
1325 break;
1326 case OMAP_DSS_ROT_90:
1327 vidrot = 1;
1328 break;
1329 case OMAP_DSS_ROT_180:
1330 vidrot = 2;
1331 break;
1332 case OMAP_DSS_ROT_270:
1333 vidrot = 3;
1334 break;
1335 }
1336 }
1337
80c39712 1338 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1339 row_repeat = true;
80c39712 1340 else
87a7484b 1341 row_repeat = false;
80c39712 1342 }
87a7484b 1343
9b372c2d 1344 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1345 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1346 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1347 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1348}
1349
1350static int color_mode_to_bpp(enum omap_color_mode color_mode)
1351{
1352 switch (color_mode) {
1353 case OMAP_DSS_COLOR_CLUT1:
1354 return 1;
1355 case OMAP_DSS_COLOR_CLUT2:
1356 return 2;
1357 case OMAP_DSS_COLOR_CLUT4:
1358 return 4;
1359 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1360 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1361 return 8;
1362 case OMAP_DSS_COLOR_RGB12U:
1363 case OMAP_DSS_COLOR_RGB16:
1364 case OMAP_DSS_COLOR_ARGB16:
1365 case OMAP_DSS_COLOR_YUV2:
1366 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1367 case OMAP_DSS_COLOR_RGBA16:
1368 case OMAP_DSS_COLOR_RGBX16:
1369 case OMAP_DSS_COLOR_ARGB16_1555:
1370 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1371 return 16;
1372 case OMAP_DSS_COLOR_RGB24P:
1373 return 24;
1374 case OMAP_DSS_COLOR_RGB24U:
1375 case OMAP_DSS_COLOR_ARGB32:
1376 case OMAP_DSS_COLOR_RGBA32:
1377 case OMAP_DSS_COLOR_RGBX32:
1378 return 32;
1379 default:
1380 BUG();
1381 }
1382}
1383
1384static s32 pixinc(int pixels, u8 ps)
1385{
1386 if (pixels == 1)
1387 return 1;
1388 else if (pixels > 1)
1389 return 1 + (pixels - 1) * ps;
1390 else if (pixels < 0)
1391 return 1 - (-pixels + 1) * ps;
1392 else
1393 BUG();
1394}
1395
1396static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1397 u16 screen_width,
1398 u16 width, u16 height,
1399 enum omap_color_mode color_mode, bool fieldmode,
1400 unsigned int field_offset,
1401 unsigned *offset0, unsigned *offset1,
aed74b55 1402 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1403{
1404 u8 ps;
1405
1406 /* FIXME CLUT formats */
1407 switch (color_mode) {
1408 case OMAP_DSS_COLOR_CLUT1:
1409 case OMAP_DSS_COLOR_CLUT2:
1410 case OMAP_DSS_COLOR_CLUT4:
1411 case OMAP_DSS_COLOR_CLUT8:
1412 BUG();
1413 return;
1414 case OMAP_DSS_COLOR_YUV2:
1415 case OMAP_DSS_COLOR_UYVY:
1416 ps = 4;
1417 break;
1418 default:
1419 ps = color_mode_to_bpp(color_mode) / 8;
1420 break;
1421 }
1422
1423 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1424 width, height);
1425
1426 /*
1427 * field 0 = even field = bottom field
1428 * field 1 = odd field = top field
1429 */
1430 switch (rotation + mirror * 4) {
1431 case OMAP_DSS_ROT_0:
1432 case OMAP_DSS_ROT_180:
1433 /*
1434 * If the pixel format is YUV or UYVY divide the width
1435 * of the image by 2 for 0 and 180 degree rotation.
1436 */
1437 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1438 color_mode == OMAP_DSS_COLOR_UYVY)
1439 width = width >> 1;
1440 case OMAP_DSS_ROT_90:
1441 case OMAP_DSS_ROT_270:
1442 *offset1 = 0;
1443 if (field_offset)
1444 *offset0 = field_offset * screen_width * ps;
1445 else
1446 *offset0 = 0;
1447
aed74b55
CM		 1448 *row_inc = pixinc(1 +
1449 (y_predecim * screen_width - x_predecim * width) +
1450 (fieldmode ? screen_width : 0), ps);
1451 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1452 break;
1453
1454 case OMAP_DSS_ROT_0 + 4:
1455 case OMAP_DSS_ROT_180 + 4:
1456 /* If the pixel format is YUV or UYVY divide the width
1457 * of the image by 2 for 0 degree and 180 degree
1458 */
1459 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1460 color_mode == OMAP_DSS_COLOR_UYVY)
1461 width = width >> 1;
1462 case OMAP_DSS_ROT_90 + 4:
1463 case OMAP_DSS_ROT_270 + 4:
1464 *offset1 = 0;
1465 if (field_offset)
1466 *offset0 = field_offset * screen_width * ps;
1467 else
1468 *offset0 = 0;
aed74b55
CM		 1469 *row_inc = pixinc(1 -
1470 (y_predecim * screen_width + x_predecim * width) -
1471 (fieldmode ? screen_width : 0), ps);
1472 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1473 break;
1474
1475 default:
1476 BUG();
1477 }
1478}
1479
1480static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1481 u16 screen_width,
1482 u16 width, u16 height,
1483 enum omap_color_mode color_mode, bool fieldmode,
1484 unsigned int field_offset,
1485 unsigned *offset0, unsigned *offset1,
aed74b55 1486 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1487{
1488 u8 ps;
1489 u16 fbw, fbh;
1490
1491 /* FIXME CLUT formats */
1492 switch (color_mode) {
1493 case OMAP_DSS_COLOR_CLUT1:
1494 case OMAP_DSS_COLOR_CLUT2:
1495 case OMAP_DSS_COLOR_CLUT4:
1496 case OMAP_DSS_COLOR_CLUT8:
1497 BUG();
1498 return;
1499 default:
1500 ps = color_mode_to_bpp(color_mode) / 8;
1501 break;
1502 }
1503
1504 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1505 width, height);
1506
1507 /* width & height are overlay sizes, convert to fb sizes */
1508
1509 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1510 fbw = width;
1511 fbh = height;
1512 } else {
1513 fbw = height;
1514 fbh = width;
1515 }
1516
1517 /*
1518 * field 0 = even field = bottom field
1519 * field 1 = odd field = top field
1520 */
1521 switch (rotation + mirror * 4) {
1522 case OMAP_DSS_ROT_0:
1523 *offset1 = 0;
1524 if (field_offset)
1525 *offset0 = *offset1 + field_offset * screen_width * ps;
1526 else
1527 *offset0 = *offset1;
aed74b55
CM		 1528 *row_inc = pixinc(1 +
1529 (y_predecim * screen_width - fbw * x_predecim) +
1530 (fieldmode ? screen_width : 0), ps);
1531 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1532 color_mode == OMAP_DSS_COLOR_UYVY)
1533 *pix_inc = pixinc(x_predecim, 2 * ps);
1534 else
1535 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1536 break;
1537 case OMAP_DSS_ROT_90:
1538 *offset1 = screen_width * (fbh - 1) * ps;
1539 if (field_offset)
1540 *offset0 = *offset1 + field_offset * ps;
1541 else
1542 *offset0 = *offset1;
aed74b55
CM		 1543 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1544 y_predecim + (fieldmode ? 1 : 0), ps);
1545 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1546 break;
1547 case OMAP_DSS_ROT_180:
1548 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1549 if (field_offset)
1550 *offset0 = *offset1 - field_offset * screen_width * ps;
1551 else
1552 *offset0 = *offset1;
1553 *row_inc = pixinc(-1 -
aed74b55
CM		 1554 (y_predecim * screen_width - fbw * x_predecim) -
1555 (fieldmode ? screen_width : 0), ps);
1556 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1557 color_mode == OMAP_DSS_COLOR_UYVY)
1558 *pix_inc = pixinc(-x_predecim, 2 * ps);
1559 else
1560 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1561 break;
1562 case OMAP_DSS_ROT_270:
1563 *offset1 = (fbw - 1) * ps;
1564 if (field_offset)
1565 *offset0 = *offset1 - field_offset * ps;
1566 else
1567 *offset0 = *offset1;
aed74b55
CM		 1568 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1569 y_predecim - (fieldmode ? 1 : 0), ps);
1570 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1571 break;
1572
1573 /* mirroring */
1574 case OMAP_DSS_ROT_0 + 4:
1575 *offset1 = (fbw - 1) * ps;
1576 if (field_offset)
1577 *offset0 = *offset1 + field_offset * screen_width * ps;
1578 else
1579 *offset0 = *offset1;
aed74b55 1580 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1581 (fieldmode ? screen_width : 0),
1582 ps);
aed74b55
CM		 1583 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1584 color_mode == OMAP_DSS_COLOR_UYVY)
1585 *pix_inc = pixinc(-x_predecim, 2 * ps);
1586 else
1587 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1588 break;
1589
1590 case OMAP_DSS_ROT_90 + 4:
1591 *offset1 = 0;
1592 if (field_offset)
1593 *offset0 = *offset1 + field_offset * ps;
1594 else
1595 *offset0 = *offset1;
aed74b55
CM		 1596 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1597 y_predecim + (fieldmode ? 1 : 0),
80c39712 1598 ps);
aed74b55 1599 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1600 break;
1601
1602 case OMAP_DSS_ROT_180 + 4:
1603 *offset1 = screen_width * (fbh - 1) * ps;
1604 if (field_offset)
1605 *offset0 = *offset1 - field_offset * screen_width * ps;
1606 else
1607 *offset0 = *offset1;
aed74b55 1608 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1609 (fieldmode ? screen_width : 0),
1610 ps);
aed74b55
CM		 1611 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1612 color_mode == OMAP_DSS_COLOR_UYVY)
1613 *pix_inc = pixinc(x_predecim, 2 * ps);
1614 else
1615 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1616 break;
1617
1618 case OMAP_DSS_ROT_270 + 4:
1619 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1620 if (field_offset)
1621 *offset0 = *offset1 - field_offset * ps;
1622 else
1623 *offset0 = *offset1;
aed74b55
CM		 1624 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1625 y_predecim - (fieldmode ? 1 : 0),
80c39712 1626 ps);
aed74b55 1627 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1628 break;
1629
1630 default:
1631 BUG();
1632 }
1633}
1634
7faa9233
CM		 1635/*
1636 * This function is used to avoid synclosts in OMAP3, because of some
1637 * undocumented horizontal position and timing related limitations.
1638 */
81ab95b7
AT		 1639static int check_horiz_timing_omap3(enum omap_channel channel,
1640 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1641 u16 width, u16 height, u16 out_width, u16 out_height)
1642{
1643 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1644 unsigned long nonactive, lclk, pclk;
1645 static const u8 limits[3] = { 8, 10, 20 };
1646 u64 val, blank;
1647 int i;
1648
81ab95b7 1649 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 1650 pclk = dispc_mgr_pclk_rate(channel);
1651 if (dispc_mgr_is_lcd(channel))
1652 lclk = dispc_mgr_lclk_rate(channel);
1653 else
1654 lclk = dispc_fclk_rate();
1655
1656 i = 0;
1657 if (out_height < height)
1658 i++;
1659 if (out_width < width)
1660 i++;
81ab95b7 1661 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1662 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1663 if (blank <= limits[i])
1664 return -EINVAL;
1665
1666 /*
1667 * Pixel data should be prepared before visible display point starts.
1668 * So, atleast DS-2 lines must have already been fetched by DISPC
1669 * during nonactive - pos_x period.
1670 */
1671 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1672 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1673 val, max(0, DS - 2) * width);
1674 if (val < max(0, DS - 2) * width)
1675 return -EINVAL;
1676
1677 /*
1678 * All lines need to be refilled during the nonactive period of which
1679 * only one line can be loaded during the active period. So, atleast
1680 * DS - 1 lines should be loaded during nonactive period.
1681 */
1682 val = div_u64((u64)nonactive * lclk, pclk);
1683 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1684 val, max(0, DS - 1) * width);
1685 if (val < max(0, DS - 1) * width)
1686 return -EINVAL;
1687
1688 return 0;
1689}
1690
8b53d991 1691static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1692 const struct omap_video_timings *mgr_timings, u16 width,
1693 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1694 enum omap_color_mode color_mode)
80c39712 1695{
8b53d991 1696 u32 core_clk = 0;
26d9dd0d 1697 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1698
7282f1b7
CM		 1699 if (height <= out_height && width <= out_width)
1700 return (unsigned long) pclk;
1701
80c39712 1702 if (height > out_height) {
81ab95b7 1703 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1704
1705 tmp = pclk * height * out_width;
1706 do_div(tmp, 2 * out_height * ppl);
8b53d991 1707 core_clk = tmp;
80c39712 1708
2d9c5597
VS		 1709 if (height > 2 * out_height) {
1710 if (ppl == out_width)
1711 return 0;
1712
80c39712
TV		 1713 tmp = pclk * (height - 2 * out_height) * out_width;
1714 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1715 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1716 }
1717 }
1718
1719 if (width > out_width) {
1720 tmp = pclk * width;
1721 do_div(tmp, out_width);
8b53d991 1722 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1723
1724 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1725 core_clk <<= 1;
80c39712
TV		 1726 }
1727
8b53d991 1728 return core_clk;
80c39712
TV		 1729}
1730
8b53d991 1731static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
ff1b2cde 1732 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1733{
1734 unsigned int hf, vf;
79ee89cd 1735 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1736
1737 /*
1738 * FIXME how to determine the 'A' factor
1739 * for the no downscaling case ?
1740 */
1741
1742 if (width > 3 * out_width)
1743 hf = 4;
1744 else if (width > 2 * out_width)
1745 hf = 3;
1746 else if (width > out_width)
1747 hf = 2;
1748 else
1749 hf = 1;
1750
1751 if (height > out_height)
1752 vf = 2;
1753 else
1754 vf = 1;
1755
7282f1b7
CM		 1756 if (cpu_is_omap24xx()) {
1757 if (vf > 1 && hf > 1)
79ee89cd 1758 return pclk * 4;
7282f1b7 1759 else
79ee89cd 1760 return pclk * 2;
7282f1b7 1761 } else if (cpu_is_omap34xx()) {
79ee89cd 1762 return pclk * vf * hf;
7282f1b7 1763 } else {
79ee89cd
AT		 1764 if (hf > 1)
1765 return DIV_ROUND_UP(pclk, out_width) * width;
1766 else
1767 return pclk;
7282f1b7 1768 }
80c39712
TV		 1769}
1770
79ad75f2 1771static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 1772 enum omap_channel channel,
1773 const struct omap_video_timings *mgr_timings,
1774 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 1775 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 1776 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 1777{
1778 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1779 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1780 const int maxsinglelinewidth =
1781 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
aed74b55 1782 const int max_decim_limit = 16;
8b53d991 1783 unsigned long core_clk = 0;
aed74b55
CM		 1784 int decim_x, decim_y, error, min_factor;
1785 u16 in_width, in_height, in_width_max = 0;
79ad75f2 1786
f95cb5eb
TV		 1787 if (width == out_width && height == out_height)
1788 return 0;
1789
1790 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1791 return -EINVAL;
79ad75f2 1792
aed74b55
CM		 1793 *x_predecim = max_decim_limit;
1794 *y_predecim = max_decim_limit;
1795
1796 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
1797 color_mode == OMAP_DSS_COLOR_CLUT2 ||
1798 color_mode == OMAP_DSS_COLOR_CLUT4 ||
1799 color_mode == OMAP_DSS_COLOR_CLUT8) {
1800 *x_predecim = 1;
1801 *y_predecim = 1;
1802 *five_taps = false;
1803 return 0;
1804 }
1805
1806 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
1807 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
1808
1809 min_factor = min(decim_x, decim_y);
1810
1811 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 1812 return -EINVAL;
1813
aed74b55 1814 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 1815 return -EINVAL;
1816
7282f1b7 1817 if (cpu_is_omap24xx()) {
7282f1b7 1818 *five_taps = false;
aed74b55
CM		 1819
1820 do {
1821 in_height = DIV_ROUND_UP(height, decim_y);
1822 in_width = DIV_ROUND_UP(width, decim_x);
8b53d991 1823 core_clk = calc_core_clk(channel, in_width, in_height,
aed74b55 1824 out_width, out_height);
8b53d991
CM		 1825 error = (in_width > maxsinglelinewidth || !core_clk ||
1826 core_clk > dispc_core_clk_rate());
aed74b55
CM		 1827 if (error) {
1828 if (decim_x == decim_y) {
1829 decim_x = min_factor;
1830 decim_y++;
1831 } else {
1832 swap(decim_x, decim_y);
1833 if (decim_x < decim_y)
1834 decim_x++;
1835 }
1836 }
1837 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
1838 error);
1839
1840 if (in_width > maxsinglelinewidth) {
1841 DSSERR("Cannot scale max input width exceeded");
1842 return -EINVAL;
1843 }
7282f1b7 1844 } else if (cpu_is_omap34xx()) {
aed74b55
CM		 1845
1846 do {
1847 in_height = DIV_ROUND_UP(height, decim_y);
1848 in_width = DIV_ROUND_UP(width, decim_x);
81ab95b7
AT		 1849 core_clk = calc_core_clk_five_taps(channel, mgr_timings,
1850 in_width, in_height, out_width, out_height,
1851 color_mode);
aed74b55 1852
81ab95b7
AT		 1853 error = check_horiz_timing_omap3(channel, mgr_timings,
1854 pos_x, in_width, in_height, out_width,
1855 out_height);
7faa9233 1856
aed74b55
CM		 1857 if (in_width > maxsinglelinewidth)
1858 if (in_height > out_height &&
1859 in_height < out_height * 2)
1860 *five_taps = false;
1861 if (!*five_taps)
8b53d991
CM		 1862 core_clk = calc_core_clk(channel, in_width,
1863 in_height, out_width, out_height);
7faa9233 1864 error = (error || in_width > maxsinglelinewidth * 2 ||
aed74b55 1865 (in_width > maxsinglelinewidth && *five_taps) ||
8b53d991 1866 !core_clk || core_clk > dispc_core_clk_rate());
aed74b55
CM		 1867 if (error) {
1868 if (decim_x == decim_y) {
1869 decim_x = min_factor;
1870 decim_y++;
1871 } else {
1872 swap(decim_x, decim_y);
1873 if (decim_x < decim_y)
1874 decim_x++;
1875 }
1876 }
1877 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
1878 && error);
1879
81ab95b7
AT		 1880 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
1881 height, out_width, out_height)){
7faa9233
CM		 1882 DSSERR("horizontal timing too tight\n");
1883 return -EINVAL;
1884 }
1885
aed74b55 1886 if (in_width > (maxsinglelinewidth * 2)) {
7282f1b7
CM		 1887 DSSERR("Cannot setup scaling");
1888 DSSERR("width exceeds maximum width possible");
1889 return -EINVAL;
1890 }
aed74b55
CM		 1891
1892 if (in_width > maxsinglelinewidth && *five_taps) {
1893 DSSERR("cannot setup scaling with five taps");
1894 return -EINVAL;
7282f1b7 1895 }
7282f1b7 1896 } else {
aed74b55
CM		 1897 int decim_x_min = decim_x;
1898 in_height = DIV_ROUND_UP(height, decim_y);
8b53d991 1899 in_width_max = dispc_core_clk_rate() /
aed74b55
CM		 1900 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
1901 out_width);
1902 decim_x = DIV_ROUND_UP(width, in_width_max);
1903
1904 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
1905 if (decim_x > *x_predecim)
1906 return -EINVAL;
1907
1908 do {
1909 in_width = DIV_ROUND_UP(width, decim_x);
1910 } while (decim_x <= *x_predecim &&
1911 in_width > maxsinglelinewidth && decim_x++);
1912
1913 if (in_width > maxsinglelinewidth) {
7282f1b7
CM		 1914 DSSERR("Cannot scale width exceeds max line width");
1915 return -EINVAL;
1916 }
aed74b55 1917
8b53d991
CM		 1918 core_clk = calc_core_clk(channel, in_width, in_height,
1919 out_width, out_height);
79ad75f2
AT		 1920 }
1921
8b53d991
CM		 1922 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
1923 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 1924
8b53d991 1925 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 1926 DSSERR("failed to set up scaling, "
8b53d991
CM		 1927 "required core clk rate = %lu Hz, "
1928 "current core clk rate = %lu Hz\n",
1929 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 1930 return -EINVAL;
1931 }
1932
aed74b55
CM		 1933 *x_predecim = decim_x;
1934 *y_predecim = decim_y;
79ad75f2
AT		 1935 return 0;
1936}
1937
a4273b7c 1938int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
81ab95b7
AT		 1939 bool ilace, bool replication,
1940 const struct omap_video_timings *mgr_timings)
80c39712 1941{
79ad75f2 1942 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 1943 bool five_taps = true;
80c39712 1944 bool fieldmode = 0;
79ad75f2 1945 int r, cconv = 0;
80c39712
TV		 1946 unsigned offset0, offset1;
1947 s32 row_inc;
1948 s32 pix_inc;
a4273b7c 1949 u16 frame_height = oi->height;
80c39712 1950 unsigned int field_offset = 0;
aed74b55
CM		 1951 u16 in_height = oi->height;
1952 u16 in_width = oi->width;
1953 u16 out_width, out_height;
2cc5d1af 1954 enum omap_channel channel;
aed74b55 1955 int x_predecim = 1, y_predecim = 1;
2cc5d1af
TV		 1956
1957 channel = dispc_ovl_get_channel_out(plane);
80c39712 1958
a4273b7c 1959 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 1960 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
1961 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 1962 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1963 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 1964 oi->mirror, ilace, channel, replication);
e6d80f95 1965
a4273b7c 1966 if (oi->paddr == 0)
80c39712
TV		 1967 return -EINVAL;
1968
aed74b55
CM		 1969 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
1970 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 1971
aed74b55 1972 if (ilace && oi->height == out_height)
80c39712
TV		 1973 fieldmode = 1;
1974
1975 if (ilace) {
1976 if (fieldmode)
aed74b55 1977 in_height /= 2;
a4273b7c 1978 oi->pos_y /= 2;
aed74b55 1979 out_height /= 2;
80c39712
TV		 1980
1981 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1982 "out_height %d\n",
aed74b55 1983 in_height, oi->pos_y, out_height);
80c39712
TV		 1984 }
1985
a4273b7c 1986 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 1987 return -EINVAL;
1988
81ab95b7
AT		 1989 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
1990 in_height, out_width, out_height, oi->color_mode,
1991 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 1992 if (r)
1993 return r;
80c39712 1994
aed74b55
CM		 1995 in_width = DIV_ROUND_UP(in_width, x_predecim);
1996 in_height = DIV_ROUND_UP(in_height, y_predecim);
1997
79ad75f2
AT		 1998 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1999 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2000 oi->color_mode == OMAP_DSS_COLOR_NV12)
2001 cconv = 1;
80c39712
TV		 2002
2003 if (ilace && !fieldmode) {
2004 /*
2005 * when downscaling the bottom field may have to start several
2006 * source lines below the top field. Unfortunately ACCUI
2007 * registers will only hold the fractional part of the offset
2008 * so the integer part must be added to the base address of the
2009 * bottom field.
2010 */
aed74b55 2011 if (!in_height || in_height == out_height)
80c39712
TV		 2012 field_offset = 0;
2013 else
aed74b55 2014 field_offset = in_height / out_height / 2;
80c39712
TV		 2015 }
2016
2017 /* Fields are independent but interleaved in memory. */
2018 if (fieldmode)
2019 field_offset = 1;
2020
a4273b7c
AT		 2021 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
2022 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2023 oi->screen_width, in_width, frame_height,
a4273b7c 2024 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2025 &offset0, &offset1, &row_inc, &pix_inc,
2026 x_predecim, y_predecim);
80c39712 2027 else
a4273b7c 2028 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2029 oi->screen_width, in_width, frame_height,
a4273b7c 2030 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2031 &offset0, &offset1, &row_inc, &pix_inc,
2032 x_predecim, y_predecim);
80c39712
TV		 2033
2034 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2035 offset0, offset1, row_inc, pix_inc);
2036
a4273b7c 2037 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2038
a4273b7c
AT		 2039 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2040 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2041
a4273b7c
AT		 2042 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2043 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2044 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2045 }
2046
2047
f0e5caab
TV		 2048 dispc_ovl_set_row_inc(plane, row_inc);
2049 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2050
aed74b55
CM		 2051 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2052 in_height, out_width, out_height);
80c39712 2053
a4273b7c 2054 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2055
aed74b55 2056 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2057
79ad75f2 2058 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2059 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2060 out_height, ilace, five_taps, fieldmode,
a4273b7c 2061 oi->color_mode, oi->rotation);
aed74b55 2062 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2063 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2064 }
2065
a4273b7c
AT		 2066 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2067 oi->color_mode);
80c39712 2068
54128701 2069 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2070 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2071 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2072
c3d92529 2073 dispc_ovl_enable_replication(plane, replication);
c3d92529 2074
80c39712
TV		 2075 return 0;
2076}
2077
f0e5caab 2078int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2079{
e6d80f95
TV		 2080 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2081
9b372c2d 2082 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2083
2084 return 0;
80c39712
TV		 2085}
2086
2087static void dispc_disable_isr(void *data, u32 mask)
2088{
2089 struct completion *compl = data;
2090 complete(compl);
2091}
2092
2a205f34 2093static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2094{
b6a44e77 2095 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 2096 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2097 /* flush posted write */
2098 dispc_read_reg(DISPC_CONTROL2);
2099 } else {
2a205f34 2100 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2101 dispc_read_reg(DISPC_CONTROL);
2102 }
80c39712
TV		 2103}
2104
26d9dd0d 2105static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2106{
2107 struct completion frame_done_completion;
2108 bool is_on;
2109 int r;
2a205f34 2110 u32 irq;
80c39712 2111
80c39712
TV		 2112 /* When we disable LCD output, we need to wait until frame is done.
2113 * Otherwise the DSS is still working, and turning off the clocks
2114 * prevents DSS from going to OFF mode */
2a205f34
SS		 2115 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2116 REG_GET(DISPC_CONTROL2, 0, 0) :
2117 REG_GET(DISPC_CONTROL, 0, 0);
2118
2119 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2120 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2121
2122 if (!enable && is_on) {
2123 init_completion(&frame_done_completion);
2124
2125 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2126 &frame_done_completion, irq);
80c39712
TV		 2127
2128 if (r)
2129 DSSERR("failed to register FRAMEDONE isr\n");
2130 }
2131
2a205f34 2132 _enable_lcd_out(channel, enable);
80c39712
TV		 2133
2134 if (!enable && is_on) {
2135 if (!wait_for_completion_timeout(&frame_done_completion,
2136 msecs_to_jiffies(100)))
2137 DSSERR("timeout waiting for FRAME DONE\n");
2138
2139 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2140 &frame_done_completion, irq);
80c39712
TV		 2141
2142 if (r)
2143 DSSERR("failed to unregister FRAMEDONE isr\n");
2144 }
80c39712
TV		 2145}
2146
2147static void _enable_digit_out(bool enable)
2148{
2149 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2150 /* flush posted write */
2151 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2152}
2153
26d9dd0d 2154static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2155{
2156 struct completion frame_done_completion;
e82b090b
TV		 2157 enum dss_hdmi_venc_clk_source_select src;
2158 int r, i;
2159 u32 irq_mask;
2160 int num_irqs;
80c39712 2161
e6d80f95 2162 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2163 return;
80c39712 2164
e82b090b
TV		 2165 src = dss_get_hdmi_venc_clk_source();
2166
80c39712
TV		 2167 if (enable) {
2168 unsigned long flags;
2169 /* When we enable digit output, we'll get an extra digit
2170 * sync lost interrupt, that we need to ignore */
2171 spin_lock_irqsave(&dispc.irq_lock, flags);
2172 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2173 _omap_dispc_set_irqs();
2174 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2175 }
2176
2177 /* When we disable digit output, we need to wait until fields are done.
2178 * Otherwise the DSS is still working, and turning off the clocks
2179 * prevents DSS from going to OFF mode. And when enabling, we need to
2180 * wait for the extra sync losts */
2181 init_completion(&frame_done_completion);
2182
e82b090b
TV		 2183 if (src == DSS_HDMI_M_PCLK && enable == false) {
2184 irq_mask = DISPC_IRQ_FRAMEDONETV;
2185 num_irqs = 1;
2186 } else {
2187 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2188 /* XXX I understand from TRM that we should only wait for the
2189 * current field to complete. But it seems we have to wait for
2190 * both fields */
2191 num_irqs = 2;
2192 }
2193
80c39712 2194 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2195 irq_mask);
80c39712 2196 if (r)
e82b090b 2197 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2198
2199 _enable_digit_out(enable);
2200
e82b090b
TV		 2201 for (i = 0; i < num_irqs; ++i) {
2202 if (!wait_for_completion_timeout(&frame_done_completion,
2203 msecs_to_jiffies(100)))
2204 DSSERR("timeout waiting for digit out to %s\n",
2205 enable ? "start" : "stop");
2206 }
80c39712 2207
e82b090b
TV		 2208 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2209 irq_mask);
80c39712 2210 if (r)
e82b090b 2211 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2212
2213 if (enable) {
2214 unsigned long flags;
2215 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2216 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2217 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2218 _omap_dispc_set_irqs();
2219 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2220 }
80c39712
TV		 2221}
2222
26d9dd0d 2223bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2224{
2225 if (channel == OMAP_DSS_CHANNEL_LCD)
2226 return !!REG_GET(DISPC_CONTROL, 0, 0);
2227 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2228 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2229 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2230 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2231 else
2232 BUG();
2233}
2234
26d9dd0d 2235void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2236{
dac57a05 2237 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2238 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2239 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2240 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2241 else
2242 BUG();
2243}
2244
80c39712
TV		 2245void dispc_lcd_enable_signal_polarity(bool act_high)
2246{
6ced40bf
AT		 2247 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2248 return;
2249
80c39712 2250 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2251}
2252
2253void dispc_lcd_enable_signal(bool enable)
2254{
6ced40bf
AT		 2255 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2256 return;
2257
80c39712 2258 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2259}
2260
2261void dispc_pck_free_enable(bool enable)
2262{
6ced40bf
AT		 2263 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2264 return;
2265
80c39712 2266 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2267}
2268
26d9dd0d 2269void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2270{
2a205f34
SS		 2271 if (channel == OMAP_DSS_CHANNEL_LCD2)
2272 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2273 else
2274 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2275}
2276
2277
26d9dd0d 2278void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2279 enum omap_lcd_display_type type)
80c39712
TV		 2280{
2281 int mode;
2282
2283 switch (type) {
2284 case OMAP_DSS_LCD_DISPLAY_STN:
2285 mode = 0;
2286 break;
2287
2288 case OMAP_DSS_LCD_DISPLAY_TFT:
2289 mode = 1;
2290 break;
2291
2292 default:
2293 BUG();
2294 return;
2295 }
2296
2a205f34
SS		 2297 if (channel == OMAP_DSS_CHANNEL_LCD2)
2298 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2299 else
2300 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2301}
2302
2303void dispc_set_loadmode(enum omap_dss_load_mode mode)
2304{
80c39712 2305 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2306}
2307
2308
c64dca40 2309static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2310{
8613b000 2311 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2312}
2313
c64dca40 2314static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2315 enum omap_dss_trans_key_type type,
2316 u32 trans_key)
2317{
80c39712
TV		 2318 if (ch == OMAP_DSS_CHANNEL_LCD)
2319 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2320 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2321 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2322 else /* OMAP_DSS_CHANNEL_LCD2 */
2323 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2324
8613b000 2325 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2326}
2327
c64dca40 2328static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2329{
80c39712
TV		 2330 if (ch == OMAP_DSS_CHANNEL_LCD)
2331 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2332 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2333 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2334 else /* OMAP_DSS_CHANNEL_LCD2 */
2335 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2336}
11354dd5 2337
c64dca40
TV		 2338static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2339 bool enable)
80c39712 2340{
11354dd5 2341 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2342 return;
2343
80c39712
TV		 2344 if (ch == OMAP_DSS_CHANNEL_LCD)
2345 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2346 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2347 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2348}
11354dd5 2349
c64dca40
TV		 2350void dispc_mgr_setup(enum omap_channel channel,
2351 struct omap_overlay_manager_info *info)
2352{
2353 dispc_mgr_set_default_color(channel, info->default_color);
2354 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2355 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2356 dispc_mgr_enable_alpha_fixed_zorder(channel,
2357 info->partial_alpha_enabled);
2358 if (dss_has_feature(FEAT_CPR)) {
2359 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2360 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2361 }
2362}
80c39712 2363
26d9dd0d 2364void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2365{
2366 int code;
2367
2368 switch (data_lines) {
2369 case 12:
2370 code = 0;
2371 break;
2372 case 16:
2373 code = 1;
2374 break;
2375 case 18:
2376 code = 2;
2377 break;
2378 case 24:
2379 code = 3;
2380 break;
2381 default:
2382 BUG();
2383 return;
2384 }
2385
2a205f34
SS		 2386 if (channel == OMAP_DSS_CHANNEL_LCD2)
2387 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2388 else
2389 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2390}
2391
569969d6 2392void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2393{
2394 u32 l;
569969d6 2395 int gpout0, gpout1;
80c39712
TV		 2396
2397 switch (mode) {
569969d6
AT		 2398 case DSS_IO_PAD_MODE_RESET:
2399 gpout0 = 0;
2400 gpout1 = 0;
80c39712 2401 break;
569969d6
AT		 2402 case DSS_IO_PAD_MODE_RFBI:
2403 gpout0 = 1;
80c39712
TV		 2404 gpout1 = 0;
2405 break;
569969d6
AT		 2406 case DSS_IO_PAD_MODE_BYPASS:
2407 gpout0 = 1;
80c39712
TV		 2408 gpout1 = 1;
2409 break;
80c39712
TV		 2410 default:
2411 BUG();
2412 return;
2413 }
2414
569969d6
AT		 2415 l = dispc_read_reg(DISPC_CONTROL);
2416 l = FLD_MOD(l, gpout0, 15, 15);
2417 l = FLD_MOD(l, gpout1, 16, 16);
2418 dispc_write_reg(DISPC_CONTROL, l);
2419}
2420
2421void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2422{
2423 if (channel == OMAP_DSS_CHANNEL_LCD2)
2424 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2425 else
2426 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2427}
2428
8f366162
AT		 2429static bool _dispc_mgr_size_ok(u16 width, u16 height)
2430{
2431 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2432 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2433}
2434
80c39712
TV		 2435static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2436 int vsw, int vfp, int vbp)
2437{
2438 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2439 if (hsw < 1 || hsw > 64 ||
2440 hfp < 1 || hfp > 256 ||
2441 hbp < 1 || hbp > 256 ||
2442 vsw < 1 || vsw > 64 ||
2443 vfp < 0 || vfp > 255 ||
2444 vbp < 0 || vbp > 255)
2445 return false;
2446 } else {
2447 if (hsw < 1 || hsw > 256 ||
2448 hfp < 1 || hfp > 4096 ||
2449 hbp < 1 || hbp > 4096 ||
2450 vsw < 1 || vsw > 256 ||
2451 vfp < 0 || vfp > 4095 ||
2452 vbp < 0 || vbp > 4095)
2453 return false;
2454 }
2455
2456 return true;
2457}
2458
8f366162 2459bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2460 const struct omap_video_timings *timings)
80c39712 2461{
8f366162
AT		 2462 bool timings_ok;
2463
2464 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2465
2466 if (dispc_mgr_is_lcd(channel))
2467 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2468 timings->hfp, timings->hbp,
2469 timings->vsw, timings->vfp,
2470 timings->vbp);
2471
2472 return timings_ok;
80c39712
TV		 2473}
2474
26d9dd0d 2475static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2476 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2477{
2478 u32 timing_h, timing_v;
2479
2480 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2481 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2482 FLD_VAL(hbp-1, 27, 20);
2483
2484 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2485 FLD_VAL(vbp, 27, 20);
2486 } else {
2487 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2488 FLD_VAL(hbp-1, 31, 20);
2489
2490 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2491 FLD_VAL(vbp, 31, 20);
2492 }
2493
64ba4f74
SS		 2494 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2495 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2496}
2497
2498/* change name to mode? */
c51d921a 2499void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2500 struct omap_video_timings *timings)
80c39712
TV		 2501{
2502 unsigned xtot, ytot;
2503 unsigned long ht, vt;
2504
c51d921a
AT		 2505 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2506 timings->y_res);
80c39712 2507
8f366162
AT		 2508 if (!dispc_mgr_timings_ok(channel, timings))
2509 BUG();
80c39712 2510
8f366162 2511 if (dispc_mgr_is_lcd(channel)) {
c51d921a
AT		 2512 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2513 timings->hbp, timings->vsw, timings->vfp,
2514 timings->vbp);
80c39712 2515
c51d921a
AT		 2516 xtot = timings->x_res + timings->hfp + timings->hsw +
2517 timings->hbp;
2518 ytot = timings->y_res + timings->vfp + timings->vsw +
2519 timings->vbp;
80c39712 2520
c51d921a
AT		 2521 ht = (timings->pixel_clock * 1000) / xtot;
2522 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2523
2524 DSSDBG("pck %u\n", timings->pixel_clock);
2525 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
80c39712
TV		 2526 timings->hsw, timings->hfp, timings->hbp,
2527 timings->vsw, timings->vfp, timings->vbp);
2528
c51d921a 2529 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
c51d921a 2530 }
8f366162
AT		 2531
2532 dispc_mgr_set_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2533}
2534
26d9dd0d 2535static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2536 u16 pck_div)
80c39712
TV		 2537{
2538 BUG_ON(lck_div < 1);
9eaaf207 2539 BUG_ON(pck_div < 1);
80c39712 2540
ce7fa5eb 2541 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2542 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2543}
2544
26d9dd0d 2545static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2546 int *pck_div)
80c39712
TV		 2547{
2548 u32 l;
ce7fa5eb 2549 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2550 *lck_div = FLD_GET(l, 23, 16);
2551 *pck_div = FLD_GET(l, 7, 0);
2552}
2553
2554unsigned long dispc_fclk_rate(void)
2555{
a72b64b9 2556 struct platform_device *dsidev;
80c39712
TV		 2557 unsigned long r = 0;
2558
66534e8e 2559 switch (dss_get_dispc_clk_source()) {
89a35e51 2560 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2561 r = clk_get_rate(dispc.dss_clk);
66534e8e 2562 break;
89a35e51 2563 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2564 dsidev = dsi_get_dsidev_from_id(0);
2565 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2566 break;
5a8b572d
AT		 2567 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2568 dsidev = dsi_get_dsidev_from_id(1);
2569 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2570 break;
66534e8e
TA		 2571 default:
2572 BUG();
2573 }
2574
80c39712
TV		 2575 return r;
2576}
2577
26d9dd0d 2578unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2579{
a72b64b9 2580 struct platform_device *dsidev;
80c39712
TV		 2581 int lcd;
2582 unsigned long r;
2583 u32 l;
2584
ce7fa5eb 2585 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2586
2587 lcd = FLD_GET(l, 23, 16);
2588
ea75159e 2589 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2590 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2591 r = clk_get_rate(dispc.dss_clk);
ea75159e 2592 break;
89a35e51 2593 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2594 dsidev = dsi_get_dsidev_from_id(0);
2595 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2596 break;
5a8b572d
AT		 2597 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2598 dsidev = dsi_get_dsidev_from_id(1);
2599 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2600 break;
ea75159e
TA		 2601 default:
2602 BUG();
2603 }
80c39712
TV		 2604
2605 return r / lcd;
2606}
2607
26d9dd0d 2608unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2609{
80c39712 2610 unsigned long r;
80c39712 2611
c3dc6a7a
AT		 2612 if (dispc_mgr_is_lcd(channel)) {
2613 int pcd;
2614 u32 l;
80c39712 2615
c3dc6a7a 2616 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2617
c3dc6a7a 2618 pcd = FLD_GET(l, 7, 0);
80c39712 2619
c3dc6a7a
AT		 2620 r = dispc_mgr_lclk_rate(channel);
2621
2622 return r / pcd;
2623 } else {
3fa03ba8 2624 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2625
3fa03ba8
AT		 2626 source = dss_get_hdmi_venc_clk_source();
2627
2628 switch (source) {
2629 case DSS_VENC_TV_CLK:
c3dc6a7a 2630 return venc_get_pixel_clock();
3fa03ba8 2631 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2632 return hdmi_get_pixel_clock();
2633 default:
2634 BUG();
2635 }
2636 }
80c39712
TV		 2637}
2638
8b53d991
CM		 2639unsigned long dispc_core_clk_rate(void)
2640{
2641 int lcd;
2642 unsigned long fclk = dispc_fclk_rate();
2643
2644 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2645 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2646 else
2647 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2648
2649 return fclk / lcd;
2650}
2651
80c39712
TV		 2652void dispc_dump_clocks(struct seq_file *s)
2653{
2654 int lcd, pcd;
0cf35df3 2655 u32 l;
89a35e51
AT		 2656 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2657 enum omap_dss_clk_source lcd_clk_src;
80c39712 2658
4fbafaf3
TV		 2659 if (dispc_runtime_get())
2660 return;
80c39712 2661
80c39712
TV		 2662 seq_printf(s, "- DISPC -\n");
2663
067a57e4
AT		 2664 seq_printf(s, "dispc fclk source = %s (%s)\n",
2665 dss_get_generic_clk_source_name(dispc_clk_src),
2666 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2667
2668 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2669
0cf35df3
MR		 2670 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2671 seq_printf(s, "- DISPC-CORE-CLK -\n");
2672 l = dispc_read_reg(DISPC_DIVISOR);
2673 lcd = FLD_GET(l, 23, 16);
2674
2675 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2676 (dispc_fclk_rate()/lcd), lcd);
2677 }
2a205f34
SS		 2678 seq_printf(s, "- LCD1 -\n");
2679
ea75159e
TA		 2680 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2681
2682 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2683 dss_get_generic_clk_source_name(lcd_clk_src),
2684 dss_feat_get_clk_source_name(lcd_clk_src));
2685
26d9dd0d 2686 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2687
ff1b2cde 2688 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2689 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2690 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2691 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2692 if (dss_has_feature(FEAT_MGR_LCD2)) {
2693 seq_printf(s, "- LCD2 -\n");
2694
ea75159e
TA		 2695 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2696
2697 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2698 dss_get_generic_clk_source_name(lcd_clk_src),
2699 dss_feat_get_clk_source_name(lcd_clk_src));
2700
26d9dd0d 2701 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2702
2a205f34 2703 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2704 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2705 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2706 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2707 }
4fbafaf3
TV		 2708
2709 dispc_runtime_put();
80c39712
TV		 2710}
2711
dfc0fd8d
TV		 2712#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2713void dispc_dump_irqs(struct seq_file *s)
2714{
2715 unsigned long flags;
2716 struct dispc_irq_stats stats;
2717
2718 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2719
2720 stats = dispc.irq_stats;
2721 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2722 dispc.irq_stats.last_reset = jiffies;
2723
2724 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2725
2726 seq_printf(s, "period %u ms\n",
2727 jiffies_to_msecs(jiffies - stats.last_reset));
2728
2729 seq_printf(s, "irqs %d\n", stats.irq_count);
2730#define PIS(x) \
2731 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2732
2733 PIS(FRAMEDONE);
2734 PIS(VSYNC);
2735 PIS(EVSYNC_EVEN);
2736 PIS(EVSYNC_ODD);
2737 PIS(ACBIAS_COUNT_STAT);
2738 PIS(PROG_LINE_NUM);
2739 PIS(GFX_FIFO_UNDERFLOW);
2740 PIS(GFX_END_WIN);
2741 PIS(PAL_GAMMA_MASK);
2742 PIS(OCP_ERR);
2743 PIS(VID1_FIFO_UNDERFLOW);
2744 PIS(VID1_END_WIN);
2745 PIS(VID2_FIFO_UNDERFLOW);
2746 PIS(VID2_END_WIN);
b8c095b4
AT		 2747 if (dss_feat_get_num_ovls() > 3) {
2748 PIS(VID3_FIFO_UNDERFLOW);
2749 PIS(VID3_END_WIN);
2750 }
dfc0fd8d
TV		 2751 PIS(SYNC_LOST);
2752 PIS(SYNC_LOST_DIGIT);
2753 PIS(WAKEUP);
2a205f34
SS		 2754 if (dss_has_feature(FEAT_MGR_LCD2)) {
2755 PIS(FRAMEDONE2);
2756 PIS(VSYNC2);
2757 PIS(ACBIAS_COUNT_STAT2);
2758 PIS(SYNC_LOST2);
2759 }
dfc0fd8d
TV		 2760#undef PIS
2761}
dfc0fd8d
TV		 2762#endif
2763
e40402cf 2764static void dispc_dump_regs(struct seq_file *s)
80c39712 2765{
4dd2da15
AT		 2766 int i, j;
2767 const char *mgr_names[] = {
2768 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2769 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2770 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2771 };
2772 const char *ovl_names[] = {
2773 [OMAP_DSS_GFX] = "GFX",
2774 [OMAP_DSS_VIDEO1] = "VID1",
2775 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2776 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2777 };
2778 const char **p_names;
2779
9b372c2d 2780#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2781
4fbafaf3
TV		 2782 if (dispc_runtime_get())
2783 return;
80c39712 2784
5010be80 2785 /* DISPC common registers */
80c39712
TV		 2786 DUMPREG(DISPC_REVISION);
2787 DUMPREG(DISPC_SYSCONFIG);
2788 DUMPREG(DISPC_SYSSTATUS);
2789 DUMPREG(DISPC_IRQSTATUS);
2790 DUMPREG(DISPC_IRQENABLE);
2791 DUMPREG(DISPC_CONTROL);
2792 DUMPREG(DISPC_CONFIG);
2793 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2794 DUMPREG(DISPC_LINE_STATUS);
2795 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2796 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2797 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2798 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2799 if (dss_has_feature(FEAT_MGR_LCD2)) {
2800 DUMPREG(DISPC_CONTROL2);
2801 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2802 }
2803
2804#undef DUMPREG
2805
2806#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2807#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2808 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2809 dispc_read_reg(DISPC_REG(i, r)))
2810
4dd2da15 2811 p_names = mgr_names;
5010be80 2812
4dd2da15
AT		 2813 /* DISPC channel specific registers */
2814 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2815 DUMPREG(i, DISPC_DEFAULT_COLOR);
2816 DUMPREG(i, DISPC_TRANS_COLOR);
2817 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2818
4dd2da15
AT		 2819 if (i == OMAP_DSS_CHANNEL_DIGIT)
2820 continue;
5010be80 2821
4dd2da15
AT		 2822 DUMPREG(i, DISPC_DEFAULT_COLOR);
2823 DUMPREG(i, DISPC_TRANS_COLOR);
2824 DUMPREG(i, DISPC_TIMING_H);
2825 DUMPREG(i, DISPC_TIMING_V);
2826 DUMPREG(i, DISPC_POL_FREQ);
2827 DUMPREG(i, DISPC_DIVISORo);
2828 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2829
4dd2da15
AT		 2830 DUMPREG(i, DISPC_DATA_CYCLE1);
2831 DUMPREG(i, DISPC_DATA_CYCLE2);
2832 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2833
332e9d70 2834 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2835 DUMPREG(i, DISPC_CPR_COEF_R);
2836 DUMPREG(i, DISPC_CPR_COEF_G);
2837 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2838 }
2a205f34 2839 }
80c39712 2840
4dd2da15
AT		 2841 p_names = ovl_names;
2842
2843 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2844 DUMPREG(i, DISPC_OVL_BA0);
2845 DUMPREG(i, DISPC_OVL_BA1);
2846 DUMPREG(i, DISPC_OVL_POSITION);
2847 DUMPREG(i, DISPC_OVL_SIZE);
2848 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2849 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2850 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2851 DUMPREG(i, DISPC_OVL_ROW_INC);
2852 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2853 if (dss_has_feature(FEAT_PRELOAD))
2854 DUMPREG(i, DISPC_OVL_PRELOAD);
2855
2856 if (i == OMAP_DSS_GFX) {
2857 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2858 DUMPREG(i, DISPC_OVL_TABLE_BA);
2859 continue;
2860 }
2861
2862 DUMPREG(i, DISPC_OVL_FIR);
2863 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2864 DUMPREG(i, DISPC_OVL_ACCU0);
2865 DUMPREG(i, DISPC_OVL_ACCU1);
2866 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2867 DUMPREG(i, DISPC_OVL_BA0_UV);
2868 DUMPREG(i, DISPC_OVL_BA1_UV);
2869 DUMPREG(i, DISPC_OVL_FIR2);
2870 DUMPREG(i, DISPC_OVL_ACCU2_0);
2871 DUMPREG(i, DISPC_OVL_ACCU2_1);
2872 }
2873 if (dss_has_feature(FEAT_ATTR2))
2874 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2875 if (dss_has_feature(FEAT_PRELOAD))
2876 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2877 }
5010be80
AT		 2878
2879#undef DISPC_REG
2880#undef DUMPREG
2881
2882#define DISPC_REG(plane, name, i) name(plane, i)
2883#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2884 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2885 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2886 dispc_read_reg(DISPC_REG(plane, name, i)))
2887
4dd2da15 2888 /* Video pipeline coefficient registers */
332e9d70 2889
4dd2da15
AT		 2890 /* start from OMAP_DSS_VIDEO1 */
2891 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2892 for (j = 0; j < 8; j++)
2893 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2894
4dd2da15
AT		 2895 for (j = 0; j < 8; j++)
2896 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2897
4dd2da15
AT		 2898 for (j = 0; j < 5; j++)
2899 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2900
4dd2da15
AT		 2901 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2902 for (j = 0; j < 8; j++)
2903 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2904 }
2905
2906 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2907 for (j = 0; j < 8; j++)
2908 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2909
2910 for (j = 0; j < 8; j++)
2911 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2912
2913 for (j = 0; j < 8; j++)
2914 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2915 }
332e9d70 2916 }
80c39712 2917
4fbafaf3 2918 dispc_runtime_put();
5010be80
AT		 2919
2920#undef DISPC_REG
80c39712
TV		 2921#undef DUMPREG
2922}
2923
26d9dd0d
TV		 2924static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2925 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2926 u8 acb)
80c39712
TV		 2927{
2928 u32 l = 0;
2929
2930 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2931 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2932
2933 l |= FLD_VAL(onoff, 17, 17);
2934 l |= FLD_VAL(rf, 16, 16);
2935 l |= FLD_VAL(ieo, 15, 15);
2936 l |= FLD_VAL(ipc, 14, 14);
2937 l |= FLD_VAL(ihs, 13, 13);
2938 l |= FLD_VAL(ivs, 12, 12);
2939 l |= FLD_VAL(acbi, 11, 8);
2940 l |= FLD_VAL(acb, 7, 0);
2941
ff1b2cde 2942 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2943}
2944
26d9dd0d 2945void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 2946 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2947{
26d9dd0d 2948 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2949 (config & OMAP_DSS_LCD_RF) != 0,
2950 (config & OMAP_DSS_LCD_IEO) != 0,
2951 (config & OMAP_DSS_LCD_IPC) != 0,
2952 (config & OMAP_DSS_LCD_IHS) != 0,
2953 (config & OMAP_DSS_LCD_IVS) != 0,
2954 acbi, acb);
2955}
2956
2957/* with fck as input clock rate, find dispc dividers that produce req_pck */
2958void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2959 struct dispc_clock_info *cinfo)
2960{
9eaaf207 2961 u16 pcd_min, pcd_max;
80c39712
TV		 2962 unsigned long best_pck;
2963 u16 best_ld, cur_ld;
2964 u16 best_pd, cur_pd;
2965
9eaaf207
TV		 2966 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2967 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2968
2969 if (!is_tft)
2970 pcd_min = 3;
2971
80c39712
TV		 2972 best_pck = 0;
2973 best_ld = 0;
2974 best_pd = 0;
2975
2976 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2977 unsigned long lck = fck / cur_ld;
2978
9eaaf207 2979 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 2980 unsigned long pck = lck / cur_pd;
2981 long old_delta = abs(best_pck - req_pck);
2982 long new_delta = abs(pck - req_pck);
2983
2984 if (best_pck == 0 || new_delta < old_delta) {
2985 best_pck = pck;
2986 best_ld = cur_ld;
2987 best_pd = cur_pd;
2988
2989 if (pck == req_pck)
2990 goto found;
2991 }
2992
2993 if (pck < req_pck)
2994 break;
2995 }
2996
2997 if (lck / pcd_min < req_pck)
2998 break;
2999 }
3000
3001found:
3002 cinfo->lck_div = best_ld;
3003 cinfo->pck_div = best_pd;
3004 cinfo->lck = fck / cinfo->lck_div;
3005 cinfo->pck = cinfo->lck / cinfo->pck_div;
3006}
3007
3008/* calculate clock rates using dividers in cinfo */
3009int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3010 struct dispc_clock_info *cinfo)
3011{
3012 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3013 return -EINVAL;
9eaaf207 3014 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3015 return -EINVAL;
3016
3017 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3018 cinfo->pck = cinfo->lck / cinfo->pck_div;
3019
3020 return 0;
3021}
3022
26d9dd0d 3023int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3024 struct dispc_clock_info *cinfo)
80c39712
TV		 3025{
3026 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3027 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3028
26d9dd0d 3029 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3030
3031 return 0;
3032}
3033
26d9dd0d 3034int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3035 struct dispc_clock_info *cinfo)
80c39712
TV		 3036{
3037 unsigned long fck;
3038
3039 fck = dispc_fclk_rate();
3040
ce7fa5eb
MR		 3041 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3042 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3043
3044 cinfo->lck = fck / cinfo->lck_div;
3045 cinfo->pck = cinfo->lck / cinfo->pck_div;
3046
3047 return 0;
3048}
3049
3050/* dispc.irq_lock has to be locked by the caller */
3051static void _omap_dispc_set_irqs(void)
3052{
3053 u32 mask;
3054 u32 old_mask;
3055 int i;
3056 struct omap_dispc_isr_data *isr_data;
3057
3058 mask = dispc.irq_error_mask;
3059
3060 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3061 isr_data = &dispc.registered_isr[i];
3062
3063 if (isr_data->isr == NULL)
3064 continue;
3065
3066 mask |= isr_data->mask;
3067 }
3068
80c39712
TV		 3069 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3070 /* clear the irqstatus for newly enabled irqs */
3071 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3072
3073 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3074}
3075
3076int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3077{
3078 int i;
3079 int ret;
3080 unsigned long flags;
3081 struct omap_dispc_isr_data *isr_data;
3082
3083 if (isr == NULL)
3084 return -EINVAL;
3085
3086 spin_lock_irqsave(&dispc.irq_lock, flags);
3087
3088 /* check for duplicate entry */
3089 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3090 isr_data = &dispc.registered_isr[i];
3091 if (isr_data->isr == isr && isr_data->arg == arg &&
3092 isr_data->mask == mask) {
3093 ret = -EINVAL;
3094 goto err;
3095 }
3096 }
3097
3098 isr_data = NULL;
3099 ret = -EBUSY;
3100
3101 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3102 isr_data = &dispc.registered_isr[i];
3103
3104 if (isr_data->isr != NULL)
3105 continue;
3106
3107 isr_data->isr = isr;
3108 isr_data->arg = arg;
3109 isr_data->mask = mask;
3110 ret = 0;
3111
3112 break;
3113 }
3114
b9cb0984
TV		 3115 if (ret)
3116 goto err;
3117
80c39712
TV		 3118 _omap_dispc_set_irqs();
3119
3120 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3121
3122 return 0;
3123err:
3124 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3125
3126 return ret;
3127}
3128EXPORT_SYMBOL(omap_dispc_register_isr);
3129
3130int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3131{
3132 int i;
3133 unsigned long flags;
3134 int ret = -EINVAL;
3135 struct omap_dispc_isr_data *isr_data;
3136
3137 spin_lock_irqsave(&dispc.irq_lock, flags);
3138
3139 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3140 isr_data = &dispc.registered_isr[i];
3141 if (isr_data->isr != isr || isr_data->arg != arg ||
3142 isr_data->mask != mask)
3143 continue;
3144
3145 /* found the correct isr */
3146
3147 isr_data->isr = NULL;
3148 isr_data->arg = NULL;
3149 isr_data->mask = 0;
3150
3151 ret = 0;
3152 break;
3153 }
3154
3155 if (ret == 0)
3156 _omap_dispc_set_irqs();
3157
3158 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3159
3160 return ret;
3161}
3162EXPORT_SYMBOL(omap_dispc_unregister_isr);
3163
3164#ifdef DEBUG
3165static void print_irq_status(u32 status)
3166{
3167 if ((status & dispc.irq_error_mask) == 0)
3168 return;
3169
3170 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3171
3172#define PIS(x) \
3173 if (status & DISPC_IRQ_##x) \
3174 printk(#x " ");
3175 PIS(GFX_FIFO_UNDERFLOW);
3176 PIS(OCP_ERR);
3177 PIS(VID1_FIFO_UNDERFLOW);
3178 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3179 if (dss_feat_get_num_ovls() > 3)
3180 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3181 PIS(SYNC_LOST);
3182 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3183 if (dss_has_feature(FEAT_MGR_LCD2))
3184 PIS(SYNC_LOST2);
80c39712
TV		 3185#undef PIS
3186
3187 printk("\n");
3188}
3189#endif
3190
3191/* Called from dss.c. Note that we don't touch clocks here,
3192 * but we presume they are on because we got an IRQ. However,
3193 * an irq handler may turn the clocks off, so we may not have
3194 * clock later in the function. */
affe360d 3195static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3196{
3197 int i;
affe360d 3198 u32 irqstatus, irqenable;
80c39712
TV		 3199 u32 handledirqs = 0;
3200 u32 unhandled_errors;
3201 struct omap_dispc_isr_data *isr_data;
3202 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3203
3204 spin_lock(&dispc.irq_lock);
3205
3206 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3207 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3208
3209 /* IRQ is not for us */
3210 if (!(irqstatus & irqenable)) {
3211 spin_unlock(&dispc.irq_lock);
3212 return IRQ_NONE;
3213 }
80c39712 3214
dfc0fd8d
TV		 3215#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3216 spin_lock(&dispc.irq_stats_lock);
3217 dispc.irq_stats.irq_count++;
3218 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3219 spin_unlock(&dispc.irq_stats_lock);
3220#endif
3221
80c39712
TV		 3222#ifdef DEBUG
3223 if (dss_debug)
3224 print_irq_status(irqstatus);
3225#endif
3226 /* Ack the interrupt. Do it here before clocks are possibly turned
3227 * off */
3228 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3229 /* flush posted write */
3230 dispc_read_reg(DISPC_IRQSTATUS);
3231
3232 /* make a copy and unlock, so that isrs can unregister
3233 * themselves */
3234 memcpy(registered_isr, dispc.registered_isr,
3235 sizeof(registered_isr));
3236
3237 spin_unlock(&dispc.irq_lock);
3238
3239 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3240 isr_data = &registered_isr[i];
3241
3242 if (!isr_data->isr)
3243 continue;
3244
3245 if (isr_data->mask & irqstatus) {
3246 isr_data->isr(isr_data->arg, irqstatus);
3247 handledirqs |= isr_data->mask;
3248 }
3249 }
3250
3251 spin_lock(&dispc.irq_lock);
3252
3253 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3254
3255 if (unhandled_errors) {
3256 dispc.error_irqs |= unhandled_errors;
3257
3258 dispc.irq_error_mask &= ~unhandled_errors;
3259 _omap_dispc_set_irqs();
3260
3261 schedule_work(&dispc.error_work);
3262 }
3263
3264 spin_unlock(&dispc.irq_lock);
affe360d 3265
3266 return IRQ_HANDLED;
80c39712
TV		 3267}
3268
3269static void dispc_error_worker(struct work_struct *work)
3270{
3271 int i;
3272 u32 errors;
3273 unsigned long flags;
fe3cc9d6
TV		 3274 static const unsigned fifo_underflow_bits[] = {
3275 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3276 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3277 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3278 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3279 };
3280
3281 static const unsigned sync_lost_bits[] = {
3282 DISPC_IRQ_SYNC_LOST,
3283 DISPC_IRQ_SYNC_LOST_DIGIT,
3284 DISPC_IRQ_SYNC_LOST2,
3285 };
80c39712
TV		 3286
3287 spin_lock_irqsave(&dispc.irq_lock, flags);
3288 errors = dispc.error_irqs;
3289 dispc.error_irqs = 0;
3290 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3291
13eae1f9
DZ		 3292 dispc_runtime_get();
3293
fe3cc9d6
TV		 3294 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3295 struct omap_overlay *ovl;
3296 unsigned bit;
80c39712 3297
fe3cc9d6
TV		 3298 ovl = omap_dss_get_overlay(i);
3299 bit = fifo_underflow_bits[i];
80c39712 3300
fe3cc9d6
TV		 3301 if (bit & errors) {
3302 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3303 ovl->name);
f0e5caab 3304 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3305 dispc_mgr_go(ovl->manager->id);
80c39712 3306 mdelay(50);
80c39712
TV		 3307 }
3308 }
3309
fe3cc9d6
TV		 3310 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3311 struct omap_overlay_manager *mgr;
3312 unsigned bit;
80c39712 3313
fe3cc9d6
TV		 3314 mgr = omap_dss_get_overlay_manager(i);
3315 bit = sync_lost_bits[i];
80c39712 3316
fe3cc9d6
TV		 3317 if (bit & errors) {
3318 struct omap_dss_device *dssdev = mgr->device;
3319 bool enable;
80c39712 3320
fe3cc9d6
TV		 3321 DSSERR("SYNC_LOST on channel %s, restarting the output "
3322 "with video overlays disabled\n",
3323 mgr->name);
2a205f34 3324
fe3cc9d6
TV		 3325 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3326 dssdev->driver->disable(dssdev);
2a205f34 3327
2a205f34
SS		 3328 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3329 struct omap_overlay *ovl;
3330 ovl = omap_dss_get_overlay(i);
3331
fe3cc9d6
TV		 3332 if (ovl->id != OMAP_DSS_GFX &&
3333 ovl->manager == mgr)
f0e5caab 3334 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3335 }
3336
26d9dd0d 3337 dispc_mgr_go(mgr->id);
2a205f34 3338 mdelay(50);
fe3cc9d6 3339
2a205f34
SS		 3340 if (enable)
3341 dssdev->driver->enable(dssdev);
3342 }
3343 }
3344
80c39712
TV		 3345 if (errors & DISPC_IRQ_OCP_ERR) {
3346 DSSERR("OCP_ERR\n");
3347 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3348 struct omap_overlay_manager *mgr;
3349 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3350 if (mgr->device && mgr->device->driver)
3351 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3352 }
3353 }
3354
3355 spin_lock_irqsave(&dispc.irq_lock, flags);
3356 dispc.irq_error_mask |= errors;
3357 _omap_dispc_set_irqs();
3358 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3359
3360 dispc_runtime_put();
80c39712
TV		 3361}
3362
3363int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3364{
3365 void dispc_irq_wait_handler(void *data, u32 mask)
3366 {
3367 complete((struct completion *)data);
3368 }
3369
3370 int r;
3371 DECLARE_COMPLETION_ONSTACK(completion);
3372
3373 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3374 irqmask);
3375
3376 if (r)
3377 return r;
3378
3379 timeout = wait_for_completion_timeout(&completion, timeout);
3380
3381 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3382
3383 if (timeout == 0)
3384 return -ETIMEDOUT;
3385
3386 if (timeout == -ERESTARTSYS)
3387 return -ERESTARTSYS;
3388
3389 return 0;
3390}
3391
3392int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3393 unsigned long timeout)
3394{
3395 void dispc_irq_wait_handler(void *data, u32 mask)
3396 {
3397 complete((struct completion *)data);
3398 }
3399
3400 int r;
3401 DECLARE_COMPLETION_ONSTACK(completion);
3402
3403 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3404 irqmask);
3405
3406 if (r)
3407 return r;
3408
3409 timeout = wait_for_completion_interruptible_timeout(&completion,
3410 timeout);
3411
3412 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3413
3414 if (timeout == 0)
3415 return -ETIMEDOUT;
3416
3417 if (timeout == -ERESTARTSYS)
3418 return -ERESTARTSYS;
3419
3420 return 0;
3421}
3422
80c39712
TV		 3423static void _omap_dispc_initialize_irq(void)
3424{
3425 unsigned long flags;
3426
3427 spin_lock_irqsave(&dispc.irq_lock, flags);
3428
3429 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3430
3431 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3432 if (dss_has_feature(FEAT_MGR_LCD2))
3433 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3434 if (dss_feat_get_num_ovls() > 3)
3435 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3436
3437 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3438 * so clear it */
3439 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3440
3441 _omap_dispc_set_irqs();
3442
3443 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3444}
3445
3446void dispc_enable_sidle(void)
3447{
3448 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3449}
3450
3451void dispc_disable_sidle(void)
3452{
3453 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3454}
3455
3456static void _omap_dispc_initial_config(void)
3457{
3458 u32 l;
3459
0cf35df3
MR		 3460 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3461 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3462 l = dispc_read_reg(DISPC_DIVISOR);
3463 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3464 l = FLD_MOD(l, 1, 0, 0);
3465 l = FLD_MOD(l, 1, 23, 16);
3466 dispc_write_reg(DISPC_DIVISOR, l);
3467 }
3468
80c39712 3469 /* FUNCGATED */
6ced40bf
AT		 3470 if (dss_has_feature(FEAT_FUNCGATED))
3471 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3472
80c39712
TV		 3473 _dispc_setup_color_conv_coef();
3474
3475 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3476
3477 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3478
3479 dispc_configure_burst_sizes();
54128701
AT		 3480
3481 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3482}
3483
060b6d9c
SG		 3484/* DISPC HW IP initialisation */
3485static int omap_dispchw_probe(struct platform_device *pdev)
3486{
3487 u32 rev;
affe360d 3488 int r = 0;
ea9da36a 3489 struct resource *dispc_mem;
4fbafaf3 3490 struct clk *clk;
ea9da36a 3491
060b6d9c
SG		 3492 dispc.pdev = pdev;
3493
3494 spin_lock_init(&dispc.irq_lock);
3495
3496#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3497 spin_lock_init(&dispc.irq_stats_lock);
3498 dispc.irq_stats.last_reset = jiffies;
3499#endif
3500
3501 INIT_WORK(&dispc.error_work, dispc_error_worker);
3502
ea9da36a
SG		 3503 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3504 if (!dispc_mem) {
3505 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3506 return -EINVAL;
ea9da36a 3507 }
cd3b3449 3508
6e2a14d2
JL		 3509 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3510 resource_size(dispc_mem));
060b6d9c
SG		 3511 if (!dispc.base) {
3512 DSSERR("can't ioremap DISPC\n");
cd3b3449 3513 return -ENOMEM;
affe360d 3514 }
cd3b3449 3515
affe360d 3516 dispc.irq = platform_get_irq(dispc.pdev, 0);
3517 if (dispc.irq < 0) {
3518 DSSERR("platform_get_irq failed\n");
cd3b3449 3519 return -ENODEV;
affe360d 3520 }
3521
6e2a14d2
JL		 3522 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3523 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3524 if (r < 0) {
3525 DSSERR("request_irq failed\n");
cd3b3449
TV		 3526 return r;
3527 }
3528
3529 clk = clk_get(&pdev->dev, "fck");
3530 if (IS_ERR(clk)) {
3531 DSSERR("can't get fck\n");
3532 r = PTR_ERR(clk);
3533 return r;
060b6d9c
SG		 3534 }
3535
cd3b3449
TV		 3536 dispc.dss_clk = clk;
3537
4fbafaf3
TV		 3538 pm_runtime_enable(&pdev->dev);
3539
3540 r = dispc_runtime_get();
3541 if (r)
3542 goto err_runtime_get;
060b6d9c
SG		 3543
3544 _omap_dispc_initial_config();
3545
3546 _omap_dispc_initialize_irq();
3547
060b6d9c 3548 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3549 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3550 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3551
4fbafaf3 3552 dispc_runtime_put();
060b6d9c 3553
e40402cf
TV		 3554 dss_debugfs_create_file("dispc", dispc_dump_regs);
3555
3556#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3557 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3558#endif
060b6d9c 3559 return 0;
4fbafaf3
TV		 3560
3561err_runtime_get:
3562 pm_runtime_disable(&pdev->dev);
4fbafaf3 3563 clk_put(dispc.dss_clk);
affe360d 3564 return r;
060b6d9c
SG		 3565}
3566
3567static int omap_dispchw_remove(struct platform_device *pdev)
3568{
4fbafaf3
TV		 3569 pm_runtime_disable(&pdev->dev);
3570
3571 clk_put(dispc.dss_clk);
3572
060b6d9c
SG		 3573 return 0;
3574}
3575
4fbafaf3
TV		 3576static int dispc_runtime_suspend(struct device *dev)
3577{
3578 dispc_save_context();
4fbafaf3
TV		 3579
3580 return 0;
3581}
3582
3583static int dispc_runtime_resume(struct device *dev)
3584{
49ea86f3 3585 dispc_restore_context();
4fbafaf3
TV		 3586
3587 return 0;
3588}
3589
3590static const struct dev_pm_ops dispc_pm_ops = {
3591 .runtime_suspend = dispc_runtime_suspend,
3592 .runtime_resume = dispc_runtime_resume,
3593};
3594
060b6d9c 3595static struct platform_driver omap_dispchw_driver = {
060b6d9c
SG		 3596 .remove = omap_dispchw_remove,
3597 .driver = {
3598 .name = "omapdss_dispc",
3599 .owner = THIS_MODULE,
4fbafaf3 3600 .pm = &dispc_pm_ops,
060b6d9c
SG		 3601 },
3602};
3603
3604int dispc_init_platform_driver(void)
3605{
11436e1d 3606 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3607}
3608
3609void dispc_uninit_platform_driver(void)
3610{
04c742c3 3611 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3612}
Linux kernel - Deliverables
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