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video: da8xx-fb: Use "SIMPLE_DEV_PM_OPS" macro
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
80c39712 39
a0b38cc4 40#include <video/omapdss.h>
80c39712
TV		 41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
9b372c2d 44#include "dispc.h"
80c39712
TV		 45
46/* DISPC */
8613b000 47#define DISPC_SZ_REGS SZ_4K
80c39712 48
5ed8cf5b
TV		 49enum omap_burst_size {
50 BURST_SIZE_X2 = 0,
51 BURST_SIZE_X4 = 1,
52 BURST_SIZE_X8 = 2,
53};
54
80c39712
TV		 55#define REG_GET(idx, start, end) \
56 FLD_GET(dispc_read_reg(idx), start, end)
57
58#define REG_FLD_MOD(idx, val, start, end) \
59 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
60
dcbe765b
CM		 61struct dispc_features {
62 u8 sw_start;
63 u8 fp_start;
64 u8 bp_start;
65 u16 sw_max;
66 u16 vp_max;
67 u16 hp_max;
33b89928
AT		 68 u8 mgr_width_start;
69 u8 mgr_height_start;
70 u16 mgr_width_max;
71 u16 mgr_height_max;
ca5ca69c
AT		 72 unsigned long max_lcd_pclk;
73 unsigned long max_tv_pclk;
0c6921de 74 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 75 const struct omap_video_timings *mgr_timings,
76 u16 width, u16 height, u16 out_width, u16 out_height,
77 enum omap_color_mode color_mode, bool *five_taps,
78 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 79 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 80 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 81 u16 width, u16 height, u16 out_width, u16 out_height,
82 bool mem_to_mem);
42a6961c 83 u8 num_fifos;
66a0f9e4
TV		 84
85 /* swap GFX & WB fifos */
86 bool gfx_fifo_workaround:1;
cffa947d
TV		 87
88 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
89 bool no_framedone_tv:1;
d0df9a2c
AT		 90
91 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
92 bool mstandby_workaround:1;
8bc65552
AT		 93
94 bool set_max_preload:1;
dcbe765b
CM		 95};
96
42a6961c
TV		 97#define DISPC_MAX_NR_FIFOS 5
98
80c39712 99static struct {
060b6d9c 100 struct platform_device *pdev;
80c39712 101 void __iomem *base;
4fbafaf3
TV		 102
103 int ctx_loss_cnt;
104
affe360d 105 int irq;
80c39712 106
7b3926b3 107 unsigned long core_clk_rate;
5391e87d 108 unsigned long tv_pclk_rate;
7b3926b3 109
42a6961c
TV		 110 u32 fifo_size[DISPC_MAX_NR_FIFOS];
111 /* maps which plane is using a fifo. fifo-id -> plane-id */
112 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 113
49ea86f3 114 bool ctx_valid;
80c39712 115 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 116
dcbe765b 117 const struct dispc_features *feat;
80c39712
TV		 118} dispc;
119
0d66cbb5
AJ		 120enum omap_color_component {
121 /* used for all color formats for OMAP3 and earlier
122 * and for RGB and Y color component on OMAP4
123 */
124 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
125 /* used for UV component for
126 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
127 * color formats on OMAP4
128 */
129 DISPC_COLOR_COMPONENT_UV = 1 << 1,
130};
131
efa70b3b
CM		 132enum mgr_reg_fields {
133 DISPC_MGR_FLD_ENABLE,
134 DISPC_MGR_FLD_STNTFT,
135 DISPC_MGR_FLD_GO,
136 DISPC_MGR_FLD_TFTDATALINES,
137 DISPC_MGR_FLD_STALLMODE,
138 DISPC_MGR_FLD_TCKENABLE,
139 DISPC_MGR_FLD_TCKSELECTION,
140 DISPC_MGR_FLD_CPR,
141 DISPC_MGR_FLD_FIFOHANDCHECK,
142 /* used to maintain a count of the above fields */
143 DISPC_MGR_FLD_NUM,
144};
145
146static const struct {
147 const char *name;
148 u32 vsync_irq;
149 u32 framedone_irq;
150 u32 sync_lost_irq;
151 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
152} mgr_desc[] = {
153 [OMAP_DSS_CHANNEL_LCD] = {
154 .name = "LCD",
155 .vsync_irq = DISPC_IRQ_VSYNC,
156 .framedone_irq = DISPC_IRQ_FRAMEDONE,
157 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
158 .reg_desc = {
159 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
160 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
161 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
162 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
163 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
164 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
165 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
166 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
167 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
168 },
169 },
170 [OMAP_DSS_CHANNEL_DIGIT] = {
171 .name = "DIGIT",
172 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 173 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 174 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
175 .reg_desc = {
176 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
177 [DISPC_MGR_FLD_STNTFT] = { },
178 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
179 [DISPC_MGR_FLD_TFTDATALINES] = { },
180 [DISPC_MGR_FLD_STALLMODE] = { },
181 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
182 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
183 [DISPC_MGR_FLD_CPR] = { },
184 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
185 },
186 },
187 [OMAP_DSS_CHANNEL_LCD2] = {
188 .name = "LCD2",
189 .vsync_irq = DISPC_IRQ_VSYNC2,
190 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
191 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
192 .reg_desc = {
193 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
194 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
195 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
196 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
197 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
198 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
199 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
200 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
201 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
202 },
203 },
e86d456a
CM		 204 [OMAP_DSS_CHANNEL_LCD3] = {
205 .name = "LCD3",
206 .vsync_irq = DISPC_IRQ_VSYNC3,
207 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
208 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
209 .reg_desc = {
210 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
211 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
212 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
213 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
214 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
215 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
216 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
217 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
218 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
219 },
220 },
efa70b3b
CM		 221};
222
6e5264b0
AT		 223struct color_conv_coef {
224 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
225 int full_range;
226};
227
3e8a6ff2
AT		 228static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
229static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 230
55978cc2 231static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 232{
55978cc2 233 __raw_writel(val, dispc.base + idx);
80c39712
TV		 234}
235
55978cc2 236static inline u32 dispc_read_reg(const u16 idx)
80c39712 237{
55978cc2 238 return __raw_readl(dispc.base + idx);
80c39712
TV		 239}
240
efa70b3b
CM		 241static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
242{
243 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
244 return REG_GET(rfld.reg, rfld.high, rfld.low);
245}
246
247static void mgr_fld_write(enum omap_channel channel,
248 enum mgr_reg_fields regfld, int val) {
249 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
250 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
251}
252
80c39712 253#define SR(reg) \
55978cc2 254 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 255#define RR(reg) \
55978cc2 256 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 257
4fbafaf3 258static void dispc_save_context(void)
80c39712 259{
c6104b8e 260 int i, j;
80c39712 261
4fbafaf3
TV		 262 DSSDBG("dispc_save_context\n");
263
80c39712
TV		 264 SR(IRQENABLE);
265 SR(CONTROL);
266 SR(CONFIG);
80c39712 267 SR(LINE_NUMBER);
11354dd5
AT		 268 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
269 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 270 SR(GLOBAL_ALPHA);
2a205f34
SS		 271 if (dss_has_feature(FEAT_MGR_LCD2)) {
272 SR(CONTROL2);
2a205f34
SS		 273 SR(CONFIG2);
274 }
e86d456a
CM		 275 if (dss_has_feature(FEAT_MGR_LCD3)) {
276 SR(CONTROL3);
277 SR(CONFIG3);
278 }
80c39712 279
c6104b8e
AT		 280 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
281 SR(DEFAULT_COLOR(i));
282 SR(TRANS_COLOR(i));
283 SR(SIZE_MGR(i));
284 if (i == OMAP_DSS_CHANNEL_DIGIT)
285 continue;
286 SR(TIMING_H(i));
287 SR(TIMING_V(i));
288 SR(POL_FREQ(i));
289 SR(DIVISORo(i));
290
291 SR(DATA_CYCLE1(i));
292 SR(DATA_CYCLE2(i));
293 SR(DATA_CYCLE3(i));
294
332e9d70 295 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 296 SR(CPR_COEF_R(i));
297 SR(CPR_COEF_G(i));
298 SR(CPR_COEF_B(i));
332e9d70 299 }
2a205f34 300 }
80c39712 301
c6104b8e
AT		 302 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
303 SR(OVL_BA0(i));
304 SR(OVL_BA1(i));
305 SR(OVL_POSITION(i));
306 SR(OVL_SIZE(i));
307 SR(OVL_ATTRIBUTES(i));
308 SR(OVL_FIFO_THRESHOLD(i));
309 SR(OVL_ROW_INC(i));
310 SR(OVL_PIXEL_INC(i));
311 if (dss_has_feature(FEAT_PRELOAD))
312 SR(OVL_PRELOAD(i));
313 if (i == OMAP_DSS_GFX) {
314 SR(OVL_WINDOW_SKIP(i));
315 SR(OVL_TABLE_BA(i));
316 continue;
317 }
318 SR(OVL_FIR(i));
319 SR(OVL_PICTURE_SIZE(i));
320 SR(OVL_ACCU0(i));
321 SR(OVL_ACCU1(i));
9b372c2d 322
c6104b8e
AT		 323 for (j = 0; j < 8; j++)
324 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 325
c6104b8e
AT		 326 for (j = 0; j < 8; j++)
327 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 328
c6104b8e
AT		 329 for (j = 0; j < 5; j++)
330 SR(OVL_CONV_COEF(i, j));
ab5ca071 331
c6104b8e
AT		 332 if (dss_has_feature(FEAT_FIR_COEF_V)) {
333 for (j = 0; j < 8; j++)
334 SR(OVL_FIR_COEF_V(i, j));
335 }
9b372c2d 336
c6104b8e
AT		 337 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
338 SR(OVL_BA0_UV(i));
339 SR(OVL_BA1_UV(i));
340 SR(OVL_FIR2(i));
341 SR(OVL_ACCU2_0(i));
342 SR(OVL_ACCU2_1(i));
ab5ca071 343
c6104b8e
AT		 344 for (j = 0; j < 8; j++)
345 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 346
c6104b8e
AT		 347 for (j = 0; j < 8; j++)
348 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 349
c6104b8e
AT		 350 for (j = 0; j < 8; j++)
351 SR(OVL_FIR_COEF_V2(i, j));
352 }
353 if (dss_has_feature(FEAT_ATTR2))
354 SR(OVL_ATTRIBUTES2(i));
ab5ca071 355 }
0cf35df3
MR		 356
357 if (dss_has_feature(FEAT_CORE_CLK_DIV))
358 SR(DIVISOR);
49ea86f3 359
bdb736ab 360 dispc.ctx_loss_cnt = dss_get_ctx_loss_count();
49ea86f3
TV		 361 dispc.ctx_valid = true;
362
363 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 364}
365
4fbafaf3 366static void dispc_restore_context(void)
80c39712 367{
c6104b8e 368 int i, j, ctx;
4fbafaf3
TV		 369
370 DSSDBG("dispc_restore_context\n");
371
49ea86f3
TV		 372 if (!dispc.ctx_valid)
373 return;
374
bdb736ab 375 ctx = dss_get_ctx_loss_count();
49ea86f3
TV		 376
377 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
378 return;
379
380 DSSDBG("ctx_loss_count: saved %d, current %d\n",
381 dispc.ctx_loss_cnt, ctx);
382
75c7d59d 383 /*RR(IRQENABLE);*/
80c39712
TV		 384 /*RR(CONTROL);*/
385 RR(CONFIG);
80c39712 386 RR(LINE_NUMBER);
11354dd5
AT		 387 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
388 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 389 RR(GLOBAL_ALPHA);
c6104b8e 390 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 391 RR(CONFIG2);
e86d456a
CM		 392 if (dss_has_feature(FEAT_MGR_LCD3))
393 RR(CONFIG3);
80c39712 394
c6104b8e
AT		 395 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
396 RR(DEFAULT_COLOR(i));
397 RR(TRANS_COLOR(i));
398 RR(SIZE_MGR(i));
399 if (i == OMAP_DSS_CHANNEL_DIGIT)
400 continue;
401 RR(TIMING_H(i));
402 RR(TIMING_V(i));
403 RR(POL_FREQ(i));
404 RR(DIVISORo(i));
405
406 RR(DATA_CYCLE1(i));
407 RR(DATA_CYCLE2(i));
408 RR(DATA_CYCLE3(i));
2a205f34 409
332e9d70 410 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 411 RR(CPR_COEF_R(i));
412 RR(CPR_COEF_G(i));
413 RR(CPR_COEF_B(i));
332e9d70 414 }
2a205f34 415 }
80c39712 416
c6104b8e
AT		 417 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
418 RR(OVL_BA0(i));
419 RR(OVL_BA1(i));
420 RR(OVL_POSITION(i));
421 RR(OVL_SIZE(i));
422 RR(OVL_ATTRIBUTES(i));
423 RR(OVL_FIFO_THRESHOLD(i));
424 RR(OVL_ROW_INC(i));
425 RR(OVL_PIXEL_INC(i));
426 if (dss_has_feature(FEAT_PRELOAD))
427 RR(OVL_PRELOAD(i));
428 if (i == OMAP_DSS_GFX) {
429 RR(OVL_WINDOW_SKIP(i));
430 RR(OVL_TABLE_BA(i));
431 continue;
432 }
433 RR(OVL_FIR(i));
434 RR(OVL_PICTURE_SIZE(i));
435 RR(OVL_ACCU0(i));
436 RR(OVL_ACCU1(i));
9b372c2d 437
c6104b8e
AT		 438 for (j = 0; j < 8; j++)
439 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 440
c6104b8e
AT		 441 for (j = 0; j < 8; j++)
442 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 443
c6104b8e
AT		 444 for (j = 0; j < 5; j++)
445 RR(OVL_CONV_COEF(i, j));
ab5ca071 446
c6104b8e
AT		 447 if (dss_has_feature(FEAT_FIR_COEF_V)) {
448 for (j = 0; j < 8; j++)
449 RR(OVL_FIR_COEF_V(i, j));
450 }
9b372c2d 451
c6104b8e
AT		 452 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
453 RR(OVL_BA0_UV(i));
454 RR(OVL_BA1_UV(i));
455 RR(OVL_FIR2(i));
456 RR(OVL_ACCU2_0(i));
457 RR(OVL_ACCU2_1(i));
ab5ca071 458
c6104b8e
AT		 459 for (j = 0; j < 8; j++)
460 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 461
c6104b8e
AT		 462 for (j = 0; j < 8; j++)
463 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 464
c6104b8e
AT		 465 for (j = 0; j < 8; j++)
466 RR(OVL_FIR_COEF_V2(i, j));
467 }
468 if (dss_has_feature(FEAT_ATTR2))
469 RR(OVL_ATTRIBUTES2(i));
ab5ca071 470 }
80c39712 471
0cf35df3
MR		 472 if (dss_has_feature(FEAT_CORE_CLK_DIV))
473 RR(DIVISOR);
474
80c39712
TV		 475 /* enable last, because LCD & DIGIT enable are here */
476 RR(CONTROL);
2a205f34
SS		 477 if (dss_has_feature(FEAT_MGR_LCD2))
478 RR(CONTROL2);
e86d456a
CM		 479 if (dss_has_feature(FEAT_MGR_LCD3))
480 RR(CONTROL3);
75c7d59d 481 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 482 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 483
484 /*
485 * enable last so IRQs won't trigger before
486 * the context is fully restored
487 */
488 RR(IRQENABLE);
49ea86f3
TV		 489
490 DSSDBG("context restored\n");
80c39712
TV		 491}
492
493#undef SR
494#undef RR
495
4fbafaf3
TV		 496int dispc_runtime_get(void)
497{
498 int r;
499
500 DSSDBG("dispc_runtime_get\n");
501
502 r = pm_runtime_get_sync(&dispc.pdev->dev);
503 WARN_ON(r < 0);
504 return r < 0 ? r : 0;
505}
348be69d 506EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 507
508void dispc_runtime_put(void)
509{
510 int r;
511
512 DSSDBG("dispc_runtime_put\n");
513
0eaf9f52 514 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 515 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 516}
348be69d 517EXPORT_SYMBOL(dispc_runtime_put);
80c39712 518
3dcec4d6
TV		 519u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
520{
efa70b3b 521 return mgr_desc[channel].vsync_irq;
3dcec4d6 522}
348be69d 523EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 524
7d1365c9
TV		 525u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
526{
cffa947d
TV		 527 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
528 return 0;
529
efa70b3b 530 return mgr_desc[channel].framedone_irq;
7d1365c9 531}
348be69d 532EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 533
cb699200
TV		 534u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
535{
536 return mgr_desc[channel].sync_lost_irq;
537}
348be69d 538EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 539
0b23e5b8
AT		 540u32 dispc_wb_get_framedone_irq(void)
541{
542 return DISPC_IRQ_FRAMEDONEWB;
543}
544
26d9dd0d 545bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 546{
efa70b3b 547 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 548}
348be69d 549EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 550
26d9dd0d 551void dispc_mgr_go(enum omap_channel channel)
80c39712 552{
3c91ee8c
TV		 553 WARN_ON(dispc_mgr_is_enabled(channel) == false);
554 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 555
efa70b3b 556 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 557
efa70b3b 558 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 559}
348be69d 560EXPORT_SYMBOL(dispc_mgr_go);
80c39712 561
0b23e5b8
AT		 562bool dispc_wb_go_busy(void)
563{
564 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
565}
566
567void dispc_wb_go(void)
568{
569 enum omap_plane plane = OMAP_DSS_WB;
570 bool enable, go;
571
572 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
573
574 if (!enable)
575 return;
576
577 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
578 if (go) {
579 DSSERR("GO bit not down for WB\n");
580 return;
581 }
582
583 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
584}
585
f0e5caab 586static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 587{
9b372c2d 588 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 589}
590
f0e5caab 591static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 592{
9b372c2d 593 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 594}
595
f0e5caab 596static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 597{
9b372c2d 598 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 599}
600
f0e5caab 601static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 602{
603 BUG_ON(plane == OMAP_DSS_GFX);
604
605 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
606}
607
f0e5caab
TV		 608static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
609 u32 value)
ab5ca071
AJ		 610{
611 BUG_ON(plane == OMAP_DSS_GFX);
612
613 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
614}
615
f0e5caab 616static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 617{
618 BUG_ON(plane == OMAP_DSS_GFX);
619
620 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
621}
622
debd9074
CM		 623static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
624 int fir_vinc, int five_taps,
625 enum omap_color_component color_comp)
80c39712 626{
debd9074 627 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 628 int i;
629
debd9074
CM		 630 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
631 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 632
633 for (i = 0; i < 8; i++) {
634 u32 h, hv;
635
debd9074
CM		 636 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
637 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
638 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
639 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
640 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
641 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
642 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
643 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 644
0d66cbb5 645 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 646 dispc_ovl_write_firh_reg(plane, i, h);
647 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 648 } else {
f0e5caab
TV		 649 dispc_ovl_write_firh2_reg(plane, i, h);
650 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 651 }
652
80c39712
TV		 653 }
654
66be8f6c
GI		 655 if (five_taps) {
656 for (i = 0; i < 8; i++) {
657 u32 v;
debd9074
CM		 658 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
659 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 660 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 661 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 662 else
f0e5caab 663 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 664 }
80c39712
TV		 665 }
666}
667
80c39712 668
6e5264b0
AT		 669static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
670 const struct color_conv_coef *ct)
671{
80c39712
TV		 672#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
673
6e5264b0
AT		 674 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
675 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
676 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
677 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
678 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 679
6e5264b0 680 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 681
682#undef CVAL
80c39712
TV		 683}
684
6e5264b0
AT		 685static void dispc_setup_color_conv_coef(void)
686{
687 int i;
688 int num_ovl = dss_feat_get_num_ovls();
689 int num_wb = dss_feat_get_num_wbs();
690 const struct color_conv_coef ctbl_bt601_5_ovl = {
691 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
692 };
693 const struct color_conv_coef ctbl_bt601_5_wb = {
694 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
695 };
696
697 for (i = 1; i < num_ovl; i++)
698 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
699
700 for (; i < num_wb; i++)
701 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
702}
80c39712 703
f0e5caab 704static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 705{
9b372c2d 706 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 707}
708
f0e5caab 709static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 710{
9b372c2d 711 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 712}
713
f0e5caab 714static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 715{
716 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
717}
718
f0e5caab 719static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 720{
721 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
722}
723
d79db853
AT		 724static void dispc_ovl_set_pos(enum omap_plane plane,
725 enum omap_overlay_caps caps, int x, int y)
80c39712 726{
d79db853
AT		 727 u32 val;
728
729 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
730 return;
731
732 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 733
734 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 735}
736
78b687fc
AT		 737static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
738 int height)
80c39712 739{
80c39712 740 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 741
36d87d95 742 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 743 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
744 else
745 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 746}
747
78b687fc
AT		 748static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
749 int height)
80c39712
TV		 750{
751 u32 val;
80c39712
TV		 752
753 BUG_ON(plane == OMAP_DSS_GFX);
754
755 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 756
36d87d95
AT		 757 if (plane == OMAP_DSS_WB)
758 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
759 else
760 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 761}
762
5b54ed3e
AT		 763static void dispc_ovl_set_zorder(enum omap_plane plane,
764 enum omap_overlay_caps caps, u8 zorder)
54128701 765{
5b54ed3e 766 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 767 return;
768
769 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
770}
771
772static void dispc_ovl_enable_zorder_planes(void)
773{
774 int i;
775
776 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
777 return;
778
779 for (i = 0; i < dss_feat_get_num_ovls(); i++)
780 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
781}
782
5b54ed3e
AT		 783static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
784 enum omap_overlay_caps caps, bool enable)
fd28a390 785{
5b54ed3e 786 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 787 return;
788
9b372c2d 789 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 790}
791
5b54ed3e
AT		 792static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
793 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 794{
b8c095b4 795 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 796 int shift;
797
5b54ed3e 798 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 799 return;
a0acb557 800
fe3cc9d6
TV		 801 shift = shifts[plane];
802 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 803}
804
f0e5caab 805static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 806{
9b372c2d 807 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 808}
809
f0e5caab 810static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 811{
9b372c2d 812 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 813}
814
f0e5caab 815static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 816 enum omap_color_mode color_mode)
817{
818 u32 m = 0;
f20e4220
AJ		 819 if (plane != OMAP_DSS_GFX) {
820 switch (color_mode) {
821 case OMAP_DSS_COLOR_NV12:
822 m = 0x0; break;
08f3267e 823 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 824 m = 0x1; break;
825 case OMAP_DSS_COLOR_RGBA16:
826 m = 0x2; break;
08f3267e 827 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 828 m = 0x4; break;
829 case OMAP_DSS_COLOR_ARGB16:
830 m = 0x5; break;
831 case OMAP_DSS_COLOR_RGB16:
832 m = 0x6; break;
833 case OMAP_DSS_COLOR_ARGB16_1555:
834 m = 0x7; break;
835 case OMAP_DSS_COLOR_RGB24U:
836 m = 0x8; break;
837 case OMAP_DSS_COLOR_RGB24P:
838 m = 0x9; break;
839 case OMAP_DSS_COLOR_YUV2:
840 m = 0xa; break;
841 case OMAP_DSS_COLOR_UYVY:
842 m = 0xb; break;
843 case OMAP_DSS_COLOR_ARGB32:
844 m = 0xc; break;
845 case OMAP_DSS_COLOR_RGBA32:
846 m = 0xd; break;
847 case OMAP_DSS_COLOR_RGBX32:
848 m = 0xe; break;
849 case OMAP_DSS_COLOR_XRGB16_1555:
850 m = 0xf; break;
851 default:
c6eee968 852 BUG(); return;
f20e4220
AJ		 853 }
854 } else {
855 switch (color_mode) {
856 case OMAP_DSS_COLOR_CLUT1:
857 m = 0x0; break;
858 case OMAP_DSS_COLOR_CLUT2:
859 m = 0x1; break;
860 case OMAP_DSS_COLOR_CLUT4:
861 m = 0x2; break;
862 case OMAP_DSS_COLOR_CLUT8:
863 m = 0x3; break;
864 case OMAP_DSS_COLOR_RGB12U:
865 m = 0x4; break;
866 case OMAP_DSS_COLOR_ARGB16:
867 m = 0x5; break;
868 case OMAP_DSS_COLOR_RGB16:
869 m = 0x6; break;
870 case OMAP_DSS_COLOR_ARGB16_1555:
871 m = 0x7; break;
872 case OMAP_DSS_COLOR_RGB24U:
873 m = 0x8; break;
874 case OMAP_DSS_COLOR_RGB24P:
875 m = 0x9; break;
08f3267e 876 case OMAP_DSS_COLOR_RGBX16:
f20e4220 877 m = 0xa; break;
08f3267e 878 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 879 m = 0xb; break;
880 case OMAP_DSS_COLOR_ARGB32:
881 m = 0xc; break;
882 case OMAP_DSS_COLOR_RGBA32:
883 m = 0xd; break;
884 case OMAP_DSS_COLOR_RGBX32:
885 m = 0xe; break;
886 case OMAP_DSS_COLOR_XRGB16_1555:
887 m = 0xf; break;
888 default:
c6eee968 889 BUG(); return;
f20e4220 890 }
80c39712
TV		 891 }
892
9b372c2d 893 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 894}
895
65e006ff
CM		 896static void dispc_ovl_configure_burst_type(enum omap_plane plane,
897 enum omap_dss_rotation_type rotation_type)
898{
899 if (dss_has_feature(FEAT_BURST_2D) == 0)
900 return;
901
902 if (rotation_type == OMAP_DSS_ROT_TILER)
903 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
904 else
905 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
906}
907
f427984e 908void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 909{
910 int shift;
911 u32 val;
2a205f34 912 int chan = 0, chan2 = 0;
80c39712
TV		 913
914 switch (plane) {
915 case OMAP_DSS_GFX:
916 shift = 8;
917 break;
918 case OMAP_DSS_VIDEO1:
919 case OMAP_DSS_VIDEO2:
b8c095b4 920 case OMAP_DSS_VIDEO3:
80c39712
TV		 921 shift = 16;
922 break;
923 default:
924 BUG();
925 return;
926 }
927
9b372c2d 928 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 929 if (dss_has_feature(FEAT_MGR_LCD2)) {
930 switch (channel) {
931 case OMAP_DSS_CHANNEL_LCD:
932 chan = 0;
933 chan2 = 0;
934 break;
935 case OMAP_DSS_CHANNEL_DIGIT:
936 chan = 1;
937 chan2 = 0;
938 break;
939 case OMAP_DSS_CHANNEL_LCD2:
940 chan = 0;
941 chan2 = 1;
942 break;
e86d456a
CM		 943 case OMAP_DSS_CHANNEL_LCD3:
944 if (dss_has_feature(FEAT_MGR_LCD3)) {
945 chan = 0;
946 chan2 = 2;
947 } else {
948 BUG();
949 return;
950 }
951 break;
2a205f34
SS		 952 default:
953 BUG();
c6eee968 954 return;
2a205f34
SS		 955 }
956
957 val = FLD_MOD(val, chan, shift, shift);
958 val = FLD_MOD(val, chan2, 31, 30);
959 } else {
960 val = FLD_MOD(val, channel, shift, shift);
961 }
9b372c2d 962 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 963}
348be69d 964EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 965
2cc5d1af
TV		 966static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
967{
968 int shift;
969 u32 val;
970 enum omap_channel channel;
971
972 switch (plane) {
973 case OMAP_DSS_GFX:
974 shift = 8;
975 break;
976 case OMAP_DSS_VIDEO1:
977 case OMAP_DSS_VIDEO2:
978 case OMAP_DSS_VIDEO3:
979 shift = 16;
980 break;
981 default:
982 BUG();
c6eee968 983 return 0;
2cc5d1af
TV		 984 }
985
986 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
987
e86d456a
CM		 988 if (dss_has_feature(FEAT_MGR_LCD3)) {
989 if (FLD_GET(val, 31, 30) == 0)
990 channel = FLD_GET(val, shift, shift);
991 else if (FLD_GET(val, 31, 30) == 1)
992 channel = OMAP_DSS_CHANNEL_LCD2;
993 else
994 channel = OMAP_DSS_CHANNEL_LCD3;
995 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 996 if (FLD_GET(val, 31, 30) == 0)
997 channel = FLD_GET(val, shift, shift);
998 else
999 channel = OMAP_DSS_CHANNEL_LCD2;
1000 } else {
1001 channel = FLD_GET(val, shift, shift);
1002 }
1003
1004 return channel;
1005}
1006
d9ac773c
AT		 1007void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1008{
1009 enum omap_plane plane = OMAP_DSS_WB;
1010
1011 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1012}
1013
f0e5caab 1014static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1015 enum omap_burst_size burst_size)
1016{
8bbe09ee 1017 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1018 int shift;
80c39712 1019
fe3cc9d6 1020 shift = shifts[plane];
5ed8cf5b 1021 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1022}
1023
5ed8cf5b
TV		 1024static void dispc_configure_burst_sizes(void)
1025{
1026 int i;
1027 const int burst_size = BURST_SIZE_X8;
1028
1029 /* Configure burst size always to maximum size */
392faa0e 1030 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1031 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1032}
1033
83fa2f2e 1034static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1035{
1036 unsigned unit = dss_feat_get_burst_size_unit();
1037 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1038 return unit * 8;
1039}
1040
d3862610
M		 1041void dispc_enable_gamma_table(bool enable)
1042{
1043 /*
1044 * This is partially implemented to support only disabling of
1045 * the gamma table.
1046 */
1047 if (enable) {
1048 DSSWARN("Gamma table enabling for TV not yet supported");
1049 return;
1050 }
1051
1052 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1053}
1054
c64dca40 1055static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1056{
efa70b3b 1057 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1058 return;
1059
efa70b3b 1060 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1061}
1062
c64dca40 1063static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1064 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1065{
1066 u32 coef_r, coef_g, coef_b;
1067
dd88b7a6 1068 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1069 return;
1070
1071 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1072 FLD_VAL(coefs->rb, 9, 0);
1073 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1074 FLD_VAL(coefs->gb, 9, 0);
1075 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1076 FLD_VAL(coefs->bb, 9, 0);
1077
1078 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1079 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1080 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1081}
1082
f0e5caab 1083static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1084{
1085 u32 val;
1086
1087 BUG_ON(plane == OMAP_DSS_GFX);
1088
9b372c2d 1089 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1090 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1091 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1092}
1093
d79db853
AT		 1094static void dispc_ovl_enable_replication(enum omap_plane plane,
1095 enum omap_overlay_caps caps, bool enable)
80c39712 1096{
b8c095b4 1097 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1098 int shift;
80c39712 1099
d79db853
AT		 1100 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1101 return;
1102
fe3cc9d6
TV		 1103 shift = shifts[plane];
1104 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1105}
1106
8f366162 1107static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1108 u16 height)
80c39712
TV		 1109{
1110 u32 val;
80c39712 1111
33b89928
AT		 1112 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1113 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1114
8f366162 1115 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1116}
1117
42a6961c 1118static void dispc_init_fifos(void)
80c39712 1119{
80c39712 1120 u32 size;
42a6961c 1121 int fifo;
a0acb557 1122 u8 start, end;
5ed8cf5b
TV		 1123 u32 unit;
1124
1125 unit = dss_feat_get_buffer_size_unit();
80c39712 1126
a0acb557 1127 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1128
42a6961c
TV		 1129 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1130 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1131 size *= unit;
42a6961c
TV		 1132 dispc.fifo_size[fifo] = size;
1133
1134 /*
1135 * By default fifos are mapped directly to overlays, fifo 0 to
1136 * ovl 0, fifo 1 to ovl 1, etc.
1137 */
1138 dispc.fifo_assignment[fifo] = fifo;
80c39712 1139 }
66a0f9e4
TV		 1140
1141 /*
1142 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1143 * causes problems with certain use cases, like using the tiler in 2D
1144 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1145 * giving GFX plane a larger fifo. WB but should work fine with a
1146 * smaller fifo.
1147 */
1148 if (dispc.feat->gfx_fifo_workaround) {
1149 u32 v;
1150
1151 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1152
1153 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1154 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1155 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1156 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1157
1158 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1159
1160 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1161 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1162 }
80c39712
TV		 1163}
1164
83fa2f2e 1165static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1166{
42a6961c
TV		 1167 int fifo;
1168 u32 size = 0;
1169
1170 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1171 if (dispc.fifo_assignment[fifo] == plane)
1172 size += dispc.fifo_size[fifo];
1173 }
1174
1175 return size;
80c39712
TV		 1176}
1177
6f04e1bf 1178void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1179{
a0acb557 1180 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1181 u32 unit;
1182
1183 unit = dss_feat_get_buffer_size_unit();
1184
1185 WARN_ON(low % unit != 0);
1186 WARN_ON(high % unit != 0);
1187
1188 low /= unit;
1189 high /= unit;
a0acb557 1190
9b372c2d
AT		 1191 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1192 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1193
3cb5d966 1194 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1195 plane,
9b372c2d 1196 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1197 lo_start, lo_end) * unit,
9b372c2d 1198 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1199 hi_start, hi_end) * unit,
1200 low * unit, high * unit);
80c39712 1201
9b372c2d 1202 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1203 FLD_VAL(high, hi_start, hi_end) |
1204 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1205
1206 /*
1207 * configure the preload to the pipeline's high threhold, if HT it's too
1208 * large for the preload field, set the threshold to the maximum value
1209 * that can be held by the preload register
1210 */
1211 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1212 plane != OMAP_DSS_WB)
1213 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712 1214}
8ee5c842 1215EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
80c39712
TV		 1216
1217void dispc_enable_fifomerge(bool enable)
1218{
e6b0f884
TV		 1219 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1220 WARN_ON(enable);
1221 return;
1222 }
1223
80c39712
TV		 1224 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1225 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1226}
1227
83fa2f2e 1228void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1229 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1230 bool manual_update)
83fa2f2e
TV		 1231{
1232 /*
1233 * All sizes are in bytes. Both the buffer and burst are made of
1234 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1235 */
1236
1237 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1238 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1239 int i;
83fa2f2e
TV		 1240
1241 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1242 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1243
e0e405b9
TV		 1244 if (use_fifomerge) {
1245 total_fifo_size = 0;
392faa0e 1246 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1247 total_fifo_size += dispc_ovl_get_fifo_size(i);
1248 } else {
1249 total_fifo_size = ovl_fifo_size;
1250 }
1251
1252 /*
1253 * We use the same low threshold for both fifomerge and non-fifomerge
1254 * cases, but for fifomerge we calculate the high threshold using the
1255 * combined fifo size
1256 */
1257
3568f2a4 1258 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1259 *fifo_low = ovl_fifo_size - burst_size * 2;
1260 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1261 } else if (plane == OMAP_DSS_WB) {
1262 /*
1263 * Most optimal configuration for writeback is to push out data
1264 * to the interconnect the moment writeback pushes enough pixels
1265 * in the FIFO to form a burst
1266 */
1267 *fifo_low = 0;
1268 *fifo_high = burst_size;
e0e405b9
TV		 1269 } else {
1270 *fifo_low = ovl_fifo_size - burst_size;
1271 *fifo_high = total_fifo_size - buf_unit;
1272 }
83fa2f2e 1273}
8ee5c842 1274EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
83fa2f2e 1275
f0e5caab 1276static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1277 int hinc, int vinc,
1278 enum omap_color_component color_comp)
80c39712
TV		 1279{
1280 u32 val;
80c39712 1281
0d66cbb5
AJ		 1282 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1283 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1284
0d66cbb5
AJ		 1285 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1286 &hinc_start, &hinc_end);
1287 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1288 &vinc_start, &vinc_end);
1289 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1290 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1291
0d66cbb5
AJ		 1292 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1293 } else {
1294 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1295 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1296 }
80c39712
TV		 1297}
1298
f0e5caab 1299static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1300{
1301 u32 val;
87a7484b 1302 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1303
87a7484b
AT		 1304 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1305 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1306
1307 val = FLD_VAL(vaccu, vert_start, vert_end) |
1308 FLD_VAL(haccu, hor_start, hor_end);
1309
9b372c2d 1310 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1311}
1312
f0e5caab 1313static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1314{
1315 u32 val;
87a7484b 1316 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1317
87a7484b
AT		 1318 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1319 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1320
1321 val = FLD_VAL(vaccu, vert_start, vert_end) |
1322 FLD_VAL(haccu, hor_start, hor_end);
1323
9b372c2d 1324 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1325}
1326
f0e5caab
TV		 1327static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1328 int vaccu)
ab5ca071
AJ		 1329{
1330 u32 val;
1331
1332 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1333 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1334}
1335
f0e5caab
TV		 1336static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1337 int vaccu)
ab5ca071
AJ		 1338{
1339 u32 val;
1340
1341 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1342 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1343}
80c39712 1344
f0e5caab 1345static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1346 u16 orig_width, u16 orig_height,
1347 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1348 bool five_taps, u8 rotation,
1349 enum omap_color_component color_comp)
80c39712 1350{
0d66cbb5 1351 int fir_hinc, fir_vinc;
80c39712 1352
ed14a3ce
AJ		 1353 fir_hinc = 1024 * orig_width / out_width;
1354 fir_vinc = 1024 * orig_height / out_height;
80c39712 1355
debd9074
CM		 1356 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1357 color_comp);
f0e5caab 1358 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1359}
1360
05dd0f53
CM		 1361static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1362 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1363 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1364{
1365 int h_accu2_0, h_accu2_1;
1366 int v_accu2_0, v_accu2_1;
1367 int chroma_hinc, chroma_vinc;
1368 int idx;
1369
1370 struct accu {
1371 s8 h0_m, h0_n;
1372 s8 h1_m, h1_n;
1373 s8 v0_m, v0_n;
1374 s8 v1_m, v1_n;
1375 };
1376
1377 const struct accu *accu_table;
1378 const struct accu *accu_val;
1379
1380 static const struct accu accu_nv12[4] = {
1381 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1382 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1383 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1384 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1385 };
1386
1387 static const struct accu accu_nv12_ilace[4] = {
1388 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1389 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1390 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1391 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1392 };
1393
1394 static const struct accu accu_yuv[4] = {
1395 { 0, 1, 0, 1, 0, 1, 0, 1 },
1396 { 0, 1, 0, 1, 0, 1, 0, 1 },
1397 { -1, 1, 0, 1, 0, 1, 0, 1 },
1398 { 0, 1, 0, 1, -1, 1, 0, 1 },
1399 };
1400
1401 switch (rotation) {
1402 case OMAP_DSS_ROT_0:
1403 idx = 0;
1404 break;
1405 case OMAP_DSS_ROT_90:
1406 idx = 1;
1407 break;
1408 case OMAP_DSS_ROT_180:
1409 idx = 2;
1410 break;
1411 case OMAP_DSS_ROT_270:
1412 idx = 3;
1413 break;
1414 default:
1415 BUG();
c6eee968 1416 return;
05dd0f53
CM		 1417 }
1418
1419 switch (color_mode) {
1420 case OMAP_DSS_COLOR_NV12:
1421 if (ilace)
1422 accu_table = accu_nv12_ilace;
1423 else
1424 accu_table = accu_nv12;
1425 break;
1426 case OMAP_DSS_COLOR_YUV2:
1427 case OMAP_DSS_COLOR_UYVY:
1428 accu_table = accu_yuv;
1429 break;
1430 default:
1431 BUG();
c6eee968 1432 return;
05dd0f53
CM		 1433 }
1434
1435 accu_val = &accu_table[idx];
1436
1437 chroma_hinc = 1024 * orig_width / out_width;
1438 chroma_vinc = 1024 * orig_height / out_height;
1439
1440 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1441 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1442 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1443 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1444
1445 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1446 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1447}
1448
f0e5caab 1449static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1450 u16 orig_width, u16 orig_height,
1451 u16 out_width, u16 out_height,
1452 bool ilace, bool five_taps,
1453 bool fieldmode, enum omap_color_mode color_mode,
1454 u8 rotation)
1455{
1456 int accu0 = 0;
1457 int accu1 = 0;
1458 u32 l;
80c39712 1459
f0e5caab 1460 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1461 out_width, out_height, five_taps,
1462 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1463 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1464
87a7484b
AT		 1465 /* RESIZEENABLE and VERTICALTAPS */
1466 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1467 l |= (orig_width != out_width) ? (1 << 5) : 0;
1468 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1469 l |= five_taps ? (1 << 21) : 0;
80c39712 1470
87a7484b
AT		 1471 /* VRESIZECONF and HRESIZECONF */
1472 if (dss_has_feature(FEAT_RESIZECONF)) {
1473 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1474 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1475 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1476 }
80c39712 1477
87a7484b
AT		 1478 /* LINEBUFFERSPLIT */
1479 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1480 l &= ~(0x1 << 22);
1481 l |= five_taps ? (1 << 22) : 0;
1482 }
80c39712 1483
9b372c2d 1484 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1485
1486 /*
1487 * field 0 = even field = bottom field
1488 * field 1 = odd field = top field
1489 */
1490 if (ilace && !fieldmode) {
1491 accu1 = 0;
0d66cbb5 1492 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1493 if (accu0 >= 1024/2) {
1494 accu1 = 1024/2;
1495 accu0 -= accu1;
1496 }
1497 }
1498
f0e5caab
TV		 1499 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1500 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1501}
1502
f0e5caab 1503static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1504 u16 orig_width, u16 orig_height,
1505 u16 out_width, u16 out_height,
1506 bool ilace, bool five_taps,
1507 bool fieldmode, enum omap_color_mode color_mode,
1508 u8 rotation)
1509{
1510 int scale_x = out_width != orig_width;
1511 int scale_y = out_height != orig_height;
f92afae2 1512 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1513
1514 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1515 return;
1516 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1517 color_mode != OMAP_DSS_COLOR_UYVY &&
1518 color_mode != OMAP_DSS_COLOR_NV12)) {
1519 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1520 if (plane != OMAP_DSS_WB)
1521 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1522 return;
1523 }
36377357
TV		 1524
1525 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1526 out_height, ilace, color_mode, rotation);
1527
0d66cbb5
AJ		 1528 switch (color_mode) {
1529 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1530 if (chroma_upscale) {
1531 /* UV is subsampled by 2 horizontally and vertically */
1532 orig_height >>= 1;
1533 orig_width >>= 1;
1534 } else {
1535 /* UV is downsampled by 2 horizontally and vertically */
1536 orig_height <<= 1;
1537 orig_width <<= 1;
1538 }
1539
0d66cbb5
AJ		 1540 break;
1541 case OMAP_DSS_COLOR_YUV2:
1542 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1543 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1544 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1545 rotation == OMAP_DSS_ROT_180) {
1546 if (chroma_upscale)
1547 /* UV is subsampled by 2 horizontally */
1548 orig_width >>= 1;
1549 else
1550 /* UV is downsampled by 2 horizontally */
1551 orig_width <<= 1;
1552 }
1553
0d66cbb5
AJ		 1554 /* must use FIR for YUV422 if rotated */
1555 if (rotation != OMAP_DSS_ROT_0)
1556 scale_x = scale_y = true;
20fbb50b 1557
0d66cbb5
AJ		 1558 break;
1559 default:
1560 BUG();
c6eee968 1561 return;
0d66cbb5
AJ		 1562 }
1563
1564 if (out_width != orig_width)
1565 scale_x = true;
1566 if (out_height != orig_height)
1567 scale_y = true;
1568
f0e5caab 1569 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1570 out_width, out_height, five_taps,
1571 rotation, DISPC_COLOR_COMPONENT_UV);
1572
2a5561b1
AT		 1573 if (plane != OMAP_DSS_WB)
1574 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1575 (scale_x || scale_y) ? 1 : 0, 8, 8);
1576
0d66cbb5
AJ		 1577 /* set H scaling */
1578 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1579 /* set V scaling */
1580 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1581}
1582
f0e5caab 1583static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1584 u16 orig_width, u16 orig_height,
1585 u16 out_width, u16 out_height,
1586 bool ilace, bool five_taps,
1587 bool fieldmode, enum omap_color_mode color_mode,
1588 u8 rotation)
1589{
1590 BUG_ON(plane == OMAP_DSS_GFX);
1591
f0e5caab 1592 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1593 orig_width, orig_height,
1594 out_width, out_height,
1595 ilace, five_taps,
1596 fieldmode, color_mode,
1597 rotation);
1598
f0e5caab 1599 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1600 orig_width, orig_height,
1601 out_width, out_height,
1602 ilace, five_taps,
1603 fieldmode, color_mode,
1604 rotation);
1605}
1606
f0e5caab 1607static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1608 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1609 bool mirroring, enum omap_color_mode color_mode)
1610{
87a7484b
AT		 1611 bool row_repeat = false;
1612 int vidrot = 0;
1613
80c39712
TV		 1614 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1615 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1616
1617 if (mirroring) {
1618 switch (rotation) {
1619 case OMAP_DSS_ROT_0:
1620 vidrot = 2;
1621 break;
1622 case OMAP_DSS_ROT_90:
1623 vidrot = 1;
1624 break;
1625 case OMAP_DSS_ROT_180:
1626 vidrot = 0;
1627 break;
1628 case OMAP_DSS_ROT_270:
1629 vidrot = 3;
1630 break;
1631 }
1632 } else {
1633 switch (rotation) {
1634 case OMAP_DSS_ROT_0:
1635 vidrot = 0;
1636 break;
1637 case OMAP_DSS_ROT_90:
1638 vidrot = 1;
1639 break;
1640 case OMAP_DSS_ROT_180:
1641 vidrot = 2;
1642 break;
1643 case OMAP_DSS_ROT_270:
1644 vidrot = 3;
1645 break;
1646 }
1647 }
1648
80c39712 1649 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1650 row_repeat = true;
80c39712 1651 else
87a7484b 1652 row_repeat = false;
80c39712 1653 }
87a7484b 1654
9b372c2d 1655 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1656 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1657 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1658 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1659
1660 if (color_mode == OMAP_DSS_COLOR_NV12) {
1661 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1662 (rotation == OMAP_DSS_ROT_0 ||
1663 rotation == OMAP_DSS_ROT_180);
1664 /* DOUBLESTRIDE */
1665 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1666 }
1667
80c39712
TV		 1668}
1669
1670static int color_mode_to_bpp(enum omap_color_mode color_mode)
1671{
1672 switch (color_mode) {
1673 case OMAP_DSS_COLOR_CLUT1:
1674 return 1;
1675 case OMAP_DSS_COLOR_CLUT2:
1676 return 2;
1677 case OMAP_DSS_COLOR_CLUT4:
1678 return 4;
1679 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1680 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1681 return 8;
1682 case OMAP_DSS_COLOR_RGB12U:
1683 case OMAP_DSS_COLOR_RGB16:
1684 case OMAP_DSS_COLOR_ARGB16:
1685 case OMAP_DSS_COLOR_YUV2:
1686 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1687 case OMAP_DSS_COLOR_RGBA16:
1688 case OMAP_DSS_COLOR_RGBX16:
1689 case OMAP_DSS_COLOR_ARGB16_1555:
1690 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1691 return 16;
1692 case OMAP_DSS_COLOR_RGB24P:
1693 return 24;
1694 case OMAP_DSS_COLOR_RGB24U:
1695 case OMAP_DSS_COLOR_ARGB32:
1696 case OMAP_DSS_COLOR_RGBA32:
1697 case OMAP_DSS_COLOR_RGBX32:
1698 return 32;
1699 default:
1700 BUG();
c6eee968 1701 return 0;
80c39712
TV		 1702 }
1703}
1704
1705static s32 pixinc(int pixels, u8 ps)
1706{
1707 if (pixels == 1)
1708 return 1;
1709 else if (pixels > 1)
1710 return 1 + (pixels - 1) * ps;
1711 else if (pixels < 0)
1712 return 1 - (-pixels + 1) * ps;
1713 else
1714 BUG();
c6eee968 1715 return 0;
80c39712
TV		 1716}
1717
1718static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1719 u16 screen_width,
1720 u16 width, u16 height,
1721 enum omap_color_mode color_mode, bool fieldmode,
1722 unsigned int field_offset,
1723 unsigned *offset0, unsigned *offset1,
aed74b55 1724 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1725{
1726 u8 ps;
1727
1728 /* FIXME CLUT formats */
1729 switch (color_mode) {
1730 case OMAP_DSS_COLOR_CLUT1:
1731 case OMAP_DSS_COLOR_CLUT2:
1732 case OMAP_DSS_COLOR_CLUT4:
1733 case OMAP_DSS_COLOR_CLUT8:
1734 BUG();
1735 return;
1736 case OMAP_DSS_COLOR_YUV2:
1737 case OMAP_DSS_COLOR_UYVY:
1738 ps = 4;
1739 break;
1740 default:
1741 ps = color_mode_to_bpp(color_mode) / 8;
1742 break;
1743 }
1744
1745 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1746 width, height);
1747
1748 /*
1749 * field 0 = even field = bottom field
1750 * field 1 = odd field = top field
1751 */
1752 switch (rotation + mirror * 4) {
1753 case OMAP_DSS_ROT_0:
1754 case OMAP_DSS_ROT_180:
1755 /*
1756 * If the pixel format is YUV or UYVY divide the width
1757 * of the image by 2 for 0 and 180 degree rotation.
1758 */
1759 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1760 color_mode == OMAP_DSS_COLOR_UYVY)
1761 width = width >> 1;
1762 case OMAP_DSS_ROT_90:
1763 case OMAP_DSS_ROT_270:
1764 *offset1 = 0;
1765 if (field_offset)
1766 *offset0 = field_offset * screen_width * ps;
1767 else
1768 *offset0 = 0;
1769
aed74b55
CM		 1770 *row_inc = pixinc(1 +
1771 (y_predecim * screen_width - x_predecim * width) +
1772 (fieldmode ? screen_width : 0), ps);
1773 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1774 break;
1775
1776 case OMAP_DSS_ROT_0 + 4:
1777 case OMAP_DSS_ROT_180 + 4:
1778 /* If the pixel format is YUV or UYVY divide the width
1779 * of the image by 2 for 0 degree and 180 degree
1780 */
1781 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1782 color_mode == OMAP_DSS_COLOR_UYVY)
1783 width = width >> 1;
1784 case OMAP_DSS_ROT_90 + 4:
1785 case OMAP_DSS_ROT_270 + 4:
1786 *offset1 = 0;
1787 if (field_offset)
1788 *offset0 = field_offset * screen_width * ps;
1789 else
1790 *offset0 = 0;
aed74b55
CM		 1791 *row_inc = pixinc(1 -
1792 (y_predecim * screen_width + x_predecim * width) -
1793 (fieldmode ? screen_width : 0), ps);
1794 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1795 break;
1796
1797 default:
1798 BUG();
c6eee968 1799 return;
80c39712
TV		 1800 }
1801}
1802
1803static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1804 u16 screen_width,
1805 u16 width, u16 height,
1806 enum omap_color_mode color_mode, bool fieldmode,
1807 unsigned int field_offset,
1808 unsigned *offset0, unsigned *offset1,
aed74b55 1809 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1810{
1811 u8 ps;
1812 u16 fbw, fbh;
1813
1814 /* FIXME CLUT formats */
1815 switch (color_mode) {
1816 case OMAP_DSS_COLOR_CLUT1:
1817 case OMAP_DSS_COLOR_CLUT2:
1818 case OMAP_DSS_COLOR_CLUT4:
1819 case OMAP_DSS_COLOR_CLUT8:
1820 BUG();
1821 return;
1822 default:
1823 ps = color_mode_to_bpp(color_mode) / 8;
1824 break;
1825 }
1826
1827 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1828 width, height);
1829
1830 /* width & height are overlay sizes, convert to fb sizes */
1831
1832 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1833 fbw = width;
1834 fbh = height;
1835 } else {
1836 fbw = height;
1837 fbh = width;
1838 }
1839
1840 /*
1841 * field 0 = even field = bottom field
1842 * field 1 = odd field = top field
1843 */
1844 switch (rotation + mirror * 4) {
1845 case OMAP_DSS_ROT_0:
1846 *offset1 = 0;
1847 if (field_offset)
1848 *offset0 = *offset1 + field_offset * screen_width * ps;
1849 else
1850 *offset0 = *offset1;
aed74b55
CM		 1851 *row_inc = pixinc(1 +
1852 (y_predecim * screen_width - fbw * x_predecim) +
1853 (fieldmode ? screen_width : 0), ps);
1854 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1855 color_mode == OMAP_DSS_COLOR_UYVY)
1856 *pix_inc = pixinc(x_predecim, 2 * ps);
1857 else
1858 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1859 break;
1860 case OMAP_DSS_ROT_90:
1861 *offset1 = screen_width * (fbh - 1) * ps;
1862 if (field_offset)
1863 *offset0 = *offset1 + field_offset * ps;
1864 else
1865 *offset0 = *offset1;
aed74b55
CM		 1866 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1867 y_predecim + (fieldmode ? 1 : 0), ps);
1868 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1869 break;
1870 case OMAP_DSS_ROT_180:
1871 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1872 if (field_offset)
1873 *offset0 = *offset1 - field_offset * screen_width * ps;
1874 else
1875 *offset0 = *offset1;
1876 *row_inc = pixinc(-1 -
aed74b55
CM		 1877 (y_predecim * screen_width - fbw * x_predecim) -
1878 (fieldmode ? screen_width : 0), ps);
1879 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1880 color_mode == OMAP_DSS_COLOR_UYVY)
1881 *pix_inc = pixinc(-x_predecim, 2 * ps);
1882 else
1883 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1884 break;
1885 case OMAP_DSS_ROT_270:
1886 *offset1 = (fbw - 1) * ps;
1887 if (field_offset)
1888 *offset0 = *offset1 - field_offset * ps;
1889 else
1890 *offset0 = *offset1;
aed74b55
CM		 1891 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1892 y_predecim - (fieldmode ? 1 : 0), ps);
1893 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1894 break;
1895
1896 /* mirroring */
1897 case OMAP_DSS_ROT_0 + 4:
1898 *offset1 = (fbw - 1) * ps;
1899 if (field_offset)
1900 *offset0 = *offset1 + field_offset * screen_width * ps;
1901 else
1902 *offset0 = *offset1;
aed74b55 1903 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1904 (fieldmode ? screen_width : 0),
1905 ps);
aed74b55
CM		 1906 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1907 color_mode == OMAP_DSS_COLOR_UYVY)
1908 *pix_inc = pixinc(-x_predecim, 2 * ps);
1909 else
1910 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1911 break;
1912
1913 case OMAP_DSS_ROT_90 + 4:
1914 *offset1 = 0;
1915 if (field_offset)
1916 *offset0 = *offset1 + field_offset * ps;
1917 else
1918 *offset0 = *offset1;
aed74b55
CM		 1919 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1920 y_predecim + (fieldmode ? 1 : 0),
80c39712 1921 ps);
aed74b55 1922 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1923 break;
1924
1925 case OMAP_DSS_ROT_180 + 4:
1926 *offset1 = screen_width * (fbh - 1) * ps;
1927 if (field_offset)
1928 *offset0 = *offset1 - field_offset * screen_width * ps;
1929 else
1930 *offset0 = *offset1;
aed74b55 1931 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1932 (fieldmode ? screen_width : 0),
1933 ps);
aed74b55
CM		 1934 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1935 color_mode == OMAP_DSS_COLOR_UYVY)
1936 *pix_inc = pixinc(x_predecim, 2 * ps);
1937 else
1938 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1939 break;
1940
1941 case OMAP_DSS_ROT_270 + 4:
1942 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1943 if (field_offset)
1944 *offset0 = *offset1 - field_offset * ps;
1945 else
1946 *offset0 = *offset1;
aed74b55
CM		 1947 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1948 y_predecim - (fieldmode ? 1 : 0),
80c39712 1949 ps);
aed74b55 1950 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1951 break;
1952
1953 default:
1954 BUG();
c6eee968 1955 return;
80c39712
TV		 1956 }
1957}
1958
65e006ff
CM		 1959static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1960 enum omap_color_mode color_mode, bool fieldmode,
1961 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1962 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1963{
1964 u8 ps;
1965
1966 switch (color_mode) {
1967 case OMAP_DSS_COLOR_CLUT1:
1968 case OMAP_DSS_COLOR_CLUT2:
1969 case OMAP_DSS_COLOR_CLUT4:
1970 case OMAP_DSS_COLOR_CLUT8:
1971 BUG();
1972 return;
1973 default:
1974 ps = color_mode_to_bpp(color_mode) / 8;
1975 break;
1976 }
1977
1978 DSSDBG("scrw %d, width %d\n", screen_width, width);
1979
1980 /*
1981 * field 0 = even field = bottom field
1982 * field 1 = odd field = top field
1983 */
1984 *offset1 = 0;
1985 if (field_offset)
1986 *offset0 = *offset1 + field_offset * screen_width * ps;
1987 else
1988 *offset0 = *offset1;
1989 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1990 (fieldmode ? screen_width : 0), ps);
1991 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1992 color_mode == OMAP_DSS_COLOR_UYVY)
1993 *pix_inc = pixinc(x_predecim, 2 * ps);
1994 else
1995 *pix_inc = pixinc(x_predecim, ps);
1996}
1997
7faa9233
CM		 1998/*
1999 * This function is used to avoid synclosts in OMAP3, because of some
2000 * undocumented horizontal position and timing related limitations.
2001 */
465ec13f 2002static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 2003 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 2004 u16 width, u16 height, u16 out_width, u16 out_height,
2005 bool five_taps)
7faa9233 2006{
230edc03 2007 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2008 unsigned long nonactive;
7faa9233
CM		 2009 static const u8 limits[3] = { 8, 10, 20 };
2010 u64 val, blank;
2011 int i;
2012
81ab95b7 2013 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2014
2015 i = 0;
2016 if (out_height < height)
2017 i++;
2018 if (out_width < width)
2019 i++;
81ab95b7 2020 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2021 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2022 if (blank <= limits[i])
2023 return -EINVAL;
2024
e4998634
ID		 2025 /* FIXME add checks for 3-tap filter once the limitations are known */
2026 if (!five_taps)
2027 return 0;
2028
7faa9233
CM		 2029 /*
2030 * Pixel data should be prepared before visible display point starts.
2031 * So, atleast DS-2 lines must have already been fetched by DISPC
2032 * during nonactive - pos_x period.
2033 */
2034 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2035 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2036 val, max(0, ds - 2) * width);
2037 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2038 return -EINVAL;
2039
2040 /*
2041 * All lines need to be refilled during the nonactive period of which
2042 * only one line can be loaded during the active period. So, atleast
2043 * DS - 1 lines should be loaded during nonactive period.
2044 */
2045 val = div_u64((u64)nonactive * lclk, pclk);
2046 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2047 val, max(0, ds - 1) * width);
2048 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2049 return -EINVAL;
2050
2051 return 0;
2052}
2053
8702ee50 2054static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2055 const struct omap_video_timings *mgr_timings, u16 width,
2056 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2057 enum omap_color_mode color_mode)
80c39712 2058{
8b53d991 2059 u32 core_clk = 0;
3e8a6ff2 2060 u64 tmp;
80c39712 2061
7282f1b7
CM		 2062 if (height <= out_height && width <= out_width)
2063 return (unsigned long) pclk;
2064
80c39712 2065 if (height > out_height) {
81ab95b7 2066 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2067
2068 tmp = pclk * height * out_width;
2069 do_div(tmp, 2 * out_height * ppl);
8b53d991 2070 core_clk = tmp;
80c39712 2071
2d9c5597
VS		 2072 if (height > 2 * out_height) {
2073 if (ppl == out_width)
2074 return 0;
2075
80c39712
TV		 2076 tmp = pclk * (height - 2 * out_height) * out_width;
2077 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2078 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2079 }
2080 }
2081
2082 if (width > out_width) {
2083 tmp = pclk * width;
2084 do_div(tmp, out_width);
8b53d991 2085 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2086
2087 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2088 core_clk <<= 1;
80c39712
TV		 2089 }
2090
8b53d991 2091 return core_clk;
80c39712
TV		 2092}
2093
8702ee50 2094static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2095 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2096{
dcbe765b
CM		 2097 if (height > out_height && width > out_width)
2098 return pclk * 4;
2099 else
2100 return pclk * 2;
2101}
2102
8702ee50 2103static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2104 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2105{
2106 unsigned int hf, vf;
2107
2108 /*
2109 * FIXME how to determine the 'A' factor
2110 * for the no downscaling case ?
2111 */
2112
2113 if (width > 3 * out_width)
2114 hf = 4;
2115 else if (width > 2 * out_width)
2116 hf = 3;
2117 else if (width > out_width)
2118 hf = 2;
2119 else
2120 hf = 1;
80c39712
TV		 2121 if (height > out_height)
2122 vf = 2;
2123 else
2124 vf = 1;
2125
dcbe765b
CM		 2126 return pclk * vf * hf;
2127}
2128
8702ee50 2129static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2130 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2131{
8ba85306
AT		 2132 /*
2133 * If the overlay/writeback is in mem to mem mode, there are no
2134 * downscaling limitations with respect to pixel clock, return 1 as
2135 * required core clock to represent that we have sufficient enough
2136 * core clock to do maximum downscaling
2137 */
2138 if (mem_to_mem)
2139 return 1;
2140
dcbe765b
CM		 2141 if (width > out_width)
2142 return DIV_ROUND_UP(pclk, out_width) * width;
2143 else
2144 return pclk;
2145}
2146
0c6921de 2147static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2148 const struct omap_video_timings *mgr_timings,
2149 u16 width, u16 height, u16 out_width, u16 out_height,
2150 enum omap_color_mode color_mode, bool *five_taps,
2151 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2152 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2153{
2154 int error;
2155 u16 in_width, in_height;
2156 int min_factor = min(*decim_x, *decim_y);
2157 const int maxsinglelinewidth =
2158 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2159
dcbe765b
CM		 2160 *five_taps = false;
2161
2162 do {
2163 in_height = DIV_ROUND_UP(height, *decim_y);
2164 in_width = DIV_ROUND_UP(width, *decim_x);
8702ee50 2165 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2166 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2167 error = (in_width > maxsinglelinewidth || !*core_clk ||
2168 *core_clk > dispc_core_clk_rate());
2169 if (error) {
2170 if (*decim_x == *decim_y) {
2171 *decim_x = min_factor;
2172 ++*decim_y;
2173 } else {
2174 swap(*decim_x, *decim_y);
2175 if (*decim_x < *decim_y)
2176 ++*decim_x;
2177 }
2178 }
2179 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2180
2181 if (in_width > maxsinglelinewidth) {
2182 DSSERR("Cannot scale max input width exceeded");
2183 return -EINVAL;
2184 }
2185 return 0;
2186}
2187
0c6921de 2188static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2189 const struct omap_video_timings *mgr_timings,
2190 u16 width, u16 height, u16 out_width, u16 out_height,
2191 enum omap_color_mode color_mode, bool *five_taps,
2192 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2193 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2194{
2195 int error;
2196 u16 in_width, in_height;
2197 int min_factor = min(*decim_x, *decim_y);
2198 const int maxsinglelinewidth =
2199 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2200
2201 do {
2202 in_height = DIV_ROUND_UP(height, *decim_y);
2203 in_width = DIV_ROUND_UP(width, *decim_x);
e4998634 2204 *five_taps = in_height > out_height;
dcbe765b
CM		 2205
2206 if (in_width > maxsinglelinewidth)
2207 if (in_height > out_height &&
2208 in_height < out_height * 2)
2209 *five_taps = false;
e4998634
ID		 2210again:
2211 if (*five_taps)
2212 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2213 in_width, in_height, out_width,
2214 out_height, color_mode);
2215 else
8702ee50 2216 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2217 in_height, out_width, out_height,
2218 mem_to_mem);
dcbe765b 2219
e4998634
ID		 2220 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2221 pos_x, in_width, in_height, out_width,
2222 out_height, *five_taps);
2223 if (error && *five_taps) {
2224 *five_taps = false;
2225 goto again;
2226 }
2227
dcbe765b
CM		 2228 error = (error || in_width > maxsinglelinewidth * 2 ||
2229 (in_width > maxsinglelinewidth && *five_taps) ||
2230 !*core_clk || *core_clk > dispc_core_clk_rate());
2231 if (error) {
2232 if (*decim_x == *decim_y) {
2233 *decim_x = min_factor;
2234 ++*decim_y;
2235 } else {
2236 swap(*decim_x, *decim_y);
2237 if (*decim_x < *decim_y)
2238 ++*decim_x;
2239 }
2240 }
2241 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2242
465ec13f 2243 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
e4998634 2244 height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2245 DSSERR("horizontal timing too tight\n");
2246 return -EINVAL;
7282f1b7 2247 }
dcbe765b
CM		 2248
2249 if (in_width > (maxsinglelinewidth * 2)) {
2250 DSSERR("Cannot setup scaling");
2251 DSSERR("width exceeds maximum width possible");
2252 return -EINVAL;
2253 }
2254
2255 if (in_width > maxsinglelinewidth && *five_taps) {
2256 DSSERR("cannot setup scaling with five taps");
2257 return -EINVAL;
2258 }
2259 return 0;
2260}
2261
0c6921de 2262static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2263 const struct omap_video_timings *mgr_timings,
2264 u16 width, u16 height, u16 out_width, u16 out_height,
2265 enum omap_color_mode color_mode, bool *five_taps,
2266 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2267 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2268{
2269 u16 in_width, in_width_max;
2270 int decim_x_min = *decim_x;
2271 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2272 const int maxsinglelinewidth =
2273 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2274 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2275
5d501085
AT		 2276 if (mem_to_mem) {
2277 in_width_max = out_width * maxdownscale;
2278 } else {
8ba85306
AT		 2279 in_width_max = dispc_core_clk_rate() /
2280 DIV_ROUND_UP(pclk, out_width);
5d501085 2281 }
dcbe765b 2282
dcbe765b
CM		 2283 *decim_x = DIV_ROUND_UP(width, in_width_max);
2284
2285 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2286 if (*decim_x > *x_predecim)
2287 return -EINVAL;
2288
2289 do {
2290 in_width = DIV_ROUND_UP(width, *decim_x);
2291 } while (*decim_x <= *x_predecim &&
2292 in_width > maxsinglelinewidth && ++*decim_x);
2293
2294 if (in_width > maxsinglelinewidth) {
2295 DSSERR("Cannot scale width exceeds max line width");
2296 return -EINVAL;
2297 }
2298
8702ee50 2299 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2300 out_width, out_height, mem_to_mem);
dcbe765b 2301 return 0;
80c39712
TV		 2302}
2303
74e16458 2304static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2305 enum omap_overlay_caps caps,
81ab95b7
AT		 2306 const struct omap_video_timings *mgr_timings,
2307 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2308 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2309 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2310 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2311{
0373cac6 2312 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2313 const int max_decim_limit = 16;
8b53d991 2314 unsigned long core_clk = 0;
dcbe765b 2315 int decim_x, decim_y, ret;
79ad75f2 2316
f95cb5eb
TV		 2317 if (width == out_width && height == out_height)
2318 return 0;
2319
5b54ed3e 2320 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2321 return -EINVAL;
79ad75f2 2322
74e16458 2323 if (mem_to_mem) {
1c031441
AT		 2324 *x_predecim = *y_predecim = 1;
2325 } else {
2326 *x_predecim = max_decim_limit;
2327 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2328 dss_has_feature(FEAT_BURST_2D)) ?
2329 2 : max_decim_limit;
2330 }
aed74b55
CM		 2331
2332 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2333 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2334 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2335 color_mode == OMAP_DSS_COLOR_CLUT8) {
2336 *x_predecim = 1;
2337 *y_predecim = 1;
2338 *five_taps = false;
2339 return 0;
2340 }
2341
2342 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2343 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2344
aed74b55 2345 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2346 return -EINVAL;
2347
aed74b55 2348 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2349 return -EINVAL;
2350
0c6921de 2351 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2352 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2353 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2354 mem_to_mem);
dcbe765b
CM		 2355 if (ret)
2356 return ret;
79ad75f2 2357
8b53d991
CM		 2358 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2359 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2360
8b53d991 2361 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2362 DSSERR("failed to set up scaling, "
8b53d991
CM		 2363 "required core clk rate = %lu Hz, "
2364 "current core clk rate = %lu Hz\n",
2365 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2366 return -EINVAL;
2367 }
2368
aed74b55
CM		 2369 *x_predecim = decim_x;
2370 *y_predecim = decim_y;
79ad75f2
AT		 2371 return 0;
2372}
2373
f9b719b6
TV		 2374int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2375 const struct omap_overlay_info *oi,
2376 const struct omap_video_timings *timings,
2377 int *x_predecim, int *y_predecim)
2378{
2379 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2380 bool five_taps = true;
62a83183 2381 bool fieldmode = false;
f9b719b6
TV		 2382 u16 in_height = oi->height;
2383 u16 in_width = oi->width;
2384 bool ilace = timings->interlace;
2385 u16 out_width, out_height;
2386 int pos_x = oi->pos_x;
2387 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2388 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2389
2390 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2391 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2392
2393 if (ilace && oi->height == out_height)
62a83183 2394 fieldmode = true;
f9b719b6
TV		 2395
2396 if (ilace) {
2397 if (fieldmode)
2398 in_height /= 2;
2399 out_height /= 2;
2400
2401 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2402 in_height, out_height);
2403 }
2404
2405 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2406 return -EINVAL;
2407
2408 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2409 in_height, out_width, out_height, oi->color_mode,
2410 &five_taps, x_predecim, y_predecim, pos_x,
2411 oi->rotation_type, false);
2412}
348be69d 2413EXPORT_SYMBOL(dispc_ovl_check);
f9b719b6 2414
84a880fd 2415static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2416 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2417 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2418 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2419 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2420 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2421 bool replication, const struct omap_video_timings *mgr_timings,
2422 bool mem_to_mem)
80c39712 2423{
7282f1b7 2424 bool five_taps = true;
62a83183 2425 bool fieldmode = false;
79ad75f2 2426 int r, cconv = 0;
80c39712
TV		 2427 unsigned offset0, offset1;
2428 s32 row_inc;
2429 s32 pix_inc;
6be0d73e 2430 u16 frame_width, frame_height;
80c39712 2431 unsigned int field_offset = 0;
84a880fd
AT		 2432 u16 in_height = height;
2433 u16 in_width = width;
aed74b55 2434 int x_predecim = 1, y_predecim = 1;
8050cbe4 2435 bool ilace = mgr_timings->interlace;
74e16458
TV		 2436 unsigned long pclk = dispc_plane_pclk_rate(plane);
2437 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2438
84a880fd 2439 if (paddr == 0)
80c39712
TV		 2440 return -EINVAL;
2441
84a880fd
AT		 2442 out_width = out_width == 0 ? width : out_width;
2443 out_height = out_height == 0 ? height : out_height;
cf073668 2444
84a880fd 2445 if (ilace && height == out_height)
62a83183 2446 fieldmode = true;
80c39712
TV		 2447
2448 if (ilace) {
2449 if (fieldmode)
aed74b55 2450 in_height /= 2;
8eeb7019 2451 pos_y /= 2;
aed74b55 2452 out_height /= 2;
80c39712
TV		 2453
2454 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2455 "out_height %d\n", in_height, pos_y,
2456 out_height);
80c39712
TV		 2457 }
2458
84a880fd 2459 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2460 return -EINVAL;
2461
74e16458 2462 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2463 in_height, out_width, out_height, color_mode,
2464 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2465 rotation_type, mem_to_mem);
79ad75f2
AT		 2466 if (r)
2467 return r;
80c39712 2468
aed74b55
CM		 2469 in_width = DIV_ROUND_UP(in_width, x_predecim);
2470 in_height = DIV_ROUND_UP(in_height, y_predecim);
2471
84a880fd
AT		 2472 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2473 color_mode == OMAP_DSS_COLOR_UYVY ||
2474 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2475 cconv = 1;
80c39712
TV		 2476
2477 if (ilace && !fieldmode) {
2478 /*
2479 * when downscaling the bottom field may have to start several
2480 * source lines below the top field. Unfortunately ACCUI
2481 * registers will only hold the fractional part of the offset
2482 * so the integer part must be added to the base address of the
2483 * bottom field.
2484 */
aed74b55 2485 if (!in_height || in_height == out_height)
80c39712
TV		 2486 field_offset = 0;
2487 else
aed74b55 2488 field_offset = in_height / out_height / 2;
80c39712
TV		 2489 }
2490
2491 /* Fields are independent but interleaved in memory. */
2492 if (fieldmode)
2493 field_offset = 1;
2494
c6eee968
TV		 2495 offset0 = 0;
2496 offset1 = 0;
2497 row_inc = 0;
2498 pix_inc = 0;
2499
6be0d73e
AT		 2500 if (plane == OMAP_DSS_WB) {
2501 frame_width = out_width;
2502 frame_height = out_height;
2503 } else {
2504 frame_width = in_width;
2505 frame_height = height;
2506 }
2507
84a880fd 2508 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2509 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2510 color_mode, fieldmode, field_offset,
65e006ff
CM		 2511 &offset0, &offset1, &row_inc, &pix_inc,
2512 x_predecim, y_predecim);
84a880fd 2513 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2514 calc_dma_rotation_offset(rotation, mirror, screen_width,
2515 frame_width, frame_height,
84a880fd 2516 color_mode, fieldmode, field_offset,
aed74b55
CM		 2517 &offset0, &offset1, &row_inc, &pix_inc,
2518 x_predecim, y_predecim);
80c39712 2519 else
84a880fd 2520 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2521 screen_width, frame_width, frame_height,
84a880fd 2522 color_mode, fieldmode, field_offset,
aed74b55
CM		 2523 &offset0, &offset1, &row_inc, &pix_inc,
2524 x_predecim, y_predecim);
80c39712
TV		 2525
2526 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2527 offset0, offset1, row_inc, pix_inc);
2528
84a880fd 2529 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2530
84a880fd 2531 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2532
84a880fd
AT		 2533 dispc_ovl_set_ba0(plane, paddr + offset0);
2534 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2535
84a880fd
AT		 2536 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2537 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2538 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2539 }
2540
f0e5caab
TV		 2541 dispc_ovl_set_row_inc(plane, row_inc);
2542 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2543
84a880fd 2544 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2545 in_height, out_width, out_height);
80c39712 2546
84a880fd 2547 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2548
78b687fc 2549 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2550
5b54ed3e 2551 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2552 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2553 out_height, ilace, five_taps, fieldmode,
84a880fd 2554 color_mode, rotation);
78b687fc 2555 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2556 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2557 }
2558
c35eeb2e
AT		 2559 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2560 color_mode);
80c39712 2561
84a880fd
AT		 2562 dispc_ovl_set_zorder(plane, caps, zorder);
2563 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2564 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2565
d79db853 2566 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2567
80c39712
TV		 2568 return 0;
2569}
2570
84a880fd 2571int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2572 bool replication, const struct omap_video_timings *mgr_timings,
2573 bool mem_to_mem)
84a880fd
AT		 2574{
2575 int r;
16bf20c7 2576 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2577 enum omap_channel channel;
2578
2579 channel = dispc_ovl_get_channel_out(plane);
2580
2581 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2582 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2583 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2584 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2585 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2586
16bf20c7 2587 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2588 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2589 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2590 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2591 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2592
2593 return r;
2594}
348be69d 2595EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2596
749feffa 2597int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2598 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2599{
2600 int r;
9e4a0fc7 2601 u32 l;
749feffa
AT		 2602 enum omap_plane plane = OMAP_DSS_WB;
2603 const int pos_x = 0, pos_y = 0;
2604 const u8 zorder = 0, global_alpha = 0;
2605 const bool replication = false;
9e4a0fc7 2606 bool truncation;
749feffa
AT		 2607 int in_width = mgr_timings->x_res;
2608 int in_height = mgr_timings->y_res;
2609 enum omap_overlay_caps caps =
2610 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2611
2612 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2613 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2614 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2615 wi->mirror);
2616
2617 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2618 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2619 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2620 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2621 replication, mgr_timings, mem_to_mem);
2622
2623 switch (wi->color_mode) {
2624 case OMAP_DSS_COLOR_RGB16:
2625 case OMAP_DSS_COLOR_RGB24P:
2626 case OMAP_DSS_COLOR_ARGB16:
2627 case OMAP_DSS_COLOR_RGBA16:
2628 case OMAP_DSS_COLOR_RGB12U:
2629 case OMAP_DSS_COLOR_ARGB16_1555:
2630 case OMAP_DSS_COLOR_XRGB16_1555:
2631 case OMAP_DSS_COLOR_RGBX16:
2632 truncation = true;
2633 break;
2634 default:
2635 truncation = false;
2636 break;
2637 }
2638
2639 /* setup extra DISPC_WB_ATTRIBUTES */
2640 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2641 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2642 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2643 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2644
2645 return r;
2646}
2647
f0e5caab 2648int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2649{
e6d80f95
TV		 2650 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2651
9b372c2d 2652 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2653
2654 return 0;
80c39712 2655}
348be69d 2656EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2657
04bd8ac1
TV		 2658bool dispc_ovl_enabled(enum omap_plane plane)
2659{
2660 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2661}
348be69d 2662EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2663
f1a813d3 2664void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2665{
efa70b3b
CM		 2666 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2667 /* flush posted write */
2668 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2669}
348be69d 2670EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2671
65398511
TV		 2672bool dispc_mgr_is_enabled(enum omap_channel channel)
2673{
2674 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2675}
348be69d 2676EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2677
0b23e5b8
AT		 2678void dispc_wb_enable(bool enable)
2679{
916188a4 2680 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2681}
2682
2683bool dispc_wb_is_enabled(void)
2684{
916188a4 2685 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2686}
2687
fb2cec1f 2688static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2689{
6ced40bf
AT		 2690 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2691 return;
2692
80c39712 2693 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2694}
2695
2696void dispc_lcd_enable_signal(bool enable)
2697{
6ced40bf
AT		 2698 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2699 return;
2700
80c39712 2701 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2702}
2703
2704void dispc_pck_free_enable(bool enable)
2705{
6ced40bf
AT		 2706 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2707 return;
2708
80c39712 2709 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2710}
2711
fb2cec1f 2712static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2713{
efa70b3b 2714 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2715}
2716
2717
fb2cec1f 2718static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2719{
d21f43bc 2720 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2721}
2722
2723void dispc_set_loadmode(enum omap_dss_load_mode mode)
2724{
80c39712 2725 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2726}
2727
2728
c64dca40 2729static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2730{
8613b000 2731 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2732}
2733
c64dca40 2734static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2735 enum omap_dss_trans_key_type type,
2736 u32 trans_key)
2737{
efa70b3b 2738 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2739
8613b000 2740 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2741}
2742
c64dca40 2743static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2744{
efa70b3b 2745 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2746}
11354dd5 2747
c64dca40
TV		 2748static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2749 bool enable)
80c39712 2750{
11354dd5 2751 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2752 return;
2753
80c39712
TV		 2754 if (ch == OMAP_DSS_CHANNEL_LCD)
2755 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2756 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2757 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2758}
11354dd5 2759
c64dca40 2760void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2761 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2762{
2763 dispc_mgr_set_default_color(channel, info->default_color);
2764 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2765 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2766 dispc_mgr_enable_alpha_fixed_zorder(channel,
2767 info->partial_alpha_enabled);
2768 if (dss_has_feature(FEAT_CPR)) {
2769 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2770 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2771 }
2772}
348be69d 2773EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 2774
fb2cec1f 2775static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2776{
2777 int code;
2778
2779 switch (data_lines) {
2780 case 12:
2781 code = 0;
2782 break;
2783 case 16:
2784 code = 1;
2785 break;
2786 case 18:
2787 code = 2;
2788 break;
2789 case 24:
2790 code = 3;
2791 break;
2792 default:
2793 BUG();
2794 return;
2795 }
2796
efa70b3b 2797 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2798}
2799
fb2cec1f 2800static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2801{
2802 u32 l;
569969d6 2803 int gpout0, gpout1;
80c39712
TV		 2804
2805 switch (mode) {
569969d6
AT		 2806 case DSS_IO_PAD_MODE_RESET:
2807 gpout0 = 0;
2808 gpout1 = 0;
80c39712 2809 break;
569969d6
AT		 2810 case DSS_IO_PAD_MODE_RFBI:
2811 gpout0 = 1;
80c39712
TV		 2812 gpout1 = 0;
2813 break;
569969d6
AT		 2814 case DSS_IO_PAD_MODE_BYPASS:
2815 gpout0 = 1;
80c39712
TV		 2816 gpout1 = 1;
2817 break;
80c39712
TV		 2818 default:
2819 BUG();
2820 return;
2821 }
2822
569969d6
AT		 2823 l = dispc_read_reg(DISPC_CONTROL);
2824 l = FLD_MOD(l, gpout0, 15, 15);
2825 l = FLD_MOD(l, gpout1, 16, 16);
2826 dispc_write_reg(DISPC_CONTROL, l);
2827}
2828
fb2cec1f 2829static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2830{
efa70b3b 2831 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2832}
2833
fb2cec1f
TV		 2834void dispc_mgr_set_lcd_config(enum omap_channel channel,
2835 const struct dss_lcd_mgr_config *config)
2836{
2837 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2838
2839 dispc_mgr_enable_stallmode(channel, config->stallmode);
2840 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2841
2842 dispc_mgr_set_clock_div(channel, &config->clock_info);
2843
2844 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2845
2846 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2847
2848 dispc_mgr_set_lcd_type_tft(channel);
2849}
348be69d 2850EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 2851
8f366162
AT		 2852static bool _dispc_mgr_size_ok(u16 width, u16 height)
2853{
33b89928
AT		 2854 return width <= dispc.feat->mgr_width_max &&
2855 height <= dispc.feat->mgr_height_max;
8f366162
AT		 2856}
2857
80c39712
TV		 2858static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2859 int vsw, int vfp, int vbp)
2860{
dcbe765b
CM		 2861 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2862 hfp < 1 || hfp > dispc.feat->hp_max ||
2863 hbp < 1 || hbp > dispc.feat->hp_max ||
2864 vsw < 1 || vsw > dispc.feat->sw_max ||
2865 vfp < 0 || vfp > dispc.feat->vp_max ||
2866 vbp < 0 || vbp > dispc.feat->vp_max)
2867 return false;
80c39712
TV		 2868 return true;
2869}
2870
ca5ca69c
AT		 2871static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2872 unsigned long pclk)
2873{
2874 if (dss_mgr_is_lcd(channel))
2875 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2876 else
2877 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2878}
2879
8f366162 2880bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2881 const struct omap_video_timings *timings)
80c39712 2882{
8f366162
AT		 2883 bool timings_ok;
2884
2885 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2886
ca5ca69c
AT		 2887 timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixel_clock * 1000);
2888
2889 if (dss_mgr_is_lcd(channel)) {
2890 timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2891 timings->hbp, timings->vsw, timings->vfp,
2892 timings->vbp);
2893 }
8f366162
AT		 2894
2895 return timings_ok;
80c39712
TV		 2896}
2897
26d9dd0d 2898static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2899 int hfp, int hbp, int vsw, int vfp, int vbp,
2900 enum omap_dss_signal_level vsync_level,
2901 enum omap_dss_signal_level hsync_level,
2902 enum omap_dss_signal_edge data_pclk_edge,
2903 enum omap_dss_signal_level de_level,
2904 enum omap_dss_signal_edge sync_pclk_edge)
2905
80c39712 2906{
655e2941
AT		 2907 u32 timing_h, timing_v, l;
2908 bool onoff, rf, ipc;
80c39712 2909
dcbe765b
CM		 2910 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2911 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2912 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2913 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2914 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2915 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 2916
64ba4f74
SS		 2917 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2918 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 2919
2920 switch (data_pclk_edge) {
2921 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2922 ipc = false;
2923 break;
2924 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2925 ipc = true;
2926 break;
2927 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2928 default:
2929 BUG();
2930 }
2931
2932 switch (sync_pclk_edge) {
2933 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2934 onoff = false;
2935 rf = false;
2936 break;
2937 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2938 onoff = true;
2939 rf = false;
2940 break;
2941 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2942 onoff = true;
2943 rf = true;
2944 break;
2945 default:
2946 BUG();
cf6ac4ce 2947 }
655e2941
AT		 2948
2949 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2950 l |= FLD_VAL(onoff, 17, 17);
2951 l |= FLD_VAL(rf, 16, 16);
2952 l |= FLD_VAL(de_level, 15, 15);
2953 l |= FLD_VAL(ipc, 14, 14);
2954 l |= FLD_VAL(hsync_level, 13, 13);
2955 l |= FLD_VAL(vsync_level, 12, 12);
2956 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2957}
2958
2959/* change name to mode? */
c51d921a 2960void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 2961 const struct omap_video_timings *timings)
80c39712
TV		 2962{
2963 unsigned xtot, ytot;
2964 unsigned long ht, vt;
2aefad49 2965 struct omap_video_timings t = *timings;
80c39712 2966
2aefad49 2967 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 2968
2aefad49 2969 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2970 BUG();
c6eee968
TV		 2971 return;
2972 }
80c39712 2973
dd88b7a6 2974 if (dss_mgr_is_lcd(channel)) {
2aefad49 2975 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 2976 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2977 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 2978
2aefad49
AT		 2979 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2980 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 2981
c51d921a
AT		 2982 ht = (timings->pixel_clock * 1000) / xtot;
2983 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2984
2985 DSSDBG("pck %u\n", timings->pixel_clock);
2986 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 2987 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 2988 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2989 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2990 t.de_level, t.sync_pclk_edge);
80c39712 2991
c51d921a 2992 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 2993 } else {
23c8f88e 2994 if (t.interlace == true)
2aefad49 2995 t.y_res /= 2;
c51d921a 2996 }
8f366162 2997
2aefad49 2998 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 2999}
348be69d 3000EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 3001
26d9dd0d 3002static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3003 u16 pck_div)
80c39712
TV		 3004{
3005 BUG_ON(lck_div < 1);
9eaaf207 3006 BUG_ON(pck_div < 1);
80c39712 3007
ce7fa5eb 3008 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3009 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3
TV		 3010
3011 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3012 channel == OMAP_DSS_CHANNEL_LCD)
3013 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3014}
3015
26d9dd0d 3016static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3017 int *pck_div)
80c39712
TV		 3018{
3019 u32 l;
ce7fa5eb 3020 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3021 *lck_div = FLD_GET(l, 23, 16);
3022 *pck_div = FLD_GET(l, 7, 0);
3023}
3024
3025unsigned long dispc_fclk_rate(void)
3026{
a72b64b9 3027 struct platform_device *dsidev;
80c39712
TV		 3028 unsigned long r = 0;
3029
66534e8e 3030 switch (dss_get_dispc_clk_source()) {
89a35e51 3031 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3032 r = dss_get_dispc_clk_rate();
66534e8e 3033 break;
89a35e51 3034 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3035 dsidev = dsi_get_dsidev_from_id(0);
3036 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 3037 break;
5a8b572d
AT		 3038 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3039 dsidev = dsi_get_dsidev_from_id(1);
3040 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3041 break;
66534e8e
TA		 3042 default:
3043 BUG();
c6eee968 3044 return 0;
66534e8e
TA		 3045 }
3046
80c39712
TV		 3047 return r;
3048}
3049
26d9dd0d 3050unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3051{
a72b64b9 3052 struct platform_device *dsidev;
80c39712
TV		 3053 int lcd;
3054 unsigned long r;
3055 u32 l;
3056
c31cba8a
TV		 3057 if (dss_mgr_is_lcd(channel)) {
3058 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3059
c31cba8a 3060 lcd = FLD_GET(l, 23, 16);
80c39712 3061
c31cba8a
TV		 3062 switch (dss_get_lcd_clk_source(channel)) {
3063 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3064 r = dss_get_dispc_clk_rate();
c31cba8a
TV		 3065 break;
3066 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3067 dsidev = dsi_get_dsidev_from_id(0);
3068 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3069 break;
3070 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3071 dsidev = dsi_get_dsidev_from_id(1);
3072 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3073 break;
3074 default:
3075 BUG();
3076 return 0;
3077 }
80c39712 3078
c31cba8a
TV		 3079 return r / lcd;
3080 } else {
3081 return dispc_fclk_rate();
3082 }
80c39712
TV		 3083}
3084
26d9dd0d 3085unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3086{
80c39712 3087 unsigned long r;
80c39712 3088
dd88b7a6 3089 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3090 int pcd;
3091 u32 l;
80c39712 3092
c3dc6a7a 3093 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3094
c3dc6a7a 3095 pcd = FLD_GET(l, 7, 0);
80c39712 3096
c3dc6a7a
AT		 3097 r = dispc_mgr_lclk_rate(channel);
3098
3099 return r / pcd;
3100 } else {
5391e87d 3101 return dispc.tv_pclk_rate;
c3dc6a7a 3102 }
80c39712
TV		 3103}
3104
5391e87d
TV		 3105void dispc_set_tv_pclk(unsigned long pclk)
3106{
3107 dispc.tv_pclk_rate = pclk;
3108}
3109
8b53d991
CM		 3110unsigned long dispc_core_clk_rate(void)
3111{
7b3926b3 3112 return dispc.core_clk_rate;
8b53d991
CM		 3113}
3114
3e8a6ff2
AT		 3115static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3116{
251886d8
TV		 3117 enum omap_channel channel;
3118
3119 if (plane == OMAP_DSS_WB)
3120 return 0;
3121
3122 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3123
3124 return dispc_mgr_pclk_rate(channel);
3125}
3126
3127static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3128{
251886d8
TV		 3129 enum omap_channel channel;
3130
3131 if (plane == OMAP_DSS_WB)
3132 return 0;
3133
3134 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3135
c31cba8a 3136 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3137}
c31cba8a 3138
6f1891fc 3139static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3140{
3141 int lcd, pcd;
6f1891fc
CM		 3142 enum omap_dss_clk_source lcd_clk_src;
3143
3144 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3145
3146 lcd_clk_src = dss_get_lcd_clk_source(channel);
3147
3148 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3149 dss_get_generic_clk_source_name(lcd_clk_src),
3150 dss_feat_get_clk_source_name(lcd_clk_src));
3151
3152 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3153
3154 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3155 dispc_mgr_lclk_rate(channel), lcd);
3156 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3157 dispc_mgr_pclk_rate(channel), pcd);
3158}
3159
3160void dispc_dump_clocks(struct seq_file *s)
3161{
3162 int lcd;
0cf35df3 3163 u32 l;
89a35e51 3164 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3165
4fbafaf3
TV		 3166 if (dispc_runtime_get())
3167 return;
80c39712 3168
80c39712
TV		 3169 seq_printf(s, "- DISPC -\n");
3170
067a57e4
AT		 3171 seq_printf(s, "dispc fclk source = %s (%s)\n",
3172 dss_get_generic_clk_source_name(dispc_clk_src),
3173 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3174
3175 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3176
0cf35df3
MR		 3177 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3178 seq_printf(s, "- DISPC-CORE-CLK -\n");
3179 l = dispc_read_reg(DISPC_DIVISOR);
3180 lcd = FLD_GET(l, 23, 16);
3181
3182 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3183 (dispc_fclk_rate()/lcd), lcd);
3184 }
2a205f34 3185
6f1891fc 3186 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3187
6f1891fc
CM		 3188 if (dss_has_feature(FEAT_MGR_LCD2))
3189 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3190 if (dss_has_feature(FEAT_MGR_LCD3))
3191 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3192
3193 dispc_runtime_put();
80c39712
TV		 3194}
3195
e40402cf 3196static void dispc_dump_regs(struct seq_file *s)
80c39712 3197{
4dd2da15
AT		 3198 int i, j;
3199 const char *mgr_names[] = {
3200 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3201 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3202 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3203 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3204 };
3205 const char *ovl_names[] = {
3206 [OMAP_DSS_GFX] = "GFX",
3207 [OMAP_DSS_VIDEO1] = "VID1",
3208 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3209 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3210 };
3211 const char **p_names;
3212
9b372c2d 3213#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3214
4fbafaf3
TV		 3215 if (dispc_runtime_get())
3216 return;
80c39712 3217
5010be80 3218 /* DISPC common registers */
80c39712
TV		 3219 DUMPREG(DISPC_REVISION);
3220 DUMPREG(DISPC_SYSCONFIG);
3221 DUMPREG(DISPC_SYSSTATUS);
3222 DUMPREG(DISPC_IRQSTATUS);
3223 DUMPREG(DISPC_IRQENABLE);
3224 DUMPREG(DISPC_CONTROL);
3225 DUMPREG(DISPC_CONFIG);
3226 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3227 DUMPREG(DISPC_LINE_STATUS);
3228 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3229 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3230 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3231 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3232 if (dss_has_feature(FEAT_MGR_LCD2)) {
3233 DUMPREG(DISPC_CONTROL2);
3234 DUMPREG(DISPC_CONFIG2);
5010be80 3235 }
6f1891fc
CM		 3236 if (dss_has_feature(FEAT_MGR_LCD3)) {
3237 DUMPREG(DISPC_CONTROL3);
3238 DUMPREG(DISPC_CONFIG3);
3239 }
29fceeeb
TV		 3240 if (dss_has_feature(FEAT_MFLAG))
3241 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3242
3243#undef DUMPREG
3244
3245#define DISPC_REG(i, name) name(i)
4dd2da15 3246#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3247 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3248 dispc_read_reg(DISPC_REG(i, r)))
3249
4dd2da15 3250 p_names = mgr_names;
5010be80 3251
4dd2da15
AT		 3252 /* DISPC channel specific registers */
3253 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3254 DUMPREG(i, DISPC_DEFAULT_COLOR);
3255 DUMPREG(i, DISPC_TRANS_COLOR);
3256 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3257
4dd2da15
AT		 3258 if (i == OMAP_DSS_CHANNEL_DIGIT)
3259 continue;
5010be80 3260
4dd2da15
AT		 3261 DUMPREG(i, DISPC_DEFAULT_COLOR);
3262 DUMPREG(i, DISPC_TRANS_COLOR);
3263 DUMPREG(i, DISPC_TIMING_H);
3264 DUMPREG(i, DISPC_TIMING_V);
3265 DUMPREG(i, DISPC_POL_FREQ);
3266 DUMPREG(i, DISPC_DIVISORo);
3267 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3268
4dd2da15
AT		 3269 DUMPREG(i, DISPC_DATA_CYCLE1);
3270 DUMPREG(i, DISPC_DATA_CYCLE2);
3271 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3272
332e9d70 3273 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3274 DUMPREG(i, DISPC_CPR_COEF_R);
3275 DUMPREG(i, DISPC_CPR_COEF_G);
3276 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3277 }
2a205f34 3278 }
80c39712 3279
4dd2da15
AT		 3280 p_names = ovl_names;
3281
3282 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3283 DUMPREG(i, DISPC_OVL_BA0);
3284 DUMPREG(i, DISPC_OVL_BA1);
3285 DUMPREG(i, DISPC_OVL_POSITION);
3286 DUMPREG(i, DISPC_OVL_SIZE);
3287 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3288 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3289 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3290 DUMPREG(i, DISPC_OVL_ROW_INC);
3291 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3292 if (dss_has_feature(FEAT_PRELOAD))
3293 DUMPREG(i, DISPC_OVL_PRELOAD);
3294
3295 if (i == OMAP_DSS_GFX) {
3296 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3297 DUMPREG(i, DISPC_OVL_TABLE_BA);
3298 continue;
3299 }
3300
3301 DUMPREG(i, DISPC_OVL_FIR);
3302 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3303 DUMPREG(i, DISPC_OVL_ACCU0);
3304 DUMPREG(i, DISPC_OVL_ACCU1);
3305 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3306 DUMPREG(i, DISPC_OVL_BA0_UV);
3307 DUMPREG(i, DISPC_OVL_BA1_UV);
3308 DUMPREG(i, DISPC_OVL_FIR2);
3309 DUMPREG(i, DISPC_OVL_ACCU2_0);
3310 DUMPREG(i, DISPC_OVL_ACCU2_1);
3311 }
3312 if (dss_has_feature(FEAT_ATTR2))
3313 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3314 if (dss_has_feature(FEAT_PRELOAD))
3315 DUMPREG(i, DISPC_OVL_PRELOAD);
29fceeeb
TV		 3316 if (dss_has_feature(FEAT_MFLAG))
3317 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
ab5ca071 3318 }
5010be80
AT		 3319
3320#undef DISPC_REG
3321#undef DUMPREG
3322
3323#define DISPC_REG(plane, name, i) name(plane, i)
3324#define DUMPREG(plane, name, i) \
4dd2da15 3325 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3326 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3327 dispc_read_reg(DISPC_REG(plane, name, i)))
3328
4dd2da15 3329 /* Video pipeline coefficient registers */
332e9d70 3330
4dd2da15
AT		 3331 /* start from OMAP_DSS_VIDEO1 */
3332 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3333 for (j = 0; j < 8; j++)
3334 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3335
4dd2da15
AT		 3336 for (j = 0; j < 8; j++)
3337 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3338
4dd2da15
AT		 3339 for (j = 0; j < 5; j++)
3340 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3341
4dd2da15
AT		 3342 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3343 for (j = 0; j < 8; j++)
3344 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3345 }
3346
3347 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3348 for (j = 0; j < 8; j++)
3349 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3350
3351 for (j = 0; j < 8; j++)
3352 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3353
3354 for (j = 0; j < 8; j++)
3355 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3356 }
332e9d70 3357 }
80c39712 3358
4fbafaf3 3359 dispc_runtime_put();
5010be80
AT		 3360
3361#undef DISPC_REG
80c39712
TV		 3362#undef DUMPREG
3363}
3364
80c39712
TV		 3365/* calculate clock rates using dividers in cinfo */
3366int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3367 struct dispc_clock_info *cinfo)
3368{
80c39712
TV		 3369 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3370 return -EINVAL;
9eaaf207 3371 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3372 return -EINVAL;
80c39712 3373
80c39712
TV		 3374 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3375 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3376
80c39712
TV		 3377 return 0;
3378}
80c39712 3379
7c284e6e
TV		 3380bool dispc_div_calc(unsigned long dispc,
3381 unsigned long pck_min, unsigned long pck_max,
3382 dispc_div_calc_func func, void *data)
3383{
3384 int lckd, lckd_start, lckd_stop;
3385 int pckd, pckd_start, pckd_stop;
3386 unsigned long pck, lck;
3387 unsigned long lck_max;
3388 unsigned long pckd_hw_min, pckd_hw_max;
3389 unsigned min_fck_per_pck;
3390 unsigned long fck;
80c39712 3391
7c284e6e
TV		 3392#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3393 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3394#else
3395 min_fck_per_pck = 0;
3396#endif
80c39712 3397
7c284e6e
TV		 3398 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3399 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3400
7c284e6e 3401 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3402
7c284e6e
TV		 3403 pck_min = pck_min ? pck_min : 1;
3404 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3405
7c284e6e
TV		 3406 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3407 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3408
7c284e6e
TV		 3409 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3410 lck = dispc / lckd;
80c39712 3411
7c284e6e
TV		 3412 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3413 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3414
7c284e6e
TV		 3415 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3416 pck = lck / pckd;
80c39712 3417
7c284e6e
TV		 3418 /*
3419 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3420 * clock, which means we're configuring DISPC fclk here
3421 * also. Thus we need to use the calculated lck. For
3422 * OMAP4+ the DISPC fclk is a separate clock.
3423 */
3424 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3425 fck = dispc_core_clk_rate();
3426 else
3427 fck = lck;
3428
3429 if (fck < pck * min_fck_per_pck)
3430 continue;
3431
3432 if (func(lckd, pckd, lck, pck, data))
3433 return true;
3434 }
3435 }
3436
3437 return false;
80c39712
TV		 3438}
3439
f0d08f89 3440void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3441 const struct dispc_clock_info *cinfo)
80c39712
TV		 3442{
3443 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3444 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3445
26d9dd0d 3446 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3447}
3448
26d9dd0d 3449int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3450 struct dispc_clock_info *cinfo)
80c39712
TV		 3451{
3452 unsigned long fck;
3453
3454 fck = dispc_fclk_rate();
3455
ce7fa5eb
MR		 3456 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3457 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3458
3459 cinfo->lck = fck / cinfo->lck_div;
3460 cinfo->pck = cinfo->lck / cinfo->pck_div;
3461
3462 return 0;
3463}
3464
4e0397cf
TV		 3465u32 dispc_read_irqstatus(void)
3466{
3467 return dispc_read_reg(DISPC_IRQSTATUS);
3468}
348be69d 3469EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3470
3471void dispc_clear_irqstatus(u32 mask)
3472{
3473 dispc_write_reg(DISPC_IRQSTATUS, mask);
3474}
348be69d 3475EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3476
3477u32 dispc_read_irqenable(void)
3478{
3479 return dispc_read_reg(DISPC_IRQENABLE);
3480}
348be69d 3481EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3482
3483void dispc_write_irqenable(u32 mask)
3484{
3485 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3486
3487 /* clear the irqstatus for newly enabled irqs */
3488 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3489
3490 dispc_write_reg(DISPC_IRQENABLE, mask);
3491}
348be69d 3492EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3493
80c39712
TV		 3494void dispc_enable_sidle(void)
3495{
3496 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3497}
3498
3499void dispc_disable_sidle(void)
3500{
3501 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3502}
3503
3504static void _omap_dispc_initial_config(void)
3505{
3506 u32 l;
3507
0cf35df3
MR		 3508 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3509 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3510 l = dispc_read_reg(DISPC_DIVISOR);
3511 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3512 l = FLD_MOD(l, 1, 0, 0);
3513 l = FLD_MOD(l, 1, 23, 16);
3514 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3515
3516 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3517 }
3518
80c39712 3519 /* FUNCGATED */
6ced40bf
AT		 3520 if (dss_has_feature(FEAT_FUNCGATED))
3521 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3522
6e5264b0 3523 dispc_setup_color_conv_coef();
80c39712
TV		 3524
3525 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3526
42a6961c 3527 dispc_init_fifos();
5ed8cf5b
TV		 3528
3529 dispc_configure_burst_sizes();
54128701
AT		 3530
3531 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3532
3533 if (dispc.feat->mstandby_workaround)
3534 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
80c39712
TV		 3535}
3536
dcbe765b
CM		 3537static const struct dispc_features omap24xx_dispc_feats __initconst = {
3538 .sw_start = 5,
3539 .fp_start = 15,
3540 .bp_start = 27,
3541 .sw_max = 64,
3542 .vp_max = 255,
3543 .hp_max = 256,
33b89928
AT		 3544 .mgr_width_start = 10,
3545 .mgr_height_start = 26,
3546 .mgr_width_max = 2048,
3547 .mgr_height_max = 2048,
ca5ca69c 3548 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3549 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3550 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3551 .num_fifos = 3,
cffa947d 3552 .no_framedone_tv = true,
8bc65552 3553 .set_max_preload = false,
dcbe765b
CM		 3554};
3555
3556static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3557 .sw_start = 5,
3558 .fp_start = 15,
3559 .bp_start = 27,
3560 .sw_max = 64,
3561 .vp_max = 255,
3562 .hp_max = 256,
33b89928
AT		 3563 .mgr_width_start = 10,
3564 .mgr_height_start = 26,
3565 .mgr_width_max = 2048,
3566 .mgr_height_max = 2048,
ca5ca69c
AT		 3567 .max_lcd_pclk = 173000000,
3568 .max_tv_pclk = 59000000,
dcbe765b
CM		 3569 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3570 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3571 .num_fifos = 3,
cffa947d 3572 .no_framedone_tv = true,
8bc65552 3573 .set_max_preload = false,
dcbe765b
CM		 3574};
3575
3576static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3577 .sw_start = 7,
3578 .fp_start = 19,
3579 .bp_start = 31,
3580 .sw_max = 256,
3581 .vp_max = 4095,
3582 .hp_max = 4096,
33b89928
AT		 3583 .mgr_width_start = 10,
3584 .mgr_height_start = 26,
3585 .mgr_width_max = 2048,
3586 .mgr_height_max = 2048,
ca5ca69c
AT		 3587 .max_lcd_pclk = 173000000,
3588 .max_tv_pclk = 59000000,
dcbe765b
CM		 3589 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3590 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3591 .num_fifos = 3,
cffa947d 3592 .no_framedone_tv = true,
8bc65552 3593 .set_max_preload = false,
dcbe765b
CM		 3594};
3595
3596static const struct dispc_features omap44xx_dispc_feats __initconst = {
3597 .sw_start = 7,
3598 .fp_start = 19,
3599 .bp_start = 31,
3600 .sw_max = 256,
3601 .vp_max = 4095,
3602 .hp_max = 4096,
33b89928
AT		 3603 .mgr_width_start = 10,
3604 .mgr_height_start = 26,
3605 .mgr_width_max = 2048,
3606 .mgr_height_max = 2048,
ca5ca69c
AT		 3607 .max_lcd_pclk = 170000000,
3608 .max_tv_pclk = 185625000,
dcbe765b
CM		 3609 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3610 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3611 .num_fifos = 5,
66a0f9e4 3612 .gfx_fifo_workaround = true,
8bc65552 3613 .set_max_preload = true,
dcbe765b
CM		 3614};
3615
264236f8
AT		 3616static const struct dispc_features omap54xx_dispc_feats __initconst = {
3617 .sw_start = 7,
3618 .fp_start = 19,
3619 .bp_start = 31,
3620 .sw_max = 256,
3621 .vp_max = 4095,
3622 .hp_max = 4096,
3623 .mgr_width_start = 11,
3624 .mgr_height_start = 27,
3625 .mgr_width_max = 4096,
3626 .mgr_height_max = 4096,
ca5ca69c
AT		 3627 .max_lcd_pclk = 170000000,
3628 .max_tv_pclk = 186000000,
264236f8
AT		 3629 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3630 .calc_core_clk = calc_core_clk_44xx,
3631 .num_fifos = 5,
3632 .gfx_fifo_workaround = true,
d0df9a2c 3633 .mstandby_workaround = true,
8bc65552 3634 .set_max_preload = true,
264236f8
AT		 3635};
3636
84b47623 3637static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3638{
3639 const struct dispc_features *src;
3640 struct dispc_features *dst;
3641
84b47623 3642 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3643 if (!dst) {
84b47623 3644 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3645 return -ENOMEM;
3646 }
3647
b2c7d54f 3648 switch (omapdss_get_version()) {
84b47623 3649 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3650 src = &omap24xx_dispc_feats;
84b47623
TV		 3651 break;
3652
3653 case OMAPDSS_VER_OMAP34xx_ES1:
3654 src = &omap34xx_rev1_0_dispc_feats;
3655 break;
3656
3657 case OMAPDSS_VER_OMAP34xx_ES3:
3658 case OMAPDSS_VER_OMAP3630:
3659 case OMAPDSS_VER_AM35xx:
3660 src = &omap34xx_rev3_0_dispc_feats;
3661 break;
3662
3663 case OMAPDSS_VER_OMAP4430_ES1:
3664 case OMAPDSS_VER_OMAP4430_ES2:
3665 case OMAPDSS_VER_OMAP4:
dcbe765b 3666 src = &omap44xx_dispc_feats;
84b47623
TV		 3667 break;
3668
3669 case OMAPDSS_VER_OMAP5:
264236f8 3670 src = &omap54xx_dispc_feats;
84b47623
TV		 3671 break;
3672
3673 default:
dcbe765b
CM		 3674 return -ENODEV;
3675 }
3676
3677 memcpy(dst, src, sizeof(*dst));
3678 dispc.feat = dst;
3679
3680 return 0;
3681}
3682
96e2e637
TV		 3683int dispc_request_irq(irq_handler_t handler, void *dev_id)
3684{
3685 return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler,
3686 IRQF_SHARED, "OMAP DISPC", dev_id);
3687}
348be69d 3688EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 3689
3690void dispc_free_irq(void *dev_id)
3691{
3692 devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id);
3693}
348be69d 3694EXPORT_SYMBOL(dispc_free_irq);
96e2e637 3695
060b6d9c 3696/* DISPC HW IP initialisation */
6e7e8f06 3697static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3698{
3699 u32 rev;
affe360d 3700 int r = 0;
ea9da36a
SG		 3701 struct resource *dispc_mem;
3702
060b6d9c
SG		 3703 dispc.pdev = pdev;
3704
84b47623 3705 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 3706 if (r)
3707 return r;
3708
ea9da36a
SG		 3709 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3710 if (!dispc_mem) {
3711 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3712 return -EINVAL;
ea9da36a 3713 }
cd3b3449 3714
6e2a14d2
JL		 3715 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3716 resource_size(dispc_mem));
060b6d9c
SG		 3717 if (!dispc.base) {
3718 DSSERR("can't ioremap DISPC\n");
cd3b3449 3719 return -ENOMEM;
affe360d 3720 }
cd3b3449 3721
affe360d 3722 dispc.irq = platform_get_irq(dispc.pdev, 0);
3723 if (dispc.irq < 0) {
3724 DSSERR("platform_get_irq failed\n");
cd3b3449 3725 return -ENODEV;
affe360d 3726 }
3727
4fbafaf3
TV		 3728 pm_runtime_enable(&pdev->dev);
3729
3730 r = dispc_runtime_get();
3731 if (r)
3732 goto err_runtime_get;
060b6d9c
SG		 3733
3734 _omap_dispc_initial_config();
3735
060b6d9c 3736 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3737 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3738 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3739
4fbafaf3 3740 dispc_runtime_put();
060b6d9c 3741
04b1fc02
TV		 3742 dss_init_overlay_managers();
3743
e40402cf
TV		 3744 dss_debugfs_create_file("dispc", dispc_dump_regs);
3745
060b6d9c 3746 return 0;
4fbafaf3
TV		 3747
3748err_runtime_get:
3749 pm_runtime_disable(&pdev->dev);
affe360d 3750 return r;
060b6d9c
SG		 3751}
3752
6e7e8f06 3753static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3754{
4fbafaf3
TV		 3755 pm_runtime_disable(&pdev->dev);
3756
04b1fc02
TV		 3757 dss_uninit_overlay_managers();
3758
060b6d9c
SG		 3759 return 0;
3760}
3761
4fbafaf3
TV		 3762static int dispc_runtime_suspend(struct device *dev)
3763{
3764 dispc_save_context();
4fbafaf3
TV		 3765
3766 return 0;
3767}
3768
3769static int dispc_runtime_resume(struct device *dev)
3770{
be07dcd7
TV		 3771 _omap_dispc_initial_config();
3772
49ea86f3 3773 dispc_restore_context();
4fbafaf3
TV		 3774
3775 return 0;
3776}
3777
3778static const struct dev_pm_ops dispc_pm_ops = {
3779 .runtime_suspend = dispc_runtime_suspend,
3780 .runtime_resume = dispc_runtime_resume,
3781};
3782
060b6d9c 3783static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3784 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3785 .driver = {
3786 .name = "omapdss_dispc",
3787 .owner = THIS_MODULE,
4fbafaf3 3788 .pm = &dispc_pm_ops,
060b6d9c
SG		 3789 },
3790};
3791
6e7e8f06 3792int __init dispc_init_platform_driver(void)
060b6d9c 3793{
11436e1d 3794 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3795}
3796
6e7e8f06 3797void __exit dispc_uninit_platform_driver(void)
060b6d9c 3798{
04c742c3 3799 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3800}
Linux kernel - Deliverables
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