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OMAPDSS: DISPC: Support rotation through TILER
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
80c39712
TV		 122static void _omap_dispc_set_irqs(void);
123
55978cc2 124static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 125{
55978cc2 126 __raw_writel(val, dispc.base + idx);
80c39712
TV		 127}
128
55978cc2 129static inline u32 dispc_read_reg(const u16 idx)
80c39712 130{
55978cc2 131 return __raw_readl(dispc.base + idx);
80c39712
TV		 132}
133
134#define SR(reg) \
55978cc2 135 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 136#define RR(reg) \
55978cc2 137 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 138
4fbafaf3 139static void dispc_save_context(void)
80c39712 140{
c6104b8e 141 int i, j;
80c39712 142
4fbafaf3
TV		 143 DSSDBG("dispc_save_context\n");
144
80c39712
TV		 145 SR(IRQENABLE);
146 SR(CONTROL);
147 SR(CONFIG);
80c39712 148 SR(LINE_NUMBER);
11354dd5
AT		 149 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
150 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 151 SR(GLOBAL_ALPHA);
2a205f34
SS		 152 if (dss_has_feature(FEAT_MGR_LCD2)) {
153 SR(CONTROL2);
2a205f34
SS		 154 SR(CONFIG2);
155 }
80c39712 156
c6104b8e
AT		 157 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
158 SR(DEFAULT_COLOR(i));
159 SR(TRANS_COLOR(i));
160 SR(SIZE_MGR(i));
161 if (i == OMAP_DSS_CHANNEL_DIGIT)
162 continue;
163 SR(TIMING_H(i));
164 SR(TIMING_V(i));
165 SR(POL_FREQ(i));
166 SR(DIVISORo(i));
167
168 SR(DATA_CYCLE1(i));
169 SR(DATA_CYCLE2(i));
170 SR(DATA_CYCLE3(i));
171
332e9d70 172 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 173 SR(CPR_COEF_R(i));
174 SR(CPR_COEF_G(i));
175 SR(CPR_COEF_B(i));
332e9d70 176 }
2a205f34 177 }
80c39712 178
c6104b8e
AT		 179 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
180 SR(OVL_BA0(i));
181 SR(OVL_BA1(i));
182 SR(OVL_POSITION(i));
183 SR(OVL_SIZE(i));
184 SR(OVL_ATTRIBUTES(i));
185 SR(OVL_FIFO_THRESHOLD(i));
186 SR(OVL_ROW_INC(i));
187 SR(OVL_PIXEL_INC(i));
188 if (dss_has_feature(FEAT_PRELOAD))
189 SR(OVL_PRELOAD(i));
190 if (i == OMAP_DSS_GFX) {
191 SR(OVL_WINDOW_SKIP(i));
192 SR(OVL_TABLE_BA(i));
193 continue;
194 }
195 SR(OVL_FIR(i));
196 SR(OVL_PICTURE_SIZE(i));
197 SR(OVL_ACCU0(i));
198 SR(OVL_ACCU1(i));
9b372c2d 199
c6104b8e
AT		 200 for (j = 0; j < 8; j++)
201 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 202
c6104b8e
AT		 203 for (j = 0; j < 8; j++)
204 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 205
c6104b8e
AT		 206 for (j = 0; j < 5; j++)
207 SR(OVL_CONV_COEF(i, j));
ab5ca071 208
c6104b8e
AT		 209 if (dss_has_feature(FEAT_FIR_COEF_V)) {
210 for (j = 0; j < 8; j++)
211 SR(OVL_FIR_COEF_V(i, j));
212 }
9b372c2d 213
c6104b8e
AT		 214 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
215 SR(OVL_BA0_UV(i));
216 SR(OVL_BA1_UV(i));
217 SR(OVL_FIR2(i));
218 SR(OVL_ACCU2_0(i));
219 SR(OVL_ACCU2_1(i));
ab5ca071 220
c6104b8e
AT		 221 for (j = 0; j < 8; j++)
222 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 223
c6104b8e
AT		 224 for (j = 0; j < 8; j++)
225 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 226
c6104b8e
AT		 227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V2(i, j));
229 }
230 if (dss_has_feature(FEAT_ATTR2))
231 SR(OVL_ATTRIBUTES2(i));
ab5ca071 232 }
0cf35df3
MR		 233
234 if (dss_has_feature(FEAT_CORE_CLK_DIV))
235 SR(DIVISOR);
49ea86f3 236
00928eaf 237 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 238 dispc.ctx_valid = true;
239
240 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 241}
242
4fbafaf3 243static void dispc_restore_context(void)
80c39712 244{
c6104b8e 245 int i, j, ctx;
4fbafaf3
TV		 246
247 DSSDBG("dispc_restore_context\n");
248
49ea86f3
TV		 249 if (!dispc.ctx_valid)
250 return;
251
00928eaf 252 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 253
254 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
255 return;
256
257 DSSDBG("ctx_loss_count: saved %d, current %d\n",
258 dispc.ctx_loss_cnt, ctx);
259
75c7d59d 260 /*RR(IRQENABLE);*/
80c39712
TV		 261 /*RR(CONTROL);*/
262 RR(CONFIG);
80c39712 263 RR(LINE_NUMBER);
11354dd5
AT		 264 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
265 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 266 RR(GLOBAL_ALPHA);
c6104b8e 267 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 268 RR(CONFIG2);
80c39712 269
c6104b8e
AT		 270 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
271 RR(DEFAULT_COLOR(i));
272 RR(TRANS_COLOR(i));
273 RR(SIZE_MGR(i));
274 if (i == OMAP_DSS_CHANNEL_DIGIT)
275 continue;
276 RR(TIMING_H(i));
277 RR(TIMING_V(i));
278 RR(POL_FREQ(i));
279 RR(DIVISORo(i));
280
281 RR(DATA_CYCLE1(i));
282 RR(DATA_CYCLE2(i));
283 RR(DATA_CYCLE3(i));
2a205f34 284
332e9d70 285 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 286 RR(CPR_COEF_R(i));
287 RR(CPR_COEF_G(i));
288 RR(CPR_COEF_B(i));
332e9d70 289 }
2a205f34 290 }
80c39712 291
c6104b8e
AT		 292 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
293 RR(OVL_BA0(i));
294 RR(OVL_BA1(i));
295 RR(OVL_POSITION(i));
296 RR(OVL_SIZE(i));
297 RR(OVL_ATTRIBUTES(i));
298 RR(OVL_FIFO_THRESHOLD(i));
299 RR(OVL_ROW_INC(i));
300 RR(OVL_PIXEL_INC(i));
301 if (dss_has_feature(FEAT_PRELOAD))
302 RR(OVL_PRELOAD(i));
303 if (i == OMAP_DSS_GFX) {
304 RR(OVL_WINDOW_SKIP(i));
305 RR(OVL_TABLE_BA(i));
306 continue;
307 }
308 RR(OVL_FIR(i));
309 RR(OVL_PICTURE_SIZE(i));
310 RR(OVL_ACCU0(i));
311 RR(OVL_ACCU1(i));
9b372c2d 312
c6104b8e
AT		 313 for (j = 0; j < 8; j++)
314 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 315
c6104b8e
AT		 316 for (j = 0; j < 8; j++)
317 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 318
c6104b8e
AT		 319 for (j = 0; j < 5; j++)
320 RR(OVL_CONV_COEF(i, j));
ab5ca071 321
c6104b8e
AT		 322 if (dss_has_feature(FEAT_FIR_COEF_V)) {
323 for (j = 0; j < 8; j++)
324 RR(OVL_FIR_COEF_V(i, j));
325 }
9b372c2d 326
c6104b8e
AT		 327 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
328 RR(OVL_BA0_UV(i));
329 RR(OVL_BA1_UV(i));
330 RR(OVL_FIR2(i));
331 RR(OVL_ACCU2_0(i));
332 RR(OVL_ACCU2_1(i));
ab5ca071 333
c6104b8e
AT		 334 for (j = 0; j < 8; j++)
335 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 336
c6104b8e
AT		 337 for (j = 0; j < 8; j++)
338 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 339
c6104b8e
AT		 340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V2(i, j));
342 }
343 if (dss_has_feature(FEAT_ATTR2))
344 RR(OVL_ATTRIBUTES2(i));
ab5ca071 345 }
80c39712 346
0cf35df3
MR		 347 if (dss_has_feature(FEAT_CORE_CLK_DIV))
348 RR(DIVISOR);
349
80c39712
TV		 350 /* enable last, because LCD & DIGIT enable are here */
351 RR(CONTROL);
2a205f34
SS		 352 if (dss_has_feature(FEAT_MGR_LCD2))
353 RR(CONTROL2);
75c7d59d
VS		 354 /* clear spurious SYNC_LOST_DIGIT interrupts */
355 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
356
357 /*
358 * enable last so IRQs won't trigger before
359 * the context is fully restored
360 */
361 RR(IRQENABLE);
49ea86f3
TV		 362
363 DSSDBG("context restored\n");
80c39712
TV		 364}
365
366#undef SR
367#undef RR
368
4fbafaf3
TV		 369int dispc_runtime_get(void)
370{
371 int r;
372
373 DSSDBG("dispc_runtime_get\n");
374
375 r = pm_runtime_get_sync(&dispc.pdev->dev);
376 WARN_ON(r < 0);
377 return r < 0 ? r : 0;
378}
379
380void dispc_runtime_put(void)
381{
382 int r;
383
384 DSSDBG("dispc_runtime_put\n");
385
0eaf9f52 386 r = pm_runtime_put_sync(&dispc.pdev->dev);
4fbafaf3 387 WARN_ON(r < 0);
80c39712
TV		 388}
389
dac57a05
AT		 390static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
391{
392 if (channel == OMAP_DSS_CHANNEL_LCD ||
393 channel == OMAP_DSS_CHANNEL_LCD2)
394 return true;
395 else
396 return false;
397}
4fbafaf3 398
3dcec4d6
TV		 399u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
400{
401 switch (channel) {
402 case OMAP_DSS_CHANNEL_LCD:
403 return DISPC_IRQ_VSYNC;
404 case OMAP_DSS_CHANNEL_LCD2:
405 return DISPC_IRQ_VSYNC2;
406 case OMAP_DSS_CHANNEL_DIGIT:
407 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
408 default:
409 BUG();
c6eee968 410 return 0;
3dcec4d6
TV		 411 }
412}
413
7d1365c9
TV		 414u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
415{
416 switch (channel) {
417 case OMAP_DSS_CHANNEL_LCD:
418 return DISPC_IRQ_FRAMEDONE;
419 case OMAP_DSS_CHANNEL_LCD2:
420 return DISPC_IRQ_FRAMEDONE2;
421 case OMAP_DSS_CHANNEL_DIGIT:
422 return 0;
423 default:
424 BUG();
c6eee968 425 return 0;
7d1365c9
TV		 426 }
427}
428
26d9dd0d 429bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 430{
431 int bit;
432
dac57a05 433 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 434 bit = 5; /* GOLCD */
435 else
436 bit = 6; /* GODIGIT */
437
2a205f34
SS		 438 if (channel == OMAP_DSS_CHANNEL_LCD2)
439 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
440 else
441 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 442}
443
26d9dd0d 444void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 445{
446 int bit;
2a205f34 447 bool enable_bit, go_bit;
80c39712 448
dac57a05 449 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 450 bit = 0; /* LCDENABLE */
451 else
452 bit = 1; /* DIGITALENABLE */
453
454 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 455 if (channel == OMAP_DSS_CHANNEL_LCD2)
456 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
457 else
458 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
459
460 if (!enable_bit)
e6d80f95 461 return;
80c39712 462
dac57a05 463 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 464 bit = 5; /* GOLCD */
465 else
466 bit = 6; /* GODIGIT */
467
2a205f34
SS		 468 if (channel == OMAP_DSS_CHANNEL_LCD2)
469 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
470 else
471 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
472
473 if (go_bit) {
80c39712 474 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 475 return;
80c39712
TV		 476 }
477
2a205f34
SS		 478 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
479 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 480
2a205f34
SS		 481 if (channel == OMAP_DSS_CHANNEL_LCD2)
482 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
483 else
484 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 485}
486
f0e5caab 487static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 488{
9b372c2d 489 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 490}
491
f0e5caab 492static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 493{
9b372c2d 494 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 495}
496
f0e5caab 497static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 498{
9b372c2d 499 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 500}
501
f0e5caab 502static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 503{
504 BUG_ON(plane == OMAP_DSS_GFX);
505
506 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
507}
508
f0e5caab
TV		 509static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
510 u32 value)
ab5ca071
AJ		 511{
512 BUG_ON(plane == OMAP_DSS_GFX);
513
514 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
515}
516
f0e5caab 517static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 518{
519 BUG_ON(plane == OMAP_DSS_GFX);
520
521 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
522}
523
debd9074
CM		 524static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
525 int fir_vinc, int five_taps,
526 enum omap_color_component color_comp)
80c39712 527{
debd9074 528 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 529 int i;
530
debd9074
CM		 531 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
532 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 533
534 for (i = 0; i < 8; i++) {
535 u32 h, hv;
536
debd9074
CM		 537 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
538 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
539 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
540 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
541 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
542 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
543 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
544 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 545
0d66cbb5 546 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 547 dispc_ovl_write_firh_reg(plane, i, h);
548 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 549 } else {
f0e5caab
TV		 550 dispc_ovl_write_firh2_reg(plane, i, h);
551 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 552 }
553
80c39712
TV		 554 }
555
66be8f6c
GI		 556 if (five_taps) {
557 for (i = 0; i < 8; i++) {
558 u32 v;
debd9074
CM		 559 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
560 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 561 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 562 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 563 else
f0e5caab 564 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 565 }
80c39712
TV		 566 }
567}
568
569static void _dispc_setup_color_conv_coef(void)
570{
ac01c29e 571 int i;
80c39712
TV		 572 const struct color_conv_coef {
573 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
574 int full_range;
575 } ctbl_bt601_5 = {
576 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
577 };
578
579 const struct color_conv_coef *ct;
580
581#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
582
583 ct = &ctbl_bt601_5;
584
ac01c29e
AT		 585 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
586 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
587 CVAL(ct->rcr, ct->ry));
588 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
589 CVAL(ct->gy, ct->rcb));
590 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
591 CVAL(ct->gcb, ct->gcr));
592 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
593 CVAL(ct->bcr, ct->by));
594 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
595 CVAL(0, ct->bcb));
596
597 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
598 11, 11);
599 }
80c39712
TV		 600
601#undef CVAL
80c39712
TV		 602}
603
604
f0e5caab 605static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 606{
9b372c2d 607 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 608}
609
f0e5caab 610static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 611{
9b372c2d 612 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 613}
614
f0e5caab 615static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 616{
617 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
618}
619
f0e5caab 620static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 621{
622 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
623}
624
f0e5caab 625static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 626{
80c39712 627 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 628
629 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 630}
631
f0e5caab 632static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 633{
80c39712 634 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 635
636 if (plane == OMAP_DSS_GFX)
637 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
638 else
639 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 640}
641
f0e5caab 642static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 643{
644 u32 val;
80c39712
TV		 645
646 BUG_ON(plane == OMAP_DSS_GFX);
647
648 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 649
650 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 651}
652
54128701
AT		 653static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
654{
655 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
656
657 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
658 return;
659
660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
661}
662
663static void dispc_ovl_enable_zorder_planes(void)
664{
665 int i;
666
667 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
668 return;
669
670 for (i = 0; i < dss_feat_get_num_ovls(); i++)
671 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
672}
673
f0e5caab 674static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 675{
f6dc8150 676 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 677
f6dc8150 678 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 679 return;
680
9b372c2d 681 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 682}
683
f0e5caab 684static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 685{
b8c095b4 686 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 687 int shift;
f6dc8150 688 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 689
f6dc8150 690 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 691 return;
a0acb557 692
fe3cc9d6
TV		 693 shift = shifts[plane];
694 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 695}
696
f0e5caab 697static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 698{
9b372c2d 699 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 700}
701
f0e5caab 702static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 703{
9b372c2d 704 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 705}
706
f0e5caab 707static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 708 enum omap_color_mode color_mode)
709{
710 u32 m = 0;
f20e4220
AJ		 711 if (plane != OMAP_DSS_GFX) {
712 switch (color_mode) {
713 case OMAP_DSS_COLOR_NV12:
714 m = 0x0; break;
08f3267e 715 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 716 m = 0x1; break;
717 case OMAP_DSS_COLOR_RGBA16:
718 m = 0x2; break;
08f3267e 719 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 720 m = 0x4; break;
721 case OMAP_DSS_COLOR_ARGB16:
722 m = 0x5; break;
723 case OMAP_DSS_COLOR_RGB16:
724 m = 0x6; break;
725 case OMAP_DSS_COLOR_ARGB16_1555:
726 m = 0x7; break;
727 case OMAP_DSS_COLOR_RGB24U:
728 m = 0x8; break;
729 case OMAP_DSS_COLOR_RGB24P:
730 m = 0x9; break;
731 case OMAP_DSS_COLOR_YUV2:
732 m = 0xa; break;
733 case OMAP_DSS_COLOR_UYVY:
734 m = 0xb; break;
735 case OMAP_DSS_COLOR_ARGB32:
736 m = 0xc; break;
737 case OMAP_DSS_COLOR_RGBA32:
738 m = 0xd; break;
739 case OMAP_DSS_COLOR_RGBX32:
740 m = 0xe; break;
741 case OMAP_DSS_COLOR_XRGB16_1555:
742 m = 0xf; break;
743 default:
c6eee968 744 BUG(); return;
f20e4220
AJ		 745 }
746 } else {
747 switch (color_mode) {
748 case OMAP_DSS_COLOR_CLUT1:
749 m = 0x0; break;
750 case OMAP_DSS_COLOR_CLUT2:
751 m = 0x1; break;
752 case OMAP_DSS_COLOR_CLUT4:
753 m = 0x2; break;
754 case OMAP_DSS_COLOR_CLUT8:
755 m = 0x3; break;
756 case OMAP_DSS_COLOR_RGB12U:
757 m = 0x4; break;
758 case OMAP_DSS_COLOR_ARGB16:
759 m = 0x5; break;
760 case OMAP_DSS_COLOR_RGB16:
761 m = 0x6; break;
762 case OMAP_DSS_COLOR_ARGB16_1555:
763 m = 0x7; break;
764 case OMAP_DSS_COLOR_RGB24U:
765 m = 0x8; break;
766 case OMAP_DSS_COLOR_RGB24P:
767 m = 0x9; break;
08f3267e 768 case OMAP_DSS_COLOR_RGBX16:
f20e4220 769 m = 0xa; break;
08f3267e 770 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 771 m = 0xb; break;
772 case OMAP_DSS_COLOR_ARGB32:
773 m = 0xc; break;
774 case OMAP_DSS_COLOR_RGBA32:
775 m = 0xd; break;
776 case OMAP_DSS_COLOR_RGBX32:
777 m = 0xe; break;
778 case OMAP_DSS_COLOR_XRGB16_1555:
779 m = 0xf; break;
780 default:
c6eee968 781 BUG(); return;
f20e4220 782 }
80c39712
TV		 783 }
784
9b372c2d 785 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 786}
787
65e006ff
CM		 788static void dispc_ovl_configure_burst_type(enum omap_plane plane,
789 enum omap_dss_rotation_type rotation_type)
790{
791 if (dss_has_feature(FEAT_BURST_2D) == 0)
792 return;
793
794 if (rotation_type == OMAP_DSS_ROT_TILER)
795 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
796 else
797 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
798}
799
f427984e 800void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 801{
802 int shift;
803 u32 val;
2a205f34 804 int chan = 0, chan2 = 0;
80c39712
TV		 805
806 switch (plane) {
807 case OMAP_DSS_GFX:
808 shift = 8;
809 break;
810 case OMAP_DSS_VIDEO1:
811 case OMAP_DSS_VIDEO2:
b8c095b4 812 case OMAP_DSS_VIDEO3:
80c39712
TV		 813 shift = 16;
814 break;
815 default:
816 BUG();
817 return;
818 }
819
9b372c2d 820 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 821 if (dss_has_feature(FEAT_MGR_LCD2)) {
822 switch (channel) {
823 case OMAP_DSS_CHANNEL_LCD:
824 chan = 0;
825 chan2 = 0;
826 break;
827 case OMAP_DSS_CHANNEL_DIGIT:
828 chan = 1;
829 chan2 = 0;
830 break;
831 case OMAP_DSS_CHANNEL_LCD2:
832 chan = 0;
833 chan2 = 1;
834 break;
835 default:
836 BUG();
c6eee968 837 return;
2a205f34
SS		 838 }
839
840 val = FLD_MOD(val, chan, shift, shift);
841 val = FLD_MOD(val, chan2, 31, 30);
842 } else {
843 val = FLD_MOD(val, channel, shift, shift);
844 }
9b372c2d 845 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 846}
847
2cc5d1af
TV		 848static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
849{
850 int shift;
851 u32 val;
852 enum omap_channel channel;
853
854 switch (plane) {
855 case OMAP_DSS_GFX:
856 shift = 8;
857 break;
858 case OMAP_DSS_VIDEO1:
859 case OMAP_DSS_VIDEO2:
860 case OMAP_DSS_VIDEO3:
861 shift = 16;
862 break;
863 default:
864 BUG();
c6eee968 865 return 0;
2cc5d1af
TV		 866 }
867
868 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
869
870 if (dss_has_feature(FEAT_MGR_LCD2)) {
871 if (FLD_GET(val, 31, 30) == 0)
872 channel = FLD_GET(val, shift, shift);
873 else
874 channel = OMAP_DSS_CHANNEL_LCD2;
875 } else {
876 channel = FLD_GET(val, shift, shift);
877 }
878
879 return channel;
880}
881
f0e5caab 882static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 883 enum omap_burst_size burst_size)
884{
b8c095b4 885 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 886 int shift;
80c39712 887
fe3cc9d6 888 shift = shifts[plane];
5ed8cf5b 889 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 890}
891
5ed8cf5b
TV		 892static void dispc_configure_burst_sizes(void)
893{
894 int i;
895 const int burst_size = BURST_SIZE_X8;
896
897 /* Configure burst size always to maximum size */
898 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 899 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 900}
901
83fa2f2e 902static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 903{
904 unsigned unit = dss_feat_get_burst_size_unit();
905 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
906 return unit * 8;
907}
908
d3862610
M		 909void dispc_enable_gamma_table(bool enable)
910{
911 /*
912 * This is partially implemented to support only disabling of
913 * the gamma table.
914 */
915 if (enable) {
916 DSSWARN("Gamma table enabling for TV not yet supported");
917 return;
918 }
919
920 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
921}
922
c64dca40 923static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 924{
925 u16 reg;
926
927 if (channel == OMAP_DSS_CHANNEL_LCD)
928 reg = DISPC_CONFIG;
929 else if (channel == OMAP_DSS_CHANNEL_LCD2)
930 reg = DISPC_CONFIG2;
931 else
932 return;
933
934 REG_FLD_MOD(reg, enable, 15, 15);
935}
936
c64dca40 937static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 938 struct omap_dss_cpr_coefs *coefs)
939{
940 u32 coef_r, coef_g, coef_b;
941
dac57a05 942 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 943 return;
944
945 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
946 FLD_VAL(coefs->rb, 9, 0);
947 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
948 FLD_VAL(coefs->gb, 9, 0);
949 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
950 FLD_VAL(coefs->bb, 9, 0);
951
952 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
953 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
954 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
955}
956
f0e5caab 957static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 958{
959 u32 val;
960
961 BUG_ON(plane == OMAP_DSS_GFX);
962
9b372c2d 963 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 964 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 965 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 966}
967
c3d92529 968static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 969{
b8c095b4 970 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 971 int shift;
80c39712 972
fe3cc9d6
TV		 973 shift = shifts[plane];
974 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 975}
976
8f366162 977static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 978 u16 height)
80c39712
TV		 979{
980 u32 val;
80c39712 981
80c39712 982 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 983 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 984}
985
986static void dispc_read_plane_fifo_sizes(void)
987{
80c39712
TV		 988 u32 size;
989 int plane;
a0acb557 990 u8 start, end;
5ed8cf5b
TV		 991 u32 unit;
992
993 unit = dss_feat_get_buffer_size_unit();
80c39712 994
a0acb557 995 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 996
e13a138b 997 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 998 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
999 size *= unit;
80c39712
TV		 1000 dispc.fifo_size[plane] = size;
1001 }
80c39712
TV		 1002}
1003
83fa2f2e 1004static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1005{
1006 return dispc.fifo_size[plane];
1007}
1008
6f04e1bf 1009void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1010{
a0acb557 1011 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1012 u32 unit;
1013
1014 unit = dss_feat_get_buffer_size_unit();
1015
1016 WARN_ON(low % unit != 0);
1017 WARN_ON(high % unit != 0);
1018
1019 low /= unit;
1020 high /= unit;
a0acb557 1021
9b372c2d
AT		 1022 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1023 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1024
3cb5d966 1025 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1026 plane,
9b372c2d 1027 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1028 lo_start, lo_end) * unit,
9b372c2d 1029 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1030 hi_start, hi_end) * unit,
1031 low * unit, high * unit);
80c39712 1032
9b372c2d 1033 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1034 FLD_VAL(high, hi_start, hi_end) |
1035 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1036}
1037
1038void dispc_enable_fifomerge(bool enable)
1039{
e6b0f884
TV		 1040 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1041 WARN_ON(enable);
1042 return;
1043 }
1044
80c39712
TV		 1045 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1046 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1047}
1048
83fa2f2e 1049void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1050 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1051 bool manual_update)
83fa2f2e
TV		 1052{
1053 /*
1054 * All sizes are in bytes. Both the buffer and burst are made of
1055 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1056 */
1057
1058 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1059 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1060 int i;
83fa2f2e
TV		 1061
1062 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1063 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1064
e0e405b9
TV		 1065 if (use_fifomerge) {
1066 total_fifo_size = 0;
1067 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1068 total_fifo_size += dispc_ovl_get_fifo_size(i);
1069 } else {
1070 total_fifo_size = ovl_fifo_size;
1071 }
1072
1073 /*
1074 * We use the same low threshold for both fifomerge and non-fifomerge
1075 * cases, but for fifomerge we calculate the high threshold using the
1076 * combined fifo size
1077 */
1078
3568f2a4 1079 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1080 *fifo_low = ovl_fifo_size - burst_size * 2;
1081 *fifo_high = total_fifo_size - burst_size;
1082 } else {
1083 *fifo_low = ovl_fifo_size - burst_size;
1084 *fifo_high = total_fifo_size - buf_unit;
1085 }
83fa2f2e
TV		 1086}
1087
f0e5caab 1088static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1089 int hinc, int vinc,
1090 enum omap_color_component color_comp)
80c39712
TV		 1091{
1092 u32 val;
80c39712 1093
0d66cbb5
AJ		 1094 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1095 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1096
0d66cbb5
AJ		 1097 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1098 &hinc_start, &hinc_end);
1099 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1100 &vinc_start, &vinc_end);
1101 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1102 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1103
0d66cbb5
AJ		 1104 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1105 } else {
1106 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1107 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1108 }
80c39712
TV		 1109}
1110
f0e5caab 1111static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1112{
1113 u32 val;
87a7484b 1114 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1115
87a7484b
AT		 1116 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1117 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1118
1119 val = FLD_VAL(vaccu, vert_start, vert_end) |
1120 FLD_VAL(haccu, hor_start, hor_end);
1121
9b372c2d 1122 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1123}
1124
f0e5caab 1125static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1126{
1127 u32 val;
87a7484b 1128 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1129
87a7484b
AT		 1130 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1131 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1132
1133 val = FLD_VAL(vaccu, vert_start, vert_end) |
1134 FLD_VAL(haccu, hor_start, hor_end);
1135
9b372c2d 1136 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1137}
1138
f0e5caab
TV		 1139static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1140 int vaccu)
ab5ca071
AJ		 1141{
1142 u32 val;
1143
1144 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1145 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1146}
1147
f0e5caab
TV		 1148static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1149 int vaccu)
ab5ca071
AJ		 1150{
1151 u32 val;
1152
1153 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1154 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1155}
80c39712 1156
f0e5caab 1157static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1158 u16 orig_width, u16 orig_height,
1159 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1160 bool five_taps, u8 rotation,
1161 enum omap_color_component color_comp)
80c39712 1162{
0d66cbb5 1163 int fir_hinc, fir_vinc;
80c39712 1164
ed14a3ce
AJ		 1165 fir_hinc = 1024 * orig_width / out_width;
1166 fir_vinc = 1024 * orig_height / out_height;
80c39712 1167
debd9074
CM		 1168 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1169 color_comp);
f0e5caab 1170 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1171}
1172
05dd0f53
CM		 1173static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1174 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1175 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1176{
1177 int h_accu2_0, h_accu2_1;
1178 int v_accu2_0, v_accu2_1;
1179 int chroma_hinc, chroma_vinc;
1180 int idx;
1181
1182 struct accu {
1183 s8 h0_m, h0_n;
1184 s8 h1_m, h1_n;
1185 s8 v0_m, v0_n;
1186 s8 v1_m, v1_n;
1187 };
1188
1189 const struct accu *accu_table;
1190 const struct accu *accu_val;
1191
1192 static const struct accu accu_nv12[4] = {
1193 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1194 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1195 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1196 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1197 };
1198
1199 static const struct accu accu_nv12_ilace[4] = {
1200 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1201 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1202 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1203 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1204 };
1205
1206 static const struct accu accu_yuv[4] = {
1207 { 0, 1, 0, 1, 0, 1, 0, 1 },
1208 { 0, 1, 0, 1, 0, 1, 0, 1 },
1209 { -1, 1, 0, 1, 0, 1, 0, 1 },
1210 { 0, 1, 0, 1, -1, 1, 0, 1 },
1211 };
1212
1213 switch (rotation) {
1214 case OMAP_DSS_ROT_0:
1215 idx = 0;
1216 break;
1217 case OMAP_DSS_ROT_90:
1218 idx = 1;
1219 break;
1220 case OMAP_DSS_ROT_180:
1221 idx = 2;
1222 break;
1223 case OMAP_DSS_ROT_270:
1224 idx = 3;
1225 break;
1226 default:
1227 BUG();
c6eee968 1228 return;
05dd0f53
CM		 1229 }
1230
1231 switch (color_mode) {
1232 case OMAP_DSS_COLOR_NV12:
1233 if (ilace)
1234 accu_table = accu_nv12_ilace;
1235 else
1236 accu_table = accu_nv12;
1237 break;
1238 case OMAP_DSS_COLOR_YUV2:
1239 case OMAP_DSS_COLOR_UYVY:
1240 accu_table = accu_yuv;
1241 break;
1242 default:
1243 BUG();
c6eee968 1244 return;
05dd0f53
CM		 1245 }
1246
1247 accu_val = &accu_table[idx];
1248
1249 chroma_hinc = 1024 * orig_width / out_width;
1250 chroma_vinc = 1024 * orig_height / out_height;
1251
1252 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1253 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1254 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1255 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1256
1257 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1258 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1259}
1260
f0e5caab 1261static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1262 u16 orig_width, u16 orig_height,
1263 u16 out_width, u16 out_height,
1264 bool ilace, bool five_taps,
1265 bool fieldmode, enum omap_color_mode color_mode,
1266 u8 rotation)
1267{
1268 int accu0 = 0;
1269 int accu1 = 0;
1270 u32 l;
80c39712 1271
f0e5caab 1272 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1273 out_width, out_height, five_taps,
1274 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1275 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1276
87a7484b
AT		 1277 /* RESIZEENABLE and VERTICALTAPS */
1278 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1279 l |= (orig_width != out_width) ? (1 << 5) : 0;
1280 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1281 l |= five_taps ? (1 << 21) : 0;
80c39712 1282
87a7484b
AT		 1283 /* VRESIZECONF and HRESIZECONF */
1284 if (dss_has_feature(FEAT_RESIZECONF)) {
1285 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1286 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1287 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1288 }
80c39712 1289
87a7484b
AT		 1290 /* LINEBUFFERSPLIT */
1291 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1292 l &= ~(0x1 << 22);
1293 l |= five_taps ? (1 << 22) : 0;
1294 }
80c39712 1295
9b372c2d 1296 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1297
1298 /*
1299 * field 0 = even field = bottom field
1300 * field 1 = odd field = top field
1301 */
1302 if (ilace && !fieldmode) {
1303 accu1 = 0;
0d66cbb5 1304 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1305 if (accu0 >= 1024/2) {
1306 accu1 = 1024/2;
1307 accu0 -= accu1;
1308 }
1309 }
1310
f0e5caab
TV		 1311 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1312 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1313}
1314
f0e5caab 1315static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1316 u16 orig_width, u16 orig_height,
1317 u16 out_width, u16 out_height,
1318 bool ilace, bool five_taps,
1319 bool fieldmode, enum omap_color_mode color_mode,
1320 u8 rotation)
1321{
1322 int scale_x = out_width != orig_width;
1323 int scale_y = out_height != orig_height;
1324
1325 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1326 return;
1327 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1328 color_mode != OMAP_DSS_COLOR_UYVY &&
1329 color_mode != OMAP_DSS_COLOR_NV12)) {
1330 /* reset chroma resampling for RGB formats */
1331 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1332 return;
1333 }
36377357
TV		 1334
1335 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1336 out_height, ilace, color_mode, rotation);
1337
0d66cbb5
AJ		 1338 switch (color_mode) {
1339 case OMAP_DSS_COLOR_NV12:
1340 /* UV is subsampled by 2 vertically*/
1341 orig_height >>= 1;
1342 /* UV is subsampled by 2 horz.*/
1343 orig_width >>= 1;
1344 break;
1345 case OMAP_DSS_COLOR_YUV2:
1346 case OMAP_DSS_COLOR_UYVY:
1347 /*For YUV422 with 90/270 rotation,
1348 *we don't upsample chroma
1349 */
1350 if (rotation == OMAP_DSS_ROT_0 ||
1351 rotation == OMAP_DSS_ROT_180)
1352 /* UV is subsampled by 2 hrz*/
1353 orig_width >>= 1;
1354 /* must use FIR for YUV422 if rotated */
1355 if (rotation != OMAP_DSS_ROT_0)
1356 scale_x = scale_y = true;
1357 break;
1358 default:
1359 BUG();
c6eee968 1360 return;
0d66cbb5
AJ		 1361 }
1362
1363 if (out_width != orig_width)
1364 scale_x = true;
1365 if (out_height != orig_height)
1366 scale_y = true;
1367
f0e5caab 1368 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1369 out_width, out_height, five_taps,
1370 rotation, DISPC_COLOR_COMPONENT_UV);
1371
1372 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1373 (scale_x || scale_y) ? 1 : 0, 8, 8);
1374 /* set H scaling */
1375 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1376 /* set V scaling */
1377 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1378}
1379
f0e5caab 1380static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1381 u16 orig_width, u16 orig_height,
1382 u16 out_width, u16 out_height,
1383 bool ilace, bool five_taps,
1384 bool fieldmode, enum omap_color_mode color_mode,
1385 u8 rotation)
1386{
1387 BUG_ON(plane == OMAP_DSS_GFX);
1388
f0e5caab 1389 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1390 orig_width, orig_height,
1391 out_width, out_height,
1392 ilace, five_taps,
1393 fieldmode, color_mode,
1394 rotation);
1395
f0e5caab 1396 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1397 orig_width, orig_height,
1398 out_width, out_height,
1399 ilace, five_taps,
1400 fieldmode, color_mode,
1401 rotation);
1402}
1403
f0e5caab 1404static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1405 bool mirroring, enum omap_color_mode color_mode)
1406{
87a7484b
AT		 1407 bool row_repeat = false;
1408 int vidrot = 0;
1409
80c39712
TV		 1410 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1411 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1412
1413 if (mirroring) {
1414 switch (rotation) {
1415 case OMAP_DSS_ROT_0:
1416 vidrot = 2;
1417 break;
1418 case OMAP_DSS_ROT_90:
1419 vidrot = 1;
1420 break;
1421 case OMAP_DSS_ROT_180:
1422 vidrot = 0;
1423 break;
1424 case OMAP_DSS_ROT_270:
1425 vidrot = 3;
1426 break;
1427 }
1428 } else {
1429 switch (rotation) {
1430 case OMAP_DSS_ROT_0:
1431 vidrot = 0;
1432 break;
1433 case OMAP_DSS_ROT_90:
1434 vidrot = 1;
1435 break;
1436 case OMAP_DSS_ROT_180:
1437 vidrot = 2;
1438 break;
1439 case OMAP_DSS_ROT_270:
1440 vidrot = 3;
1441 break;
1442 }
1443 }
1444
80c39712 1445 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1446 row_repeat = true;
80c39712 1447 else
87a7484b 1448 row_repeat = false;
80c39712 1449 }
87a7484b 1450
9b372c2d 1451 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1452 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1453 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1454 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1455}
1456
1457static int color_mode_to_bpp(enum omap_color_mode color_mode)
1458{
1459 switch (color_mode) {
1460 case OMAP_DSS_COLOR_CLUT1:
1461 return 1;
1462 case OMAP_DSS_COLOR_CLUT2:
1463 return 2;
1464 case OMAP_DSS_COLOR_CLUT4:
1465 return 4;
1466 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1467 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1468 return 8;
1469 case OMAP_DSS_COLOR_RGB12U:
1470 case OMAP_DSS_COLOR_RGB16:
1471 case OMAP_DSS_COLOR_ARGB16:
1472 case OMAP_DSS_COLOR_YUV2:
1473 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1474 case OMAP_DSS_COLOR_RGBA16:
1475 case OMAP_DSS_COLOR_RGBX16:
1476 case OMAP_DSS_COLOR_ARGB16_1555:
1477 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1478 return 16;
1479 case OMAP_DSS_COLOR_RGB24P:
1480 return 24;
1481 case OMAP_DSS_COLOR_RGB24U:
1482 case OMAP_DSS_COLOR_ARGB32:
1483 case OMAP_DSS_COLOR_RGBA32:
1484 case OMAP_DSS_COLOR_RGBX32:
1485 return 32;
1486 default:
1487 BUG();
c6eee968 1488 return 0;
80c39712
TV		 1489 }
1490}
1491
1492static s32 pixinc(int pixels, u8 ps)
1493{
1494 if (pixels == 1)
1495 return 1;
1496 else if (pixels > 1)
1497 return 1 + (pixels - 1) * ps;
1498 else if (pixels < 0)
1499 return 1 - (-pixels + 1) * ps;
1500 else
1501 BUG();
c6eee968 1502 return 0;
80c39712
TV		 1503}
1504
1505static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1506 u16 screen_width,
1507 u16 width, u16 height,
1508 enum omap_color_mode color_mode, bool fieldmode,
1509 unsigned int field_offset,
1510 unsigned *offset0, unsigned *offset1,
aed74b55 1511 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1512{
1513 u8 ps;
1514
1515 /* FIXME CLUT formats */
1516 switch (color_mode) {
1517 case OMAP_DSS_COLOR_CLUT1:
1518 case OMAP_DSS_COLOR_CLUT2:
1519 case OMAP_DSS_COLOR_CLUT4:
1520 case OMAP_DSS_COLOR_CLUT8:
1521 BUG();
1522 return;
1523 case OMAP_DSS_COLOR_YUV2:
1524 case OMAP_DSS_COLOR_UYVY:
1525 ps = 4;
1526 break;
1527 default:
1528 ps = color_mode_to_bpp(color_mode) / 8;
1529 break;
1530 }
1531
1532 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1533 width, height);
1534
1535 /*
1536 * field 0 = even field = bottom field
1537 * field 1 = odd field = top field
1538 */
1539 switch (rotation + mirror * 4) {
1540 case OMAP_DSS_ROT_0:
1541 case OMAP_DSS_ROT_180:
1542 /*
1543 * If the pixel format is YUV or UYVY divide the width
1544 * of the image by 2 for 0 and 180 degree rotation.
1545 */
1546 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1547 color_mode == OMAP_DSS_COLOR_UYVY)
1548 width = width >> 1;
1549 case OMAP_DSS_ROT_90:
1550 case OMAP_DSS_ROT_270:
1551 *offset1 = 0;
1552 if (field_offset)
1553 *offset0 = field_offset * screen_width * ps;
1554 else
1555 *offset0 = 0;
1556
aed74b55
CM		 1557 *row_inc = pixinc(1 +
1558 (y_predecim * screen_width - x_predecim * width) +
1559 (fieldmode ? screen_width : 0), ps);
1560 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1561 break;
1562
1563 case OMAP_DSS_ROT_0 + 4:
1564 case OMAP_DSS_ROT_180 + 4:
1565 /* If the pixel format is YUV or UYVY divide the width
1566 * of the image by 2 for 0 degree and 180 degree
1567 */
1568 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1569 color_mode == OMAP_DSS_COLOR_UYVY)
1570 width = width >> 1;
1571 case OMAP_DSS_ROT_90 + 4:
1572 case OMAP_DSS_ROT_270 + 4:
1573 *offset1 = 0;
1574 if (field_offset)
1575 *offset0 = field_offset * screen_width * ps;
1576 else
1577 *offset0 = 0;
aed74b55
CM		 1578 *row_inc = pixinc(1 -
1579 (y_predecim * screen_width + x_predecim * width) -
1580 (fieldmode ? screen_width : 0), ps);
1581 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1582 break;
1583
1584 default:
1585 BUG();
c6eee968 1586 return;
80c39712
TV		 1587 }
1588}
1589
1590static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1591 u16 screen_width,
1592 u16 width, u16 height,
1593 enum omap_color_mode color_mode, bool fieldmode,
1594 unsigned int field_offset,
1595 unsigned *offset0, unsigned *offset1,
aed74b55 1596 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1597{
1598 u8 ps;
1599 u16 fbw, fbh;
1600
1601 /* FIXME CLUT formats */
1602 switch (color_mode) {
1603 case OMAP_DSS_COLOR_CLUT1:
1604 case OMAP_DSS_COLOR_CLUT2:
1605 case OMAP_DSS_COLOR_CLUT4:
1606 case OMAP_DSS_COLOR_CLUT8:
1607 BUG();
1608 return;
1609 default:
1610 ps = color_mode_to_bpp(color_mode) / 8;
1611 break;
1612 }
1613
1614 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1615 width, height);
1616
1617 /* width & height are overlay sizes, convert to fb sizes */
1618
1619 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1620 fbw = width;
1621 fbh = height;
1622 } else {
1623 fbw = height;
1624 fbh = width;
1625 }
1626
1627 /*
1628 * field 0 = even field = bottom field
1629 * field 1 = odd field = top field
1630 */
1631 switch (rotation + mirror * 4) {
1632 case OMAP_DSS_ROT_0:
1633 *offset1 = 0;
1634 if (field_offset)
1635 *offset0 = *offset1 + field_offset * screen_width * ps;
1636 else
1637 *offset0 = *offset1;
aed74b55
CM		 1638 *row_inc = pixinc(1 +
1639 (y_predecim * screen_width - fbw * x_predecim) +
1640 (fieldmode ? screen_width : 0), ps);
1641 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1642 color_mode == OMAP_DSS_COLOR_UYVY)
1643 *pix_inc = pixinc(x_predecim, 2 * ps);
1644 else
1645 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1646 break;
1647 case OMAP_DSS_ROT_90:
1648 *offset1 = screen_width * (fbh - 1) * ps;
1649 if (field_offset)
1650 *offset0 = *offset1 + field_offset * ps;
1651 else
1652 *offset0 = *offset1;
aed74b55
CM		 1653 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1654 y_predecim + (fieldmode ? 1 : 0), ps);
1655 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1656 break;
1657 case OMAP_DSS_ROT_180:
1658 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1659 if (field_offset)
1660 *offset0 = *offset1 - field_offset * screen_width * ps;
1661 else
1662 *offset0 = *offset1;
1663 *row_inc = pixinc(-1 -
aed74b55
CM		 1664 (y_predecim * screen_width - fbw * x_predecim) -
1665 (fieldmode ? screen_width : 0), ps);
1666 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1667 color_mode == OMAP_DSS_COLOR_UYVY)
1668 *pix_inc = pixinc(-x_predecim, 2 * ps);
1669 else
1670 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1671 break;
1672 case OMAP_DSS_ROT_270:
1673 *offset1 = (fbw - 1) * ps;
1674 if (field_offset)
1675 *offset0 = *offset1 - field_offset * ps;
1676 else
1677 *offset0 = *offset1;
aed74b55
CM		 1678 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1679 y_predecim - (fieldmode ? 1 : 0), ps);
1680 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1681 break;
1682
1683 /* mirroring */
1684 case OMAP_DSS_ROT_0 + 4:
1685 *offset1 = (fbw - 1) * ps;
1686 if (field_offset)
1687 *offset0 = *offset1 + field_offset * screen_width * ps;
1688 else
1689 *offset0 = *offset1;
aed74b55 1690 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1691 (fieldmode ? screen_width : 0),
1692 ps);
aed74b55
CM		 1693 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1694 color_mode == OMAP_DSS_COLOR_UYVY)
1695 *pix_inc = pixinc(-x_predecim, 2 * ps);
1696 else
1697 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1698 break;
1699
1700 case OMAP_DSS_ROT_90 + 4:
1701 *offset1 = 0;
1702 if (field_offset)
1703 *offset0 = *offset1 + field_offset * ps;
1704 else
1705 *offset0 = *offset1;
aed74b55
CM		 1706 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1707 y_predecim + (fieldmode ? 1 : 0),
80c39712 1708 ps);
aed74b55 1709 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1710 break;
1711
1712 case OMAP_DSS_ROT_180 + 4:
1713 *offset1 = screen_width * (fbh - 1) * ps;
1714 if (field_offset)
1715 *offset0 = *offset1 - field_offset * screen_width * ps;
1716 else
1717 *offset0 = *offset1;
aed74b55 1718 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1719 (fieldmode ? screen_width : 0),
1720 ps);
aed74b55
CM		 1721 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1722 color_mode == OMAP_DSS_COLOR_UYVY)
1723 *pix_inc = pixinc(x_predecim, 2 * ps);
1724 else
1725 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1726 break;
1727
1728 case OMAP_DSS_ROT_270 + 4:
1729 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1730 if (field_offset)
1731 *offset0 = *offset1 - field_offset * ps;
1732 else
1733 *offset0 = *offset1;
aed74b55
CM		 1734 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1735 y_predecim - (fieldmode ? 1 : 0),
80c39712 1736 ps);
aed74b55 1737 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1738 break;
1739
1740 default:
1741 BUG();
c6eee968 1742 return;
80c39712
TV		 1743 }
1744}
1745
65e006ff
CM		 1746static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1747 enum omap_color_mode color_mode, bool fieldmode,
1748 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1749 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1750{
1751 u8 ps;
1752
1753 switch (color_mode) {
1754 case OMAP_DSS_COLOR_CLUT1:
1755 case OMAP_DSS_COLOR_CLUT2:
1756 case OMAP_DSS_COLOR_CLUT4:
1757 case OMAP_DSS_COLOR_CLUT8:
1758 BUG();
1759 return;
1760 default:
1761 ps = color_mode_to_bpp(color_mode) / 8;
1762 break;
1763 }
1764
1765 DSSDBG("scrw %d, width %d\n", screen_width, width);
1766
1767 /*
1768 * field 0 = even field = bottom field
1769 * field 1 = odd field = top field
1770 */
1771 *offset1 = 0;
1772 if (field_offset)
1773 *offset0 = *offset1 + field_offset * screen_width * ps;
1774 else
1775 *offset0 = *offset1;
1776 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1777 (fieldmode ? screen_width : 0), ps);
1778 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1779 color_mode == OMAP_DSS_COLOR_UYVY)
1780 *pix_inc = pixinc(x_predecim, 2 * ps);
1781 else
1782 *pix_inc = pixinc(x_predecim, ps);
1783}
1784
7faa9233
CM		 1785/*
1786 * This function is used to avoid synclosts in OMAP3, because of some
1787 * undocumented horizontal position and timing related limitations.
1788 */
81ab95b7
AT		 1789static int check_horiz_timing_omap3(enum omap_channel channel,
1790 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1791 u16 width, u16 height, u16 out_width, u16 out_height)
1792{
1793 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1794 unsigned long nonactive, lclk, pclk;
1795 static const u8 limits[3] = { 8, 10, 20 };
1796 u64 val, blank;
1797 int i;
1798
81ab95b7 1799 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 1800 pclk = dispc_mgr_pclk_rate(channel);
1801 if (dispc_mgr_is_lcd(channel))
1802 lclk = dispc_mgr_lclk_rate(channel);
1803 else
1804 lclk = dispc_fclk_rate();
1805
1806 i = 0;
1807 if (out_height < height)
1808 i++;
1809 if (out_width < width)
1810 i++;
81ab95b7 1811 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1812 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1813 if (blank <= limits[i])
1814 return -EINVAL;
1815
1816 /*
1817 * Pixel data should be prepared before visible display point starts.
1818 * So, atleast DS-2 lines must have already been fetched by DISPC
1819 * during nonactive - pos_x period.
1820 */
1821 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1822 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1823 val, max(0, DS - 2) * width);
1824 if (val < max(0, DS - 2) * width)
1825 return -EINVAL;
1826
1827 /*
1828 * All lines need to be refilled during the nonactive period of which
1829 * only one line can be loaded during the active period. So, atleast
1830 * DS - 1 lines should be loaded during nonactive period.
1831 */
1832 val = div_u64((u64)nonactive * lclk, pclk);
1833 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1834 val, max(0, DS - 1) * width);
1835 if (val < max(0, DS - 1) * width)
1836 return -EINVAL;
1837
1838 return 0;
1839}
1840
8b53d991 1841static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1842 const struct omap_video_timings *mgr_timings, u16 width,
1843 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1844 enum omap_color_mode color_mode)
80c39712 1845{
8b53d991 1846 u32 core_clk = 0;
26d9dd0d 1847 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1848
7282f1b7
CM		 1849 if (height <= out_height && width <= out_width)
1850 return (unsigned long) pclk;
1851
80c39712 1852 if (height > out_height) {
81ab95b7 1853 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1854
1855 tmp = pclk * height * out_width;
1856 do_div(tmp, 2 * out_height * ppl);
8b53d991 1857 core_clk = tmp;
80c39712 1858
2d9c5597
VS		 1859 if (height > 2 * out_height) {
1860 if (ppl == out_width)
1861 return 0;
1862
80c39712
TV		 1863 tmp = pclk * (height - 2 * out_height) * out_width;
1864 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1865 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1866 }
1867 }
1868
1869 if (width > out_width) {
1870 tmp = pclk * width;
1871 do_div(tmp, out_width);
8b53d991 1872 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1873
1874 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1875 core_clk <<= 1;
80c39712
TV		 1876 }
1877
8b53d991 1878 return core_clk;
80c39712
TV		 1879}
1880
8b53d991 1881static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
ff1b2cde 1882 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1883{
1884 unsigned int hf, vf;
79ee89cd 1885 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1886
1887 /*
1888 * FIXME how to determine the 'A' factor
1889 * for the no downscaling case ?
1890 */
1891
1892 if (width > 3 * out_width)
1893 hf = 4;
1894 else if (width > 2 * out_width)
1895 hf = 3;
1896 else if (width > out_width)
1897 hf = 2;
1898 else
1899 hf = 1;
1900
1901 if (height > out_height)
1902 vf = 2;
1903 else
1904 vf = 1;
1905
7282f1b7
CM		 1906 if (cpu_is_omap24xx()) {
1907 if (vf > 1 && hf > 1)
79ee89cd 1908 return pclk * 4;
7282f1b7 1909 else
79ee89cd 1910 return pclk * 2;
7282f1b7 1911 } else if (cpu_is_omap34xx()) {
79ee89cd 1912 return pclk * vf * hf;
7282f1b7 1913 } else {
79ee89cd
AT		 1914 if (hf > 1)
1915 return DIV_ROUND_UP(pclk, out_width) * width;
1916 else
1917 return pclk;
7282f1b7 1918 }
80c39712
TV		 1919}
1920
79ad75f2 1921static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 1922 enum omap_channel channel,
1923 const struct omap_video_timings *mgr_timings,
1924 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 1925 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 1926 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 1927{
1928 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1929 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1930 const int maxsinglelinewidth =
1931 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
aed74b55 1932 const int max_decim_limit = 16;
8b53d991 1933 unsigned long core_clk = 0;
aed74b55
CM		 1934 int decim_x, decim_y, error, min_factor;
1935 u16 in_width, in_height, in_width_max = 0;
79ad75f2 1936
f95cb5eb
TV		 1937 if (width == out_width && height == out_height)
1938 return 0;
1939
1940 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1941 return -EINVAL;
79ad75f2 1942
aed74b55
CM		 1943 *x_predecim = max_decim_limit;
1944 *y_predecim = max_decim_limit;
1945
1946 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
1947 color_mode == OMAP_DSS_COLOR_CLUT2 ||
1948 color_mode == OMAP_DSS_COLOR_CLUT4 ||
1949 color_mode == OMAP_DSS_COLOR_CLUT8) {
1950 *x_predecim = 1;
1951 *y_predecim = 1;
1952 *five_taps = false;
1953 return 0;
1954 }
1955
1956 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
1957 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
1958
1959 min_factor = min(decim_x, decim_y);
1960
1961 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 1962 return -EINVAL;
1963
aed74b55 1964 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 1965 return -EINVAL;
1966
7282f1b7 1967 if (cpu_is_omap24xx()) {
7282f1b7 1968 *five_taps = false;
aed74b55
CM		 1969
1970 do {
1971 in_height = DIV_ROUND_UP(height, decim_y);
1972 in_width = DIV_ROUND_UP(width, decim_x);
8b53d991 1973 core_clk = calc_core_clk(channel, in_width, in_height,
aed74b55 1974 out_width, out_height);
8b53d991
CM		 1975 error = (in_width > maxsinglelinewidth || !core_clk ||
1976 core_clk > dispc_core_clk_rate());
aed74b55
CM		 1977 if (error) {
1978 if (decim_x == decim_y) {
1979 decim_x = min_factor;
1980 decim_y++;
1981 } else {
1982 swap(decim_x, decim_y);
1983 if (decim_x < decim_y)
1984 decim_x++;
1985 }
1986 }
1987 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
1988 error);
1989
1990 if (in_width > maxsinglelinewidth) {
1991 DSSERR("Cannot scale max input width exceeded");
1992 return -EINVAL;
1993 }
7282f1b7 1994 } else if (cpu_is_omap34xx()) {
aed74b55
CM		 1995
1996 do {
1997 in_height = DIV_ROUND_UP(height, decim_y);
1998 in_width = DIV_ROUND_UP(width, decim_x);
81ab95b7
AT		 1999 core_clk = calc_core_clk_five_taps(channel, mgr_timings,
2000 in_width, in_height, out_width, out_height,
2001 color_mode);
aed74b55 2002
81ab95b7
AT		 2003 error = check_horiz_timing_omap3(channel, mgr_timings,
2004 pos_x, in_width, in_height, out_width,
2005 out_height);
7faa9233 2006
aed74b55
CM		 2007 if (in_width > maxsinglelinewidth)
2008 if (in_height > out_height &&
2009 in_height < out_height * 2)
2010 *five_taps = false;
2011 if (!*five_taps)
8b53d991
CM		 2012 core_clk = calc_core_clk(channel, in_width,
2013 in_height, out_width, out_height);
7faa9233 2014 error = (error || in_width > maxsinglelinewidth * 2 ||
aed74b55 2015 (in_width > maxsinglelinewidth && *five_taps) ||
8b53d991 2016 !core_clk || core_clk > dispc_core_clk_rate());
aed74b55
CM		 2017 if (error) {
2018 if (decim_x == decim_y) {
2019 decim_x = min_factor;
2020 decim_y++;
2021 } else {
2022 swap(decim_x, decim_y);
2023 if (decim_x < decim_y)
2024 decim_x++;
2025 }
2026 }
2027 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
2028 && error);
2029
81ab95b7
AT		 2030 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
2031 height, out_width, out_height)){
7faa9233
CM		 2032 DSSERR("horizontal timing too tight\n");
2033 return -EINVAL;
2034 }
2035
aed74b55 2036 if (in_width > (maxsinglelinewidth * 2)) {
7282f1b7
CM		 2037 DSSERR("Cannot setup scaling");
2038 DSSERR("width exceeds maximum width possible");
2039 return -EINVAL;
2040 }
aed74b55
CM		 2041
2042 if (in_width > maxsinglelinewidth && *five_taps) {
2043 DSSERR("cannot setup scaling with five taps");
2044 return -EINVAL;
7282f1b7 2045 }
7282f1b7 2046 } else {
aed74b55
CM		 2047 int decim_x_min = decim_x;
2048 in_height = DIV_ROUND_UP(height, decim_y);
8b53d991 2049 in_width_max = dispc_core_clk_rate() /
aed74b55
CM		 2050 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
2051 out_width);
2052 decim_x = DIV_ROUND_UP(width, in_width_max);
2053
2054 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
2055 if (decim_x > *x_predecim)
2056 return -EINVAL;
2057
2058 do {
2059 in_width = DIV_ROUND_UP(width, decim_x);
2060 } while (decim_x <= *x_predecim &&
2061 in_width > maxsinglelinewidth && decim_x++);
2062
2063 if (in_width > maxsinglelinewidth) {
7282f1b7
CM		 2064 DSSERR("Cannot scale width exceeds max line width");
2065 return -EINVAL;
2066 }
aed74b55 2067
8b53d991
CM		 2068 core_clk = calc_core_clk(channel, in_width, in_height,
2069 out_width, out_height);
79ad75f2
AT		 2070 }
2071
8b53d991
CM		 2072 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2073 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2074
8b53d991 2075 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2076 DSSERR("failed to set up scaling, "
8b53d991
CM		 2077 "required core clk rate = %lu Hz, "
2078 "current core clk rate = %lu Hz\n",
2079 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2080 return -EINVAL;
2081 }
2082
aed74b55
CM		 2083 *x_predecim = decim_x;
2084 *y_predecim = decim_y;
79ad75f2
AT		 2085 return 0;
2086}
2087
a4273b7c 2088int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
81ab95b7
AT		 2089 bool ilace, bool replication,
2090 const struct omap_video_timings *mgr_timings)
80c39712 2091{
79ad75f2 2092 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 2093 bool five_taps = true;
80c39712 2094 bool fieldmode = 0;
79ad75f2 2095 int r, cconv = 0;
80c39712
TV		 2096 unsigned offset0, offset1;
2097 s32 row_inc;
2098 s32 pix_inc;
a4273b7c 2099 u16 frame_height = oi->height;
80c39712 2100 unsigned int field_offset = 0;
aed74b55
CM		 2101 u16 in_height = oi->height;
2102 u16 in_width = oi->width;
2103 u16 out_width, out_height;
2cc5d1af 2104 enum omap_channel channel;
aed74b55 2105 int x_predecim = 1, y_predecim = 1;
2cc5d1af
TV		 2106
2107 channel = dispc_ovl_get_channel_out(plane);
80c39712 2108
a4273b7c 2109 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 2110 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2111 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 2112 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2113 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 2114 oi->mirror, ilace, channel, replication);
e6d80f95 2115
a4273b7c 2116 if (oi->paddr == 0)
80c39712
TV		 2117 return -EINVAL;
2118
aed74b55
CM		 2119 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2120 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 2121
aed74b55 2122 if (ilace && oi->height == out_height)
80c39712
TV		 2123 fieldmode = 1;
2124
2125 if (ilace) {
2126 if (fieldmode)
aed74b55 2127 in_height /= 2;
a4273b7c 2128 oi->pos_y /= 2;
aed74b55 2129 out_height /= 2;
80c39712
TV		 2130
2131 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2132 "out_height %d\n",
aed74b55 2133 in_height, oi->pos_y, out_height);
80c39712
TV		 2134 }
2135
a4273b7c 2136 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2137 return -EINVAL;
2138
81ab95b7
AT		 2139 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2140 in_height, out_width, out_height, oi->color_mode,
2141 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 2142 if (r)
2143 return r;
80c39712 2144
aed74b55
CM		 2145 in_width = DIV_ROUND_UP(in_width, x_predecim);
2146 in_height = DIV_ROUND_UP(in_height, y_predecim);
2147
79ad75f2
AT		 2148 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2149 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2150 oi->color_mode == OMAP_DSS_COLOR_NV12)
2151 cconv = 1;
80c39712
TV		 2152
2153 if (ilace && !fieldmode) {
2154 /*
2155 * when downscaling the bottom field may have to start several
2156 * source lines below the top field. Unfortunately ACCUI
2157 * registers will only hold the fractional part of the offset
2158 * so the integer part must be added to the base address of the
2159 * bottom field.
2160 */
aed74b55 2161 if (!in_height || in_height == out_height)
80c39712
TV		 2162 field_offset = 0;
2163 else
aed74b55 2164 field_offset = in_height / out_height / 2;
80c39712
TV		 2165 }
2166
2167 /* Fields are independent but interleaved in memory. */
2168 if (fieldmode)
2169 field_offset = 1;
2170
c6eee968
TV		 2171 offset0 = 0;
2172 offset1 = 0;
2173 row_inc = 0;
2174 pix_inc = 0;
2175
65e006ff
CM		 2176 if (oi->rotation_type == OMAP_DSS_ROT_TILER)
2177 calc_tiler_rotation_offset(oi->screen_width, in_width,
2178 oi->color_mode, fieldmode, field_offset,
2179 &offset0, &offset1, &row_inc, &pix_inc,
2180 x_predecim, y_predecim);
2181 else if (oi->rotation_type == OMAP_DSS_ROT_DMA)
a4273b7c 2182 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2183 oi->screen_width, in_width, frame_height,
a4273b7c 2184 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2185 &offset0, &offset1, &row_inc, &pix_inc,
2186 x_predecim, y_predecim);
80c39712 2187 else
a4273b7c 2188 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2189 oi->screen_width, in_width, frame_height,
a4273b7c 2190 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2191 &offset0, &offset1, &row_inc, &pix_inc,
2192 x_predecim, y_predecim);
80c39712
TV		 2193
2194 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2195 offset0, offset1, row_inc, pix_inc);
2196
a4273b7c 2197 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2198
65e006ff
CM		 2199 dispc_ovl_configure_burst_type(plane, oi->rotation_type);
2200
a4273b7c
AT		 2201 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2202 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2203
a4273b7c
AT		 2204 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2205 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2206 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2207 }
2208
2209
f0e5caab
TV		 2210 dispc_ovl_set_row_inc(plane, row_inc);
2211 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2212
aed74b55
CM		 2213 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2214 in_height, out_width, out_height);
80c39712 2215
a4273b7c 2216 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2217
aed74b55 2218 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2219
79ad75f2 2220 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2221 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2222 out_height, ilace, five_taps, fieldmode,
a4273b7c 2223 oi->color_mode, oi->rotation);
aed74b55 2224 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2225 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2226 }
2227
a4273b7c
AT		 2228 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2229 oi->color_mode);
80c39712 2230
54128701 2231 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2232 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2233 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2234
c3d92529 2235 dispc_ovl_enable_replication(plane, replication);
c3d92529 2236
80c39712
TV		 2237 return 0;
2238}
2239
f0e5caab 2240int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2241{
e6d80f95
TV		 2242 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2243
9b372c2d 2244 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2245
2246 return 0;
80c39712
TV		 2247}
2248
2249static void dispc_disable_isr(void *data, u32 mask)
2250{
2251 struct completion *compl = data;
2252 complete(compl);
2253}
2254
2a205f34 2255static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2256{
b6a44e77 2257 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 2258 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2259 /* flush posted write */
2260 dispc_read_reg(DISPC_CONTROL2);
2261 } else {
2a205f34 2262 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2263 dispc_read_reg(DISPC_CONTROL);
2264 }
80c39712
TV		 2265}
2266
26d9dd0d 2267static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2268{
2269 struct completion frame_done_completion;
2270 bool is_on;
2271 int r;
2a205f34 2272 u32 irq;
80c39712 2273
80c39712
TV		 2274 /* When we disable LCD output, we need to wait until frame is done.
2275 * Otherwise the DSS is still working, and turning off the clocks
2276 * prevents DSS from going to OFF mode */
2a205f34
SS		 2277 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2278 REG_GET(DISPC_CONTROL2, 0, 0) :
2279 REG_GET(DISPC_CONTROL, 0, 0);
2280
2281 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2282 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2283
2284 if (!enable && is_on) {
2285 init_completion(&frame_done_completion);
2286
2287 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2288 &frame_done_completion, irq);
80c39712
TV		 2289
2290 if (r)
2291 DSSERR("failed to register FRAMEDONE isr\n");
2292 }
2293
2a205f34 2294 _enable_lcd_out(channel, enable);
80c39712
TV		 2295
2296 if (!enable && is_on) {
2297 if (!wait_for_completion_timeout(&frame_done_completion,
2298 msecs_to_jiffies(100)))
2299 DSSERR("timeout waiting for FRAME DONE\n");
2300
2301 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2302 &frame_done_completion, irq);
80c39712
TV		 2303
2304 if (r)
2305 DSSERR("failed to unregister FRAMEDONE isr\n");
2306 }
80c39712
TV		 2307}
2308
2309static void _enable_digit_out(bool enable)
2310{
2311 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2312 /* flush posted write */
2313 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2314}
2315
26d9dd0d 2316static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2317{
2318 struct completion frame_done_completion;
e82b090b
TV		 2319 enum dss_hdmi_venc_clk_source_select src;
2320 int r, i;
2321 u32 irq_mask;
2322 int num_irqs;
80c39712 2323
e6d80f95 2324 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2325 return;
80c39712 2326
e82b090b
TV		 2327 src = dss_get_hdmi_venc_clk_source();
2328
80c39712
TV		 2329 if (enable) {
2330 unsigned long flags;
2331 /* When we enable digit output, we'll get an extra digit
2332 * sync lost interrupt, that we need to ignore */
2333 spin_lock_irqsave(&dispc.irq_lock, flags);
2334 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2335 _omap_dispc_set_irqs();
2336 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2337 }
2338
2339 /* When we disable digit output, we need to wait until fields are done.
2340 * Otherwise the DSS is still working, and turning off the clocks
2341 * prevents DSS from going to OFF mode. And when enabling, we need to
2342 * wait for the extra sync losts */
2343 init_completion(&frame_done_completion);
2344
e82b090b
TV		 2345 if (src == DSS_HDMI_M_PCLK && enable == false) {
2346 irq_mask = DISPC_IRQ_FRAMEDONETV;
2347 num_irqs = 1;
2348 } else {
2349 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2350 /* XXX I understand from TRM that we should only wait for the
2351 * current field to complete. But it seems we have to wait for
2352 * both fields */
2353 num_irqs = 2;
2354 }
2355
80c39712 2356 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2357 irq_mask);
80c39712 2358 if (r)
e82b090b 2359 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2360
2361 _enable_digit_out(enable);
2362
e82b090b
TV		 2363 for (i = 0; i < num_irqs; ++i) {
2364 if (!wait_for_completion_timeout(&frame_done_completion,
2365 msecs_to_jiffies(100)))
2366 DSSERR("timeout waiting for digit out to %s\n",
2367 enable ? "start" : "stop");
2368 }
80c39712 2369
e82b090b
TV		 2370 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2371 irq_mask);
80c39712 2372 if (r)
e82b090b 2373 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2374
2375 if (enable) {
2376 unsigned long flags;
2377 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2378 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2379 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2380 _omap_dispc_set_irqs();
2381 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2382 }
80c39712
TV		 2383}
2384
26d9dd0d 2385bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2386{
2387 if (channel == OMAP_DSS_CHANNEL_LCD)
2388 return !!REG_GET(DISPC_CONTROL, 0, 0);
2389 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2390 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2391 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2392 return !!REG_GET(DISPC_CONTROL2, 0, 0);
c6eee968 2393 else {
a2faee84 2394 BUG();
c6eee968
TV		 2395 return false;
2396 }
a2faee84
TV		 2397}
2398
26d9dd0d 2399void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2400{
dac57a05 2401 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2402 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2403 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2404 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2405 else
2406 BUG();
2407}
2408
80c39712
TV		 2409void dispc_lcd_enable_signal_polarity(bool act_high)
2410{
6ced40bf
AT		 2411 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2412 return;
2413
80c39712 2414 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2415}
2416
2417void dispc_lcd_enable_signal(bool enable)
2418{
6ced40bf
AT		 2419 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2420 return;
2421
80c39712 2422 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2423}
2424
2425void dispc_pck_free_enable(bool enable)
2426{
6ced40bf
AT		 2427 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2428 return;
2429
80c39712 2430 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2431}
2432
26d9dd0d 2433void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2434{
2a205f34
SS		 2435 if (channel == OMAP_DSS_CHANNEL_LCD2)
2436 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2437 else
2438 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2439}
2440
2441
26d9dd0d 2442void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2443 enum omap_lcd_display_type type)
80c39712
TV		 2444{
2445 int mode;
2446
2447 switch (type) {
2448 case OMAP_DSS_LCD_DISPLAY_STN:
2449 mode = 0;
2450 break;
2451
2452 case OMAP_DSS_LCD_DISPLAY_TFT:
2453 mode = 1;
2454 break;
2455
2456 default:
2457 BUG();
2458 return;
2459 }
2460
2a205f34
SS		 2461 if (channel == OMAP_DSS_CHANNEL_LCD2)
2462 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2463 else
2464 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2465}
2466
2467void dispc_set_loadmode(enum omap_dss_load_mode mode)
2468{
80c39712 2469 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2470}
2471
2472
c64dca40 2473static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2474{
8613b000 2475 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2476}
2477
c64dca40 2478static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2479 enum omap_dss_trans_key_type type,
2480 u32 trans_key)
2481{
80c39712
TV		 2482 if (ch == OMAP_DSS_CHANNEL_LCD)
2483 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2484 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2485 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2486 else /* OMAP_DSS_CHANNEL_LCD2 */
2487 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2488
8613b000 2489 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2490}
2491
c64dca40 2492static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2493{
80c39712
TV		 2494 if (ch == OMAP_DSS_CHANNEL_LCD)
2495 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2496 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2497 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2498 else /* OMAP_DSS_CHANNEL_LCD2 */
2499 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2500}
11354dd5 2501
c64dca40
TV		 2502static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2503 bool enable)
80c39712 2504{
11354dd5 2505 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2506 return;
2507
80c39712
TV		 2508 if (ch == OMAP_DSS_CHANNEL_LCD)
2509 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2510 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2511 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2512}
11354dd5 2513
c64dca40
TV		 2514void dispc_mgr_setup(enum omap_channel channel,
2515 struct omap_overlay_manager_info *info)
2516{
2517 dispc_mgr_set_default_color(channel, info->default_color);
2518 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2519 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2520 dispc_mgr_enable_alpha_fixed_zorder(channel,
2521 info->partial_alpha_enabled);
2522 if (dss_has_feature(FEAT_CPR)) {
2523 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2524 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2525 }
2526}
80c39712 2527
26d9dd0d 2528void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2529{
2530 int code;
2531
2532 switch (data_lines) {
2533 case 12:
2534 code = 0;
2535 break;
2536 case 16:
2537 code = 1;
2538 break;
2539 case 18:
2540 code = 2;
2541 break;
2542 case 24:
2543 code = 3;
2544 break;
2545 default:
2546 BUG();
2547 return;
2548 }
2549
2a205f34
SS		 2550 if (channel == OMAP_DSS_CHANNEL_LCD2)
2551 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2552 else
2553 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2554}
2555
569969d6 2556void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2557{
2558 u32 l;
569969d6 2559 int gpout0, gpout1;
80c39712
TV		 2560
2561 switch (mode) {
569969d6
AT		 2562 case DSS_IO_PAD_MODE_RESET:
2563 gpout0 = 0;
2564 gpout1 = 0;
80c39712 2565 break;
569969d6
AT		 2566 case DSS_IO_PAD_MODE_RFBI:
2567 gpout0 = 1;
80c39712
TV		 2568 gpout1 = 0;
2569 break;
569969d6
AT		 2570 case DSS_IO_PAD_MODE_BYPASS:
2571 gpout0 = 1;
80c39712
TV		 2572 gpout1 = 1;
2573 break;
80c39712
TV		 2574 default:
2575 BUG();
2576 return;
2577 }
2578
569969d6
AT		 2579 l = dispc_read_reg(DISPC_CONTROL);
2580 l = FLD_MOD(l, gpout0, 15, 15);
2581 l = FLD_MOD(l, gpout1, 16, 16);
2582 dispc_write_reg(DISPC_CONTROL, l);
2583}
2584
2585void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2586{
2587 if (channel == OMAP_DSS_CHANNEL_LCD2)
2588 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2589 else
2590 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2591}
2592
8f366162
AT		 2593static bool _dispc_mgr_size_ok(u16 width, u16 height)
2594{
2595 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2596 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2597}
2598
80c39712
TV		 2599static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2600 int vsw, int vfp, int vbp)
2601{
2602 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2603 if (hsw < 1 || hsw > 64 ||
2604 hfp < 1 || hfp > 256 ||
2605 hbp < 1 || hbp > 256 ||
2606 vsw < 1 || vsw > 64 ||
2607 vfp < 0 || vfp > 255 ||
2608 vbp < 0 || vbp > 255)
2609 return false;
2610 } else {
2611 if (hsw < 1 || hsw > 256 ||
2612 hfp < 1 || hfp > 4096 ||
2613 hbp < 1 || hbp > 4096 ||
2614 vsw < 1 || vsw > 256 ||
2615 vfp < 0 || vfp > 4095 ||
2616 vbp < 0 || vbp > 4095)
2617 return false;
2618 }
2619
2620 return true;
2621}
2622
8f366162 2623bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2624 const struct omap_video_timings *timings)
80c39712 2625{
8f366162
AT		 2626 bool timings_ok;
2627
2628 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2629
2630 if (dispc_mgr_is_lcd(channel))
2631 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2632 timings->hfp, timings->hbp,
2633 timings->vsw, timings->vfp,
2634 timings->vbp);
2635
2636 return timings_ok;
80c39712
TV		 2637}
2638
26d9dd0d 2639static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2640 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2641{
2642 u32 timing_h, timing_v;
2643
2644 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2645 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2646 FLD_VAL(hbp-1, 27, 20);
2647
2648 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2649 FLD_VAL(vbp, 27, 20);
2650 } else {
2651 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2652 FLD_VAL(hbp-1, 31, 20);
2653
2654 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2655 FLD_VAL(vbp, 31, 20);
2656 }
2657
64ba4f74
SS		 2658 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2659 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2660}
2661
2662/* change name to mode? */
c51d921a 2663void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2664 struct omap_video_timings *timings)
80c39712
TV		 2665{
2666 unsigned xtot, ytot;
2667 unsigned long ht, vt;
2668
c51d921a
AT		 2669 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2670 timings->y_res);
80c39712 2671
c6eee968 2672 if (!dispc_mgr_timings_ok(channel, timings)) {
8f366162 2673 BUG();
c6eee968
TV		 2674 return;
2675 }
80c39712 2676
8f366162 2677 if (dispc_mgr_is_lcd(channel)) {
c51d921a
AT		 2678 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2679 timings->hbp, timings->vsw, timings->vfp,
2680 timings->vbp);
80c39712 2681
c51d921a
AT		 2682 xtot = timings->x_res + timings->hfp + timings->hsw +
2683 timings->hbp;
2684 ytot = timings->y_res + timings->vfp + timings->vsw +
2685 timings->vbp;
80c39712 2686
c51d921a
AT		 2687 ht = (timings->pixel_clock * 1000) / xtot;
2688 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2689
2690 DSSDBG("pck %u\n", timings->pixel_clock);
2691 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
80c39712
TV		 2692 timings->hsw, timings->hfp, timings->hbp,
2693 timings->vsw, timings->vfp, timings->vbp);
2694
c51d921a 2695 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
c51d921a 2696 }
8f366162
AT		 2697
2698 dispc_mgr_set_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2699}
2700
26d9dd0d 2701static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2702 u16 pck_div)
80c39712
TV		 2703{
2704 BUG_ON(lck_div < 1);
9eaaf207 2705 BUG_ON(pck_div < 1);
80c39712 2706
ce7fa5eb 2707 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2708 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2709}
2710
26d9dd0d 2711static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2712 int *pck_div)
80c39712
TV		 2713{
2714 u32 l;
ce7fa5eb 2715 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2716 *lck_div = FLD_GET(l, 23, 16);
2717 *pck_div = FLD_GET(l, 7, 0);
2718}
2719
2720unsigned long dispc_fclk_rate(void)
2721{
a72b64b9 2722 struct platform_device *dsidev;
80c39712
TV		 2723 unsigned long r = 0;
2724
66534e8e 2725 switch (dss_get_dispc_clk_source()) {
89a35e51 2726 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2727 r = clk_get_rate(dispc.dss_clk);
66534e8e 2728 break;
89a35e51 2729 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2730 dsidev = dsi_get_dsidev_from_id(0);
2731 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2732 break;
5a8b572d
AT		 2733 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2734 dsidev = dsi_get_dsidev_from_id(1);
2735 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2736 break;
66534e8e
TA		 2737 default:
2738 BUG();
c6eee968 2739 return 0;
66534e8e
TA		 2740 }
2741
80c39712
TV		 2742 return r;
2743}
2744
26d9dd0d 2745unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2746{
a72b64b9 2747 struct platform_device *dsidev;
80c39712
TV		 2748 int lcd;
2749 unsigned long r;
2750 u32 l;
2751
ce7fa5eb 2752 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2753
2754 lcd = FLD_GET(l, 23, 16);
2755
ea75159e 2756 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2757 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2758 r = clk_get_rate(dispc.dss_clk);
ea75159e 2759 break;
89a35e51 2760 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2761 dsidev = dsi_get_dsidev_from_id(0);
2762 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2763 break;
5a8b572d
AT		 2764 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2765 dsidev = dsi_get_dsidev_from_id(1);
2766 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2767 break;
ea75159e
TA		 2768 default:
2769 BUG();
c6eee968 2770 return 0;
ea75159e 2771 }
80c39712
TV		 2772
2773 return r / lcd;
2774}
2775
26d9dd0d 2776unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2777{
80c39712 2778 unsigned long r;
80c39712 2779
c3dc6a7a
AT		 2780 if (dispc_mgr_is_lcd(channel)) {
2781 int pcd;
2782 u32 l;
80c39712 2783
c3dc6a7a 2784 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2785
c3dc6a7a 2786 pcd = FLD_GET(l, 7, 0);
80c39712 2787
c3dc6a7a
AT		 2788 r = dispc_mgr_lclk_rate(channel);
2789
2790 return r / pcd;
2791 } else {
3fa03ba8 2792 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2793
3fa03ba8
AT		 2794 source = dss_get_hdmi_venc_clk_source();
2795
2796 switch (source) {
2797 case DSS_VENC_TV_CLK:
c3dc6a7a 2798 return venc_get_pixel_clock();
3fa03ba8 2799 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2800 return hdmi_get_pixel_clock();
2801 default:
2802 BUG();
c6eee968 2803 return 0;
c3dc6a7a
AT		 2804 }
2805 }
80c39712
TV		 2806}
2807
8b53d991
CM		 2808unsigned long dispc_core_clk_rate(void)
2809{
2810 int lcd;
2811 unsigned long fclk = dispc_fclk_rate();
2812
2813 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2814 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2815 else
2816 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2817
2818 return fclk / lcd;
2819}
2820
80c39712
TV		 2821void dispc_dump_clocks(struct seq_file *s)
2822{
2823 int lcd, pcd;
0cf35df3 2824 u32 l;
89a35e51
AT		 2825 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2826 enum omap_dss_clk_source lcd_clk_src;
80c39712 2827
4fbafaf3
TV		 2828 if (dispc_runtime_get())
2829 return;
80c39712 2830
80c39712
TV		 2831 seq_printf(s, "- DISPC -\n");
2832
067a57e4
AT		 2833 seq_printf(s, "dispc fclk source = %s (%s)\n",
2834 dss_get_generic_clk_source_name(dispc_clk_src),
2835 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2836
2837 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2838
0cf35df3
MR		 2839 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2840 seq_printf(s, "- DISPC-CORE-CLK -\n");
2841 l = dispc_read_reg(DISPC_DIVISOR);
2842 lcd = FLD_GET(l, 23, 16);
2843
2844 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2845 (dispc_fclk_rate()/lcd), lcd);
2846 }
2a205f34
SS		 2847 seq_printf(s, "- LCD1 -\n");
2848
ea75159e
TA		 2849 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2850
2851 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2852 dss_get_generic_clk_source_name(lcd_clk_src),
2853 dss_feat_get_clk_source_name(lcd_clk_src));
2854
26d9dd0d 2855 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2856
ff1b2cde 2857 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2858 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2859 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2860 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2861 if (dss_has_feature(FEAT_MGR_LCD2)) {
2862 seq_printf(s, "- LCD2 -\n");
2863
ea75159e
TA		 2864 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2865
2866 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2867 dss_get_generic_clk_source_name(lcd_clk_src),
2868 dss_feat_get_clk_source_name(lcd_clk_src));
2869
26d9dd0d 2870 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2871
2a205f34 2872 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2873 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2874 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2875 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2876 }
4fbafaf3
TV		 2877
2878 dispc_runtime_put();
80c39712
TV		 2879}
2880
dfc0fd8d
TV		 2881#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2882void dispc_dump_irqs(struct seq_file *s)
2883{
2884 unsigned long flags;
2885 struct dispc_irq_stats stats;
2886
2887 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2888
2889 stats = dispc.irq_stats;
2890 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2891 dispc.irq_stats.last_reset = jiffies;
2892
2893 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2894
2895 seq_printf(s, "period %u ms\n",
2896 jiffies_to_msecs(jiffies - stats.last_reset));
2897
2898 seq_printf(s, "irqs %d\n", stats.irq_count);
2899#define PIS(x) \
2900 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2901
2902 PIS(FRAMEDONE);
2903 PIS(VSYNC);
2904 PIS(EVSYNC_EVEN);
2905 PIS(EVSYNC_ODD);
2906 PIS(ACBIAS_COUNT_STAT);
2907 PIS(PROG_LINE_NUM);
2908 PIS(GFX_FIFO_UNDERFLOW);
2909 PIS(GFX_END_WIN);
2910 PIS(PAL_GAMMA_MASK);
2911 PIS(OCP_ERR);
2912 PIS(VID1_FIFO_UNDERFLOW);
2913 PIS(VID1_END_WIN);
2914 PIS(VID2_FIFO_UNDERFLOW);
2915 PIS(VID2_END_WIN);
b8c095b4
AT		 2916 if (dss_feat_get_num_ovls() > 3) {
2917 PIS(VID3_FIFO_UNDERFLOW);
2918 PIS(VID3_END_WIN);
2919 }
dfc0fd8d
TV		 2920 PIS(SYNC_LOST);
2921 PIS(SYNC_LOST_DIGIT);
2922 PIS(WAKEUP);
2a205f34
SS		 2923 if (dss_has_feature(FEAT_MGR_LCD2)) {
2924 PIS(FRAMEDONE2);
2925 PIS(VSYNC2);
2926 PIS(ACBIAS_COUNT_STAT2);
2927 PIS(SYNC_LOST2);
2928 }
dfc0fd8d
TV		 2929#undef PIS
2930}
dfc0fd8d
TV		 2931#endif
2932
e40402cf 2933static void dispc_dump_regs(struct seq_file *s)
80c39712 2934{
4dd2da15
AT		 2935 int i, j;
2936 const char *mgr_names[] = {
2937 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2938 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2939 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2940 };
2941 const char *ovl_names[] = {
2942 [OMAP_DSS_GFX] = "GFX",
2943 [OMAP_DSS_VIDEO1] = "VID1",
2944 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2945 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2946 };
2947 const char **p_names;
2948
9b372c2d 2949#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2950
4fbafaf3
TV		 2951 if (dispc_runtime_get())
2952 return;
80c39712 2953
5010be80 2954 /* DISPC common registers */
80c39712
TV		 2955 DUMPREG(DISPC_REVISION);
2956 DUMPREG(DISPC_SYSCONFIG);
2957 DUMPREG(DISPC_SYSSTATUS);
2958 DUMPREG(DISPC_IRQSTATUS);
2959 DUMPREG(DISPC_IRQENABLE);
2960 DUMPREG(DISPC_CONTROL);
2961 DUMPREG(DISPC_CONFIG);
2962 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2963 DUMPREG(DISPC_LINE_STATUS);
2964 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2965 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2966 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2967 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2968 if (dss_has_feature(FEAT_MGR_LCD2)) {
2969 DUMPREG(DISPC_CONTROL2);
2970 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2971 }
2972
2973#undef DUMPREG
2974
2975#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2976#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2977 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2978 dispc_read_reg(DISPC_REG(i, r)))
2979
4dd2da15 2980 p_names = mgr_names;
5010be80 2981
4dd2da15
AT		 2982 /* DISPC channel specific registers */
2983 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2984 DUMPREG(i, DISPC_DEFAULT_COLOR);
2985 DUMPREG(i, DISPC_TRANS_COLOR);
2986 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2987
4dd2da15
AT		 2988 if (i == OMAP_DSS_CHANNEL_DIGIT)
2989 continue;
5010be80 2990
4dd2da15
AT		 2991 DUMPREG(i, DISPC_DEFAULT_COLOR);
2992 DUMPREG(i, DISPC_TRANS_COLOR);
2993 DUMPREG(i, DISPC_TIMING_H);
2994 DUMPREG(i, DISPC_TIMING_V);
2995 DUMPREG(i, DISPC_POL_FREQ);
2996 DUMPREG(i, DISPC_DIVISORo);
2997 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2998
4dd2da15
AT		 2999 DUMPREG(i, DISPC_DATA_CYCLE1);
3000 DUMPREG(i, DISPC_DATA_CYCLE2);
3001 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3002
332e9d70 3003 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3004 DUMPREG(i, DISPC_CPR_COEF_R);
3005 DUMPREG(i, DISPC_CPR_COEF_G);
3006 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3007 }
2a205f34 3008 }
80c39712 3009
4dd2da15
AT		 3010 p_names = ovl_names;
3011
3012 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3013 DUMPREG(i, DISPC_OVL_BA0);
3014 DUMPREG(i, DISPC_OVL_BA1);
3015 DUMPREG(i, DISPC_OVL_POSITION);
3016 DUMPREG(i, DISPC_OVL_SIZE);
3017 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3018 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3019 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3020 DUMPREG(i, DISPC_OVL_ROW_INC);
3021 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3022 if (dss_has_feature(FEAT_PRELOAD))
3023 DUMPREG(i, DISPC_OVL_PRELOAD);
3024
3025 if (i == OMAP_DSS_GFX) {
3026 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3027 DUMPREG(i, DISPC_OVL_TABLE_BA);
3028 continue;
3029 }
3030
3031 DUMPREG(i, DISPC_OVL_FIR);
3032 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3033 DUMPREG(i, DISPC_OVL_ACCU0);
3034 DUMPREG(i, DISPC_OVL_ACCU1);
3035 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3036 DUMPREG(i, DISPC_OVL_BA0_UV);
3037 DUMPREG(i, DISPC_OVL_BA1_UV);
3038 DUMPREG(i, DISPC_OVL_FIR2);
3039 DUMPREG(i, DISPC_OVL_ACCU2_0);
3040 DUMPREG(i, DISPC_OVL_ACCU2_1);
3041 }
3042 if (dss_has_feature(FEAT_ATTR2))
3043 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3044 if (dss_has_feature(FEAT_PRELOAD))
3045 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3046 }
5010be80
AT		 3047
3048#undef DISPC_REG
3049#undef DUMPREG
3050
3051#define DISPC_REG(plane, name, i) name(plane, i)
3052#define DUMPREG(plane, name, i) \
4dd2da15
AT		 3053 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3054 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 3055 dispc_read_reg(DISPC_REG(plane, name, i)))
3056
4dd2da15 3057 /* Video pipeline coefficient registers */
332e9d70 3058
4dd2da15
AT		 3059 /* start from OMAP_DSS_VIDEO1 */
3060 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3061 for (j = 0; j < 8; j++)
3062 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3063
4dd2da15
AT		 3064 for (j = 0; j < 8; j++)
3065 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3066
4dd2da15
AT		 3067 for (j = 0; j < 5; j++)
3068 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3069
4dd2da15
AT		 3070 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3071 for (j = 0; j < 8; j++)
3072 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3073 }
3074
3075 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3076 for (j = 0; j < 8; j++)
3077 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3078
3079 for (j = 0; j < 8; j++)
3080 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3081
3082 for (j = 0; j < 8; j++)
3083 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3084 }
332e9d70 3085 }
80c39712 3086
4fbafaf3 3087 dispc_runtime_put();
5010be80
AT		 3088
3089#undef DISPC_REG
80c39712
TV		 3090#undef DUMPREG
3091}
3092
26d9dd0d
TV		 3093static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
3094 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
3095 u8 acb)
80c39712
TV		 3096{
3097 u32 l = 0;
3098
3099 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
3100 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
3101
3102 l |= FLD_VAL(onoff, 17, 17);
3103 l |= FLD_VAL(rf, 16, 16);
3104 l |= FLD_VAL(ieo, 15, 15);
3105 l |= FLD_VAL(ipc, 14, 14);
3106 l |= FLD_VAL(ihs, 13, 13);
3107 l |= FLD_VAL(ivs, 12, 12);
3108 l |= FLD_VAL(acbi, 11, 8);
3109 l |= FLD_VAL(acb, 7, 0);
3110
ff1b2cde 3111 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3112}
3113
26d9dd0d 3114void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 3115 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 3116{
26d9dd0d 3117 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 3118 (config & OMAP_DSS_LCD_RF) != 0,
3119 (config & OMAP_DSS_LCD_IEO) != 0,
3120 (config & OMAP_DSS_LCD_IPC) != 0,
3121 (config & OMAP_DSS_LCD_IHS) != 0,
3122 (config & OMAP_DSS_LCD_IVS) != 0,
3123 acbi, acb);
3124}
3125
3126/* with fck as input clock rate, find dispc dividers that produce req_pck */
3127void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3128 struct dispc_clock_info *cinfo)
3129{
9eaaf207 3130 u16 pcd_min, pcd_max;
80c39712
TV		 3131 unsigned long best_pck;
3132 u16 best_ld, cur_ld;
3133 u16 best_pd, cur_pd;
3134
9eaaf207
TV		 3135 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3136 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3137
3138 if (!is_tft)
3139 pcd_min = 3;
3140
80c39712
TV		 3141 best_pck = 0;
3142 best_ld = 0;
3143 best_pd = 0;
3144
3145 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3146 unsigned long lck = fck / cur_ld;
3147
9eaaf207 3148 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3149 unsigned long pck = lck / cur_pd;
3150 long old_delta = abs(best_pck - req_pck);
3151 long new_delta = abs(pck - req_pck);
3152
3153 if (best_pck == 0 || new_delta < old_delta) {
3154 best_pck = pck;
3155 best_ld = cur_ld;
3156 best_pd = cur_pd;
3157
3158 if (pck == req_pck)
3159 goto found;
3160 }
3161
3162 if (pck < req_pck)
3163 break;
3164 }
3165
3166 if (lck / pcd_min < req_pck)
3167 break;
3168 }
3169
3170found:
3171 cinfo->lck_div = best_ld;
3172 cinfo->pck_div = best_pd;
3173 cinfo->lck = fck / cinfo->lck_div;
3174 cinfo->pck = cinfo->lck / cinfo->pck_div;
3175}
3176
3177/* calculate clock rates using dividers in cinfo */
3178int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3179 struct dispc_clock_info *cinfo)
3180{
3181 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3182 return -EINVAL;
9eaaf207 3183 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3184 return -EINVAL;
3185
3186 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3187 cinfo->pck = cinfo->lck / cinfo->pck_div;
3188
3189 return 0;
3190}
3191
26d9dd0d 3192int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3193 struct dispc_clock_info *cinfo)
80c39712
TV		 3194{
3195 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3196 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3197
26d9dd0d 3198 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3199
3200 return 0;
3201}
3202
26d9dd0d 3203int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3204 struct dispc_clock_info *cinfo)
80c39712
TV		 3205{
3206 unsigned long fck;
3207
3208 fck = dispc_fclk_rate();
3209
ce7fa5eb
MR		 3210 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3211 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3212
3213 cinfo->lck = fck / cinfo->lck_div;
3214 cinfo->pck = cinfo->lck / cinfo->pck_div;
3215
3216 return 0;
3217}
3218
3219/* dispc.irq_lock has to be locked by the caller */
3220static void _omap_dispc_set_irqs(void)
3221{
3222 u32 mask;
3223 u32 old_mask;
3224 int i;
3225 struct omap_dispc_isr_data *isr_data;
3226
3227 mask = dispc.irq_error_mask;
3228
3229 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3230 isr_data = &dispc.registered_isr[i];
3231
3232 if (isr_data->isr == NULL)
3233 continue;
3234
3235 mask |= isr_data->mask;
3236 }
3237
80c39712
TV		 3238 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3239 /* clear the irqstatus for newly enabled irqs */
3240 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3241
3242 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3243}
3244
3245int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3246{
3247 int i;
3248 int ret;
3249 unsigned long flags;
3250 struct omap_dispc_isr_data *isr_data;
3251
3252 if (isr == NULL)
3253 return -EINVAL;
3254
3255 spin_lock_irqsave(&dispc.irq_lock, flags);
3256
3257 /* check for duplicate entry */
3258 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3259 isr_data = &dispc.registered_isr[i];
3260 if (isr_data->isr == isr && isr_data->arg == arg &&
3261 isr_data->mask == mask) {
3262 ret = -EINVAL;
3263 goto err;
3264 }
3265 }
3266
3267 isr_data = NULL;
3268 ret = -EBUSY;
3269
3270 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3271 isr_data = &dispc.registered_isr[i];
3272
3273 if (isr_data->isr != NULL)
3274 continue;
3275
3276 isr_data->isr = isr;
3277 isr_data->arg = arg;
3278 isr_data->mask = mask;
3279 ret = 0;
3280
3281 break;
3282 }
3283
b9cb0984
TV		 3284 if (ret)
3285 goto err;
3286
80c39712
TV		 3287 _omap_dispc_set_irqs();
3288
3289 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3290
3291 return 0;
3292err:
3293 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3294
3295 return ret;
3296}
3297EXPORT_SYMBOL(omap_dispc_register_isr);
3298
3299int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3300{
3301 int i;
3302 unsigned long flags;
3303 int ret = -EINVAL;
3304 struct omap_dispc_isr_data *isr_data;
3305
3306 spin_lock_irqsave(&dispc.irq_lock, flags);
3307
3308 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3309 isr_data = &dispc.registered_isr[i];
3310 if (isr_data->isr != isr || isr_data->arg != arg ||
3311 isr_data->mask != mask)
3312 continue;
3313
3314 /* found the correct isr */
3315
3316 isr_data->isr = NULL;
3317 isr_data->arg = NULL;
3318 isr_data->mask = 0;
3319
3320 ret = 0;
3321 break;
3322 }
3323
3324 if (ret == 0)
3325 _omap_dispc_set_irqs();
3326
3327 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3328
3329 return ret;
3330}
3331EXPORT_SYMBOL(omap_dispc_unregister_isr);
3332
3333#ifdef DEBUG
3334static void print_irq_status(u32 status)
3335{
3336 if ((status & dispc.irq_error_mask) == 0)
3337 return;
3338
3339 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3340
3341#define PIS(x) \
3342 if (status & DISPC_IRQ_##x) \
3343 printk(#x " ");
3344 PIS(GFX_FIFO_UNDERFLOW);
3345 PIS(OCP_ERR);
3346 PIS(VID1_FIFO_UNDERFLOW);
3347 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3348 if (dss_feat_get_num_ovls() > 3)
3349 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3350 PIS(SYNC_LOST);
3351 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3352 if (dss_has_feature(FEAT_MGR_LCD2))
3353 PIS(SYNC_LOST2);
80c39712
TV		 3354#undef PIS
3355
3356 printk("\n");
3357}
3358#endif
3359
3360/* Called from dss.c. Note that we don't touch clocks here,
3361 * but we presume they are on because we got an IRQ. However,
3362 * an irq handler may turn the clocks off, so we may not have
3363 * clock later in the function. */
affe360d 3364static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3365{
3366 int i;
affe360d 3367 u32 irqstatus, irqenable;
80c39712
TV		 3368 u32 handledirqs = 0;
3369 u32 unhandled_errors;
3370 struct omap_dispc_isr_data *isr_data;
3371 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3372
3373 spin_lock(&dispc.irq_lock);
3374
3375 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3376 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3377
3378 /* IRQ is not for us */
3379 if (!(irqstatus & irqenable)) {
3380 spin_unlock(&dispc.irq_lock);
3381 return IRQ_NONE;
3382 }
80c39712 3383
dfc0fd8d
TV		 3384#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3385 spin_lock(&dispc.irq_stats_lock);
3386 dispc.irq_stats.irq_count++;
3387 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3388 spin_unlock(&dispc.irq_stats_lock);
3389#endif
3390
80c39712
TV		 3391#ifdef DEBUG
3392 if (dss_debug)
3393 print_irq_status(irqstatus);
3394#endif
3395 /* Ack the interrupt. Do it here before clocks are possibly turned
3396 * off */
3397 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3398 /* flush posted write */
3399 dispc_read_reg(DISPC_IRQSTATUS);
3400
3401 /* make a copy and unlock, so that isrs can unregister
3402 * themselves */
3403 memcpy(registered_isr, dispc.registered_isr,
3404 sizeof(registered_isr));
3405
3406 spin_unlock(&dispc.irq_lock);
3407
3408 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3409 isr_data = &registered_isr[i];
3410
3411 if (!isr_data->isr)
3412 continue;
3413
3414 if (isr_data->mask & irqstatus) {
3415 isr_data->isr(isr_data->arg, irqstatus);
3416 handledirqs |= isr_data->mask;
3417 }
3418 }
3419
3420 spin_lock(&dispc.irq_lock);
3421
3422 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3423
3424 if (unhandled_errors) {
3425 dispc.error_irqs |= unhandled_errors;
3426
3427 dispc.irq_error_mask &= ~unhandled_errors;
3428 _omap_dispc_set_irqs();
3429
3430 schedule_work(&dispc.error_work);
3431 }
3432
3433 spin_unlock(&dispc.irq_lock);
affe360d 3434
3435 return IRQ_HANDLED;
80c39712
TV		 3436}
3437
3438static void dispc_error_worker(struct work_struct *work)
3439{
3440 int i;
3441 u32 errors;
3442 unsigned long flags;
fe3cc9d6
TV		 3443 static const unsigned fifo_underflow_bits[] = {
3444 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3445 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3446 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3447 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3448 };
3449
3450 static const unsigned sync_lost_bits[] = {
3451 DISPC_IRQ_SYNC_LOST,
3452 DISPC_IRQ_SYNC_LOST_DIGIT,
3453 DISPC_IRQ_SYNC_LOST2,
3454 };
80c39712
TV		 3455
3456 spin_lock_irqsave(&dispc.irq_lock, flags);
3457 errors = dispc.error_irqs;
3458 dispc.error_irqs = 0;
3459 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3460
13eae1f9
DZ		 3461 dispc_runtime_get();
3462
fe3cc9d6
TV		 3463 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3464 struct omap_overlay *ovl;
3465 unsigned bit;
80c39712 3466
fe3cc9d6
TV		 3467 ovl = omap_dss_get_overlay(i);
3468 bit = fifo_underflow_bits[i];
80c39712 3469
fe3cc9d6
TV		 3470 if (bit & errors) {
3471 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3472 ovl->name);
f0e5caab 3473 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3474 dispc_mgr_go(ovl->manager->id);
80c39712 3475 mdelay(50);
80c39712
TV		 3476 }
3477 }
3478
fe3cc9d6
TV		 3479 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3480 struct omap_overlay_manager *mgr;
3481 unsigned bit;
80c39712 3482
fe3cc9d6
TV		 3483 mgr = omap_dss_get_overlay_manager(i);
3484 bit = sync_lost_bits[i];
80c39712 3485
fe3cc9d6
TV		 3486 if (bit & errors) {
3487 struct omap_dss_device *dssdev = mgr->device;
3488 bool enable;
80c39712 3489
fe3cc9d6
TV		 3490 DSSERR("SYNC_LOST on channel %s, restarting the output "
3491 "with video overlays disabled\n",
3492 mgr->name);
2a205f34 3493
fe3cc9d6
TV		 3494 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3495 dssdev->driver->disable(dssdev);
2a205f34 3496
2a205f34
SS		 3497 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3498 struct omap_overlay *ovl;
3499 ovl = omap_dss_get_overlay(i);
3500
fe3cc9d6
TV		 3501 if (ovl->id != OMAP_DSS_GFX &&
3502 ovl->manager == mgr)
f0e5caab 3503 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3504 }
3505
26d9dd0d 3506 dispc_mgr_go(mgr->id);
2a205f34 3507 mdelay(50);
fe3cc9d6 3508
2a205f34
SS		 3509 if (enable)
3510 dssdev->driver->enable(dssdev);
3511 }
3512 }
3513
80c39712
TV		 3514 if (errors & DISPC_IRQ_OCP_ERR) {
3515 DSSERR("OCP_ERR\n");
3516 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3517 struct omap_overlay_manager *mgr;
3518 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3519 if (mgr->device && mgr->device->driver)
3520 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3521 }
3522 }
3523
3524 spin_lock_irqsave(&dispc.irq_lock, flags);
3525 dispc.irq_error_mask |= errors;
3526 _omap_dispc_set_irqs();
3527 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3528
3529 dispc_runtime_put();
80c39712
TV		 3530}
3531
3532int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3533{
3534 void dispc_irq_wait_handler(void *data, u32 mask)
3535 {
3536 complete((struct completion *)data);
3537 }
3538
3539 int r;
3540 DECLARE_COMPLETION_ONSTACK(completion);
3541
3542 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3543 irqmask);
3544
3545 if (r)
3546 return r;
3547
3548 timeout = wait_for_completion_timeout(&completion, timeout);
3549
3550 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3551
3552 if (timeout == 0)
3553 return -ETIMEDOUT;
3554
3555 if (timeout == -ERESTARTSYS)
3556 return -ERESTARTSYS;
3557
3558 return 0;
3559}
3560
3561int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3562 unsigned long timeout)
3563{
3564 void dispc_irq_wait_handler(void *data, u32 mask)
3565 {
3566 complete((struct completion *)data);
3567 }
3568
3569 int r;
3570 DECLARE_COMPLETION_ONSTACK(completion);
3571
3572 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3573 irqmask);
3574
3575 if (r)
3576 return r;
3577
3578 timeout = wait_for_completion_interruptible_timeout(&completion,
3579 timeout);
3580
3581 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3582
3583 if (timeout == 0)
3584 return -ETIMEDOUT;
3585
3586 if (timeout == -ERESTARTSYS)
3587 return -ERESTARTSYS;
3588
3589 return 0;
3590}
3591
80c39712
TV		 3592static void _omap_dispc_initialize_irq(void)
3593{
3594 unsigned long flags;
3595
3596 spin_lock_irqsave(&dispc.irq_lock, flags);
3597
3598 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3599
3600 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3601 if (dss_has_feature(FEAT_MGR_LCD2))
3602 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3603 if (dss_feat_get_num_ovls() > 3)
3604 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3605
3606 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3607 * so clear it */
3608 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3609
3610 _omap_dispc_set_irqs();
3611
3612 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3613}
3614
3615void dispc_enable_sidle(void)
3616{
3617 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3618}
3619
3620void dispc_disable_sidle(void)
3621{
3622 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3623}
3624
3625static void _omap_dispc_initial_config(void)
3626{
3627 u32 l;
3628
0cf35df3
MR		 3629 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3630 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3631 l = dispc_read_reg(DISPC_DIVISOR);
3632 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3633 l = FLD_MOD(l, 1, 0, 0);
3634 l = FLD_MOD(l, 1, 23, 16);
3635 dispc_write_reg(DISPC_DIVISOR, l);
3636 }
3637
80c39712 3638 /* FUNCGATED */
6ced40bf
AT		 3639 if (dss_has_feature(FEAT_FUNCGATED))
3640 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3641
80c39712
TV		 3642 _dispc_setup_color_conv_coef();
3643
3644 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3645
3646 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3647
3648 dispc_configure_burst_sizes();
54128701
AT		 3649
3650 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3651}
3652
060b6d9c 3653/* DISPC HW IP initialisation */
6e7e8f06 3654static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3655{
3656 u32 rev;
affe360d 3657 int r = 0;
ea9da36a 3658 struct resource *dispc_mem;
4fbafaf3 3659 struct clk *clk;
ea9da36a 3660
060b6d9c
SG		 3661 dispc.pdev = pdev;
3662
3663 spin_lock_init(&dispc.irq_lock);
3664
3665#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3666 spin_lock_init(&dispc.irq_stats_lock);
3667 dispc.irq_stats.last_reset = jiffies;
3668#endif
3669
3670 INIT_WORK(&dispc.error_work, dispc_error_worker);
3671
ea9da36a
SG		 3672 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3673 if (!dispc_mem) {
3674 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3675 return -EINVAL;
ea9da36a 3676 }
cd3b3449 3677
6e2a14d2
JL		 3678 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3679 resource_size(dispc_mem));
060b6d9c
SG		 3680 if (!dispc.base) {
3681 DSSERR("can't ioremap DISPC\n");
cd3b3449 3682 return -ENOMEM;
affe360d 3683 }
cd3b3449 3684
affe360d 3685 dispc.irq = platform_get_irq(dispc.pdev, 0);
3686 if (dispc.irq < 0) {
3687 DSSERR("platform_get_irq failed\n");
cd3b3449 3688 return -ENODEV;
affe360d 3689 }
3690
6e2a14d2
JL		 3691 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3692 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3693 if (r < 0) {
3694 DSSERR("request_irq failed\n");
cd3b3449
TV		 3695 return r;
3696 }
3697
3698 clk = clk_get(&pdev->dev, "fck");
3699 if (IS_ERR(clk)) {
3700 DSSERR("can't get fck\n");
3701 r = PTR_ERR(clk);
3702 return r;
060b6d9c
SG		 3703 }
3704
cd3b3449
TV		 3705 dispc.dss_clk = clk;
3706
4fbafaf3
TV		 3707 pm_runtime_enable(&pdev->dev);
3708
3709 r = dispc_runtime_get();
3710 if (r)
3711 goto err_runtime_get;
060b6d9c
SG		 3712
3713 _omap_dispc_initial_config();
3714
3715 _omap_dispc_initialize_irq();
3716
060b6d9c 3717 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3718 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3719 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3720
4fbafaf3 3721 dispc_runtime_put();
060b6d9c 3722
e40402cf
TV		 3723 dss_debugfs_create_file("dispc", dispc_dump_regs);
3724
3725#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3726 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3727#endif
060b6d9c 3728 return 0;
4fbafaf3
TV		 3729
3730err_runtime_get:
3731 pm_runtime_disable(&pdev->dev);
4fbafaf3 3732 clk_put(dispc.dss_clk);
affe360d 3733 return r;
060b6d9c
SG		 3734}
3735
6e7e8f06 3736static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3737{
4fbafaf3
TV		 3738 pm_runtime_disable(&pdev->dev);
3739
3740 clk_put(dispc.dss_clk);
3741
060b6d9c
SG		 3742 return 0;
3743}
3744
4fbafaf3
TV		 3745static int dispc_runtime_suspend(struct device *dev)
3746{
3747 dispc_save_context();
4fbafaf3
TV		 3748
3749 return 0;
3750}
3751
3752static int dispc_runtime_resume(struct device *dev)
3753{
49ea86f3 3754 dispc_restore_context();
4fbafaf3
TV		 3755
3756 return 0;
3757}
3758
3759static const struct dev_pm_ops dispc_pm_ops = {
3760 .runtime_suspend = dispc_runtime_suspend,
3761 .runtime_resume = dispc_runtime_resume,
3762};
3763
060b6d9c 3764static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3765 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3766 .driver = {
3767 .name = "omapdss_dispc",
3768 .owner = THIS_MODULE,
4fbafaf3 3769 .pm = &dispc_pm_ops,
060b6d9c
SG		 3770 },
3771};
3772
6e7e8f06 3773int __init dispc_init_platform_driver(void)
060b6d9c 3774{
11436e1d 3775 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3776}
3777
6e7e8f06 3778void __exit dispc_uninit_platform_driver(void)
060b6d9c 3779{
04c742c3 3780 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3781}
Linux kernel - Deliverables
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