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OMAP2PLUS: DSS2: Cleanup clock source related code
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
80c39712
TV		 36
37#include <plat/sram.h>
38#include <plat/clock.h>
39
40#include <plat/display.h>
41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
80c39712
TV		 44
45/* DISPC */
8613b000 46#define DISPC_SZ_REGS SZ_4K
80c39712
TV		 47
48struct dispc_reg { u16 idx; };
49
50#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
51
8613b000
SS		 52/*
53 * DISPC common registers and
54 * DISPC channel registers , ch = 0 for LCD, ch = 1 for
55 * DIGIT, and ch = 2 for LCD2
56 */
80c39712
TV		 57#define DISPC_REVISION DISPC_REG(0x0000)
58#define DISPC_SYSCONFIG DISPC_REG(0x0010)
59#define DISPC_SYSSTATUS DISPC_REG(0x0014)
60#define DISPC_IRQSTATUS DISPC_REG(0x0018)
61#define DISPC_IRQENABLE DISPC_REG(0x001C)
62#define DISPC_CONTROL DISPC_REG(0x0040)
8613b000 63#define DISPC_CONTROL2 DISPC_REG(0x0238)
80c39712 64#define DISPC_CONFIG DISPC_REG(0x0044)
8613b000 65#define DISPC_CONFIG2 DISPC_REG(0x0620)
80c39712 66#define DISPC_CAPABLE DISPC_REG(0x0048)
8613b000
SS		 67#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
68 (ch == 1 ? 0x0050 : 0x03AC))
69#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
70 (ch == 1 ? 0x0058 : 0x03B0))
80c39712
TV		 71#define DISPC_LINE_STATUS DISPC_REG(0x005C)
72#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
8613b000
SS		 73#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
74#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
75#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
ce7fa5eb 76#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
80c39712
TV		 77#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
78#define DISPC_SIZE_DIG DISPC_REG(0x0078)
8613b000 79#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
80c39712
TV		 80
81/* DISPC GFX plane */
82#define DISPC_GFX_BA0 DISPC_REG(0x0080)
83#define DISPC_GFX_BA1 DISPC_REG(0x0084)
84#define DISPC_GFX_POSITION DISPC_REG(0x0088)
85#define DISPC_GFX_SIZE DISPC_REG(0x008C)
86#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
87#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
88#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
89#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
90#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
91#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
92#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
93
8613b000
SS		 94#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
95#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
96#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
97#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
98#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
99#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
80c39712
TV		 100
101#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
102
103/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
104#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
105
106#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
107#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
108#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
109#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
110#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
111#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
112#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
113#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
114#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
115#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
116#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
117#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
118#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
119
120/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
121#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
122/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
123#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
124/* coef index i = {0, 1, 2, 3, 4} */
125#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
126/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
127#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
128
129#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
130
ce7fa5eb 131#define DISPC_DIVISOR DISPC_REG(0x0804)
80c39712
TV		 132
133#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
134 DISPC_IRQ_OCP_ERR | \
135 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
136 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
137 DISPC_IRQ_SYNC_LOST | \
138 DISPC_IRQ_SYNC_LOST_DIGIT)
139
140#define DISPC_MAX_NR_ISRS 8
141
142struct omap_dispc_isr_data {
143 omap_dispc_isr_t isr;
144 void *arg;
145 u32 mask;
146};
147
66be8f6c
GI		 148struct dispc_h_coef {
149 s8 hc4;
150 s8 hc3;
151 u8 hc2;
152 s8 hc1;
153 s8 hc0;
154};
155
156struct dispc_v_coef {
157 s8 vc22;
158 s8 vc2;
159 u8 vc1;
160 s8 vc0;
161 s8 vc00;
162};
163
80c39712
TV		 164#define REG_GET(idx, start, end) \
165 FLD_GET(dispc_read_reg(idx), start, end)
166
167#define REG_FLD_MOD(idx, val, start, end) \
168 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
169
170static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
171 DISPC_VID_ATTRIBUTES(0),
172 DISPC_VID_ATTRIBUTES(1) };
173
dfc0fd8d
TV		 174struct dispc_irq_stats {
175 unsigned long last_reset;
176 unsigned irq_count;
177 unsigned irqs[32];
178};
179
80c39712 180static struct {
060b6d9c 181 struct platform_device *pdev;
80c39712 182 void __iomem *base;
affe360d 183 int irq;
80c39712
TV		 184
185 u32 fifo_size[3];
186
187 spinlock_t irq_lock;
188 u32 irq_error_mask;
189 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
190 u32 error_irqs;
191 struct work_struct error_work;
192
193 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 194
195#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
196 spinlock_t irq_stats_lock;
197 struct dispc_irq_stats irq_stats;
198#endif
80c39712
TV		 199} dispc;
200
201static void _omap_dispc_set_irqs(void);
202
203static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
204{
205 __raw_writel(val, dispc.base + idx.idx);
206}
207
208static inline u32 dispc_read_reg(const struct dispc_reg idx)
209{
210 return __raw_readl(dispc.base + idx.idx);
211}
212
213#define SR(reg) \
214 dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
215#define RR(reg) \
216 dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
217
218void dispc_save_context(void)
219{
220 if (cpu_is_omap24xx())
221 return;
222
223 SR(SYSCONFIG);
224 SR(IRQENABLE);
225 SR(CONTROL);
226 SR(CONFIG);
8613b000
SS		 227 SR(DEFAULT_COLOR(0));
228 SR(DEFAULT_COLOR(1));
229 SR(TRANS_COLOR(0));
230 SR(TRANS_COLOR(1));
80c39712 231 SR(LINE_NUMBER);
8613b000
SS		 232 SR(TIMING_H(0));
233 SR(TIMING_V(0));
234 SR(POL_FREQ(0));
ce7fa5eb 235 SR(DIVISORo(0));
80c39712
TV		 236 SR(GLOBAL_ALPHA);
237 SR(SIZE_DIG);
8613b000 238 SR(SIZE_LCD(0));
2a205f34
SS		 239 if (dss_has_feature(FEAT_MGR_LCD2)) {
240 SR(CONTROL2);
241 SR(DEFAULT_COLOR(2));
242 SR(TRANS_COLOR(2));
243 SR(SIZE_LCD(2));
244 SR(TIMING_H(2));
245 SR(TIMING_V(2));
246 SR(POL_FREQ(2));
ce7fa5eb 247 SR(DIVISORo(2));
2a205f34
SS		 248 SR(CONFIG2);
249 }
80c39712
TV		 250
251 SR(GFX_BA0);
252 SR(GFX_BA1);
253 SR(GFX_POSITION);
254 SR(GFX_SIZE);
255 SR(GFX_ATTRIBUTES);
256 SR(GFX_FIFO_THRESHOLD);
257 SR(GFX_ROW_INC);
258 SR(GFX_PIXEL_INC);
259 SR(GFX_WINDOW_SKIP);
260 SR(GFX_TABLE_BA);
261
8613b000
SS		 262 SR(DATA_CYCLE1(0));
263 SR(DATA_CYCLE2(0));
264 SR(DATA_CYCLE3(0));
80c39712 265
8613b000
SS		 266 SR(CPR_COEF_R(0));
267 SR(CPR_COEF_G(0));
268 SR(CPR_COEF_B(0));
2a205f34
SS		 269 if (dss_has_feature(FEAT_MGR_LCD2)) {
270 SR(CPR_COEF_B(2));
271 SR(CPR_COEF_G(2));
272 SR(CPR_COEF_R(2));
273
274 SR(DATA_CYCLE1(2));
275 SR(DATA_CYCLE2(2));
276 SR(DATA_CYCLE3(2));
277 }
80c39712
TV		 278
279 SR(GFX_PRELOAD);
280
281 /* VID1 */
282 SR(VID_BA0(0));
283 SR(VID_BA1(0));
284 SR(VID_POSITION(0));
285 SR(VID_SIZE(0));
286 SR(VID_ATTRIBUTES(0));
287 SR(VID_FIFO_THRESHOLD(0));
288 SR(VID_ROW_INC(0));
289 SR(VID_PIXEL_INC(0));
290 SR(VID_FIR(0));
291 SR(VID_PICTURE_SIZE(0));
292 SR(VID_ACCU0(0));
293 SR(VID_ACCU1(0));
294
295 SR(VID_FIR_COEF_H(0, 0));
296 SR(VID_FIR_COEF_H(0, 1));
297 SR(VID_FIR_COEF_H(0, 2));
298 SR(VID_FIR_COEF_H(0, 3));
299 SR(VID_FIR_COEF_H(0, 4));
300 SR(VID_FIR_COEF_H(0, 5));
301 SR(VID_FIR_COEF_H(0, 6));
302 SR(VID_FIR_COEF_H(0, 7));
303
304 SR(VID_FIR_COEF_HV(0, 0));
305 SR(VID_FIR_COEF_HV(0, 1));
306 SR(VID_FIR_COEF_HV(0, 2));
307 SR(VID_FIR_COEF_HV(0, 3));
308 SR(VID_FIR_COEF_HV(0, 4));
309 SR(VID_FIR_COEF_HV(0, 5));
310 SR(VID_FIR_COEF_HV(0, 6));
311 SR(VID_FIR_COEF_HV(0, 7));
312
313 SR(VID_CONV_COEF(0, 0));
314 SR(VID_CONV_COEF(0, 1));
315 SR(VID_CONV_COEF(0, 2));
316 SR(VID_CONV_COEF(0, 3));
317 SR(VID_CONV_COEF(0, 4));
318
319 SR(VID_FIR_COEF_V(0, 0));
320 SR(VID_FIR_COEF_V(0, 1));
321 SR(VID_FIR_COEF_V(0, 2));
322 SR(VID_FIR_COEF_V(0, 3));
323 SR(VID_FIR_COEF_V(0, 4));
324 SR(VID_FIR_COEF_V(0, 5));
325 SR(VID_FIR_COEF_V(0, 6));
326 SR(VID_FIR_COEF_V(0, 7));
327
328 SR(VID_PRELOAD(0));
329
330 /* VID2 */
331 SR(VID_BA0(1));
332 SR(VID_BA1(1));
333 SR(VID_POSITION(1));
334 SR(VID_SIZE(1));
335 SR(VID_ATTRIBUTES(1));
336 SR(VID_FIFO_THRESHOLD(1));
337 SR(VID_ROW_INC(1));
338 SR(VID_PIXEL_INC(1));
339 SR(VID_FIR(1));
340 SR(VID_PICTURE_SIZE(1));
341 SR(VID_ACCU0(1));
342 SR(VID_ACCU1(1));
343
344 SR(VID_FIR_COEF_H(1, 0));
345 SR(VID_FIR_COEF_H(1, 1));
346 SR(VID_FIR_COEF_H(1, 2));
347 SR(VID_FIR_COEF_H(1, 3));
348 SR(VID_FIR_COEF_H(1, 4));
349 SR(VID_FIR_COEF_H(1, 5));
350 SR(VID_FIR_COEF_H(1, 6));
351 SR(VID_FIR_COEF_H(1, 7));
352
353 SR(VID_FIR_COEF_HV(1, 0));
354 SR(VID_FIR_COEF_HV(1, 1));
355 SR(VID_FIR_COEF_HV(1, 2));
356 SR(VID_FIR_COEF_HV(1, 3));
357 SR(VID_FIR_COEF_HV(1, 4));
358 SR(VID_FIR_COEF_HV(1, 5));
359 SR(VID_FIR_COEF_HV(1, 6));
360 SR(VID_FIR_COEF_HV(1, 7));
361
362 SR(VID_CONV_COEF(1, 0));
363 SR(VID_CONV_COEF(1, 1));
364 SR(VID_CONV_COEF(1, 2));
365 SR(VID_CONV_COEF(1, 3));
366 SR(VID_CONV_COEF(1, 4));
367
368 SR(VID_FIR_COEF_V(1, 0));
369 SR(VID_FIR_COEF_V(1, 1));
370 SR(VID_FIR_COEF_V(1, 2));
371 SR(VID_FIR_COEF_V(1, 3));
372 SR(VID_FIR_COEF_V(1, 4));
373 SR(VID_FIR_COEF_V(1, 5));
374 SR(VID_FIR_COEF_V(1, 6));
375 SR(VID_FIR_COEF_V(1, 7));
376
377 SR(VID_PRELOAD(1));
0cf35df3
MR		 378
379 if (dss_has_feature(FEAT_CORE_CLK_DIV))
380 SR(DIVISOR);
80c39712
TV		 381}
382
383void dispc_restore_context(void)
384{
385 RR(SYSCONFIG);
75c7d59d 386 /*RR(IRQENABLE);*/
80c39712
TV		 387 /*RR(CONTROL);*/
388 RR(CONFIG);
8613b000
SS		 389 RR(DEFAULT_COLOR(0));
390 RR(DEFAULT_COLOR(1));
391 RR(TRANS_COLOR(0));
392 RR(TRANS_COLOR(1));
80c39712 393 RR(LINE_NUMBER);
8613b000
SS		 394 RR(TIMING_H(0));
395 RR(TIMING_V(0));
396 RR(POL_FREQ(0));
ce7fa5eb 397 RR(DIVISORo(0));
80c39712
TV		 398 RR(GLOBAL_ALPHA);
399 RR(SIZE_DIG);
8613b000 400 RR(SIZE_LCD(0));
2a205f34
SS		 401 if (dss_has_feature(FEAT_MGR_LCD2)) {
402 RR(DEFAULT_COLOR(2));
403 RR(TRANS_COLOR(2));
404 RR(SIZE_LCD(2));
405 RR(TIMING_H(2));
406 RR(TIMING_V(2));
407 RR(POL_FREQ(2));
ce7fa5eb 408 RR(DIVISORo(2));
2a205f34
SS		 409 RR(CONFIG2);
410 }
80c39712
TV		 411
412 RR(GFX_BA0);
413 RR(GFX_BA1);
414 RR(GFX_POSITION);
415 RR(GFX_SIZE);
416 RR(GFX_ATTRIBUTES);
417 RR(GFX_FIFO_THRESHOLD);
418 RR(GFX_ROW_INC);
419 RR(GFX_PIXEL_INC);
420 RR(GFX_WINDOW_SKIP);
421 RR(GFX_TABLE_BA);
422
8613b000
SS		 423 RR(DATA_CYCLE1(0));
424 RR(DATA_CYCLE2(0));
425 RR(DATA_CYCLE3(0));
80c39712 426
8613b000
SS		 427 RR(CPR_COEF_R(0));
428 RR(CPR_COEF_G(0));
429 RR(CPR_COEF_B(0));
2a205f34
SS		 430 if (dss_has_feature(FEAT_MGR_LCD2)) {
431 RR(DATA_CYCLE1(2));
432 RR(DATA_CYCLE2(2));
433 RR(DATA_CYCLE3(2));
434
435 RR(CPR_COEF_B(2));
436 RR(CPR_COEF_G(2));
437 RR(CPR_COEF_R(2));
438 }
80c39712
TV		 439
440 RR(GFX_PRELOAD);
441
442 /* VID1 */
443 RR(VID_BA0(0));
444 RR(VID_BA1(0));
445 RR(VID_POSITION(0));
446 RR(VID_SIZE(0));
447 RR(VID_ATTRIBUTES(0));
448 RR(VID_FIFO_THRESHOLD(0));
449 RR(VID_ROW_INC(0));
450 RR(VID_PIXEL_INC(0));
451 RR(VID_FIR(0));
452 RR(VID_PICTURE_SIZE(0));
453 RR(VID_ACCU0(0));
454 RR(VID_ACCU1(0));
455
456 RR(VID_FIR_COEF_H(0, 0));
457 RR(VID_FIR_COEF_H(0, 1));
458 RR(VID_FIR_COEF_H(0, 2));
459 RR(VID_FIR_COEF_H(0, 3));
460 RR(VID_FIR_COEF_H(0, 4));
461 RR(VID_FIR_COEF_H(0, 5));
462 RR(VID_FIR_COEF_H(0, 6));
463 RR(VID_FIR_COEF_H(0, 7));
464
465 RR(VID_FIR_COEF_HV(0, 0));
466 RR(VID_FIR_COEF_HV(0, 1));
467 RR(VID_FIR_COEF_HV(0, 2));
468 RR(VID_FIR_COEF_HV(0, 3));
469 RR(VID_FIR_COEF_HV(0, 4));
470 RR(VID_FIR_COEF_HV(0, 5));
471 RR(VID_FIR_COEF_HV(0, 6));
472 RR(VID_FIR_COEF_HV(0, 7));
473
474 RR(VID_CONV_COEF(0, 0));
475 RR(VID_CONV_COEF(0, 1));
476 RR(VID_CONV_COEF(0, 2));
477 RR(VID_CONV_COEF(0, 3));
478 RR(VID_CONV_COEF(0, 4));
479
480 RR(VID_FIR_COEF_V(0, 0));
481 RR(VID_FIR_COEF_V(0, 1));
482 RR(VID_FIR_COEF_V(0, 2));
483 RR(VID_FIR_COEF_V(0, 3));
484 RR(VID_FIR_COEF_V(0, 4));
485 RR(VID_FIR_COEF_V(0, 5));
486 RR(VID_FIR_COEF_V(0, 6));
487 RR(VID_FIR_COEF_V(0, 7));
488
489 RR(VID_PRELOAD(0));
490
491 /* VID2 */
492 RR(VID_BA0(1));
493 RR(VID_BA1(1));
494 RR(VID_POSITION(1));
495 RR(VID_SIZE(1));
496 RR(VID_ATTRIBUTES(1));
497 RR(VID_FIFO_THRESHOLD(1));
498 RR(VID_ROW_INC(1));
499 RR(VID_PIXEL_INC(1));
500 RR(VID_FIR(1));
501 RR(VID_PICTURE_SIZE(1));
502 RR(VID_ACCU0(1));
503 RR(VID_ACCU1(1));
504
505 RR(VID_FIR_COEF_H(1, 0));
506 RR(VID_FIR_COEF_H(1, 1));
507 RR(VID_FIR_COEF_H(1, 2));
508 RR(VID_FIR_COEF_H(1, 3));
509 RR(VID_FIR_COEF_H(1, 4));
510 RR(VID_FIR_COEF_H(1, 5));
511 RR(VID_FIR_COEF_H(1, 6));
512 RR(VID_FIR_COEF_H(1, 7));
513
514 RR(VID_FIR_COEF_HV(1, 0));
515 RR(VID_FIR_COEF_HV(1, 1));
516 RR(VID_FIR_COEF_HV(1, 2));
517 RR(VID_FIR_COEF_HV(1, 3));
518 RR(VID_FIR_COEF_HV(1, 4));
519 RR(VID_FIR_COEF_HV(1, 5));
520 RR(VID_FIR_COEF_HV(1, 6));
521 RR(VID_FIR_COEF_HV(1, 7));
522
523 RR(VID_CONV_COEF(1, 0));
524 RR(VID_CONV_COEF(1, 1));
525 RR(VID_CONV_COEF(1, 2));
526 RR(VID_CONV_COEF(1, 3));
527 RR(VID_CONV_COEF(1, 4));
528
529 RR(VID_FIR_COEF_V(1, 0));
530 RR(VID_FIR_COEF_V(1, 1));
531 RR(VID_FIR_COEF_V(1, 2));
532 RR(VID_FIR_COEF_V(1, 3));
533 RR(VID_FIR_COEF_V(1, 4));
534 RR(VID_FIR_COEF_V(1, 5));
535 RR(VID_FIR_COEF_V(1, 6));
536 RR(VID_FIR_COEF_V(1, 7));
537
538 RR(VID_PRELOAD(1));
539
0cf35df3
MR		 540 if (dss_has_feature(FEAT_CORE_CLK_DIV))
541 RR(DIVISOR);
542
80c39712
TV		 543 /* enable last, because LCD & DIGIT enable are here */
544 RR(CONTROL);
2a205f34
SS		 545 if (dss_has_feature(FEAT_MGR_LCD2))
546 RR(CONTROL2);
75c7d59d
VS		 547 /* clear spurious SYNC_LOST_DIGIT interrupts */
548 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
549
550 /*
551 * enable last so IRQs won't trigger before
552 * the context is fully restored
553 */
554 RR(IRQENABLE);
80c39712
TV		 555}
556
557#undef SR
558#undef RR
559
560static inline void enable_clocks(bool enable)
561{
562 if (enable)
6af9cd14 563 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712 564 else
6af9cd14 565 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 566}
567
568bool dispc_go_busy(enum omap_channel channel)
569{
570 int bit;
571
2a205f34
SS		 572 if (channel == OMAP_DSS_CHANNEL_LCD ||
573 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 574 bit = 5; /* GOLCD */
575 else
576 bit = 6; /* GODIGIT */
577
2a205f34
SS		 578 if (channel == OMAP_DSS_CHANNEL_LCD2)
579 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
580 else
581 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 582}
583
584void dispc_go(enum omap_channel channel)
585{
586 int bit;
2a205f34 587 bool enable_bit, go_bit;
80c39712
TV		 588
589 enable_clocks(1);
590
2a205f34
SS		 591 if (channel == OMAP_DSS_CHANNEL_LCD ||
592 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 593 bit = 0; /* LCDENABLE */
594 else
595 bit = 1; /* DIGITALENABLE */
596
597 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 598 if (channel == OMAP_DSS_CHANNEL_LCD2)
599 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
600 else
601 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
602
603 if (!enable_bit)
80c39712
TV		 604 goto end;
605
2a205f34
SS		 606 if (channel == OMAP_DSS_CHANNEL_LCD ||
607 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 608 bit = 5; /* GOLCD */
609 else
610 bit = 6; /* GODIGIT */
611
2a205f34
SS		 612 if (channel == OMAP_DSS_CHANNEL_LCD2)
613 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
614 else
615 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
616
617 if (go_bit) {
80c39712
TV		 618 DSSERR("GO bit not down for channel %d\n", channel);
619 goto end;
620 }
621
2a205f34
SS		 622 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
623 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 624
2a205f34
SS		 625 if (channel == OMAP_DSS_CHANNEL_LCD2)
626 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
627 else
628 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 629end:
630 enable_clocks(0);
631}
632
633static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
634{
635 BUG_ON(plane == OMAP_DSS_GFX);
636
637 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
638}
639
640static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
641{
642 BUG_ON(plane == OMAP_DSS_GFX);
643
644 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
645}
646
647static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
648{
649 BUG_ON(plane == OMAP_DSS_GFX);
650
651 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
652}
653
654static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
655 int vscaleup, int five_taps)
656{
657 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 658 static const struct dispc_h_coef coef_hup[8] = {
659 { 0, 0, 128, 0, 0 },
660 { -1, 13, 124, -8, 0 },
661 { -2, 30, 112, -11, -1 },
662 { -5, 51, 95, -11, -2 },
663 { 0, -9, 73, 73, -9 },
664 { -2, -11, 95, 51, -5 },
665 { -1, -11, 112, 30, -2 },
666 { 0, -8, 124, 13, -1 },
80c39712
TV		 667 };
668
66be8f6c
GI		 669 /* Coefficients for vertical up-sampling */
670 static const struct dispc_v_coef coef_vup_3tap[8] = {
671 { 0, 0, 128, 0, 0 },
672 { 0, 3, 123, 2, 0 },
673 { 0, 12, 111, 5, 0 },
674 { 0, 32, 89, 7, 0 },
675 { 0, 0, 64, 64, 0 },
676 { 0, 7, 89, 32, 0 },
677 { 0, 5, 111, 12, 0 },
678 { 0, 2, 123, 3, 0 },
80c39712
TV		 679 };
680
66be8f6c
GI		 681 static const struct dispc_v_coef coef_vup_5tap[8] = {
682 { 0, 0, 128, 0, 0 },
683 { -1, 13, 124, -8, 0 },
684 { -2, 30, 112, -11, -1 },
685 { -5, 51, 95, -11, -2 },
686 { 0, -9, 73, 73, -9 },
687 { -2, -11, 95, 51, -5 },
688 { -1, -11, 112, 30, -2 },
689 { 0, -8, 124, 13, -1 },
80c39712
TV		 690 };
691
66be8f6c
GI		 692 /* Coefficients for horizontal down-sampling */
693 static const struct dispc_h_coef coef_hdown[8] = {
694 { 0, 36, 56, 36, 0 },
695 { 4, 40, 55, 31, -2 },
696 { 8, 44, 54, 27, -5 },
697 { 12, 48, 53, 22, -7 },
698 { -9, 17, 52, 51, 17 },
699 { -7, 22, 53, 48, 12 },
700 { -5, 27, 54, 44, 8 },
701 { -2, 31, 55, 40, 4 },
80c39712
TV		 702 };
703
66be8f6c
GI		 704 /* Coefficients for vertical down-sampling */
705 static const struct dispc_v_coef coef_vdown_3tap[8] = {
706 { 0, 36, 56, 36, 0 },
707 { 0, 40, 57, 31, 0 },
708 { 0, 45, 56, 27, 0 },
709 { 0, 50, 55, 23, 0 },
710 { 0, 18, 55, 55, 0 },
711 { 0, 23, 55, 50, 0 },
712 { 0, 27, 56, 45, 0 },
713 { 0, 31, 57, 40, 0 },
80c39712
TV		 714 };
715
66be8f6c
GI		 716 static const struct dispc_v_coef coef_vdown_5tap[8] = {
717 { 0, 36, 56, 36, 0 },
718 { 4, 40, 55, 31, -2 },
719 { 8, 44, 54, 27, -5 },
720 { 12, 48, 53, 22, -7 },
721 { -9, 17, 52, 51, 17 },
722 { -7, 22, 53, 48, 12 },
723 { -5, 27, 54, 44, 8 },
724 { -2, 31, 55, 40, 4 },
80c39712
TV		 725 };
726
66be8f6c
GI		 727 const struct dispc_h_coef *h_coef;
728 const struct dispc_v_coef *v_coef;
80c39712
TV		 729 int i;
730
731 if (hscaleup)
732 h_coef = coef_hup;
733 else
734 h_coef = coef_hdown;
735
66be8f6c
GI		 736 if (vscaleup)
737 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
738 else
739 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 740
741 for (i = 0; i < 8; i++) {
742 u32 h, hv;
743
66be8f6c
GI		 744 h = FLD_VAL(h_coef[i].hc0, 7, 0)
745 | FLD_VAL(h_coef[i].hc1, 15, 8)
746 | FLD_VAL(h_coef[i].hc2, 23, 16)
747 | FLD_VAL(h_coef[i].hc3, 31, 24);
748 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
749 | FLD_VAL(v_coef[i].vc0, 15, 8)
750 | FLD_VAL(v_coef[i].vc1, 23, 16)
751 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712
TV		 752
753 _dispc_write_firh_reg(plane, i, h);
754 _dispc_write_firhv_reg(plane, i, hv);
755 }
756
66be8f6c
GI		 757 if (five_taps) {
758 for (i = 0; i < 8; i++) {
759 u32 v;
760 v = FLD_VAL(v_coef[i].vc00, 7, 0)
761 | FLD_VAL(v_coef[i].vc22, 15, 8);
762 _dispc_write_firv_reg(plane, i, v);
763 }
80c39712
TV		 764 }
765}
766
767static void _dispc_setup_color_conv_coef(void)
768{
769 const struct color_conv_coef {
770 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
771 int full_range;
772 } ctbl_bt601_5 = {
773 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
774 };
775
776 const struct color_conv_coef *ct;
777
778#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
779
780 ct = &ctbl_bt601_5;
781
782 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
783 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
784 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
785 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
786 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
787
788 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
789 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
790 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
791 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
792 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
793
794#undef CVAL
795
796 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
797 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
798}
799
800
801static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
802{
803 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
804 DISPC_VID_BA0(0),
805 DISPC_VID_BA0(1) };
806
807 dispc_write_reg(ba0_reg[plane], paddr);
808}
809
810static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
811{
812 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
813 DISPC_VID_BA1(0),
814 DISPC_VID_BA1(1) };
815
816 dispc_write_reg(ba1_reg[plane], paddr);
817}
818
819static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
820{
821 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
822 DISPC_VID_POSITION(0),
823 DISPC_VID_POSITION(1) };
824
825 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
826 dispc_write_reg(pos_reg[plane], val);
827}
828
829static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
830{
831 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
832 DISPC_VID_PICTURE_SIZE(0),
833 DISPC_VID_PICTURE_SIZE(1) };
834 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
835 dispc_write_reg(siz_reg[plane], val);
836}
837
838static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
839{
840 u32 val;
841 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
842 DISPC_VID_SIZE(1) };
843
844 BUG_ON(plane == OMAP_DSS_GFX);
845
846 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
847 dispc_write_reg(vsi_reg[plane-1], val);
848}
849
fd28a390
R		 850static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
851{
852 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
853 return;
854
855 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
856 plane == OMAP_DSS_VIDEO1)
857 return;
858
859 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
860}
861
80c39712
TV		 862static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
863{
a0acb557 864 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 865 return;
866
fd28a390
R		 867 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
868 plane == OMAP_DSS_VIDEO1)
869 return;
a0acb557 870
80c39712
TV		 871 if (plane == OMAP_DSS_GFX)
872 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
873 else if (plane == OMAP_DSS_VIDEO2)
874 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
875}
876
877static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
878{
879 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
880 DISPC_VID_PIXEL_INC(0),
881 DISPC_VID_PIXEL_INC(1) };
882
883 dispc_write_reg(ri_reg[plane], inc);
884}
885
886static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
887{
888 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
889 DISPC_VID_ROW_INC(0),
890 DISPC_VID_ROW_INC(1) };
891
892 dispc_write_reg(ri_reg[plane], inc);
893}
894
895static void _dispc_set_color_mode(enum omap_plane plane,
896 enum omap_color_mode color_mode)
897{
898 u32 m = 0;
899
900 switch (color_mode) {
901 case OMAP_DSS_COLOR_CLUT1:
902 m = 0x0; break;
903 case OMAP_DSS_COLOR_CLUT2:
904 m = 0x1; break;
905 case OMAP_DSS_COLOR_CLUT4:
906 m = 0x2; break;
907 case OMAP_DSS_COLOR_CLUT8:
908 m = 0x3; break;
909 case OMAP_DSS_COLOR_RGB12U:
910 m = 0x4; break;
911 case OMAP_DSS_COLOR_ARGB16:
912 m = 0x5; break;
913 case OMAP_DSS_COLOR_RGB16:
914 m = 0x6; break;
915 case OMAP_DSS_COLOR_RGB24U:
916 m = 0x8; break;
917 case OMAP_DSS_COLOR_RGB24P:
918 m = 0x9; break;
919 case OMAP_DSS_COLOR_YUV2:
920 m = 0xa; break;
921 case OMAP_DSS_COLOR_UYVY:
922 m = 0xb; break;
923 case OMAP_DSS_COLOR_ARGB32:
924 m = 0xc; break;
925 case OMAP_DSS_COLOR_RGBA32:
926 m = 0xd; break;
927 case OMAP_DSS_COLOR_RGBX32:
928 m = 0xe; break;
929 default:
930 BUG(); break;
931 }
932
933 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
934}
935
936static void _dispc_set_channel_out(enum omap_plane plane,
937 enum omap_channel channel)
938{
939 int shift;
940 u32 val;
2a205f34 941 int chan = 0, chan2 = 0;
80c39712
TV		 942
943 switch (plane) {
944 case OMAP_DSS_GFX:
945 shift = 8;
946 break;
947 case OMAP_DSS_VIDEO1:
948 case OMAP_DSS_VIDEO2:
949 shift = 16;
950 break;
951 default:
952 BUG();
953 return;
954 }
955
956 val = dispc_read_reg(dispc_reg_att[plane]);
2a205f34
SS		 957 if (dss_has_feature(FEAT_MGR_LCD2)) {
958 switch (channel) {
959 case OMAP_DSS_CHANNEL_LCD:
960 chan = 0;
961 chan2 = 0;
962 break;
963 case OMAP_DSS_CHANNEL_DIGIT:
964 chan = 1;
965 chan2 = 0;
966 break;
967 case OMAP_DSS_CHANNEL_LCD2:
968 chan = 0;
969 chan2 = 1;
970 break;
971 default:
972 BUG();
973 }
974
975 val = FLD_MOD(val, chan, shift, shift);
976 val = FLD_MOD(val, chan2, 31, 30);
977 } else {
978 val = FLD_MOD(val, channel, shift, shift);
979 }
80c39712
TV		 980 dispc_write_reg(dispc_reg_att[plane], val);
981}
982
983void dispc_set_burst_size(enum omap_plane plane,
984 enum omap_burst_size burst_size)
985{
986 int shift;
987 u32 val;
988
989 enable_clocks(1);
990
991 switch (plane) {
992 case OMAP_DSS_GFX:
993 shift = 6;
994 break;
995 case OMAP_DSS_VIDEO1:
996 case OMAP_DSS_VIDEO2:
997 shift = 14;
998 break;
999 default:
1000 BUG();
1001 return;
1002 }
1003
1004 val = dispc_read_reg(dispc_reg_att[plane]);
1005 val = FLD_MOD(val, burst_size, shift+1, shift);
1006 dispc_write_reg(dispc_reg_att[plane], val);
1007
1008 enable_clocks(0);
1009}
1010
1011static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1012{
1013 u32 val;
1014
1015 BUG_ON(plane == OMAP_DSS_GFX);
1016
1017 val = dispc_read_reg(dispc_reg_att[plane]);
1018 val = FLD_MOD(val, enable, 9, 9);
1019 dispc_write_reg(dispc_reg_att[plane], val);
1020}
1021
1022void dispc_enable_replication(enum omap_plane plane, bool enable)
1023{
1024 int bit;
1025
1026 if (plane == OMAP_DSS_GFX)
1027 bit = 5;
1028 else
1029 bit = 10;
1030
1031 enable_clocks(1);
1032 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1033 enable_clocks(0);
1034}
1035
64ba4f74 1036void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1037{
1038 u32 val;
1039 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1040 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1041 enable_clocks(1);
64ba4f74 1042 dispc_write_reg(DISPC_SIZE_LCD(channel), val);
80c39712
TV		 1043 enable_clocks(0);
1044}
1045
1046void dispc_set_digit_size(u16 width, u16 height)
1047{
1048 u32 val;
1049 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1050 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1051 enable_clocks(1);
1052 dispc_write_reg(DISPC_SIZE_DIG, val);
1053 enable_clocks(0);
1054}
1055
1056static void dispc_read_plane_fifo_sizes(void)
1057{
1058 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1059 DISPC_VID_FIFO_SIZE_STATUS(0),
1060 DISPC_VID_FIFO_SIZE_STATUS(1) };
1061 u32 size;
1062 int plane;
a0acb557 1063 u8 start, end;
80c39712
TV		 1064
1065 enable_clocks(1);
1066
a0acb557 1067 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1068
a0acb557
AT		 1069 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1070 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
80c39712
TV		 1071 dispc.fifo_size[plane] = size;
1072 }
1073
1074 enable_clocks(0);
1075}
1076
1077u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1078{
1079 return dispc.fifo_size[plane];
1080}
1081
1082void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1083{
1084 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1085 DISPC_VID_FIFO_THRESHOLD(0),
1086 DISPC_VID_FIFO_THRESHOLD(1) };
a0acb557
AT		 1087 u8 hi_start, hi_end, lo_start, lo_end;
1088
80c39712
TV		 1089 enable_clocks(1);
1090
1091 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1092 plane,
1093 REG_GET(ftrs_reg[plane], 11, 0),
1094 REG_GET(ftrs_reg[plane], 27, 16),
1095 low, high);
1096
a0acb557
AT		 1097 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1098 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1099
1100 dispc_write_reg(ftrs_reg[plane],
1101 FLD_VAL(high, hi_start, hi_end) |
1102 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1103
1104 enable_clocks(0);
1105}
1106
1107void dispc_enable_fifomerge(bool enable)
1108{
1109 enable_clocks(1);
1110
1111 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1112 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1113
1114 enable_clocks(0);
1115}
1116
1117static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1118{
1119 u32 val;
1120 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1121 DISPC_VID_FIR(1) };
a0acb557 1122 u8 hinc_start, hinc_end, vinc_start, vinc_end;
80c39712
TV		 1123
1124 BUG_ON(plane == OMAP_DSS_GFX);
1125
a0acb557
AT		 1126 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1127 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1128
1129 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1130 FLD_VAL(hinc, hinc_start, hinc_end);
1131
80c39712
TV		 1132 dispc_write_reg(fir_reg[plane-1], val);
1133}
1134
1135static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1136{
1137 u32 val;
1138 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1139 DISPC_VID_ACCU0(1) };
87a7484b 1140 u8 hor_start, hor_end, vert_start, vert_end;
80c39712
TV		 1141
1142 BUG_ON(plane == OMAP_DSS_GFX);
1143
87a7484b
AT		 1144 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1145 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1146
1147 val = FLD_VAL(vaccu, vert_start, vert_end) |
1148 FLD_VAL(haccu, hor_start, hor_end);
1149
80c39712
TV		 1150 dispc_write_reg(ac0_reg[plane-1], val);
1151}
1152
1153static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1154{
1155 u32 val;
1156 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1157 DISPC_VID_ACCU1(1) };
87a7484b 1158 u8 hor_start, hor_end, vert_start, vert_end;
80c39712
TV		 1159
1160 BUG_ON(plane == OMAP_DSS_GFX);
1161
87a7484b
AT		 1162 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1163 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1164
1165 val = FLD_VAL(vaccu, vert_start, vert_end) |
1166 FLD_VAL(haccu, hor_start, hor_end);
1167
80c39712
TV		 1168 dispc_write_reg(ac1_reg[plane-1], val);
1169}
1170
1171
1172static void _dispc_set_scaling(enum omap_plane plane,
1173 u16 orig_width, u16 orig_height,
1174 u16 out_width, u16 out_height,
1175 bool ilace, bool five_taps,
1176 bool fieldmode)
1177{
1178 int fir_hinc;
1179 int fir_vinc;
1180 int hscaleup, vscaleup;
1181 int accu0 = 0;
1182 int accu1 = 0;
1183 u32 l;
1184
1185 BUG_ON(plane == OMAP_DSS_GFX);
1186
1187 hscaleup = orig_width <= out_width;
1188 vscaleup = orig_height <= out_height;
1189
1190 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1191
1192 if (!orig_width || orig_width == out_width)
1193 fir_hinc = 0;
1194 else
1195 fir_hinc = 1024 * orig_width / out_width;
1196
1197 if (!orig_height || orig_height == out_height)
1198 fir_vinc = 0;
1199 else
1200 fir_vinc = 1024 * orig_height / out_height;
1201
1202 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1203
1204 l = dispc_read_reg(dispc_reg_att[plane]);
80c39712 1205
87a7484b
AT		 1206 /* RESIZEENABLE and VERTICALTAPS */
1207 l &= ~((0x3 << 5) | (0x1 << 21));
80c39712
TV		 1208 l |= fir_hinc ? (1 << 5) : 0;
1209 l |= fir_vinc ? (1 << 6) : 0;
87a7484b 1210 l |= five_taps ? (1 << 21) : 0;
80c39712 1211
87a7484b
AT		 1212 /* VRESIZECONF and HRESIZECONF */
1213 if (dss_has_feature(FEAT_RESIZECONF)) {
1214 l &= ~(0x3 << 7);
1215 l |= hscaleup ? 0 : (1 << 7);
1216 l |= vscaleup ? 0 : (1 << 8);
1217 }
80c39712 1218
87a7484b
AT		 1219 /* LINEBUFFERSPLIT */
1220 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1221 l &= ~(0x1 << 22);
1222 l |= five_taps ? (1 << 22) : 0;
1223 }
80c39712
TV		 1224
1225 dispc_write_reg(dispc_reg_att[plane], l);
1226
1227 /*
1228 * field 0 = even field = bottom field
1229 * field 1 = odd field = top field
1230 */
1231 if (ilace && !fieldmode) {
1232 accu1 = 0;
1233 accu0 = (fir_vinc / 2) & 0x3ff;
1234 if (accu0 >= 1024/2) {
1235 accu1 = 1024/2;
1236 accu0 -= accu1;
1237 }
1238 }
1239
1240 _dispc_set_vid_accu0(plane, 0, accu0);
1241 _dispc_set_vid_accu1(plane, 0, accu1);
1242}
1243
1244static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1245 bool mirroring, enum omap_color_mode color_mode)
1246{
87a7484b
AT		 1247 bool row_repeat = false;
1248 int vidrot = 0;
1249
80c39712
TV		 1250 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1251 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1252
1253 if (mirroring) {
1254 switch (rotation) {
1255 case OMAP_DSS_ROT_0:
1256 vidrot = 2;
1257 break;
1258 case OMAP_DSS_ROT_90:
1259 vidrot = 1;
1260 break;
1261 case OMAP_DSS_ROT_180:
1262 vidrot = 0;
1263 break;
1264 case OMAP_DSS_ROT_270:
1265 vidrot = 3;
1266 break;
1267 }
1268 } else {
1269 switch (rotation) {
1270 case OMAP_DSS_ROT_0:
1271 vidrot = 0;
1272 break;
1273 case OMAP_DSS_ROT_90:
1274 vidrot = 1;
1275 break;
1276 case OMAP_DSS_ROT_180:
1277 vidrot = 2;
1278 break;
1279 case OMAP_DSS_ROT_270:
1280 vidrot = 3;
1281 break;
1282 }
1283 }
1284
80c39712 1285 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1286 row_repeat = true;
80c39712 1287 else
87a7484b 1288 row_repeat = false;
80c39712 1289 }
87a7484b
AT		 1290
1291 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1292 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1293 REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1294}
1295
1296static int color_mode_to_bpp(enum omap_color_mode color_mode)
1297{
1298 switch (color_mode) {
1299 case OMAP_DSS_COLOR_CLUT1:
1300 return 1;
1301 case OMAP_DSS_COLOR_CLUT2:
1302 return 2;
1303 case OMAP_DSS_COLOR_CLUT4:
1304 return 4;
1305 case OMAP_DSS_COLOR_CLUT8:
1306 return 8;
1307 case OMAP_DSS_COLOR_RGB12U:
1308 case OMAP_DSS_COLOR_RGB16:
1309 case OMAP_DSS_COLOR_ARGB16:
1310 case OMAP_DSS_COLOR_YUV2:
1311 case OMAP_DSS_COLOR_UYVY:
1312 return 16;
1313 case OMAP_DSS_COLOR_RGB24P:
1314 return 24;
1315 case OMAP_DSS_COLOR_RGB24U:
1316 case OMAP_DSS_COLOR_ARGB32:
1317 case OMAP_DSS_COLOR_RGBA32:
1318 case OMAP_DSS_COLOR_RGBX32:
1319 return 32;
1320 default:
1321 BUG();
1322 }
1323}
1324
1325static s32 pixinc(int pixels, u8 ps)
1326{
1327 if (pixels == 1)
1328 return 1;
1329 else if (pixels > 1)
1330 return 1 + (pixels - 1) * ps;
1331 else if (pixels < 0)
1332 return 1 - (-pixels + 1) * ps;
1333 else
1334 BUG();
1335}
1336
1337static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1338 u16 screen_width,
1339 u16 width, u16 height,
1340 enum omap_color_mode color_mode, bool fieldmode,
1341 unsigned int field_offset,
1342 unsigned *offset0, unsigned *offset1,
1343 s32 *row_inc, s32 *pix_inc)
1344{
1345 u8 ps;
1346
1347 /* FIXME CLUT formats */
1348 switch (color_mode) {
1349 case OMAP_DSS_COLOR_CLUT1:
1350 case OMAP_DSS_COLOR_CLUT2:
1351 case OMAP_DSS_COLOR_CLUT4:
1352 case OMAP_DSS_COLOR_CLUT8:
1353 BUG();
1354 return;
1355 case OMAP_DSS_COLOR_YUV2:
1356 case OMAP_DSS_COLOR_UYVY:
1357 ps = 4;
1358 break;
1359 default:
1360 ps = color_mode_to_bpp(color_mode) / 8;
1361 break;
1362 }
1363
1364 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1365 width, height);
1366
1367 /*
1368 * field 0 = even field = bottom field
1369 * field 1 = odd field = top field
1370 */
1371 switch (rotation + mirror * 4) {
1372 case OMAP_DSS_ROT_0:
1373 case OMAP_DSS_ROT_180:
1374 /*
1375 * If the pixel format is YUV or UYVY divide the width
1376 * of the image by 2 for 0 and 180 degree rotation.
1377 */
1378 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1379 color_mode == OMAP_DSS_COLOR_UYVY)
1380 width = width >> 1;
1381 case OMAP_DSS_ROT_90:
1382 case OMAP_DSS_ROT_270:
1383 *offset1 = 0;
1384 if (field_offset)
1385 *offset0 = field_offset * screen_width * ps;
1386 else
1387 *offset0 = 0;
1388
1389 *row_inc = pixinc(1 + (screen_width - width) +
1390 (fieldmode ? screen_width : 0),
1391 ps);
1392 *pix_inc = pixinc(1, ps);
1393 break;
1394
1395 case OMAP_DSS_ROT_0 + 4:
1396 case OMAP_DSS_ROT_180 + 4:
1397 /* If the pixel format is YUV or UYVY divide the width
1398 * of the image by 2 for 0 degree and 180 degree
1399 */
1400 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1401 color_mode == OMAP_DSS_COLOR_UYVY)
1402 width = width >> 1;
1403 case OMAP_DSS_ROT_90 + 4:
1404 case OMAP_DSS_ROT_270 + 4:
1405 *offset1 = 0;
1406 if (field_offset)
1407 *offset0 = field_offset * screen_width * ps;
1408 else
1409 *offset0 = 0;
1410 *row_inc = pixinc(1 - (screen_width + width) -
1411 (fieldmode ? screen_width : 0),
1412 ps);
1413 *pix_inc = pixinc(1, ps);
1414 break;
1415
1416 default:
1417 BUG();
1418 }
1419}
1420
1421static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1422 u16 screen_width,
1423 u16 width, u16 height,
1424 enum omap_color_mode color_mode, bool fieldmode,
1425 unsigned int field_offset,
1426 unsigned *offset0, unsigned *offset1,
1427 s32 *row_inc, s32 *pix_inc)
1428{
1429 u8 ps;
1430 u16 fbw, fbh;
1431
1432 /* FIXME CLUT formats */
1433 switch (color_mode) {
1434 case OMAP_DSS_COLOR_CLUT1:
1435 case OMAP_DSS_COLOR_CLUT2:
1436 case OMAP_DSS_COLOR_CLUT4:
1437 case OMAP_DSS_COLOR_CLUT8:
1438 BUG();
1439 return;
1440 default:
1441 ps = color_mode_to_bpp(color_mode) / 8;
1442 break;
1443 }
1444
1445 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1446 width, height);
1447
1448 /* width & height are overlay sizes, convert to fb sizes */
1449
1450 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1451 fbw = width;
1452 fbh = height;
1453 } else {
1454 fbw = height;
1455 fbh = width;
1456 }
1457
1458 /*
1459 * field 0 = even field = bottom field
1460 * field 1 = odd field = top field
1461 */
1462 switch (rotation + mirror * 4) {
1463 case OMAP_DSS_ROT_0:
1464 *offset1 = 0;
1465 if (field_offset)
1466 *offset0 = *offset1 + field_offset * screen_width * ps;
1467 else
1468 *offset0 = *offset1;
1469 *row_inc = pixinc(1 + (screen_width - fbw) +
1470 (fieldmode ? screen_width : 0),
1471 ps);
1472 *pix_inc = pixinc(1, ps);
1473 break;
1474 case OMAP_DSS_ROT_90:
1475 *offset1 = screen_width * (fbh - 1) * ps;
1476 if (field_offset)
1477 *offset0 = *offset1 + field_offset * ps;
1478 else
1479 *offset0 = *offset1;
1480 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1481 (fieldmode ? 1 : 0), ps);
1482 *pix_inc = pixinc(-screen_width, ps);
1483 break;
1484 case OMAP_DSS_ROT_180:
1485 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1486 if (field_offset)
1487 *offset0 = *offset1 - field_offset * screen_width * ps;
1488 else
1489 *offset0 = *offset1;
1490 *row_inc = pixinc(-1 -
1491 (screen_width - fbw) -
1492 (fieldmode ? screen_width : 0),
1493 ps);
1494 *pix_inc = pixinc(-1, ps);
1495 break;
1496 case OMAP_DSS_ROT_270:
1497 *offset1 = (fbw - 1) * ps;
1498 if (field_offset)
1499 *offset0 = *offset1 - field_offset * ps;
1500 else
1501 *offset0 = *offset1;
1502 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1503 (fieldmode ? 1 : 0), ps);
1504 *pix_inc = pixinc(screen_width, ps);
1505 break;
1506
1507 /* mirroring */
1508 case OMAP_DSS_ROT_0 + 4:
1509 *offset1 = (fbw - 1) * ps;
1510 if (field_offset)
1511 *offset0 = *offset1 + field_offset * screen_width * ps;
1512 else
1513 *offset0 = *offset1;
1514 *row_inc = pixinc(screen_width * 2 - 1 +
1515 (fieldmode ? screen_width : 0),
1516 ps);
1517 *pix_inc = pixinc(-1, ps);
1518 break;
1519
1520 case OMAP_DSS_ROT_90 + 4:
1521 *offset1 = 0;
1522 if (field_offset)
1523 *offset0 = *offset1 + field_offset * ps;
1524 else
1525 *offset0 = *offset1;
1526 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1527 (fieldmode ? 1 : 0),
1528 ps);
1529 *pix_inc = pixinc(screen_width, ps);
1530 break;
1531
1532 case OMAP_DSS_ROT_180 + 4:
1533 *offset1 = screen_width * (fbh - 1) * ps;
1534 if (field_offset)
1535 *offset0 = *offset1 - field_offset * screen_width * ps;
1536 else
1537 *offset0 = *offset1;
1538 *row_inc = pixinc(1 - screen_width * 2 -
1539 (fieldmode ? screen_width : 0),
1540 ps);
1541 *pix_inc = pixinc(1, ps);
1542 break;
1543
1544 case OMAP_DSS_ROT_270 + 4:
1545 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1546 if (field_offset)
1547 *offset0 = *offset1 - field_offset * ps;
1548 else
1549 *offset0 = *offset1;
1550 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1551 (fieldmode ? 1 : 0),
1552 ps);
1553 *pix_inc = pixinc(-screen_width, ps);
1554 break;
1555
1556 default:
1557 BUG();
1558 }
1559}
1560
ff1b2cde
SS		 1561static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1562 u16 height, u16 out_width, u16 out_height,
1563 enum omap_color_mode color_mode)
80c39712
TV		 1564{
1565 u32 fclk = 0;
1566 /* FIXME venc pclk? */
ff1b2cde 1567 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1568
1569 if (height > out_height) {
1570 /* FIXME get real display PPL */
1571 unsigned int ppl = 800;
1572
1573 tmp = pclk * height * out_width;
1574 do_div(tmp, 2 * out_height * ppl);
1575 fclk = tmp;
1576
2d9c5597
VS		 1577 if (height > 2 * out_height) {
1578 if (ppl == out_width)
1579 return 0;
1580
80c39712
TV		 1581 tmp = pclk * (height - 2 * out_height) * out_width;
1582 do_div(tmp, 2 * out_height * (ppl - out_width));
1583 fclk = max(fclk, (u32) tmp);
1584 }
1585 }
1586
1587 if (width > out_width) {
1588 tmp = pclk * width;
1589 do_div(tmp, out_width);
1590 fclk = max(fclk, (u32) tmp);
1591
1592 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1593 fclk <<= 1;
1594 }
1595
1596 return fclk;
1597}
1598
ff1b2cde
SS		 1599static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1600 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1601{
1602 unsigned int hf, vf;
1603
1604 /*
1605 * FIXME how to determine the 'A' factor
1606 * for the no downscaling case ?
1607 */
1608
1609 if (width > 3 * out_width)
1610 hf = 4;
1611 else if (width > 2 * out_width)
1612 hf = 3;
1613 else if (width > out_width)
1614 hf = 2;
1615 else
1616 hf = 1;
1617
1618 if (height > out_height)
1619 vf = 2;
1620 else
1621 vf = 1;
1622
1623 /* FIXME venc pclk? */
ff1b2cde 1624 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1625}
1626
1627void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1628{
1629 enable_clocks(1);
1630 _dispc_set_channel_out(plane, channel_out);
1631 enable_clocks(0);
1632}
1633
1634static int _dispc_setup_plane(enum omap_plane plane,
1635 u32 paddr, u16 screen_width,
1636 u16 pos_x, u16 pos_y,
1637 u16 width, u16 height,
1638 u16 out_width, u16 out_height,
1639 enum omap_color_mode color_mode,
1640 bool ilace,
1641 enum omap_dss_rotation_type rotation_type,
1642 u8 rotation, int mirror,
18faa1b6
SS		 1643 u8 global_alpha, u8 pre_mult_alpha,
1644 enum omap_channel channel)
80c39712
TV		 1645{
1646 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1647 bool five_taps = 0;
1648 bool fieldmode = 0;
1649 int cconv = 0;
1650 unsigned offset0, offset1;
1651 s32 row_inc;
1652 s32 pix_inc;
1653 u16 frame_height = height;
1654 unsigned int field_offset = 0;
1655
1656 if (paddr == 0)
1657 return -EINVAL;
1658
1659 if (ilace && height == out_height)
1660 fieldmode = 1;
1661
1662 if (ilace) {
1663 if (fieldmode)
1664 height /= 2;
1665 pos_y /= 2;
1666 out_height /= 2;
1667
1668 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1669 "out_height %d\n",
1670 height, pos_y, out_height);
1671 }
1672
8dad2ab6
AT		 1673 if (!dss_feat_color_mode_supported(plane, color_mode))
1674 return -EINVAL;
1675
80c39712
TV		 1676 if (plane == OMAP_DSS_GFX) {
1677 if (width != out_width || height != out_height)
1678 return -EINVAL;
80c39712
TV		 1679 } else {
1680 /* video plane */
1681
1682 unsigned long fclk = 0;
1683
1684 if (out_width < width / maxdownscale ||
1685 out_width > width * 8)
1686 return -EINVAL;
1687
1688 if (out_height < height / maxdownscale ||
1689 out_height > height * 8)
1690 return -EINVAL;
1691
8dad2ab6
AT		 1692 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1693 color_mode == OMAP_DSS_COLOR_UYVY)
80c39712 1694 cconv = 1;
80c39712
TV		 1695
1696 /* Must use 5-tap filter? */
1697 five_taps = height > out_height * 2;
1698
1699 if (!five_taps) {
18faa1b6
SS		 1700 fclk = calc_fclk(channel, width, height, out_width,
1701 out_height);
80c39712
TV		 1702
1703 /* Try 5-tap filter if 3-tap fclk is too high */
1704 if (cpu_is_omap34xx() && height > out_height &&
1705 fclk > dispc_fclk_rate())
1706 five_taps = true;
1707 }
1708
1709 if (width > (2048 >> five_taps)) {
1710 DSSERR("failed to set up scaling, fclk too low\n");
1711 return -EINVAL;
1712 }
1713
1714 if (five_taps)
18faa1b6
SS		 1715 fclk = calc_fclk_five_taps(channel, width, height,
1716 out_width, out_height, color_mode);
80c39712
TV		 1717
1718 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1719 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1720
2d9c5597 1721 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1722 DSSERR("failed to set up scaling, "
1723 "required fclk rate = %lu Hz, "
1724 "current fclk rate = %lu Hz\n",
1725 fclk, dispc_fclk_rate());
1726 return -EINVAL;
1727 }
1728 }
1729
1730 if (ilace && !fieldmode) {
1731 /*
1732 * when downscaling the bottom field may have to start several
1733 * source lines below the top field. Unfortunately ACCUI
1734 * registers will only hold the fractional part of the offset
1735 * so the integer part must be added to the base address of the
1736 * bottom field.
1737 */
1738 if (!height || height == out_height)
1739 field_offset = 0;
1740 else
1741 field_offset = height / out_height / 2;
1742 }
1743
1744 /* Fields are independent but interleaved in memory. */
1745 if (fieldmode)
1746 field_offset = 1;
1747
1748 if (rotation_type == OMAP_DSS_ROT_DMA)
1749 calc_dma_rotation_offset(rotation, mirror,
1750 screen_width, width, frame_height, color_mode,
1751 fieldmode, field_offset,
1752 &offset0, &offset1, &row_inc, &pix_inc);
1753 else
1754 calc_vrfb_rotation_offset(rotation, mirror,
1755 screen_width, width, frame_height, color_mode,
1756 fieldmode, field_offset,
1757 &offset0, &offset1, &row_inc, &pix_inc);
1758
1759 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1760 offset0, offset1, row_inc, pix_inc);
1761
1762 _dispc_set_color_mode(plane, color_mode);
1763
1764 _dispc_set_plane_ba0(plane, paddr + offset0);
1765 _dispc_set_plane_ba1(plane, paddr + offset1);
1766
1767 _dispc_set_row_inc(plane, row_inc);
1768 _dispc_set_pix_inc(plane, pix_inc);
1769
1770 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1771 out_width, out_height);
1772
1773 _dispc_set_plane_pos(plane, pos_x, pos_y);
1774
1775 _dispc_set_pic_size(plane, width, height);
1776
1777 if (plane != OMAP_DSS_GFX) {
1778 _dispc_set_scaling(plane, width, height,
1779 out_width, out_height,
1780 ilace, five_taps, fieldmode);
1781 _dispc_set_vid_size(plane, out_width, out_height);
1782 _dispc_set_vid_color_conv(plane, cconv);
1783 }
1784
1785 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1786
fd28a390
R		 1787 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1788 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 1789
1790 return 0;
1791}
1792
1793static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1794{
1795 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1796}
1797
1798static void dispc_disable_isr(void *data, u32 mask)
1799{
1800 struct completion *compl = data;
1801 complete(compl);
1802}
1803
2a205f34 1804static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1805{
2a205f34
SS		 1806 if (channel == OMAP_DSS_CHANNEL_LCD2)
1807 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1808 else
1809 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1810}
1811
2a205f34 1812static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1813{
1814 struct completion frame_done_completion;
1815 bool is_on;
1816 int r;
2a205f34 1817 u32 irq;
80c39712
TV		 1818
1819 enable_clocks(1);
1820
1821 /* When we disable LCD output, we need to wait until frame is done.
1822 * Otherwise the DSS is still working, and turning off the clocks
1823 * prevents DSS from going to OFF mode */
2a205f34
SS		 1824 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1825 REG_GET(DISPC_CONTROL2, 0, 0) :
1826 REG_GET(DISPC_CONTROL, 0, 0);
1827
1828 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1829 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1830
1831 if (!enable && is_on) {
1832 init_completion(&frame_done_completion);
1833
1834 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1835 &frame_done_completion, irq);
80c39712
TV		 1836
1837 if (r)
1838 DSSERR("failed to register FRAMEDONE isr\n");
1839 }
1840
2a205f34 1841 _enable_lcd_out(channel, enable);
80c39712
TV		 1842
1843 if (!enable && is_on) {
1844 if (!wait_for_completion_timeout(&frame_done_completion,
1845 msecs_to_jiffies(100)))
1846 DSSERR("timeout waiting for FRAME DONE\n");
1847
1848 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1849 &frame_done_completion, irq);
80c39712
TV		 1850
1851 if (r)
1852 DSSERR("failed to unregister FRAMEDONE isr\n");
1853 }
1854
1855 enable_clocks(0);
1856}
1857
1858static void _enable_digit_out(bool enable)
1859{
1860 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1861}
1862
a2faee84 1863static void dispc_enable_digit_out(bool enable)
80c39712
TV		 1864{
1865 struct completion frame_done_completion;
1866 int r;
1867
1868 enable_clocks(1);
1869
1870 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1871 enable_clocks(0);
1872 return;
1873 }
1874
1875 if (enable) {
1876 unsigned long flags;
1877 /* When we enable digit output, we'll get an extra digit
1878 * sync lost interrupt, that we need to ignore */
1879 spin_lock_irqsave(&dispc.irq_lock, flags);
1880 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1881 _omap_dispc_set_irqs();
1882 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1883 }
1884
1885 /* When we disable digit output, we need to wait until fields are done.
1886 * Otherwise the DSS is still working, and turning off the clocks
1887 * prevents DSS from going to OFF mode. And when enabling, we need to
1888 * wait for the extra sync losts */
1889 init_completion(&frame_done_completion);
1890
1891 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1892 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1893 if (r)
1894 DSSERR("failed to register EVSYNC isr\n");
1895
1896 _enable_digit_out(enable);
1897
1898 /* XXX I understand from TRM that we should only wait for the
1899 * current field to complete. But it seems we have to wait
1900 * for both fields */
1901 if (!wait_for_completion_timeout(&frame_done_completion,
1902 msecs_to_jiffies(100)))
1903 DSSERR("timeout waiting for EVSYNC\n");
1904
1905 if (!wait_for_completion_timeout(&frame_done_completion,
1906 msecs_to_jiffies(100)))
1907 DSSERR("timeout waiting for EVSYNC\n");
1908
1909 r = omap_dispc_unregister_isr(dispc_disable_isr,
1910 &frame_done_completion,
1911 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1912 if (r)
1913 DSSERR("failed to unregister EVSYNC isr\n");
1914
1915 if (enable) {
1916 unsigned long flags;
1917 spin_lock_irqsave(&dispc.irq_lock, flags);
1918 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 1919 if (dss_has_feature(FEAT_MGR_LCD2))
1920 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 1921 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1922 _omap_dispc_set_irqs();
1923 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1924 }
1925
1926 enable_clocks(0);
1927}
1928
a2faee84
TV		 1929bool dispc_is_channel_enabled(enum omap_channel channel)
1930{
1931 if (channel == OMAP_DSS_CHANNEL_LCD)
1932 return !!REG_GET(DISPC_CONTROL, 0, 0);
1933 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1934 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 1935 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1936 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 1937 else
1938 BUG();
1939}
1940
1941void dispc_enable_channel(enum omap_channel channel, bool enable)
1942{
2a205f34
SS		 1943 if (channel == OMAP_DSS_CHANNEL_LCD ||
1944 channel == OMAP_DSS_CHANNEL_LCD2)
1945 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 1946 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1947 dispc_enable_digit_out(enable);
1948 else
1949 BUG();
1950}
1951
80c39712
TV		 1952void dispc_lcd_enable_signal_polarity(bool act_high)
1953{
6ced40bf
AT		 1954 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1955 return;
1956
80c39712
TV		 1957 enable_clocks(1);
1958 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1959 enable_clocks(0);
1960}
1961
1962void dispc_lcd_enable_signal(bool enable)
1963{
6ced40bf
AT		 1964 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1965 return;
1966
80c39712
TV		 1967 enable_clocks(1);
1968 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1969 enable_clocks(0);
1970}
1971
1972void dispc_pck_free_enable(bool enable)
1973{
6ced40bf
AT		 1974 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1975 return;
1976
80c39712
TV		 1977 enable_clocks(1);
1978 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1979 enable_clocks(0);
1980}
1981
64ba4f74 1982void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712
TV		 1983{
1984 enable_clocks(1);
2a205f34
SS		 1985 if (channel == OMAP_DSS_CHANNEL_LCD2)
1986 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1987 else
1988 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 1989 enable_clocks(0);
1990}
1991
1992
64ba4f74
SS		 1993void dispc_set_lcd_display_type(enum omap_channel channel,
1994 enum omap_lcd_display_type type)
80c39712
TV		 1995{
1996 int mode;
1997
1998 switch (type) {
1999 case OMAP_DSS_LCD_DISPLAY_STN:
2000 mode = 0;
2001 break;
2002
2003 case OMAP_DSS_LCD_DISPLAY_TFT:
2004 mode = 1;
2005 break;
2006
2007 default:
2008 BUG();
2009 return;
2010 }
2011
2012 enable_clocks(1);
2a205f34
SS		 2013 if (channel == OMAP_DSS_CHANNEL_LCD2)
2014 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2015 else
2016 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2017 enable_clocks(0);
2018}
2019
2020void dispc_set_loadmode(enum omap_dss_load_mode mode)
2021{
2022 enable_clocks(1);
2023 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2024 enable_clocks(0);
2025}
2026
2027
2028void dispc_set_default_color(enum omap_channel channel, u32 color)
2029{
80c39712 2030 enable_clocks(1);
8613b000 2031 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2032 enable_clocks(0);
2033}
2034
2035u32 dispc_get_default_color(enum omap_channel channel)
2036{
80c39712
TV		 2037 u32 l;
2038
2039 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2040 channel != OMAP_DSS_CHANNEL_LCD &&
2041 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712
TV		 2042
2043 enable_clocks(1);
8613b000 2044 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2045 enable_clocks(0);
2046
2047 return l;
2048}
2049
2050void dispc_set_trans_key(enum omap_channel ch,
2051 enum omap_dss_trans_key_type type,
2052 u32 trans_key)
2053{
80c39712
TV		 2054 enable_clocks(1);
2055 if (ch == OMAP_DSS_CHANNEL_LCD)
2056 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2057 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2058 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2059 else /* OMAP_DSS_CHANNEL_LCD2 */
2060 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2061
8613b000 2062 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2063 enable_clocks(0);
2064}
2065
2066void dispc_get_trans_key(enum omap_channel ch,
2067 enum omap_dss_trans_key_type *type,
2068 u32 *trans_key)
2069{
80c39712
TV		 2070 enable_clocks(1);
2071 if (type) {
2072 if (ch == OMAP_DSS_CHANNEL_LCD)
2073 *type = REG_GET(DISPC_CONFIG, 11, 11);
2074 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2075 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2076 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2077 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2078 else
2079 BUG();
2080 }
2081
2082 if (trans_key)
8613b000 2083 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2084 enable_clocks(0);
2085}
2086
2087void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2088{
2089 enable_clocks(1);
2090 if (ch == OMAP_DSS_CHANNEL_LCD)
2091 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2092 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2093 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2094 else /* OMAP_DSS_CHANNEL_LCD2 */
2095 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2096 enable_clocks(0);
2097}
2098void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2099{
a0acb557 2100 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2101 return;
2102
2103 enable_clocks(1);
2104 if (ch == OMAP_DSS_CHANNEL_LCD)
2105 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2106 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2107 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2108 else /* OMAP_DSS_CHANNEL_LCD2 */
2109 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2110 enable_clocks(0);
2111}
2112bool dispc_alpha_blending_enabled(enum omap_channel ch)
2113{
2114 bool enabled;
2115
a0acb557 2116 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2117 return false;
2118
2119 enable_clocks(1);
2120 if (ch == OMAP_DSS_CHANNEL_LCD)
2121 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2122 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2123 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2124 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2125 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2126 else
2127 BUG();
2128 enable_clocks(0);
2129
2130 return enabled;
80c39712
TV		 2131}
2132
2133
2134bool dispc_trans_key_enabled(enum omap_channel ch)
2135{
2136 bool enabled;
2137
2138 enable_clocks(1);
2139 if (ch == OMAP_DSS_CHANNEL_LCD)
2140 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2141 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2142 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2143 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2144 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2145 else
2146 BUG();
2147 enable_clocks(0);
2148
2149 return enabled;
2150}
2151
2152
64ba4f74 2153void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2154{
2155 int code;
2156
2157 switch (data_lines) {
2158 case 12:
2159 code = 0;
2160 break;
2161 case 16:
2162 code = 1;
2163 break;
2164 case 18:
2165 code = 2;
2166 break;
2167 case 24:
2168 code = 3;
2169 break;
2170 default:
2171 BUG();
2172 return;
2173 }
2174
2175 enable_clocks(1);
2a205f34
SS		 2176 if (channel == OMAP_DSS_CHANNEL_LCD2)
2177 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2178 else
2179 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2180 enable_clocks(0);
2181}
2182
64ba4f74
SS		 2183void dispc_set_parallel_interface_mode(enum omap_channel channel,
2184 enum omap_parallel_interface_mode mode)
80c39712
TV		 2185{
2186 u32 l;
2187 int stallmode;
2188 int gpout0 = 1;
2189 int gpout1;
2190
2191 switch (mode) {
2192 case OMAP_DSS_PARALLELMODE_BYPASS:
2193 stallmode = 0;
2194 gpout1 = 1;
2195 break;
2196
2197 case OMAP_DSS_PARALLELMODE_RFBI:
2198 stallmode = 1;
2199 gpout1 = 0;
2200 break;
2201
2202 case OMAP_DSS_PARALLELMODE_DSI:
2203 stallmode = 1;
2204 gpout1 = 1;
2205 break;
2206
2207 default:
2208 BUG();
2209 return;
2210 }
2211
2212 enable_clocks(1);
2213
2a205f34
SS		 2214 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2215 l = dispc_read_reg(DISPC_CONTROL2);
2216 l = FLD_MOD(l, stallmode, 11, 11);
2217 dispc_write_reg(DISPC_CONTROL2, l);
2218 } else {
2219 l = dispc_read_reg(DISPC_CONTROL);
2220 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2221 l = FLD_MOD(l, gpout0, 15, 15);
2222 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2223 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2224 }
80c39712
TV		 2225
2226 enable_clocks(0);
2227}
2228
2229static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2230 int vsw, int vfp, int vbp)
2231{
2232 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2233 if (hsw < 1 || hsw > 64 ||
2234 hfp < 1 || hfp > 256 ||
2235 hbp < 1 || hbp > 256 ||
2236 vsw < 1 || vsw > 64 ||
2237 vfp < 0 || vfp > 255 ||
2238 vbp < 0 || vbp > 255)
2239 return false;
2240 } else {
2241 if (hsw < 1 || hsw > 256 ||
2242 hfp < 1 || hfp > 4096 ||
2243 hbp < 1 || hbp > 4096 ||
2244 vsw < 1 || vsw > 256 ||
2245 vfp < 0 || vfp > 4095 ||
2246 vbp < 0 || vbp > 4095)
2247 return false;
2248 }
2249
2250 return true;
2251}
2252
2253bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2254{
2255 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2256 timings->hbp, timings->vsw,
2257 timings->vfp, timings->vbp);
2258}
2259
64ba4f74
SS		 2260static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2261 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2262{
2263 u32 timing_h, timing_v;
2264
2265 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2266 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2267 FLD_VAL(hbp-1, 27, 20);
2268
2269 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2270 FLD_VAL(vbp, 27, 20);
2271 } else {
2272 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2273 FLD_VAL(hbp-1, 31, 20);
2274
2275 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2276 FLD_VAL(vbp, 31, 20);
2277 }
2278
2279 enable_clocks(1);
64ba4f74
SS		 2280 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2281 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2282 enable_clocks(0);
2283}
2284
2285/* change name to mode? */
64ba4f74
SS		 2286void dispc_set_lcd_timings(enum omap_channel channel,
2287 struct omap_video_timings *timings)
80c39712
TV		 2288{
2289 unsigned xtot, ytot;
2290 unsigned long ht, vt;
2291
2292 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2293 timings->hbp, timings->vsw,
2294 timings->vfp, timings->vbp))
2295 BUG();
2296
64ba4f74
SS		 2297 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2298 timings->hbp, timings->vsw, timings->vfp,
2299 timings->vbp);
80c39712 2300
64ba4f74 2301 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2302
2303 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2304 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2305
2306 ht = (timings->pixel_clock * 1000) / xtot;
2307 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2308
2a205f34
SS		 2309 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2310 timings->y_res);
80c39712
TV		 2311 DSSDBG("pck %u\n", timings->pixel_clock);
2312 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2313 timings->hsw, timings->hfp, timings->hbp,
2314 timings->vsw, timings->vfp, timings->vbp);
2315
2316 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2317}
2318
ff1b2cde
SS		 2319static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2320 u16 pck_div)
80c39712
TV		 2321{
2322 BUG_ON(lck_div < 1);
2323 BUG_ON(pck_div < 2);
2324
2325 enable_clocks(1);
ce7fa5eb 2326 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712
TV		 2327 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2328 enable_clocks(0);
2329}
2330
2a205f34
SS		 2331static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2332 int *pck_div)
80c39712
TV		 2333{
2334 u32 l;
ce7fa5eb 2335 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2336 *lck_div = FLD_GET(l, 23, 16);
2337 *pck_div = FLD_GET(l, 7, 0);
2338}
2339
2340unsigned long dispc_fclk_rate(void)
2341{
2342 unsigned long r = 0;
2343
66534e8e
TA		 2344 switch (dss_get_dispc_clk_source()) {
2345 case DSS_CLK_SRC_FCK:
6af9cd14 2346 r = dss_clk_get_rate(DSS_CLK_FCK);
66534e8e
TA		 2347 break;
2348 case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
1bb47835 2349 r = dsi_get_pll_hsdiv_dispc_rate();
66534e8e
TA		 2350 break;
2351 default:
2352 BUG();
2353 }
2354
80c39712
TV		 2355 return r;
2356}
2357
ff1b2cde 2358unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712
TV		 2359{
2360 int lcd;
2361 unsigned long r;
2362 u32 l;
2363
ce7fa5eb 2364 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2365
2366 lcd = FLD_GET(l, 23, 16);
2367
2368 r = dispc_fclk_rate();
2369
2370 return r / lcd;
2371}
2372
ff1b2cde 2373unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712
TV		 2374{
2375 int lcd, pcd;
2376 unsigned long r;
2377 u32 l;
2378
ce7fa5eb 2379 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2380
2381 lcd = FLD_GET(l, 23, 16);
2382 pcd = FLD_GET(l, 7, 0);
2383
2384 r = dispc_fclk_rate();
2385
2386 return r / lcd / pcd;
2387}
2388
2389void dispc_dump_clocks(struct seq_file *s)
2390{
2391 int lcd, pcd;
0cf35df3 2392 u32 l;
067a57e4 2393 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712
TV		 2394
2395 enable_clocks(1);
2396
80c39712
TV		 2397 seq_printf(s, "- DISPC -\n");
2398
067a57e4
AT		 2399 seq_printf(s, "dispc fclk source = %s (%s)\n",
2400 dss_get_generic_clk_source_name(dispc_clk_src),
2401 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2402
2403 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2404
0cf35df3
MR		 2405 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2406 seq_printf(s, "- DISPC-CORE-CLK -\n");
2407 l = dispc_read_reg(DISPC_DIVISOR);
2408 lcd = FLD_GET(l, 23, 16);
2409
2410 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2411 (dispc_fclk_rate()/lcd), lcd);
2412 }
2a205f34
SS		 2413 seq_printf(s, "- LCD1 -\n");
2414
2415 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2416
ff1b2cde
SS		 2417 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2418 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2419 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2420 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2421 if (dss_has_feature(FEAT_MGR_LCD2)) {
2422 seq_printf(s, "- LCD2 -\n");
2423
2424 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2425
2a205f34
SS		 2426 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2427 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2428 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2429 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2430 }
80c39712
TV		 2431 enable_clocks(0);
2432}
2433
dfc0fd8d
TV		 2434#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2435void dispc_dump_irqs(struct seq_file *s)
2436{
2437 unsigned long flags;
2438 struct dispc_irq_stats stats;
2439
2440 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2441
2442 stats = dispc.irq_stats;
2443 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2444 dispc.irq_stats.last_reset = jiffies;
2445
2446 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2447
2448 seq_printf(s, "period %u ms\n",
2449 jiffies_to_msecs(jiffies - stats.last_reset));
2450
2451 seq_printf(s, "irqs %d\n", stats.irq_count);
2452#define PIS(x) \
2453 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2454
2455 PIS(FRAMEDONE);
2456 PIS(VSYNC);
2457 PIS(EVSYNC_EVEN);
2458 PIS(EVSYNC_ODD);
2459 PIS(ACBIAS_COUNT_STAT);
2460 PIS(PROG_LINE_NUM);
2461 PIS(GFX_FIFO_UNDERFLOW);
2462 PIS(GFX_END_WIN);
2463 PIS(PAL_GAMMA_MASK);
2464 PIS(OCP_ERR);
2465 PIS(VID1_FIFO_UNDERFLOW);
2466 PIS(VID1_END_WIN);
2467 PIS(VID2_FIFO_UNDERFLOW);
2468 PIS(VID2_END_WIN);
2469 PIS(SYNC_LOST);
2470 PIS(SYNC_LOST_DIGIT);
2471 PIS(WAKEUP);
2a205f34
SS		 2472 if (dss_has_feature(FEAT_MGR_LCD2)) {
2473 PIS(FRAMEDONE2);
2474 PIS(VSYNC2);
2475 PIS(ACBIAS_COUNT_STAT2);
2476 PIS(SYNC_LOST2);
2477 }
dfc0fd8d
TV		 2478#undef PIS
2479}
dfc0fd8d
TV		 2480#endif
2481
80c39712
TV		 2482void dispc_dump_regs(struct seq_file *s)
2483{
2484#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2485
6af9cd14 2486 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2487
2488 DUMPREG(DISPC_REVISION);
2489 DUMPREG(DISPC_SYSCONFIG);
2490 DUMPREG(DISPC_SYSSTATUS);
2491 DUMPREG(DISPC_IRQSTATUS);
2492 DUMPREG(DISPC_IRQENABLE);
2493 DUMPREG(DISPC_CONTROL);
2494 DUMPREG(DISPC_CONFIG);
2495 DUMPREG(DISPC_CAPABLE);
8613b000
SS		 2496 DUMPREG(DISPC_DEFAULT_COLOR(0));
2497 DUMPREG(DISPC_DEFAULT_COLOR(1));
2498 DUMPREG(DISPC_TRANS_COLOR(0));
2499 DUMPREG(DISPC_TRANS_COLOR(1));
80c39712
TV		 2500 DUMPREG(DISPC_LINE_STATUS);
2501 DUMPREG(DISPC_LINE_NUMBER);
8613b000
SS		 2502 DUMPREG(DISPC_TIMING_H(0));
2503 DUMPREG(DISPC_TIMING_V(0));
2504 DUMPREG(DISPC_POL_FREQ(0));
ce7fa5eb 2505 DUMPREG(DISPC_DIVISORo(0));
80c39712
TV		 2506 DUMPREG(DISPC_GLOBAL_ALPHA);
2507 DUMPREG(DISPC_SIZE_DIG);
8613b000 2508 DUMPREG(DISPC_SIZE_LCD(0));
2a205f34
SS		 2509 if (dss_has_feature(FEAT_MGR_LCD2)) {
2510 DUMPREG(DISPC_CONTROL2);
2511 DUMPREG(DISPC_CONFIG2);
2512 DUMPREG(DISPC_DEFAULT_COLOR(2));
2513 DUMPREG(DISPC_TRANS_COLOR(2));
2514 DUMPREG(DISPC_TIMING_H(2));
2515 DUMPREG(DISPC_TIMING_V(2));
2516 DUMPREG(DISPC_POL_FREQ(2));
ce7fa5eb 2517 DUMPREG(DISPC_DIVISORo(2));
2a205f34
SS		 2518 DUMPREG(DISPC_SIZE_LCD(2));
2519 }
80c39712
TV		 2520
2521 DUMPREG(DISPC_GFX_BA0);
2522 DUMPREG(DISPC_GFX_BA1);
2523 DUMPREG(DISPC_GFX_POSITION);
2524 DUMPREG(DISPC_GFX_SIZE);
2525 DUMPREG(DISPC_GFX_ATTRIBUTES);
2526 DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2527 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2528 DUMPREG(DISPC_GFX_ROW_INC);
2529 DUMPREG(DISPC_GFX_PIXEL_INC);
2530 DUMPREG(DISPC_GFX_WINDOW_SKIP);
2531 DUMPREG(DISPC_GFX_TABLE_BA);
2532
8613b000
SS		 2533 DUMPREG(DISPC_DATA_CYCLE1(0));
2534 DUMPREG(DISPC_DATA_CYCLE2(0));
2535 DUMPREG(DISPC_DATA_CYCLE3(0));
80c39712 2536
8613b000
SS		 2537 DUMPREG(DISPC_CPR_COEF_R(0));
2538 DUMPREG(DISPC_CPR_COEF_G(0));
2539 DUMPREG(DISPC_CPR_COEF_B(0));
2a205f34
SS		 2540 if (dss_has_feature(FEAT_MGR_LCD2)) {
2541 DUMPREG(DISPC_DATA_CYCLE1(2));
2542 DUMPREG(DISPC_DATA_CYCLE2(2));
2543 DUMPREG(DISPC_DATA_CYCLE3(2));
2544
2545 DUMPREG(DISPC_CPR_COEF_R(2));
2546 DUMPREG(DISPC_CPR_COEF_G(2));
2547 DUMPREG(DISPC_CPR_COEF_B(2));
2548 }
80c39712
TV		 2549
2550 DUMPREG(DISPC_GFX_PRELOAD);
2551
2552 DUMPREG(DISPC_VID_BA0(0));
2553 DUMPREG(DISPC_VID_BA1(0));
2554 DUMPREG(DISPC_VID_POSITION(0));
2555 DUMPREG(DISPC_VID_SIZE(0));
2556 DUMPREG(DISPC_VID_ATTRIBUTES(0));
2557 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2558 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2559 DUMPREG(DISPC_VID_ROW_INC(0));
2560 DUMPREG(DISPC_VID_PIXEL_INC(0));
2561 DUMPREG(DISPC_VID_FIR(0));
2562 DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2563 DUMPREG(DISPC_VID_ACCU0(0));
2564 DUMPREG(DISPC_VID_ACCU1(0));
2565
2566 DUMPREG(DISPC_VID_BA0(1));
2567 DUMPREG(DISPC_VID_BA1(1));
2568 DUMPREG(DISPC_VID_POSITION(1));
2569 DUMPREG(DISPC_VID_SIZE(1));
2570 DUMPREG(DISPC_VID_ATTRIBUTES(1));
2571 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2572 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2573 DUMPREG(DISPC_VID_ROW_INC(1));
2574 DUMPREG(DISPC_VID_PIXEL_INC(1));
2575 DUMPREG(DISPC_VID_FIR(1));
2576 DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2577 DUMPREG(DISPC_VID_ACCU0(1));
2578 DUMPREG(DISPC_VID_ACCU1(1));
2579
2580 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2581 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2582 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2583 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2584 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2585 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2586 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2587 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2588 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2589 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2590 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2591 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2592 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2593 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2594 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2595 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2596 DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2597 DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2598 DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2599 DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2600 DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2601 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2602 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2603 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2604 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2605 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2606 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2607 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2608 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2609
2610 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2611 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2612 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2613 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2614 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2615 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2616 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2617 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2618 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2619 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2620 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2621 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2622 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2623 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2624 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2625 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2626 DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2627 DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2628 DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2629 DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2630 DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2631 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2632 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2633 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2634 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2635 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2636 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2637 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2638 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2639
2640 DUMPREG(DISPC_VID_PRELOAD(0));
2641 DUMPREG(DISPC_VID_PRELOAD(1));
2642
6af9cd14 2643 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2644#undef DUMPREG
2645}
2646
ff1b2cde
SS		 2647static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2648 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2649{
2650 u32 l = 0;
2651
2652 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2653 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2654
2655 l |= FLD_VAL(onoff, 17, 17);
2656 l |= FLD_VAL(rf, 16, 16);
2657 l |= FLD_VAL(ieo, 15, 15);
2658 l |= FLD_VAL(ipc, 14, 14);
2659 l |= FLD_VAL(ihs, 13, 13);
2660 l |= FLD_VAL(ivs, 12, 12);
2661 l |= FLD_VAL(acbi, 11, 8);
2662 l |= FLD_VAL(acb, 7, 0);
2663
2664 enable_clocks(1);
ff1b2cde 2665 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2666 enable_clocks(0);
2667}
2668
ff1b2cde
SS		 2669void dispc_set_pol_freq(enum omap_channel channel,
2670 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2671{
ff1b2cde 2672 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2673 (config & OMAP_DSS_LCD_RF) != 0,
2674 (config & OMAP_DSS_LCD_IEO) != 0,
2675 (config & OMAP_DSS_LCD_IPC) != 0,
2676 (config & OMAP_DSS_LCD_IHS) != 0,
2677 (config & OMAP_DSS_LCD_IVS) != 0,
2678 acbi, acb);
2679}
2680
2681/* with fck as input clock rate, find dispc dividers that produce req_pck */
2682void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2683 struct dispc_clock_info *cinfo)
2684{
2685 u16 pcd_min = is_tft ? 2 : 3;
2686 unsigned long best_pck;
2687 u16 best_ld, cur_ld;
2688 u16 best_pd, cur_pd;
2689
2690 best_pck = 0;
2691 best_ld = 0;
2692 best_pd = 0;
2693
2694 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2695 unsigned long lck = fck / cur_ld;
2696
2697 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2698 unsigned long pck = lck / cur_pd;
2699 long old_delta = abs(best_pck - req_pck);
2700 long new_delta = abs(pck - req_pck);
2701
2702 if (best_pck == 0 || new_delta < old_delta) {
2703 best_pck = pck;
2704 best_ld = cur_ld;
2705 best_pd = cur_pd;
2706
2707 if (pck == req_pck)
2708 goto found;
2709 }
2710
2711 if (pck < req_pck)
2712 break;
2713 }
2714
2715 if (lck / pcd_min < req_pck)
2716 break;
2717 }
2718
2719found:
2720 cinfo->lck_div = best_ld;
2721 cinfo->pck_div = best_pd;
2722 cinfo->lck = fck / cinfo->lck_div;
2723 cinfo->pck = cinfo->lck / cinfo->pck_div;
2724}
2725
2726/* calculate clock rates using dividers in cinfo */
2727int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2728 struct dispc_clock_info *cinfo)
2729{
2730 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2731 return -EINVAL;
2732 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2733 return -EINVAL;
2734
2735 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2736 cinfo->pck = cinfo->lck / cinfo->pck_div;
2737
2738 return 0;
2739}
2740
ff1b2cde
SS		 2741int dispc_set_clock_div(enum omap_channel channel,
2742 struct dispc_clock_info *cinfo)
80c39712
TV		 2743{
2744 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2745 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2746
ff1b2cde 2747 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2748
2749 return 0;
2750}
2751
ff1b2cde
SS		 2752int dispc_get_clock_div(enum omap_channel channel,
2753 struct dispc_clock_info *cinfo)
80c39712
TV		 2754{
2755 unsigned long fck;
2756
2757 fck = dispc_fclk_rate();
2758
ce7fa5eb
MR		 2759 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2760 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2761
2762 cinfo->lck = fck / cinfo->lck_div;
2763 cinfo->pck = cinfo->lck / cinfo->pck_div;
2764
2765 return 0;
2766}
2767
2768/* dispc.irq_lock has to be locked by the caller */
2769static void _omap_dispc_set_irqs(void)
2770{
2771 u32 mask;
2772 u32 old_mask;
2773 int i;
2774 struct omap_dispc_isr_data *isr_data;
2775
2776 mask = dispc.irq_error_mask;
2777
2778 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2779 isr_data = &dispc.registered_isr[i];
2780
2781 if (isr_data->isr == NULL)
2782 continue;
2783
2784 mask |= isr_data->mask;
2785 }
2786
2787 enable_clocks(1);
2788
2789 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2790 /* clear the irqstatus for newly enabled irqs */
2791 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2792
2793 dispc_write_reg(DISPC_IRQENABLE, mask);
2794
2795 enable_clocks(0);
2796}
2797
2798int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2799{
2800 int i;
2801 int ret;
2802 unsigned long flags;
2803 struct omap_dispc_isr_data *isr_data;
2804
2805 if (isr == NULL)
2806 return -EINVAL;
2807
2808 spin_lock_irqsave(&dispc.irq_lock, flags);
2809
2810 /* check for duplicate entry */
2811 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2812 isr_data = &dispc.registered_isr[i];
2813 if (isr_data->isr == isr && isr_data->arg == arg &&
2814 isr_data->mask == mask) {
2815 ret = -EINVAL;
2816 goto err;
2817 }
2818 }
2819
2820 isr_data = NULL;
2821 ret = -EBUSY;
2822
2823 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2824 isr_data = &dispc.registered_isr[i];
2825
2826 if (isr_data->isr != NULL)
2827 continue;
2828
2829 isr_data->isr = isr;
2830 isr_data->arg = arg;
2831 isr_data->mask = mask;
2832 ret = 0;
2833
2834 break;
2835 }
2836
b9cb0984
TV		 2837 if (ret)
2838 goto err;
2839
80c39712
TV		 2840 _omap_dispc_set_irqs();
2841
2842 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2843
2844 return 0;
2845err:
2846 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2847
2848 return ret;
2849}
2850EXPORT_SYMBOL(omap_dispc_register_isr);
2851
2852int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2853{
2854 int i;
2855 unsigned long flags;
2856 int ret = -EINVAL;
2857 struct omap_dispc_isr_data *isr_data;
2858
2859 spin_lock_irqsave(&dispc.irq_lock, flags);
2860
2861 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2862 isr_data = &dispc.registered_isr[i];
2863 if (isr_data->isr != isr || isr_data->arg != arg ||
2864 isr_data->mask != mask)
2865 continue;
2866
2867 /* found the correct isr */
2868
2869 isr_data->isr = NULL;
2870 isr_data->arg = NULL;
2871 isr_data->mask = 0;
2872
2873 ret = 0;
2874 break;
2875 }
2876
2877 if (ret == 0)
2878 _omap_dispc_set_irqs();
2879
2880 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2881
2882 return ret;
2883}
2884EXPORT_SYMBOL(omap_dispc_unregister_isr);
2885
2886#ifdef DEBUG
2887static void print_irq_status(u32 status)
2888{
2889 if ((status & dispc.irq_error_mask) == 0)
2890 return;
2891
2892 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2893
2894#define PIS(x) \
2895 if (status & DISPC_IRQ_##x) \
2896 printk(#x " ");
2897 PIS(GFX_FIFO_UNDERFLOW);
2898 PIS(OCP_ERR);
2899 PIS(VID1_FIFO_UNDERFLOW);
2900 PIS(VID2_FIFO_UNDERFLOW);
2901 PIS(SYNC_LOST);
2902 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 2903 if (dss_has_feature(FEAT_MGR_LCD2))
2904 PIS(SYNC_LOST2);
80c39712
TV		 2905#undef PIS
2906
2907 printk("\n");
2908}
2909#endif
2910
2911/* Called from dss.c. Note that we don't touch clocks here,
2912 * but we presume they are on because we got an IRQ. However,
2913 * an irq handler may turn the clocks off, so we may not have
2914 * clock later in the function. */
affe360d 2915static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 2916{
2917 int i;
affe360d 2918 u32 irqstatus, irqenable;
80c39712
TV		 2919 u32 handledirqs = 0;
2920 u32 unhandled_errors;
2921 struct omap_dispc_isr_data *isr_data;
2922 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2923
2924 spin_lock(&dispc.irq_lock);
2925
2926 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 2927 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2928
2929 /* IRQ is not for us */
2930 if (!(irqstatus & irqenable)) {
2931 spin_unlock(&dispc.irq_lock);
2932 return IRQ_NONE;
2933 }
80c39712 2934
dfc0fd8d
TV		 2935#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2936 spin_lock(&dispc.irq_stats_lock);
2937 dispc.irq_stats.irq_count++;
2938 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2939 spin_unlock(&dispc.irq_stats_lock);
2940#endif
2941
80c39712
TV		 2942#ifdef DEBUG
2943 if (dss_debug)
2944 print_irq_status(irqstatus);
2945#endif
2946 /* Ack the interrupt. Do it here before clocks are possibly turned
2947 * off */
2948 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2949 /* flush posted write */
2950 dispc_read_reg(DISPC_IRQSTATUS);
2951
2952 /* make a copy and unlock, so that isrs can unregister
2953 * themselves */
2954 memcpy(registered_isr, dispc.registered_isr,
2955 sizeof(registered_isr));
2956
2957 spin_unlock(&dispc.irq_lock);
2958
2959 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2960 isr_data = &registered_isr[i];
2961
2962 if (!isr_data->isr)
2963 continue;
2964
2965 if (isr_data->mask & irqstatus) {
2966 isr_data->isr(isr_data->arg, irqstatus);
2967 handledirqs |= isr_data->mask;
2968 }
2969 }
2970
2971 spin_lock(&dispc.irq_lock);
2972
2973 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2974
2975 if (unhandled_errors) {
2976 dispc.error_irqs |= unhandled_errors;
2977
2978 dispc.irq_error_mask &= ~unhandled_errors;
2979 _omap_dispc_set_irqs();
2980
2981 schedule_work(&dispc.error_work);
2982 }
2983
2984 spin_unlock(&dispc.irq_lock);
affe360d 2985
2986 return IRQ_HANDLED;
80c39712
TV		 2987}
2988
2989static void dispc_error_worker(struct work_struct *work)
2990{
2991 int i;
2992 u32 errors;
2993 unsigned long flags;
2994
2995 spin_lock_irqsave(&dispc.irq_lock, flags);
2996 errors = dispc.error_irqs;
2997 dispc.error_irqs = 0;
2998 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2999
3000 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
3001 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
3002 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3003 struct omap_overlay *ovl;
3004 ovl = omap_dss_get_overlay(i);
3005
3006 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3007 continue;
3008
3009 if (ovl->id == 0) {
3010 dispc_enable_plane(ovl->id, 0);
3011 dispc_go(ovl->manager->id);
3012 mdelay(50);
3013 break;
3014 }
3015 }
3016 }
3017
3018 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3019 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3020 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3021 struct omap_overlay *ovl;
3022 ovl = omap_dss_get_overlay(i);
3023
3024 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3025 continue;
3026
3027 if (ovl->id == 1) {
3028 dispc_enable_plane(ovl->id, 0);
3029 dispc_go(ovl->manager->id);
3030 mdelay(50);
3031 break;
3032 }
3033 }
3034 }
3035
3036 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3037 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3038 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3039 struct omap_overlay *ovl;
3040 ovl = omap_dss_get_overlay(i);
3041
3042 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3043 continue;
3044
3045 if (ovl->id == 2) {
3046 dispc_enable_plane(ovl->id, 0);
3047 dispc_go(ovl->manager->id);
3048 mdelay(50);
3049 break;
3050 }
3051 }
3052 }
3053
3054 if (errors & DISPC_IRQ_SYNC_LOST) {
3055 struct omap_overlay_manager *manager = NULL;
3056 bool enable = false;
3057
3058 DSSERR("SYNC_LOST, disabling LCD\n");
3059
3060 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3061 struct omap_overlay_manager *mgr;
3062 mgr = omap_dss_get_overlay_manager(i);
3063
3064 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3065 manager = mgr;
3066 enable = mgr->device->state ==
3067 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3068 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3069 break;
3070 }
3071 }
3072
3073 if (manager) {
37ac60e4 3074 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3075 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3076 struct omap_overlay *ovl;
3077 ovl = omap_dss_get_overlay(i);
3078
3079 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3080 continue;
3081
3082 if (ovl->id != 0 && ovl->manager == manager)
3083 dispc_enable_plane(ovl->id, 0);
3084 }
3085
3086 dispc_go(manager->id);
3087 mdelay(50);
3088 if (enable)
37ac60e4 3089 dssdev->driver->enable(dssdev);
80c39712
TV		 3090 }
3091 }
3092
3093 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3094 struct omap_overlay_manager *manager = NULL;
3095 bool enable = false;
3096
3097 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3098
3099 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3100 struct omap_overlay_manager *mgr;
3101 mgr = omap_dss_get_overlay_manager(i);
3102
3103 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3104 manager = mgr;
3105 enable = mgr->device->state ==
3106 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3107 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3108 break;
3109 }
3110 }
3111
3112 if (manager) {
37ac60e4 3113 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3114 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3115 struct omap_overlay *ovl;
3116 ovl = omap_dss_get_overlay(i);
3117
3118 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3119 continue;
3120
3121 if (ovl->id != 0 && ovl->manager == manager)
3122 dispc_enable_plane(ovl->id, 0);
3123 }
3124
3125 dispc_go(manager->id);
3126 mdelay(50);
3127 if (enable)
37ac60e4 3128 dssdev->driver->enable(dssdev);
80c39712
TV		 3129 }
3130 }
3131
2a205f34
SS		 3132 if (errors & DISPC_IRQ_SYNC_LOST2) {
3133 struct omap_overlay_manager *manager = NULL;
3134 bool enable = false;
3135
3136 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3137
3138 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3139 struct omap_overlay_manager *mgr;
3140 mgr = omap_dss_get_overlay_manager(i);
3141
3142 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3143 manager = mgr;
3144 enable = mgr->device->state ==
3145 OMAP_DSS_DISPLAY_ACTIVE;
3146 mgr->device->driver->disable(mgr->device);
3147 break;
3148 }
3149 }
3150
3151 if (manager) {
3152 struct omap_dss_device *dssdev = manager->device;
3153 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3154 struct omap_overlay *ovl;
3155 ovl = omap_dss_get_overlay(i);
3156
3157 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3158 continue;
3159
3160 if (ovl->id != 0 && ovl->manager == manager)
3161 dispc_enable_plane(ovl->id, 0);
3162 }
3163
3164 dispc_go(manager->id);
3165 mdelay(50);
3166 if (enable)
3167 dssdev->driver->enable(dssdev);
3168 }
3169 }
3170
80c39712
TV		 3171 if (errors & DISPC_IRQ_OCP_ERR) {
3172 DSSERR("OCP_ERR\n");
3173 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3174 struct omap_overlay_manager *mgr;
3175 mgr = omap_dss_get_overlay_manager(i);
3176
3177 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3178 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3179 }
3180 }
3181
3182 spin_lock_irqsave(&dispc.irq_lock, flags);
3183 dispc.irq_error_mask |= errors;
3184 _omap_dispc_set_irqs();
3185 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3186}
3187
3188int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3189{
3190 void dispc_irq_wait_handler(void *data, u32 mask)
3191 {
3192 complete((struct completion *)data);
3193 }
3194
3195 int r;
3196 DECLARE_COMPLETION_ONSTACK(completion);
3197
3198 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3199 irqmask);
3200
3201 if (r)
3202 return r;
3203
3204 timeout = wait_for_completion_timeout(&completion, timeout);
3205
3206 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3207
3208 if (timeout == 0)
3209 return -ETIMEDOUT;
3210
3211 if (timeout == -ERESTARTSYS)
3212 return -ERESTARTSYS;
3213
3214 return 0;
3215}
3216
3217int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3218 unsigned long timeout)
3219{
3220 void dispc_irq_wait_handler(void *data, u32 mask)
3221 {
3222 complete((struct completion *)data);
3223 }
3224
3225 int r;
3226 DECLARE_COMPLETION_ONSTACK(completion);
3227
3228 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3229 irqmask);
3230
3231 if (r)
3232 return r;
3233
3234 timeout = wait_for_completion_interruptible_timeout(&completion,
3235 timeout);
3236
3237 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3238
3239 if (timeout == 0)
3240 return -ETIMEDOUT;
3241
3242 if (timeout == -ERESTARTSYS)
3243 return -ERESTARTSYS;
3244
3245 return 0;
3246}
3247
3248#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3249void dispc_fake_vsync_irq(void)
3250{
3251 u32 irqstatus = DISPC_IRQ_VSYNC;
3252 int i;
3253
ab83b14c 3254 WARN_ON(!in_interrupt());
80c39712
TV		 3255
3256 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3257 struct omap_dispc_isr_data *isr_data;
3258 isr_data = &dispc.registered_isr[i];
3259
3260 if (!isr_data->isr)
3261 continue;
3262
3263 if (isr_data->mask & irqstatus)
3264 isr_data->isr(isr_data->arg, irqstatus);
3265 }
80c39712
TV		 3266}
3267#endif
3268
3269static void _omap_dispc_initialize_irq(void)
3270{
3271 unsigned long flags;
3272
3273 spin_lock_irqsave(&dispc.irq_lock, flags);
3274
3275 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3276
3277 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3278 if (dss_has_feature(FEAT_MGR_LCD2))
3279 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3280
3281 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3282 * so clear it */
3283 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3284
3285 _omap_dispc_set_irqs();
3286
3287 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3288}
3289
3290void dispc_enable_sidle(void)
3291{
3292 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3293}
3294
3295void dispc_disable_sidle(void)
3296{
3297 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3298}
3299
3300static void _omap_dispc_initial_config(void)
3301{
3302 u32 l;
3303
3304 l = dispc_read_reg(DISPC_SYSCONFIG);
3305 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3306 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3307 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3308 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3309 dispc_write_reg(DISPC_SYSCONFIG, l);
3310
0cf35df3
MR		 3311 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3312 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3313 l = dispc_read_reg(DISPC_DIVISOR);
3314 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3315 l = FLD_MOD(l, 1, 0, 0);
3316 l = FLD_MOD(l, 1, 23, 16);
3317 dispc_write_reg(DISPC_DIVISOR, l);
3318 }
3319
80c39712 3320 /* FUNCGATED */
6ced40bf
AT		 3321 if (dss_has_feature(FEAT_FUNCGATED))
3322 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3323
3324 /* L3 firewall setting: enable access to OCM RAM */
3325 /* XXX this should be somewhere in plat-omap */
3326 if (cpu_is_omap24xx())
3327 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3328
3329 _dispc_setup_color_conv_coef();
3330
3331 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3332
3333 dispc_read_plane_fifo_sizes();
3334}
3335
80c39712
TV		 3336int dispc_enable_plane(enum omap_plane plane, bool enable)
3337{
3338 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3339
3340 enable_clocks(1);
3341 _dispc_enable_plane(plane, enable);
3342 enable_clocks(0);
3343
3344 return 0;
3345}
3346
3347int dispc_setup_plane(enum omap_plane plane,
3348 u32 paddr, u16 screen_width,
3349 u16 pos_x, u16 pos_y,
3350 u16 width, u16 height,
3351 u16 out_width, u16 out_height,
3352 enum omap_color_mode color_mode,
3353 bool ilace,
3354 enum omap_dss_rotation_type rotation_type,
fd28a390 3355 u8 rotation, bool mirror, u8 global_alpha,
18faa1b6 3356 u8 pre_mult_alpha, enum omap_channel channel)
80c39712
TV		 3357{
3358 int r = 0;
3359
3360 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
18faa1b6 3361 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
80c39712
TV		 3362 plane, paddr, screen_width, pos_x, pos_y,
3363 width, height,
3364 out_width, out_height,
3365 ilace, color_mode,
18faa1b6 3366 rotation, mirror, channel);
80c39712
TV		 3367
3368 enable_clocks(1);
3369
3370 r = _dispc_setup_plane(plane,
3371 paddr, screen_width,
3372 pos_x, pos_y,
3373 width, height,
3374 out_width, out_height,
3375 color_mode, ilace,
3376 rotation_type,
3377 rotation, mirror,
fd28a390 3378 global_alpha,
18faa1b6 3379 pre_mult_alpha, channel);
80c39712
TV		 3380
3381 enable_clocks(0);
3382
3383 return r;
3384}
060b6d9c
SG		 3385
3386/* DISPC HW IP initialisation */
3387static int omap_dispchw_probe(struct platform_device *pdev)
3388{
3389 u32 rev;
affe360d 3390 int r = 0;
ea9da36a
SG		 3391 struct resource *dispc_mem;
3392
060b6d9c
SG		 3393 dispc.pdev = pdev;
3394
3395 spin_lock_init(&dispc.irq_lock);
3396
3397#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3398 spin_lock_init(&dispc.irq_stats_lock);
3399 dispc.irq_stats.last_reset = jiffies;
3400#endif
3401
3402 INIT_WORK(&dispc.error_work, dispc_error_worker);
3403
ea9da36a
SG		 3404 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3405 if (!dispc_mem) {
3406 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3407 r = -EINVAL;
3408 goto fail0;
ea9da36a
SG		 3409 }
3410 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3411 if (!dispc.base) {
3412 DSSERR("can't ioremap DISPC\n");
affe360d 3413 r = -ENOMEM;
3414 goto fail0;
3415 }
3416 dispc.irq = platform_get_irq(dispc.pdev, 0);
3417 if (dispc.irq < 0) {
3418 DSSERR("platform_get_irq failed\n");
3419 r = -ENODEV;
3420 goto fail1;
3421 }
3422
3423 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3424 "OMAP DISPC", dispc.pdev);
3425 if (r < 0) {
3426 DSSERR("request_irq failed\n");
3427 goto fail1;
060b6d9c
SG		 3428 }
3429
3430 enable_clocks(1);
3431
3432 _omap_dispc_initial_config();
3433
3434 _omap_dispc_initialize_irq();
3435
3436 dispc_save_context();
3437
3438 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3439 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3440 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3441
3442 enable_clocks(0);
3443
3444 return 0;
affe360d 3445fail1:
3446 iounmap(dispc.base);
3447fail0:
3448 return r;
060b6d9c
SG		 3449}
3450
3451static int omap_dispchw_remove(struct platform_device *pdev)
3452{
affe360d 3453 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3454 iounmap(dispc.base);
3455 return 0;
3456}
3457
3458static struct platform_driver omap_dispchw_driver = {
3459 .probe = omap_dispchw_probe,
3460 .remove = omap_dispchw_remove,
3461 .driver = {
3462 .name = "omapdss_dispc",
3463 .owner = THIS_MODULE,
3464 },
3465};
3466
3467int dispc_init_platform_driver(void)
3468{
3469 return platform_driver_register(&omap_dispchw_driver);
3470}
3471
3472void dispc_uninit_platform_driver(void)
3473{
3474 return platform_driver_unregister(&omap_dispchw_driver);
3475}
Linux kernel - Deliverables
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