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OMAPDSS: DSI: Support command mode interleaving during video mode blanking periods
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
80c39712
TV		 122static void _omap_dispc_set_irqs(void);
123
55978cc2 124static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 125{
55978cc2 126 __raw_writel(val, dispc.base + idx);
80c39712
TV		 127}
128
55978cc2 129static inline u32 dispc_read_reg(const u16 idx)
80c39712 130{
55978cc2 131 return __raw_readl(dispc.base + idx);
80c39712
TV		 132}
133
134#define SR(reg) \
55978cc2 135 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 136#define RR(reg) \
55978cc2 137 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 138
4fbafaf3 139static void dispc_save_context(void)
80c39712 140{
c6104b8e 141 int i, j;
80c39712 142
4fbafaf3
TV		 143 DSSDBG("dispc_save_context\n");
144
80c39712
TV		 145 SR(IRQENABLE);
146 SR(CONTROL);
147 SR(CONFIG);
80c39712 148 SR(LINE_NUMBER);
11354dd5
AT		 149 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
150 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 151 SR(GLOBAL_ALPHA);
2a205f34
SS		 152 if (dss_has_feature(FEAT_MGR_LCD2)) {
153 SR(CONTROL2);
2a205f34
SS		 154 SR(CONFIG2);
155 }
80c39712 156
c6104b8e
AT		 157 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
158 SR(DEFAULT_COLOR(i));
159 SR(TRANS_COLOR(i));
160 SR(SIZE_MGR(i));
161 if (i == OMAP_DSS_CHANNEL_DIGIT)
162 continue;
163 SR(TIMING_H(i));
164 SR(TIMING_V(i));
165 SR(POL_FREQ(i));
166 SR(DIVISORo(i));
167
168 SR(DATA_CYCLE1(i));
169 SR(DATA_CYCLE2(i));
170 SR(DATA_CYCLE3(i));
171
332e9d70 172 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 173 SR(CPR_COEF_R(i));
174 SR(CPR_COEF_G(i));
175 SR(CPR_COEF_B(i));
332e9d70 176 }
2a205f34 177 }
80c39712 178
c6104b8e
AT		 179 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
180 SR(OVL_BA0(i));
181 SR(OVL_BA1(i));
182 SR(OVL_POSITION(i));
183 SR(OVL_SIZE(i));
184 SR(OVL_ATTRIBUTES(i));
185 SR(OVL_FIFO_THRESHOLD(i));
186 SR(OVL_ROW_INC(i));
187 SR(OVL_PIXEL_INC(i));
188 if (dss_has_feature(FEAT_PRELOAD))
189 SR(OVL_PRELOAD(i));
190 if (i == OMAP_DSS_GFX) {
191 SR(OVL_WINDOW_SKIP(i));
192 SR(OVL_TABLE_BA(i));
193 continue;
194 }
195 SR(OVL_FIR(i));
196 SR(OVL_PICTURE_SIZE(i));
197 SR(OVL_ACCU0(i));
198 SR(OVL_ACCU1(i));
9b372c2d 199
c6104b8e
AT		 200 for (j = 0; j < 8; j++)
201 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 202
c6104b8e
AT		 203 for (j = 0; j < 8; j++)
204 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 205
c6104b8e
AT		 206 for (j = 0; j < 5; j++)
207 SR(OVL_CONV_COEF(i, j));
ab5ca071 208
c6104b8e
AT		 209 if (dss_has_feature(FEAT_FIR_COEF_V)) {
210 for (j = 0; j < 8; j++)
211 SR(OVL_FIR_COEF_V(i, j));
212 }
9b372c2d 213
c6104b8e
AT		 214 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
215 SR(OVL_BA0_UV(i));
216 SR(OVL_BA1_UV(i));
217 SR(OVL_FIR2(i));
218 SR(OVL_ACCU2_0(i));
219 SR(OVL_ACCU2_1(i));
ab5ca071 220
c6104b8e
AT		 221 for (j = 0; j < 8; j++)
222 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 223
c6104b8e
AT		 224 for (j = 0; j < 8; j++)
225 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 226
c6104b8e
AT		 227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V2(i, j));
229 }
230 if (dss_has_feature(FEAT_ATTR2))
231 SR(OVL_ATTRIBUTES2(i));
ab5ca071 232 }
0cf35df3
MR		 233
234 if (dss_has_feature(FEAT_CORE_CLK_DIV))
235 SR(DIVISOR);
49ea86f3 236
00928eaf 237 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 238 dispc.ctx_valid = true;
239
240 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 241}
242
4fbafaf3 243static void dispc_restore_context(void)
80c39712 244{
c6104b8e 245 int i, j, ctx;
4fbafaf3
TV		 246
247 DSSDBG("dispc_restore_context\n");
248
49ea86f3
TV		 249 if (!dispc.ctx_valid)
250 return;
251
00928eaf 252 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 253
254 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
255 return;
256
257 DSSDBG("ctx_loss_count: saved %d, current %d\n",
258 dispc.ctx_loss_cnt, ctx);
259
75c7d59d 260 /*RR(IRQENABLE);*/
80c39712
TV		 261 /*RR(CONTROL);*/
262 RR(CONFIG);
80c39712 263 RR(LINE_NUMBER);
11354dd5
AT		 264 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
265 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 266 RR(GLOBAL_ALPHA);
c6104b8e 267 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 268 RR(CONFIG2);
80c39712 269
c6104b8e
AT		 270 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
271 RR(DEFAULT_COLOR(i));
272 RR(TRANS_COLOR(i));
273 RR(SIZE_MGR(i));
274 if (i == OMAP_DSS_CHANNEL_DIGIT)
275 continue;
276 RR(TIMING_H(i));
277 RR(TIMING_V(i));
278 RR(POL_FREQ(i));
279 RR(DIVISORo(i));
280
281 RR(DATA_CYCLE1(i));
282 RR(DATA_CYCLE2(i));
283 RR(DATA_CYCLE3(i));
2a205f34 284
332e9d70 285 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 286 RR(CPR_COEF_R(i));
287 RR(CPR_COEF_G(i));
288 RR(CPR_COEF_B(i));
332e9d70 289 }
2a205f34 290 }
80c39712 291
c6104b8e
AT		 292 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
293 RR(OVL_BA0(i));
294 RR(OVL_BA1(i));
295 RR(OVL_POSITION(i));
296 RR(OVL_SIZE(i));
297 RR(OVL_ATTRIBUTES(i));
298 RR(OVL_FIFO_THRESHOLD(i));
299 RR(OVL_ROW_INC(i));
300 RR(OVL_PIXEL_INC(i));
301 if (dss_has_feature(FEAT_PRELOAD))
302 RR(OVL_PRELOAD(i));
303 if (i == OMAP_DSS_GFX) {
304 RR(OVL_WINDOW_SKIP(i));
305 RR(OVL_TABLE_BA(i));
306 continue;
307 }
308 RR(OVL_FIR(i));
309 RR(OVL_PICTURE_SIZE(i));
310 RR(OVL_ACCU0(i));
311 RR(OVL_ACCU1(i));
9b372c2d 312
c6104b8e
AT		 313 for (j = 0; j < 8; j++)
314 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 315
c6104b8e
AT		 316 for (j = 0; j < 8; j++)
317 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 318
c6104b8e
AT		 319 for (j = 0; j < 5; j++)
320 RR(OVL_CONV_COEF(i, j));
ab5ca071 321
c6104b8e
AT		 322 if (dss_has_feature(FEAT_FIR_COEF_V)) {
323 for (j = 0; j < 8; j++)
324 RR(OVL_FIR_COEF_V(i, j));
325 }
9b372c2d 326
c6104b8e
AT		 327 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
328 RR(OVL_BA0_UV(i));
329 RR(OVL_BA1_UV(i));
330 RR(OVL_FIR2(i));
331 RR(OVL_ACCU2_0(i));
332 RR(OVL_ACCU2_1(i));
ab5ca071 333
c6104b8e
AT		 334 for (j = 0; j < 8; j++)
335 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 336
c6104b8e
AT		 337 for (j = 0; j < 8; j++)
338 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 339
c6104b8e
AT		 340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V2(i, j));
342 }
343 if (dss_has_feature(FEAT_ATTR2))
344 RR(OVL_ATTRIBUTES2(i));
ab5ca071 345 }
80c39712 346
0cf35df3
MR		 347 if (dss_has_feature(FEAT_CORE_CLK_DIV))
348 RR(DIVISOR);
349
80c39712
TV		 350 /* enable last, because LCD & DIGIT enable are here */
351 RR(CONTROL);
2a205f34
SS		 352 if (dss_has_feature(FEAT_MGR_LCD2))
353 RR(CONTROL2);
75c7d59d
VS		 354 /* clear spurious SYNC_LOST_DIGIT interrupts */
355 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
356
357 /*
358 * enable last so IRQs won't trigger before
359 * the context is fully restored
360 */
361 RR(IRQENABLE);
49ea86f3
TV		 362
363 DSSDBG("context restored\n");
80c39712
TV		 364}
365
366#undef SR
367#undef RR
368
4fbafaf3
TV		 369int dispc_runtime_get(void)
370{
371 int r;
372
373 DSSDBG("dispc_runtime_get\n");
374
375 r = pm_runtime_get_sync(&dispc.pdev->dev);
376 WARN_ON(r < 0);
377 return r < 0 ? r : 0;
378}
379
380void dispc_runtime_put(void)
381{
382 int r;
383
384 DSSDBG("dispc_runtime_put\n");
385
0eaf9f52 386 r = pm_runtime_put_sync(&dispc.pdev->dev);
4fbafaf3 387 WARN_ON(r < 0);
80c39712
TV		 388}
389
dac57a05
AT		 390static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
391{
392 if (channel == OMAP_DSS_CHANNEL_LCD ||
393 channel == OMAP_DSS_CHANNEL_LCD2)
394 return true;
395 else
396 return false;
397}
4fbafaf3 398
3dcec4d6
TV		 399u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
400{
401 switch (channel) {
402 case OMAP_DSS_CHANNEL_LCD:
403 return DISPC_IRQ_VSYNC;
404 case OMAP_DSS_CHANNEL_LCD2:
405 return DISPC_IRQ_VSYNC2;
406 case OMAP_DSS_CHANNEL_DIGIT:
407 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
408 default:
409 BUG();
410 }
411}
412
7d1365c9
TV		 413u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
414{
415 switch (channel) {
416 case OMAP_DSS_CHANNEL_LCD:
417 return DISPC_IRQ_FRAMEDONE;
418 case OMAP_DSS_CHANNEL_LCD2:
419 return DISPC_IRQ_FRAMEDONE2;
420 case OMAP_DSS_CHANNEL_DIGIT:
421 return 0;
422 default:
423 BUG();
424 }
425}
426
26d9dd0d 427bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 428{
429 int bit;
430
dac57a05 431 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 432 bit = 5; /* GOLCD */
433 else
434 bit = 6; /* GODIGIT */
435
2a205f34
SS		 436 if (channel == OMAP_DSS_CHANNEL_LCD2)
437 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
438 else
439 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 440}
441
26d9dd0d 442void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 443{
444 int bit;
2a205f34 445 bool enable_bit, go_bit;
80c39712 446
dac57a05 447 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 448 bit = 0; /* LCDENABLE */
449 else
450 bit = 1; /* DIGITALENABLE */
451
452 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 453 if (channel == OMAP_DSS_CHANNEL_LCD2)
454 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
455 else
456 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
457
458 if (!enable_bit)
e6d80f95 459 return;
80c39712 460
dac57a05 461 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 462 bit = 5; /* GOLCD */
463 else
464 bit = 6; /* GODIGIT */
465
2a205f34
SS		 466 if (channel == OMAP_DSS_CHANNEL_LCD2)
467 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
468 else
469 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
470
471 if (go_bit) {
80c39712 472 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 473 return;
80c39712
TV		 474 }
475
2a205f34
SS		 476 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
477 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 478
2a205f34
SS		 479 if (channel == OMAP_DSS_CHANNEL_LCD2)
480 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
481 else
482 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 483}
484
f0e5caab 485static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 486{
9b372c2d 487 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 488}
489
f0e5caab 490static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 491{
9b372c2d 492 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 493}
494
f0e5caab 495static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 496{
9b372c2d 497 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 498}
499
f0e5caab 500static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 501{
502 BUG_ON(plane == OMAP_DSS_GFX);
503
504 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
505}
506
f0e5caab
TV		 507static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
508 u32 value)
ab5ca071
AJ		 509{
510 BUG_ON(plane == OMAP_DSS_GFX);
511
512 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
513}
514
f0e5caab 515static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 516{
517 BUG_ON(plane == OMAP_DSS_GFX);
518
519 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
520}
521
debd9074
CM		 522static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
523 int fir_vinc, int five_taps,
524 enum omap_color_component color_comp)
80c39712 525{
debd9074 526 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 527 int i;
528
debd9074
CM		 529 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
530 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 531
532 for (i = 0; i < 8; i++) {
533 u32 h, hv;
534
debd9074
CM		 535 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
536 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
537 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
538 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
539 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
540 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
541 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
542 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 543
0d66cbb5 544 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 545 dispc_ovl_write_firh_reg(plane, i, h);
546 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 547 } else {
f0e5caab
TV		 548 dispc_ovl_write_firh2_reg(plane, i, h);
549 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 550 }
551
80c39712
TV		 552 }
553
66be8f6c
GI		 554 if (five_taps) {
555 for (i = 0; i < 8; i++) {
556 u32 v;
debd9074
CM		 557 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
558 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 559 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 560 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 561 else
f0e5caab 562 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 563 }
80c39712
TV		 564 }
565}
566
567static void _dispc_setup_color_conv_coef(void)
568{
ac01c29e 569 int i;
80c39712
TV		 570 const struct color_conv_coef {
571 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
572 int full_range;
573 } ctbl_bt601_5 = {
574 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
575 };
576
577 const struct color_conv_coef *ct;
578
579#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
580
581 ct = &ctbl_bt601_5;
582
ac01c29e
AT		 583 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
584 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
585 CVAL(ct->rcr, ct->ry));
586 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
587 CVAL(ct->gy, ct->rcb));
588 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
589 CVAL(ct->gcb, ct->gcr));
590 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
591 CVAL(ct->bcr, ct->by));
592 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
593 CVAL(0, ct->bcb));
594
595 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
596 11, 11);
597 }
80c39712
TV		 598
599#undef CVAL
80c39712
TV		 600}
601
602
f0e5caab 603static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 604{
9b372c2d 605 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 606}
607
f0e5caab 608static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 609{
9b372c2d 610 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 611}
612
f0e5caab 613static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 614{
615 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
616}
617
f0e5caab 618static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 619{
620 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
621}
622
f0e5caab 623static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 624{
80c39712 625 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 626
627 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 628}
629
f0e5caab 630static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 631{
80c39712 632 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 633
634 if (plane == OMAP_DSS_GFX)
635 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
636 else
637 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 638}
639
f0e5caab 640static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 641{
642 u32 val;
80c39712
TV		 643
644 BUG_ON(plane == OMAP_DSS_GFX);
645
646 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 647
648 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 649}
650
54128701
AT		 651static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
652{
653 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
654
655 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
656 return;
657
658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
659}
660
661static void dispc_ovl_enable_zorder_planes(void)
662{
663 int i;
664
665 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
666 return;
667
668 for (i = 0; i < dss_feat_get_num_ovls(); i++)
669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
670}
671
f0e5caab 672static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 673{
f6dc8150 674 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 675
f6dc8150 676 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 677 return;
678
9b372c2d 679 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 680}
681
f0e5caab 682static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 683{
b8c095b4 684 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 685 int shift;
f6dc8150 686 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 687
f6dc8150 688 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 689 return;
a0acb557 690
fe3cc9d6
TV		 691 shift = shifts[plane];
692 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 693}
694
f0e5caab 695static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 696{
9b372c2d 697 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 698}
699
f0e5caab 700static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 701{
9b372c2d 702 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 703}
704
f0e5caab 705static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 706 enum omap_color_mode color_mode)
707{
708 u32 m = 0;
f20e4220
AJ		 709 if (plane != OMAP_DSS_GFX) {
710 switch (color_mode) {
711 case OMAP_DSS_COLOR_NV12:
712 m = 0x0; break;
08f3267e 713 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 714 m = 0x1; break;
715 case OMAP_DSS_COLOR_RGBA16:
716 m = 0x2; break;
08f3267e 717 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 718 m = 0x4; break;
719 case OMAP_DSS_COLOR_ARGB16:
720 m = 0x5; break;
721 case OMAP_DSS_COLOR_RGB16:
722 m = 0x6; break;
723 case OMAP_DSS_COLOR_ARGB16_1555:
724 m = 0x7; break;
725 case OMAP_DSS_COLOR_RGB24U:
726 m = 0x8; break;
727 case OMAP_DSS_COLOR_RGB24P:
728 m = 0x9; break;
729 case OMAP_DSS_COLOR_YUV2:
730 m = 0xa; break;
731 case OMAP_DSS_COLOR_UYVY:
732 m = 0xb; break;
733 case OMAP_DSS_COLOR_ARGB32:
734 m = 0xc; break;
735 case OMAP_DSS_COLOR_RGBA32:
736 m = 0xd; break;
737 case OMAP_DSS_COLOR_RGBX32:
738 m = 0xe; break;
739 case OMAP_DSS_COLOR_XRGB16_1555:
740 m = 0xf; break;
741 default:
742 BUG(); break;
743 }
744 } else {
745 switch (color_mode) {
746 case OMAP_DSS_COLOR_CLUT1:
747 m = 0x0; break;
748 case OMAP_DSS_COLOR_CLUT2:
749 m = 0x1; break;
750 case OMAP_DSS_COLOR_CLUT4:
751 m = 0x2; break;
752 case OMAP_DSS_COLOR_CLUT8:
753 m = 0x3; break;
754 case OMAP_DSS_COLOR_RGB12U:
755 m = 0x4; break;
756 case OMAP_DSS_COLOR_ARGB16:
757 m = 0x5; break;
758 case OMAP_DSS_COLOR_RGB16:
759 m = 0x6; break;
760 case OMAP_DSS_COLOR_ARGB16_1555:
761 m = 0x7; break;
762 case OMAP_DSS_COLOR_RGB24U:
763 m = 0x8; break;
764 case OMAP_DSS_COLOR_RGB24P:
765 m = 0x9; break;
08f3267e 766 case OMAP_DSS_COLOR_RGBX16:
f20e4220 767 m = 0xa; break;
08f3267e 768 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 769 m = 0xb; break;
770 case OMAP_DSS_COLOR_ARGB32:
771 m = 0xc; break;
772 case OMAP_DSS_COLOR_RGBA32:
773 m = 0xd; break;
774 case OMAP_DSS_COLOR_RGBX32:
775 m = 0xe; break;
776 case OMAP_DSS_COLOR_XRGB16_1555:
777 m = 0xf; break;
778 default:
779 BUG(); break;
780 }
80c39712
TV		 781 }
782
9b372c2d 783 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 784}
785
f427984e 786void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 787{
788 int shift;
789 u32 val;
2a205f34 790 int chan = 0, chan2 = 0;
80c39712
TV		 791
792 switch (plane) {
793 case OMAP_DSS_GFX:
794 shift = 8;
795 break;
796 case OMAP_DSS_VIDEO1:
797 case OMAP_DSS_VIDEO2:
b8c095b4 798 case OMAP_DSS_VIDEO3:
80c39712
TV		 799 shift = 16;
800 break;
801 default:
802 BUG();
803 return;
804 }
805
9b372c2d 806 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 807 if (dss_has_feature(FEAT_MGR_LCD2)) {
808 switch (channel) {
809 case OMAP_DSS_CHANNEL_LCD:
810 chan = 0;
811 chan2 = 0;
812 break;
813 case OMAP_DSS_CHANNEL_DIGIT:
814 chan = 1;
815 chan2 = 0;
816 break;
817 case OMAP_DSS_CHANNEL_LCD2:
818 chan = 0;
819 chan2 = 1;
820 break;
821 default:
822 BUG();
823 }
824
825 val = FLD_MOD(val, chan, shift, shift);
826 val = FLD_MOD(val, chan2, 31, 30);
827 } else {
828 val = FLD_MOD(val, channel, shift, shift);
829 }
9b372c2d 830 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 831}
832
2cc5d1af
TV		 833static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
834{
835 int shift;
836 u32 val;
837 enum omap_channel channel;
838
839 switch (plane) {
840 case OMAP_DSS_GFX:
841 shift = 8;
842 break;
843 case OMAP_DSS_VIDEO1:
844 case OMAP_DSS_VIDEO2:
845 case OMAP_DSS_VIDEO3:
846 shift = 16;
847 break;
848 default:
849 BUG();
850 }
851
852 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
853
854 if (dss_has_feature(FEAT_MGR_LCD2)) {
855 if (FLD_GET(val, 31, 30) == 0)
856 channel = FLD_GET(val, shift, shift);
857 else
858 channel = OMAP_DSS_CHANNEL_LCD2;
859 } else {
860 channel = FLD_GET(val, shift, shift);
861 }
862
863 return channel;
864}
865
f0e5caab 866static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 867 enum omap_burst_size burst_size)
868{
b8c095b4 869 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 870 int shift;
80c39712 871
fe3cc9d6 872 shift = shifts[plane];
5ed8cf5b 873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 874}
875
5ed8cf5b
TV		 876static void dispc_configure_burst_sizes(void)
877{
878 int i;
879 const int burst_size = BURST_SIZE_X8;
880
881 /* Configure burst size always to maximum size */
882 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 883 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 884}
885
83fa2f2e 886static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 887{
888 unsigned unit = dss_feat_get_burst_size_unit();
889 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
890 return unit * 8;
891}
892
d3862610
M		 893void dispc_enable_gamma_table(bool enable)
894{
895 /*
896 * This is partially implemented to support only disabling of
897 * the gamma table.
898 */
899 if (enable) {
900 DSSWARN("Gamma table enabling for TV not yet supported");
901 return;
902 }
903
904 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
905}
906
c64dca40 907static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 908{
909 u16 reg;
910
911 if (channel == OMAP_DSS_CHANNEL_LCD)
912 reg = DISPC_CONFIG;
913 else if (channel == OMAP_DSS_CHANNEL_LCD2)
914 reg = DISPC_CONFIG2;
915 else
916 return;
917
918 REG_FLD_MOD(reg, enable, 15, 15);
919}
920
c64dca40 921static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 922 struct omap_dss_cpr_coefs *coefs)
923{
924 u32 coef_r, coef_g, coef_b;
925
dac57a05 926 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 927 return;
928
929 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
930 FLD_VAL(coefs->rb, 9, 0);
931 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
932 FLD_VAL(coefs->gb, 9, 0);
933 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
934 FLD_VAL(coefs->bb, 9, 0);
935
936 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
937 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
938 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
939}
940
f0e5caab 941static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 942{
943 u32 val;
944
945 BUG_ON(plane == OMAP_DSS_GFX);
946
9b372c2d 947 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 948 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 949 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 950}
951
c3d92529 952static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 953{
b8c095b4 954 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 955 int shift;
80c39712 956
fe3cc9d6
TV		 957 shift = shifts[plane];
958 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 959}
960
8f366162 961static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 962 u16 height)
80c39712
TV		 963{
964 u32 val;
80c39712 965
80c39712 966 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 967 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 968}
969
970static void dispc_read_plane_fifo_sizes(void)
971{
80c39712
TV		 972 u32 size;
973 int plane;
a0acb557 974 u8 start, end;
5ed8cf5b
TV		 975 u32 unit;
976
977 unit = dss_feat_get_buffer_size_unit();
80c39712 978
a0acb557 979 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 980
e13a138b 981 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 982 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
983 size *= unit;
80c39712
TV		 984 dispc.fifo_size[plane] = size;
985 }
80c39712
TV		 986}
987
83fa2f2e 988static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 989{
990 return dispc.fifo_size[plane];
991}
992
6f04e1bf 993void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 994{
a0acb557 995 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 996 u32 unit;
997
998 unit = dss_feat_get_buffer_size_unit();
999
1000 WARN_ON(low % unit != 0);
1001 WARN_ON(high % unit != 0);
1002
1003 low /= unit;
1004 high /= unit;
a0acb557 1005
9b372c2d
AT		 1006 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1007 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1008
3cb5d966 1009 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1010 plane,
9b372c2d 1011 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1012 lo_start, lo_end) * unit,
9b372c2d 1013 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1014 hi_start, hi_end) * unit,
1015 low * unit, high * unit);
80c39712 1016
9b372c2d 1017 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1018 FLD_VAL(high, hi_start, hi_end) |
1019 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1020}
1021
1022void dispc_enable_fifomerge(bool enable)
1023{
e6b0f884
TV		 1024 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1025 WARN_ON(enable);
1026 return;
1027 }
1028
80c39712
TV		 1029 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1030 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1031}
1032
83fa2f2e
TV		 1033void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1034 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
1035{
1036 /*
1037 * All sizes are in bytes. Both the buffer and burst are made of
1038 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1039 */
1040
1041 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1042 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1043 int i;
83fa2f2e
TV		 1044
1045 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1046 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1047
e0e405b9
TV		 1048 if (use_fifomerge) {
1049 total_fifo_size = 0;
1050 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1051 total_fifo_size += dispc_ovl_get_fifo_size(i);
1052 } else {
1053 total_fifo_size = ovl_fifo_size;
1054 }
1055
1056 /*
1057 * We use the same low threshold for both fifomerge and non-fifomerge
1058 * cases, but for fifomerge we calculate the high threshold using the
1059 * combined fifo size
1060 */
1061
1062 if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1063 *fifo_low = ovl_fifo_size - burst_size * 2;
1064 *fifo_high = total_fifo_size - burst_size;
1065 } else {
1066 *fifo_low = ovl_fifo_size - burst_size;
1067 *fifo_high = total_fifo_size - buf_unit;
1068 }
83fa2f2e
TV		 1069}
1070
f0e5caab 1071static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1072 int hinc, int vinc,
1073 enum omap_color_component color_comp)
80c39712
TV		 1074{
1075 u32 val;
80c39712 1076
0d66cbb5
AJ		 1077 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1078 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1079
0d66cbb5
AJ		 1080 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1081 &hinc_start, &hinc_end);
1082 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1083 &vinc_start, &vinc_end);
1084 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1085 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1086
0d66cbb5
AJ		 1087 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1088 } else {
1089 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1090 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1091 }
80c39712
TV		 1092}
1093
f0e5caab 1094static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1095{
1096 u32 val;
87a7484b 1097 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1098
87a7484b
AT		 1099 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1100 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1101
1102 val = FLD_VAL(vaccu, vert_start, vert_end) |
1103 FLD_VAL(haccu, hor_start, hor_end);
1104
9b372c2d 1105 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1106}
1107
f0e5caab 1108static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1109{
1110 u32 val;
87a7484b 1111 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1112
87a7484b
AT		 1113 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1114 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1115
1116 val = FLD_VAL(vaccu, vert_start, vert_end) |
1117 FLD_VAL(haccu, hor_start, hor_end);
1118
9b372c2d 1119 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1120}
1121
f0e5caab
TV		 1122static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1123 int vaccu)
ab5ca071
AJ		 1124{
1125 u32 val;
1126
1127 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1128 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1129}
1130
f0e5caab
TV		 1131static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1132 int vaccu)
ab5ca071
AJ		 1133{
1134 u32 val;
1135
1136 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1137 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1138}
80c39712 1139
f0e5caab 1140static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1141 u16 orig_width, u16 orig_height,
1142 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1143 bool five_taps, u8 rotation,
1144 enum omap_color_component color_comp)
80c39712 1145{
0d66cbb5 1146 int fir_hinc, fir_vinc;
80c39712 1147
ed14a3ce
AJ		 1148 fir_hinc = 1024 * orig_width / out_width;
1149 fir_vinc = 1024 * orig_height / out_height;
80c39712 1150
debd9074
CM		 1151 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1152 color_comp);
f0e5caab 1153 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1154}
1155
05dd0f53
CM		 1156static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1157 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1158 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1159{
1160 int h_accu2_0, h_accu2_1;
1161 int v_accu2_0, v_accu2_1;
1162 int chroma_hinc, chroma_vinc;
1163 int idx;
1164
1165 struct accu {
1166 s8 h0_m, h0_n;
1167 s8 h1_m, h1_n;
1168 s8 v0_m, v0_n;
1169 s8 v1_m, v1_n;
1170 };
1171
1172 const struct accu *accu_table;
1173 const struct accu *accu_val;
1174
1175 static const struct accu accu_nv12[4] = {
1176 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1177 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1178 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1179 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1180 };
1181
1182 static const struct accu accu_nv12_ilace[4] = {
1183 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1184 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1185 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1186 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1187 };
1188
1189 static const struct accu accu_yuv[4] = {
1190 { 0, 1, 0, 1, 0, 1, 0, 1 },
1191 { 0, 1, 0, 1, 0, 1, 0, 1 },
1192 { -1, 1, 0, 1, 0, 1, 0, 1 },
1193 { 0, 1, 0, 1, -1, 1, 0, 1 },
1194 };
1195
1196 switch (rotation) {
1197 case OMAP_DSS_ROT_0:
1198 idx = 0;
1199 break;
1200 case OMAP_DSS_ROT_90:
1201 idx = 1;
1202 break;
1203 case OMAP_DSS_ROT_180:
1204 idx = 2;
1205 break;
1206 case OMAP_DSS_ROT_270:
1207 idx = 3;
1208 break;
1209 default:
1210 BUG();
1211 }
1212
1213 switch (color_mode) {
1214 case OMAP_DSS_COLOR_NV12:
1215 if (ilace)
1216 accu_table = accu_nv12_ilace;
1217 else
1218 accu_table = accu_nv12;
1219 break;
1220 case OMAP_DSS_COLOR_YUV2:
1221 case OMAP_DSS_COLOR_UYVY:
1222 accu_table = accu_yuv;
1223 break;
1224 default:
1225 BUG();
1226 }
1227
1228 accu_val = &accu_table[idx];
1229
1230 chroma_hinc = 1024 * orig_width / out_width;
1231 chroma_vinc = 1024 * orig_height / out_height;
1232
1233 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1234 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1235 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1236 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1237
1238 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1239 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1240}
1241
f0e5caab 1242static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1243 u16 orig_width, u16 orig_height,
1244 u16 out_width, u16 out_height,
1245 bool ilace, bool five_taps,
1246 bool fieldmode, enum omap_color_mode color_mode,
1247 u8 rotation)
1248{
1249 int accu0 = 0;
1250 int accu1 = 0;
1251 u32 l;
80c39712 1252
f0e5caab 1253 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1254 out_width, out_height, five_taps,
1255 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1256 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1257
87a7484b
AT		 1258 /* RESIZEENABLE and VERTICALTAPS */
1259 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1260 l |= (orig_width != out_width) ? (1 << 5) : 0;
1261 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1262 l |= five_taps ? (1 << 21) : 0;
80c39712 1263
87a7484b
AT		 1264 /* VRESIZECONF and HRESIZECONF */
1265 if (dss_has_feature(FEAT_RESIZECONF)) {
1266 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1267 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1268 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1269 }
80c39712 1270
87a7484b
AT		 1271 /* LINEBUFFERSPLIT */
1272 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1273 l &= ~(0x1 << 22);
1274 l |= five_taps ? (1 << 22) : 0;
1275 }
80c39712 1276
9b372c2d 1277 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1278
1279 /*
1280 * field 0 = even field = bottom field
1281 * field 1 = odd field = top field
1282 */
1283 if (ilace && !fieldmode) {
1284 accu1 = 0;
0d66cbb5 1285 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1286 if (accu0 >= 1024/2) {
1287 accu1 = 1024/2;
1288 accu0 -= accu1;
1289 }
1290 }
1291
f0e5caab
TV		 1292 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1293 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1294}
1295
f0e5caab 1296static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1297 u16 orig_width, u16 orig_height,
1298 u16 out_width, u16 out_height,
1299 bool ilace, bool five_taps,
1300 bool fieldmode, enum omap_color_mode color_mode,
1301 u8 rotation)
1302{
1303 int scale_x = out_width != orig_width;
1304 int scale_y = out_height != orig_height;
1305
05dd0f53
CM		 1306 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1307 out_height, ilace, color_mode, rotation);
1308
0d66cbb5
AJ		 1309 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1310 return;
1311 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1312 color_mode != OMAP_DSS_COLOR_UYVY &&
1313 color_mode != OMAP_DSS_COLOR_NV12)) {
1314 /* reset chroma resampling for RGB formats */
1315 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1316 return;
1317 }
1318 switch (color_mode) {
1319 case OMAP_DSS_COLOR_NV12:
1320 /* UV is subsampled by 2 vertically*/
1321 orig_height >>= 1;
1322 /* UV is subsampled by 2 horz.*/
1323 orig_width >>= 1;
1324 break;
1325 case OMAP_DSS_COLOR_YUV2:
1326 case OMAP_DSS_COLOR_UYVY:
1327 /*For YUV422 with 90/270 rotation,
1328 *we don't upsample chroma
1329 */
1330 if (rotation == OMAP_DSS_ROT_0 ||
1331 rotation == OMAP_DSS_ROT_180)
1332 /* UV is subsampled by 2 hrz*/
1333 orig_width >>= 1;
1334 /* must use FIR for YUV422 if rotated */
1335 if (rotation != OMAP_DSS_ROT_0)
1336 scale_x = scale_y = true;
1337 break;
1338 default:
1339 BUG();
1340 }
1341
1342 if (out_width != orig_width)
1343 scale_x = true;
1344 if (out_height != orig_height)
1345 scale_y = true;
1346
f0e5caab 1347 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1348 out_width, out_height, five_taps,
1349 rotation, DISPC_COLOR_COMPONENT_UV);
1350
1351 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1352 (scale_x || scale_y) ? 1 : 0, 8, 8);
1353 /* set H scaling */
1354 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1355 /* set V scaling */
1356 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1357}
1358
f0e5caab 1359static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1360 u16 orig_width, u16 orig_height,
1361 u16 out_width, u16 out_height,
1362 bool ilace, bool five_taps,
1363 bool fieldmode, enum omap_color_mode color_mode,
1364 u8 rotation)
1365{
1366 BUG_ON(plane == OMAP_DSS_GFX);
1367
f0e5caab 1368 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1369 orig_width, orig_height,
1370 out_width, out_height,
1371 ilace, five_taps,
1372 fieldmode, color_mode,
1373 rotation);
1374
f0e5caab 1375 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1376 orig_width, orig_height,
1377 out_width, out_height,
1378 ilace, five_taps,
1379 fieldmode, color_mode,
1380 rotation);
1381}
1382
f0e5caab 1383static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1384 bool mirroring, enum omap_color_mode color_mode)
1385{
87a7484b
AT		 1386 bool row_repeat = false;
1387 int vidrot = 0;
1388
80c39712
TV		 1389 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1390 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1391
1392 if (mirroring) {
1393 switch (rotation) {
1394 case OMAP_DSS_ROT_0:
1395 vidrot = 2;
1396 break;
1397 case OMAP_DSS_ROT_90:
1398 vidrot = 1;
1399 break;
1400 case OMAP_DSS_ROT_180:
1401 vidrot = 0;
1402 break;
1403 case OMAP_DSS_ROT_270:
1404 vidrot = 3;
1405 break;
1406 }
1407 } else {
1408 switch (rotation) {
1409 case OMAP_DSS_ROT_0:
1410 vidrot = 0;
1411 break;
1412 case OMAP_DSS_ROT_90:
1413 vidrot = 1;
1414 break;
1415 case OMAP_DSS_ROT_180:
1416 vidrot = 2;
1417 break;
1418 case OMAP_DSS_ROT_270:
1419 vidrot = 3;
1420 break;
1421 }
1422 }
1423
80c39712 1424 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1425 row_repeat = true;
80c39712 1426 else
87a7484b 1427 row_repeat = false;
80c39712 1428 }
87a7484b 1429
9b372c2d 1430 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1431 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1432 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1433 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1434}
1435
1436static int color_mode_to_bpp(enum omap_color_mode color_mode)
1437{
1438 switch (color_mode) {
1439 case OMAP_DSS_COLOR_CLUT1:
1440 return 1;
1441 case OMAP_DSS_COLOR_CLUT2:
1442 return 2;
1443 case OMAP_DSS_COLOR_CLUT4:
1444 return 4;
1445 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1446 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1447 return 8;
1448 case OMAP_DSS_COLOR_RGB12U:
1449 case OMAP_DSS_COLOR_RGB16:
1450 case OMAP_DSS_COLOR_ARGB16:
1451 case OMAP_DSS_COLOR_YUV2:
1452 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1453 case OMAP_DSS_COLOR_RGBA16:
1454 case OMAP_DSS_COLOR_RGBX16:
1455 case OMAP_DSS_COLOR_ARGB16_1555:
1456 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1457 return 16;
1458 case OMAP_DSS_COLOR_RGB24P:
1459 return 24;
1460 case OMAP_DSS_COLOR_RGB24U:
1461 case OMAP_DSS_COLOR_ARGB32:
1462 case OMAP_DSS_COLOR_RGBA32:
1463 case OMAP_DSS_COLOR_RGBX32:
1464 return 32;
1465 default:
1466 BUG();
1467 }
1468}
1469
1470static s32 pixinc(int pixels, u8 ps)
1471{
1472 if (pixels == 1)
1473 return 1;
1474 else if (pixels > 1)
1475 return 1 + (pixels - 1) * ps;
1476 else if (pixels < 0)
1477 return 1 - (-pixels + 1) * ps;
1478 else
1479 BUG();
1480}
1481
1482static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1483 u16 screen_width,
1484 u16 width, u16 height,
1485 enum omap_color_mode color_mode, bool fieldmode,
1486 unsigned int field_offset,
1487 unsigned *offset0, unsigned *offset1,
aed74b55 1488 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1489{
1490 u8 ps;
1491
1492 /* FIXME CLUT formats */
1493 switch (color_mode) {
1494 case OMAP_DSS_COLOR_CLUT1:
1495 case OMAP_DSS_COLOR_CLUT2:
1496 case OMAP_DSS_COLOR_CLUT4:
1497 case OMAP_DSS_COLOR_CLUT8:
1498 BUG();
1499 return;
1500 case OMAP_DSS_COLOR_YUV2:
1501 case OMAP_DSS_COLOR_UYVY:
1502 ps = 4;
1503 break;
1504 default:
1505 ps = color_mode_to_bpp(color_mode) / 8;
1506 break;
1507 }
1508
1509 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1510 width, height);
1511
1512 /*
1513 * field 0 = even field = bottom field
1514 * field 1 = odd field = top field
1515 */
1516 switch (rotation + mirror * 4) {
1517 case OMAP_DSS_ROT_0:
1518 case OMAP_DSS_ROT_180:
1519 /*
1520 * If the pixel format is YUV or UYVY divide the width
1521 * of the image by 2 for 0 and 180 degree rotation.
1522 */
1523 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1524 color_mode == OMAP_DSS_COLOR_UYVY)
1525 width = width >> 1;
1526 case OMAP_DSS_ROT_90:
1527 case OMAP_DSS_ROT_270:
1528 *offset1 = 0;
1529 if (field_offset)
1530 *offset0 = field_offset * screen_width * ps;
1531 else
1532 *offset0 = 0;
1533
aed74b55
CM		 1534 *row_inc = pixinc(1 +
1535 (y_predecim * screen_width - x_predecim * width) +
1536 (fieldmode ? screen_width : 0), ps);
1537 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1538 break;
1539
1540 case OMAP_DSS_ROT_0 + 4:
1541 case OMAP_DSS_ROT_180 + 4:
1542 /* If the pixel format is YUV or UYVY divide the width
1543 * of the image by 2 for 0 degree and 180 degree
1544 */
1545 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1546 color_mode == OMAP_DSS_COLOR_UYVY)
1547 width = width >> 1;
1548 case OMAP_DSS_ROT_90 + 4:
1549 case OMAP_DSS_ROT_270 + 4:
1550 *offset1 = 0;
1551 if (field_offset)
1552 *offset0 = field_offset * screen_width * ps;
1553 else
1554 *offset0 = 0;
aed74b55
CM		 1555 *row_inc = pixinc(1 -
1556 (y_predecim * screen_width + x_predecim * width) -
1557 (fieldmode ? screen_width : 0), ps);
1558 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1559 break;
1560
1561 default:
1562 BUG();
1563 }
1564}
1565
1566static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1567 u16 screen_width,
1568 u16 width, u16 height,
1569 enum omap_color_mode color_mode, bool fieldmode,
1570 unsigned int field_offset,
1571 unsigned *offset0, unsigned *offset1,
aed74b55 1572 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1573{
1574 u8 ps;
1575 u16 fbw, fbh;
1576
1577 /* FIXME CLUT formats */
1578 switch (color_mode) {
1579 case OMAP_DSS_COLOR_CLUT1:
1580 case OMAP_DSS_COLOR_CLUT2:
1581 case OMAP_DSS_COLOR_CLUT4:
1582 case OMAP_DSS_COLOR_CLUT8:
1583 BUG();
1584 return;
1585 default:
1586 ps = color_mode_to_bpp(color_mode) / 8;
1587 break;
1588 }
1589
1590 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1591 width, height);
1592
1593 /* width & height are overlay sizes, convert to fb sizes */
1594
1595 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1596 fbw = width;
1597 fbh = height;
1598 } else {
1599 fbw = height;
1600 fbh = width;
1601 }
1602
1603 /*
1604 * field 0 = even field = bottom field
1605 * field 1 = odd field = top field
1606 */
1607 switch (rotation + mirror * 4) {
1608 case OMAP_DSS_ROT_0:
1609 *offset1 = 0;
1610 if (field_offset)
1611 *offset0 = *offset1 + field_offset * screen_width * ps;
1612 else
1613 *offset0 = *offset1;
aed74b55
CM		 1614 *row_inc = pixinc(1 +
1615 (y_predecim * screen_width - fbw * x_predecim) +
1616 (fieldmode ? screen_width : 0), ps);
1617 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1618 color_mode == OMAP_DSS_COLOR_UYVY)
1619 *pix_inc = pixinc(x_predecim, 2 * ps);
1620 else
1621 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1622 break;
1623 case OMAP_DSS_ROT_90:
1624 *offset1 = screen_width * (fbh - 1) * ps;
1625 if (field_offset)
1626 *offset0 = *offset1 + field_offset * ps;
1627 else
1628 *offset0 = *offset1;
aed74b55
CM		 1629 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1630 y_predecim + (fieldmode ? 1 : 0), ps);
1631 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1632 break;
1633 case OMAP_DSS_ROT_180:
1634 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1635 if (field_offset)
1636 *offset0 = *offset1 - field_offset * screen_width * ps;
1637 else
1638 *offset0 = *offset1;
1639 *row_inc = pixinc(-1 -
aed74b55
CM		 1640 (y_predecim * screen_width - fbw * x_predecim) -
1641 (fieldmode ? screen_width : 0), ps);
1642 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1643 color_mode == OMAP_DSS_COLOR_UYVY)
1644 *pix_inc = pixinc(-x_predecim, 2 * ps);
1645 else
1646 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1647 break;
1648 case OMAP_DSS_ROT_270:
1649 *offset1 = (fbw - 1) * ps;
1650 if (field_offset)
1651 *offset0 = *offset1 - field_offset * ps;
1652 else
1653 *offset0 = *offset1;
aed74b55
CM		 1654 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1655 y_predecim - (fieldmode ? 1 : 0), ps);
1656 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1657 break;
1658
1659 /* mirroring */
1660 case OMAP_DSS_ROT_0 + 4:
1661 *offset1 = (fbw - 1) * ps;
1662 if (field_offset)
1663 *offset0 = *offset1 + field_offset * screen_width * ps;
1664 else
1665 *offset0 = *offset1;
aed74b55 1666 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1667 (fieldmode ? screen_width : 0),
1668 ps);
aed74b55
CM		 1669 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1670 color_mode == OMAP_DSS_COLOR_UYVY)
1671 *pix_inc = pixinc(-x_predecim, 2 * ps);
1672 else
1673 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1674 break;
1675
1676 case OMAP_DSS_ROT_90 + 4:
1677 *offset1 = 0;
1678 if (field_offset)
1679 *offset0 = *offset1 + field_offset * ps;
1680 else
1681 *offset0 = *offset1;
aed74b55
CM		 1682 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1683 y_predecim + (fieldmode ? 1 : 0),
80c39712 1684 ps);
aed74b55 1685 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1686 break;
1687
1688 case OMAP_DSS_ROT_180 + 4:
1689 *offset1 = screen_width * (fbh - 1) * ps;
1690 if (field_offset)
1691 *offset0 = *offset1 - field_offset * screen_width * ps;
1692 else
1693 *offset0 = *offset1;
aed74b55 1694 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1695 (fieldmode ? screen_width : 0),
1696 ps);
aed74b55
CM		 1697 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1698 color_mode == OMAP_DSS_COLOR_UYVY)
1699 *pix_inc = pixinc(x_predecim, 2 * ps);
1700 else
1701 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1702 break;
1703
1704 case OMAP_DSS_ROT_270 + 4:
1705 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1706 if (field_offset)
1707 *offset0 = *offset1 - field_offset * ps;
1708 else
1709 *offset0 = *offset1;
aed74b55
CM		 1710 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1711 y_predecim - (fieldmode ? 1 : 0),
80c39712 1712 ps);
aed74b55 1713 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1714 break;
1715
1716 default:
1717 BUG();
1718 }
1719}
1720
7faa9233
CM		 1721/*
1722 * This function is used to avoid synclosts in OMAP3, because of some
1723 * undocumented horizontal position and timing related limitations.
1724 */
81ab95b7
AT		 1725static int check_horiz_timing_omap3(enum omap_channel channel,
1726 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1727 u16 width, u16 height, u16 out_width, u16 out_height)
1728{
1729 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1730 unsigned long nonactive, lclk, pclk;
1731 static const u8 limits[3] = { 8, 10, 20 };
1732 u64 val, blank;
1733 int i;
1734
81ab95b7 1735 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 1736 pclk = dispc_mgr_pclk_rate(channel);
1737 if (dispc_mgr_is_lcd(channel))
1738 lclk = dispc_mgr_lclk_rate(channel);
1739 else
1740 lclk = dispc_fclk_rate();
1741
1742 i = 0;
1743 if (out_height < height)
1744 i++;
1745 if (out_width < width)
1746 i++;
81ab95b7 1747 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1748 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1749 if (blank <= limits[i])
1750 return -EINVAL;
1751
1752 /*
1753 * Pixel data should be prepared before visible display point starts.
1754 * So, atleast DS-2 lines must have already been fetched by DISPC
1755 * during nonactive - pos_x period.
1756 */
1757 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1758 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1759 val, max(0, DS - 2) * width);
1760 if (val < max(0, DS - 2) * width)
1761 return -EINVAL;
1762
1763 /*
1764 * All lines need to be refilled during the nonactive period of which
1765 * only one line can be loaded during the active period. So, atleast
1766 * DS - 1 lines should be loaded during nonactive period.
1767 */
1768 val = div_u64((u64)nonactive * lclk, pclk);
1769 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1770 val, max(0, DS - 1) * width);
1771 if (val < max(0, DS - 1) * width)
1772 return -EINVAL;
1773
1774 return 0;
1775}
1776
8b53d991 1777static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1778 const struct omap_video_timings *mgr_timings, u16 width,
1779 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1780 enum omap_color_mode color_mode)
80c39712 1781{
8b53d991 1782 u32 core_clk = 0;
26d9dd0d 1783 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1784
7282f1b7
CM		 1785 if (height <= out_height && width <= out_width)
1786 return (unsigned long) pclk;
1787
80c39712 1788 if (height > out_height) {
81ab95b7 1789 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1790
1791 tmp = pclk * height * out_width;
1792 do_div(tmp, 2 * out_height * ppl);
8b53d991 1793 core_clk = tmp;
80c39712 1794
2d9c5597
VS		 1795 if (height > 2 * out_height) {
1796 if (ppl == out_width)
1797 return 0;
1798
80c39712
TV		 1799 tmp = pclk * (height - 2 * out_height) * out_width;
1800 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1801 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1802 }
1803 }
1804
1805 if (width > out_width) {
1806 tmp = pclk * width;
1807 do_div(tmp, out_width);
8b53d991 1808 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1809
1810 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1811 core_clk <<= 1;
80c39712
TV		 1812 }
1813
8b53d991 1814 return core_clk;
80c39712
TV		 1815}
1816
8b53d991 1817static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
ff1b2cde 1818 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1819{
1820 unsigned int hf, vf;
79ee89cd 1821 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1822
1823 /*
1824 * FIXME how to determine the 'A' factor
1825 * for the no downscaling case ?
1826 */
1827
1828 if (width > 3 * out_width)
1829 hf = 4;
1830 else if (width > 2 * out_width)
1831 hf = 3;
1832 else if (width > out_width)
1833 hf = 2;
1834 else
1835 hf = 1;
1836
1837 if (height > out_height)
1838 vf = 2;
1839 else
1840 vf = 1;
1841
7282f1b7
CM		 1842 if (cpu_is_omap24xx()) {
1843 if (vf > 1 && hf > 1)
79ee89cd 1844 return pclk * 4;
7282f1b7 1845 else
79ee89cd 1846 return pclk * 2;
7282f1b7 1847 } else if (cpu_is_omap34xx()) {
79ee89cd 1848 return pclk * vf * hf;
7282f1b7 1849 } else {
79ee89cd
AT		 1850 if (hf > 1)
1851 return DIV_ROUND_UP(pclk, out_width) * width;
1852 else
1853 return pclk;
7282f1b7 1854 }
80c39712
TV		 1855}
1856
79ad75f2 1857static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 1858 enum omap_channel channel,
1859 const struct omap_video_timings *mgr_timings,
1860 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 1861 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 1862 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 1863{
1864 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1865 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1866 const int maxsinglelinewidth =
1867 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
aed74b55 1868 const int max_decim_limit = 16;
8b53d991 1869 unsigned long core_clk = 0;
aed74b55
CM		 1870 int decim_x, decim_y, error, min_factor;
1871 u16 in_width, in_height, in_width_max = 0;
79ad75f2 1872
f95cb5eb
TV		 1873 if (width == out_width && height == out_height)
1874 return 0;
1875
1876 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1877 return -EINVAL;
79ad75f2 1878
aed74b55
CM		 1879 *x_predecim = max_decim_limit;
1880 *y_predecim = max_decim_limit;
1881
1882 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
1883 color_mode == OMAP_DSS_COLOR_CLUT2 ||
1884 color_mode == OMAP_DSS_COLOR_CLUT4 ||
1885 color_mode == OMAP_DSS_COLOR_CLUT8) {
1886 *x_predecim = 1;
1887 *y_predecim = 1;
1888 *five_taps = false;
1889 return 0;
1890 }
1891
1892 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
1893 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
1894
1895 min_factor = min(decim_x, decim_y);
1896
1897 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 1898 return -EINVAL;
1899
aed74b55 1900 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 1901 return -EINVAL;
1902
7282f1b7 1903 if (cpu_is_omap24xx()) {
7282f1b7 1904 *five_taps = false;
aed74b55
CM		 1905
1906 do {
1907 in_height = DIV_ROUND_UP(height, decim_y);
1908 in_width = DIV_ROUND_UP(width, decim_x);
8b53d991 1909 core_clk = calc_core_clk(channel, in_width, in_height,
aed74b55 1910 out_width, out_height);
8b53d991
CM		 1911 error = (in_width > maxsinglelinewidth || !core_clk ||
1912 core_clk > dispc_core_clk_rate());
aed74b55
CM		 1913 if (error) {
1914 if (decim_x == decim_y) {
1915 decim_x = min_factor;
1916 decim_y++;
1917 } else {
1918 swap(decim_x, decim_y);
1919 if (decim_x < decim_y)
1920 decim_x++;
1921 }
1922 }
1923 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
1924 error);
1925
1926 if (in_width > maxsinglelinewidth) {
1927 DSSERR("Cannot scale max input width exceeded");
1928 return -EINVAL;
1929 }
7282f1b7 1930 } else if (cpu_is_omap34xx()) {
aed74b55
CM		 1931
1932 do {
1933 in_height = DIV_ROUND_UP(height, decim_y);
1934 in_width = DIV_ROUND_UP(width, decim_x);
81ab95b7
AT		 1935 core_clk = calc_core_clk_five_taps(channel, mgr_timings,
1936 in_width, in_height, out_width, out_height,
1937 color_mode);
aed74b55 1938
81ab95b7
AT		 1939 error = check_horiz_timing_omap3(channel, mgr_timings,
1940 pos_x, in_width, in_height, out_width,
1941 out_height);
7faa9233 1942
aed74b55
CM		 1943 if (in_width > maxsinglelinewidth)
1944 if (in_height > out_height &&
1945 in_height < out_height * 2)
1946 *five_taps = false;
1947 if (!*five_taps)
8b53d991
CM		 1948 core_clk = calc_core_clk(channel, in_width,
1949 in_height, out_width, out_height);
7faa9233 1950 error = (error || in_width > maxsinglelinewidth * 2 ||
aed74b55 1951 (in_width > maxsinglelinewidth && *five_taps) ||
8b53d991 1952 !core_clk || core_clk > dispc_core_clk_rate());
aed74b55
CM		 1953 if (error) {
1954 if (decim_x == decim_y) {
1955 decim_x = min_factor;
1956 decim_y++;
1957 } else {
1958 swap(decim_x, decim_y);
1959 if (decim_x < decim_y)
1960 decim_x++;
1961 }
1962 }
1963 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
1964 && error);
1965
81ab95b7
AT		 1966 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
1967 height, out_width, out_height)){
7faa9233
CM		 1968 DSSERR("horizontal timing too tight\n");
1969 return -EINVAL;
1970 }
1971
aed74b55 1972 if (in_width > (maxsinglelinewidth * 2)) {
7282f1b7
CM		 1973 DSSERR("Cannot setup scaling");
1974 DSSERR("width exceeds maximum width possible");
1975 return -EINVAL;
1976 }
aed74b55
CM		 1977
1978 if (in_width > maxsinglelinewidth && *five_taps) {
1979 DSSERR("cannot setup scaling with five taps");
1980 return -EINVAL;
7282f1b7 1981 }
7282f1b7 1982 } else {
aed74b55
CM		 1983 int decim_x_min = decim_x;
1984 in_height = DIV_ROUND_UP(height, decim_y);
8b53d991 1985 in_width_max = dispc_core_clk_rate() /
aed74b55
CM		 1986 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
1987 out_width);
1988 decim_x = DIV_ROUND_UP(width, in_width_max);
1989
1990 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
1991 if (decim_x > *x_predecim)
1992 return -EINVAL;
1993
1994 do {
1995 in_width = DIV_ROUND_UP(width, decim_x);
1996 } while (decim_x <= *x_predecim &&
1997 in_width > maxsinglelinewidth && decim_x++);
1998
1999 if (in_width > maxsinglelinewidth) {
7282f1b7
CM		 2000 DSSERR("Cannot scale width exceeds max line width");
2001 return -EINVAL;
2002 }
aed74b55 2003
8b53d991
CM		 2004 core_clk = calc_core_clk(channel, in_width, in_height,
2005 out_width, out_height);
79ad75f2
AT		 2006 }
2007
8b53d991
CM		 2008 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2009 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2010
8b53d991 2011 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2012 DSSERR("failed to set up scaling, "
8b53d991
CM		 2013 "required core clk rate = %lu Hz, "
2014 "current core clk rate = %lu Hz\n",
2015 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2016 return -EINVAL;
2017 }
2018
aed74b55
CM		 2019 *x_predecim = decim_x;
2020 *y_predecim = decim_y;
79ad75f2
AT		 2021 return 0;
2022}
2023
a4273b7c 2024int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
81ab95b7
AT		 2025 bool ilace, bool replication,
2026 const struct omap_video_timings *mgr_timings)
80c39712 2027{
79ad75f2 2028 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 2029 bool five_taps = true;
80c39712 2030 bool fieldmode = 0;
79ad75f2 2031 int r, cconv = 0;
80c39712
TV		 2032 unsigned offset0, offset1;
2033 s32 row_inc;
2034 s32 pix_inc;
a4273b7c 2035 u16 frame_height = oi->height;
80c39712 2036 unsigned int field_offset = 0;
aed74b55
CM		 2037 u16 in_height = oi->height;
2038 u16 in_width = oi->width;
2039 u16 out_width, out_height;
2cc5d1af 2040 enum omap_channel channel;
aed74b55 2041 int x_predecim = 1, y_predecim = 1;
2cc5d1af
TV		 2042
2043 channel = dispc_ovl_get_channel_out(plane);
80c39712 2044
a4273b7c 2045 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 2046 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2047 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 2048 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2049 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 2050 oi->mirror, ilace, channel, replication);
e6d80f95 2051
a4273b7c 2052 if (oi->paddr == 0)
80c39712
TV		 2053 return -EINVAL;
2054
aed74b55
CM		 2055 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2056 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 2057
aed74b55 2058 if (ilace && oi->height == out_height)
80c39712
TV		 2059 fieldmode = 1;
2060
2061 if (ilace) {
2062 if (fieldmode)
aed74b55 2063 in_height /= 2;
a4273b7c 2064 oi->pos_y /= 2;
aed74b55 2065 out_height /= 2;
80c39712
TV		 2066
2067 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2068 "out_height %d\n",
aed74b55 2069 in_height, oi->pos_y, out_height);
80c39712
TV		 2070 }
2071
a4273b7c 2072 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2073 return -EINVAL;
2074
81ab95b7
AT		 2075 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2076 in_height, out_width, out_height, oi->color_mode,
2077 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 2078 if (r)
2079 return r;
80c39712 2080
aed74b55
CM		 2081 in_width = DIV_ROUND_UP(in_width, x_predecim);
2082 in_height = DIV_ROUND_UP(in_height, y_predecim);
2083
79ad75f2
AT		 2084 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2085 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2086 oi->color_mode == OMAP_DSS_COLOR_NV12)
2087 cconv = 1;
80c39712
TV		 2088
2089 if (ilace && !fieldmode) {
2090 /*
2091 * when downscaling the bottom field may have to start several
2092 * source lines below the top field. Unfortunately ACCUI
2093 * registers will only hold the fractional part of the offset
2094 * so the integer part must be added to the base address of the
2095 * bottom field.
2096 */
aed74b55 2097 if (!in_height || in_height == out_height)
80c39712
TV		 2098 field_offset = 0;
2099 else
aed74b55 2100 field_offset = in_height / out_height / 2;
80c39712
TV		 2101 }
2102
2103 /* Fields are independent but interleaved in memory. */
2104 if (fieldmode)
2105 field_offset = 1;
2106
a4273b7c
AT		 2107 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
2108 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2109 oi->screen_width, in_width, frame_height,
a4273b7c 2110 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2111 &offset0, &offset1, &row_inc, &pix_inc,
2112 x_predecim, y_predecim);
80c39712 2113 else
a4273b7c 2114 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2115 oi->screen_width, in_width, frame_height,
a4273b7c 2116 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2117 &offset0, &offset1, &row_inc, &pix_inc,
2118 x_predecim, y_predecim);
80c39712
TV		 2119
2120 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2121 offset0, offset1, row_inc, pix_inc);
2122
a4273b7c 2123 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2124
a4273b7c
AT		 2125 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2126 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2127
a4273b7c
AT		 2128 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2129 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2130 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2131 }
2132
2133
f0e5caab
TV		 2134 dispc_ovl_set_row_inc(plane, row_inc);
2135 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2136
aed74b55
CM		 2137 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2138 in_height, out_width, out_height);
80c39712 2139
a4273b7c 2140 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2141
aed74b55 2142 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2143
79ad75f2 2144 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2145 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2146 out_height, ilace, five_taps, fieldmode,
a4273b7c 2147 oi->color_mode, oi->rotation);
aed74b55 2148 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2149 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2150 }
2151
a4273b7c
AT		 2152 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2153 oi->color_mode);
80c39712 2154
54128701 2155 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2156 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2157 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2158
c3d92529 2159 dispc_ovl_enable_replication(plane, replication);
c3d92529 2160
80c39712
TV		 2161 return 0;
2162}
2163
f0e5caab 2164int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2165{
e6d80f95
TV		 2166 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2167
9b372c2d 2168 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2169
2170 return 0;
80c39712
TV		 2171}
2172
2173static void dispc_disable_isr(void *data, u32 mask)
2174{
2175 struct completion *compl = data;
2176 complete(compl);
2177}
2178
2a205f34 2179static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2180{
b6a44e77 2181 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 2182 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2183 /* flush posted write */
2184 dispc_read_reg(DISPC_CONTROL2);
2185 } else {
2a205f34 2186 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2187 dispc_read_reg(DISPC_CONTROL);
2188 }
80c39712
TV		 2189}
2190
26d9dd0d 2191static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2192{
2193 struct completion frame_done_completion;
2194 bool is_on;
2195 int r;
2a205f34 2196 u32 irq;
80c39712 2197
80c39712
TV		 2198 /* When we disable LCD output, we need to wait until frame is done.
2199 * Otherwise the DSS is still working, and turning off the clocks
2200 * prevents DSS from going to OFF mode */
2a205f34
SS		 2201 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2202 REG_GET(DISPC_CONTROL2, 0, 0) :
2203 REG_GET(DISPC_CONTROL, 0, 0);
2204
2205 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2206 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2207
2208 if (!enable && is_on) {
2209 init_completion(&frame_done_completion);
2210
2211 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2212 &frame_done_completion, irq);
80c39712
TV		 2213
2214 if (r)
2215 DSSERR("failed to register FRAMEDONE isr\n");
2216 }
2217
2a205f34 2218 _enable_lcd_out(channel, enable);
80c39712
TV		 2219
2220 if (!enable && is_on) {
2221 if (!wait_for_completion_timeout(&frame_done_completion,
2222 msecs_to_jiffies(100)))
2223 DSSERR("timeout waiting for FRAME DONE\n");
2224
2225 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2226 &frame_done_completion, irq);
80c39712
TV		 2227
2228 if (r)
2229 DSSERR("failed to unregister FRAMEDONE isr\n");
2230 }
80c39712
TV		 2231}
2232
2233static void _enable_digit_out(bool enable)
2234{
2235 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2236 /* flush posted write */
2237 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2238}
2239
26d9dd0d 2240static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2241{
2242 struct completion frame_done_completion;
e82b090b
TV		 2243 enum dss_hdmi_venc_clk_source_select src;
2244 int r, i;
2245 u32 irq_mask;
2246 int num_irqs;
80c39712 2247
e6d80f95 2248 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2249 return;
80c39712 2250
e82b090b
TV		 2251 src = dss_get_hdmi_venc_clk_source();
2252
80c39712
TV		 2253 if (enable) {
2254 unsigned long flags;
2255 /* When we enable digit output, we'll get an extra digit
2256 * sync lost interrupt, that we need to ignore */
2257 spin_lock_irqsave(&dispc.irq_lock, flags);
2258 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2259 _omap_dispc_set_irqs();
2260 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2261 }
2262
2263 /* When we disable digit output, we need to wait until fields are done.
2264 * Otherwise the DSS is still working, and turning off the clocks
2265 * prevents DSS from going to OFF mode. And when enabling, we need to
2266 * wait for the extra sync losts */
2267 init_completion(&frame_done_completion);
2268
e82b090b
TV		 2269 if (src == DSS_HDMI_M_PCLK && enable == false) {
2270 irq_mask = DISPC_IRQ_FRAMEDONETV;
2271 num_irqs = 1;
2272 } else {
2273 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2274 /* XXX I understand from TRM that we should only wait for the
2275 * current field to complete. But it seems we have to wait for
2276 * both fields */
2277 num_irqs = 2;
2278 }
2279
80c39712 2280 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2281 irq_mask);
80c39712 2282 if (r)
e82b090b 2283 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2284
2285 _enable_digit_out(enable);
2286
e82b090b
TV		 2287 for (i = 0; i < num_irqs; ++i) {
2288 if (!wait_for_completion_timeout(&frame_done_completion,
2289 msecs_to_jiffies(100)))
2290 DSSERR("timeout waiting for digit out to %s\n",
2291 enable ? "start" : "stop");
2292 }
80c39712 2293
e82b090b
TV		 2294 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2295 irq_mask);
80c39712 2296 if (r)
e82b090b 2297 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2298
2299 if (enable) {
2300 unsigned long flags;
2301 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2302 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2303 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2304 _omap_dispc_set_irqs();
2305 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2306 }
80c39712
TV		 2307}
2308
26d9dd0d 2309bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2310{
2311 if (channel == OMAP_DSS_CHANNEL_LCD)
2312 return !!REG_GET(DISPC_CONTROL, 0, 0);
2313 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2314 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2315 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2316 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2317 else
2318 BUG();
2319}
2320
26d9dd0d 2321void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2322{
dac57a05 2323 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2324 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2325 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2326 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2327 else
2328 BUG();
2329}
2330
80c39712
TV		 2331void dispc_lcd_enable_signal_polarity(bool act_high)
2332{
6ced40bf
AT		 2333 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2334 return;
2335
80c39712 2336 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2337}
2338
2339void dispc_lcd_enable_signal(bool enable)
2340{
6ced40bf
AT		 2341 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2342 return;
2343
80c39712 2344 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2345}
2346
2347void dispc_pck_free_enable(bool enable)
2348{
6ced40bf
AT		 2349 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2350 return;
2351
80c39712 2352 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2353}
2354
26d9dd0d 2355void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2356{
2a205f34
SS		 2357 if (channel == OMAP_DSS_CHANNEL_LCD2)
2358 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2359 else
2360 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2361}
2362
2363
26d9dd0d 2364void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2365 enum omap_lcd_display_type type)
80c39712
TV		 2366{
2367 int mode;
2368
2369 switch (type) {
2370 case OMAP_DSS_LCD_DISPLAY_STN:
2371 mode = 0;
2372 break;
2373
2374 case OMAP_DSS_LCD_DISPLAY_TFT:
2375 mode = 1;
2376 break;
2377
2378 default:
2379 BUG();
2380 return;
2381 }
2382
2a205f34
SS		 2383 if (channel == OMAP_DSS_CHANNEL_LCD2)
2384 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2385 else
2386 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2387}
2388
2389void dispc_set_loadmode(enum omap_dss_load_mode mode)
2390{
80c39712 2391 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2392}
2393
2394
c64dca40 2395static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2396{
8613b000 2397 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2398}
2399
c64dca40 2400static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2401 enum omap_dss_trans_key_type type,
2402 u32 trans_key)
2403{
80c39712
TV		 2404 if (ch == OMAP_DSS_CHANNEL_LCD)
2405 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2406 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2407 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2408 else /* OMAP_DSS_CHANNEL_LCD2 */
2409 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2410
8613b000 2411 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2412}
2413
c64dca40 2414static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2415{
80c39712
TV		 2416 if (ch == OMAP_DSS_CHANNEL_LCD)
2417 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2418 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2419 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2420 else /* OMAP_DSS_CHANNEL_LCD2 */
2421 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2422}
11354dd5 2423
c64dca40
TV		 2424static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2425 bool enable)
80c39712 2426{
11354dd5 2427 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2428 return;
2429
80c39712
TV		 2430 if (ch == OMAP_DSS_CHANNEL_LCD)
2431 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2432 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2433 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2434}
11354dd5 2435
c64dca40
TV		 2436void dispc_mgr_setup(enum omap_channel channel,
2437 struct omap_overlay_manager_info *info)
2438{
2439 dispc_mgr_set_default_color(channel, info->default_color);
2440 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2441 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2442 dispc_mgr_enable_alpha_fixed_zorder(channel,
2443 info->partial_alpha_enabled);
2444 if (dss_has_feature(FEAT_CPR)) {
2445 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2446 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2447 }
2448}
80c39712 2449
26d9dd0d 2450void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2451{
2452 int code;
2453
2454 switch (data_lines) {
2455 case 12:
2456 code = 0;
2457 break;
2458 case 16:
2459 code = 1;
2460 break;
2461 case 18:
2462 code = 2;
2463 break;
2464 case 24:
2465 code = 3;
2466 break;
2467 default:
2468 BUG();
2469 return;
2470 }
2471
2a205f34
SS		 2472 if (channel == OMAP_DSS_CHANNEL_LCD2)
2473 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2474 else
2475 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2476}
2477
569969d6 2478void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2479{
2480 u32 l;
569969d6 2481 int gpout0, gpout1;
80c39712
TV		 2482
2483 switch (mode) {
569969d6
AT		 2484 case DSS_IO_PAD_MODE_RESET:
2485 gpout0 = 0;
2486 gpout1 = 0;
80c39712 2487 break;
569969d6
AT		 2488 case DSS_IO_PAD_MODE_RFBI:
2489 gpout0 = 1;
80c39712
TV		 2490 gpout1 = 0;
2491 break;
569969d6
AT		 2492 case DSS_IO_PAD_MODE_BYPASS:
2493 gpout0 = 1;
80c39712
TV		 2494 gpout1 = 1;
2495 break;
80c39712
TV		 2496 default:
2497 BUG();
2498 return;
2499 }
2500
569969d6
AT		 2501 l = dispc_read_reg(DISPC_CONTROL);
2502 l = FLD_MOD(l, gpout0, 15, 15);
2503 l = FLD_MOD(l, gpout1, 16, 16);
2504 dispc_write_reg(DISPC_CONTROL, l);
2505}
2506
2507void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2508{
2509 if (channel == OMAP_DSS_CHANNEL_LCD2)
2510 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2511 else
2512 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2513}
2514
8f366162
AT		 2515static bool _dispc_mgr_size_ok(u16 width, u16 height)
2516{
2517 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2518 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2519}
2520
80c39712
TV		 2521static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2522 int vsw, int vfp, int vbp)
2523{
2524 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2525 if (hsw < 1 || hsw > 64 ||
2526 hfp < 1 || hfp > 256 ||
2527 hbp < 1 || hbp > 256 ||
2528 vsw < 1 || vsw > 64 ||
2529 vfp < 0 || vfp > 255 ||
2530 vbp < 0 || vbp > 255)
2531 return false;
2532 } else {
2533 if (hsw < 1 || hsw > 256 ||
2534 hfp < 1 || hfp > 4096 ||
2535 hbp < 1 || hbp > 4096 ||
2536 vsw < 1 || vsw > 256 ||
2537 vfp < 0 || vfp > 4095 ||
2538 vbp < 0 || vbp > 4095)
2539 return false;
2540 }
2541
2542 return true;
2543}
2544
8f366162 2545bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2546 const struct omap_video_timings *timings)
80c39712 2547{
8f366162
AT		 2548 bool timings_ok;
2549
2550 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2551
2552 if (dispc_mgr_is_lcd(channel))
2553 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2554 timings->hfp, timings->hbp,
2555 timings->vsw, timings->vfp,
2556 timings->vbp);
2557
2558 return timings_ok;
80c39712
TV		 2559}
2560
26d9dd0d 2561static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2562 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2563{
2564 u32 timing_h, timing_v;
2565
2566 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2567 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2568 FLD_VAL(hbp-1, 27, 20);
2569
2570 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2571 FLD_VAL(vbp, 27, 20);
2572 } else {
2573 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2574 FLD_VAL(hbp-1, 31, 20);
2575
2576 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2577 FLD_VAL(vbp, 31, 20);
2578 }
2579
64ba4f74
SS		 2580 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2581 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2582}
2583
2584/* change name to mode? */
c51d921a 2585void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2586 struct omap_video_timings *timings)
80c39712
TV		 2587{
2588 unsigned xtot, ytot;
2589 unsigned long ht, vt;
2590
c51d921a
AT		 2591 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2592 timings->y_res);
80c39712 2593
8f366162
AT		 2594 if (!dispc_mgr_timings_ok(channel, timings))
2595 BUG();
80c39712 2596
8f366162 2597 if (dispc_mgr_is_lcd(channel)) {
c51d921a
AT		 2598 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2599 timings->hbp, timings->vsw, timings->vfp,
2600 timings->vbp);
80c39712 2601
c51d921a
AT		 2602 xtot = timings->x_res + timings->hfp + timings->hsw +
2603 timings->hbp;
2604 ytot = timings->y_res + timings->vfp + timings->vsw +
2605 timings->vbp;
80c39712 2606
c51d921a
AT		 2607 ht = (timings->pixel_clock * 1000) / xtot;
2608 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2609
2610 DSSDBG("pck %u\n", timings->pixel_clock);
2611 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
80c39712
TV		 2612 timings->hsw, timings->hfp, timings->hbp,
2613 timings->vsw, timings->vfp, timings->vbp);
2614
c51d921a 2615 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
c51d921a 2616 }
8f366162
AT		 2617
2618 dispc_mgr_set_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2619}
2620
26d9dd0d 2621static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2622 u16 pck_div)
80c39712
TV		 2623{
2624 BUG_ON(lck_div < 1);
9eaaf207 2625 BUG_ON(pck_div < 1);
80c39712 2626
ce7fa5eb 2627 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2628 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2629}
2630
26d9dd0d 2631static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2632 int *pck_div)
80c39712
TV		 2633{
2634 u32 l;
ce7fa5eb 2635 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2636 *lck_div = FLD_GET(l, 23, 16);
2637 *pck_div = FLD_GET(l, 7, 0);
2638}
2639
2640unsigned long dispc_fclk_rate(void)
2641{
a72b64b9 2642 struct platform_device *dsidev;
80c39712
TV		 2643 unsigned long r = 0;
2644
66534e8e 2645 switch (dss_get_dispc_clk_source()) {
89a35e51 2646 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2647 r = clk_get_rate(dispc.dss_clk);
66534e8e 2648 break;
89a35e51 2649 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2650 dsidev = dsi_get_dsidev_from_id(0);
2651 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2652 break;
5a8b572d
AT		 2653 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2654 dsidev = dsi_get_dsidev_from_id(1);
2655 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2656 break;
66534e8e
TA		 2657 default:
2658 BUG();
2659 }
2660
80c39712
TV		 2661 return r;
2662}
2663
26d9dd0d 2664unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2665{
a72b64b9 2666 struct platform_device *dsidev;
80c39712
TV		 2667 int lcd;
2668 unsigned long r;
2669 u32 l;
2670
ce7fa5eb 2671 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2672
2673 lcd = FLD_GET(l, 23, 16);
2674
ea75159e 2675 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2676 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2677 r = clk_get_rate(dispc.dss_clk);
ea75159e 2678 break;
89a35e51 2679 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2680 dsidev = dsi_get_dsidev_from_id(0);
2681 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2682 break;
5a8b572d
AT		 2683 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2684 dsidev = dsi_get_dsidev_from_id(1);
2685 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2686 break;
ea75159e
TA		 2687 default:
2688 BUG();
2689 }
80c39712
TV		 2690
2691 return r / lcd;
2692}
2693
26d9dd0d 2694unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2695{
80c39712 2696 unsigned long r;
80c39712 2697
c3dc6a7a
AT		 2698 if (dispc_mgr_is_lcd(channel)) {
2699 int pcd;
2700 u32 l;
80c39712 2701
c3dc6a7a 2702 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2703
c3dc6a7a 2704 pcd = FLD_GET(l, 7, 0);
80c39712 2705
c3dc6a7a
AT		 2706 r = dispc_mgr_lclk_rate(channel);
2707
2708 return r / pcd;
2709 } else {
3fa03ba8 2710 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2711
3fa03ba8
AT		 2712 source = dss_get_hdmi_venc_clk_source();
2713
2714 switch (source) {
2715 case DSS_VENC_TV_CLK:
c3dc6a7a 2716 return venc_get_pixel_clock();
3fa03ba8 2717 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2718 return hdmi_get_pixel_clock();
2719 default:
2720 BUG();
2721 }
2722 }
80c39712
TV		 2723}
2724
8b53d991
CM		 2725unsigned long dispc_core_clk_rate(void)
2726{
2727 int lcd;
2728 unsigned long fclk = dispc_fclk_rate();
2729
2730 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2731 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2732 else
2733 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2734
2735 return fclk / lcd;
2736}
2737
80c39712
TV		 2738void dispc_dump_clocks(struct seq_file *s)
2739{
2740 int lcd, pcd;
0cf35df3 2741 u32 l;
89a35e51
AT		 2742 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2743 enum omap_dss_clk_source lcd_clk_src;
80c39712 2744
4fbafaf3
TV		 2745 if (dispc_runtime_get())
2746 return;
80c39712 2747
80c39712
TV		 2748 seq_printf(s, "- DISPC -\n");
2749
067a57e4
AT		 2750 seq_printf(s, "dispc fclk source = %s (%s)\n",
2751 dss_get_generic_clk_source_name(dispc_clk_src),
2752 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2753
2754 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2755
0cf35df3
MR		 2756 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2757 seq_printf(s, "- DISPC-CORE-CLK -\n");
2758 l = dispc_read_reg(DISPC_DIVISOR);
2759 lcd = FLD_GET(l, 23, 16);
2760
2761 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2762 (dispc_fclk_rate()/lcd), lcd);
2763 }
2a205f34
SS		 2764 seq_printf(s, "- LCD1 -\n");
2765
ea75159e
TA		 2766 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2767
2768 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2769 dss_get_generic_clk_source_name(lcd_clk_src),
2770 dss_feat_get_clk_source_name(lcd_clk_src));
2771
26d9dd0d 2772 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2773
ff1b2cde 2774 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2775 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2776 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2777 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2778 if (dss_has_feature(FEAT_MGR_LCD2)) {
2779 seq_printf(s, "- LCD2 -\n");
2780
ea75159e
TA		 2781 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2782
2783 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2784 dss_get_generic_clk_source_name(lcd_clk_src),
2785 dss_feat_get_clk_source_name(lcd_clk_src));
2786
26d9dd0d 2787 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2788
2a205f34 2789 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2790 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2791 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2792 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2793 }
4fbafaf3
TV		 2794
2795 dispc_runtime_put();
80c39712
TV		 2796}
2797
dfc0fd8d
TV		 2798#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2799void dispc_dump_irqs(struct seq_file *s)
2800{
2801 unsigned long flags;
2802 struct dispc_irq_stats stats;
2803
2804 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2805
2806 stats = dispc.irq_stats;
2807 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2808 dispc.irq_stats.last_reset = jiffies;
2809
2810 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2811
2812 seq_printf(s, "period %u ms\n",
2813 jiffies_to_msecs(jiffies - stats.last_reset));
2814
2815 seq_printf(s, "irqs %d\n", stats.irq_count);
2816#define PIS(x) \
2817 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2818
2819 PIS(FRAMEDONE);
2820 PIS(VSYNC);
2821 PIS(EVSYNC_EVEN);
2822 PIS(EVSYNC_ODD);
2823 PIS(ACBIAS_COUNT_STAT);
2824 PIS(PROG_LINE_NUM);
2825 PIS(GFX_FIFO_UNDERFLOW);
2826 PIS(GFX_END_WIN);
2827 PIS(PAL_GAMMA_MASK);
2828 PIS(OCP_ERR);
2829 PIS(VID1_FIFO_UNDERFLOW);
2830 PIS(VID1_END_WIN);
2831 PIS(VID2_FIFO_UNDERFLOW);
2832 PIS(VID2_END_WIN);
b8c095b4
AT		 2833 if (dss_feat_get_num_ovls() > 3) {
2834 PIS(VID3_FIFO_UNDERFLOW);
2835 PIS(VID3_END_WIN);
2836 }
dfc0fd8d
TV		 2837 PIS(SYNC_LOST);
2838 PIS(SYNC_LOST_DIGIT);
2839 PIS(WAKEUP);
2a205f34
SS		 2840 if (dss_has_feature(FEAT_MGR_LCD2)) {
2841 PIS(FRAMEDONE2);
2842 PIS(VSYNC2);
2843 PIS(ACBIAS_COUNT_STAT2);
2844 PIS(SYNC_LOST2);
2845 }
dfc0fd8d
TV		 2846#undef PIS
2847}
dfc0fd8d
TV		 2848#endif
2849
e40402cf 2850static void dispc_dump_regs(struct seq_file *s)
80c39712 2851{
4dd2da15
AT		 2852 int i, j;
2853 const char *mgr_names[] = {
2854 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2855 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2856 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2857 };
2858 const char *ovl_names[] = {
2859 [OMAP_DSS_GFX] = "GFX",
2860 [OMAP_DSS_VIDEO1] = "VID1",
2861 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2862 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2863 };
2864 const char **p_names;
2865
9b372c2d 2866#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2867
4fbafaf3
TV		 2868 if (dispc_runtime_get())
2869 return;
80c39712 2870
5010be80 2871 /* DISPC common registers */
80c39712
TV		 2872 DUMPREG(DISPC_REVISION);
2873 DUMPREG(DISPC_SYSCONFIG);
2874 DUMPREG(DISPC_SYSSTATUS);
2875 DUMPREG(DISPC_IRQSTATUS);
2876 DUMPREG(DISPC_IRQENABLE);
2877 DUMPREG(DISPC_CONTROL);
2878 DUMPREG(DISPC_CONFIG);
2879 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2880 DUMPREG(DISPC_LINE_STATUS);
2881 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2882 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2883 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2884 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2885 if (dss_has_feature(FEAT_MGR_LCD2)) {
2886 DUMPREG(DISPC_CONTROL2);
2887 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2888 }
2889
2890#undef DUMPREG
2891
2892#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2893#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2894 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2895 dispc_read_reg(DISPC_REG(i, r)))
2896
4dd2da15 2897 p_names = mgr_names;
5010be80 2898
4dd2da15
AT		 2899 /* DISPC channel specific registers */
2900 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2901 DUMPREG(i, DISPC_DEFAULT_COLOR);
2902 DUMPREG(i, DISPC_TRANS_COLOR);
2903 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2904
4dd2da15
AT		 2905 if (i == OMAP_DSS_CHANNEL_DIGIT)
2906 continue;
5010be80 2907
4dd2da15
AT		 2908 DUMPREG(i, DISPC_DEFAULT_COLOR);
2909 DUMPREG(i, DISPC_TRANS_COLOR);
2910 DUMPREG(i, DISPC_TIMING_H);
2911 DUMPREG(i, DISPC_TIMING_V);
2912 DUMPREG(i, DISPC_POL_FREQ);
2913 DUMPREG(i, DISPC_DIVISORo);
2914 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2915
4dd2da15
AT		 2916 DUMPREG(i, DISPC_DATA_CYCLE1);
2917 DUMPREG(i, DISPC_DATA_CYCLE2);
2918 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2919
332e9d70 2920 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2921 DUMPREG(i, DISPC_CPR_COEF_R);
2922 DUMPREG(i, DISPC_CPR_COEF_G);
2923 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2924 }
2a205f34 2925 }
80c39712 2926
4dd2da15
AT		 2927 p_names = ovl_names;
2928
2929 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2930 DUMPREG(i, DISPC_OVL_BA0);
2931 DUMPREG(i, DISPC_OVL_BA1);
2932 DUMPREG(i, DISPC_OVL_POSITION);
2933 DUMPREG(i, DISPC_OVL_SIZE);
2934 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2935 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2936 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2937 DUMPREG(i, DISPC_OVL_ROW_INC);
2938 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2939 if (dss_has_feature(FEAT_PRELOAD))
2940 DUMPREG(i, DISPC_OVL_PRELOAD);
2941
2942 if (i == OMAP_DSS_GFX) {
2943 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2944 DUMPREG(i, DISPC_OVL_TABLE_BA);
2945 continue;
2946 }
2947
2948 DUMPREG(i, DISPC_OVL_FIR);
2949 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2950 DUMPREG(i, DISPC_OVL_ACCU0);
2951 DUMPREG(i, DISPC_OVL_ACCU1);
2952 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2953 DUMPREG(i, DISPC_OVL_BA0_UV);
2954 DUMPREG(i, DISPC_OVL_BA1_UV);
2955 DUMPREG(i, DISPC_OVL_FIR2);
2956 DUMPREG(i, DISPC_OVL_ACCU2_0);
2957 DUMPREG(i, DISPC_OVL_ACCU2_1);
2958 }
2959 if (dss_has_feature(FEAT_ATTR2))
2960 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2961 if (dss_has_feature(FEAT_PRELOAD))
2962 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2963 }
5010be80
AT		 2964
2965#undef DISPC_REG
2966#undef DUMPREG
2967
2968#define DISPC_REG(plane, name, i) name(plane, i)
2969#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2970 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2971 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2972 dispc_read_reg(DISPC_REG(plane, name, i)))
2973
4dd2da15 2974 /* Video pipeline coefficient registers */
332e9d70 2975
4dd2da15
AT		 2976 /* start from OMAP_DSS_VIDEO1 */
2977 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2978 for (j = 0; j < 8; j++)
2979 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2980
4dd2da15
AT		 2981 for (j = 0; j < 8; j++)
2982 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2983
4dd2da15
AT		 2984 for (j = 0; j < 5; j++)
2985 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2986
4dd2da15
AT		 2987 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2988 for (j = 0; j < 8; j++)
2989 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2990 }
2991
2992 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2993 for (j = 0; j < 8; j++)
2994 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2995
2996 for (j = 0; j < 8; j++)
2997 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2998
2999 for (j = 0; j < 8; j++)
3000 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3001 }
332e9d70 3002 }
80c39712 3003
4fbafaf3 3004 dispc_runtime_put();
5010be80
AT		 3005
3006#undef DISPC_REG
80c39712
TV		 3007#undef DUMPREG
3008}
3009
26d9dd0d
TV		 3010static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
3011 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
3012 u8 acb)
80c39712
TV		 3013{
3014 u32 l = 0;
3015
3016 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
3017 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
3018
3019 l |= FLD_VAL(onoff, 17, 17);
3020 l |= FLD_VAL(rf, 16, 16);
3021 l |= FLD_VAL(ieo, 15, 15);
3022 l |= FLD_VAL(ipc, 14, 14);
3023 l |= FLD_VAL(ihs, 13, 13);
3024 l |= FLD_VAL(ivs, 12, 12);
3025 l |= FLD_VAL(acbi, 11, 8);
3026 l |= FLD_VAL(acb, 7, 0);
3027
ff1b2cde 3028 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3029}
3030
26d9dd0d 3031void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 3032 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 3033{
26d9dd0d 3034 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 3035 (config & OMAP_DSS_LCD_RF) != 0,
3036 (config & OMAP_DSS_LCD_IEO) != 0,
3037 (config & OMAP_DSS_LCD_IPC) != 0,
3038 (config & OMAP_DSS_LCD_IHS) != 0,
3039 (config & OMAP_DSS_LCD_IVS) != 0,
3040 acbi, acb);
3041}
3042
3043/* with fck as input clock rate, find dispc dividers that produce req_pck */
3044void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3045 struct dispc_clock_info *cinfo)
3046{
9eaaf207 3047 u16 pcd_min, pcd_max;
80c39712
TV		 3048 unsigned long best_pck;
3049 u16 best_ld, cur_ld;
3050 u16 best_pd, cur_pd;
3051
9eaaf207
TV		 3052 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3053 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3054
3055 if (!is_tft)
3056 pcd_min = 3;
3057
80c39712
TV		 3058 best_pck = 0;
3059 best_ld = 0;
3060 best_pd = 0;
3061
3062 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3063 unsigned long lck = fck / cur_ld;
3064
9eaaf207 3065 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3066 unsigned long pck = lck / cur_pd;
3067 long old_delta = abs(best_pck - req_pck);
3068 long new_delta = abs(pck - req_pck);
3069
3070 if (best_pck == 0 || new_delta < old_delta) {
3071 best_pck = pck;
3072 best_ld = cur_ld;
3073 best_pd = cur_pd;
3074
3075 if (pck == req_pck)
3076 goto found;
3077 }
3078
3079 if (pck < req_pck)
3080 break;
3081 }
3082
3083 if (lck / pcd_min < req_pck)
3084 break;
3085 }
3086
3087found:
3088 cinfo->lck_div = best_ld;
3089 cinfo->pck_div = best_pd;
3090 cinfo->lck = fck / cinfo->lck_div;
3091 cinfo->pck = cinfo->lck / cinfo->pck_div;
3092}
3093
3094/* calculate clock rates using dividers in cinfo */
3095int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3096 struct dispc_clock_info *cinfo)
3097{
3098 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3099 return -EINVAL;
9eaaf207 3100 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3101 return -EINVAL;
3102
3103 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3104 cinfo->pck = cinfo->lck / cinfo->pck_div;
3105
3106 return 0;
3107}
3108
26d9dd0d 3109int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3110 struct dispc_clock_info *cinfo)
80c39712
TV		 3111{
3112 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3113 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3114
26d9dd0d 3115 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3116
3117 return 0;
3118}
3119
26d9dd0d 3120int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3121 struct dispc_clock_info *cinfo)
80c39712
TV		 3122{
3123 unsigned long fck;
3124
3125 fck = dispc_fclk_rate();
3126
ce7fa5eb
MR		 3127 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3128 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3129
3130 cinfo->lck = fck / cinfo->lck_div;
3131 cinfo->pck = cinfo->lck / cinfo->pck_div;
3132
3133 return 0;
3134}
3135
3136/* dispc.irq_lock has to be locked by the caller */
3137static void _omap_dispc_set_irqs(void)
3138{
3139 u32 mask;
3140 u32 old_mask;
3141 int i;
3142 struct omap_dispc_isr_data *isr_data;
3143
3144 mask = dispc.irq_error_mask;
3145
3146 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3147 isr_data = &dispc.registered_isr[i];
3148
3149 if (isr_data->isr == NULL)
3150 continue;
3151
3152 mask |= isr_data->mask;
3153 }
3154
80c39712
TV		 3155 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3156 /* clear the irqstatus for newly enabled irqs */
3157 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3158
3159 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3160}
3161
3162int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3163{
3164 int i;
3165 int ret;
3166 unsigned long flags;
3167 struct omap_dispc_isr_data *isr_data;
3168
3169 if (isr == NULL)
3170 return -EINVAL;
3171
3172 spin_lock_irqsave(&dispc.irq_lock, flags);
3173
3174 /* check for duplicate entry */
3175 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3176 isr_data = &dispc.registered_isr[i];
3177 if (isr_data->isr == isr && isr_data->arg == arg &&
3178 isr_data->mask == mask) {
3179 ret = -EINVAL;
3180 goto err;
3181 }
3182 }
3183
3184 isr_data = NULL;
3185 ret = -EBUSY;
3186
3187 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3188 isr_data = &dispc.registered_isr[i];
3189
3190 if (isr_data->isr != NULL)
3191 continue;
3192
3193 isr_data->isr = isr;
3194 isr_data->arg = arg;
3195 isr_data->mask = mask;
3196 ret = 0;
3197
3198 break;
3199 }
3200
b9cb0984
TV		 3201 if (ret)
3202 goto err;
3203
80c39712
TV		 3204 _omap_dispc_set_irqs();
3205
3206 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3207
3208 return 0;
3209err:
3210 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3211
3212 return ret;
3213}
3214EXPORT_SYMBOL(omap_dispc_register_isr);
3215
3216int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3217{
3218 int i;
3219 unsigned long flags;
3220 int ret = -EINVAL;
3221 struct omap_dispc_isr_data *isr_data;
3222
3223 spin_lock_irqsave(&dispc.irq_lock, flags);
3224
3225 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3226 isr_data = &dispc.registered_isr[i];
3227 if (isr_data->isr != isr || isr_data->arg != arg ||
3228 isr_data->mask != mask)
3229 continue;
3230
3231 /* found the correct isr */
3232
3233 isr_data->isr = NULL;
3234 isr_data->arg = NULL;
3235 isr_data->mask = 0;
3236
3237 ret = 0;
3238 break;
3239 }
3240
3241 if (ret == 0)
3242 _omap_dispc_set_irqs();
3243
3244 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3245
3246 return ret;
3247}
3248EXPORT_SYMBOL(omap_dispc_unregister_isr);
3249
3250#ifdef DEBUG
3251static void print_irq_status(u32 status)
3252{
3253 if ((status & dispc.irq_error_mask) == 0)
3254 return;
3255
3256 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3257
3258#define PIS(x) \
3259 if (status & DISPC_IRQ_##x) \
3260 printk(#x " ");
3261 PIS(GFX_FIFO_UNDERFLOW);
3262 PIS(OCP_ERR);
3263 PIS(VID1_FIFO_UNDERFLOW);
3264 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3265 if (dss_feat_get_num_ovls() > 3)
3266 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3267 PIS(SYNC_LOST);
3268 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3269 if (dss_has_feature(FEAT_MGR_LCD2))
3270 PIS(SYNC_LOST2);
80c39712
TV		 3271#undef PIS
3272
3273 printk("\n");
3274}
3275#endif
3276
3277/* Called from dss.c. Note that we don't touch clocks here,
3278 * but we presume they are on because we got an IRQ. However,
3279 * an irq handler may turn the clocks off, so we may not have
3280 * clock later in the function. */
affe360d 3281static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3282{
3283 int i;
affe360d 3284 u32 irqstatus, irqenable;
80c39712
TV		 3285 u32 handledirqs = 0;
3286 u32 unhandled_errors;
3287 struct omap_dispc_isr_data *isr_data;
3288 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3289
3290 spin_lock(&dispc.irq_lock);
3291
3292 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3293 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3294
3295 /* IRQ is not for us */
3296 if (!(irqstatus & irqenable)) {
3297 spin_unlock(&dispc.irq_lock);
3298 return IRQ_NONE;
3299 }
80c39712 3300
dfc0fd8d
TV		 3301#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3302 spin_lock(&dispc.irq_stats_lock);
3303 dispc.irq_stats.irq_count++;
3304 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3305 spin_unlock(&dispc.irq_stats_lock);
3306#endif
3307
80c39712
TV		 3308#ifdef DEBUG
3309 if (dss_debug)
3310 print_irq_status(irqstatus);
3311#endif
3312 /* Ack the interrupt. Do it here before clocks are possibly turned
3313 * off */
3314 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3315 /* flush posted write */
3316 dispc_read_reg(DISPC_IRQSTATUS);
3317
3318 /* make a copy and unlock, so that isrs can unregister
3319 * themselves */
3320 memcpy(registered_isr, dispc.registered_isr,
3321 sizeof(registered_isr));
3322
3323 spin_unlock(&dispc.irq_lock);
3324
3325 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3326 isr_data = &registered_isr[i];
3327
3328 if (!isr_data->isr)
3329 continue;
3330
3331 if (isr_data->mask & irqstatus) {
3332 isr_data->isr(isr_data->arg, irqstatus);
3333 handledirqs |= isr_data->mask;
3334 }
3335 }
3336
3337 spin_lock(&dispc.irq_lock);
3338
3339 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3340
3341 if (unhandled_errors) {
3342 dispc.error_irqs |= unhandled_errors;
3343
3344 dispc.irq_error_mask &= ~unhandled_errors;
3345 _omap_dispc_set_irqs();
3346
3347 schedule_work(&dispc.error_work);
3348 }
3349
3350 spin_unlock(&dispc.irq_lock);
affe360d 3351
3352 return IRQ_HANDLED;
80c39712
TV		 3353}
3354
3355static void dispc_error_worker(struct work_struct *work)
3356{
3357 int i;
3358 u32 errors;
3359 unsigned long flags;
fe3cc9d6
TV		 3360 static const unsigned fifo_underflow_bits[] = {
3361 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3362 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3363 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3364 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3365 };
3366
3367 static const unsigned sync_lost_bits[] = {
3368 DISPC_IRQ_SYNC_LOST,
3369 DISPC_IRQ_SYNC_LOST_DIGIT,
3370 DISPC_IRQ_SYNC_LOST2,
3371 };
80c39712
TV		 3372
3373 spin_lock_irqsave(&dispc.irq_lock, flags);
3374 errors = dispc.error_irqs;
3375 dispc.error_irqs = 0;
3376 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3377
13eae1f9
DZ		 3378 dispc_runtime_get();
3379
fe3cc9d6
TV		 3380 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3381 struct omap_overlay *ovl;
3382 unsigned bit;
80c39712 3383
fe3cc9d6
TV		 3384 ovl = omap_dss_get_overlay(i);
3385 bit = fifo_underflow_bits[i];
80c39712 3386
fe3cc9d6
TV		 3387 if (bit & errors) {
3388 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3389 ovl->name);
f0e5caab 3390 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3391 dispc_mgr_go(ovl->manager->id);
80c39712 3392 mdelay(50);
80c39712
TV		 3393 }
3394 }
3395
fe3cc9d6
TV		 3396 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3397 struct omap_overlay_manager *mgr;
3398 unsigned bit;
80c39712 3399
fe3cc9d6
TV		 3400 mgr = omap_dss_get_overlay_manager(i);
3401 bit = sync_lost_bits[i];
80c39712 3402
fe3cc9d6
TV		 3403 if (bit & errors) {
3404 struct omap_dss_device *dssdev = mgr->device;
3405 bool enable;
80c39712 3406
fe3cc9d6
TV		 3407 DSSERR("SYNC_LOST on channel %s, restarting the output "
3408 "with video overlays disabled\n",
3409 mgr->name);
2a205f34 3410
fe3cc9d6
TV		 3411 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3412 dssdev->driver->disable(dssdev);
2a205f34 3413
2a205f34
SS		 3414 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3415 struct omap_overlay *ovl;
3416 ovl = omap_dss_get_overlay(i);
3417
fe3cc9d6
TV		 3418 if (ovl->id != OMAP_DSS_GFX &&
3419 ovl->manager == mgr)
f0e5caab 3420 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3421 }
3422
26d9dd0d 3423 dispc_mgr_go(mgr->id);
2a205f34 3424 mdelay(50);
fe3cc9d6 3425
2a205f34
SS		 3426 if (enable)
3427 dssdev->driver->enable(dssdev);
3428 }
3429 }
3430
80c39712
TV		 3431 if (errors & DISPC_IRQ_OCP_ERR) {
3432 DSSERR("OCP_ERR\n");
3433 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3434 struct omap_overlay_manager *mgr;
3435 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3436 if (mgr->device && mgr->device->driver)
3437 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3438 }
3439 }
3440
3441 spin_lock_irqsave(&dispc.irq_lock, flags);
3442 dispc.irq_error_mask |= errors;
3443 _omap_dispc_set_irqs();
3444 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3445
3446 dispc_runtime_put();
80c39712
TV		 3447}
3448
3449int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3450{
3451 void dispc_irq_wait_handler(void *data, u32 mask)
3452 {
3453 complete((struct completion *)data);
3454 }
3455
3456 int r;
3457 DECLARE_COMPLETION_ONSTACK(completion);
3458
3459 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3460 irqmask);
3461
3462 if (r)
3463 return r;
3464
3465 timeout = wait_for_completion_timeout(&completion, timeout);
3466
3467 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3468
3469 if (timeout == 0)
3470 return -ETIMEDOUT;
3471
3472 if (timeout == -ERESTARTSYS)
3473 return -ERESTARTSYS;
3474
3475 return 0;
3476}
3477
3478int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3479 unsigned long timeout)
3480{
3481 void dispc_irq_wait_handler(void *data, u32 mask)
3482 {
3483 complete((struct completion *)data);
3484 }
3485
3486 int r;
3487 DECLARE_COMPLETION_ONSTACK(completion);
3488
3489 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3490 irqmask);
3491
3492 if (r)
3493 return r;
3494
3495 timeout = wait_for_completion_interruptible_timeout(&completion,
3496 timeout);
3497
3498 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3499
3500 if (timeout == 0)
3501 return -ETIMEDOUT;
3502
3503 if (timeout == -ERESTARTSYS)
3504 return -ERESTARTSYS;
3505
3506 return 0;
3507}
3508
80c39712
TV		 3509static void _omap_dispc_initialize_irq(void)
3510{
3511 unsigned long flags;
3512
3513 spin_lock_irqsave(&dispc.irq_lock, flags);
3514
3515 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3516
3517 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3518 if (dss_has_feature(FEAT_MGR_LCD2))
3519 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3520 if (dss_feat_get_num_ovls() > 3)
3521 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3522
3523 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3524 * so clear it */
3525 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3526
3527 _omap_dispc_set_irqs();
3528
3529 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3530}
3531
3532void dispc_enable_sidle(void)
3533{
3534 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3535}
3536
3537void dispc_disable_sidle(void)
3538{
3539 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3540}
3541
3542static void _omap_dispc_initial_config(void)
3543{
3544 u32 l;
3545
0cf35df3
MR		 3546 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3547 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3548 l = dispc_read_reg(DISPC_DIVISOR);
3549 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3550 l = FLD_MOD(l, 1, 0, 0);
3551 l = FLD_MOD(l, 1, 23, 16);
3552 dispc_write_reg(DISPC_DIVISOR, l);
3553 }
3554
80c39712 3555 /* FUNCGATED */
6ced40bf
AT		 3556 if (dss_has_feature(FEAT_FUNCGATED))
3557 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3558
80c39712
TV		 3559 _dispc_setup_color_conv_coef();
3560
3561 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3562
3563 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3564
3565 dispc_configure_burst_sizes();
54128701
AT		 3566
3567 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3568}
3569
060b6d9c 3570/* DISPC HW IP initialisation */
6e7e8f06 3571static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3572{
3573 u32 rev;
affe360d 3574 int r = 0;
ea9da36a 3575 struct resource *dispc_mem;
4fbafaf3 3576 struct clk *clk;
ea9da36a 3577
060b6d9c
SG		 3578 dispc.pdev = pdev;
3579
3580 spin_lock_init(&dispc.irq_lock);
3581
3582#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3583 spin_lock_init(&dispc.irq_stats_lock);
3584 dispc.irq_stats.last_reset = jiffies;
3585#endif
3586
3587 INIT_WORK(&dispc.error_work, dispc_error_worker);
3588
ea9da36a
SG		 3589 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3590 if (!dispc_mem) {
3591 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3592 return -EINVAL;
ea9da36a 3593 }
cd3b3449 3594
6e2a14d2
JL		 3595 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3596 resource_size(dispc_mem));
060b6d9c
SG		 3597 if (!dispc.base) {
3598 DSSERR("can't ioremap DISPC\n");
cd3b3449 3599 return -ENOMEM;
affe360d 3600 }
cd3b3449 3601
affe360d 3602 dispc.irq = platform_get_irq(dispc.pdev, 0);
3603 if (dispc.irq < 0) {
3604 DSSERR("platform_get_irq failed\n");
cd3b3449 3605 return -ENODEV;
affe360d 3606 }
3607
6e2a14d2
JL		 3608 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3609 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3610 if (r < 0) {
3611 DSSERR("request_irq failed\n");
cd3b3449
TV		 3612 return r;
3613 }
3614
3615 clk = clk_get(&pdev->dev, "fck");
3616 if (IS_ERR(clk)) {
3617 DSSERR("can't get fck\n");
3618 r = PTR_ERR(clk);
3619 return r;
060b6d9c
SG		 3620 }
3621
cd3b3449
TV		 3622 dispc.dss_clk = clk;
3623
4fbafaf3
TV		 3624 pm_runtime_enable(&pdev->dev);
3625
3626 r = dispc_runtime_get();
3627 if (r)
3628 goto err_runtime_get;
060b6d9c
SG		 3629
3630 _omap_dispc_initial_config();
3631
3632 _omap_dispc_initialize_irq();
3633
060b6d9c 3634 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3635 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3636 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3637
4fbafaf3 3638 dispc_runtime_put();
060b6d9c 3639
e40402cf
TV		 3640 dss_debugfs_create_file("dispc", dispc_dump_regs);
3641
3642#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3643 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3644#endif
060b6d9c 3645 return 0;
4fbafaf3
TV		 3646
3647err_runtime_get:
3648 pm_runtime_disable(&pdev->dev);
4fbafaf3 3649 clk_put(dispc.dss_clk);
affe360d 3650 return r;
060b6d9c
SG		 3651}
3652
6e7e8f06 3653static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3654{
4fbafaf3
TV		 3655 pm_runtime_disable(&pdev->dev);
3656
3657 clk_put(dispc.dss_clk);
3658
060b6d9c
SG		 3659 return 0;
3660}
3661
4fbafaf3
TV		 3662static int dispc_runtime_suspend(struct device *dev)
3663{
3664 dispc_save_context();
4fbafaf3
TV		 3665
3666 return 0;
3667}
3668
3669static int dispc_runtime_resume(struct device *dev)
3670{
49ea86f3 3671 dispc_restore_context();
4fbafaf3
TV		 3672
3673 return 0;
3674}
3675
3676static const struct dev_pm_ops dispc_pm_ops = {
3677 .runtime_suspend = dispc_runtime_suspend,
3678 .runtime_resume = dispc_runtime_resume,
3679};
3680
060b6d9c 3681static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3682 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3683 .driver = {
3684 .name = "omapdss_dispc",
3685 .owner = THIS_MODULE,
4fbafaf3 3686 .pm = &dispc_pm_ops,
060b6d9c
SG		 3687 },
3688};
3689
6e7e8f06 3690int __init dispc_init_platform_driver(void)
060b6d9c 3691{
11436e1d 3692 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3693}
3694
6e7e8f06 3695void __exit dispc_uninit_platform_driver(void)
060b6d9c 3696{
04c742c3 3697 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3698}
Linux kernel - Deliverables
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