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OMAPDSS: DISPC: pass pclk to calc_core_clk()
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
33366d0e 39#include <linux/sizes.h>
80c39712 40
a0b38cc4 41#include <video/omapdss.h>
80c39712
TV		 42
43#include "dss.h"
a0acb557 44#include "dss_features.h"
9b372c2d 45#include "dispc.h"
80c39712
TV		 46
47/* DISPC */
8613b000 48#define DISPC_SZ_REGS SZ_4K
80c39712 49
80c39712
TV		 50#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
51 DISPC_IRQ_OCP_ERR | \
52 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
53 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
54 DISPC_IRQ_SYNC_LOST | \
55 DISPC_IRQ_SYNC_LOST_DIGIT)
56
57#define DISPC_MAX_NR_ISRS 8
58
59struct omap_dispc_isr_data {
60 omap_dispc_isr_t isr;
61 void *arg;
62 u32 mask;
63};
64
5ed8cf5b
TV		 65enum omap_burst_size {
66 BURST_SIZE_X2 = 0,
67 BURST_SIZE_X4 = 1,
68 BURST_SIZE_X8 = 2,
69};
70
80c39712
TV		 71#define REG_GET(idx, start, end) \
72 FLD_GET(dispc_read_reg(idx), start, end)
73
74#define REG_FLD_MOD(idx, val, start, end) \
75 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
76
dfc0fd8d
TV		 77struct dispc_irq_stats {
78 unsigned long last_reset;
79 unsigned irq_count;
80 unsigned irqs[32];
81};
82
dcbe765b
CM		 83struct dispc_features {
84 u8 sw_start;
85 u8 fp_start;
86 u8 bp_start;
87 u16 sw_max;
88 u16 vp_max;
89 u16 hp_max;
33b89928
AT		 90 u8 mgr_width_start;
91 u8 mgr_height_start;
92 u16 mgr_width_max;
93 u16 mgr_height_max;
3e8a6ff2 94 int (*calc_scaling) (enum omap_plane plane,
dcbe765b
CM		 95 const struct omap_video_timings *mgr_timings,
96 u16 width, u16 height, u16 out_width, u16 out_height,
97 enum omap_color_mode color_mode, bool *five_taps,
98 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 99 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 100 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 101 u16 width, u16 height, u16 out_width, u16 out_height,
102 bool mem_to_mem);
42a6961c 103 u8 num_fifos;
66a0f9e4
TV		 104
105 /* swap GFX & WB fifos */
106 bool gfx_fifo_workaround:1;
cffa947d
TV		 107
108 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
109 bool no_framedone_tv:1;
dcbe765b
CM		 110};
111
42a6961c
TV		 112#define DISPC_MAX_NR_FIFOS 5
113
80c39712 114static struct {
060b6d9c 115 struct platform_device *pdev;
80c39712 116 void __iomem *base;
4fbafaf3
TV		 117
118 int ctx_loss_cnt;
119
affe360d 120 int irq;
4fbafaf3 121 struct clk *dss_clk;
80c39712 122
42a6961c
TV		 123 u32 fifo_size[DISPC_MAX_NR_FIFOS];
124 /* maps which plane is using a fifo. fifo-id -> plane-id */
125 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712
TV		 126
127 spinlock_t irq_lock;
128 u32 irq_error_mask;
129 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
130 u32 error_irqs;
131 struct work_struct error_work;
132
49ea86f3 133 bool ctx_valid;
80c39712 134 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 135
dcbe765b
CM		 136 const struct dispc_features *feat;
137
dfc0fd8d
TV		 138#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
139 spinlock_t irq_stats_lock;
140 struct dispc_irq_stats irq_stats;
141#endif
80c39712
TV		 142} dispc;
143
0d66cbb5
AJ		 144enum omap_color_component {
145 /* used for all color formats for OMAP3 and earlier
146 * and for RGB and Y color component on OMAP4
147 */
148 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
149 /* used for UV component for
150 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
151 * color formats on OMAP4
152 */
153 DISPC_COLOR_COMPONENT_UV = 1 << 1,
154};
155
efa70b3b
CM		 156enum mgr_reg_fields {
157 DISPC_MGR_FLD_ENABLE,
158 DISPC_MGR_FLD_STNTFT,
159 DISPC_MGR_FLD_GO,
160 DISPC_MGR_FLD_TFTDATALINES,
161 DISPC_MGR_FLD_STALLMODE,
162 DISPC_MGR_FLD_TCKENABLE,
163 DISPC_MGR_FLD_TCKSELECTION,
164 DISPC_MGR_FLD_CPR,
165 DISPC_MGR_FLD_FIFOHANDCHECK,
166 /* used to maintain a count of the above fields */
167 DISPC_MGR_FLD_NUM,
168};
169
170static const struct {
171 const char *name;
172 u32 vsync_irq;
173 u32 framedone_irq;
174 u32 sync_lost_irq;
175 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
176} mgr_desc[] = {
177 [OMAP_DSS_CHANNEL_LCD] = {
178 .name = "LCD",
179 .vsync_irq = DISPC_IRQ_VSYNC,
180 .framedone_irq = DISPC_IRQ_FRAMEDONE,
181 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
182 .reg_desc = {
183 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
184 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
185 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
186 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
187 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
188 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
189 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
190 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
191 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
192 },
193 },
194 [OMAP_DSS_CHANNEL_DIGIT] = {
195 .name = "DIGIT",
196 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 197 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 198 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
199 .reg_desc = {
200 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
201 [DISPC_MGR_FLD_STNTFT] = { },
202 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
203 [DISPC_MGR_FLD_TFTDATALINES] = { },
204 [DISPC_MGR_FLD_STALLMODE] = { },
205 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
206 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
207 [DISPC_MGR_FLD_CPR] = { },
208 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
209 },
210 },
211 [OMAP_DSS_CHANNEL_LCD2] = {
212 .name = "LCD2",
213 .vsync_irq = DISPC_IRQ_VSYNC2,
214 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
215 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
216 .reg_desc = {
217 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
218 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
219 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
220 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
221 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
222 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
223 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
224 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
225 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
226 },
227 },
e86d456a
CM		 228 [OMAP_DSS_CHANNEL_LCD3] = {
229 .name = "LCD3",
230 .vsync_irq = DISPC_IRQ_VSYNC3,
231 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
232 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
233 .reg_desc = {
234 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
235 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
236 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
237 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
238 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
239 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
240 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
241 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
242 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
243 },
244 },
efa70b3b
CM		 245};
246
6e5264b0
AT		 247struct color_conv_coef {
248 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
249 int full_range;
250};
251
80c39712 252static void _omap_dispc_set_irqs(void);
3e8a6ff2
AT		 253static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
254static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 255
55978cc2 256static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 257{
55978cc2 258 __raw_writel(val, dispc.base + idx);
80c39712
TV		 259}
260
55978cc2 261static inline u32 dispc_read_reg(const u16 idx)
80c39712 262{
55978cc2 263 return __raw_readl(dispc.base + idx);
80c39712
TV		 264}
265
efa70b3b
CM		 266static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
267{
268 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
269 return REG_GET(rfld.reg, rfld.high, rfld.low);
270}
271
272static void mgr_fld_write(enum omap_channel channel,
273 enum mgr_reg_fields regfld, int val) {
274 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
276}
277
80c39712 278#define SR(reg) \
55978cc2 279 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 280#define RR(reg) \
55978cc2 281 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 282
4fbafaf3 283static void dispc_save_context(void)
80c39712 284{
c6104b8e 285 int i, j;
80c39712 286
4fbafaf3
TV		 287 DSSDBG("dispc_save_context\n");
288
80c39712
TV		 289 SR(IRQENABLE);
290 SR(CONTROL);
291 SR(CONFIG);
80c39712 292 SR(LINE_NUMBER);
11354dd5
AT		 293 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
294 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 295 SR(GLOBAL_ALPHA);
2a205f34
SS		 296 if (dss_has_feature(FEAT_MGR_LCD2)) {
297 SR(CONTROL2);
2a205f34
SS		 298 SR(CONFIG2);
299 }
e86d456a
CM		 300 if (dss_has_feature(FEAT_MGR_LCD3)) {
301 SR(CONTROL3);
302 SR(CONFIG3);
303 }
80c39712 304
c6104b8e
AT		 305 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
306 SR(DEFAULT_COLOR(i));
307 SR(TRANS_COLOR(i));
308 SR(SIZE_MGR(i));
309 if (i == OMAP_DSS_CHANNEL_DIGIT)
310 continue;
311 SR(TIMING_H(i));
312 SR(TIMING_V(i));
313 SR(POL_FREQ(i));
314 SR(DIVISORo(i));
315
316 SR(DATA_CYCLE1(i));
317 SR(DATA_CYCLE2(i));
318 SR(DATA_CYCLE3(i));
319
332e9d70 320 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 321 SR(CPR_COEF_R(i));
322 SR(CPR_COEF_G(i));
323 SR(CPR_COEF_B(i));
332e9d70 324 }
2a205f34 325 }
80c39712 326
c6104b8e
AT		 327 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
328 SR(OVL_BA0(i));
329 SR(OVL_BA1(i));
330 SR(OVL_POSITION(i));
331 SR(OVL_SIZE(i));
332 SR(OVL_ATTRIBUTES(i));
333 SR(OVL_FIFO_THRESHOLD(i));
334 SR(OVL_ROW_INC(i));
335 SR(OVL_PIXEL_INC(i));
336 if (dss_has_feature(FEAT_PRELOAD))
337 SR(OVL_PRELOAD(i));
338 if (i == OMAP_DSS_GFX) {
339 SR(OVL_WINDOW_SKIP(i));
340 SR(OVL_TABLE_BA(i));
341 continue;
342 }
343 SR(OVL_FIR(i));
344 SR(OVL_PICTURE_SIZE(i));
345 SR(OVL_ACCU0(i));
346 SR(OVL_ACCU1(i));
9b372c2d 347
c6104b8e
AT		 348 for (j = 0; j < 8; j++)
349 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 350
c6104b8e
AT		 351 for (j = 0; j < 8; j++)
352 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 353
c6104b8e
AT		 354 for (j = 0; j < 5; j++)
355 SR(OVL_CONV_COEF(i, j));
ab5ca071 356
c6104b8e
AT		 357 if (dss_has_feature(FEAT_FIR_COEF_V)) {
358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_V(i, j));
360 }
9b372c2d 361
c6104b8e
AT		 362 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
363 SR(OVL_BA0_UV(i));
364 SR(OVL_BA1_UV(i));
365 SR(OVL_FIR2(i));
366 SR(OVL_ACCU2_0(i));
367 SR(OVL_ACCU2_1(i));
ab5ca071 368
c6104b8e
AT		 369 for (j = 0; j < 8; j++)
370 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 371
c6104b8e
AT		 372 for (j = 0; j < 8; j++)
373 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 374
c6104b8e
AT		 375 for (j = 0; j < 8; j++)
376 SR(OVL_FIR_COEF_V2(i, j));
377 }
378 if (dss_has_feature(FEAT_ATTR2))
379 SR(OVL_ATTRIBUTES2(i));
ab5ca071 380 }
0cf35df3
MR		 381
382 if (dss_has_feature(FEAT_CORE_CLK_DIV))
383 SR(DIVISOR);
49ea86f3 384
00928eaf 385 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 386 dispc.ctx_valid = true;
387
388 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 389}
390
4fbafaf3 391static void dispc_restore_context(void)
80c39712 392{
c6104b8e 393 int i, j, ctx;
4fbafaf3
TV		 394
395 DSSDBG("dispc_restore_context\n");
396
49ea86f3
TV		 397 if (!dispc.ctx_valid)
398 return;
399
00928eaf 400 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 401
402 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
403 return;
404
405 DSSDBG("ctx_loss_count: saved %d, current %d\n",
406 dispc.ctx_loss_cnt, ctx);
407
75c7d59d 408 /*RR(IRQENABLE);*/
80c39712
TV		 409 /*RR(CONTROL);*/
410 RR(CONFIG);
80c39712 411 RR(LINE_NUMBER);
11354dd5
AT		 412 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
413 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 414 RR(GLOBAL_ALPHA);
c6104b8e 415 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 416 RR(CONFIG2);
e86d456a
CM		 417 if (dss_has_feature(FEAT_MGR_LCD3))
418 RR(CONFIG3);
80c39712 419
c6104b8e
AT		 420 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
421 RR(DEFAULT_COLOR(i));
422 RR(TRANS_COLOR(i));
423 RR(SIZE_MGR(i));
424 if (i == OMAP_DSS_CHANNEL_DIGIT)
425 continue;
426 RR(TIMING_H(i));
427 RR(TIMING_V(i));
428 RR(POL_FREQ(i));
429 RR(DIVISORo(i));
430
431 RR(DATA_CYCLE1(i));
432 RR(DATA_CYCLE2(i));
433 RR(DATA_CYCLE3(i));
2a205f34 434
332e9d70 435 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 436 RR(CPR_COEF_R(i));
437 RR(CPR_COEF_G(i));
438 RR(CPR_COEF_B(i));
332e9d70 439 }
2a205f34 440 }
80c39712 441
c6104b8e
AT		 442 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
443 RR(OVL_BA0(i));
444 RR(OVL_BA1(i));
445 RR(OVL_POSITION(i));
446 RR(OVL_SIZE(i));
447 RR(OVL_ATTRIBUTES(i));
448 RR(OVL_FIFO_THRESHOLD(i));
449 RR(OVL_ROW_INC(i));
450 RR(OVL_PIXEL_INC(i));
451 if (dss_has_feature(FEAT_PRELOAD))
452 RR(OVL_PRELOAD(i));
453 if (i == OMAP_DSS_GFX) {
454 RR(OVL_WINDOW_SKIP(i));
455 RR(OVL_TABLE_BA(i));
456 continue;
457 }
458 RR(OVL_FIR(i));
459 RR(OVL_PICTURE_SIZE(i));
460 RR(OVL_ACCU0(i));
461 RR(OVL_ACCU1(i));
9b372c2d 462
c6104b8e
AT		 463 for (j = 0; j < 8; j++)
464 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 465
c6104b8e
AT		 466 for (j = 0; j < 8; j++)
467 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 468
c6104b8e
AT		 469 for (j = 0; j < 5; j++)
470 RR(OVL_CONV_COEF(i, j));
ab5ca071 471
c6104b8e
AT		 472 if (dss_has_feature(FEAT_FIR_COEF_V)) {
473 for (j = 0; j < 8; j++)
474 RR(OVL_FIR_COEF_V(i, j));
475 }
9b372c2d 476
c6104b8e
AT		 477 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
478 RR(OVL_BA0_UV(i));
479 RR(OVL_BA1_UV(i));
480 RR(OVL_FIR2(i));
481 RR(OVL_ACCU2_0(i));
482 RR(OVL_ACCU2_1(i));
ab5ca071 483
c6104b8e
AT		 484 for (j = 0; j < 8; j++)
485 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 486
c6104b8e
AT		 487 for (j = 0; j < 8; j++)
488 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 489
c6104b8e
AT		 490 for (j = 0; j < 8; j++)
491 RR(OVL_FIR_COEF_V2(i, j));
492 }
493 if (dss_has_feature(FEAT_ATTR2))
494 RR(OVL_ATTRIBUTES2(i));
ab5ca071 495 }
80c39712 496
0cf35df3
MR		 497 if (dss_has_feature(FEAT_CORE_CLK_DIV))
498 RR(DIVISOR);
499
80c39712
TV		 500 /* enable last, because LCD & DIGIT enable are here */
501 RR(CONTROL);
2a205f34
SS		 502 if (dss_has_feature(FEAT_MGR_LCD2))
503 RR(CONTROL2);
e86d456a
CM		 504 if (dss_has_feature(FEAT_MGR_LCD3))
505 RR(CONTROL3);
75c7d59d 506 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 507 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 508
509 /*
510 * enable last so IRQs won't trigger before
511 * the context is fully restored
512 */
513 RR(IRQENABLE);
49ea86f3
TV		 514
515 DSSDBG("context restored\n");
80c39712
TV		 516}
517
518#undef SR
519#undef RR
520
4fbafaf3
TV		 521int dispc_runtime_get(void)
522{
523 int r;
524
525 DSSDBG("dispc_runtime_get\n");
526
527 r = pm_runtime_get_sync(&dispc.pdev->dev);
528 WARN_ON(r < 0);
529 return r < 0 ? r : 0;
530}
531
532void dispc_runtime_put(void)
533{
534 int r;
535
536 DSSDBG("dispc_runtime_put\n");
537
0eaf9f52 538 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 539 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 540}
541
3dcec4d6
TV		 542u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
543{
efa70b3b 544 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 545}
546
7d1365c9
TV		 547u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
548{
cffa947d
TV		 549 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
550 return 0;
551
efa70b3b 552 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 553}
554
cb699200
TV		 555u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
556{
557 return mgr_desc[channel].sync_lost_irq;
558}
559
0b23e5b8
AT		 560u32 dispc_wb_get_framedone_irq(void)
561{
562 return DISPC_IRQ_FRAMEDONEWB;
563}
564
26d9dd0d 565bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 566{
efa70b3b 567 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 568}
569
26d9dd0d 570void dispc_mgr_go(enum omap_channel channel)
80c39712 571{
3c91ee8c
TV		 572 WARN_ON(dispc_mgr_is_enabled(channel) == false);
573 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 574
efa70b3b 575 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 576
efa70b3b 577 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 578}
579
0b23e5b8
AT		 580bool dispc_wb_go_busy(void)
581{
582 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
583}
584
585void dispc_wb_go(void)
586{
587 enum omap_plane plane = OMAP_DSS_WB;
588 bool enable, go;
589
590 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
591
592 if (!enable)
593 return;
594
595 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
596 if (go) {
597 DSSERR("GO bit not down for WB\n");
598 return;
599 }
600
601 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
602}
603
f0e5caab 604static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 605{
9b372c2d 606 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 607}
608
f0e5caab 609static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 610{
9b372c2d 611 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 612}
613
f0e5caab 614static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 615{
9b372c2d 616 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 617}
618
f0e5caab 619static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 620{
621 BUG_ON(plane == OMAP_DSS_GFX);
622
623 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
624}
625
f0e5caab
TV		 626static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
627 u32 value)
ab5ca071
AJ		 628{
629 BUG_ON(plane == OMAP_DSS_GFX);
630
631 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
632}
633
f0e5caab 634static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 635{
636 BUG_ON(plane == OMAP_DSS_GFX);
637
638 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
639}
640
debd9074
CM		 641static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
642 int fir_vinc, int five_taps,
643 enum omap_color_component color_comp)
80c39712 644{
debd9074 645 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 646 int i;
647
debd9074
CM		 648 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
649 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 650
651 for (i = 0; i < 8; i++) {
652 u32 h, hv;
653
debd9074
CM		 654 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
655 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
656 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
657 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
658 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
659 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
660 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
661 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 662
0d66cbb5 663 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 664 dispc_ovl_write_firh_reg(plane, i, h);
665 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 666 } else {
f0e5caab
TV		 667 dispc_ovl_write_firh2_reg(plane, i, h);
668 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 669 }
670
80c39712
TV		 671 }
672
66be8f6c
GI		 673 if (five_taps) {
674 for (i = 0; i < 8; i++) {
675 u32 v;
debd9074
CM		 676 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
677 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 678 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 679 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 680 else
f0e5caab 681 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 682 }
80c39712
TV		 683 }
684}
685
80c39712 686
6e5264b0
AT		 687static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
688 const struct color_conv_coef *ct)
689{
80c39712
TV		 690#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
691
6e5264b0
AT		 692 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
693 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
694 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
695 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
696 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 697
6e5264b0 698 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 699
700#undef CVAL
80c39712
TV		 701}
702
6e5264b0
AT		 703static void dispc_setup_color_conv_coef(void)
704{
705 int i;
706 int num_ovl = dss_feat_get_num_ovls();
707 int num_wb = dss_feat_get_num_wbs();
708 const struct color_conv_coef ctbl_bt601_5_ovl = {
709 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
710 };
711 const struct color_conv_coef ctbl_bt601_5_wb = {
712 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
713 };
714
715 for (i = 1; i < num_ovl; i++)
716 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
717
718 for (; i < num_wb; i++)
719 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
720}
80c39712 721
f0e5caab 722static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 723{
9b372c2d 724 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 725}
726
f0e5caab 727static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 728{
9b372c2d 729 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 730}
731
f0e5caab 732static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 733{
734 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
735}
736
f0e5caab 737static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 738{
739 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
740}
741
d79db853
AT		 742static void dispc_ovl_set_pos(enum omap_plane plane,
743 enum omap_overlay_caps caps, int x, int y)
80c39712 744{
d79db853
AT		 745 u32 val;
746
747 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
748 return;
749
750 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 751
752 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 753}
754
78b687fc
AT		 755static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
756 int height)
80c39712 757{
80c39712 758 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 759
36d87d95 760 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 761 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
762 else
763 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 764}
765
78b687fc
AT		 766static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
767 int height)
80c39712
TV		 768{
769 u32 val;
80c39712
TV		 770
771 BUG_ON(plane == OMAP_DSS_GFX);
772
773 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 774
36d87d95
AT		 775 if (plane == OMAP_DSS_WB)
776 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
777 else
778 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 779}
780
5b54ed3e
AT		 781static void dispc_ovl_set_zorder(enum omap_plane plane,
782 enum omap_overlay_caps caps, u8 zorder)
54128701 783{
5b54ed3e 784 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 785 return;
786
787 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
788}
789
790static void dispc_ovl_enable_zorder_planes(void)
791{
792 int i;
793
794 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
795 return;
796
797 for (i = 0; i < dss_feat_get_num_ovls(); i++)
798 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
799}
800
5b54ed3e
AT		 801static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
802 enum omap_overlay_caps caps, bool enable)
fd28a390 803{
5b54ed3e 804 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 805 return;
806
9b372c2d 807 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 808}
809
5b54ed3e
AT		 810static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
811 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 812{
b8c095b4 813 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 814 int shift;
815
5b54ed3e 816 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 817 return;
a0acb557 818
fe3cc9d6
TV		 819 shift = shifts[plane];
820 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 821}
822
f0e5caab 823static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 824{
9b372c2d 825 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 826}
827
f0e5caab 828static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 829{
9b372c2d 830 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 831}
832
f0e5caab 833static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 834 enum omap_color_mode color_mode)
835{
836 u32 m = 0;
f20e4220
AJ		 837 if (plane != OMAP_DSS_GFX) {
838 switch (color_mode) {
839 case OMAP_DSS_COLOR_NV12:
840 m = 0x0; break;
08f3267e 841 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 842 m = 0x1; break;
843 case OMAP_DSS_COLOR_RGBA16:
844 m = 0x2; break;
08f3267e 845 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 846 m = 0x4; break;
847 case OMAP_DSS_COLOR_ARGB16:
848 m = 0x5; break;
849 case OMAP_DSS_COLOR_RGB16:
850 m = 0x6; break;
851 case OMAP_DSS_COLOR_ARGB16_1555:
852 m = 0x7; break;
853 case OMAP_DSS_COLOR_RGB24U:
854 m = 0x8; break;
855 case OMAP_DSS_COLOR_RGB24P:
856 m = 0x9; break;
857 case OMAP_DSS_COLOR_YUV2:
858 m = 0xa; break;
859 case OMAP_DSS_COLOR_UYVY:
860 m = 0xb; break;
861 case OMAP_DSS_COLOR_ARGB32:
862 m = 0xc; break;
863 case OMAP_DSS_COLOR_RGBA32:
864 m = 0xd; break;
865 case OMAP_DSS_COLOR_RGBX32:
866 m = 0xe; break;
867 case OMAP_DSS_COLOR_XRGB16_1555:
868 m = 0xf; break;
869 default:
c6eee968 870 BUG(); return;
f20e4220
AJ		 871 }
872 } else {
873 switch (color_mode) {
874 case OMAP_DSS_COLOR_CLUT1:
875 m = 0x0; break;
876 case OMAP_DSS_COLOR_CLUT2:
877 m = 0x1; break;
878 case OMAP_DSS_COLOR_CLUT4:
879 m = 0x2; break;
880 case OMAP_DSS_COLOR_CLUT8:
881 m = 0x3; break;
882 case OMAP_DSS_COLOR_RGB12U:
883 m = 0x4; break;
884 case OMAP_DSS_COLOR_ARGB16:
885 m = 0x5; break;
886 case OMAP_DSS_COLOR_RGB16:
887 m = 0x6; break;
888 case OMAP_DSS_COLOR_ARGB16_1555:
889 m = 0x7; break;
890 case OMAP_DSS_COLOR_RGB24U:
891 m = 0x8; break;
892 case OMAP_DSS_COLOR_RGB24P:
893 m = 0x9; break;
08f3267e 894 case OMAP_DSS_COLOR_RGBX16:
f20e4220 895 m = 0xa; break;
08f3267e 896 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 897 m = 0xb; break;
898 case OMAP_DSS_COLOR_ARGB32:
899 m = 0xc; break;
900 case OMAP_DSS_COLOR_RGBA32:
901 m = 0xd; break;
902 case OMAP_DSS_COLOR_RGBX32:
903 m = 0xe; break;
904 case OMAP_DSS_COLOR_XRGB16_1555:
905 m = 0xf; break;
906 default:
c6eee968 907 BUG(); return;
f20e4220 908 }
80c39712
TV		 909 }
910
9b372c2d 911 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 912}
913
65e006ff
CM		 914static void dispc_ovl_configure_burst_type(enum omap_plane plane,
915 enum omap_dss_rotation_type rotation_type)
916{
917 if (dss_has_feature(FEAT_BURST_2D) == 0)
918 return;
919
920 if (rotation_type == OMAP_DSS_ROT_TILER)
921 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
922 else
923 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
924}
925
f427984e 926void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 927{
928 int shift;
929 u32 val;
2a205f34 930 int chan = 0, chan2 = 0;
80c39712
TV		 931
932 switch (plane) {
933 case OMAP_DSS_GFX:
934 shift = 8;
935 break;
936 case OMAP_DSS_VIDEO1:
937 case OMAP_DSS_VIDEO2:
b8c095b4 938 case OMAP_DSS_VIDEO3:
80c39712
TV		 939 shift = 16;
940 break;
941 default:
942 BUG();
943 return;
944 }
945
9b372c2d 946 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 947 if (dss_has_feature(FEAT_MGR_LCD2)) {
948 switch (channel) {
949 case OMAP_DSS_CHANNEL_LCD:
950 chan = 0;
951 chan2 = 0;
952 break;
953 case OMAP_DSS_CHANNEL_DIGIT:
954 chan = 1;
955 chan2 = 0;
956 break;
957 case OMAP_DSS_CHANNEL_LCD2:
958 chan = 0;
959 chan2 = 1;
960 break;
e86d456a
CM		 961 case OMAP_DSS_CHANNEL_LCD3:
962 if (dss_has_feature(FEAT_MGR_LCD3)) {
963 chan = 0;
964 chan2 = 2;
965 } else {
966 BUG();
967 return;
968 }
969 break;
2a205f34
SS		 970 default:
971 BUG();
c6eee968 972 return;
2a205f34
SS		 973 }
974
975 val = FLD_MOD(val, chan, shift, shift);
976 val = FLD_MOD(val, chan2, 31, 30);
977 } else {
978 val = FLD_MOD(val, channel, shift, shift);
979 }
9b372c2d 980 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 981}
982
2cc5d1af
TV		 983static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
984{
985 int shift;
986 u32 val;
987 enum omap_channel channel;
988
989 switch (plane) {
990 case OMAP_DSS_GFX:
991 shift = 8;
992 break;
993 case OMAP_DSS_VIDEO1:
994 case OMAP_DSS_VIDEO2:
995 case OMAP_DSS_VIDEO3:
996 shift = 16;
997 break;
998 default:
999 BUG();
c6eee968 1000 return 0;
2cc5d1af
TV		 1001 }
1002
1003 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1004
e86d456a
CM		 1005 if (dss_has_feature(FEAT_MGR_LCD3)) {
1006 if (FLD_GET(val, 31, 30) == 0)
1007 channel = FLD_GET(val, shift, shift);
1008 else if (FLD_GET(val, 31, 30) == 1)
1009 channel = OMAP_DSS_CHANNEL_LCD2;
1010 else
1011 channel = OMAP_DSS_CHANNEL_LCD3;
1012 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 1013 if (FLD_GET(val, 31, 30) == 0)
1014 channel = FLD_GET(val, shift, shift);
1015 else
1016 channel = OMAP_DSS_CHANNEL_LCD2;
1017 } else {
1018 channel = FLD_GET(val, shift, shift);
1019 }
1020
1021 return channel;
1022}
1023
d9ac773c
AT		 1024void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1025{
1026 enum omap_plane plane = OMAP_DSS_WB;
1027
1028 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1029}
1030
f0e5caab 1031static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1032 enum omap_burst_size burst_size)
1033{
8bbe09ee 1034 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1035 int shift;
80c39712 1036
fe3cc9d6 1037 shift = shifts[plane];
5ed8cf5b 1038 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1039}
1040
5ed8cf5b
TV		 1041static void dispc_configure_burst_sizes(void)
1042{
1043 int i;
1044 const int burst_size = BURST_SIZE_X8;
1045
1046 /* Configure burst size always to maximum size */
392faa0e 1047 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1048 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1049}
1050
83fa2f2e 1051static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1052{
1053 unsigned unit = dss_feat_get_burst_size_unit();
1054 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1055 return unit * 8;
1056}
1057
d3862610
M		 1058void dispc_enable_gamma_table(bool enable)
1059{
1060 /*
1061 * This is partially implemented to support only disabling of
1062 * the gamma table.
1063 */
1064 if (enable) {
1065 DSSWARN("Gamma table enabling for TV not yet supported");
1066 return;
1067 }
1068
1069 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1070}
1071
c64dca40 1072static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1073{
efa70b3b 1074 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1075 return;
1076
efa70b3b 1077 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1078}
1079
c64dca40 1080static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1081 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1082{
1083 u32 coef_r, coef_g, coef_b;
1084
dd88b7a6 1085 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1086 return;
1087
1088 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1089 FLD_VAL(coefs->rb, 9, 0);
1090 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1091 FLD_VAL(coefs->gb, 9, 0);
1092 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1093 FLD_VAL(coefs->bb, 9, 0);
1094
1095 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1096 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1097 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1098}
1099
f0e5caab 1100static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1101{
1102 u32 val;
1103
1104 BUG_ON(plane == OMAP_DSS_GFX);
1105
9b372c2d 1106 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1107 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1108 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1109}
1110
d79db853
AT		 1111static void dispc_ovl_enable_replication(enum omap_plane plane,
1112 enum omap_overlay_caps caps, bool enable)
80c39712 1113{
b8c095b4 1114 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1115 int shift;
80c39712 1116
d79db853
AT		 1117 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1118 return;
1119
fe3cc9d6
TV		 1120 shift = shifts[plane];
1121 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1122}
1123
8f366162 1124static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1125 u16 height)
80c39712
TV		 1126{
1127 u32 val;
80c39712 1128
33b89928
AT		 1129 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1130 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1131
8f366162 1132 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1133}
1134
42a6961c 1135static void dispc_init_fifos(void)
80c39712 1136{
80c39712 1137 u32 size;
42a6961c 1138 int fifo;
a0acb557 1139 u8 start, end;
5ed8cf5b
TV		 1140 u32 unit;
1141
1142 unit = dss_feat_get_buffer_size_unit();
80c39712 1143
a0acb557 1144 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1145
42a6961c
TV		 1146 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1147 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1148 size *= unit;
42a6961c
TV		 1149 dispc.fifo_size[fifo] = size;
1150
1151 /*
1152 * By default fifos are mapped directly to overlays, fifo 0 to
1153 * ovl 0, fifo 1 to ovl 1, etc.
1154 */
1155 dispc.fifo_assignment[fifo] = fifo;
80c39712 1156 }
66a0f9e4
TV		 1157
1158 /*
1159 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1160 * causes problems with certain use cases, like using the tiler in 2D
1161 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1162 * giving GFX plane a larger fifo. WB but should work fine with a
1163 * smaller fifo.
1164 */
1165 if (dispc.feat->gfx_fifo_workaround) {
1166 u32 v;
1167
1168 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1169
1170 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1171 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1172 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1173 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1174
1175 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1176
1177 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1178 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1179 }
80c39712
TV		 1180}
1181
83fa2f2e 1182static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1183{
42a6961c
TV		 1184 int fifo;
1185 u32 size = 0;
1186
1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1188 if (dispc.fifo_assignment[fifo] == plane)
1189 size += dispc.fifo_size[fifo];
1190 }
1191
1192 return size;
80c39712
TV		 1193}
1194
6f04e1bf 1195void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1196{
a0acb557 1197 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1198 u32 unit;
1199
1200 unit = dss_feat_get_buffer_size_unit();
1201
1202 WARN_ON(low % unit != 0);
1203 WARN_ON(high % unit != 0);
1204
1205 low /= unit;
1206 high /= unit;
a0acb557 1207
9b372c2d
AT		 1208 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1209 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1210
3cb5d966 1211 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1212 plane,
9b372c2d 1213 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1214 lo_start, lo_end) * unit,
9b372c2d 1215 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1216 hi_start, hi_end) * unit,
1217 low * unit, high * unit);
80c39712 1218
9b372c2d 1219 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1220 FLD_VAL(high, hi_start, hi_end) |
1221 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1222}
1223
1224void dispc_enable_fifomerge(bool enable)
1225{
e6b0f884
TV		 1226 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1227 WARN_ON(enable);
1228 return;
1229 }
1230
80c39712
TV		 1231 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1232 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1233}
1234
83fa2f2e 1235void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1236 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1237 bool manual_update)
83fa2f2e
TV		 1238{
1239 /*
1240 * All sizes are in bytes. Both the buffer and burst are made of
1241 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1242 */
1243
1244 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1245 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1246 int i;
83fa2f2e
TV		 1247
1248 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1249 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1250
e0e405b9
TV		 1251 if (use_fifomerge) {
1252 total_fifo_size = 0;
392faa0e 1253 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1254 total_fifo_size += dispc_ovl_get_fifo_size(i);
1255 } else {
1256 total_fifo_size = ovl_fifo_size;
1257 }
1258
1259 /*
1260 * We use the same low threshold for both fifomerge and non-fifomerge
1261 * cases, but for fifomerge we calculate the high threshold using the
1262 * combined fifo size
1263 */
1264
3568f2a4 1265 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1266 *fifo_low = ovl_fifo_size - burst_size * 2;
1267 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1268 } else if (plane == OMAP_DSS_WB) {
1269 /*
1270 * Most optimal configuration for writeback is to push out data
1271 * to the interconnect the moment writeback pushes enough pixels
1272 * in the FIFO to form a burst
1273 */
1274 *fifo_low = 0;
1275 *fifo_high = burst_size;
e0e405b9
TV		 1276 } else {
1277 *fifo_low = ovl_fifo_size - burst_size;
1278 *fifo_high = total_fifo_size - buf_unit;
1279 }
83fa2f2e
TV		 1280}
1281
f0e5caab 1282static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1283 int hinc, int vinc,
1284 enum omap_color_component color_comp)
80c39712
TV		 1285{
1286 u32 val;
80c39712 1287
0d66cbb5
AJ		 1288 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1289 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1290
0d66cbb5
AJ		 1291 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1292 &hinc_start, &hinc_end);
1293 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1294 &vinc_start, &vinc_end);
1295 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1296 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1297
0d66cbb5
AJ		 1298 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1299 } else {
1300 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1301 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1302 }
80c39712
TV		 1303}
1304
f0e5caab 1305static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1306{
1307 u32 val;
87a7484b 1308 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1309
87a7484b
AT		 1310 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1311 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1312
1313 val = FLD_VAL(vaccu, vert_start, vert_end) |
1314 FLD_VAL(haccu, hor_start, hor_end);
1315
9b372c2d 1316 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1317}
1318
f0e5caab 1319static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1320{
1321 u32 val;
87a7484b 1322 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1323
87a7484b
AT		 1324 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1325 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1326
1327 val = FLD_VAL(vaccu, vert_start, vert_end) |
1328 FLD_VAL(haccu, hor_start, hor_end);
1329
9b372c2d 1330 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1331}
1332
f0e5caab
TV		 1333static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1334 int vaccu)
ab5ca071
AJ		 1335{
1336 u32 val;
1337
1338 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1339 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1340}
1341
f0e5caab
TV		 1342static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1343 int vaccu)
ab5ca071
AJ		 1344{
1345 u32 val;
1346
1347 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1348 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1349}
80c39712 1350
f0e5caab 1351static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1352 u16 orig_width, u16 orig_height,
1353 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1354 bool five_taps, u8 rotation,
1355 enum omap_color_component color_comp)
80c39712 1356{
0d66cbb5 1357 int fir_hinc, fir_vinc;
80c39712 1358
ed14a3ce
AJ		 1359 fir_hinc = 1024 * orig_width / out_width;
1360 fir_vinc = 1024 * orig_height / out_height;
80c39712 1361
debd9074
CM		 1362 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1363 color_comp);
f0e5caab 1364 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1365}
1366
05dd0f53
CM		 1367static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1368 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1369 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1370{
1371 int h_accu2_0, h_accu2_1;
1372 int v_accu2_0, v_accu2_1;
1373 int chroma_hinc, chroma_vinc;
1374 int idx;
1375
1376 struct accu {
1377 s8 h0_m, h0_n;
1378 s8 h1_m, h1_n;
1379 s8 v0_m, v0_n;
1380 s8 v1_m, v1_n;
1381 };
1382
1383 const struct accu *accu_table;
1384 const struct accu *accu_val;
1385
1386 static const struct accu accu_nv12[4] = {
1387 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1388 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1389 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1390 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1391 };
1392
1393 static const struct accu accu_nv12_ilace[4] = {
1394 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1395 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1396 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1397 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1398 };
1399
1400 static const struct accu accu_yuv[4] = {
1401 { 0, 1, 0, 1, 0, 1, 0, 1 },
1402 { 0, 1, 0, 1, 0, 1, 0, 1 },
1403 { -1, 1, 0, 1, 0, 1, 0, 1 },
1404 { 0, 1, 0, 1, -1, 1, 0, 1 },
1405 };
1406
1407 switch (rotation) {
1408 case OMAP_DSS_ROT_0:
1409 idx = 0;
1410 break;
1411 case OMAP_DSS_ROT_90:
1412 idx = 1;
1413 break;
1414 case OMAP_DSS_ROT_180:
1415 idx = 2;
1416 break;
1417 case OMAP_DSS_ROT_270:
1418 idx = 3;
1419 break;
1420 default:
1421 BUG();
c6eee968 1422 return;
05dd0f53
CM		 1423 }
1424
1425 switch (color_mode) {
1426 case OMAP_DSS_COLOR_NV12:
1427 if (ilace)
1428 accu_table = accu_nv12_ilace;
1429 else
1430 accu_table = accu_nv12;
1431 break;
1432 case OMAP_DSS_COLOR_YUV2:
1433 case OMAP_DSS_COLOR_UYVY:
1434 accu_table = accu_yuv;
1435 break;
1436 default:
1437 BUG();
c6eee968 1438 return;
05dd0f53
CM		 1439 }
1440
1441 accu_val = &accu_table[idx];
1442
1443 chroma_hinc = 1024 * orig_width / out_width;
1444 chroma_vinc = 1024 * orig_height / out_height;
1445
1446 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1447 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1448 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1449 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1450
1451 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1452 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1453}
1454
f0e5caab 1455static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1456 u16 orig_width, u16 orig_height,
1457 u16 out_width, u16 out_height,
1458 bool ilace, bool five_taps,
1459 bool fieldmode, enum omap_color_mode color_mode,
1460 u8 rotation)
1461{
1462 int accu0 = 0;
1463 int accu1 = 0;
1464 u32 l;
80c39712 1465
f0e5caab 1466 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1467 out_width, out_height, five_taps,
1468 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1469 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1470
87a7484b
AT		 1471 /* RESIZEENABLE and VERTICALTAPS */
1472 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1473 l |= (orig_width != out_width) ? (1 << 5) : 0;
1474 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1475 l |= five_taps ? (1 << 21) : 0;
80c39712 1476
87a7484b
AT		 1477 /* VRESIZECONF and HRESIZECONF */
1478 if (dss_has_feature(FEAT_RESIZECONF)) {
1479 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1480 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1481 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1482 }
80c39712 1483
87a7484b
AT		 1484 /* LINEBUFFERSPLIT */
1485 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1486 l &= ~(0x1 << 22);
1487 l |= five_taps ? (1 << 22) : 0;
1488 }
80c39712 1489
9b372c2d 1490 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1491
1492 /*
1493 * field 0 = even field = bottom field
1494 * field 1 = odd field = top field
1495 */
1496 if (ilace && !fieldmode) {
1497 accu1 = 0;
0d66cbb5 1498 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1499 if (accu0 >= 1024/2) {
1500 accu1 = 1024/2;
1501 accu0 -= accu1;
1502 }
1503 }
1504
f0e5caab
TV		 1505 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1506 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1507}
1508
f0e5caab 1509static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1510 u16 orig_width, u16 orig_height,
1511 u16 out_width, u16 out_height,
1512 bool ilace, bool five_taps,
1513 bool fieldmode, enum omap_color_mode color_mode,
1514 u8 rotation)
1515{
1516 int scale_x = out_width != orig_width;
1517 int scale_y = out_height != orig_height;
f92afae2 1518 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1519
1520 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1521 return;
1522 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1523 color_mode != OMAP_DSS_COLOR_UYVY &&
1524 color_mode != OMAP_DSS_COLOR_NV12)) {
1525 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1526 if (plane != OMAP_DSS_WB)
1527 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1528 return;
1529 }
36377357
TV		 1530
1531 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1532 out_height, ilace, color_mode, rotation);
1533
0d66cbb5
AJ		 1534 switch (color_mode) {
1535 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1536 if (chroma_upscale) {
1537 /* UV is subsampled by 2 horizontally and vertically */
1538 orig_height >>= 1;
1539 orig_width >>= 1;
1540 } else {
1541 /* UV is downsampled by 2 horizontally and vertically */
1542 orig_height <<= 1;
1543 orig_width <<= 1;
1544 }
1545
0d66cbb5
AJ		 1546 break;
1547 case OMAP_DSS_COLOR_YUV2:
1548 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1549 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1550 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1551 rotation == OMAP_DSS_ROT_180) {
1552 if (chroma_upscale)
1553 /* UV is subsampled by 2 horizontally */
1554 orig_width >>= 1;
1555 else
1556 /* UV is downsampled by 2 horizontally */
1557 orig_width <<= 1;
1558 }
1559
0d66cbb5
AJ		 1560 /* must use FIR for YUV422 if rotated */
1561 if (rotation != OMAP_DSS_ROT_0)
1562 scale_x = scale_y = true;
20fbb50b 1563
0d66cbb5
AJ		 1564 break;
1565 default:
1566 BUG();
c6eee968 1567 return;
0d66cbb5
AJ		 1568 }
1569
1570 if (out_width != orig_width)
1571 scale_x = true;
1572 if (out_height != orig_height)
1573 scale_y = true;
1574
f0e5caab 1575 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1576 out_width, out_height, five_taps,
1577 rotation, DISPC_COLOR_COMPONENT_UV);
1578
2a5561b1
AT		 1579 if (plane != OMAP_DSS_WB)
1580 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1581 (scale_x || scale_y) ? 1 : 0, 8, 8);
1582
0d66cbb5
AJ		 1583 /* set H scaling */
1584 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1585 /* set V scaling */
1586 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1587}
1588
f0e5caab 1589static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1590 u16 orig_width, u16 orig_height,
1591 u16 out_width, u16 out_height,
1592 bool ilace, bool five_taps,
1593 bool fieldmode, enum omap_color_mode color_mode,
1594 u8 rotation)
1595{
1596 BUG_ON(plane == OMAP_DSS_GFX);
1597
f0e5caab 1598 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1599 orig_width, orig_height,
1600 out_width, out_height,
1601 ilace, five_taps,
1602 fieldmode, color_mode,
1603 rotation);
1604
f0e5caab 1605 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1606 orig_width, orig_height,
1607 out_width, out_height,
1608 ilace, five_taps,
1609 fieldmode, color_mode,
1610 rotation);
1611}
1612
f0e5caab 1613static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1614 bool mirroring, enum omap_color_mode color_mode)
1615{
87a7484b
AT		 1616 bool row_repeat = false;
1617 int vidrot = 0;
1618
80c39712
TV		 1619 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1621
1622 if (mirroring) {
1623 switch (rotation) {
1624 case OMAP_DSS_ROT_0:
1625 vidrot = 2;
1626 break;
1627 case OMAP_DSS_ROT_90:
1628 vidrot = 1;
1629 break;
1630 case OMAP_DSS_ROT_180:
1631 vidrot = 0;
1632 break;
1633 case OMAP_DSS_ROT_270:
1634 vidrot = 3;
1635 break;
1636 }
1637 } else {
1638 switch (rotation) {
1639 case OMAP_DSS_ROT_0:
1640 vidrot = 0;
1641 break;
1642 case OMAP_DSS_ROT_90:
1643 vidrot = 1;
1644 break;
1645 case OMAP_DSS_ROT_180:
1646 vidrot = 2;
1647 break;
1648 case OMAP_DSS_ROT_270:
1649 vidrot = 3;
1650 break;
1651 }
1652 }
1653
80c39712 1654 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1655 row_repeat = true;
80c39712 1656 else
87a7484b 1657 row_repeat = false;
80c39712 1658 }
87a7484b 1659
9b372c2d 1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1661 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1662 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1663 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1664}
1665
1666static int color_mode_to_bpp(enum omap_color_mode color_mode)
1667{
1668 switch (color_mode) {
1669 case OMAP_DSS_COLOR_CLUT1:
1670 return 1;
1671 case OMAP_DSS_COLOR_CLUT2:
1672 return 2;
1673 case OMAP_DSS_COLOR_CLUT4:
1674 return 4;
1675 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1676 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1677 return 8;
1678 case OMAP_DSS_COLOR_RGB12U:
1679 case OMAP_DSS_COLOR_RGB16:
1680 case OMAP_DSS_COLOR_ARGB16:
1681 case OMAP_DSS_COLOR_YUV2:
1682 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1683 case OMAP_DSS_COLOR_RGBA16:
1684 case OMAP_DSS_COLOR_RGBX16:
1685 case OMAP_DSS_COLOR_ARGB16_1555:
1686 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1687 return 16;
1688 case OMAP_DSS_COLOR_RGB24P:
1689 return 24;
1690 case OMAP_DSS_COLOR_RGB24U:
1691 case OMAP_DSS_COLOR_ARGB32:
1692 case OMAP_DSS_COLOR_RGBA32:
1693 case OMAP_DSS_COLOR_RGBX32:
1694 return 32;
1695 default:
1696 BUG();
c6eee968 1697 return 0;
80c39712
TV		 1698 }
1699}
1700
1701static s32 pixinc(int pixels, u8 ps)
1702{
1703 if (pixels == 1)
1704 return 1;
1705 else if (pixels > 1)
1706 return 1 + (pixels - 1) * ps;
1707 else if (pixels < 0)
1708 return 1 - (-pixels + 1) * ps;
1709 else
1710 BUG();
c6eee968 1711 return 0;
80c39712
TV		 1712}
1713
1714static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1715 u16 screen_width,
1716 u16 width, u16 height,
1717 enum omap_color_mode color_mode, bool fieldmode,
1718 unsigned int field_offset,
1719 unsigned *offset0, unsigned *offset1,
aed74b55 1720 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1721{
1722 u8 ps;
1723
1724 /* FIXME CLUT formats */
1725 switch (color_mode) {
1726 case OMAP_DSS_COLOR_CLUT1:
1727 case OMAP_DSS_COLOR_CLUT2:
1728 case OMAP_DSS_COLOR_CLUT4:
1729 case OMAP_DSS_COLOR_CLUT8:
1730 BUG();
1731 return;
1732 case OMAP_DSS_COLOR_YUV2:
1733 case OMAP_DSS_COLOR_UYVY:
1734 ps = 4;
1735 break;
1736 default:
1737 ps = color_mode_to_bpp(color_mode) / 8;
1738 break;
1739 }
1740
1741 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1742 width, height);
1743
1744 /*
1745 * field 0 = even field = bottom field
1746 * field 1 = odd field = top field
1747 */
1748 switch (rotation + mirror * 4) {
1749 case OMAP_DSS_ROT_0:
1750 case OMAP_DSS_ROT_180:
1751 /*
1752 * If the pixel format is YUV or UYVY divide the width
1753 * of the image by 2 for 0 and 180 degree rotation.
1754 */
1755 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1756 color_mode == OMAP_DSS_COLOR_UYVY)
1757 width = width >> 1;
1758 case OMAP_DSS_ROT_90:
1759 case OMAP_DSS_ROT_270:
1760 *offset1 = 0;
1761 if (field_offset)
1762 *offset0 = field_offset * screen_width * ps;
1763 else
1764 *offset0 = 0;
1765
aed74b55
CM		 1766 *row_inc = pixinc(1 +
1767 (y_predecim * screen_width - x_predecim * width) +
1768 (fieldmode ? screen_width : 0), ps);
1769 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1770 break;
1771
1772 case OMAP_DSS_ROT_0 + 4:
1773 case OMAP_DSS_ROT_180 + 4:
1774 /* If the pixel format is YUV or UYVY divide the width
1775 * of the image by 2 for 0 degree and 180 degree
1776 */
1777 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1778 color_mode == OMAP_DSS_COLOR_UYVY)
1779 width = width >> 1;
1780 case OMAP_DSS_ROT_90 + 4:
1781 case OMAP_DSS_ROT_270 + 4:
1782 *offset1 = 0;
1783 if (field_offset)
1784 *offset0 = field_offset * screen_width * ps;
1785 else
1786 *offset0 = 0;
aed74b55
CM		 1787 *row_inc = pixinc(1 -
1788 (y_predecim * screen_width + x_predecim * width) -
1789 (fieldmode ? screen_width : 0), ps);
1790 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1791 break;
1792
1793 default:
1794 BUG();
c6eee968 1795 return;
80c39712
TV		 1796 }
1797}
1798
1799static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1800 u16 screen_width,
1801 u16 width, u16 height,
1802 enum omap_color_mode color_mode, bool fieldmode,
1803 unsigned int field_offset,
1804 unsigned *offset0, unsigned *offset1,
aed74b55 1805 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1806{
1807 u8 ps;
1808 u16 fbw, fbh;
1809
1810 /* FIXME CLUT formats */
1811 switch (color_mode) {
1812 case OMAP_DSS_COLOR_CLUT1:
1813 case OMAP_DSS_COLOR_CLUT2:
1814 case OMAP_DSS_COLOR_CLUT4:
1815 case OMAP_DSS_COLOR_CLUT8:
1816 BUG();
1817 return;
1818 default:
1819 ps = color_mode_to_bpp(color_mode) / 8;
1820 break;
1821 }
1822
1823 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1824 width, height);
1825
1826 /* width & height are overlay sizes, convert to fb sizes */
1827
1828 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1829 fbw = width;
1830 fbh = height;
1831 } else {
1832 fbw = height;
1833 fbh = width;
1834 }
1835
1836 /*
1837 * field 0 = even field = bottom field
1838 * field 1 = odd field = top field
1839 */
1840 switch (rotation + mirror * 4) {
1841 case OMAP_DSS_ROT_0:
1842 *offset1 = 0;
1843 if (field_offset)
1844 *offset0 = *offset1 + field_offset * screen_width * ps;
1845 else
1846 *offset0 = *offset1;
aed74b55
CM		 1847 *row_inc = pixinc(1 +
1848 (y_predecim * screen_width - fbw * x_predecim) +
1849 (fieldmode ? screen_width : 0), ps);
1850 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1851 color_mode == OMAP_DSS_COLOR_UYVY)
1852 *pix_inc = pixinc(x_predecim, 2 * ps);
1853 else
1854 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1855 break;
1856 case OMAP_DSS_ROT_90:
1857 *offset1 = screen_width * (fbh - 1) * ps;
1858 if (field_offset)
1859 *offset0 = *offset1 + field_offset * ps;
1860 else
1861 *offset0 = *offset1;
aed74b55
CM		 1862 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1863 y_predecim + (fieldmode ? 1 : 0), ps);
1864 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1865 break;
1866 case OMAP_DSS_ROT_180:
1867 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1868 if (field_offset)
1869 *offset0 = *offset1 - field_offset * screen_width * ps;
1870 else
1871 *offset0 = *offset1;
1872 *row_inc = pixinc(-1 -
aed74b55
CM		 1873 (y_predecim * screen_width - fbw * x_predecim) -
1874 (fieldmode ? screen_width : 0), ps);
1875 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1876 color_mode == OMAP_DSS_COLOR_UYVY)
1877 *pix_inc = pixinc(-x_predecim, 2 * ps);
1878 else
1879 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1880 break;
1881 case OMAP_DSS_ROT_270:
1882 *offset1 = (fbw - 1) * ps;
1883 if (field_offset)
1884 *offset0 = *offset1 - field_offset * ps;
1885 else
1886 *offset0 = *offset1;
aed74b55
CM		 1887 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1888 y_predecim - (fieldmode ? 1 : 0), ps);
1889 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1890 break;
1891
1892 /* mirroring */
1893 case OMAP_DSS_ROT_0 + 4:
1894 *offset1 = (fbw - 1) * ps;
1895 if (field_offset)
1896 *offset0 = *offset1 + field_offset * screen_width * ps;
1897 else
1898 *offset0 = *offset1;
aed74b55 1899 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1900 (fieldmode ? screen_width : 0),
1901 ps);
aed74b55
CM		 1902 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1903 color_mode == OMAP_DSS_COLOR_UYVY)
1904 *pix_inc = pixinc(-x_predecim, 2 * ps);
1905 else
1906 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1907 break;
1908
1909 case OMAP_DSS_ROT_90 + 4:
1910 *offset1 = 0;
1911 if (field_offset)
1912 *offset0 = *offset1 + field_offset * ps;
1913 else
1914 *offset0 = *offset1;
aed74b55
CM		 1915 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1916 y_predecim + (fieldmode ? 1 : 0),
80c39712 1917 ps);
aed74b55 1918 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1919 break;
1920
1921 case OMAP_DSS_ROT_180 + 4:
1922 *offset1 = screen_width * (fbh - 1) * ps;
1923 if (field_offset)
1924 *offset0 = *offset1 - field_offset * screen_width * ps;
1925 else
1926 *offset0 = *offset1;
aed74b55 1927 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1928 (fieldmode ? screen_width : 0),
1929 ps);
aed74b55
CM		 1930 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1931 color_mode == OMAP_DSS_COLOR_UYVY)
1932 *pix_inc = pixinc(x_predecim, 2 * ps);
1933 else
1934 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1935 break;
1936
1937 case OMAP_DSS_ROT_270 + 4:
1938 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1939 if (field_offset)
1940 *offset0 = *offset1 - field_offset * ps;
1941 else
1942 *offset0 = *offset1;
aed74b55
CM		 1943 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1944 y_predecim - (fieldmode ? 1 : 0),
80c39712 1945 ps);
aed74b55 1946 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1947 break;
1948
1949 default:
1950 BUG();
c6eee968 1951 return;
80c39712
TV		 1952 }
1953}
1954
65e006ff
CM		 1955static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1956 enum omap_color_mode color_mode, bool fieldmode,
1957 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1958 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1959{
1960 u8 ps;
1961
1962 switch (color_mode) {
1963 case OMAP_DSS_COLOR_CLUT1:
1964 case OMAP_DSS_COLOR_CLUT2:
1965 case OMAP_DSS_COLOR_CLUT4:
1966 case OMAP_DSS_COLOR_CLUT8:
1967 BUG();
1968 return;
1969 default:
1970 ps = color_mode_to_bpp(color_mode) / 8;
1971 break;
1972 }
1973
1974 DSSDBG("scrw %d, width %d\n", screen_width, width);
1975
1976 /*
1977 * field 0 = even field = bottom field
1978 * field 1 = odd field = top field
1979 */
1980 *offset1 = 0;
1981 if (field_offset)
1982 *offset0 = *offset1 + field_offset * screen_width * ps;
1983 else
1984 *offset0 = *offset1;
1985 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1986 (fieldmode ? screen_width : 0), ps);
1987 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1988 color_mode == OMAP_DSS_COLOR_UYVY)
1989 *pix_inc = pixinc(x_predecim, 2 * ps);
1990 else
1991 *pix_inc = pixinc(x_predecim, ps);
1992}
1993
7faa9233
CM		 1994/*
1995 * This function is used to avoid synclosts in OMAP3, because of some
1996 * undocumented horizontal position and timing related limitations.
1997 */
3e8a6ff2 1998static int check_horiz_timing_omap3(enum omap_plane plane,
81ab95b7 1999 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 2000 u16 width, u16 height, u16 out_width, u16 out_height)
2001{
230edc03 2002 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2003 unsigned long nonactive;
7faa9233
CM		 2004 static const u8 limits[3] = { 8, 10, 20 };
2005 u64 val, blank;
3e8a6ff2
AT		 2006 unsigned long pclk = dispc_plane_pclk_rate(plane);
2007 unsigned long lclk = dispc_plane_lclk_rate(plane);
7faa9233
CM		 2008 int i;
2009
81ab95b7 2010 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2011
2012 i = 0;
2013 if (out_height < height)
2014 i++;
2015 if (out_width < width)
2016 i++;
81ab95b7 2017 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2018 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2019 if (blank <= limits[i])
2020 return -EINVAL;
2021
2022 /*
2023 * Pixel data should be prepared before visible display point starts.
2024 * So, atleast DS-2 lines must have already been fetched by DISPC
2025 * during nonactive - pos_x period.
2026 */
2027 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2028 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2029 val, max(0, ds - 2) * width);
2030 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2031 return -EINVAL;
2032
2033 /*
2034 * All lines need to be refilled during the nonactive period of which
2035 * only one line can be loaded during the active period. So, atleast
2036 * DS - 1 lines should be loaded during nonactive period.
2037 */
2038 val = div_u64((u64)nonactive * lclk, pclk);
2039 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2040 val, max(0, ds - 1) * width);
2041 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2042 return -EINVAL;
2043
2044 return 0;
2045}
2046
8702ee50 2047static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2048 const struct omap_video_timings *mgr_timings, u16 width,
2049 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2050 enum omap_color_mode color_mode)
80c39712 2051{
8b53d991 2052 u32 core_clk = 0;
3e8a6ff2 2053 u64 tmp;
80c39712 2054
7282f1b7
CM		 2055 if (height <= out_height && width <= out_width)
2056 return (unsigned long) pclk;
2057
80c39712 2058 if (height > out_height) {
81ab95b7 2059 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2060
2061 tmp = pclk * height * out_width;
2062 do_div(tmp, 2 * out_height * ppl);
8b53d991 2063 core_clk = tmp;
80c39712 2064
2d9c5597
VS		 2065 if (height > 2 * out_height) {
2066 if (ppl == out_width)
2067 return 0;
2068
80c39712
TV		 2069 tmp = pclk * (height - 2 * out_height) * out_width;
2070 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2071 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2072 }
2073 }
2074
2075 if (width > out_width) {
2076 tmp = pclk * width;
2077 do_div(tmp, out_width);
8b53d991 2078 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2079
2080 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2081 core_clk <<= 1;
80c39712
TV		 2082 }
2083
8b53d991 2084 return core_clk;
80c39712
TV		 2085}
2086
8702ee50 2087static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2088 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2089{
dcbe765b
CM		 2090 if (height > out_height && width > out_width)
2091 return pclk * 4;
2092 else
2093 return pclk * 2;
2094}
2095
8702ee50 2096static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2097 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2098{
2099 unsigned int hf, vf;
2100
2101 /*
2102 * FIXME how to determine the 'A' factor
2103 * for the no downscaling case ?
2104 */
2105
2106 if (width > 3 * out_width)
2107 hf = 4;
2108 else if (width > 2 * out_width)
2109 hf = 3;
2110 else if (width > out_width)
2111 hf = 2;
2112 else
2113 hf = 1;
80c39712
TV		 2114 if (height > out_height)
2115 vf = 2;
2116 else
2117 vf = 1;
2118
dcbe765b
CM		 2119 return pclk * vf * hf;
2120}
2121
8702ee50 2122static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2123 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2124{
8ba85306
AT		 2125 /*
2126 * If the overlay/writeback is in mem to mem mode, there are no
2127 * downscaling limitations with respect to pixel clock, return 1 as
2128 * required core clock to represent that we have sufficient enough
2129 * core clock to do maximum downscaling
2130 */
2131 if (mem_to_mem)
2132 return 1;
2133
dcbe765b
CM		 2134 if (width > out_width)
2135 return DIV_ROUND_UP(pclk, out_width) * width;
2136 else
2137 return pclk;
2138}
2139
3e8a6ff2 2140static int dispc_ovl_calc_scaling_24xx(enum omap_plane plane,
dcbe765b
CM		 2141 const struct omap_video_timings *mgr_timings,
2142 u16 width, u16 height, u16 out_width, u16 out_height,
2143 enum omap_color_mode color_mode, bool *five_taps,
2144 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2145 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2146{
2147 int error;
2148 u16 in_width, in_height;
2149 int min_factor = min(*decim_x, *decim_y);
2150 const int maxsinglelinewidth =
2151 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8702ee50 2152 unsigned long pclk = dispc_plane_pclk_rate(plane);
3e8a6ff2 2153
dcbe765b
CM		 2154 *five_taps = false;
2155
2156 do {
2157 in_height = DIV_ROUND_UP(height, *decim_y);
2158 in_width = DIV_ROUND_UP(width, *decim_x);
8702ee50 2159 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2160 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2161 error = (in_width > maxsinglelinewidth || !*core_clk ||
2162 *core_clk > dispc_core_clk_rate());
2163 if (error) {
2164 if (*decim_x == *decim_y) {
2165 *decim_x = min_factor;
2166 ++*decim_y;
2167 } else {
2168 swap(*decim_x, *decim_y);
2169 if (*decim_x < *decim_y)
2170 ++*decim_x;
2171 }
2172 }
2173 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2174
2175 if (in_width > maxsinglelinewidth) {
2176 DSSERR("Cannot scale max input width exceeded");
2177 return -EINVAL;
2178 }
2179 return 0;
2180}
2181
3e8a6ff2 2182static int dispc_ovl_calc_scaling_34xx(enum omap_plane plane,
dcbe765b
CM		 2183 const struct omap_video_timings *mgr_timings,
2184 u16 width, u16 height, u16 out_width, u16 out_height,
2185 enum omap_color_mode color_mode, bool *five_taps,
2186 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2187 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2188{
2189 int error;
2190 u16 in_width, in_height;
2191 int min_factor = min(*decim_x, *decim_y);
2192 const int maxsinglelinewidth =
2193 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8702ee50 2194 unsigned long pclk = dispc_plane_pclk_rate(plane);
dcbe765b
CM		 2195
2196 do {
2197 in_height = DIV_ROUND_UP(height, *decim_y);
2198 in_width = DIV_ROUND_UP(width, *decim_x);
8702ee50 2199 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
dcbe765b
CM		 2200 in_width, in_height, out_width, out_height, color_mode);
2201
3e8a6ff2
AT		 2202 error = check_horiz_timing_omap3(plane, mgr_timings,
2203 pos_x, in_width, in_height, out_width,
2204 out_height);
dcbe765b
CM		 2205
2206 if (in_width > maxsinglelinewidth)
2207 if (in_height > out_height &&
2208 in_height < out_height * 2)
2209 *five_taps = false;
2210 if (!*five_taps)
8702ee50 2211 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2212 in_height, out_width, out_height,
2213 mem_to_mem);
dcbe765b
CM		 2214
2215 error = (error || in_width > maxsinglelinewidth * 2 ||
2216 (in_width > maxsinglelinewidth && *five_taps) ||
2217 !*core_clk || *core_clk > dispc_core_clk_rate());
2218 if (error) {
2219 if (*decim_x == *decim_y) {
2220 *decim_x = min_factor;
2221 ++*decim_y;
2222 } else {
2223 swap(*decim_x, *decim_y);
2224 if (*decim_x < *decim_y)
2225 ++*decim_x;
2226 }
2227 }
2228 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2229
3e8a6ff2 2230 if (check_horiz_timing_omap3(plane, mgr_timings, pos_x, width, height,
dcbe765b
CM		 2231 out_width, out_height)){
2232 DSSERR("horizontal timing too tight\n");
2233 return -EINVAL;
7282f1b7 2234 }
dcbe765b
CM		 2235
2236 if (in_width > (maxsinglelinewidth * 2)) {
2237 DSSERR("Cannot setup scaling");
2238 DSSERR("width exceeds maximum width possible");
2239 return -EINVAL;
2240 }
2241
2242 if (in_width > maxsinglelinewidth && *five_taps) {
2243 DSSERR("cannot setup scaling with five taps");
2244 return -EINVAL;
2245 }
2246 return 0;
2247}
2248
3e8a6ff2 2249static int dispc_ovl_calc_scaling_44xx(enum omap_plane plane,
dcbe765b
CM		 2250 const struct omap_video_timings *mgr_timings,
2251 u16 width, u16 height, u16 out_width, u16 out_height,
2252 enum omap_color_mode color_mode, bool *five_taps,
2253 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2254 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2255{
2256 u16 in_width, in_width_max;
2257 int decim_x_min = *decim_x;
2258 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2259 const int maxsinglelinewidth =
2260 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2261 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
8702ee50 2262 unsigned long pclk = dispc_plane_pclk_rate(plane);
3e8a6ff2 2263
5d501085
AT		 2264 if (mem_to_mem) {
2265 in_width_max = out_width * maxdownscale;
2266 } else {
8ba85306
AT		 2267 in_width_max = dispc_core_clk_rate() /
2268 DIV_ROUND_UP(pclk, out_width);
5d501085 2269 }
dcbe765b 2270
dcbe765b
CM		 2271 *decim_x = DIV_ROUND_UP(width, in_width_max);
2272
2273 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2274 if (*decim_x > *x_predecim)
2275 return -EINVAL;
2276
2277 do {
2278 in_width = DIV_ROUND_UP(width, *decim_x);
2279 } while (*decim_x <= *x_predecim &&
2280 in_width > maxsinglelinewidth && ++*decim_x);
2281
2282 if (in_width > maxsinglelinewidth) {
2283 DSSERR("Cannot scale width exceeds max line width");
2284 return -EINVAL;
2285 }
2286
8702ee50 2287 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2288 out_width, out_height, mem_to_mem);
dcbe765b 2289 return 0;
80c39712
TV		 2290}
2291
79ad75f2 2292static int dispc_ovl_calc_scaling(enum omap_plane plane,
3e8a6ff2 2293 enum omap_overlay_caps caps,
81ab95b7
AT		 2294 const struct omap_video_timings *mgr_timings,
2295 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2296 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2297 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2298 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2299{
0373cac6 2300 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2301 const int max_decim_limit = 16;
8b53d991 2302 unsigned long core_clk = 0;
dcbe765b 2303 int decim_x, decim_y, ret;
79ad75f2 2304
f95cb5eb
TV		 2305 if (width == out_width && height == out_height)
2306 return 0;
2307
5b54ed3e 2308 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2309 return -EINVAL;
79ad75f2 2310
1c031441
AT		 2311 if (plane == OMAP_DSS_WB) {
2312 *x_predecim = *y_predecim = 1;
2313 } else {
2314 *x_predecim = max_decim_limit;
2315 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2316 dss_has_feature(FEAT_BURST_2D)) ?
2317 2 : max_decim_limit;
2318 }
aed74b55
CM		 2319
2320 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2321 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2322 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2323 color_mode == OMAP_DSS_COLOR_CLUT8) {
2324 *x_predecim = 1;
2325 *y_predecim = 1;
2326 *five_taps = false;
2327 return 0;
2328 }
2329
2330 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2331 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2332
aed74b55 2333 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2334 return -EINVAL;
2335
aed74b55 2336 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2337 return -EINVAL;
2338
3e8a6ff2
AT		 2339 ret = dispc.feat->calc_scaling(plane, mgr_timings, width, height,
2340 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2341 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2342 mem_to_mem);
dcbe765b
CM		 2343 if (ret)
2344 return ret;
79ad75f2 2345
8b53d991
CM		 2346 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2347 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2348
8b53d991 2349 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2350 DSSERR("failed to set up scaling, "
8b53d991
CM		 2351 "required core clk rate = %lu Hz, "
2352 "current core clk rate = %lu Hz\n",
2353 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2354 return -EINVAL;
2355 }
2356
aed74b55
CM		 2357 *x_predecim = decim_x;
2358 *y_predecim = decim_y;
79ad75f2
AT		 2359 return 0;
2360}
2361
84a880fd 2362static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2363 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2364 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2365 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2366 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2367 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2368 bool replication, const struct omap_video_timings *mgr_timings,
2369 bool mem_to_mem)
80c39712 2370{
7282f1b7 2371 bool five_taps = true;
80c39712 2372 bool fieldmode = 0;
79ad75f2 2373 int r, cconv = 0;
80c39712
TV		 2374 unsigned offset0, offset1;
2375 s32 row_inc;
2376 s32 pix_inc;
6be0d73e 2377 u16 frame_width, frame_height;
80c39712 2378 unsigned int field_offset = 0;
84a880fd
AT		 2379 u16 in_height = height;
2380 u16 in_width = width;
aed74b55 2381 int x_predecim = 1, y_predecim = 1;
8050cbe4 2382 bool ilace = mgr_timings->interlace;
e6d80f95 2383
84a880fd 2384 if (paddr == 0)
80c39712
TV		 2385 return -EINVAL;
2386
84a880fd
AT		 2387 out_width = out_width == 0 ? width : out_width;
2388 out_height = out_height == 0 ? height : out_height;
cf073668 2389
84a880fd 2390 if (ilace && height == out_height)
80c39712
TV		 2391 fieldmode = 1;
2392
2393 if (ilace) {
2394 if (fieldmode)
aed74b55 2395 in_height /= 2;
8eeb7019 2396 pos_y /= 2;
aed74b55 2397 out_height /= 2;
80c39712
TV		 2398
2399 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2400 "out_height %d\n", in_height, pos_y,
2401 out_height);
80c39712
TV		 2402 }
2403
84a880fd 2404 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2405 return -EINVAL;
2406
3e8a6ff2 2407 r = dispc_ovl_calc_scaling(plane, caps, mgr_timings, in_width,
84a880fd
AT		 2408 in_height, out_width, out_height, color_mode,
2409 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2410 rotation_type, mem_to_mem);
79ad75f2
AT		 2411 if (r)
2412 return r;
80c39712 2413
aed74b55
CM		 2414 in_width = DIV_ROUND_UP(in_width, x_predecim);
2415 in_height = DIV_ROUND_UP(in_height, y_predecim);
2416
84a880fd
AT		 2417 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2418 color_mode == OMAP_DSS_COLOR_UYVY ||
2419 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2420 cconv = 1;
80c39712
TV		 2421
2422 if (ilace && !fieldmode) {
2423 /*
2424 * when downscaling the bottom field may have to start several
2425 * source lines below the top field. Unfortunately ACCUI
2426 * registers will only hold the fractional part of the offset
2427 * so the integer part must be added to the base address of the
2428 * bottom field.
2429 */
aed74b55 2430 if (!in_height || in_height == out_height)
80c39712
TV		 2431 field_offset = 0;
2432 else
aed74b55 2433 field_offset = in_height / out_height / 2;
80c39712
TV		 2434 }
2435
2436 /* Fields are independent but interleaved in memory. */
2437 if (fieldmode)
2438 field_offset = 1;
2439
c6eee968
TV		 2440 offset0 = 0;
2441 offset1 = 0;
2442 row_inc = 0;
2443 pix_inc = 0;
2444
6be0d73e
AT		 2445 if (plane == OMAP_DSS_WB) {
2446 frame_width = out_width;
2447 frame_height = out_height;
2448 } else {
2449 frame_width = in_width;
2450 frame_height = height;
2451 }
2452
84a880fd 2453 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2454 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2455 color_mode, fieldmode, field_offset,
65e006ff
CM		 2456 &offset0, &offset1, &row_inc, &pix_inc,
2457 x_predecim, y_predecim);
84a880fd 2458 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2459 calc_dma_rotation_offset(rotation, mirror, screen_width,
2460 frame_width, frame_height,
84a880fd 2461 color_mode, fieldmode, field_offset,
aed74b55
CM		 2462 &offset0, &offset1, &row_inc, &pix_inc,
2463 x_predecim, y_predecim);
80c39712 2464 else
84a880fd 2465 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2466 screen_width, frame_width, frame_height,
84a880fd 2467 color_mode, fieldmode, field_offset,
aed74b55
CM		 2468 &offset0, &offset1, &row_inc, &pix_inc,
2469 x_predecim, y_predecim);
80c39712
TV		 2470
2471 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2472 offset0, offset1, row_inc, pix_inc);
2473
84a880fd 2474 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2475
84a880fd 2476 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2477
84a880fd
AT		 2478 dispc_ovl_set_ba0(plane, paddr + offset0);
2479 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2480
84a880fd
AT		 2481 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2482 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2483 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2484 }
2485
f0e5caab
TV		 2486 dispc_ovl_set_row_inc(plane, row_inc);
2487 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2488
84a880fd 2489 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2490 in_height, out_width, out_height);
80c39712 2491
84a880fd 2492 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2493
78b687fc 2494 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2495
5b54ed3e 2496 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2497 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2498 out_height, ilace, five_taps, fieldmode,
84a880fd 2499 color_mode, rotation);
78b687fc 2500 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2501 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2502 }
2503
84a880fd 2504 dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
80c39712 2505
84a880fd
AT		 2506 dispc_ovl_set_zorder(plane, caps, zorder);
2507 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2508 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2509
d79db853 2510 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2511
80c39712
TV		 2512 return 0;
2513}
2514
84a880fd 2515int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2516 bool replication, const struct omap_video_timings *mgr_timings,
2517 bool mem_to_mem)
84a880fd
AT		 2518{
2519 int r;
16bf20c7 2520 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2521 enum omap_channel channel;
2522
2523 channel = dispc_ovl_get_channel_out(plane);
2524
2525 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2526 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2527 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2528 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2529 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2530
16bf20c7 2531 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2532 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2533 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2534 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2535 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2536
2537 return r;
2538}
2539
749feffa 2540int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2541 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2542{
2543 int r;
9e4a0fc7 2544 u32 l;
749feffa
AT		 2545 enum omap_plane plane = OMAP_DSS_WB;
2546 const int pos_x = 0, pos_y = 0;
2547 const u8 zorder = 0, global_alpha = 0;
2548 const bool replication = false;
9e4a0fc7 2549 bool truncation;
749feffa
AT		 2550 int in_width = mgr_timings->x_res;
2551 int in_height = mgr_timings->y_res;
2552 enum omap_overlay_caps caps =
2553 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2554
2555 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2556 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2557 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2558 wi->mirror);
2559
2560 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2561 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2562 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2563 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2564 replication, mgr_timings, mem_to_mem);
2565
2566 switch (wi->color_mode) {
2567 case OMAP_DSS_COLOR_RGB16:
2568 case OMAP_DSS_COLOR_RGB24P:
2569 case OMAP_DSS_COLOR_ARGB16:
2570 case OMAP_DSS_COLOR_RGBA16:
2571 case OMAP_DSS_COLOR_RGB12U:
2572 case OMAP_DSS_COLOR_ARGB16_1555:
2573 case OMAP_DSS_COLOR_XRGB16_1555:
2574 case OMAP_DSS_COLOR_RGBX16:
2575 truncation = true;
2576 break;
2577 default:
2578 truncation = false;
2579 break;
2580 }
2581
2582 /* setup extra DISPC_WB_ATTRIBUTES */
2583 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2584 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2585 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2586 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2587
2588 return r;
2589}
2590
f0e5caab 2591int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2592{
e6d80f95
TV		 2593 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2594
9b372c2d 2595 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2596
2597 return 0;
80c39712
TV		 2598}
2599
04bd8ac1
TV		 2600bool dispc_ovl_enabled(enum omap_plane plane)
2601{
2602 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2603}
2604
b1112249 2605static void dispc_mgr_disable_isr(void *data, u32 mask)
80c39712
TV		 2606{
2607 struct completion *compl = data;
2608 complete(compl);
2609}
2610
f1a813d3 2611void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2612{
efa70b3b
CM		 2613 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2614 /* flush posted write */
2615 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2616}
2617
65398511
TV		 2618bool dispc_mgr_is_enabled(enum omap_channel channel)
2619{
2620 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2621}
2622
b1112249 2623static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
80c39712 2624{
f1a813d3 2625 dispc_mgr_enable(channel, true);
b1112249
TV		 2626}
2627
2628static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
2629{
2630 DECLARE_COMPLETION_ONSTACK(framedone_compl);
80c39712 2631 int r;
2a205f34 2632 u32 irq;
80c39712 2633
b1112249
TV		 2634 if (dispc_mgr_is_enabled(channel) == false)
2635 return;
2a205f34 2636
b1112249
TV		 2637 /*
2638 * When we disable LCD output, we need to wait for FRAMEDONE to know
2639 * that DISPC has finished with the LCD output.
2640 */
80c39712 2641
b1112249 2642 irq = dispc_mgr_get_framedone_irq(channel);
80c39712 2643
b1112249
TV		 2644 r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
2645 irq);
2646 if (r)
2647 DSSERR("failed to register FRAMEDONE isr\n");
80c39712 2648
f1a813d3 2649 dispc_mgr_enable(channel, false);
b1112249
TV		 2650
2651 /* if we couldn't register for framedone, just sleep and exit */
2652 if (r) {
2653 msleep(100);
2654 return;
80c39712
TV		 2655 }
2656
b1112249
TV		 2657 if (!wait_for_completion_timeout(&framedone_compl,
2658 msecs_to_jiffies(100)))
2659 DSSERR("timeout waiting for FRAME DONE\n");
80c39712 2660
b1112249
TV		 2661 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
2662 irq);
2663 if (r)
2664 DSSERR("failed to unregister FRAMEDONE isr\n");
2665}
80c39712 2666
b1112249
TV		 2667static void dispc_digit_out_enable_isr(void *data, u32 mask)
2668{
2669 struct completion *compl = data;
80c39712 2670
b1112249
TV		 2671 /* ignore any sync lost interrupts */
2672 if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
2673 complete(compl);
2674}
2675
2676static void dispc_mgr_enable_digit_out(void)
2677{
2678 DECLARE_COMPLETION_ONSTACK(vsync_compl);
2679 int r;
2680 u32 irq_mask;
2681
2682 if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
2683 return;
2684
2685 /*
2686 * Digit output produces some sync lost interrupts during the first
2687 * frame when enabling. Those need to be ignored, so we register for the
2688 * sync lost irq to prevent the error handler from triggering.
2689 */
2690
2691 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
2692 dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
2693
2694 r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
2695 irq_mask);
2696 if (r) {
2697 DSSERR("failed to register %x isr\n", irq_mask);
2698 return;
80c39712 2699 }
b1112249 2700
f1a813d3 2701 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, true);
b1112249
TV		 2702
2703 /* wait for the first evsync */
2704 if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
2705 DSSERR("timeout waiting for digit out to start\n");
2706
2707 r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
2708 irq_mask);
2709 if (r)
2710 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2711}
2712
b1112249 2713static void dispc_mgr_disable_digit_out(void)
80c39712 2714{
b1112249 2715 DECLARE_COMPLETION_ONSTACK(framedone_compl);
e82b090b
TV		 2716 int r, i;
2717 u32 irq_mask;
2718 int num_irqs;
80c39712 2719
b1112249 2720 if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
80c39712 2721 return;
80c39712 2722
b1112249
TV		 2723 /*
2724 * When we disable the digit output, we need to wait for FRAMEDONE to
15f5e732 2725 * know that DISPC has finished with the output.
b1112249 2726 */
80c39712 2727
15f5e732
TV		 2728 irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
2729 num_irqs = 1;
2730
2731 if (!irq_mask) {
2732 /*
2733 * omap 2/3 don't have framedone irq for TV, so we need to use
2734 * vsyncs for this.
2735 */
2736
b1112249
TV		 2737 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
2738 /*
2739 * We need to wait for both even and odd vsyncs. Note that this
2740 * is not totally reliable, as we could get a vsync interrupt
2741 * before we disable the output, which leads to timeout in the
2742 * wait_for_completion.
2743 */
e82b090b
TV		 2744 num_irqs = 2;
2745 }
2746
b1112249 2747 r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
e82b090b 2748 irq_mask);
80c39712 2749 if (r)
e82b090b 2750 DSSERR("failed to register %x isr\n", irq_mask);
80c39712 2751
f1a813d3 2752 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, false);
b1112249
TV		 2753
2754 /* if we couldn't register the irq, just sleep and exit */
2755 if (r) {
2756 msleep(100);
2757 return;
2758 }
80c39712 2759
e82b090b 2760 for (i = 0; i < num_irqs; ++i) {
b1112249 2761 if (!wait_for_completion_timeout(&framedone_compl,
e82b090b 2762 msecs_to_jiffies(100)))
b1112249 2763 DSSERR("timeout waiting for digit out to stop\n");
e82b090b 2764 }
80c39712 2765
b1112249 2766 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
e82b090b 2767 irq_mask);
80c39712 2768 if (r)
e82b090b 2769 DSSERR("failed to unregister %x isr\n", irq_mask);
b1112249 2770}
80c39712 2771
3a979f8a 2772void dispc_mgr_enable_sync(enum omap_channel channel)
b1112249
TV		 2773{
2774 if (dss_mgr_is_lcd(channel))
2775 dispc_mgr_enable_lcd_out(channel);
2776 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2777 dispc_mgr_enable_digit_out();
2778 else
2779 WARN_ON(1);
80c39712
TV		 2780}
2781
3a979f8a 2782void dispc_mgr_disable_sync(enum omap_channel channel)
a2faee84 2783{
dd88b7a6 2784 if (dss_mgr_is_lcd(channel))
b1112249 2785 dispc_mgr_disable_lcd_out(channel);
a2faee84 2786 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
b1112249 2787 dispc_mgr_disable_digit_out();
a2faee84 2788 else
b1112249 2789 WARN_ON(1);
a2faee84
TV		 2790}
2791
0b23e5b8
AT		 2792void dispc_wb_enable(bool enable)
2793{
916188a4 2794 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2795}
2796
2797bool dispc_wb_is_enabled(void)
2798{
916188a4 2799 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2800}
2801
fb2cec1f 2802static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2803{
6ced40bf
AT		 2804 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2805 return;
2806
80c39712 2807 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2808}
2809
2810void dispc_lcd_enable_signal(bool enable)
2811{
6ced40bf
AT		 2812 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2813 return;
2814
80c39712 2815 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2816}
2817
2818void dispc_pck_free_enable(bool enable)
2819{
6ced40bf
AT		 2820 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2821 return;
2822
80c39712 2823 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2824}
2825
fb2cec1f 2826static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2827{
efa70b3b 2828 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2829}
2830
2831
fb2cec1f 2832static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2833{
d21f43bc 2834 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2835}
2836
2837void dispc_set_loadmode(enum omap_dss_load_mode mode)
2838{
80c39712 2839 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2840}
2841
2842
c64dca40 2843static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2844{
8613b000 2845 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2846}
2847
c64dca40 2848static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2849 enum omap_dss_trans_key_type type,
2850 u32 trans_key)
2851{
efa70b3b 2852 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2853
8613b000 2854 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2855}
2856
c64dca40 2857static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2858{
efa70b3b 2859 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2860}
11354dd5 2861
c64dca40
TV		 2862static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2863 bool enable)
80c39712 2864{
11354dd5 2865 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2866 return;
2867
80c39712
TV		 2868 if (ch == OMAP_DSS_CHANNEL_LCD)
2869 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2870 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2871 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2872}
11354dd5 2873
c64dca40 2874void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2875 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2876{
2877 dispc_mgr_set_default_color(channel, info->default_color);
2878 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2879 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2880 dispc_mgr_enable_alpha_fixed_zorder(channel,
2881 info->partial_alpha_enabled);
2882 if (dss_has_feature(FEAT_CPR)) {
2883 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2884 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2885 }
2886}
80c39712 2887
fb2cec1f 2888static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2889{
2890 int code;
2891
2892 switch (data_lines) {
2893 case 12:
2894 code = 0;
2895 break;
2896 case 16:
2897 code = 1;
2898 break;
2899 case 18:
2900 code = 2;
2901 break;
2902 case 24:
2903 code = 3;
2904 break;
2905 default:
2906 BUG();
2907 return;
2908 }
2909
efa70b3b 2910 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2911}
2912
fb2cec1f 2913static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2914{
2915 u32 l;
569969d6 2916 int gpout0, gpout1;
80c39712
TV		 2917
2918 switch (mode) {
569969d6
AT		 2919 case DSS_IO_PAD_MODE_RESET:
2920 gpout0 = 0;
2921 gpout1 = 0;
80c39712 2922 break;
569969d6
AT		 2923 case DSS_IO_PAD_MODE_RFBI:
2924 gpout0 = 1;
80c39712
TV		 2925 gpout1 = 0;
2926 break;
569969d6
AT		 2927 case DSS_IO_PAD_MODE_BYPASS:
2928 gpout0 = 1;
80c39712
TV		 2929 gpout1 = 1;
2930 break;
80c39712
TV		 2931 default:
2932 BUG();
2933 return;
2934 }
2935
569969d6
AT		 2936 l = dispc_read_reg(DISPC_CONTROL);
2937 l = FLD_MOD(l, gpout0, 15, 15);
2938 l = FLD_MOD(l, gpout1, 16, 16);
2939 dispc_write_reg(DISPC_CONTROL, l);
2940}
2941
fb2cec1f 2942static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2943{
efa70b3b 2944 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2945}
2946
fb2cec1f
TV		 2947void dispc_mgr_set_lcd_config(enum omap_channel channel,
2948 const struct dss_lcd_mgr_config *config)
2949{
2950 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2951
2952 dispc_mgr_enable_stallmode(channel, config->stallmode);
2953 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2954
2955 dispc_mgr_set_clock_div(channel, &config->clock_info);
2956
2957 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2958
2959 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2960
2961 dispc_mgr_set_lcd_type_tft(channel);
2962}
2963
8f366162
AT		 2964static bool _dispc_mgr_size_ok(u16 width, u16 height)
2965{
33b89928
AT		 2966 return width <= dispc.feat->mgr_width_max &&
2967 height <= dispc.feat->mgr_height_max;
8f366162
AT		 2968}
2969
80c39712
TV		 2970static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2971 int vsw, int vfp, int vbp)
2972{
dcbe765b
CM		 2973 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2974 hfp < 1 || hfp > dispc.feat->hp_max ||
2975 hbp < 1 || hbp > dispc.feat->hp_max ||
2976 vsw < 1 || vsw > dispc.feat->sw_max ||
2977 vfp < 0 || vfp > dispc.feat->vp_max ||
2978 vbp < 0 || vbp > dispc.feat->vp_max)
2979 return false;
80c39712
TV		 2980 return true;
2981}
2982
8f366162 2983bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2984 const struct omap_video_timings *timings)
80c39712 2985{
8f366162
AT		 2986 bool timings_ok;
2987
2988 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2989
dd88b7a6 2990 if (dss_mgr_is_lcd(channel))
8f366162
AT		 2991 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2992 timings->hfp, timings->hbp,
2993 timings->vsw, timings->vfp,
2994 timings->vbp);
2995
2996 return timings_ok;
80c39712
TV		 2997}
2998
26d9dd0d 2999static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 3000 int hfp, int hbp, int vsw, int vfp, int vbp,
3001 enum omap_dss_signal_level vsync_level,
3002 enum omap_dss_signal_level hsync_level,
3003 enum omap_dss_signal_edge data_pclk_edge,
3004 enum omap_dss_signal_level de_level,
3005 enum omap_dss_signal_edge sync_pclk_edge)
3006
80c39712 3007{
655e2941
AT		 3008 u32 timing_h, timing_v, l;
3009 bool onoff, rf, ipc;
80c39712 3010
dcbe765b
CM		 3011 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3012 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3013 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3014 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3015 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3016 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3017
64ba4f74
SS		 3018 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3019 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 3020
3021 switch (data_pclk_edge) {
3022 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3023 ipc = false;
3024 break;
3025 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3026 ipc = true;
3027 break;
3028 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
3029 default:
3030 BUG();
3031 }
3032
3033 switch (sync_pclk_edge) {
3034 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
3035 onoff = false;
3036 rf = false;
3037 break;
3038 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3039 onoff = true;
3040 rf = false;
3041 break;
3042 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3043 onoff = true;
3044 rf = true;
3045 break;
3046 default:
3047 BUG();
3048 };
3049
3050 l = dispc_read_reg(DISPC_POL_FREQ(channel));
3051 l |= FLD_VAL(onoff, 17, 17);
3052 l |= FLD_VAL(rf, 16, 16);
3053 l |= FLD_VAL(de_level, 15, 15);
3054 l |= FLD_VAL(ipc, 14, 14);
3055 l |= FLD_VAL(hsync_level, 13, 13);
3056 l |= FLD_VAL(vsync_level, 12, 12);
3057 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3058}
3059
3060/* change name to mode? */
c51d921a 3061void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3062 const struct omap_video_timings *timings)
80c39712
TV		 3063{
3064 unsigned xtot, ytot;
3065 unsigned long ht, vt;
2aefad49 3066 struct omap_video_timings t = *timings;
80c39712 3067
2aefad49 3068 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3069
2aefad49 3070 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3071 BUG();
c6eee968
TV		 3072 return;
3073 }
80c39712 3074
dd88b7a6 3075 if (dss_mgr_is_lcd(channel)) {
2aefad49 3076 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3077 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3078 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3079
2aefad49
AT		 3080 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3081 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3082
c51d921a
AT		 3083 ht = (timings->pixel_clock * 1000) / xtot;
3084 vt = (timings->pixel_clock * 1000) / xtot / ytot;
3085
3086 DSSDBG("pck %u\n", timings->pixel_clock);
3087 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3088 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3089 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3090 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3091 t.de_level, t.sync_pclk_edge);
80c39712 3092
c51d921a 3093 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3094 } else {
23c8f88e 3095 if (t.interlace == true)
2aefad49 3096 t.y_res /= 2;
c51d921a 3097 }
8f366162 3098
2aefad49 3099 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 3100}
3101
26d9dd0d 3102static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3103 u16 pck_div)
80c39712
TV		 3104{
3105 BUG_ON(lck_div < 1);
9eaaf207 3106 BUG_ON(pck_div < 1);
80c39712 3107
ce7fa5eb 3108 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3109 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 3110}
3111
26d9dd0d 3112static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3113 int *pck_div)
80c39712
TV		 3114{
3115 u32 l;
ce7fa5eb 3116 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3117 *lck_div = FLD_GET(l, 23, 16);
3118 *pck_div = FLD_GET(l, 7, 0);
3119}
3120
3121unsigned long dispc_fclk_rate(void)
3122{
a72b64b9 3123 struct platform_device *dsidev;
80c39712
TV		 3124 unsigned long r = 0;
3125
66534e8e 3126 switch (dss_get_dispc_clk_source()) {
89a35e51 3127 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 3128 r = clk_get_rate(dispc.dss_clk);
66534e8e 3129 break;
89a35e51 3130 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3131 dsidev = dsi_get_dsidev_from_id(0);
3132 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 3133 break;
5a8b572d
AT		 3134 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3135 dsidev = dsi_get_dsidev_from_id(1);
3136 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3137 break;
66534e8e
TA		 3138 default:
3139 BUG();
c6eee968 3140 return 0;
66534e8e
TA		 3141 }
3142
80c39712
TV		 3143 return r;
3144}
3145
26d9dd0d 3146unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3147{
a72b64b9 3148 struct platform_device *dsidev;
80c39712
TV		 3149 int lcd;
3150 unsigned long r;
3151 u32 l;
3152
c31cba8a
TV		 3153 if (dss_mgr_is_lcd(channel)) {
3154 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3155
c31cba8a 3156 lcd = FLD_GET(l, 23, 16);
80c39712 3157
c31cba8a
TV		 3158 switch (dss_get_lcd_clk_source(channel)) {
3159 case OMAP_DSS_CLK_SRC_FCK:
3160 r = clk_get_rate(dispc.dss_clk);
3161 break;
3162 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3163 dsidev = dsi_get_dsidev_from_id(0);
3164 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3165 break;
3166 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3167 dsidev = dsi_get_dsidev_from_id(1);
3168 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3169 break;
3170 default:
3171 BUG();
3172 return 0;
3173 }
80c39712 3174
c31cba8a
TV		 3175 return r / lcd;
3176 } else {
3177 return dispc_fclk_rate();
3178 }
80c39712
TV		 3179}
3180
26d9dd0d 3181unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3182{
80c39712 3183 unsigned long r;
80c39712 3184
dd88b7a6 3185 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3186 int pcd;
3187 u32 l;
80c39712 3188
c3dc6a7a 3189 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3190
c3dc6a7a 3191 pcd = FLD_GET(l, 7, 0);
80c39712 3192
c3dc6a7a
AT		 3193 r = dispc_mgr_lclk_rate(channel);
3194
3195 return r / pcd;
3196 } else {
3fa03ba8 3197 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 3198
3fa03ba8
AT		 3199 source = dss_get_hdmi_venc_clk_source();
3200
3201 switch (source) {
3202 case DSS_VENC_TV_CLK:
c3dc6a7a 3203 return venc_get_pixel_clock();
3fa03ba8 3204 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 3205 return hdmi_get_pixel_clock();
3206 default:
3207 BUG();
c6eee968 3208 return 0;
c3dc6a7a
AT		 3209 }
3210 }
80c39712
TV		 3211}
3212
8b53d991
CM		 3213unsigned long dispc_core_clk_rate(void)
3214{
3215 int lcd;
3216 unsigned long fclk = dispc_fclk_rate();
3217
3218 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3219 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3220 else
3221 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3222
3223 return fclk / lcd;
3224}
3225
3e8a6ff2
AT		 3226static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3227{
251886d8
TV		 3228 enum omap_channel channel;
3229
3230 if (plane == OMAP_DSS_WB)
3231 return 0;
3232
3233 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3234
3235 return dispc_mgr_pclk_rate(channel);
3236}
3237
3238static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3239{
251886d8
TV		 3240 enum omap_channel channel;
3241
3242 if (plane == OMAP_DSS_WB)
3243 return 0;
3244
3245 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3246
c31cba8a 3247 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3248}
c31cba8a 3249
6f1891fc 3250static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3251{
3252 int lcd, pcd;
6f1891fc
CM		 3253 enum omap_dss_clk_source lcd_clk_src;
3254
3255 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3256
3257 lcd_clk_src = dss_get_lcd_clk_source(channel);
3258
3259 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3260 dss_get_generic_clk_source_name(lcd_clk_src),
3261 dss_feat_get_clk_source_name(lcd_clk_src));
3262
3263 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3264
3265 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3266 dispc_mgr_lclk_rate(channel), lcd);
3267 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3268 dispc_mgr_pclk_rate(channel), pcd);
3269}
3270
3271void dispc_dump_clocks(struct seq_file *s)
3272{
3273 int lcd;
0cf35df3 3274 u32 l;
89a35e51 3275 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3276
4fbafaf3
TV		 3277 if (dispc_runtime_get())
3278 return;
80c39712 3279
80c39712
TV		 3280 seq_printf(s, "- DISPC -\n");
3281
067a57e4
AT		 3282 seq_printf(s, "dispc fclk source = %s (%s)\n",
3283 dss_get_generic_clk_source_name(dispc_clk_src),
3284 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3285
3286 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3287
0cf35df3
MR		 3288 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3289 seq_printf(s, "- DISPC-CORE-CLK -\n");
3290 l = dispc_read_reg(DISPC_DIVISOR);
3291 lcd = FLD_GET(l, 23, 16);
3292
3293 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3294 (dispc_fclk_rate()/lcd), lcd);
3295 }
2a205f34 3296
6f1891fc 3297 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3298
6f1891fc
CM		 3299 if (dss_has_feature(FEAT_MGR_LCD2))
3300 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3301 if (dss_has_feature(FEAT_MGR_LCD3))
3302 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3303
3304 dispc_runtime_put();
80c39712
TV		 3305}
3306
dfc0fd8d 3307#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5b30b7fb 3308static void dispc_dump_irqs(struct seq_file *s)
dfc0fd8d
TV		 3309{
3310 unsigned long flags;
3311 struct dispc_irq_stats stats;
3312
3313 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3314
3315 stats = dispc.irq_stats;
3316 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3317 dispc.irq_stats.last_reset = jiffies;
3318
3319 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3320
3321 seq_printf(s, "period %u ms\n",
3322 jiffies_to_msecs(jiffies - stats.last_reset));
3323
3324 seq_printf(s, "irqs %d\n", stats.irq_count);
3325#define PIS(x) \
3326 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3327
3328 PIS(FRAMEDONE);
3329 PIS(VSYNC);
3330 PIS(EVSYNC_EVEN);
3331 PIS(EVSYNC_ODD);
3332 PIS(ACBIAS_COUNT_STAT);
3333 PIS(PROG_LINE_NUM);
3334 PIS(GFX_FIFO_UNDERFLOW);
3335 PIS(GFX_END_WIN);
3336 PIS(PAL_GAMMA_MASK);
3337 PIS(OCP_ERR);
3338 PIS(VID1_FIFO_UNDERFLOW);
3339 PIS(VID1_END_WIN);
3340 PIS(VID2_FIFO_UNDERFLOW);
3341 PIS(VID2_END_WIN);
b8c095b4
AT		 3342 if (dss_feat_get_num_ovls() > 3) {
3343 PIS(VID3_FIFO_UNDERFLOW);
3344 PIS(VID3_END_WIN);
3345 }
dfc0fd8d
TV		 3346 PIS(SYNC_LOST);
3347 PIS(SYNC_LOST_DIGIT);
3348 PIS(WAKEUP);
2a205f34
SS		 3349 if (dss_has_feature(FEAT_MGR_LCD2)) {
3350 PIS(FRAMEDONE2);
3351 PIS(VSYNC2);
3352 PIS(ACBIAS_COUNT_STAT2);
3353 PIS(SYNC_LOST2);
3354 }
6f1891fc
CM		 3355 if (dss_has_feature(FEAT_MGR_LCD3)) {
3356 PIS(FRAMEDONE3);
3357 PIS(VSYNC3);
3358 PIS(ACBIAS_COUNT_STAT3);
3359 PIS(SYNC_LOST3);
3360 }
dfc0fd8d
TV		 3361#undef PIS
3362}
dfc0fd8d
TV		 3363#endif
3364
e40402cf 3365static void dispc_dump_regs(struct seq_file *s)
80c39712 3366{
4dd2da15
AT		 3367 int i, j;
3368 const char *mgr_names[] = {
3369 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3370 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3371 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3372 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3373 };
3374 const char *ovl_names[] = {
3375 [OMAP_DSS_GFX] = "GFX",
3376 [OMAP_DSS_VIDEO1] = "VID1",
3377 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3378 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3379 };
3380 const char **p_names;
3381
9b372c2d 3382#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3383
4fbafaf3
TV		 3384 if (dispc_runtime_get())
3385 return;
80c39712 3386
5010be80 3387 /* DISPC common registers */
80c39712
TV		 3388 DUMPREG(DISPC_REVISION);
3389 DUMPREG(DISPC_SYSCONFIG);
3390 DUMPREG(DISPC_SYSSTATUS);
3391 DUMPREG(DISPC_IRQSTATUS);
3392 DUMPREG(DISPC_IRQENABLE);
3393 DUMPREG(DISPC_CONTROL);
3394 DUMPREG(DISPC_CONFIG);
3395 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3396 DUMPREG(DISPC_LINE_STATUS);
3397 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3398 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3399 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3400 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3401 if (dss_has_feature(FEAT_MGR_LCD2)) {
3402 DUMPREG(DISPC_CONTROL2);
3403 DUMPREG(DISPC_CONFIG2);
5010be80 3404 }
6f1891fc
CM		 3405 if (dss_has_feature(FEAT_MGR_LCD3)) {
3406 DUMPREG(DISPC_CONTROL3);
3407 DUMPREG(DISPC_CONFIG3);
3408 }
5010be80
AT		 3409
3410#undef DUMPREG
3411
3412#define DISPC_REG(i, name) name(i)
4dd2da15 3413#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3414 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3415 dispc_read_reg(DISPC_REG(i, r)))
3416
4dd2da15 3417 p_names = mgr_names;
5010be80 3418
4dd2da15
AT		 3419 /* DISPC channel specific registers */
3420 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3421 DUMPREG(i, DISPC_DEFAULT_COLOR);
3422 DUMPREG(i, DISPC_TRANS_COLOR);
3423 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3424
4dd2da15
AT		 3425 if (i == OMAP_DSS_CHANNEL_DIGIT)
3426 continue;
5010be80 3427
4dd2da15
AT		 3428 DUMPREG(i, DISPC_DEFAULT_COLOR);
3429 DUMPREG(i, DISPC_TRANS_COLOR);
3430 DUMPREG(i, DISPC_TIMING_H);
3431 DUMPREG(i, DISPC_TIMING_V);
3432 DUMPREG(i, DISPC_POL_FREQ);
3433 DUMPREG(i, DISPC_DIVISORo);
3434 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3435
4dd2da15
AT		 3436 DUMPREG(i, DISPC_DATA_CYCLE1);
3437 DUMPREG(i, DISPC_DATA_CYCLE2);
3438 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3439
332e9d70 3440 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3441 DUMPREG(i, DISPC_CPR_COEF_R);
3442 DUMPREG(i, DISPC_CPR_COEF_G);
3443 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3444 }
2a205f34 3445 }
80c39712 3446
4dd2da15
AT		 3447 p_names = ovl_names;
3448
3449 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3450 DUMPREG(i, DISPC_OVL_BA0);
3451 DUMPREG(i, DISPC_OVL_BA1);
3452 DUMPREG(i, DISPC_OVL_POSITION);
3453 DUMPREG(i, DISPC_OVL_SIZE);
3454 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3455 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3456 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3457 DUMPREG(i, DISPC_OVL_ROW_INC);
3458 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3459 if (dss_has_feature(FEAT_PRELOAD))
3460 DUMPREG(i, DISPC_OVL_PRELOAD);
3461
3462 if (i == OMAP_DSS_GFX) {
3463 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3464 DUMPREG(i, DISPC_OVL_TABLE_BA);
3465 continue;
3466 }
3467
3468 DUMPREG(i, DISPC_OVL_FIR);
3469 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3470 DUMPREG(i, DISPC_OVL_ACCU0);
3471 DUMPREG(i, DISPC_OVL_ACCU1);
3472 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3473 DUMPREG(i, DISPC_OVL_BA0_UV);
3474 DUMPREG(i, DISPC_OVL_BA1_UV);
3475 DUMPREG(i, DISPC_OVL_FIR2);
3476 DUMPREG(i, DISPC_OVL_ACCU2_0);
3477 DUMPREG(i, DISPC_OVL_ACCU2_1);
3478 }
3479 if (dss_has_feature(FEAT_ATTR2))
3480 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3481 if (dss_has_feature(FEAT_PRELOAD))
3482 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3483 }
5010be80
AT		 3484
3485#undef DISPC_REG
3486#undef DUMPREG
3487
3488#define DISPC_REG(plane, name, i) name(plane, i)
3489#define DUMPREG(plane, name, i) \
4dd2da15 3490 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3491 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3492 dispc_read_reg(DISPC_REG(plane, name, i)))
3493
4dd2da15 3494 /* Video pipeline coefficient registers */
332e9d70 3495
4dd2da15
AT		 3496 /* start from OMAP_DSS_VIDEO1 */
3497 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3498 for (j = 0; j < 8; j++)
3499 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3500
4dd2da15
AT		 3501 for (j = 0; j < 8; j++)
3502 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3503
4dd2da15
AT		 3504 for (j = 0; j < 5; j++)
3505 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3506
4dd2da15
AT		 3507 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3508 for (j = 0; j < 8; j++)
3509 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3510 }
3511
3512 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3513 for (j = 0; j < 8; j++)
3514 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3515
3516 for (j = 0; j < 8; j++)
3517 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3518
3519 for (j = 0; j < 8; j++)
3520 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3521 }
332e9d70 3522 }
80c39712 3523
4fbafaf3 3524 dispc_runtime_put();
5010be80
AT		 3525
3526#undef DISPC_REG
80c39712
TV		 3527#undef DUMPREG
3528}
3529
80c39712 3530/* with fck as input clock rate, find dispc dividers that produce req_pck */
6d523e7b 3531void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
80c39712
TV		 3532 struct dispc_clock_info *cinfo)
3533{
9eaaf207 3534 u16 pcd_min, pcd_max;
80c39712
TV		 3535 unsigned long best_pck;
3536 u16 best_ld, cur_ld;
3537 u16 best_pd, cur_pd;
3538
9eaaf207
TV		 3539 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3540 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3541
80c39712
TV		 3542 best_pck = 0;
3543 best_ld = 0;
3544 best_pd = 0;
3545
3546 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3547 unsigned long lck = fck / cur_ld;
3548
9eaaf207 3549 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3550 unsigned long pck = lck / cur_pd;
3551 long old_delta = abs(best_pck - req_pck);
3552 long new_delta = abs(pck - req_pck);
3553
3554 if (best_pck == 0 || new_delta < old_delta) {
3555 best_pck = pck;
3556 best_ld = cur_ld;
3557 best_pd = cur_pd;
3558
3559 if (pck == req_pck)
3560 goto found;
3561 }
3562
3563 if (pck < req_pck)
3564 break;
3565 }
3566
3567 if (lck / pcd_min < req_pck)
3568 break;
3569 }
3570
3571found:
3572 cinfo->lck_div = best_ld;
3573 cinfo->pck_div = best_pd;
3574 cinfo->lck = fck / cinfo->lck_div;
3575 cinfo->pck = cinfo->lck / cinfo->pck_div;
3576}
3577
3578/* calculate clock rates using dividers in cinfo */
3579int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3580 struct dispc_clock_info *cinfo)
3581{
3582 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3583 return -EINVAL;
9eaaf207 3584 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3585 return -EINVAL;
3586
3587 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3588 cinfo->pck = cinfo->lck / cinfo->pck_div;
3589
3590 return 0;
3591}
3592
f0d08f89 3593void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3594 const struct dispc_clock_info *cinfo)
80c39712
TV		 3595{
3596 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3597 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3598
26d9dd0d 3599 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3600}
3601
26d9dd0d 3602int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3603 struct dispc_clock_info *cinfo)
80c39712
TV		 3604{
3605 unsigned long fck;
3606
3607 fck = dispc_fclk_rate();
3608
ce7fa5eb
MR		 3609 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3610 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3611
3612 cinfo->lck = fck / cinfo->lck_div;
3613 cinfo->pck = cinfo->lck / cinfo->pck_div;
3614
3615 return 0;
3616}
3617
4e0397cf
TV		 3618u32 dispc_read_irqstatus(void)
3619{
3620 return dispc_read_reg(DISPC_IRQSTATUS);
3621}
3622
3623void dispc_clear_irqstatus(u32 mask)
3624{
3625 dispc_write_reg(DISPC_IRQSTATUS, mask);
3626}
3627
3628u32 dispc_read_irqenable(void)
3629{
3630 return dispc_read_reg(DISPC_IRQENABLE);
3631}
3632
3633void dispc_write_irqenable(u32 mask)
3634{
3635 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3636
3637 /* clear the irqstatus for newly enabled irqs */
3638 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3639
3640 dispc_write_reg(DISPC_IRQENABLE, mask);
3641}
3642
80c39712
TV		 3643/* dispc.irq_lock has to be locked by the caller */
3644static void _omap_dispc_set_irqs(void)
3645{
3646 u32 mask;
80c39712
TV		 3647 int i;
3648 struct omap_dispc_isr_data *isr_data;
3649
3650 mask = dispc.irq_error_mask;
3651
3652 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3653 isr_data = &dispc.registered_isr[i];
3654
3655 if (isr_data->isr == NULL)
3656 continue;
3657
3658 mask |= isr_data->mask;
3659 }
3660
4e0397cf 3661 dispc_write_irqenable(mask);
80c39712
TV		 3662}
3663
3664int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3665{
3666 int i;
3667 int ret;
3668 unsigned long flags;
3669 struct omap_dispc_isr_data *isr_data;
3670
3671 if (isr == NULL)
3672 return -EINVAL;
3673
3674 spin_lock_irqsave(&dispc.irq_lock, flags);
3675
3676 /* check for duplicate entry */
3677 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3678 isr_data = &dispc.registered_isr[i];
3679 if (isr_data->isr == isr && isr_data->arg == arg &&
3680 isr_data->mask == mask) {
3681 ret = -EINVAL;
3682 goto err;
3683 }
3684 }
3685
3686 isr_data = NULL;
3687 ret = -EBUSY;
3688
3689 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3690 isr_data = &dispc.registered_isr[i];
3691
3692 if (isr_data->isr != NULL)
3693 continue;
3694
3695 isr_data->isr = isr;
3696 isr_data->arg = arg;
3697 isr_data->mask = mask;
3698 ret = 0;
3699
3700 break;
3701 }
3702
b9cb0984
TV		 3703 if (ret)
3704 goto err;
3705
80c39712
TV		 3706 _omap_dispc_set_irqs();
3707
3708 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3709
3710 return 0;
3711err:
3712 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3713
3714 return ret;
3715}
3716EXPORT_SYMBOL(omap_dispc_register_isr);
3717
3718int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3719{
3720 int i;
3721 unsigned long flags;
3722 int ret = -EINVAL;
3723 struct omap_dispc_isr_data *isr_data;
3724
3725 spin_lock_irqsave(&dispc.irq_lock, flags);
3726
3727 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3728 isr_data = &dispc.registered_isr[i];
3729 if (isr_data->isr != isr || isr_data->arg != arg ||
3730 isr_data->mask != mask)
3731 continue;
3732
3733 /* found the correct isr */
3734
3735 isr_data->isr = NULL;
3736 isr_data->arg = NULL;
3737 isr_data->mask = 0;
3738
3739 ret = 0;
3740 break;
3741 }
3742
3743 if (ret == 0)
3744 _omap_dispc_set_irqs();
3745
3746 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3747
3748 return ret;
3749}
3750EXPORT_SYMBOL(omap_dispc_unregister_isr);
3751
80c39712
TV		 3752static void print_irq_status(u32 status)
3753{
3754 if ((status & dispc.irq_error_mask) == 0)
3755 return;
3756
f30be7d3
CM		 3757#define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : ""
3758
3759 pr_debug("DISPC IRQ: 0x%x: %s%s%s%s%s%s%s%s%s\n",
3760 status,
3761 PIS(OCP_ERR),
3762 PIS(GFX_FIFO_UNDERFLOW),
3763 PIS(VID1_FIFO_UNDERFLOW),
3764 PIS(VID2_FIFO_UNDERFLOW),
3765 dss_feat_get_num_ovls() > 3 ? PIS(VID3_FIFO_UNDERFLOW) : "",
3766 PIS(SYNC_LOST),
3767 PIS(SYNC_LOST_DIGIT),
3768 dss_has_feature(FEAT_MGR_LCD2) ? PIS(SYNC_LOST2) : "",
3769 dss_has_feature(FEAT_MGR_LCD3) ? PIS(SYNC_LOST3) : "");
80c39712 3770#undef PIS
80c39712 3771}
80c39712
TV		 3772
3773/* Called from dss.c. Note that we don't touch clocks here,
3774 * but we presume they are on because we got an IRQ. However,
3775 * an irq handler may turn the clocks off, so we may not have
3776 * clock later in the function. */
affe360d 3777static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3778{
3779 int i;
affe360d 3780 u32 irqstatus, irqenable;
80c39712
TV		 3781 u32 handledirqs = 0;
3782 u32 unhandled_errors;
3783 struct omap_dispc_isr_data *isr_data;
3784 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3785
3786 spin_lock(&dispc.irq_lock);
3787
4e0397cf
TV		 3788 irqstatus = dispc_read_irqstatus();
3789 irqenable = dispc_read_irqenable();
affe360d 3790
3791 /* IRQ is not for us */
3792 if (!(irqstatus & irqenable)) {
3793 spin_unlock(&dispc.irq_lock);
3794 return IRQ_NONE;
3795 }
80c39712 3796
dfc0fd8d
TV		 3797#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3798 spin_lock(&dispc.irq_stats_lock);
3799 dispc.irq_stats.irq_count++;
3800 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3801 spin_unlock(&dispc.irq_stats_lock);
3802#endif
3803
28bcd199
CM		 3804 print_irq_status(irqstatus);
3805
80c39712
TV		 3806 /* Ack the interrupt. Do it here before clocks are possibly turned
3807 * off */
4e0397cf 3808 dispc_clear_irqstatus(irqstatus);
80c39712 3809 /* flush posted write */
4e0397cf 3810 dispc_read_irqstatus();
80c39712
TV		 3811
3812 /* make a copy and unlock, so that isrs can unregister
3813 * themselves */
3814 memcpy(registered_isr, dispc.registered_isr,
3815 sizeof(registered_isr));
3816
3817 spin_unlock(&dispc.irq_lock);
3818
3819 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3820 isr_data = &registered_isr[i];
3821
3822 if (!isr_data->isr)
3823 continue;
3824
3825 if (isr_data->mask & irqstatus) {
3826 isr_data->isr(isr_data->arg, irqstatus);
3827 handledirqs |= isr_data->mask;
3828 }
3829 }
3830
3831 spin_lock(&dispc.irq_lock);
3832
3833 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3834
3835 if (unhandled_errors) {
3836 dispc.error_irqs |= unhandled_errors;
3837
3838 dispc.irq_error_mask &= ~unhandled_errors;
3839 _omap_dispc_set_irqs();
3840
3841 schedule_work(&dispc.error_work);
3842 }
3843
3844 spin_unlock(&dispc.irq_lock);
affe360d 3845
3846 return IRQ_HANDLED;
80c39712
TV		 3847}
3848
3849static void dispc_error_worker(struct work_struct *work)
3850{
3851 int i;
3852 u32 errors;
3853 unsigned long flags;
fe3cc9d6
TV		 3854 static const unsigned fifo_underflow_bits[] = {
3855 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3856 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3857 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3858 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3859 };
3860
80c39712
TV		 3861 spin_lock_irqsave(&dispc.irq_lock, flags);
3862 errors = dispc.error_irqs;
3863 dispc.error_irqs = 0;
3864 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3865
13eae1f9
DZ		 3866 dispc_runtime_get();
3867
fe3cc9d6
TV		 3868 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3869 struct omap_overlay *ovl;
3870 unsigned bit;
80c39712 3871
fe3cc9d6
TV		 3872 ovl = omap_dss_get_overlay(i);
3873 bit = fifo_underflow_bits[i];
80c39712 3874
fe3cc9d6
TV		 3875 if (bit & errors) {
3876 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3877 ovl->name);
f0e5caab 3878 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3879 dispc_mgr_go(ovl->manager->id);
d7ad718d 3880 msleep(50);
80c39712
TV		 3881 }
3882 }
3883
fe3cc9d6
TV		 3884 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3885 struct omap_overlay_manager *mgr;
3886 unsigned bit;
80c39712 3887
fe3cc9d6 3888 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3889 bit = mgr_desc[i].sync_lost_irq;
80c39712 3890
fe3cc9d6 3891 if (bit & errors) {
4c6c65b0 3892 int j;
80c39712 3893
fe3cc9d6
TV		 3894 DSSERR("SYNC_LOST on channel %s, restarting the output "
3895 "with video overlays disabled\n",
3896 mgr->name);
2a205f34 3897
b276dd09 3898 dss_mgr_disable(mgr);
2a205f34 3899
4c6c65b0 3900 for (j = 0; j < omap_dss_get_num_overlays(); ++j) {
2a205f34 3901 struct omap_overlay *ovl;
4c6c65b0 3902 ovl = omap_dss_get_overlay(j);
2a205f34 3903
fe3cc9d6
TV		 3904 if (ovl->id != OMAP_DSS_GFX &&
3905 ovl->manager == mgr)
b276dd09 3906 ovl->disable(ovl);
2a205f34
SS		 3907 }
3908
b276dd09 3909 dss_mgr_enable(mgr);
2a205f34
SS		 3910 }
3911 }
3912
80c39712
TV		 3913 if (errors & DISPC_IRQ_OCP_ERR) {
3914 DSSERR("OCP_ERR\n");
3915 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3916 struct omap_overlay_manager *mgr;
794bc4ee 3917
80c39712 3918 mgr = omap_dss_get_overlay_manager(i);
b276dd09 3919 dss_mgr_disable(mgr);
80c39712
TV		 3920 }
3921 }
3922
3923 spin_lock_irqsave(&dispc.irq_lock, flags);
3924 dispc.irq_error_mask |= errors;
3925 _omap_dispc_set_irqs();
3926 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3927
3928 dispc_runtime_put();
80c39712
TV		 3929}
3930
3931int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3932{
3933 void dispc_irq_wait_handler(void *data, u32 mask)
3934 {
3935 complete((struct completion *)data);
3936 }
3937
3938 int r;
3939 DECLARE_COMPLETION_ONSTACK(completion);
3940
3941 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3942 irqmask);
3943
3944 if (r)
3945 return r;
3946
3947 timeout = wait_for_completion_timeout(&completion, timeout);
3948
3949 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3950
3951 if (timeout == 0)
3952 return -ETIMEDOUT;
3953
80c39712
TV		 3954 return 0;
3955}
3956
3957int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3958 unsigned long timeout)
3959{
3960 void dispc_irq_wait_handler(void *data, u32 mask)
3961 {
3962 complete((struct completion *)data);
3963 }
3964
3965 int r;
3966 DECLARE_COMPLETION_ONSTACK(completion);
3967
3968 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3969 irqmask);
3970
3971 if (r)
3972 return r;
3973
3974 timeout = wait_for_completion_interruptible_timeout(&completion,
3975 timeout);
3976
3977 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3978
3979 if (timeout == 0)
3980 return -ETIMEDOUT;
3981
3982 if (timeout == -ERESTARTSYS)
3983 return -ERESTARTSYS;
3984
3985 return 0;
3986}
3987
80c39712
TV		 3988static void _omap_dispc_initialize_irq(void)
3989{
3990 unsigned long flags;
3991
3992 spin_lock_irqsave(&dispc.irq_lock, flags);
3993
3994 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3995
3996 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3997 if (dss_has_feature(FEAT_MGR_LCD2))
3998 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
e86d456a
CM		 3999 if (dss_has_feature(FEAT_MGR_LCD3))
4000 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
b8c095b4
AT		 4001 if (dss_feat_get_num_ovls() > 3)
4002 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 4003
4004 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
4005 * so clear it */
4e0397cf 4006 dispc_clear_irqstatus(dispc_read_irqstatus());
80c39712
TV		 4007
4008 _omap_dispc_set_irqs();
4009
4010 spin_unlock_irqrestore(&dispc.irq_lock, flags);
4011}
4012
4013void dispc_enable_sidle(void)
4014{
4015 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
4016}
4017
4018void dispc_disable_sidle(void)
4019{
4020 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
4021}
4022
4023static void _omap_dispc_initial_config(void)
4024{
4025 u32 l;
4026
0cf35df3
MR		 4027 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
4028 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
4029 l = dispc_read_reg(DISPC_DIVISOR);
4030 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
4031 l = FLD_MOD(l, 1, 0, 0);
4032 l = FLD_MOD(l, 1, 23, 16);
4033 dispc_write_reg(DISPC_DIVISOR, l);
4034 }
4035
80c39712 4036 /* FUNCGATED */
6ced40bf
AT		 4037 if (dss_has_feature(FEAT_FUNCGATED))
4038 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 4039
6e5264b0 4040 dispc_setup_color_conv_coef();
80c39712
TV		 4041
4042 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
4043
42a6961c 4044 dispc_init_fifos();
5ed8cf5b
TV		 4045
4046 dispc_configure_burst_sizes();
54128701
AT		 4047
4048 dispc_ovl_enable_zorder_planes();
80c39712
TV		 4049}
4050
dcbe765b
CM		 4051static const struct dispc_features omap24xx_dispc_feats __initconst = {
4052 .sw_start = 5,
4053 .fp_start = 15,
4054 .bp_start = 27,
4055 .sw_max = 64,
4056 .vp_max = 255,
4057 .hp_max = 256,
33b89928
AT		 4058 .mgr_width_start = 10,
4059 .mgr_height_start = 26,
4060 .mgr_width_max = 2048,
4061 .mgr_height_max = 2048,
dcbe765b
CM		 4062 .calc_scaling = dispc_ovl_calc_scaling_24xx,
4063 .calc_core_clk = calc_core_clk_24xx,
42a6961c 4064 .num_fifos = 3,
cffa947d 4065 .no_framedone_tv = true,
dcbe765b
CM		 4066};
4067
4068static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
4069 .sw_start = 5,
4070 .fp_start = 15,
4071 .bp_start = 27,
4072 .sw_max = 64,
4073 .vp_max = 255,
4074 .hp_max = 256,
33b89928
AT		 4075 .mgr_width_start = 10,
4076 .mgr_height_start = 26,
4077 .mgr_width_max = 2048,
4078 .mgr_height_max = 2048,
dcbe765b
CM		 4079 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4080 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4081 .num_fifos = 3,
cffa947d 4082 .no_framedone_tv = true,
dcbe765b
CM		 4083};
4084
4085static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
4086 .sw_start = 7,
4087 .fp_start = 19,
4088 .bp_start = 31,
4089 .sw_max = 256,
4090 .vp_max = 4095,
4091 .hp_max = 4096,
33b89928
AT		 4092 .mgr_width_start = 10,
4093 .mgr_height_start = 26,
4094 .mgr_width_max = 2048,
4095 .mgr_height_max = 2048,
dcbe765b
CM		 4096 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4097 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4098 .num_fifos = 3,
cffa947d 4099 .no_framedone_tv = true,
dcbe765b
CM		 4100};
4101
4102static const struct dispc_features omap44xx_dispc_feats __initconst = {
4103 .sw_start = 7,
4104 .fp_start = 19,
4105 .bp_start = 31,
4106 .sw_max = 256,
4107 .vp_max = 4095,
4108 .hp_max = 4096,
33b89928
AT		 4109 .mgr_width_start = 10,
4110 .mgr_height_start = 26,
4111 .mgr_width_max = 2048,
4112 .mgr_height_max = 2048,
dcbe765b
CM		 4113 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4114 .calc_core_clk = calc_core_clk_44xx,
42a6961c 4115 .num_fifos = 5,
66a0f9e4 4116 .gfx_fifo_workaround = true,
dcbe765b
CM		 4117};
4118
264236f8
AT		 4119static const struct dispc_features omap54xx_dispc_feats __initconst = {
4120 .sw_start = 7,
4121 .fp_start = 19,
4122 .bp_start = 31,
4123 .sw_max = 256,
4124 .vp_max = 4095,
4125 .hp_max = 4096,
4126 .mgr_width_start = 11,
4127 .mgr_height_start = 27,
4128 .mgr_width_max = 4096,
4129 .mgr_height_max = 4096,
4130 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4131 .calc_core_clk = calc_core_clk_44xx,
4132 .num_fifos = 5,
4133 .gfx_fifo_workaround = true,
4134};
4135
84b47623 4136static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 4137{
4138 const struct dispc_features *src;
4139 struct dispc_features *dst;
4140
84b47623 4141 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 4142 if (!dst) {
84b47623 4143 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 4144 return -ENOMEM;
4145 }
4146
b2c7d54f 4147 switch (omapdss_get_version()) {
84b47623 4148 case OMAPDSS_VER_OMAP24xx:
dcbe765b 4149 src = &omap24xx_dispc_feats;
84b47623
TV		 4150 break;
4151
4152 case OMAPDSS_VER_OMAP34xx_ES1:
4153 src = &omap34xx_rev1_0_dispc_feats;
4154 break;
4155
4156 case OMAPDSS_VER_OMAP34xx_ES3:
4157 case OMAPDSS_VER_OMAP3630:
4158 case OMAPDSS_VER_AM35xx:
4159 src = &omap34xx_rev3_0_dispc_feats;
4160 break;
4161
4162 case OMAPDSS_VER_OMAP4430_ES1:
4163 case OMAPDSS_VER_OMAP4430_ES2:
4164 case OMAPDSS_VER_OMAP4:
dcbe765b 4165 src = &omap44xx_dispc_feats;
84b47623
TV		 4166 break;
4167
4168 case OMAPDSS_VER_OMAP5:
264236f8 4169 src = &omap54xx_dispc_feats;
84b47623
TV		 4170 break;
4171
4172 default:
dcbe765b
CM		 4173 return -ENODEV;
4174 }
4175
4176 memcpy(dst, src, sizeof(*dst));
4177 dispc.feat = dst;
4178
4179 return 0;
4180}
4181
060b6d9c 4182/* DISPC HW IP initialisation */
6e7e8f06 4183static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 4184{
4185 u32 rev;
affe360d 4186 int r = 0;
ea9da36a 4187 struct resource *dispc_mem;
4fbafaf3 4188 struct clk *clk;
ea9da36a 4189
060b6d9c
SG		 4190 dispc.pdev = pdev;
4191
84b47623 4192 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4193 if (r)
4194 return r;
4195
060b6d9c
SG		 4196 spin_lock_init(&dispc.irq_lock);
4197
4198#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4199 spin_lock_init(&dispc.irq_stats_lock);
4200 dispc.irq_stats.last_reset = jiffies;
4201#endif
4202
4203 INIT_WORK(&dispc.error_work, dispc_error_worker);
4204
ea9da36a
SG		 4205 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4206 if (!dispc_mem) {
4207 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 4208 return -EINVAL;
ea9da36a 4209 }
cd3b3449 4210
6e2a14d2
JL		 4211 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4212 resource_size(dispc_mem));
060b6d9c
SG		 4213 if (!dispc.base) {
4214 DSSERR("can't ioremap DISPC\n");
cd3b3449 4215 return -ENOMEM;
affe360d 4216 }
cd3b3449 4217
affe360d 4218 dispc.irq = platform_get_irq(dispc.pdev, 0);
4219 if (dispc.irq < 0) {
4220 DSSERR("platform_get_irq failed\n");
cd3b3449 4221 return -ENODEV;
affe360d 4222 }
4223
6e2a14d2
JL		 4224 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
4225 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 4226 if (r < 0) {
4227 DSSERR("request_irq failed\n");
cd3b3449
TV		 4228 return r;
4229 }
4230
4231 clk = clk_get(&pdev->dev, "fck");
4232 if (IS_ERR(clk)) {
4233 DSSERR("can't get fck\n");
4234 r = PTR_ERR(clk);
4235 return r;
060b6d9c
SG		 4236 }
4237
cd3b3449
TV		 4238 dispc.dss_clk = clk;
4239
4fbafaf3
TV		 4240 pm_runtime_enable(&pdev->dev);
4241
4242 r = dispc_runtime_get();
4243 if (r)
4244 goto err_runtime_get;
060b6d9c
SG		 4245
4246 _omap_dispc_initial_config();
4247
4248 _omap_dispc_initialize_irq();
4249
060b6d9c 4250 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4251 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4252 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4253
4fbafaf3 4254 dispc_runtime_put();
060b6d9c 4255
e40402cf
TV		 4256 dss_debugfs_create_file("dispc", dispc_dump_regs);
4257
4258#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4259 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
4260#endif
060b6d9c 4261 return 0;
4fbafaf3
TV		 4262
4263err_runtime_get:
4264 pm_runtime_disable(&pdev->dev);
4fbafaf3 4265 clk_put(dispc.dss_clk);
affe360d 4266 return r;
060b6d9c
SG		 4267}
4268
6e7e8f06 4269static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 4270{
4fbafaf3
TV		 4271 pm_runtime_disable(&pdev->dev);
4272
4273 clk_put(dispc.dss_clk);
4274
060b6d9c
SG		 4275 return 0;
4276}
4277
4fbafaf3
TV		 4278static int dispc_runtime_suspend(struct device *dev)
4279{
4280 dispc_save_context();
4fbafaf3
TV		 4281
4282 return 0;
4283}
4284
4285static int dispc_runtime_resume(struct device *dev)
4286{
49ea86f3 4287 dispc_restore_context();
4fbafaf3
TV		 4288
4289 return 0;
4290}
4291
4292static const struct dev_pm_ops dispc_pm_ops = {
4293 .runtime_suspend = dispc_runtime_suspend,
4294 .runtime_resume = dispc_runtime_resume,
4295};
4296
060b6d9c 4297static struct platform_driver omap_dispchw_driver = {
6e7e8f06 4298 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 4299 .driver = {
4300 .name = "omapdss_dispc",
4301 .owner = THIS_MODULE,
4fbafaf3 4302 .pm = &dispc_pm_ops,
060b6d9c
SG		 4303 },
4304};
4305
6e7e8f06 4306int __init dispc_init_platform_driver(void)
060b6d9c 4307{
11436e1d 4308 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 4309}
4310
6e7e8f06 4311void __exit dispc_uninit_platform_driver(void)
060b6d9c 4312{
04c742c3 4313 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4314}
Linux kernel - Deliverables
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