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OMAP: DSS2: Add new registers for NV12 support
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
80c39712
TV		 36
37#include <plat/sram.h>
38#include <plat/clock.h>
39
a0b38cc4 40#include <video/omapdss.h>
80c39712
TV		 41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
9b372c2d 44#include "dispc.h"
80c39712
TV		 45
46/* DISPC */
8613b000 47#define DISPC_SZ_REGS SZ_4K
80c39712 48
80c39712
TV		 49#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
50 DISPC_IRQ_OCP_ERR | \
51 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
52 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
53 DISPC_IRQ_SYNC_LOST | \
54 DISPC_IRQ_SYNC_LOST_DIGIT)
55
56#define DISPC_MAX_NR_ISRS 8
57
58struct omap_dispc_isr_data {
59 omap_dispc_isr_t isr;
60 void *arg;
61 u32 mask;
62};
63
66be8f6c
GI		 64struct dispc_h_coef {
65 s8 hc4;
66 s8 hc3;
67 u8 hc2;
68 s8 hc1;
69 s8 hc0;
70};
71
72struct dispc_v_coef {
73 s8 vc22;
74 s8 vc2;
75 u8 vc1;
76 s8 vc0;
77 s8 vc00;
78};
79
80c39712
TV		 80#define REG_GET(idx, start, end) \
81 FLD_GET(dispc_read_reg(idx), start, end)
82
83#define REG_FLD_MOD(idx, val, start, end) \
84 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
85
dfc0fd8d
TV		 86struct dispc_irq_stats {
87 unsigned long last_reset;
88 unsigned irq_count;
89 unsigned irqs[32];
90};
91
80c39712 92static struct {
060b6d9c 93 struct platform_device *pdev;
80c39712 94 void __iomem *base;
affe360d 95 int irq;
80c39712
TV		 96
97 u32 fifo_size[3];
98
99 spinlock_t irq_lock;
100 u32 irq_error_mask;
101 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
102 u32 error_irqs;
103 struct work_struct error_work;
104
105 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 106
107#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
108 spinlock_t irq_stats_lock;
109 struct dispc_irq_stats irq_stats;
110#endif
80c39712
TV		 111} dispc;
112
113static void _omap_dispc_set_irqs(void);
114
55978cc2 115static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 116{
55978cc2 117 __raw_writel(val, dispc.base + idx);
80c39712
TV		 118}
119
55978cc2 120static inline u32 dispc_read_reg(const u16 idx)
80c39712 121{
55978cc2 122 return __raw_readl(dispc.base + idx);
80c39712
TV		 123}
124
125#define SR(reg) \
55978cc2 126 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 127#define RR(reg) \
55978cc2 128 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712
TV		 129
130void dispc_save_context(void)
131{
5719d35c 132 int i;
80c39712
TV		 133 if (cpu_is_omap24xx())
134 return;
135
136 SR(SYSCONFIG);
137 SR(IRQENABLE);
138 SR(CONTROL);
139 SR(CONFIG);
702d1448
AT		 140 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
141 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
142 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
143 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712 144 SR(LINE_NUMBER);
702d1448
AT		 145 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
146 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
147 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
148 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
80c39712 149 SR(GLOBAL_ALPHA);
702d1448
AT		 150 SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
151 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34
SS		 152 if (dss_has_feature(FEAT_MGR_LCD2)) {
153 SR(CONTROL2);
702d1448
AT		 154 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
155 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
156 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
157 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
158 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
159 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
160 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2a205f34
SS		 161 SR(CONFIG2);
162 }
80c39712 163
9b372c2d
AT		 164 SR(OVL_BA0(OMAP_DSS_GFX));
165 SR(OVL_BA1(OMAP_DSS_GFX));
166 SR(OVL_POSITION(OMAP_DSS_GFX));
167 SR(OVL_SIZE(OMAP_DSS_GFX));
168 SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
169 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
170 SR(OVL_ROW_INC(OMAP_DSS_GFX));
171 SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
172 SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
173 SR(OVL_TABLE_BA(OMAP_DSS_GFX));
80c39712 174
702d1448
AT		 175 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
176 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
177 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 178
702d1448
AT		 179 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
180 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
181 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
2a205f34 182 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 183 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
184 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
185 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2a205f34 186
702d1448
AT		 187 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
188 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
189 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 190 }
80c39712 191
9b372c2d 192 SR(OVL_PRELOAD(OMAP_DSS_GFX));
80c39712
TV		 193
194 /* VID1 */
9b372c2d
AT		 195 SR(OVL_BA0(OMAP_DSS_VIDEO1));
196 SR(OVL_BA1(OMAP_DSS_VIDEO1));
197 SR(OVL_POSITION(OMAP_DSS_VIDEO1));
198 SR(OVL_SIZE(OMAP_DSS_VIDEO1));
199 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
200 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
201 SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
202 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
203 SR(OVL_FIR(OMAP_DSS_VIDEO1));
204 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
205 SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
206 SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
207
5719d35c
AJ		 208 for (i = 0; i < 8; i++)
209 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
210
211 for (i = 0; i < 8; i++)
212 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
213
214 for (i = 0; i < 5; i++)
215 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
216
217 for (i = 0; i < 8; i++)
218 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
9b372c2d 219
ab5ca071
AJ		 220 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
221 SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
222 SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
223 SR(OVL_FIR2(OMAP_DSS_VIDEO1));
224 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
225 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
226
227 for (i = 0; i < 8; i++)
228 SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
229
230 for (i = 0; i < 8; i++)
231 SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
232
233 for (i = 0; i < 8; i++)
234 SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
235 }
236 if (dss_has_feature(FEAT_ATTR2))
237 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
238
9b372c2d 239 SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
80c39712
TV		 240
241 /* VID2 */
9b372c2d
AT		 242 SR(OVL_BA0(OMAP_DSS_VIDEO2));
243 SR(OVL_BA1(OMAP_DSS_VIDEO2));
244 SR(OVL_POSITION(OMAP_DSS_VIDEO2));
245 SR(OVL_SIZE(OMAP_DSS_VIDEO2));
246 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
247 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
248 SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
249 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
250 SR(OVL_FIR(OMAP_DSS_VIDEO2));
251 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
252 SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
253 SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
254
5719d35c
AJ		 255 for (i = 0; i < 8; i++)
256 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
257
258 for (i = 0; i < 8; i++)
259 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
260
261 for (i = 0; i < 5; i++)
262 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
263
264 for (i = 0; i < 8; i++)
265 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
9b372c2d 266
ab5ca071
AJ		 267 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
268 SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
269 SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
270 SR(OVL_FIR2(OMAP_DSS_VIDEO2));
271 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
272 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
273
274 for (i = 0; i < 8; i++)
275 SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
276
277 for (i = 0; i < 8; i++)
278 SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
279
280 for (i = 0; i < 8; i++)
281 SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
282 }
283 if (dss_has_feature(FEAT_ATTR2))
284 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
285
9b372c2d 286 SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
0cf35df3
MR		 287
288 if (dss_has_feature(FEAT_CORE_CLK_DIV))
289 SR(DIVISOR);
80c39712
TV		 290}
291
292void dispc_restore_context(void)
293{
5719d35c 294 int i;
80c39712 295 RR(SYSCONFIG);
75c7d59d 296 /*RR(IRQENABLE);*/
80c39712
TV		 297 /*RR(CONTROL);*/
298 RR(CONFIG);
702d1448
AT		 299 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
300 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
301 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
302 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712 303 RR(LINE_NUMBER);
702d1448
AT		 304 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
305 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
306 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
307 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
80c39712 308 RR(GLOBAL_ALPHA);
702d1448
AT		 309 RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
310 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34 311 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 312 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
313 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
314 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
315 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
316 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
317 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
318 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2a205f34
SS		 319 RR(CONFIG2);
320 }
80c39712 321
9b372c2d
AT		 322 RR(OVL_BA0(OMAP_DSS_GFX));
323 RR(OVL_BA1(OMAP_DSS_GFX));
324 RR(OVL_POSITION(OMAP_DSS_GFX));
325 RR(OVL_SIZE(OMAP_DSS_GFX));
326 RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
327 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
328 RR(OVL_ROW_INC(OMAP_DSS_GFX));
329 RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
330 RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
331 RR(OVL_TABLE_BA(OMAP_DSS_GFX));
332
80c39712 333
702d1448
AT		 334 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
335 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
336 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 337
702d1448
AT		 338 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
339 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
340 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
2a205f34 341 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 342 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
343 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
344 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 345
702d1448
AT		 346 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
347 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
348 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2a205f34 349 }
80c39712 350
9b372c2d 351 RR(OVL_PRELOAD(OMAP_DSS_GFX));
80c39712
TV		 352
353 /* VID1 */
9b372c2d
AT		 354 RR(OVL_BA0(OMAP_DSS_VIDEO1));
355 RR(OVL_BA1(OMAP_DSS_VIDEO1));
356 RR(OVL_POSITION(OMAP_DSS_VIDEO1));
357 RR(OVL_SIZE(OMAP_DSS_VIDEO1));
358 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
359 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
360 RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
361 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
362 RR(OVL_FIR(OMAP_DSS_VIDEO1));
363 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
364 RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
365 RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
366
5719d35c
AJ		 367 for (i = 0; i < 8; i++)
368 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
369
370 for (i = 0; i < 8; i++)
371 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
372
373 for (i = 0; i < 5; i++)
374 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
375
376 for (i = 0; i < 8; i++)
377 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
9b372c2d 378
ab5ca071
AJ		 379 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
380 RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
381 RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
382 RR(OVL_FIR2(OMAP_DSS_VIDEO1));
383 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
384 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
385
386 for (i = 0; i < 8; i++)
387 RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
388
389 for (i = 0; i < 8; i++)
390 RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
391
392 for (i = 0; i < 8; i++)
393 RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
394 }
395 if (dss_has_feature(FEAT_ATTR2))
396 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
397
9b372c2d 398 RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
80c39712
TV		 399
400 /* VID2 */
9b372c2d
AT		 401 RR(OVL_BA0(OMAP_DSS_VIDEO2));
402 RR(OVL_BA1(OMAP_DSS_VIDEO2));
403 RR(OVL_POSITION(OMAP_DSS_VIDEO2));
404 RR(OVL_SIZE(OMAP_DSS_VIDEO2));
405 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
406 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
407 RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
408 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
409 RR(OVL_FIR(OMAP_DSS_VIDEO2));
410 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
411 RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
412 RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
413
5719d35c
AJ		 414 for (i = 0; i < 8; i++)
415 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
416
417 for (i = 0; i < 8; i++)
418 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
419
420 for (i = 0; i < 5; i++)
421 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
422
423 for (i = 0; i < 8; i++)
424 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
9b372c2d 425
ab5ca071
AJ		 426 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
427 RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
428 RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
429 RR(OVL_FIR2(OMAP_DSS_VIDEO2));
430 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
431 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
432
433 for (i = 0; i < 8; i++)
434 RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
435
436 for (i = 0; i < 8; i++)
437 RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
438
439 for (i = 0; i < 8; i++)
440 RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
441 }
442 if (dss_has_feature(FEAT_ATTR2))
443 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
444
9b372c2d 445 RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
80c39712 446
0cf35df3
MR		 447 if (dss_has_feature(FEAT_CORE_CLK_DIV))
448 RR(DIVISOR);
449
80c39712
TV		 450 /* enable last, because LCD & DIGIT enable are here */
451 RR(CONTROL);
2a205f34
SS		 452 if (dss_has_feature(FEAT_MGR_LCD2))
453 RR(CONTROL2);
75c7d59d
VS		 454 /* clear spurious SYNC_LOST_DIGIT interrupts */
455 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
456
457 /*
458 * enable last so IRQs won't trigger before
459 * the context is fully restored
460 */
461 RR(IRQENABLE);
80c39712
TV		 462}
463
464#undef SR
465#undef RR
466
467static inline void enable_clocks(bool enable)
468{
469 if (enable)
6af9cd14 470 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712 471 else
6af9cd14 472 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 473}
474
475bool dispc_go_busy(enum omap_channel channel)
476{
477 int bit;
478
2a205f34
SS		 479 if (channel == OMAP_DSS_CHANNEL_LCD ||
480 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 481 bit = 5; /* GOLCD */
482 else
483 bit = 6; /* GODIGIT */
484
2a205f34
SS		 485 if (channel == OMAP_DSS_CHANNEL_LCD2)
486 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
487 else
488 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 489}
490
491void dispc_go(enum omap_channel channel)
492{
493 int bit;
2a205f34 494 bool enable_bit, go_bit;
80c39712
TV		 495
496 enable_clocks(1);
497
2a205f34
SS		 498 if (channel == OMAP_DSS_CHANNEL_LCD ||
499 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 500 bit = 0; /* LCDENABLE */
501 else
502 bit = 1; /* DIGITALENABLE */
503
504 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 505 if (channel == OMAP_DSS_CHANNEL_LCD2)
506 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
507 else
508 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
509
510 if (!enable_bit)
80c39712
TV		 511 goto end;
512
2a205f34
SS		 513 if (channel == OMAP_DSS_CHANNEL_LCD ||
514 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 515 bit = 5; /* GOLCD */
516 else
517 bit = 6; /* GODIGIT */
518
2a205f34
SS		 519 if (channel == OMAP_DSS_CHANNEL_LCD2)
520 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
521 else
522 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
523
524 if (go_bit) {
80c39712
TV		 525 DSSERR("GO bit not down for channel %d\n", channel);
526 goto end;
527 }
528
2a205f34
SS		 529 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
530 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 531
2a205f34
SS		 532 if (channel == OMAP_DSS_CHANNEL_LCD2)
533 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
534 else
535 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 536end:
537 enable_clocks(0);
538}
539
540static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
541{
9b372c2d 542 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 543}
544
545static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
546{
9b372c2d 547 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 548}
549
550static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
551{
9b372c2d 552 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 553}
554
ab5ca071
AJ		 555static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
556{
557 BUG_ON(plane == OMAP_DSS_GFX);
558
559 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
560}
561
562static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
563{
564 BUG_ON(plane == OMAP_DSS_GFX);
565
566 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
567}
568
569static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
570{
571 BUG_ON(plane == OMAP_DSS_GFX);
572
573 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
574}
575
80c39712
TV		 576static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
577 int vscaleup, int five_taps)
578{
579 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 580 static const struct dispc_h_coef coef_hup[8] = {
581 { 0, 0, 128, 0, 0 },
582 { -1, 13, 124, -8, 0 },
583 { -2, 30, 112, -11, -1 },
584 { -5, 51, 95, -11, -2 },
585 { 0, -9, 73, 73, -9 },
586 { -2, -11, 95, 51, -5 },
587 { -1, -11, 112, 30, -2 },
588 { 0, -8, 124, 13, -1 },
80c39712
TV		 589 };
590
66be8f6c
GI		 591 /* Coefficients for vertical up-sampling */
592 static const struct dispc_v_coef coef_vup_3tap[8] = {
593 { 0, 0, 128, 0, 0 },
594 { 0, 3, 123, 2, 0 },
595 { 0, 12, 111, 5, 0 },
596 { 0, 32, 89, 7, 0 },
597 { 0, 0, 64, 64, 0 },
598 { 0, 7, 89, 32, 0 },
599 { 0, 5, 111, 12, 0 },
600 { 0, 2, 123, 3, 0 },
80c39712
TV		 601 };
602
66be8f6c
GI		 603 static const struct dispc_v_coef coef_vup_5tap[8] = {
604 { 0, 0, 128, 0, 0 },
605 { -1, 13, 124, -8, 0 },
606 { -2, 30, 112, -11, -1 },
607 { -5, 51, 95, -11, -2 },
608 { 0, -9, 73, 73, -9 },
609 { -2, -11, 95, 51, -5 },
610 { -1, -11, 112, 30, -2 },
611 { 0, -8, 124, 13, -1 },
80c39712
TV		 612 };
613
66be8f6c
GI		 614 /* Coefficients for horizontal down-sampling */
615 static const struct dispc_h_coef coef_hdown[8] = {
616 { 0, 36, 56, 36, 0 },
617 { 4, 40, 55, 31, -2 },
618 { 8, 44, 54, 27, -5 },
619 { 12, 48, 53, 22, -7 },
620 { -9, 17, 52, 51, 17 },
621 { -7, 22, 53, 48, 12 },
622 { -5, 27, 54, 44, 8 },
623 { -2, 31, 55, 40, 4 },
80c39712
TV		 624 };
625
66be8f6c
GI		 626 /* Coefficients for vertical down-sampling */
627 static const struct dispc_v_coef coef_vdown_3tap[8] = {
628 { 0, 36, 56, 36, 0 },
629 { 0, 40, 57, 31, 0 },
630 { 0, 45, 56, 27, 0 },
631 { 0, 50, 55, 23, 0 },
632 { 0, 18, 55, 55, 0 },
633 { 0, 23, 55, 50, 0 },
634 { 0, 27, 56, 45, 0 },
635 { 0, 31, 57, 40, 0 },
80c39712
TV		 636 };
637
66be8f6c
GI		 638 static const struct dispc_v_coef coef_vdown_5tap[8] = {
639 { 0, 36, 56, 36, 0 },
640 { 4, 40, 55, 31, -2 },
641 { 8, 44, 54, 27, -5 },
642 { 12, 48, 53, 22, -7 },
643 { -9, 17, 52, 51, 17 },
644 { -7, 22, 53, 48, 12 },
645 { -5, 27, 54, 44, 8 },
646 { -2, 31, 55, 40, 4 },
80c39712
TV		 647 };
648
66be8f6c
GI		 649 const struct dispc_h_coef *h_coef;
650 const struct dispc_v_coef *v_coef;
80c39712
TV		 651 int i;
652
653 if (hscaleup)
654 h_coef = coef_hup;
655 else
656 h_coef = coef_hdown;
657
66be8f6c
GI		 658 if (vscaleup)
659 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
660 else
661 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 662
663 for (i = 0; i < 8; i++) {
664 u32 h, hv;
665
66be8f6c
GI		 666 h = FLD_VAL(h_coef[i].hc0, 7, 0)
667 | FLD_VAL(h_coef[i].hc1, 15, 8)
668 | FLD_VAL(h_coef[i].hc2, 23, 16)
669 | FLD_VAL(h_coef[i].hc3, 31, 24);
670 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
671 | FLD_VAL(v_coef[i].vc0, 15, 8)
672 | FLD_VAL(v_coef[i].vc1, 23, 16)
673 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712
TV		 674
675 _dispc_write_firh_reg(plane, i, h);
676 _dispc_write_firhv_reg(plane, i, hv);
677 }
678
66be8f6c
GI		 679 if (five_taps) {
680 for (i = 0; i < 8; i++) {
681 u32 v;
682 v = FLD_VAL(v_coef[i].vc00, 7, 0)
683 | FLD_VAL(v_coef[i].vc22, 15, 8);
684 _dispc_write_firv_reg(plane, i, v);
685 }
80c39712
TV		 686 }
687}
688
689static void _dispc_setup_color_conv_coef(void)
690{
691 const struct color_conv_coef {
692 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
693 int full_range;
694 } ctbl_bt601_5 = {
695 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
696 };
697
698 const struct color_conv_coef *ct;
699
700#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
701
702 ct = &ctbl_bt601_5;
703
9b372c2d
AT		 704 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
705 CVAL(ct->rcr, ct->ry));
706 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
707 CVAL(ct->gy, ct->rcb));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
709 CVAL(ct->gcb, ct->gcr));
710 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
711 CVAL(ct->bcr, ct->by));
712 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
713 CVAL(0, ct->bcb));
714
715 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
716 CVAL(ct->rcr, ct->ry));
717 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
718 CVAL(ct->gy, ct->rcb));
719 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
720 CVAL(ct->gcb, ct->gcr));
721 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
722 CVAL(ct->bcr, ct->by));
723 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
724 CVAL(0, ct->bcb));
80c39712
TV		 725
726#undef CVAL
727
9b372c2d
AT		 728 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
729 ct->full_range, 11, 11);
730 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
731 ct->full_range, 11, 11);
80c39712
TV		 732}
733
734
735static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
736{
9b372c2d 737 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 738}
739
740static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
741{
9b372c2d 742 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 743}
744
ab5ca071
AJ		 745static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
746{
747 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
748}
749
750static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
751{
752 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
753}
754
80c39712
TV		 755static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
756{
80c39712 757 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 758
759 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 760}
761
762static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
763{
80c39712 764 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 765
766 if (plane == OMAP_DSS_GFX)
767 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
768 else
769 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 770}
771
772static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
773{
774 u32 val;
80c39712
TV		 775
776 BUG_ON(plane == OMAP_DSS_GFX);
777
778 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 779
780 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 781}
782
fd28a390
R		 783static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
784{
785 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
786 return;
787
788 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
789 plane == OMAP_DSS_VIDEO1)
790 return;
791
9b372c2d 792 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 793}
794
80c39712
TV		 795static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
796{
a0acb557 797 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 798 return;
799
fd28a390
R		 800 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
801 plane == OMAP_DSS_VIDEO1)
802 return;
a0acb557 803
80c39712
TV		 804 if (plane == OMAP_DSS_GFX)
805 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
806 else if (plane == OMAP_DSS_VIDEO2)
807 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
808}
809
810static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
811{
9b372c2d 812 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 813}
814
815static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
816{
9b372c2d 817 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 818}
819
820static void _dispc_set_color_mode(enum omap_plane plane,
821 enum omap_color_mode color_mode)
822{
823 u32 m = 0;
f20e4220
AJ		 824 if (plane != OMAP_DSS_GFX) {
825 switch (color_mode) {
826 case OMAP_DSS_COLOR_NV12:
827 m = 0x0; break;
828 case OMAP_DSS_COLOR_RGB12U:
829 m = 0x1; break;
830 case OMAP_DSS_COLOR_RGBA16:
831 m = 0x2; break;
832 case OMAP_DSS_COLOR_RGBX16:
833 m = 0x4; break;
834 case OMAP_DSS_COLOR_ARGB16:
835 m = 0x5; break;
836 case OMAP_DSS_COLOR_RGB16:
837 m = 0x6; break;
838 case OMAP_DSS_COLOR_ARGB16_1555:
839 m = 0x7; break;
840 case OMAP_DSS_COLOR_RGB24U:
841 m = 0x8; break;
842 case OMAP_DSS_COLOR_RGB24P:
843 m = 0x9; break;
844 case OMAP_DSS_COLOR_YUV2:
845 m = 0xa; break;
846 case OMAP_DSS_COLOR_UYVY:
847 m = 0xb; break;
848 case OMAP_DSS_COLOR_ARGB32:
849 m = 0xc; break;
850 case OMAP_DSS_COLOR_RGBA32:
851 m = 0xd; break;
852 case OMAP_DSS_COLOR_RGBX32:
853 m = 0xe; break;
854 case OMAP_DSS_COLOR_XRGB16_1555:
855 m = 0xf; break;
856 default:
857 BUG(); break;
858 }
859 } else {
860 switch (color_mode) {
861 case OMAP_DSS_COLOR_CLUT1:
862 m = 0x0; break;
863 case OMAP_DSS_COLOR_CLUT2:
864 m = 0x1; break;
865 case OMAP_DSS_COLOR_CLUT4:
866 m = 0x2; break;
867 case OMAP_DSS_COLOR_CLUT8:
868 m = 0x3; break;
869 case OMAP_DSS_COLOR_RGB12U:
870 m = 0x4; break;
871 case OMAP_DSS_COLOR_ARGB16:
872 m = 0x5; break;
873 case OMAP_DSS_COLOR_RGB16:
874 m = 0x6; break;
875 case OMAP_DSS_COLOR_ARGB16_1555:
876 m = 0x7; break;
877 case OMAP_DSS_COLOR_RGB24U:
878 m = 0x8; break;
879 case OMAP_DSS_COLOR_RGB24P:
880 m = 0x9; break;
881 case OMAP_DSS_COLOR_YUV2:
882 m = 0xa; break;
883 case OMAP_DSS_COLOR_UYVY:
884 m = 0xb; break;
885 case OMAP_DSS_COLOR_ARGB32:
886 m = 0xc; break;
887 case OMAP_DSS_COLOR_RGBA32:
888 m = 0xd; break;
889 case OMAP_DSS_COLOR_RGBX32:
890 m = 0xe; break;
891 case OMAP_DSS_COLOR_XRGB16_1555:
892 m = 0xf; break;
893 default:
894 BUG(); break;
895 }
80c39712
TV		 896 }
897
9b372c2d 898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 899}
900
901static void _dispc_set_channel_out(enum omap_plane plane,
902 enum omap_channel channel)
903{
904 int shift;
905 u32 val;
2a205f34 906 int chan = 0, chan2 = 0;
80c39712
TV		 907
908 switch (plane) {
909 case OMAP_DSS_GFX:
910 shift = 8;
911 break;
912 case OMAP_DSS_VIDEO1:
913 case OMAP_DSS_VIDEO2:
914 shift = 16;
915 break;
916 default:
917 BUG();
918 return;
919 }
920
9b372c2d 921 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 922 if (dss_has_feature(FEAT_MGR_LCD2)) {
923 switch (channel) {
924 case OMAP_DSS_CHANNEL_LCD:
925 chan = 0;
926 chan2 = 0;
927 break;
928 case OMAP_DSS_CHANNEL_DIGIT:
929 chan = 1;
930 chan2 = 0;
931 break;
932 case OMAP_DSS_CHANNEL_LCD2:
933 chan = 0;
934 chan2 = 1;
935 break;
936 default:
937 BUG();
938 }
939
940 val = FLD_MOD(val, chan, shift, shift);
941 val = FLD_MOD(val, chan2, 31, 30);
942 } else {
943 val = FLD_MOD(val, channel, shift, shift);
944 }
9b372c2d 945 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 946}
947
948void dispc_set_burst_size(enum omap_plane plane,
949 enum omap_burst_size burst_size)
950{
951 int shift;
952 u32 val;
953
954 enable_clocks(1);
955
956 switch (plane) {
957 case OMAP_DSS_GFX:
958 shift = 6;
959 break;
960 case OMAP_DSS_VIDEO1:
961 case OMAP_DSS_VIDEO2:
962 shift = 14;
963 break;
964 default:
965 BUG();
966 return;
967 }
968
9b372c2d 969 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 970 val = FLD_MOD(val, burst_size, shift+1, shift);
9b372c2d 971 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 972
973 enable_clocks(0);
974}
975
d3862610
M		 976void dispc_enable_gamma_table(bool enable)
977{
978 /*
979 * This is partially implemented to support only disabling of
980 * the gamma table.
981 */
982 if (enable) {
983 DSSWARN("Gamma table enabling for TV not yet supported");
984 return;
985 }
986
987 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
988}
989
80c39712
TV		 990static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
991{
992 u32 val;
993
994 BUG_ON(plane == OMAP_DSS_GFX);
995
9b372c2d 996 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 997 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 998 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 999}
1000
1001void dispc_enable_replication(enum omap_plane plane, bool enable)
1002{
1003 int bit;
1004
1005 if (plane == OMAP_DSS_GFX)
1006 bit = 5;
1007 else
1008 bit = 10;
1009
1010 enable_clocks(1);
9b372c2d 1011 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
80c39712
TV		 1012 enable_clocks(0);
1013}
1014
64ba4f74 1015void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1016{
1017 u32 val;
1018 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1019 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1020 enable_clocks(1);
702d1448 1021 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1022 enable_clocks(0);
1023}
1024
1025void dispc_set_digit_size(u16 width, u16 height)
1026{
1027 u32 val;
1028 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1029 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1030 enable_clocks(1);
702d1448 1031 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1032 enable_clocks(0);
1033}
1034
1035static void dispc_read_plane_fifo_sizes(void)
1036{
80c39712
TV		 1037 u32 size;
1038 int plane;
a0acb557 1039 u8 start, end;
80c39712
TV		 1040
1041 enable_clocks(1);
1042
a0acb557 1043 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1044
a0acb557 1045 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
9b372c2d
AT		 1046 size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
1047 start, end);
80c39712
TV		 1048 dispc.fifo_size[plane] = size;
1049 }
1050
1051 enable_clocks(0);
1052}
1053
1054u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1055{
1056 return dispc.fifo_size[plane];
1057}
1058
1059void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1060{
a0acb557
AT		 1061 u8 hi_start, hi_end, lo_start, lo_end;
1062
9b372c2d
AT		 1063 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1064 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1065
80c39712
TV		 1066 enable_clocks(1);
1067
1068 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1069 plane,
9b372c2d
AT		 1070 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1071 lo_start, lo_end),
1072 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1073 hi_start, hi_end),
80c39712
TV		 1074 low, high);
1075
9b372c2d 1076 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1077 FLD_VAL(high, hi_start, hi_end) |
1078 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1079
1080 enable_clocks(0);
1081}
1082
1083void dispc_enable_fifomerge(bool enable)
1084{
1085 enable_clocks(1);
1086
1087 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1088 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1089
1090 enable_clocks(0);
1091}
1092
1093static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1094{
1095 u32 val;
a0acb557 1096 u8 hinc_start, hinc_end, vinc_start, vinc_end;
80c39712 1097
a0acb557
AT		 1098 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1099 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1100
1101 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1102 FLD_VAL(hinc, hinc_start, hinc_end);
1103
9b372c2d 1104 dispc_write_reg(DISPC_OVL_FIR(plane), val);
80c39712
TV		 1105}
1106
1107static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1108{
1109 u32 val;
87a7484b 1110 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1111
87a7484b
AT		 1112 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1113 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1114
1115 val = FLD_VAL(vaccu, vert_start, vert_end) |
1116 FLD_VAL(haccu, hor_start, hor_end);
1117
9b372c2d 1118 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1119}
1120
1121static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1122{
1123 u32 val;
87a7484b 1124 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1125
87a7484b
AT		 1126 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1127 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1128
1129 val = FLD_VAL(vaccu, vert_start, vert_end) |
1130 FLD_VAL(haccu, hor_start, hor_end);
1131
9b372c2d 1132 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1133}
1134
ab5ca071
AJ		 1135static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
1136{
1137 u32 val;
1138
1139 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1140 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1141}
1142
1143static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
1144{
1145 u32 val;
1146
1147 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1148 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1149}
80c39712
TV		 1150
1151static void _dispc_set_scaling(enum omap_plane plane,
1152 u16 orig_width, u16 orig_height,
1153 u16 out_width, u16 out_height,
1154 bool ilace, bool five_taps,
1155 bool fieldmode)
1156{
1157 int fir_hinc;
1158 int fir_vinc;
1159 int hscaleup, vscaleup;
1160 int accu0 = 0;
1161 int accu1 = 0;
1162 u32 l;
1163
1164 BUG_ON(plane == OMAP_DSS_GFX);
1165
1166 hscaleup = orig_width <= out_width;
1167 vscaleup = orig_height <= out_height;
1168
1169 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1170
ed14a3ce
AJ		 1171 fir_hinc = 1024 * orig_width / out_width;
1172 fir_vinc = 1024 * orig_height / out_height;
80c39712
TV		 1173
1174 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1175
9b372c2d 1176 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1177
87a7484b
AT		 1178 /* RESIZEENABLE and VERTICALTAPS */
1179 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1180 l |= (orig_width != out_width) ? (1 << 5) : 0;
1181 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1182 l |= five_taps ? (1 << 21) : 0;
80c39712 1183
87a7484b
AT		 1184 /* VRESIZECONF and HRESIZECONF */
1185 if (dss_has_feature(FEAT_RESIZECONF)) {
1186 l &= ~(0x3 << 7);
1187 l |= hscaleup ? 0 : (1 << 7);
1188 l |= vscaleup ? 0 : (1 << 8);
1189 }
80c39712 1190
87a7484b
AT		 1191 /* LINEBUFFERSPLIT */
1192 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1193 l &= ~(0x1 << 22);
1194 l |= five_taps ? (1 << 22) : 0;
1195 }
80c39712 1196
9b372c2d 1197 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1198
1199 /*
1200 * field 0 = even field = bottom field
1201 * field 1 = odd field = top field
1202 */
1203 if (ilace && !fieldmode) {
1204 accu1 = 0;
1205 accu0 = (fir_vinc / 2) & 0x3ff;
1206 if (accu0 >= 1024/2) {
1207 accu1 = 1024/2;
1208 accu0 -= accu1;
1209 }
1210 }
1211
1212 _dispc_set_vid_accu0(plane, 0, accu0);
1213 _dispc_set_vid_accu1(plane, 0, accu1);
1214}
1215
1216static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1217 bool mirroring, enum omap_color_mode color_mode)
1218{
87a7484b
AT		 1219 bool row_repeat = false;
1220 int vidrot = 0;
1221
80c39712
TV		 1222 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1223 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1224
1225 if (mirroring) {
1226 switch (rotation) {
1227 case OMAP_DSS_ROT_0:
1228 vidrot = 2;
1229 break;
1230 case OMAP_DSS_ROT_90:
1231 vidrot = 1;
1232 break;
1233 case OMAP_DSS_ROT_180:
1234 vidrot = 0;
1235 break;
1236 case OMAP_DSS_ROT_270:
1237 vidrot = 3;
1238 break;
1239 }
1240 } else {
1241 switch (rotation) {
1242 case OMAP_DSS_ROT_0:
1243 vidrot = 0;
1244 break;
1245 case OMAP_DSS_ROT_90:
1246 vidrot = 1;
1247 break;
1248 case OMAP_DSS_ROT_180:
1249 vidrot = 2;
1250 break;
1251 case OMAP_DSS_ROT_270:
1252 vidrot = 3;
1253 break;
1254 }
1255 }
1256
80c39712 1257 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1258 row_repeat = true;
80c39712 1259 else
87a7484b 1260 row_repeat = false;
80c39712 1261 }
87a7484b 1262
9b372c2d 1263 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1264 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1265 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1266 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1267}
1268
1269static int color_mode_to_bpp(enum omap_color_mode color_mode)
1270{
1271 switch (color_mode) {
1272 case OMAP_DSS_COLOR_CLUT1:
1273 return 1;
1274 case OMAP_DSS_COLOR_CLUT2:
1275 return 2;
1276 case OMAP_DSS_COLOR_CLUT4:
1277 return 4;
1278 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1279 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1280 return 8;
1281 case OMAP_DSS_COLOR_RGB12U:
1282 case OMAP_DSS_COLOR_RGB16:
1283 case OMAP_DSS_COLOR_ARGB16:
1284 case OMAP_DSS_COLOR_YUV2:
1285 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1286 case OMAP_DSS_COLOR_RGBA16:
1287 case OMAP_DSS_COLOR_RGBX16:
1288 case OMAP_DSS_COLOR_ARGB16_1555:
1289 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1290 return 16;
1291 case OMAP_DSS_COLOR_RGB24P:
1292 return 24;
1293 case OMAP_DSS_COLOR_RGB24U:
1294 case OMAP_DSS_COLOR_ARGB32:
1295 case OMAP_DSS_COLOR_RGBA32:
1296 case OMAP_DSS_COLOR_RGBX32:
1297 return 32;
1298 default:
1299 BUG();
1300 }
1301}
1302
1303static s32 pixinc(int pixels, u8 ps)
1304{
1305 if (pixels == 1)
1306 return 1;
1307 else if (pixels > 1)
1308 return 1 + (pixels - 1) * ps;
1309 else if (pixels < 0)
1310 return 1 - (-pixels + 1) * ps;
1311 else
1312 BUG();
1313}
1314
1315static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1316 u16 screen_width,
1317 u16 width, u16 height,
1318 enum omap_color_mode color_mode, bool fieldmode,
1319 unsigned int field_offset,
1320 unsigned *offset0, unsigned *offset1,
1321 s32 *row_inc, s32 *pix_inc)
1322{
1323 u8 ps;
1324
1325 /* FIXME CLUT formats */
1326 switch (color_mode) {
1327 case OMAP_DSS_COLOR_CLUT1:
1328 case OMAP_DSS_COLOR_CLUT2:
1329 case OMAP_DSS_COLOR_CLUT4:
1330 case OMAP_DSS_COLOR_CLUT8:
1331 BUG();
1332 return;
1333 case OMAP_DSS_COLOR_YUV2:
1334 case OMAP_DSS_COLOR_UYVY:
1335 ps = 4;
1336 break;
1337 default:
1338 ps = color_mode_to_bpp(color_mode) / 8;
1339 break;
1340 }
1341
1342 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1343 width, height);
1344
1345 /*
1346 * field 0 = even field = bottom field
1347 * field 1 = odd field = top field
1348 */
1349 switch (rotation + mirror * 4) {
1350 case OMAP_DSS_ROT_0:
1351 case OMAP_DSS_ROT_180:
1352 /*
1353 * If the pixel format is YUV or UYVY divide the width
1354 * of the image by 2 for 0 and 180 degree rotation.
1355 */
1356 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1357 color_mode == OMAP_DSS_COLOR_UYVY)
1358 width = width >> 1;
1359 case OMAP_DSS_ROT_90:
1360 case OMAP_DSS_ROT_270:
1361 *offset1 = 0;
1362 if (field_offset)
1363 *offset0 = field_offset * screen_width * ps;
1364 else
1365 *offset0 = 0;
1366
1367 *row_inc = pixinc(1 + (screen_width - width) +
1368 (fieldmode ? screen_width : 0),
1369 ps);
1370 *pix_inc = pixinc(1, ps);
1371 break;
1372
1373 case OMAP_DSS_ROT_0 + 4:
1374 case OMAP_DSS_ROT_180 + 4:
1375 /* If the pixel format is YUV or UYVY divide the width
1376 * of the image by 2 for 0 degree and 180 degree
1377 */
1378 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1379 color_mode == OMAP_DSS_COLOR_UYVY)
1380 width = width >> 1;
1381 case OMAP_DSS_ROT_90 + 4:
1382 case OMAP_DSS_ROT_270 + 4:
1383 *offset1 = 0;
1384 if (field_offset)
1385 *offset0 = field_offset * screen_width * ps;
1386 else
1387 *offset0 = 0;
1388 *row_inc = pixinc(1 - (screen_width + width) -
1389 (fieldmode ? screen_width : 0),
1390 ps);
1391 *pix_inc = pixinc(1, ps);
1392 break;
1393
1394 default:
1395 BUG();
1396 }
1397}
1398
1399static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1400 u16 screen_width,
1401 u16 width, u16 height,
1402 enum omap_color_mode color_mode, bool fieldmode,
1403 unsigned int field_offset,
1404 unsigned *offset0, unsigned *offset1,
1405 s32 *row_inc, s32 *pix_inc)
1406{
1407 u8 ps;
1408 u16 fbw, fbh;
1409
1410 /* FIXME CLUT formats */
1411 switch (color_mode) {
1412 case OMAP_DSS_COLOR_CLUT1:
1413 case OMAP_DSS_COLOR_CLUT2:
1414 case OMAP_DSS_COLOR_CLUT4:
1415 case OMAP_DSS_COLOR_CLUT8:
1416 BUG();
1417 return;
1418 default:
1419 ps = color_mode_to_bpp(color_mode) / 8;
1420 break;
1421 }
1422
1423 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1424 width, height);
1425
1426 /* width & height are overlay sizes, convert to fb sizes */
1427
1428 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1429 fbw = width;
1430 fbh = height;
1431 } else {
1432 fbw = height;
1433 fbh = width;
1434 }
1435
1436 /*
1437 * field 0 = even field = bottom field
1438 * field 1 = odd field = top field
1439 */
1440 switch (rotation + mirror * 4) {
1441 case OMAP_DSS_ROT_0:
1442 *offset1 = 0;
1443 if (field_offset)
1444 *offset0 = *offset1 + field_offset * screen_width * ps;
1445 else
1446 *offset0 = *offset1;
1447 *row_inc = pixinc(1 + (screen_width - fbw) +
1448 (fieldmode ? screen_width : 0),
1449 ps);
1450 *pix_inc = pixinc(1, ps);
1451 break;
1452 case OMAP_DSS_ROT_90:
1453 *offset1 = screen_width * (fbh - 1) * ps;
1454 if (field_offset)
1455 *offset0 = *offset1 + field_offset * ps;
1456 else
1457 *offset0 = *offset1;
1458 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1459 (fieldmode ? 1 : 0), ps);
1460 *pix_inc = pixinc(-screen_width, ps);
1461 break;
1462 case OMAP_DSS_ROT_180:
1463 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1464 if (field_offset)
1465 *offset0 = *offset1 - field_offset * screen_width * ps;
1466 else
1467 *offset0 = *offset1;
1468 *row_inc = pixinc(-1 -
1469 (screen_width - fbw) -
1470 (fieldmode ? screen_width : 0),
1471 ps);
1472 *pix_inc = pixinc(-1, ps);
1473 break;
1474 case OMAP_DSS_ROT_270:
1475 *offset1 = (fbw - 1) * ps;
1476 if (field_offset)
1477 *offset0 = *offset1 - field_offset * ps;
1478 else
1479 *offset0 = *offset1;
1480 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1481 (fieldmode ? 1 : 0), ps);
1482 *pix_inc = pixinc(screen_width, ps);
1483 break;
1484
1485 /* mirroring */
1486 case OMAP_DSS_ROT_0 + 4:
1487 *offset1 = (fbw - 1) * ps;
1488 if (field_offset)
1489 *offset0 = *offset1 + field_offset * screen_width * ps;
1490 else
1491 *offset0 = *offset1;
1492 *row_inc = pixinc(screen_width * 2 - 1 +
1493 (fieldmode ? screen_width : 0),
1494 ps);
1495 *pix_inc = pixinc(-1, ps);
1496 break;
1497
1498 case OMAP_DSS_ROT_90 + 4:
1499 *offset1 = 0;
1500 if (field_offset)
1501 *offset0 = *offset1 + field_offset * ps;
1502 else
1503 *offset0 = *offset1;
1504 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1505 (fieldmode ? 1 : 0),
1506 ps);
1507 *pix_inc = pixinc(screen_width, ps);
1508 break;
1509
1510 case OMAP_DSS_ROT_180 + 4:
1511 *offset1 = screen_width * (fbh - 1) * ps;
1512 if (field_offset)
1513 *offset0 = *offset1 - field_offset * screen_width * ps;
1514 else
1515 *offset0 = *offset1;
1516 *row_inc = pixinc(1 - screen_width * 2 -
1517 (fieldmode ? screen_width : 0),
1518 ps);
1519 *pix_inc = pixinc(1, ps);
1520 break;
1521
1522 case OMAP_DSS_ROT_270 + 4:
1523 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1524 if (field_offset)
1525 *offset0 = *offset1 - field_offset * ps;
1526 else
1527 *offset0 = *offset1;
1528 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1529 (fieldmode ? 1 : 0),
1530 ps);
1531 *pix_inc = pixinc(-screen_width, ps);
1532 break;
1533
1534 default:
1535 BUG();
1536 }
1537}
1538
ff1b2cde
SS		 1539static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1540 u16 height, u16 out_width, u16 out_height,
1541 enum omap_color_mode color_mode)
80c39712
TV		 1542{
1543 u32 fclk = 0;
1544 /* FIXME venc pclk? */
ff1b2cde 1545 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1546
1547 if (height > out_height) {
1548 /* FIXME get real display PPL */
1549 unsigned int ppl = 800;
1550
1551 tmp = pclk * height * out_width;
1552 do_div(tmp, 2 * out_height * ppl);
1553 fclk = tmp;
1554
2d9c5597
VS		 1555 if (height > 2 * out_height) {
1556 if (ppl == out_width)
1557 return 0;
1558
80c39712
TV		 1559 tmp = pclk * (height - 2 * out_height) * out_width;
1560 do_div(tmp, 2 * out_height * (ppl - out_width));
1561 fclk = max(fclk, (u32) tmp);
1562 }
1563 }
1564
1565 if (width > out_width) {
1566 tmp = pclk * width;
1567 do_div(tmp, out_width);
1568 fclk = max(fclk, (u32) tmp);
1569
1570 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1571 fclk <<= 1;
1572 }
1573
1574 return fclk;
1575}
1576
ff1b2cde
SS		 1577static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1578 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1579{
1580 unsigned int hf, vf;
1581
1582 /*
1583 * FIXME how to determine the 'A' factor
1584 * for the no downscaling case ?
1585 */
1586
1587 if (width > 3 * out_width)
1588 hf = 4;
1589 else if (width > 2 * out_width)
1590 hf = 3;
1591 else if (width > out_width)
1592 hf = 2;
1593 else
1594 hf = 1;
1595
1596 if (height > out_height)
1597 vf = 2;
1598 else
1599 vf = 1;
1600
1601 /* FIXME venc pclk? */
ff1b2cde 1602 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1603}
1604
1605void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1606{
1607 enable_clocks(1);
1608 _dispc_set_channel_out(plane, channel_out);
1609 enable_clocks(0);
1610}
1611
1612static int _dispc_setup_plane(enum omap_plane plane,
1613 u32 paddr, u16 screen_width,
1614 u16 pos_x, u16 pos_y,
1615 u16 width, u16 height,
1616 u16 out_width, u16 out_height,
1617 enum omap_color_mode color_mode,
1618 bool ilace,
1619 enum omap_dss_rotation_type rotation_type,
1620 u8 rotation, int mirror,
18faa1b6
SS		 1621 u8 global_alpha, u8 pre_mult_alpha,
1622 enum omap_channel channel)
80c39712
TV		 1623{
1624 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1625 bool five_taps = 0;
1626 bool fieldmode = 0;
1627 int cconv = 0;
1628 unsigned offset0, offset1;
1629 s32 row_inc;
1630 s32 pix_inc;
1631 u16 frame_height = height;
1632 unsigned int field_offset = 0;
1633
1634 if (paddr == 0)
1635 return -EINVAL;
1636
1637 if (ilace && height == out_height)
1638 fieldmode = 1;
1639
1640 if (ilace) {
1641 if (fieldmode)
1642 height /= 2;
1643 pos_y /= 2;
1644 out_height /= 2;
1645
1646 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1647 "out_height %d\n",
1648 height, pos_y, out_height);
1649 }
1650
8dad2ab6
AT		 1651 if (!dss_feat_color_mode_supported(plane, color_mode))
1652 return -EINVAL;
1653
80c39712
TV		 1654 if (plane == OMAP_DSS_GFX) {
1655 if (width != out_width || height != out_height)
1656 return -EINVAL;
80c39712
TV		 1657 } else {
1658 /* video plane */
1659
1660 unsigned long fclk = 0;
1661
1662 if (out_width < width / maxdownscale ||
1663 out_width > width * 8)
1664 return -EINVAL;
1665
1666 if (out_height < height / maxdownscale ||
1667 out_height > height * 8)
1668 return -EINVAL;
1669
8dad2ab6
AT		 1670 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1671 color_mode == OMAP_DSS_COLOR_UYVY)
80c39712 1672 cconv = 1;
80c39712
TV		 1673
1674 /* Must use 5-tap filter? */
1675 five_taps = height > out_height * 2;
1676
1677 if (!five_taps) {
18faa1b6
SS		 1678 fclk = calc_fclk(channel, width, height, out_width,
1679 out_height);
80c39712
TV		 1680
1681 /* Try 5-tap filter if 3-tap fclk is too high */
1682 if (cpu_is_omap34xx() && height > out_height &&
1683 fclk > dispc_fclk_rate())
1684 five_taps = true;
1685 }
1686
1687 if (width > (2048 >> five_taps)) {
1688 DSSERR("failed to set up scaling, fclk too low\n");
1689 return -EINVAL;
1690 }
1691
1692 if (five_taps)
18faa1b6
SS		 1693 fclk = calc_fclk_five_taps(channel, width, height,
1694 out_width, out_height, color_mode);
80c39712
TV		 1695
1696 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1697 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1698
2d9c5597 1699 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1700 DSSERR("failed to set up scaling, "
1701 "required fclk rate = %lu Hz, "
1702 "current fclk rate = %lu Hz\n",
1703 fclk, dispc_fclk_rate());
1704 return -EINVAL;
1705 }
1706 }
1707
1708 if (ilace && !fieldmode) {
1709 /*
1710 * when downscaling the bottom field may have to start several
1711 * source lines below the top field. Unfortunately ACCUI
1712 * registers will only hold the fractional part of the offset
1713 * so the integer part must be added to the base address of the
1714 * bottom field.
1715 */
1716 if (!height || height == out_height)
1717 field_offset = 0;
1718 else
1719 field_offset = height / out_height / 2;
1720 }
1721
1722 /* Fields are independent but interleaved in memory. */
1723 if (fieldmode)
1724 field_offset = 1;
1725
1726 if (rotation_type == OMAP_DSS_ROT_DMA)
1727 calc_dma_rotation_offset(rotation, mirror,
1728 screen_width, width, frame_height, color_mode,
1729 fieldmode, field_offset,
1730 &offset0, &offset1, &row_inc, &pix_inc);
1731 else
1732 calc_vrfb_rotation_offset(rotation, mirror,
1733 screen_width, width, frame_height, color_mode,
1734 fieldmode, field_offset,
1735 &offset0, &offset1, &row_inc, &pix_inc);
1736
1737 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1738 offset0, offset1, row_inc, pix_inc);
1739
1740 _dispc_set_color_mode(plane, color_mode);
1741
1742 _dispc_set_plane_ba0(plane, paddr + offset0);
1743 _dispc_set_plane_ba1(plane, paddr + offset1);
1744
1745 _dispc_set_row_inc(plane, row_inc);
1746 _dispc_set_pix_inc(plane, pix_inc);
1747
1748 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1749 out_width, out_height);
1750
1751 _dispc_set_plane_pos(plane, pos_x, pos_y);
1752
1753 _dispc_set_pic_size(plane, width, height);
1754
1755 if (plane != OMAP_DSS_GFX) {
1756 _dispc_set_scaling(plane, width, height,
1757 out_width, out_height,
1758 ilace, five_taps, fieldmode);
1759 _dispc_set_vid_size(plane, out_width, out_height);
1760 _dispc_set_vid_color_conv(plane, cconv);
1761 }
1762
1763 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1764
fd28a390
R		 1765 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1766 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 1767
1768 return 0;
1769}
1770
1771static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1772{
9b372c2d 1773 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
80c39712
TV		 1774}
1775
1776static void dispc_disable_isr(void *data, u32 mask)
1777{
1778 struct completion *compl = data;
1779 complete(compl);
1780}
1781
2a205f34 1782static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1783{
2a205f34
SS		 1784 if (channel == OMAP_DSS_CHANNEL_LCD2)
1785 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1786 else
1787 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1788}
1789
2a205f34 1790static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1791{
1792 struct completion frame_done_completion;
1793 bool is_on;
1794 int r;
2a205f34 1795 u32 irq;
80c39712
TV		 1796
1797 enable_clocks(1);
1798
1799 /* When we disable LCD output, we need to wait until frame is done.
1800 * Otherwise the DSS is still working, and turning off the clocks
1801 * prevents DSS from going to OFF mode */
2a205f34
SS		 1802 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1803 REG_GET(DISPC_CONTROL2, 0, 0) :
1804 REG_GET(DISPC_CONTROL, 0, 0);
1805
1806 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1807 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1808
1809 if (!enable && is_on) {
1810 init_completion(&frame_done_completion);
1811
1812 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1813 &frame_done_completion, irq);
80c39712
TV		 1814
1815 if (r)
1816 DSSERR("failed to register FRAMEDONE isr\n");
1817 }
1818
2a205f34 1819 _enable_lcd_out(channel, enable);
80c39712
TV		 1820
1821 if (!enable && is_on) {
1822 if (!wait_for_completion_timeout(&frame_done_completion,
1823 msecs_to_jiffies(100)))
1824 DSSERR("timeout waiting for FRAME DONE\n");
1825
1826 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1827 &frame_done_completion, irq);
80c39712
TV		 1828
1829 if (r)
1830 DSSERR("failed to unregister FRAMEDONE isr\n");
1831 }
1832
1833 enable_clocks(0);
1834}
1835
1836static void _enable_digit_out(bool enable)
1837{
1838 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1839}
1840
a2faee84 1841static void dispc_enable_digit_out(bool enable)
80c39712
TV		 1842{
1843 struct completion frame_done_completion;
1844 int r;
1845
1846 enable_clocks(1);
1847
1848 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1849 enable_clocks(0);
1850 return;
1851 }
1852
1853 if (enable) {
1854 unsigned long flags;
1855 /* When we enable digit output, we'll get an extra digit
1856 * sync lost interrupt, that we need to ignore */
1857 spin_lock_irqsave(&dispc.irq_lock, flags);
1858 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1859 _omap_dispc_set_irqs();
1860 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1861 }
1862
1863 /* When we disable digit output, we need to wait until fields are done.
1864 * Otherwise the DSS is still working, and turning off the clocks
1865 * prevents DSS from going to OFF mode. And when enabling, we need to
1866 * wait for the extra sync losts */
1867 init_completion(&frame_done_completion);
1868
1869 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1870 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1871 if (r)
1872 DSSERR("failed to register EVSYNC isr\n");
1873
1874 _enable_digit_out(enable);
1875
1876 /* XXX I understand from TRM that we should only wait for the
1877 * current field to complete. But it seems we have to wait
1878 * for both fields */
1879 if (!wait_for_completion_timeout(&frame_done_completion,
1880 msecs_to_jiffies(100)))
1881 DSSERR("timeout waiting for EVSYNC\n");
1882
1883 if (!wait_for_completion_timeout(&frame_done_completion,
1884 msecs_to_jiffies(100)))
1885 DSSERR("timeout waiting for EVSYNC\n");
1886
1887 r = omap_dispc_unregister_isr(dispc_disable_isr,
1888 &frame_done_completion,
1889 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1890 if (r)
1891 DSSERR("failed to unregister EVSYNC isr\n");
1892
1893 if (enable) {
1894 unsigned long flags;
1895 spin_lock_irqsave(&dispc.irq_lock, flags);
1896 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 1897 if (dss_has_feature(FEAT_MGR_LCD2))
1898 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 1899 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1900 _omap_dispc_set_irqs();
1901 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1902 }
1903
1904 enable_clocks(0);
1905}
1906
a2faee84
TV		 1907bool dispc_is_channel_enabled(enum omap_channel channel)
1908{
1909 if (channel == OMAP_DSS_CHANNEL_LCD)
1910 return !!REG_GET(DISPC_CONTROL, 0, 0);
1911 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1912 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 1913 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1914 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 1915 else
1916 BUG();
1917}
1918
1919void dispc_enable_channel(enum omap_channel channel, bool enable)
1920{
2a205f34
SS		 1921 if (channel == OMAP_DSS_CHANNEL_LCD ||
1922 channel == OMAP_DSS_CHANNEL_LCD2)
1923 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 1924 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1925 dispc_enable_digit_out(enable);
1926 else
1927 BUG();
1928}
1929
80c39712
TV		 1930void dispc_lcd_enable_signal_polarity(bool act_high)
1931{
6ced40bf
AT		 1932 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1933 return;
1934
80c39712
TV		 1935 enable_clocks(1);
1936 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1937 enable_clocks(0);
1938}
1939
1940void dispc_lcd_enable_signal(bool enable)
1941{
6ced40bf
AT		 1942 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1943 return;
1944
80c39712
TV		 1945 enable_clocks(1);
1946 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1947 enable_clocks(0);
1948}
1949
1950void dispc_pck_free_enable(bool enable)
1951{
6ced40bf
AT		 1952 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1953 return;
1954
80c39712
TV		 1955 enable_clocks(1);
1956 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1957 enable_clocks(0);
1958}
1959
64ba4f74 1960void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712
TV		 1961{
1962 enable_clocks(1);
2a205f34
SS		 1963 if (channel == OMAP_DSS_CHANNEL_LCD2)
1964 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1965 else
1966 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 1967 enable_clocks(0);
1968}
1969
1970
64ba4f74
SS		 1971void dispc_set_lcd_display_type(enum omap_channel channel,
1972 enum omap_lcd_display_type type)
80c39712
TV		 1973{
1974 int mode;
1975
1976 switch (type) {
1977 case OMAP_DSS_LCD_DISPLAY_STN:
1978 mode = 0;
1979 break;
1980
1981 case OMAP_DSS_LCD_DISPLAY_TFT:
1982 mode = 1;
1983 break;
1984
1985 default:
1986 BUG();
1987 return;
1988 }
1989
1990 enable_clocks(1);
2a205f34
SS		 1991 if (channel == OMAP_DSS_CHANNEL_LCD2)
1992 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
1993 else
1994 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 1995 enable_clocks(0);
1996}
1997
1998void dispc_set_loadmode(enum omap_dss_load_mode mode)
1999{
2000 enable_clocks(1);
2001 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2002 enable_clocks(0);
2003}
2004
2005
2006void dispc_set_default_color(enum omap_channel channel, u32 color)
2007{
80c39712 2008 enable_clocks(1);
8613b000 2009 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2010 enable_clocks(0);
2011}
2012
2013u32 dispc_get_default_color(enum omap_channel channel)
2014{
80c39712
TV		 2015 u32 l;
2016
2017 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2018 channel != OMAP_DSS_CHANNEL_LCD &&
2019 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712
TV		 2020
2021 enable_clocks(1);
8613b000 2022 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2023 enable_clocks(0);
2024
2025 return l;
2026}
2027
2028void dispc_set_trans_key(enum omap_channel ch,
2029 enum omap_dss_trans_key_type type,
2030 u32 trans_key)
2031{
80c39712
TV		 2032 enable_clocks(1);
2033 if (ch == OMAP_DSS_CHANNEL_LCD)
2034 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2035 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2036 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2037 else /* OMAP_DSS_CHANNEL_LCD2 */
2038 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2039
8613b000 2040 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2041 enable_clocks(0);
2042}
2043
2044void dispc_get_trans_key(enum omap_channel ch,
2045 enum omap_dss_trans_key_type *type,
2046 u32 *trans_key)
2047{
80c39712
TV		 2048 enable_clocks(1);
2049 if (type) {
2050 if (ch == OMAP_DSS_CHANNEL_LCD)
2051 *type = REG_GET(DISPC_CONFIG, 11, 11);
2052 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2053 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2054 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2055 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2056 else
2057 BUG();
2058 }
2059
2060 if (trans_key)
8613b000 2061 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2062 enable_clocks(0);
2063}
2064
2065void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2066{
2067 enable_clocks(1);
2068 if (ch == OMAP_DSS_CHANNEL_LCD)
2069 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2070 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2071 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2072 else /* OMAP_DSS_CHANNEL_LCD2 */
2073 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2074 enable_clocks(0);
2075}
2076void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2077{
a0acb557 2078 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2079 return;
2080
2081 enable_clocks(1);
2082 if (ch == OMAP_DSS_CHANNEL_LCD)
2083 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2084 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2085 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2086 else /* OMAP_DSS_CHANNEL_LCD2 */
2087 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2088 enable_clocks(0);
2089}
2090bool dispc_alpha_blending_enabled(enum omap_channel ch)
2091{
2092 bool enabled;
2093
a0acb557 2094 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2095 return false;
2096
2097 enable_clocks(1);
2098 if (ch == OMAP_DSS_CHANNEL_LCD)
2099 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2100 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2101 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2102 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2103 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2104 else
2105 BUG();
2106 enable_clocks(0);
2107
2108 return enabled;
80c39712
TV		 2109}
2110
2111
2112bool dispc_trans_key_enabled(enum omap_channel ch)
2113{
2114 bool enabled;
2115
2116 enable_clocks(1);
2117 if (ch == OMAP_DSS_CHANNEL_LCD)
2118 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2119 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2120 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2121 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2122 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2123 else
2124 BUG();
2125 enable_clocks(0);
2126
2127 return enabled;
2128}
2129
2130
64ba4f74 2131void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2132{
2133 int code;
2134
2135 switch (data_lines) {
2136 case 12:
2137 code = 0;
2138 break;
2139 case 16:
2140 code = 1;
2141 break;
2142 case 18:
2143 code = 2;
2144 break;
2145 case 24:
2146 code = 3;
2147 break;
2148 default:
2149 BUG();
2150 return;
2151 }
2152
2153 enable_clocks(1);
2a205f34
SS		 2154 if (channel == OMAP_DSS_CHANNEL_LCD2)
2155 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2156 else
2157 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2158 enable_clocks(0);
2159}
2160
64ba4f74
SS		 2161void dispc_set_parallel_interface_mode(enum omap_channel channel,
2162 enum omap_parallel_interface_mode mode)
80c39712
TV		 2163{
2164 u32 l;
2165 int stallmode;
2166 int gpout0 = 1;
2167 int gpout1;
2168
2169 switch (mode) {
2170 case OMAP_DSS_PARALLELMODE_BYPASS:
2171 stallmode = 0;
2172 gpout1 = 1;
2173 break;
2174
2175 case OMAP_DSS_PARALLELMODE_RFBI:
2176 stallmode = 1;
2177 gpout1 = 0;
2178 break;
2179
2180 case OMAP_DSS_PARALLELMODE_DSI:
2181 stallmode = 1;
2182 gpout1 = 1;
2183 break;
2184
2185 default:
2186 BUG();
2187 return;
2188 }
2189
2190 enable_clocks(1);
2191
2a205f34
SS		 2192 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2193 l = dispc_read_reg(DISPC_CONTROL2);
2194 l = FLD_MOD(l, stallmode, 11, 11);
2195 dispc_write_reg(DISPC_CONTROL2, l);
2196 } else {
2197 l = dispc_read_reg(DISPC_CONTROL);
2198 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2199 l = FLD_MOD(l, gpout0, 15, 15);
2200 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2201 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2202 }
80c39712
TV		 2203
2204 enable_clocks(0);
2205}
2206
2207static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2208 int vsw, int vfp, int vbp)
2209{
2210 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2211 if (hsw < 1 || hsw > 64 ||
2212 hfp < 1 || hfp > 256 ||
2213 hbp < 1 || hbp > 256 ||
2214 vsw < 1 || vsw > 64 ||
2215 vfp < 0 || vfp > 255 ||
2216 vbp < 0 || vbp > 255)
2217 return false;
2218 } else {
2219 if (hsw < 1 || hsw > 256 ||
2220 hfp < 1 || hfp > 4096 ||
2221 hbp < 1 || hbp > 4096 ||
2222 vsw < 1 || vsw > 256 ||
2223 vfp < 0 || vfp > 4095 ||
2224 vbp < 0 || vbp > 4095)
2225 return false;
2226 }
2227
2228 return true;
2229}
2230
2231bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2232{
2233 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2234 timings->hbp, timings->vsw,
2235 timings->vfp, timings->vbp);
2236}
2237
64ba4f74
SS		 2238static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2239 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2240{
2241 u32 timing_h, timing_v;
2242
2243 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2244 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2245 FLD_VAL(hbp-1, 27, 20);
2246
2247 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2248 FLD_VAL(vbp, 27, 20);
2249 } else {
2250 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2251 FLD_VAL(hbp-1, 31, 20);
2252
2253 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2254 FLD_VAL(vbp, 31, 20);
2255 }
2256
2257 enable_clocks(1);
64ba4f74
SS		 2258 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2259 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2260 enable_clocks(0);
2261}
2262
2263/* change name to mode? */
64ba4f74
SS		 2264void dispc_set_lcd_timings(enum omap_channel channel,
2265 struct omap_video_timings *timings)
80c39712
TV		 2266{
2267 unsigned xtot, ytot;
2268 unsigned long ht, vt;
2269
2270 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2271 timings->hbp, timings->vsw,
2272 timings->vfp, timings->vbp))
2273 BUG();
2274
64ba4f74
SS		 2275 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2276 timings->hbp, timings->vsw, timings->vfp,
2277 timings->vbp);
80c39712 2278
64ba4f74 2279 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2280
2281 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2282 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2283
2284 ht = (timings->pixel_clock * 1000) / xtot;
2285 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2286
2a205f34
SS		 2287 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2288 timings->y_res);
80c39712
TV		 2289 DSSDBG("pck %u\n", timings->pixel_clock);
2290 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2291 timings->hsw, timings->hfp, timings->hbp,
2292 timings->vsw, timings->vfp, timings->vbp);
2293
2294 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2295}
2296
ff1b2cde
SS		 2297static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2298 u16 pck_div)
80c39712
TV		 2299{
2300 BUG_ON(lck_div < 1);
2301 BUG_ON(pck_div < 2);
2302
2303 enable_clocks(1);
ce7fa5eb 2304 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712
TV		 2305 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2306 enable_clocks(0);
2307}
2308
2a205f34
SS		 2309static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2310 int *pck_div)
80c39712
TV		 2311{
2312 u32 l;
ce7fa5eb 2313 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2314 *lck_div = FLD_GET(l, 23, 16);
2315 *pck_div = FLD_GET(l, 7, 0);
2316}
2317
2318unsigned long dispc_fclk_rate(void)
2319{
a72b64b9 2320 struct platform_device *dsidev;
80c39712
TV		 2321 unsigned long r = 0;
2322
66534e8e 2323 switch (dss_get_dispc_clk_source()) {
89a35e51 2324 case OMAP_DSS_CLK_SRC_FCK:
6af9cd14 2325 r = dss_clk_get_rate(DSS_CLK_FCK);
66534e8e 2326 break;
89a35e51 2327 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2328 dsidev = dsi_get_dsidev_from_id(0);
2329 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2330 break;
5a8b572d
AT		 2331 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2332 dsidev = dsi_get_dsidev_from_id(1);
2333 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2334 break;
66534e8e
TA		 2335 default:
2336 BUG();
2337 }
2338
80c39712
TV		 2339 return r;
2340}
2341
ff1b2cde 2342unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712 2343{
a72b64b9 2344 struct platform_device *dsidev;
80c39712
TV		 2345 int lcd;
2346 unsigned long r;
2347 u32 l;
2348
ce7fa5eb 2349 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2350
2351 lcd = FLD_GET(l, 23, 16);
2352
ea75159e 2353 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2354 case OMAP_DSS_CLK_SRC_FCK:
ea75159e
TA		 2355 r = dss_clk_get_rate(DSS_CLK_FCK);
2356 break;
89a35e51 2357 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2358 dsidev = dsi_get_dsidev_from_id(0);
2359 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2360 break;
5a8b572d
AT		 2361 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2362 dsidev = dsi_get_dsidev_from_id(1);
2363 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2364 break;
ea75159e
TA		 2365 default:
2366 BUG();
2367 }
80c39712
TV		 2368
2369 return r / lcd;
2370}
2371
ff1b2cde 2372unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712 2373{
ea75159e 2374 int pcd;
80c39712
TV		 2375 unsigned long r;
2376 u32 l;
2377
ce7fa5eb 2378 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2379
80c39712
TV		 2380 pcd = FLD_GET(l, 7, 0);
2381
ea75159e 2382 r = dispc_lclk_rate(channel);
80c39712 2383
ea75159e 2384 return r / pcd;
80c39712
TV		 2385}
2386
2387void dispc_dump_clocks(struct seq_file *s)
2388{
2389 int lcd, pcd;
0cf35df3 2390 u32 l;
89a35e51
AT		 2391 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2392 enum omap_dss_clk_source lcd_clk_src;
80c39712
TV		 2393
2394 enable_clocks(1);
2395
80c39712
TV		 2396 seq_printf(s, "- DISPC -\n");
2397
067a57e4
AT		 2398 seq_printf(s, "dispc fclk source = %s (%s)\n",
2399 dss_get_generic_clk_source_name(dispc_clk_src),
2400 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2401
2402 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2403
0cf35df3
MR		 2404 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2405 seq_printf(s, "- DISPC-CORE-CLK -\n");
2406 l = dispc_read_reg(DISPC_DIVISOR);
2407 lcd = FLD_GET(l, 23, 16);
2408
2409 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2410 (dispc_fclk_rate()/lcd), lcd);
2411 }
2a205f34
SS		 2412 seq_printf(s, "- LCD1 -\n");
2413
ea75159e
TA		 2414 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2415
2416 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2417 dss_get_generic_clk_source_name(lcd_clk_src),
2418 dss_feat_get_clk_source_name(lcd_clk_src));
2419
2a205f34
SS		 2420 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2421
ff1b2cde
SS		 2422 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2423 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2424 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2425 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2426 if (dss_has_feature(FEAT_MGR_LCD2)) {
2427 seq_printf(s, "- LCD2 -\n");
2428
ea75159e
TA		 2429 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2430
2431 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2432 dss_get_generic_clk_source_name(lcd_clk_src),
2433 dss_feat_get_clk_source_name(lcd_clk_src));
2434
2a205f34 2435 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2436
2a205f34
SS		 2437 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2438 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2439 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2440 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2441 }
80c39712
TV		 2442 enable_clocks(0);
2443}
2444
dfc0fd8d
TV		 2445#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2446void dispc_dump_irqs(struct seq_file *s)
2447{
2448 unsigned long flags;
2449 struct dispc_irq_stats stats;
2450
2451 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2452
2453 stats = dispc.irq_stats;
2454 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2455 dispc.irq_stats.last_reset = jiffies;
2456
2457 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2458
2459 seq_printf(s, "period %u ms\n",
2460 jiffies_to_msecs(jiffies - stats.last_reset));
2461
2462 seq_printf(s, "irqs %d\n", stats.irq_count);
2463#define PIS(x) \
2464 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2465
2466 PIS(FRAMEDONE);
2467 PIS(VSYNC);
2468 PIS(EVSYNC_EVEN);
2469 PIS(EVSYNC_ODD);
2470 PIS(ACBIAS_COUNT_STAT);
2471 PIS(PROG_LINE_NUM);
2472 PIS(GFX_FIFO_UNDERFLOW);
2473 PIS(GFX_END_WIN);
2474 PIS(PAL_GAMMA_MASK);
2475 PIS(OCP_ERR);
2476 PIS(VID1_FIFO_UNDERFLOW);
2477 PIS(VID1_END_WIN);
2478 PIS(VID2_FIFO_UNDERFLOW);
2479 PIS(VID2_END_WIN);
2480 PIS(SYNC_LOST);
2481 PIS(SYNC_LOST_DIGIT);
2482 PIS(WAKEUP);
2a205f34
SS		 2483 if (dss_has_feature(FEAT_MGR_LCD2)) {
2484 PIS(FRAMEDONE2);
2485 PIS(VSYNC2);
2486 PIS(ACBIAS_COUNT_STAT2);
2487 PIS(SYNC_LOST2);
2488 }
dfc0fd8d
TV		 2489#undef PIS
2490}
dfc0fd8d
TV		 2491#endif
2492
80c39712
TV		 2493void dispc_dump_regs(struct seq_file *s)
2494{
9b372c2d 2495#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2496
6af9cd14 2497 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2498
2499 DUMPREG(DISPC_REVISION);
2500 DUMPREG(DISPC_SYSCONFIG);
2501 DUMPREG(DISPC_SYSSTATUS);
2502 DUMPREG(DISPC_IRQSTATUS);
2503 DUMPREG(DISPC_IRQENABLE);
2504 DUMPREG(DISPC_CONTROL);
2505 DUMPREG(DISPC_CONFIG);
2506 DUMPREG(DISPC_CAPABLE);
702d1448
AT		 2507 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
2508 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
2509 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
2510 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712
TV		 2511 DUMPREG(DISPC_LINE_STATUS);
2512 DUMPREG(DISPC_LINE_NUMBER);
702d1448
AT		 2513 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
2514 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
2515 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
2516 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
80c39712 2517 DUMPREG(DISPC_GLOBAL_ALPHA);
702d1448
AT		 2518 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
2519 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34
SS		 2520 if (dss_has_feature(FEAT_MGR_LCD2)) {
2521 DUMPREG(DISPC_CONTROL2);
2522 DUMPREG(DISPC_CONFIG2);
702d1448
AT		 2523 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
2524 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
2525 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
2526 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
2527 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
2528 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2529 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
2a205f34 2530 }
80c39712 2531
9b372c2d
AT		 2532 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
2533 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
2534 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
2535 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
2536 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
2537 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
2538 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
2539 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
2540 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
2541 DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
2542 DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
80c39712 2543
702d1448
AT		 2544 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
2545 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
2546 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 2547
702d1448
AT		 2548 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
2549 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
2550 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
2a205f34 2551 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 2552 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
2553 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
2554 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 2555
702d1448
AT		 2556 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2557 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
2558 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
2a205f34 2559 }
80c39712 2560
9b372c2d
AT		 2561 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
2562
2563 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
2564 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
2565 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
2566 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
2567 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
2568 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
2569 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
2570 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
2571 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
2572 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
2573 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
2574 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
2575 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
2576
2577 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
2578 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
2579 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
2580 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
2581 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
2582 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
2583 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
2584 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
2585 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
2586 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
2587 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
2588 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
2589 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
2590
2591 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
2592 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
2593 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
2594 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
2595 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
2596 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
2597 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
2598 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
2599 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
2600 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
2601 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
2602 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
2603 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
2604 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
2605 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
2606 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
2607 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
2608 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
2609 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
2610 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
2611 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
2612 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
2613 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
2614 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
2615 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
2616 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
2617 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
2618 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
2619 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
2620
ab5ca071
AJ		 2621 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2622 DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
2623 DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
2624 DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
2625 DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
2626 DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
2627
2628 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
2629 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
2630 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
2631 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
2632 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
2633 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
2634 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
2635 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));
2636
2637 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
2638 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
2639 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
2640 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
2641 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
2642 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
2643 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
2644 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));
2645
2646 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
2647 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
2648 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
2649 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
2650 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
2651 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
2652 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
2653 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
2654 }
2655 if (dss_has_feature(FEAT_ATTR2))
2656 DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
2657
2658
9b372c2d
AT		 2659 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
2660 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
2661 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
2662 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
2663 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
2664 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
2665 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
2666 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
2667 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
2668 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
2669 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
2670 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
2671 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
2672 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
2673 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
2674 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
2675 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
2676 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
2677 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
2678 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
2679 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
2680 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
2681 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
2682 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
2683 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
2684 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
2685 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
2686 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
2687 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
2688
ab5ca071
AJ		 2689 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2690 DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
2691 DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
2692 DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
2693 DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
2694 DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
2695
2696 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
2697 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
2698 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
2699 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
2700 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
2701 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
2702 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
2703 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));
2704
2705 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
2706 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
2707 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
2708 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
2709 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
2710 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
2711 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
2712 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));
2713
2714 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
2715 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
2716 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
2717 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
2718 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
2719 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
2720 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
2721 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
2722 }
2723 if (dss_has_feature(FEAT_ATTR2))
2724 DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
2725
9b372c2d
AT		 2726 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
2727 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
80c39712 2728
6af9cd14 2729 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2730#undef DUMPREG
2731}
2732
ff1b2cde
SS		 2733static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2734 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2735{
2736 u32 l = 0;
2737
2738 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2739 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2740
2741 l |= FLD_VAL(onoff, 17, 17);
2742 l |= FLD_VAL(rf, 16, 16);
2743 l |= FLD_VAL(ieo, 15, 15);
2744 l |= FLD_VAL(ipc, 14, 14);
2745 l |= FLD_VAL(ihs, 13, 13);
2746 l |= FLD_VAL(ivs, 12, 12);
2747 l |= FLD_VAL(acbi, 11, 8);
2748 l |= FLD_VAL(acb, 7, 0);
2749
2750 enable_clocks(1);
ff1b2cde 2751 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2752 enable_clocks(0);
2753}
2754
ff1b2cde
SS		 2755void dispc_set_pol_freq(enum omap_channel channel,
2756 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2757{
ff1b2cde 2758 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2759 (config & OMAP_DSS_LCD_RF) != 0,
2760 (config & OMAP_DSS_LCD_IEO) != 0,
2761 (config & OMAP_DSS_LCD_IPC) != 0,
2762 (config & OMAP_DSS_LCD_IHS) != 0,
2763 (config & OMAP_DSS_LCD_IVS) != 0,
2764 acbi, acb);
2765}
2766
2767/* with fck as input clock rate, find dispc dividers that produce req_pck */
2768void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2769 struct dispc_clock_info *cinfo)
2770{
2771 u16 pcd_min = is_tft ? 2 : 3;
2772 unsigned long best_pck;
2773 u16 best_ld, cur_ld;
2774 u16 best_pd, cur_pd;
2775
2776 best_pck = 0;
2777 best_ld = 0;
2778 best_pd = 0;
2779
2780 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2781 unsigned long lck = fck / cur_ld;
2782
2783 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2784 unsigned long pck = lck / cur_pd;
2785 long old_delta = abs(best_pck - req_pck);
2786 long new_delta = abs(pck - req_pck);
2787
2788 if (best_pck == 0 || new_delta < old_delta) {
2789 best_pck = pck;
2790 best_ld = cur_ld;
2791 best_pd = cur_pd;
2792
2793 if (pck == req_pck)
2794 goto found;
2795 }
2796
2797 if (pck < req_pck)
2798 break;
2799 }
2800
2801 if (lck / pcd_min < req_pck)
2802 break;
2803 }
2804
2805found:
2806 cinfo->lck_div = best_ld;
2807 cinfo->pck_div = best_pd;
2808 cinfo->lck = fck / cinfo->lck_div;
2809 cinfo->pck = cinfo->lck / cinfo->pck_div;
2810}
2811
2812/* calculate clock rates using dividers in cinfo */
2813int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2814 struct dispc_clock_info *cinfo)
2815{
2816 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2817 return -EINVAL;
2818 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2819 return -EINVAL;
2820
2821 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2822 cinfo->pck = cinfo->lck / cinfo->pck_div;
2823
2824 return 0;
2825}
2826
ff1b2cde
SS		 2827int dispc_set_clock_div(enum omap_channel channel,
2828 struct dispc_clock_info *cinfo)
80c39712
TV		 2829{
2830 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2831 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2832
ff1b2cde 2833 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2834
2835 return 0;
2836}
2837
ff1b2cde
SS		 2838int dispc_get_clock_div(enum omap_channel channel,
2839 struct dispc_clock_info *cinfo)
80c39712
TV		 2840{
2841 unsigned long fck;
2842
2843 fck = dispc_fclk_rate();
2844
ce7fa5eb
MR		 2845 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2846 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2847
2848 cinfo->lck = fck / cinfo->lck_div;
2849 cinfo->pck = cinfo->lck / cinfo->pck_div;
2850
2851 return 0;
2852}
2853
2854/* dispc.irq_lock has to be locked by the caller */
2855static void _omap_dispc_set_irqs(void)
2856{
2857 u32 mask;
2858 u32 old_mask;
2859 int i;
2860 struct omap_dispc_isr_data *isr_data;
2861
2862 mask = dispc.irq_error_mask;
2863
2864 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2865 isr_data = &dispc.registered_isr[i];
2866
2867 if (isr_data->isr == NULL)
2868 continue;
2869
2870 mask |= isr_data->mask;
2871 }
2872
2873 enable_clocks(1);
2874
2875 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2876 /* clear the irqstatus for newly enabled irqs */
2877 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2878
2879 dispc_write_reg(DISPC_IRQENABLE, mask);
2880
2881 enable_clocks(0);
2882}
2883
2884int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2885{
2886 int i;
2887 int ret;
2888 unsigned long flags;
2889 struct omap_dispc_isr_data *isr_data;
2890
2891 if (isr == NULL)
2892 return -EINVAL;
2893
2894 spin_lock_irqsave(&dispc.irq_lock, flags);
2895
2896 /* check for duplicate entry */
2897 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2898 isr_data = &dispc.registered_isr[i];
2899 if (isr_data->isr == isr && isr_data->arg == arg &&
2900 isr_data->mask == mask) {
2901 ret = -EINVAL;
2902 goto err;
2903 }
2904 }
2905
2906 isr_data = NULL;
2907 ret = -EBUSY;
2908
2909 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2910 isr_data = &dispc.registered_isr[i];
2911
2912 if (isr_data->isr != NULL)
2913 continue;
2914
2915 isr_data->isr = isr;
2916 isr_data->arg = arg;
2917 isr_data->mask = mask;
2918 ret = 0;
2919
2920 break;
2921 }
2922
b9cb0984
TV		 2923 if (ret)
2924 goto err;
2925
80c39712
TV		 2926 _omap_dispc_set_irqs();
2927
2928 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2929
2930 return 0;
2931err:
2932 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2933
2934 return ret;
2935}
2936EXPORT_SYMBOL(omap_dispc_register_isr);
2937
2938int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2939{
2940 int i;
2941 unsigned long flags;
2942 int ret = -EINVAL;
2943 struct omap_dispc_isr_data *isr_data;
2944
2945 spin_lock_irqsave(&dispc.irq_lock, flags);
2946
2947 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2948 isr_data = &dispc.registered_isr[i];
2949 if (isr_data->isr != isr || isr_data->arg != arg ||
2950 isr_data->mask != mask)
2951 continue;
2952
2953 /* found the correct isr */
2954
2955 isr_data->isr = NULL;
2956 isr_data->arg = NULL;
2957 isr_data->mask = 0;
2958
2959 ret = 0;
2960 break;
2961 }
2962
2963 if (ret == 0)
2964 _omap_dispc_set_irqs();
2965
2966 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2967
2968 return ret;
2969}
2970EXPORT_SYMBOL(omap_dispc_unregister_isr);
2971
2972#ifdef DEBUG
2973static void print_irq_status(u32 status)
2974{
2975 if ((status & dispc.irq_error_mask) == 0)
2976 return;
2977
2978 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2979
2980#define PIS(x) \
2981 if (status & DISPC_IRQ_##x) \
2982 printk(#x " ");
2983 PIS(GFX_FIFO_UNDERFLOW);
2984 PIS(OCP_ERR);
2985 PIS(VID1_FIFO_UNDERFLOW);
2986 PIS(VID2_FIFO_UNDERFLOW);
2987 PIS(SYNC_LOST);
2988 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 2989 if (dss_has_feature(FEAT_MGR_LCD2))
2990 PIS(SYNC_LOST2);
80c39712
TV		 2991#undef PIS
2992
2993 printk("\n");
2994}
2995#endif
2996
2997/* Called from dss.c. Note that we don't touch clocks here,
2998 * but we presume they are on because we got an IRQ. However,
2999 * an irq handler may turn the clocks off, so we may not have
3000 * clock later in the function. */
affe360d 3001static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3002{
3003 int i;
affe360d 3004 u32 irqstatus, irqenable;
80c39712
TV		 3005 u32 handledirqs = 0;
3006 u32 unhandled_errors;
3007 struct omap_dispc_isr_data *isr_data;
3008 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3009
3010 spin_lock(&dispc.irq_lock);
3011
3012 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3013 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3014
3015 /* IRQ is not for us */
3016 if (!(irqstatus & irqenable)) {
3017 spin_unlock(&dispc.irq_lock);
3018 return IRQ_NONE;
3019 }
80c39712 3020
dfc0fd8d
TV		 3021#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3022 spin_lock(&dispc.irq_stats_lock);
3023 dispc.irq_stats.irq_count++;
3024 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3025 spin_unlock(&dispc.irq_stats_lock);
3026#endif
3027
80c39712
TV		 3028#ifdef DEBUG
3029 if (dss_debug)
3030 print_irq_status(irqstatus);
3031#endif
3032 /* Ack the interrupt. Do it here before clocks are possibly turned
3033 * off */
3034 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3035 /* flush posted write */
3036 dispc_read_reg(DISPC_IRQSTATUS);
3037
3038 /* make a copy and unlock, so that isrs can unregister
3039 * themselves */
3040 memcpy(registered_isr, dispc.registered_isr,
3041 sizeof(registered_isr));
3042
3043 spin_unlock(&dispc.irq_lock);
3044
3045 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3046 isr_data = &registered_isr[i];
3047
3048 if (!isr_data->isr)
3049 continue;
3050
3051 if (isr_data->mask & irqstatus) {
3052 isr_data->isr(isr_data->arg, irqstatus);
3053 handledirqs |= isr_data->mask;
3054 }
3055 }
3056
3057 spin_lock(&dispc.irq_lock);
3058
3059 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3060
3061 if (unhandled_errors) {
3062 dispc.error_irqs |= unhandled_errors;
3063
3064 dispc.irq_error_mask &= ~unhandled_errors;
3065 _omap_dispc_set_irqs();
3066
3067 schedule_work(&dispc.error_work);
3068 }
3069
3070 spin_unlock(&dispc.irq_lock);
affe360d 3071
3072 return IRQ_HANDLED;
80c39712
TV		 3073}
3074
3075static void dispc_error_worker(struct work_struct *work)
3076{
3077 int i;
3078 u32 errors;
3079 unsigned long flags;
3080
3081 spin_lock_irqsave(&dispc.irq_lock, flags);
3082 errors = dispc.error_irqs;
3083 dispc.error_irqs = 0;
3084 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3085
3086 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
3087 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
3088 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3089 struct omap_overlay *ovl;
3090 ovl = omap_dss_get_overlay(i);
3091
3092 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3093 continue;
3094
3095 if (ovl->id == 0) {
3096 dispc_enable_plane(ovl->id, 0);
3097 dispc_go(ovl->manager->id);
3098 mdelay(50);
3099 break;
3100 }
3101 }
3102 }
3103
3104 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3105 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3106 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3107 struct omap_overlay *ovl;
3108 ovl = omap_dss_get_overlay(i);
3109
3110 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3111 continue;
3112
3113 if (ovl->id == 1) {
3114 dispc_enable_plane(ovl->id, 0);
3115 dispc_go(ovl->manager->id);
3116 mdelay(50);
3117 break;
3118 }
3119 }
3120 }
3121
3122 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3123 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3124 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3125 struct omap_overlay *ovl;
3126 ovl = omap_dss_get_overlay(i);
3127
3128 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3129 continue;
3130
3131 if (ovl->id == 2) {
3132 dispc_enable_plane(ovl->id, 0);
3133 dispc_go(ovl->manager->id);
3134 mdelay(50);
3135 break;
3136 }
3137 }
3138 }
3139
3140 if (errors & DISPC_IRQ_SYNC_LOST) {
3141 struct omap_overlay_manager *manager = NULL;
3142 bool enable = false;
3143
3144 DSSERR("SYNC_LOST, disabling LCD\n");
3145
3146 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3147 struct omap_overlay_manager *mgr;
3148 mgr = omap_dss_get_overlay_manager(i);
3149
3150 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3151 manager = mgr;
3152 enable = mgr->device->state ==
3153 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3154 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3155 break;
3156 }
3157 }
3158
3159 if (manager) {
37ac60e4 3160 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3161 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3162 struct omap_overlay *ovl;
3163 ovl = omap_dss_get_overlay(i);
3164
3165 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3166 continue;
3167
3168 if (ovl->id != 0 && ovl->manager == manager)
3169 dispc_enable_plane(ovl->id, 0);
3170 }
3171
3172 dispc_go(manager->id);
3173 mdelay(50);
3174 if (enable)
37ac60e4 3175 dssdev->driver->enable(dssdev);
80c39712
TV		 3176 }
3177 }
3178
3179 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3180 struct omap_overlay_manager *manager = NULL;
3181 bool enable = false;
3182
3183 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3184
3185 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3186 struct omap_overlay_manager *mgr;
3187 mgr = omap_dss_get_overlay_manager(i);
3188
3189 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3190 manager = mgr;
3191 enable = mgr->device->state ==
3192 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3193 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3194 break;
3195 }
3196 }
3197
3198 if (manager) {
37ac60e4 3199 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3200 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3201 struct omap_overlay *ovl;
3202 ovl = omap_dss_get_overlay(i);
3203
3204 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3205 continue;
3206
3207 if (ovl->id != 0 && ovl->manager == manager)
3208 dispc_enable_plane(ovl->id, 0);
3209 }
3210
3211 dispc_go(manager->id);
3212 mdelay(50);
3213 if (enable)
37ac60e4 3214 dssdev->driver->enable(dssdev);
80c39712
TV		 3215 }
3216 }
3217
2a205f34
SS		 3218 if (errors & DISPC_IRQ_SYNC_LOST2) {
3219 struct omap_overlay_manager *manager = NULL;
3220 bool enable = false;
3221
3222 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3223
3224 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3225 struct omap_overlay_manager *mgr;
3226 mgr = omap_dss_get_overlay_manager(i);
3227
3228 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3229 manager = mgr;
3230 enable = mgr->device->state ==
3231 OMAP_DSS_DISPLAY_ACTIVE;
3232 mgr->device->driver->disable(mgr->device);
3233 break;
3234 }
3235 }
3236
3237 if (manager) {
3238 struct omap_dss_device *dssdev = manager->device;
3239 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3240 struct omap_overlay *ovl;
3241 ovl = omap_dss_get_overlay(i);
3242
3243 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3244 continue;
3245
3246 if (ovl->id != 0 && ovl->manager == manager)
3247 dispc_enable_plane(ovl->id, 0);
3248 }
3249
3250 dispc_go(manager->id);
3251 mdelay(50);
3252 if (enable)
3253 dssdev->driver->enable(dssdev);
3254 }
3255 }
3256
80c39712
TV		 3257 if (errors & DISPC_IRQ_OCP_ERR) {
3258 DSSERR("OCP_ERR\n");
3259 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3260 struct omap_overlay_manager *mgr;
3261 mgr = omap_dss_get_overlay_manager(i);
3262
3263 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3264 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3265 }
3266 }
3267
3268 spin_lock_irqsave(&dispc.irq_lock, flags);
3269 dispc.irq_error_mask |= errors;
3270 _omap_dispc_set_irqs();
3271 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3272}
3273
3274int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3275{
3276 void dispc_irq_wait_handler(void *data, u32 mask)
3277 {
3278 complete((struct completion *)data);
3279 }
3280
3281 int r;
3282 DECLARE_COMPLETION_ONSTACK(completion);
3283
3284 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3285 irqmask);
3286
3287 if (r)
3288 return r;
3289
3290 timeout = wait_for_completion_timeout(&completion, timeout);
3291
3292 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3293
3294 if (timeout == 0)
3295 return -ETIMEDOUT;
3296
3297 if (timeout == -ERESTARTSYS)
3298 return -ERESTARTSYS;
3299
3300 return 0;
3301}
3302
3303int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3304 unsigned long timeout)
3305{
3306 void dispc_irq_wait_handler(void *data, u32 mask)
3307 {
3308 complete((struct completion *)data);
3309 }
3310
3311 int r;
3312 DECLARE_COMPLETION_ONSTACK(completion);
3313
3314 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3315 irqmask);
3316
3317 if (r)
3318 return r;
3319
3320 timeout = wait_for_completion_interruptible_timeout(&completion,
3321 timeout);
3322
3323 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3324
3325 if (timeout == 0)
3326 return -ETIMEDOUT;
3327
3328 if (timeout == -ERESTARTSYS)
3329 return -ERESTARTSYS;
3330
3331 return 0;
3332}
3333
3334#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3335void dispc_fake_vsync_irq(void)
3336{
3337 u32 irqstatus = DISPC_IRQ_VSYNC;
3338 int i;
3339
ab83b14c 3340 WARN_ON(!in_interrupt());
80c39712
TV		 3341
3342 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3343 struct omap_dispc_isr_data *isr_data;
3344 isr_data = &dispc.registered_isr[i];
3345
3346 if (!isr_data->isr)
3347 continue;
3348
3349 if (isr_data->mask & irqstatus)
3350 isr_data->isr(isr_data->arg, irqstatus);
3351 }
80c39712
TV		 3352}
3353#endif
3354
3355static void _omap_dispc_initialize_irq(void)
3356{
3357 unsigned long flags;
3358
3359 spin_lock_irqsave(&dispc.irq_lock, flags);
3360
3361 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3362
3363 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3364 if (dss_has_feature(FEAT_MGR_LCD2))
3365 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3366
3367 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3368 * so clear it */
3369 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3370
3371 _omap_dispc_set_irqs();
3372
3373 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3374}
3375
3376void dispc_enable_sidle(void)
3377{
3378 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3379}
3380
3381void dispc_disable_sidle(void)
3382{
3383 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3384}
3385
3386static void _omap_dispc_initial_config(void)
3387{
3388 u32 l;
3389
3390 l = dispc_read_reg(DISPC_SYSCONFIG);
3391 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3392 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3393 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3394 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3395 dispc_write_reg(DISPC_SYSCONFIG, l);
3396
0cf35df3
MR		 3397 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3398 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3399 l = dispc_read_reg(DISPC_DIVISOR);
3400 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3401 l = FLD_MOD(l, 1, 0, 0);
3402 l = FLD_MOD(l, 1, 23, 16);
3403 dispc_write_reg(DISPC_DIVISOR, l);
3404 }
3405
80c39712 3406 /* FUNCGATED */
6ced40bf
AT		 3407 if (dss_has_feature(FEAT_FUNCGATED))
3408 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3409
3410 /* L3 firewall setting: enable access to OCM RAM */
3411 /* XXX this should be somewhere in plat-omap */
3412 if (cpu_is_omap24xx())
3413 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3414
3415 _dispc_setup_color_conv_coef();
3416
3417 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3418
3419 dispc_read_plane_fifo_sizes();
3420}
3421
80c39712
TV		 3422int dispc_enable_plane(enum omap_plane plane, bool enable)
3423{
3424 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3425
3426 enable_clocks(1);
3427 _dispc_enable_plane(plane, enable);
3428 enable_clocks(0);
3429
3430 return 0;
3431}
3432
3433int dispc_setup_plane(enum omap_plane plane,
3434 u32 paddr, u16 screen_width,
3435 u16 pos_x, u16 pos_y,
3436 u16 width, u16 height,
3437 u16 out_width, u16 out_height,
3438 enum omap_color_mode color_mode,
3439 bool ilace,
3440 enum omap_dss_rotation_type rotation_type,
fd28a390 3441 u8 rotation, bool mirror, u8 global_alpha,
18faa1b6 3442 u8 pre_mult_alpha, enum omap_channel channel)
80c39712
TV		 3443{
3444 int r = 0;
3445
3446 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
18faa1b6 3447 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
80c39712
TV		 3448 plane, paddr, screen_width, pos_x, pos_y,
3449 width, height,
3450 out_width, out_height,
3451 ilace, color_mode,
18faa1b6 3452 rotation, mirror, channel);
80c39712
TV		 3453
3454 enable_clocks(1);
3455
3456 r = _dispc_setup_plane(plane,
3457 paddr, screen_width,
3458 pos_x, pos_y,
3459 width, height,
3460 out_width, out_height,
3461 color_mode, ilace,
3462 rotation_type,
3463 rotation, mirror,
fd28a390 3464 global_alpha,
18faa1b6 3465 pre_mult_alpha, channel);
80c39712
TV		 3466
3467 enable_clocks(0);
3468
3469 return r;
3470}
060b6d9c
SG		 3471
3472/* DISPC HW IP initialisation */
3473static int omap_dispchw_probe(struct platform_device *pdev)
3474{
3475 u32 rev;
affe360d 3476 int r = 0;
ea9da36a
SG		 3477 struct resource *dispc_mem;
3478
060b6d9c
SG		 3479 dispc.pdev = pdev;
3480
3481 spin_lock_init(&dispc.irq_lock);
3482
3483#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3484 spin_lock_init(&dispc.irq_stats_lock);
3485 dispc.irq_stats.last_reset = jiffies;
3486#endif
3487
3488 INIT_WORK(&dispc.error_work, dispc_error_worker);
3489
ea9da36a
SG		 3490 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3491 if (!dispc_mem) {
3492 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3493 r = -EINVAL;
3494 goto fail0;
ea9da36a
SG		 3495 }
3496 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3497 if (!dispc.base) {
3498 DSSERR("can't ioremap DISPC\n");
affe360d 3499 r = -ENOMEM;
3500 goto fail0;
3501 }
3502 dispc.irq = platform_get_irq(dispc.pdev, 0);
3503 if (dispc.irq < 0) {
3504 DSSERR("platform_get_irq failed\n");
3505 r = -ENODEV;
3506 goto fail1;
3507 }
3508
3509 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3510 "OMAP DISPC", dispc.pdev);
3511 if (r < 0) {
3512 DSSERR("request_irq failed\n");
3513 goto fail1;
060b6d9c
SG		 3514 }
3515
3516 enable_clocks(1);
3517
3518 _omap_dispc_initial_config();
3519
3520 _omap_dispc_initialize_irq();
3521
3522 dispc_save_context();
3523
3524 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3525 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3526 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3527
3528 enable_clocks(0);
3529
3530 return 0;
affe360d 3531fail1:
3532 iounmap(dispc.base);
3533fail0:
3534 return r;
060b6d9c
SG		 3535}
3536
3537static int omap_dispchw_remove(struct platform_device *pdev)
3538{
affe360d 3539 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3540 iounmap(dispc.base);
3541 return 0;
3542}
3543
3544static struct platform_driver omap_dispchw_driver = {
3545 .probe = omap_dispchw_probe,
3546 .remove = omap_dispchw_remove,
3547 .driver = {
3548 .name = "omapdss_dispc",
3549 .owner = THIS_MODULE,
3550 },
3551};
3552
3553int dispc_init_platform_driver(void)
3554{
3555 return platform_driver_register(&omap_dispchw_driver);
3556}
3557
3558void dispc_uninit_platform_driver(void)
3559{
3560 return platform_driver_unregister(&omap_dispchw_driver);
3561}
Linux kernel - Deliverables
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