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OMAPDSS: DISPC: Use a common function to set manager timings
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
80c39712
TV		 122static void _omap_dispc_set_irqs(void);
123
55978cc2 124static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 125{
55978cc2 126 __raw_writel(val, dispc.base + idx);
80c39712
TV		 127}
128
55978cc2 129static inline u32 dispc_read_reg(const u16 idx)
80c39712 130{
55978cc2 131 return __raw_readl(dispc.base + idx);
80c39712
TV		 132}
133
49ea86f3
TV		 134static int dispc_get_ctx_loss_count(void)
135{
136 struct device *dev = &dispc.pdev->dev;
137 struct omap_display_platform_data *pdata = dev->platform_data;
138 struct omap_dss_board_info *board_data = pdata->board_data;
139 int cnt;
140
141 if (!board_data->get_context_loss_count)
142 return -ENOENT;
143
144 cnt = board_data->get_context_loss_count(dev);
145
146 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
147
148 return cnt;
149}
150
80c39712 151#define SR(reg) \
55978cc2 152 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 153#define RR(reg) \
55978cc2 154 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 155
4fbafaf3 156static void dispc_save_context(void)
80c39712 157{
c6104b8e 158 int i, j;
80c39712 159
4fbafaf3
TV		 160 DSSDBG("dispc_save_context\n");
161
80c39712
TV		 162 SR(IRQENABLE);
163 SR(CONTROL);
164 SR(CONFIG);
80c39712 165 SR(LINE_NUMBER);
11354dd5
AT		 166 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
167 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 168 SR(GLOBAL_ALPHA);
2a205f34
SS		 169 if (dss_has_feature(FEAT_MGR_LCD2)) {
170 SR(CONTROL2);
2a205f34
SS		 171 SR(CONFIG2);
172 }
80c39712 173
c6104b8e
AT		 174 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
175 SR(DEFAULT_COLOR(i));
176 SR(TRANS_COLOR(i));
177 SR(SIZE_MGR(i));
178 if (i == OMAP_DSS_CHANNEL_DIGIT)
179 continue;
180 SR(TIMING_H(i));
181 SR(TIMING_V(i));
182 SR(POL_FREQ(i));
183 SR(DIVISORo(i));
184
185 SR(DATA_CYCLE1(i));
186 SR(DATA_CYCLE2(i));
187 SR(DATA_CYCLE3(i));
188
332e9d70 189 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 190 SR(CPR_COEF_R(i));
191 SR(CPR_COEF_G(i));
192 SR(CPR_COEF_B(i));
332e9d70 193 }
2a205f34 194 }
80c39712 195
c6104b8e
AT		 196 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
197 SR(OVL_BA0(i));
198 SR(OVL_BA1(i));
199 SR(OVL_POSITION(i));
200 SR(OVL_SIZE(i));
201 SR(OVL_ATTRIBUTES(i));
202 SR(OVL_FIFO_THRESHOLD(i));
203 SR(OVL_ROW_INC(i));
204 SR(OVL_PIXEL_INC(i));
205 if (dss_has_feature(FEAT_PRELOAD))
206 SR(OVL_PRELOAD(i));
207 if (i == OMAP_DSS_GFX) {
208 SR(OVL_WINDOW_SKIP(i));
209 SR(OVL_TABLE_BA(i));
210 continue;
211 }
212 SR(OVL_FIR(i));
213 SR(OVL_PICTURE_SIZE(i));
214 SR(OVL_ACCU0(i));
215 SR(OVL_ACCU1(i));
9b372c2d 216
c6104b8e
AT		 217 for (j = 0; j < 8; j++)
218 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 219
c6104b8e
AT		 220 for (j = 0; j < 8; j++)
221 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 222
c6104b8e
AT		 223 for (j = 0; j < 5; j++)
224 SR(OVL_CONV_COEF(i, j));
ab5ca071 225
c6104b8e
AT		 226 if (dss_has_feature(FEAT_FIR_COEF_V)) {
227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V(i, j));
229 }
9b372c2d 230
c6104b8e
AT		 231 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
232 SR(OVL_BA0_UV(i));
233 SR(OVL_BA1_UV(i));
234 SR(OVL_FIR2(i));
235 SR(OVL_ACCU2_0(i));
236 SR(OVL_ACCU2_1(i));
ab5ca071 237
c6104b8e
AT		 238 for (j = 0; j < 8; j++)
239 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 240
c6104b8e
AT		 241 for (j = 0; j < 8; j++)
242 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 243
c6104b8e
AT		 244 for (j = 0; j < 8; j++)
245 SR(OVL_FIR_COEF_V2(i, j));
246 }
247 if (dss_has_feature(FEAT_ATTR2))
248 SR(OVL_ATTRIBUTES2(i));
ab5ca071 249 }
0cf35df3
MR		 250
251 if (dss_has_feature(FEAT_CORE_CLK_DIV))
252 SR(DIVISOR);
49ea86f3
TV		 253
254 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
255 dispc.ctx_valid = true;
256
257 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 258}
259
4fbafaf3 260static void dispc_restore_context(void)
80c39712 261{
c6104b8e 262 int i, j, ctx;
4fbafaf3
TV		 263
264 DSSDBG("dispc_restore_context\n");
265
49ea86f3
TV		 266 if (!dispc.ctx_valid)
267 return;
268
269 ctx = dispc_get_ctx_loss_count();
270
271 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
272 return;
273
274 DSSDBG("ctx_loss_count: saved %d, current %d\n",
275 dispc.ctx_loss_cnt, ctx);
276
75c7d59d 277 /*RR(IRQENABLE);*/
80c39712
TV		 278 /*RR(CONTROL);*/
279 RR(CONFIG);
80c39712 280 RR(LINE_NUMBER);
11354dd5
AT		 281 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
282 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 283 RR(GLOBAL_ALPHA);
c6104b8e 284 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 285 RR(CONFIG2);
80c39712 286
c6104b8e
AT		 287 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
288 RR(DEFAULT_COLOR(i));
289 RR(TRANS_COLOR(i));
290 RR(SIZE_MGR(i));
291 if (i == OMAP_DSS_CHANNEL_DIGIT)
292 continue;
293 RR(TIMING_H(i));
294 RR(TIMING_V(i));
295 RR(POL_FREQ(i));
296 RR(DIVISORo(i));
297
298 RR(DATA_CYCLE1(i));
299 RR(DATA_CYCLE2(i));
300 RR(DATA_CYCLE3(i));
2a205f34 301
332e9d70 302 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 303 RR(CPR_COEF_R(i));
304 RR(CPR_COEF_G(i));
305 RR(CPR_COEF_B(i));
332e9d70 306 }
2a205f34 307 }
80c39712 308
c6104b8e
AT		 309 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
310 RR(OVL_BA0(i));
311 RR(OVL_BA1(i));
312 RR(OVL_POSITION(i));
313 RR(OVL_SIZE(i));
314 RR(OVL_ATTRIBUTES(i));
315 RR(OVL_FIFO_THRESHOLD(i));
316 RR(OVL_ROW_INC(i));
317 RR(OVL_PIXEL_INC(i));
318 if (dss_has_feature(FEAT_PRELOAD))
319 RR(OVL_PRELOAD(i));
320 if (i == OMAP_DSS_GFX) {
321 RR(OVL_WINDOW_SKIP(i));
322 RR(OVL_TABLE_BA(i));
323 continue;
324 }
325 RR(OVL_FIR(i));
326 RR(OVL_PICTURE_SIZE(i));
327 RR(OVL_ACCU0(i));
328 RR(OVL_ACCU1(i));
9b372c2d 329
c6104b8e
AT		 330 for (j = 0; j < 8; j++)
331 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 332
c6104b8e
AT		 333 for (j = 0; j < 8; j++)
334 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 335
c6104b8e
AT		 336 for (j = 0; j < 5; j++)
337 RR(OVL_CONV_COEF(i, j));
ab5ca071 338
c6104b8e
AT		 339 if (dss_has_feature(FEAT_FIR_COEF_V)) {
340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V(i, j));
342 }
9b372c2d 343
c6104b8e
AT		 344 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
345 RR(OVL_BA0_UV(i));
346 RR(OVL_BA1_UV(i));
347 RR(OVL_FIR2(i));
348 RR(OVL_ACCU2_0(i));
349 RR(OVL_ACCU2_1(i));
ab5ca071 350
c6104b8e
AT		 351 for (j = 0; j < 8; j++)
352 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 353
c6104b8e
AT		 354 for (j = 0; j < 8; j++)
355 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 356
c6104b8e
AT		 357 for (j = 0; j < 8; j++)
358 RR(OVL_FIR_COEF_V2(i, j));
359 }
360 if (dss_has_feature(FEAT_ATTR2))
361 RR(OVL_ATTRIBUTES2(i));
ab5ca071 362 }
80c39712 363
0cf35df3
MR		 364 if (dss_has_feature(FEAT_CORE_CLK_DIV))
365 RR(DIVISOR);
366
80c39712
TV		 367 /* enable last, because LCD & DIGIT enable are here */
368 RR(CONTROL);
2a205f34
SS		 369 if (dss_has_feature(FEAT_MGR_LCD2))
370 RR(CONTROL2);
75c7d59d
VS		 371 /* clear spurious SYNC_LOST_DIGIT interrupts */
372 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
373
374 /*
375 * enable last so IRQs won't trigger before
376 * the context is fully restored
377 */
378 RR(IRQENABLE);
49ea86f3
TV		 379
380 DSSDBG("context restored\n");
80c39712
TV		 381}
382
383#undef SR
384#undef RR
385
4fbafaf3
TV		 386int dispc_runtime_get(void)
387{
388 int r;
389
390 DSSDBG("dispc_runtime_get\n");
391
392 r = pm_runtime_get_sync(&dispc.pdev->dev);
393 WARN_ON(r < 0);
394 return r < 0 ? r : 0;
395}
396
397void dispc_runtime_put(void)
398{
399 int r;
400
401 DSSDBG("dispc_runtime_put\n");
402
0eaf9f52 403 r = pm_runtime_put_sync(&dispc.pdev->dev);
4fbafaf3 404 WARN_ON(r < 0);
80c39712
TV		 405}
406
dac57a05
AT		 407static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
408{
409 if (channel == OMAP_DSS_CHANNEL_LCD ||
410 channel == OMAP_DSS_CHANNEL_LCD2)
411 return true;
412 else
413 return false;
414}
4fbafaf3 415
c3dc6a7a
AT		 416static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
417{
418 struct omap_overlay_manager *mgr =
419 omap_dss_get_overlay_manager(channel);
420
421 return mgr ? mgr->device : NULL;
422}
423
3dcec4d6
TV		 424u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
425{
426 switch (channel) {
427 case OMAP_DSS_CHANNEL_LCD:
428 return DISPC_IRQ_VSYNC;
429 case OMAP_DSS_CHANNEL_LCD2:
430 return DISPC_IRQ_VSYNC2;
431 case OMAP_DSS_CHANNEL_DIGIT:
432 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
433 default:
434 BUG();
435 }
436}
437
7d1365c9
TV		 438u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
439{
440 switch (channel) {
441 case OMAP_DSS_CHANNEL_LCD:
442 return DISPC_IRQ_FRAMEDONE;
443 case OMAP_DSS_CHANNEL_LCD2:
444 return DISPC_IRQ_FRAMEDONE2;
445 case OMAP_DSS_CHANNEL_DIGIT:
446 return 0;
447 default:
448 BUG();
449 }
450}
451
26d9dd0d 452bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 453{
454 int bit;
455
dac57a05 456 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 457 bit = 5; /* GOLCD */
458 else
459 bit = 6; /* GODIGIT */
460
2a205f34
SS		 461 if (channel == OMAP_DSS_CHANNEL_LCD2)
462 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
463 else
464 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 465}
466
26d9dd0d 467void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 468{
469 int bit;
2a205f34 470 bool enable_bit, go_bit;
80c39712 471
dac57a05 472 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 473 bit = 0; /* LCDENABLE */
474 else
475 bit = 1; /* DIGITALENABLE */
476
477 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 478 if (channel == OMAP_DSS_CHANNEL_LCD2)
479 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
480 else
481 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
482
483 if (!enable_bit)
e6d80f95 484 return;
80c39712 485
dac57a05 486 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 487 bit = 5; /* GOLCD */
488 else
489 bit = 6; /* GODIGIT */
490
2a205f34
SS		 491 if (channel == OMAP_DSS_CHANNEL_LCD2)
492 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
493 else
494 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
495
496 if (go_bit) {
80c39712 497 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 498 return;
80c39712
TV		 499 }
500
2a205f34
SS		 501 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
502 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 503
2a205f34
SS		 504 if (channel == OMAP_DSS_CHANNEL_LCD2)
505 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
506 else
507 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 508}
509
f0e5caab 510static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 511{
9b372c2d 512 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 513}
514
f0e5caab 515static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 516{
9b372c2d 517 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 518}
519
f0e5caab 520static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 521{
9b372c2d 522 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 523}
524
f0e5caab 525static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 526{
527 BUG_ON(plane == OMAP_DSS_GFX);
528
529 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
530}
531
f0e5caab
TV		 532static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
533 u32 value)
ab5ca071
AJ		 534{
535 BUG_ON(plane == OMAP_DSS_GFX);
536
537 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
538}
539
f0e5caab 540static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 541{
542 BUG_ON(plane == OMAP_DSS_GFX);
543
544 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
545}
546
debd9074
CM		 547static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
548 int fir_vinc, int five_taps,
549 enum omap_color_component color_comp)
80c39712 550{
debd9074 551 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 552 int i;
553
debd9074
CM		 554 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
555 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 556
557 for (i = 0; i < 8; i++) {
558 u32 h, hv;
559
debd9074
CM		 560 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
561 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
562 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
563 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
564 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
565 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
566 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
567 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 568
0d66cbb5 569 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 570 dispc_ovl_write_firh_reg(plane, i, h);
571 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 572 } else {
f0e5caab
TV		 573 dispc_ovl_write_firh2_reg(plane, i, h);
574 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 575 }
576
80c39712
TV		 577 }
578
66be8f6c
GI		 579 if (five_taps) {
580 for (i = 0; i < 8; i++) {
581 u32 v;
debd9074
CM		 582 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
583 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 584 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 585 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 586 else
f0e5caab 587 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 588 }
80c39712
TV		 589 }
590}
591
592static void _dispc_setup_color_conv_coef(void)
593{
ac01c29e 594 int i;
80c39712
TV		 595 const struct color_conv_coef {
596 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
597 int full_range;
598 } ctbl_bt601_5 = {
599 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
600 };
601
602 const struct color_conv_coef *ct;
603
604#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
605
606 ct = &ctbl_bt601_5;
607
ac01c29e
AT		 608 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
609 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
610 CVAL(ct->rcr, ct->ry));
611 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
612 CVAL(ct->gy, ct->rcb));
613 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
614 CVAL(ct->gcb, ct->gcr));
615 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
616 CVAL(ct->bcr, ct->by));
617 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
618 CVAL(0, ct->bcb));
619
620 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
621 11, 11);
622 }
80c39712
TV		 623
624#undef CVAL
80c39712
TV		 625}
626
627
f0e5caab 628static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 629{
9b372c2d 630 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 631}
632
f0e5caab 633static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 634{
9b372c2d 635 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 636}
637
f0e5caab 638static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 639{
640 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
641}
642
f0e5caab 643static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 644{
645 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
646}
647
f0e5caab 648static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 649{
80c39712 650 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 651
652 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 653}
654
f0e5caab 655static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 656{
80c39712 657 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 658
659 if (plane == OMAP_DSS_GFX)
660 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
661 else
662 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 663}
664
f0e5caab 665static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 666{
667 u32 val;
80c39712
TV		 668
669 BUG_ON(plane == OMAP_DSS_GFX);
670
671 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 672
673 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 674}
675
54128701
AT		 676static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
677{
678 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
679
680 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
681 return;
682
683 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
684}
685
686static void dispc_ovl_enable_zorder_planes(void)
687{
688 int i;
689
690 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
691 return;
692
693 for (i = 0; i < dss_feat_get_num_ovls(); i++)
694 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
695}
696
f0e5caab 697static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 698{
f6dc8150 699 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 700
f6dc8150 701 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 702 return;
703
9b372c2d 704 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 705}
706
f0e5caab 707static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 708{
b8c095b4 709 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 710 int shift;
f6dc8150 711 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 712
f6dc8150 713 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 714 return;
a0acb557 715
fe3cc9d6
TV		 716 shift = shifts[plane];
717 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 718}
719
f0e5caab 720static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 721{
9b372c2d 722 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 723}
724
f0e5caab 725static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 726{
9b372c2d 727 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 728}
729
f0e5caab 730static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 731 enum omap_color_mode color_mode)
732{
733 u32 m = 0;
f20e4220
AJ		 734 if (plane != OMAP_DSS_GFX) {
735 switch (color_mode) {
736 case OMAP_DSS_COLOR_NV12:
737 m = 0x0; break;
08f3267e 738 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 739 m = 0x1; break;
740 case OMAP_DSS_COLOR_RGBA16:
741 m = 0x2; break;
08f3267e 742 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 743 m = 0x4; break;
744 case OMAP_DSS_COLOR_ARGB16:
745 m = 0x5; break;
746 case OMAP_DSS_COLOR_RGB16:
747 m = 0x6; break;
748 case OMAP_DSS_COLOR_ARGB16_1555:
749 m = 0x7; break;
750 case OMAP_DSS_COLOR_RGB24U:
751 m = 0x8; break;
752 case OMAP_DSS_COLOR_RGB24P:
753 m = 0x9; break;
754 case OMAP_DSS_COLOR_YUV2:
755 m = 0xa; break;
756 case OMAP_DSS_COLOR_UYVY:
757 m = 0xb; break;
758 case OMAP_DSS_COLOR_ARGB32:
759 m = 0xc; break;
760 case OMAP_DSS_COLOR_RGBA32:
761 m = 0xd; break;
762 case OMAP_DSS_COLOR_RGBX32:
763 m = 0xe; break;
764 case OMAP_DSS_COLOR_XRGB16_1555:
765 m = 0xf; break;
766 default:
767 BUG(); break;
768 }
769 } else {
770 switch (color_mode) {
771 case OMAP_DSS_COLOR_CLUT1:
772 m = 0x0; break;
773 case OMAP_DSS_COLOR_CLUT2:
774 m = 0x1; break;
775 case OMAP_DSS_COLOR_CLUT4:
776 m = 0x2; break;
777 case OMAP_DSS_COLOR_CLUT8:
778 m = 0x3; break;
779 case OMAP_DSS_COLOR_RGB12U:
780 m = 0x4; break;
781 case OMAP_DSS_COLOR_ARGB16:
782 m = 0x5; break;
783 case OMAP_DSS_COLOR_RGB16:
784 m = 0x6; break;
785 case OMAP_DSS_COLOR_ARGB16_1555:
786 m = 0x7; break;
787 case OMAP_DSS_COLOR_RGB24U:
788 m = 0x8; break;
789 case OMAP_DSS_COLOR_RGB24P:
790 m = 0x9; break;
08f3267e 791 case OMAP_DSS_COLOR_RGBX16:
f20e4220 792 m = 0xa; break;
08f3267e 793 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 794 m = 0xb; break;
795 case OMAP_DSS_COLOR_ARGB32:
796 m = 0xc; break;
797 case OMAP_DSS_COLOR_RGBA32:
798 m = 0xd; break;
799 case OMAP_DSS_COLOR_RGBX32:
800 m = 0xe; break;
801 case OMAP_DSS_COLOR_XRGB16_1555:
802 m = 0xf; break;
803 default:
804 BUG(); break;
805 }
80c39712
TV		 806 }
807
9b372c2d 808 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 809}
810
f427984e 811void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 812{
813 int shift;
814 u32 val;
2a205f34 815 int chan = 0, chan2 = 0;
80c39712
TV		 816
817 switch (plane) {
818 case OMAP_DSS_GFX:
819 shift = 8;
820 break;
821 case OMAP_DSS_VIDEO1:
822 case OMAP_DSS_VIDEO2:
b8c095b4 823 case OMAP_DSS_VIDEO3:
80c39712
TV		 824 shift = 16;
825 break;
826 default:
827 BUG();
828 return;
829 }
830
9b372c2d 831 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 832 if (dss_has_feature(FEAT_MGR_LCD2)) {
833 switch (channel) {
834 case OMAP_DSS_CHANNEL_LCD:
835 chan = 0;
836 chan2 = 0;
837 break;
838 case OMAP_DSS_CHANNEL_DIGIT:
839 chan = 1;
840 chan2 = 0;
841 break;
842 case OMAP_DSS_CHANNEL_LCD2:
843 chan = 0;
844 chan2 = 1;
845 break;
846 default:
847 BUG();
848 }
849
850 val = FLD_MOD(val, chan, shift, shift);
851 val = FLD_MOD(val, chan2, 31, 30);
852 } else {
853 val = FLD_MOD(val, channel, shift, shift);
854 }
9b372c2d 855 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 856}
857
2cc5d1af
TV		 858static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
859{
860 int shift;
861 u32 val;
862 enum omap_channel channel;
863
864 switch (plane) {
865 case OMAP_DSS_GFX:
866 shift = 8;
867 break;
868 case OMAP_DSS_VIDEO1:
869 case OMAP_DSS_VIDEO2:
870 case OMAP_DSS_VIDEO3:
871 shift = 16;
872 break;
873 default:
874 BUG();
875 }
876
877 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
878
879 if (dss_has_feature(FEAT_MGR_LCD2)) {
880 if (FLD_GET(val, 31, 30) == 0)
881 channel = FLD_GET(val, shift, shift);
882 else
883 channel = OMAP_DSS_CHANNEL_LCD2;
884 } else {
885 channel = FLD_GET(val, shift, shift);
886 }
887
888 return channel;
889}
890
f0e5caab 891static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 892 enum omap_burst_size burst_size)
893{
b8c095b4 894 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 895 int shift;
80c39712 896
fe3cc9d6 897 shift = shifts[plane];
5ed8cf5b 898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 899}
900
5ed8cf5b
TV		 901static void dispc_configure_burst_sizes(void)
902{
903 int i;
904 const int burst_size = BURST_SIZE_X8;
905
906 /* Configure burst size always to maximum size */
907 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 908 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 909}
910
83fa2f2e 911static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 912{
913 unsigned unit = dss_feat_get_burst_size_unit();
914 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
915 return unit * 8;
916}
917
d3862610
M		 918void dispc_enable_gamma_table(bool enable)
919{
920 /*
921 * This is partially implemented to support only disabling of
922 * the gamma table.
923 */
924 if (enable) {
925 DSSWARN("Gamma table enabling for TV not yet supported");
926 return;
927 }
928
929 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
930}
931
c64dca40 932static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 933{
934 u16 reg;
935
936 if (channel == OMAP_DSS_CHANNEL_LCD)
937 reg = DISPC_CONFIG;
938 else if (channel == OMAP_DSS_CHANNEL_LCD2)
939 reg = DISPC_CONFIG2;
940 else
941 return;
942
943 REG_FLD_MOD(reg, enable, 15, 15);
944}
945
c64dca40 946static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 947 struct omap_dss_cpr_coefs *coefs)
948{
949 u32 coef_r, coef_g, coef_b;
950
dac57a05 951 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 952 return;
953
954 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
955 FLD_VAL(coefs->rb, 9, 0);
956 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
957 FLD_VAL(coefs->gb, 9, 0);
958 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
959 FLD_VAL(coefs->bb, 9, 0);
960
961 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
962 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
963 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
964}
965
f0e5caab 966static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 967{
968 u32 val;
969
970 BUG_ON(plane == OMAP_DSS_GFX);
971
9b372c2d 972 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 973 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 974 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 975}
976
c3d92529 977static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 978{
b8c095b4 979 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 980 int shift;
80c39712 981
fe3cc9d6
TV		 982 shift = shifts[plane];
983 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 984}
985
e5c09e06
AT		 986static void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width,
987 u16 height)
80c39712
TV		 988{
989 u32 val;
990 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
991 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 992 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 993}
994
c51d921a 995static void dispc_mgr_set_digit_size(u16 width, u16 height)
80c39712
TV		 996{
997 u32 val;
998 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
999 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1000 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1001}
1002
1003static void dispc_read_plane_fifo_sizes(void)
1004{
80c39712
TV		 1005 u32 size;
1006 int plane;
a0acb557 1007 u8 start, end;
5ed8cf5b
TV		 1008 u32 unit;
1009
1010 unit = dss_feat_get_buffer_size_unit();
80c39712 1011
a0acb557 1012 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1013
e13a138b 1014 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1015 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1016 size *= unit;
80c39712
TV		 1017 dispc.fifo_size[plane] = size;
1018 }
80c39712
TV		 1019}
1020
83fa2f2e 1021static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1022{
1023 return dispc.fifo_size[plane];
1024}
1025
6f04e1bf 1026void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1027{
a0acb557 1028 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1029 u32 unit;
1030
1031 unit = dss_feat_get_buffer_size_unit();
1032
1033 WARN_ON(low % unit != 0);
1034 WARN_ON(high % unit != 0);
1035
1036 low /= unit;
1037 high /= unit;
a0acb557 1038
9b372c2d
AT		 1039 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1040 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1041
3cb5d966 1042 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1043 plane,
9b372c2d 1044 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1045 lo_start, lo_end) * unit,
9b372c2d 1046 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1047 hi_start, hi_end) * unit,
1048 low * unit, high * unit);
80c39712 1049
9b372c2d 1050 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1051 FLD_VAL(high, hi_start, hi_end) |
1052 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1053}
1054
1055void dispc_enable_fifomerge(bool enable)
1056{
e6b0f884
TV		 1057 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1058 WARN_ON(enable);
1059 return;
1060 }
1061
80c39712
TV		 1062 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1063 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1064}
1065
83fa2f2e
TV		 1066void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1067 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
1068{
1069 /*
1070 * All sizes are in bytes. Both the buffer and burst are made of
1071 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1072 */
1073
1074 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1075 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1076 int i;
83fa2f2e
TV		 1077
1078 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1079 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1080
e0e405b9
TV		 1081 if (use_fifomerge) {
1082 total_fifo_size = 0;
1083 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1084 total_fifo_size += dispc_ovl_get_fifo_size(i);
1085 } else {
1086 total_fifo_size = ovl_fifo_size;
1087 }
1088
1089 /*
1090 * We use the same low threshold for both fifomerge and non-fifomerge
1091 * cases, but for fifomerge we calculate the high threshold using the
1092 * combined fifo size
1093 */
1094
1095 if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1096 *fifo_low = ovl_fifo_size - burst_size * 2;
1097 *fifo_high = total_fifo_size - burst_size;
1098 } else {
1099 *fifo_low = ovl_fifo_size - burst_size;
1100 *fifo_high = total_fifo_size - buf_unit;
1101 }
83fa2f2e
TV		 1102}
1103
f0e5caab 1104static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1105 int hinc, int vinc,
1106 enum omap_color_component color_comp)
80c39712
TV		 1107{
1108 u32 val;
80c39712 1109
0d66cbb5
AJ		 1110 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1111 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1112
0d66cbb5
AJ		 1113 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1114 &hinc_start, &hinc_end);
1115 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1116 &vinc_start, &vinc_end);
1117 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1118 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1119
0d66cbb5
AJ		 1120 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1121 } else {
1122 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1123 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1124 }
80c39712
TV		 1125}
1126
f0e5caab 1127static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1128{
1129 u32 val;
87a7484b 1130 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1131
87a7484b
AT		 1132 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1133 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1134
1135 val = FLD_VAL(vaccu, vert_start, vert_end) |
1136 FLD_VAL(haccu, hor_start, hor_end);
1137
9b372c2d 1138 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1139}
1140
f0e5caab 1141static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1142{
1143 u32 val;
87a7484b 1144 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1145
87a7484b
AT		 1146 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1147 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1148
1149 val = FLD_VAL(vaccu, vert_start, vert_end) |
1150 FLD_VAL(haccu, hor_start, hor_end);
1151
9b372c2d 1152 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1153}
1154
f0e5caab
TV		 1155static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1156 int vaccu)
ab5ca071
AJ		 1157{
1158 u32 val;
1159
1160 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1161 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1162}
1163
f0e5caab
TV		 1164static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1165 int vaccu)
ab5ca071
AJ		 1166{
1167 u32 val;
1168
1169 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1170 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1171}
80c39712 1172
f0e5caab 1173static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1174 u16 orig_width, u16 orig_height,
1175 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1176 bool five_taps, u8 rotation,
1177 enum omap_color_component color_comp)
80c39712 1178{
0d66cbb5 1179 int fir_hinc, fir_vinc;
80c39712 1180
ed14a3ce
AJ		 1181 fir_hinc = 1024 * orig_width / out_width;
1182 fir_vinc = 1024 * orig_height / out_height;
80c39712 1183
debd9074
CM		 1184 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1185 color_comp);
f0e5caab 1186 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1187}
1188
f0e5caab 1189static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1190 u16 orig_width, u16 orig_height,
1191 u16 out_width, u16 out_height,
1192 bool ilace, bool five_taps,
1193 bool fieldmode, enum omap_color_mode color_mode,
1194 u8 rotation)
1195{
1196 int accu0 = 0;
1197 int accu1 = 0;
1198 u32 l;
80c39712 1199
f0e5caab 1200 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1201 out_width, out_height, five_taps,
1202 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1203 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1204
87a7484b
AT		 1205 /* RESIZEENABLE and VERTICALTAPS */
1206 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1207 l |= (orig_width != out_width) ? (1 << 5) : 0;
1208 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1209 l |= five_taps ? (1 << 21) : 0;
80c39712 1210
87a7484b
AT		 1211 /* VRESIZECONF and HRESIZECONF */
1212 if (dss_has_feature(FEAT_RESIZECONF)) {
1213 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1214 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1215 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1216 }
80c39712 1217
87a7484b
AT		 1218 /* LINEBUFFERSPLIT */
1219 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1220 l &= ~(0x1 << 22);
1221 l |= five_taps ? (1 << 22) : 0;
1222 }
80c39712 1223
9b372c2d 1224 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1225
1226 /*
1227 * field 0 = even field = bottom field
1228 * field 1 = odd field = top field
1229 */
1230 if (ilace && !fieldmode) {
1231 accu1 = 0;
0d66cbb5 1232 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1233 if (accu0 >= 1024/2) {
1234 accu1 = 1024/2;
1235 accu0 -= accu1;
1236 }
1237 }
1238
f0e5caab
TV		 1239 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1240 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1241}
1242
f0e5caab 1243static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1244 u16 orig_width, u16 orig_height,
1245 u16 out_width, u16 out_height,
1246 bool ilace, bool five_taps,
1247 bool fieldmode, enum omap_color_mode color_mode,
1248 u8 rotation)
1249{
1250 int scale_x = out_width != orig_width;
1251 int scale_y = out_height != orig_height;
1252
1253 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1254 return;
1255 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1256 color_mode != OMAP_DSS_COLOR_UYVY &&
1257 color_mode != OMAP_DSS_COLOR_NV12)) {
1258 /* reset chroma resampling for RGB formats */
1259 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1260 return;
1261 }
1262 switch (color_mode) {
1263 case OMAP_DSS_COLOR_NV12:
1264 /* UV is subsampled by 2 vertically*/
1265 orig_height >>= 1;
1266 /* UV is subsampled by 2 horz.*/
1267 orig_width >>= 1;
1268 break;
1269 case OMAP_DSS_COLOR_YUV2:
1270 case OMAP_DSS_COLOR_UYVY:
1271 /*For YUV422 with 90/270 rotation,
1272 *we don't upsample chroma
1273 */
1274 if (rotation == OMAP_DSS_ROT_0 ||
1275 rotation == OMAP_DSS_ROT_180)
1276 /* UV is subsampled by 2 hrz*/
1277 orig_width >>= 1;
1278 /* must use FIR for YUV422 if rotated */
1279 if (rotation != OMAP_DSS_ROT_0)
1280 scale_x = scale_y = true;
1281 break;
1282 default:
1283 BUG();
1284 }
1285
1286 if (out_width != orig_width)
1287 scale_x = true;
1288 if (out_height != orig_height)
1289 scale_y = true;
1290
f0e5caab 1291 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1292 out_width, out_height, five_taps,
1293 rotation, DISPC_COLOR_COMPONENT_UV);
1294
1295 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1296 (scale_x || scale_y) ? 1 : 0, 8, 8);
1297 /* set H scaling */
1298 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1299 /* set V scaling */
1300 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1301
f0e5caab
TV		 1302 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1303 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
0d66cbb5
AJ		 1304}
1305
f0e5caab 1306static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1307 u16 orig_width, u16 orig_height,
1308 u16 out_width, u16 out_height,
1309 bool ilace, bool five_taps,
1310 bool fieldmode, enum omap_color_mode color_mode,
1311 u8 rotation)
1312{
1313 BUG_ON(plane == OMAP_DSS_GFX);
1314
f0e5caab 1315 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1316 orig_width, orig_height,
1317 out_width, out_height,
1318 ilace, five_taps,
1319 fieldmode, color_mode,
1320 rotation);
1321
f0e5caab 1322 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1323 orig_width, orig_height,
1324 out_width, out_height,
1325 ilace, five_taps,
1326 fieldmode, color_mode,
1327 rotation);
1328}
1329
f0e5caab 1330static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1331 bool mirroring, enum omap_color_mode color_mode)
1332{
87a7484b
AT		 1333 bool row_repeat = false;
1334 int vidrot = 0;
1335
80c39712
TV		 1336 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1337 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1338
1339 if (mirroring) {
1340 switch (rotation) {
1341 case OMAP_DSS_ROT_0:
1342 vidrot = 2;
1343 break;
1344 case OMAP_DSS_ROT_90:
1345 vidrot = 1;
1346 break;
1347 case OMAP_DSS_ROT_180:
1348 vidrot = 0;
1349 break;
1350 case OMAP_DSS_ROT_270:
1351 vidrot = 3;
1352 break;
1353 }
1354 } else {
1355 switch (rotation) {
1356 case OMAP_DSS_ROT_0:
1357 vidrot = 0;
1358 break;
1359 case OMAP_DSS_ROT_90:
1360 vidrot = 1;
1361 break;
1362 case OMAP_DSS_ROT_180:
1363 vidrot = 2;
1364 break;
1365 case OMAP_DSS_ROT_270:
1366 vidrot = 3;
1367 break;
1368 }
1369 }
1370
80c39712 1371 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1372 row_repeat = true;
80c39712 1373 else
87a7484b 1374 row_repeat = false;
80c39712 1375 }
87a7484b 1376
9b372c2d 1377 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1378 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1379 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1380 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1381}
1382
1383static int color_mode_to_bpp(enum omap_color_mode color_mode)
1384{
1385 switch (color_mode) {
1386 case OMAP_DSS_COLOR_CLUT1:
1387 return 1;
1388 case OMAP_DSS_COLOR_CLUT2:
1389 return 2;
1390 case OMAP_DSS_COLOR_CLUT4:
1391 return 4;
1392 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1393 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1394 return 8;
1395 case OMAP_DSS_COLOR_RGB12U:
1396 case OMAP_DSS_COLOR_RGB16:
1397 case OMAP_DSS_COLOR_ARGB16:
1398 case OMAP_DSS_COLOR_YUV2:
1399 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1400 case OMAP_DSS_COLOR_RGBA16:
1401 case OMAP_DSS_COLOR_RGBX16:
1402 case OMAP_DSS_COLOR_ARGB16_1555:
1403 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1404 return 16;
1405 case OMAP_DSS_COLOR_RGB24P:
1406 return 24;
1407 case OMAP_DSS_COLOR_RGB24U:
1408 case OMAP_DSS_COLOR_ARGB32:
1409 case OMAP_DSS_COLOR_RGBA32:
1410 case OMAP_DSS_COLOR_RGBX32:
1411 return 32;
1412 default:
1413 BUG();
1414 }
1415}
1416
1417static s32 pixinc(int pixels, u8 ps)
1418{
1419 if (pixels == 1)
1420 return 1;
1421 else if (pixels > 1)
1422 return 1 + (pixels - 1) * ps;
1423 else if (pixels < 0)
1424 return 1 - (-pixels + 1) * ps;
1425 else
1426 BUG();
1427}
1428
1429static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1430 u16 screen_width,
1431 u16 width, u16 height,
1432 enum omap_color_mode color_mode, bool fieldmode,
1433 unsigned int field_offset,
1434 unsigned *offset0, unsigned *offset1,
1435 s32 *row_inc, s32 *pix_inc)
1436{
1437 u8 ps;
1438
1439 /* FIXME CLUT formats */
1440 switch (color_mode) {
1441 case OMAP_DSS_COLOR_CLUT1:
1442 case OMAP_DSS_COLOR_CLUT2:
1443 case OMAP_DSS_COLOR_CLUT4:
1444 case OMAP_DSS_COLOR_CLUT8:
1445 BUG();
1446 return;
1447 case OMAP_DSS_COLOR_YUV2:
1448 case OMAP_DSS_COLOR_UYVY:
1449 ps = 4;
1450 break;
1451 default:
1452 ps = color_mode_to_bpp(color_mode) / 8;
1453 break;
1454 }
1455
1456 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1457 width, height);
1458
1459 /*
1460 * field 0 = even field = bottom field
1461 * field 1 = odd field = top field
1462 */
1463 switch (rotation + mirror * 4) {
1464 case OMAP_DSS_ROT_0:
1465 case OMAP_DSS_ROT_180:
1466 /*
1467 * If the pixel format is YUV or UYVY divide the width
1468 * of the image by 2 for 0 and 180 degree rotation.
1469 */
1470 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1471 color_mode == OMAP_DSS_COLOR_UYVY)
1472 width = width >> 1;
1473 case OMAP_DSS_ROT_90:
1474 case OMAP_DSS_ROT_270:
1475 *offset1 = 0;
1476 if (field_offset)
1477 *offset0 = field_offset * screen_width * ps;
1478 else
1479 *offset0 = 0;
1480
1481 *row_inc = pixinc(1 + (screen_width - width) +
1482 (fieldmode ? screen_width : 0),
1483 ps);
1484 *pix_inc = pixinc(1, ps);
1485 break;
1486
1487 case OMAP_DSS_ROT_0 + 4:
1488 case OMAP_DSS_ROT_180 + 4:
1489 /* If the pixel format is YUV or UYVY divide the width
1490 * of the image by 2 for 0 degree and 180 degree
1491 */
1492 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1493 color_mode == OMAP_DSS_COLOR_UYVY)
1494 width = width >> 1;
1495 case OMAP_DSS_ROT_90 + 4:
1496 case OMAP_DSS_ROT_270 + 4:
1497 *offset1 = 0;
1498 if (field_offset)
1499 *offset0 = field_offset * screen_width * ps;
1500 else
1501 *offset0 = 0;
1502 *row_inc = pixinc(1 - (screen_width + width) -
1503 (fieldmode ? screen_width : 0),
1504 ps);
1505 *pix_inc = pixinc(1, ps);
1506 break;
1507
1508 default:
1509 BUG();
1510 }
1511}
1512
1513static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1514 u16 screen_width,
1515 u16 width, u16 height,
1516 enum omap_color_mode color_mode, bool fieldmode,
1517 unsigned int field_offset,
1518 unsigned *offset0, unsigned *offset1,
1519 s32 *row_inc, s32 *pix_inc)
1520{
1521 u8 ps;
1522 u16 fbw, fbh;
1523
1524 /* FIXME CLUT formats */
1525 switch (color_mode) {
1526 case OMAP_DSS_COLOR_CLUT1:
1527 case OMAP_DSS_COLOR_CLUT2:
1528 case OMAP_DSS_COLOR_CLUT4:
1529 case OMAP_DSS_COLOR_CLUT8:
1530 BUG();
1531 return;
1532 default:
1533 ps = color_mode_to_bpp(color_mode) / 8;
1534 break;
1535 }
1536
1537 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1538 width, height);
1539
1540 /* width & height are overlay sizes, convert to fb sizes */
1541
1542 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1543 fbw = width;
1544 fbh = height;
1545 } else {
1546 fbw = height;
1547 fbh = width;
1548 }
1549
1550 /*
1551 * field 0 = even field = bottom field
1552 * field 1 = odd field = top field
1553 */
1554 switch (rotation + mirror * 4) {
1555 case OMAP_DSS_ROT_0:
1556 *offset1 = 0;
1557 if (field_offset)
1558 *offset0 = *offset1 + field_offset * screen_width * ps;
1559 else
1560 *offset0 = *offset1;
1561 *row_inc = pixinc(1 + (screen_width - fbw) +
1562 (fieldmode ? screen_width : 0),
1563 ps);
1564 *pix_inc = pixinc(1, ps);
1565 break;
1566 case OMAP_DSS_ROT_90:
1567 *offset1 = screen_width * (fbh - 1) * ps;
1568 if (field_offset)
1569 *offset0 = *offset1 + field_offset * ps;
1570 else
1571 *offset0 = *offset1;
1572 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1573 (fieldmode ? 1 : 0), ps);
1574 *pix_inc = pixinc(-screen_width, ps);
1575 break;
1576 case OMAP_DSS_ROT_180:
1577 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1578 if (field_offset)
1579 *offset0 = *offset1 - field_offset * screen_width * ps;
1580 else
1581 *offset0 = *offset1;
1582 *row_inc = pixinc(-1 -
1583 (screen_width - fbw) -
1584 (fieldmode ? screen_width : 0),
1585 ps);
1586 *pix_inc = pixinc(-1, ps);
1587 break;
1588 case OMAP_DSS_ROT_270:
1589 *offset1 = (fbw - 1) * ps;
1590 if (field_offset)
1591 *offset0 = *offset1 - field_offset * ps;
1592 else
1593 *offset0 = *offset1;
1594 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1595 (fieldmode ? 1 : 0), ps);
1596 *pix_inc = pixinc(screen_width, ps);
1597 break;
1598
1599 /* mirroring */
1600 case OMAP_DSS_ROT_0 + 4:
1601 *offset1 = (fbw - 1) * ps;
1602 if (field_offset)
1603 *offset0 = *offset1 + field_offset * screen_width * ps;
1604 else
1605 *offset0 = *offset1;
1606 *row_inc = pixinc(screen_width * 2 - 1 +
1607 (fieldmode ? screen_width : 0),
1608 ps);
1609 *pix_inc = pixinc(-1, ps);
1610 break;
1611
1612 case OMAP_DSS_ROT_90 + 4:
1613 *offset1 = 0;
1614 if (field_offset)
1615 *offset0 = *offset1 + field_offset * ps;
1616 else
1617 *offset0 = *offset1;
1618 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1619 (fieldmode ? 1 : 0),
1620 ps);
1621 *pix_inc = pixinc(screen_width, ps);
1622 break;
1623
1624 case OMAP_DSS_ROT_180 + 4:
1625 *offset1 = screen_width * (fbh - 1) * ps;
1626 if (field_offset)
1627 *offset0 = *offset1 - field_offset * screen_width * ps;
1628 else
1629 *offset0 = *offset1;
1630 *row_inc = pixinc(1 - screen_width * 2 -
1631 (fieldmode ? screen_width : 0),
1632 ps);
1633 *pix_inc = pixinc(1, ps);
1634 break;
1635
1636 case OMAP_DSS_ROT_270 + 4:
1637 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1638 if (field_offset)
1639 *offset0 = *offset1 - field_offset * ps;
1640 else
1641 *offset0 = *offset1;
1642 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1643 (fieldmode ? 1 : 0),
1644 ps);
1645 *pix_inc = pixinc(-screen_width, ps);
1646 break;
1647
1648 default:
1649 BUG();
1650 }
1651}
1652
ff1b2cde
SS		 1653static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1654 u16 height, u16 out_width, u16 out_height,
1655 enum omap_color_mode color_mode)
80c39712
TV		 1656{
1657 u32 fclk = 0;
26d9dd0d 1658 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1659
7282f1b7
CM		 1660 if (height <= out_height && width <= out_width)
1661 return (unsigned long) pclk;
1662
80c39712 1663 if (height > out_height) {
ebdc5249
AT		 1664 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1665 unsigned int ppl = dssdev->panel.timings.x_res;
80c39712
TV		 1666
1667 tmp = pclk * height * out_width;
1668 do_div(tmp, 2 * out_height * ppl);
1669 fclk = tmp;
1670
2d9c5597
VS		 1671 if (height > 2 * out_height) {
1672 if (ppl == out_width)
1673 return 0;
1674
80c39712
TV		 1675 tmp = pclk * (height - 2 * out_height) * out_width;
1676 do_div(tmp, 2 * out_height * (ppl - out_width));
1677 fclk = max(fclk, (u32) tmp);
1678 }
1679 }
1680
1681 if (width > out_width) {
1682 tmp = pclk * width;
1683 do_div(tmp, out_width);
1684 fclk = max(fclk, (u32) tmp);
1685
1686 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1687 fclk <<= 1;
1688 }
1689
1690 return fclk;
1691}
1692
ff1b2cde
SS		 1693static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1694 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1695{
1696 unsigned int hf, vf;
79ee89cd 1697 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1698
1699 /*
1700 * FIXME how to determine the 'A' factor
1701 * for the no downscaling case ?
1702 */
1703
1704 if (width > 3 * out_width)
1705 hf = 4;
1706 else if (width > 2 * out_width)
1707 hf = 3;
1708 else if (width > out_width)
1709 hf = 2;
1710 else
1711 hf = 1;
1712
1713 if (height > out_height)
1714 vf = 2;
1715 else
1716 vf = 1;
1717
7282f1b7
CM		 1718 if (cpu_is_omap24xx()) {
1719 if (vf > 1 && hf > 1)
79ee89cd 1720 return pclk * 4;
7282f1b7 1721 else
79ee89cd 1722 return pclk * 2;
7282f1b7 1723 } else if (cpu_is_omap34xx()) {
79ee89cd 1724 return pclk * vf * hf;
7282f1b7 1725 } else {
79ee89cd
AT		 1726 if (hf > 1)
1727 return DIV_ROUND_UP(pclk, out_width) * width;
1728 else
1729 return pclk;
7282f1b7 1730 }
80c39712
TV		 1731}
1732
79ad75f2
AT		 1733static int dispc_ovl_calc_scaling(enum omap_plane plane,
1734 enum omap_channel channel, u16 width, u16 height,
1735 u16 out_width, u16 out_height,
1736 enum omap_color_mode color_mode, bool *five_taps)
1737{
1738 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1739 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1740 const int maxsinglelinewidth =
1741 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
79ad75f2
AT		 1742 unsigned long fclk = 0;
1743
f95cb5eb
TV		 1744 if (width == out_width && height == out_height)
1745 return 0;
1746
1747 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1748 return -EINVAL;
79ad75f2
AT		 1749
1750 if (out_width < width / maxdownscale ||
1751 out_width > width * 8)
1752 return -EINVAL;
1753
1754 if (out_height < height / maxdownscale ||
1755 out_height > height * 8)
1756 return -EINVAL;
1757
7282f1b7
CM		 1758 if (cpu_is_omap24xx()) {
1759 if (width > maxsinglelinewidth)
1760 DSSERR("Cannot scale max input width exceeded");
1761 *five_taps = false;
1762 fclk = calc_fclk(channel, width, height, out_width,
1763 out_height);
1764 } else if (cpu_is_omap34xx()) {
1765 if (width > (maxsinglelinewidth * 2)) {
1766 DSSERR("Cannot setup scaling");
1767 DSSERR("width exceeds maximum width possible");
1768 return -EINVAL;
1769 }
1770 fclk = calc_fclk_five_taps(channel, width, height, out_width,
1771 out_height, color_mode);
1772 if (width > maxsinglelinewidth) {
1773 if (height > out_height && height < out_height * 2)
1774 *five_taps = false;
1775 else {
1776 DSSERR("cannot setup scaling with five taps");
1777 return -EINVAL;
1778 }
1779 }
1780 if (!*five_taps)
1781 fclk = calc_fclk(channel, width, height, out_width,
1782 out_height);
1783 } else {
1784 if (width > maxsinglelinewidth) {
1785 DSSERR("Cannot scale width exceeds max line width");
1786 return -EINVAL;
1787 }
79ad75f2
AT		 1788 fclk = calc_fclk(channel, width, height, out_width,
1789 out_height);
79ad75f2
AT		 1790 }
1791
79ad75f2
AT		 1792 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1793 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1794
1795 if (!fclk || fclk > dispc_fclk_rate()) {
1796 DSSERR("failed to set up scaling, "
1797 "required fclk rate = %lu Hz, "
1798 "current fclk rate = %lu Hz\n",
1799 fclk, dispc_fclk_rate());
1800 return -EINVAL;
1801 }
1802
1803 return 0;
1804}
1805
a4273b7c 1806int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
2cc5d1af 1807 bool ilace, bool replication)
80c39712 1808{
79ad75f2 1809 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 1810 bool five_taps = true;
80c39712 1811 bool fieldmode = 0;
79ad75f2 1812 int r, cconv = 0;
80c39712
TV		 1813 unsigned offset0, offset1;
1814 s32 row_inc;
1815 s32 pix_inc;
a4273b7c 1816 u16 frame_height = oi->height;
80c39712 1817 unsigned int field_offset = 0;
cf073668 1818 u16 outw, outh;
2cc5d1af
TV		 1819 enum omap_channel channel;
1820
1821 channel = dispc_ovl_get_channel_out(plane);
80c39712 1822
a4273b7c 1823 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 1824 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
1825 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 1826 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1827 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 1828 oi->mirror, ilace, channel, replication);
e6d80f95 1829
a4273b7c 1830 if (oi->paddr == 0)
80c39712
TV		 1831 return -EINVAL;
1832
cf073668
TV		 1833 outw = oi->out_width == 0 ? oi->width : oi->out_width;
1834 outh = oi->out_height == 0 ? oi->height : oi->out_height;
1835
1836 if (ilace && oi->height == outh)
80c39712
TV		 1837 fieldmode = 1;
1838
1839 if (ilace) {
1840 if (fieldmode)
a4273b7c
AT		 1841 oi->height /= 2;
1842 oi->pos_y /= 2;
cf073668 1843 outh /= 2;
80c39712
TV		 1844
1845 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1846 "out_height %d\n",
cf073668 1847 oi->height, oi->pos_y, outh);
80c39712
TV		 1848 }
1849
a4273b7c 1850 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 1851 return -EINVAL;
1852
79ad75f2 1853 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
cf073668 1854 outw, outh, oi->color_mode,
79ad75f2
AT		 1855 &five_taps);
1856 if (r)
1857 return r;
80c39712 1858
79ad75f2
AT		 1859 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1860 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1861 oi->color_mode == OMAP_DSS_COLOR_NV12)
1862 cconv = 1;
80c39712
TV		 1863
1864 if (ilace && !fieldmode) {
1865 /*
1866 * when downscaling the bottom field may have to start several
1867 * source lines below the top field. Unfortunately ACCUI
1868 * registers will only hold the fractional part of the offset
1869 * so the integer part must be added to the base address of the
1870 * bottom field.
1871 */
cf073668 1872 if (!oi->height || oi->height == outh)
80c39712
TV		 1873 field_offset = 0;
1874 else
cf073668 1875 field_offset = oi->height / outh / 2;
80c39712
TV		 1876 }
1877
1878 /* Fields are independent but interleaved in memory. */
1879 if (fieldmode)
1880 field_offset = 1;
1881
a4273b7c
AT		 1882 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1883 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1884 oi->screen_width, oi->width, frame_height,
1885 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1886 &offset0, &offset1, &row_inc, &pix_inc);
1887 else
a4273b7c
AT		 1888 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1889 oi->screen_width, oi->width, frame_height,
1890 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1891 &offset0, &offset1, &row_inc, &pix_inc);
1892
1893 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1894 offset0, offset1, row_inc, pix_inc);
1895
a4273b7c 1896 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 1897
a4273b7c
AT		 1898 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1899 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 1900
a4273b7c
AT		 1901 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1902 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1903 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 1904 }
1905
1906
f0e5caab
TV		 1907 dispc_ovl_set_row_inc(plane, row_inc);
1908 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 1909
a4273b7c 1910 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
cf073668 1911 oi->height, outw, outh);
80c39712 1912
a4273b7c 1913 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 1914
a4273b7c 1915 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
80c39712 1916
79ad75f2 1917 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
a4273b7c 1918 dispc_ovl_set_scaling(plane, oi->width, oi->height,
cf073668 1919 outw, outh,
0d66cbb5 1920 ilace, five_taps, fieldmode,
a4273b7c 1921 oi->color_mode, oi->rotation);
cf073668 1922 dispc_ovl_set_vid_size(plane, outw, outh);
f0e5caab 1923 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 1924 }
1925
a4273b7c
AT		 1926 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1927 oi->color_mode);
80c39712 1928
54128701 1929 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 1930 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1931 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 1932
c3d92529 1933 dispc_ovl_enable_replication(plane, replication);
c3d92529 1934
80c39712
TV		 1935 return 0;
1936}
1937
f0e5caab 1938int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 1939{
e6d80f95
TV		 1940 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1941
9b372c2d 1942 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 1943
1944 return 0;
80c39712
TV		 1945}
1946
1947static void dispc_disable_isr(void *data, u32 mask)
1948{
1949 struct completion *compl = data;
1950 complete(compl);
1951}
1952
2a205f34 1953static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1954{
b6a44e77 1955 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 1956 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 1957 /* flush posted write */
1958 dispc_read_reg(DISPC_CONTROL2);
1959 } else {
2a205f34 1960 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 1961 dispc_read_reg(DISPC_CONTROL);
1962 }
80c39712
TV		 1963}
1964
26d9dd0d 1965static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1966{
1967 struct completion frame_done_completion;
1968 bool is_on;
1969 int r;
2a205f34 1970 u32 irq;
80c39712 1971
80c39712
TV		 1972 /* When we disable LCD output, we need to wait until frame is done.
1973 * Otherwise the DSS is still working, and turning off the clocks
1974 * prevents DSS from going to OFF mode */
2a205f34
SS		 1975 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1976 REG_GET(DISPC_CONTROL2, 0, 0) :
1977 REG_GET(DISPC_CONTROL, 0, 0);
1978
1979 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1980 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1981
1982 if (!enable && is_on) {
1983 init_completion(&frame_done_completion);
1984
1985 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1986 &frame_done_completion, irq);
80c39712
TV		 1987
1988 if (r)
1989 DSSERR("failed to register FRAMEDONE isr\n");
1990 }
1991
2a205f34 1992 _enable_lcd_out(channel, enable);
80c39712
TV		 1993
1994 if (!enable && is_on) {
1995 if (!wait_for_completion_timeout(&frame_done_completion,
1996 msecs_to_jiffies(100)))
1997 DSSERR("timeout waiting for FRAME DONE\n");
1998
1999 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2000 &frame_done_completion, irq);
80c39712
TV		 2001
2002 if (r)
2003 DSSERR("failed to unregister FRAMEDONE isr\n");
2004 }
80c39712
TV		 2005}
2006
2007static void _enable_digit_out(bool enable)
2008{
2009 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2010 /* flush posted write */
2011 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2012}
2013
26d9dd0d 2014static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2015{
2016 struct completion frame_done_completion;
e82b090b
TV		 2017 enum dss_hdmi_venc_clk_source_select src;
2018 int r, i;
2019 u32 irq_mask;
2020 int num_irqs;
80c39712 2021
e6d80f95 2022 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2023 return;
80c39712 2024
e82b090b
TV		 2025 src = dss_get_hdmi_venc_clk_source();
2026
80c39712
TV		 2027 if (enable) {
2028 unsigned long flags;
2029 /* When we enable digit output, we'll get an extra digit
2030 * sync lost interrupt, that we need to ignore */
2031 spin_lock_irqsave(&dispc.irq_lock, flags);
2032 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2033 _omap_dispc_set_irqs();
2034 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2035 }
2036
2037 /* When we disable digit output, we need to wait until fields are done.
2038 * Otherwise the DSS is still working, and turning off the clocks
2039 * prevents DSS from going to OFF mode. And when enabling, we need to
2040 * wait for the extra sync losts */
2041 init_completion(&frame_done_completion);
2042
e82b090b
TV		 2043 if (src == DSS_HDMI_M_PCLK && enable == false) {
2044 irq_mask = DISPC_IRQ_FRAMEDONETV;
2045 num_irqs = 1;
2046 } else {
2047 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2048 /* XXX I understand from TRM that we should only wait for the
2049 * current field to complete. But it seems we have to wait for
2050 * both fields */
2051 num_irqs = 2;
2052 }
2053
80c39712 2054 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2055 irq_mask);
80c39712 2056 if (r)
e82b090b 2057 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2058
2059 _enable_digit_out(enable);
2060
e82b090b
TV		 2061 for (i = 0; i < num_irqs; ++i) {
2062 if (!wait_for_completion_timeout(&frame_done_completion,
2063 msecs_to_jiffies(100)))
2064 DSSERR("timeout waiting for digit out to %s\n",
2065 enable ? "start" : "stop");
2066 }
80c39712 2067
e82b090b
TV		 2068 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2069 irq_mask);
80c39712 2070 if (r)
e82b090b 2071 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2072
2073 if (enable) {
2074 unsigned long flags;
2075 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2076 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2077 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2078 _omap_dispc_set_irqs();
2079 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2080 }
80c39712
TV		 2081}
2082
26d9dd0d 2083bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2084{
2085 if (channel == OMAP_DSS_CHANNEL_LCD)
2086 return !!REG_GET(DISPC_CONTROL, 0, 0);
2087 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2088 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2089 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2090 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2091 else
2092 BUG();
2093}
2094
26d9dd0d 2095void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2096{
dac57a05 2097 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2098 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2099 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2100 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2101 else
2102 BUG();
2103}
2104
80c39712
TV		 2105void dispc_lcd_enable_signal_polarity(bool act_high)
2106{
6ced40bf
AT		 2107 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2108 return;
2109
80c39712 2110 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2111}
2112
2113void dispc_lcd_enable_signal(bool enable)
2114{
6ced40bf
AT		 2115 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2116 return;
2117
80c39712 2118 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2119}
2120
2121void dispc_pck_free_enable(bool enable)
2122{
6ced40bf
AT		 2123 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2124 return;
2125
80c39712 2126 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2127}
2128
26d9dd0d 2129void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2130{
2a205f34
SS		 2131 if (channel == OMAP_DSS_CHANNEL_LCD2)
2132 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2133 else
2134 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2135}
2136
2137
26d9dd0d 2138void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2139 enum omap_lcd_display_type type)
80c39712
TV		 2140{
2141 int mode;
2142
2143 switch (type) {
2144 case OMAP_DSS_LCD_DISPLAY_STN:
2145 mode = 0;
2146 break;
2147
2148 case OMAP_DSS_LCD_DISPLAY_TFT:
2149 mode = 1;
2150 break;
2151
2152 default:
2153 BUG();
2154 return;
2155 }
2156
2a205f34
SS		 2157 if (channel == OMAP_DSS_CHANNEL_LCD2)
2158 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2159 else
2160 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2161}
2162
2163void dispc_set_loadmode(enum omap_dss_load_mode mode)
2164{
80c39712 2165 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2166}
2167
2168
c64dca40 2169static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2170{
8613b000 2171 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2172}
2173
c64dca40 2174static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2175 enum omap_dss_trans_key_type type,
2176 u32 trans_key)
2177{
80c39712
TV		 2178 if (ch == OMAP_DSS_CHANNEL_LCD)
2179 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2180 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2181 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2182 else /* OMAP_DSS_CHANNEL_LCD2 */
2183 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2184
8613b000 2185 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2186}
2187
c64dca40 2188static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2189{
80c39712
TV		 2190 if (ch == OMAP_DSS_CHANNEL_LCD)
2191 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2192 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2193 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2194 else /* OMAP_DSS_CHANNEL_LCD2 */
2195 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2196}
11354dd5 2197
c64dca40
TV		 2198static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2199 bool enable)
80c39712 2200{
11354dd5 2201 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2202 return;
2203
80c39712
TV		 2204 if (ch == OMAP_DSS_CHANNEL_LCD)
2205 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2206 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2207 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2208}
11354dd5 2209
c64dca40
TV		 2210void dispc_mgr_setup(enum omap_channel channel,
2211 struct omap_overlay_manager_info *info)
2212{
2213 dispc_mgr_set_default_color(channel, info->default_color);
2214 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2215 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2216 dispc_mgr_enable_alpha_fixed_zorder(channel,
2217 info->partial_alpha_enabled);
2218 if (dss_has_feature(FEAT_CPR)) {
2219 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2220 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2221 }
2222}
80c39712 2223
26d9dd0d 2224void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2225{
2226 int code;
2227
2228 switch (data_lines) {
2229 case 12:
2230 code = 0;
2231 break;
2232 case 16:
2233 code = 1;
2234 break;
2235 case 18:
2236 code = 2;
2237 break;
2238 case 24:
2239 code = 3;
2240 break;
2241 default:
2242 BUG();
2243 return;
2244 }
2245
2a205f34
SS		 2246 if (channel == OMAP_DSS_CHANNEL_LCD2)
2247 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2248 else
2249 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2250}
2251
569969d6 2252void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2253{
2254 u32 l;
569969d6 2255 int gpout0, gpout1;
80c39712
TV		 2256
2257 switch (mode) {
569969d6
AT		 2258 case DSS_IO_PAD_MODE_RESET:
2259 gpout0 = 0;
2260 gpout1 = 0;
80c39712 2261 break;
569969d6
AT		 2262 case DSS_IO_PAD_MODE_RFBI:
2263 gpout0 = 1;
80c39712
TV		 2264 gpout1 = 0;
2265 break;
569969d6
AT		 2266 case DSS_IO_PAD_MODE_BYPASS:
2267 gpout0 = 1;
80c39712
TV		 2268 gpout1 = 1;
2269 break;
80c39712
TV		 2270 default:
2271 BUG();
2272 return;
2273 }
2274
569969d6
AT		 2275 l = dispc_read_reg(DISPC_CONTROL);
2276 l = FLD_MOD(l, gpout0, 15, 15);
2277 l = FLD_MOD(l, gpout1, 16, 16);
2278 dispc_write_reg(DISPC_CONTROL, l);
2279}
2280
2281void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2282{
2283 if (channel == OMAP_DSS_CHANNEL_LCD2)
2284 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2285 else
2286 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2287}
2288
2289static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2290 int vsw, int vfp, int vbp)
2291{
2292 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2293 if (hsw < 1 || hsw > 64 ||
2294 hfp < 1 || hfp > 256 ||
2295 hbp < 1 || hbp > 256 ||
2296 vsw < 1 || vsw > 64 ||
2297 vfp < 0 || vfp > 255 ||
2298 vbp < 0 || vbp > 255)
2299 return false;
2300 } else {
2301 if (hsw < 1 || hsw > 256 ||
2302 hfp < 1 || hfp > 4096 ||
2303 hbp < 1 || hbp > 4096 ||
2304 vsw < 1 || vsw > 256 ||
2305 vfp < 0 || vfp > 4095 ||
2306 vbp < 0 || vbp > 4095)
2307 return false;
2308 }
2309
2310 return true;
2311}
2312
2313bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2314{
2315 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2316 timings->hbp, timings->vsw,
2317 timings->vfp, timings->vbp);
2318}
2319
26d9dd0d 2320static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2321 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2322{
2323 u32 timing_h, timing_v;
2324
2325 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2326 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2327 FLD_VAL(hbp-1, 27, 20);
2328
2329 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2330 FLD_VAL(vbp, 27, 20);
2331 } else {
2332 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2333 FLD_VAL(hbp-1, 31, 20);
2334
2335 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2336 FLD_VAL(vbp, 31, 20);
2337 }
2338
64ba4f74
SS		 2339 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2340 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2341}
2342
2343/* change name to mode? */
c51d921a 2344void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2345 struct omap_video_timings *timings)
80c39712
TV		 2346{
2347 unsigned xtot, ytot;
2348 unsigned long ht, vt;
2349
c51d921a
AT		 2350 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2351 timings->y_res);
80c39712 2352
c51d921a
AT		 2353 if (dispc_mgr_is_lcd(channel)) {
2354 if (!dispc_lcd_timings_ok(timings))
2355 BUG();
80c39712 2356
c51d921a
AT		 2357 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2358 timings->hbp, timings->vsw, timings->vfp,
2359 timings->vbp);
80c39712 2360
c51d921a 2361 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712 2362
c51d921a
AT		 2363 xtot = timings->x_res + timings->hfp + timings->hsw +
2364 timings->hbp;
2365 ytot = timings->y_res + timings->vfp + timings->vsw +
2366 timings->vbp;
80c39712 2367
c51d921a
AT		 2368 ht = (timings->pixel_clock * 1000) / xtot;
2369 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2370
2371 DSSDBG("pck %u\n", timings->pixel_clock);
2372 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
80c39712
TV		 2373 timings->hsw, timings->hfp, timings->hbp,
2374 timings->vsw, timings->vfp, timings->vbp);
2375
c51d921a
AT		 2376 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2377 } else {
2378 dispc_mgr_set_digit_size(timings->x_res, timings->y_res);
2379 }
80c39712
TV		 2380}
2381
26d9dd0d 2382static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2383 u16 pck_div)
80c39712
TV		 2384{
2385 BUG_ON(lck_div < 1);
9eaaf207 2386 BUG_ON(pck_div < 1);
80c39712 2387
ce7fa5eb 2388 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2389 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2390}
2391
26d9dd0d 2392static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2393 int *pck_div)
80c39712
TV		 2394{
2395 u32 l;
ce7fa5eb 2396 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2397 *lck_div = FLD_GET(l, 23, 16);
2398 *pck_div = FLD_GET(l, 7, 0);
2399}
2400
2401unsigned long dispc_fclk_rate(void)
2402{
a72b64b9 2403 struct platform_device *dsidev;
80c39712
TV		 2404 unsigned long r = 0;
2405
66534e8e 2406 switch (dss_get_dispc_clk_source()) {
89a35e51 2407 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2408 r = clk_get_rate(dispc.dss_clk);
66534e8e 2409 break;
89a35e51 2410 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2411 dsidev = dsi_get_dsidev_from_id(0);
2412 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2413 break;
5a8b572d
AT		 2414 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2415 dsidev = dsi_get_dsidev_from_id(1);
2416 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2417 break;
66534e8e
TA		 2418 default:
2419 BUG();
2420 }
2421
80c39712
TV		 2422 return r;
2423}
2424
26d9dd0d 2425unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2426{
a72b64b9 2427 struct platform_device *dsidev;
80c39712
TV		 2428 int lcd;
2429 unsigned long r;
2430 u32 l;
2431
ce7fa5eb 2432 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2433
2434 lcd = FLD_GET(l, 23, 16);
2435
ea75159e 2436 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2437 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2438 r = clk_get_rate(dispc.dss_clk);
ea75159e 2439 break;
89a35e51 2440 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2441 dsidev = dsi_get_dsidev_from_id(0);
2442 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2443 break;
5a8b572d
AT		 2444 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2445 dsidev = dsi_get_dsidev_from_id(1);
2446 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2447 break;
ea75159e
TA		 2448 default:
2449 BUG();
2450 }
80c39712
TV		 2451
2452 return r / lcd;
2453}
2454
26d9dd0d 2455unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2456{
80c39712 2457 unsigned long r;
80c39712 2458
c3dc6a7a
AT		 2459 if (dispc_mgr_is_lcd(channel)) {
2460 int pcd;
2461 u32 l;
80c39712 2462
c3dc6a7a 2463 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2464
c3dc6a7a 2465 pcd = FLD_GET(l, 7, 0);
80c39712 2466
c3dc6a7a
AT		 2467 r = dispc_mgr_lclk_rate(channel);
2468
2469 return r / pcd;
2470 } else {
2471 struct omap_dss_device *dssdev =
2472 dispc_mgr_get_device(channel);
2473
2474 switch (dssdev->type) {
2475 case OMAP_DISPLAY_TYPE_VENC:
2476 return venc_get_pixel_clock();
2477 case OMAP_DISPLAY_TYPE_HDMI:
2478 return hdmi_get_pixel_clock();
2479 default:
2480 BUG();
2481 }
2482 }
80c39712
TV		 2483}
2484
2485void dispc_dump_clocks(struct seq_file *s)
2486{
2487 int lcd, pcd;
0cf35df3 2488 u32 l;
89a35e51
AT		 2489 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2490 enum omap_dss_clk_source lcd_clk_src;
80c39712 2491
4fbafaf3
TV		 2492 if (dispc_runtime_get())
2493 return;
80c39712 2494
80c39712
TV		 2495 seq_printf(s, "- DISPC -\n");
2496
067a57e4
AT		 2497 seq_printf(s, "dispc fclk source = %s (%s)\n",
2498 dss_get_generic_clk_source_name(dispc_clk_src),
2499 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2500
2501 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2502
0cf35df3
MR		 2503 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2504 seq_printf(s, "- DISPC-CORE-CLK -\n");
2505 l = dispc_read_reg(DISPC_DIVISOR);
2506 lcd = FLD_GET(l, 23, 16);
2507
2508 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2509 (dispc_fclk_rate()/lcd), lcd);
2510 }
2a205f34
SS		 2511 seq_printf(s, "- LCD1 -\n");
2512
ea75159e
TA		 2513 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2514
2515 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2516 dss_get_generic_clk_source_name(lcd_clk_src),
2517 dss_feat_get_clk_source_name(lcd_clk_src));
2518
26d9dd0d 2519 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2520
ff1b2cde 2521 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2522 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2523 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2524 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2525 if (dss_has_feature(FEAT_MGR_LCD2)) {
2526 seq_printf(s, "- LCD2 -\n");
2527
ea75159e
TA		 2528 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2529
2530 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2531 dss_get_generic_clk_source_name(lcd_clk_src),
2532 dss_feat_get_clk_source_name(lcd_clk_src));
2533
26d9dd0d 2534 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2535
2a205f34 2536 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2537 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2538 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2539 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2540 }
4fbafaf3
TV		 2541
2542 dispc_runtime_put();
80c39712
TV		 2543}
2544
dfc0fd8d
TV		 2545#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2546void dispc_dump_irqs(struct seq_file *s)
2547{
2548 unsigned long flags;
2549 struct dispc_irq_stats stats;
2550
2551 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2552
2553 stats = dispc.irq_stats;
2554 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2555 dispc.irq_stats.last_reset = jiffies;
2556
2557 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2558
2559 seq_printf(s, "period %u ms\n",
2560 jiffies_to_msecs(jiffies - stats.last_reset));
2561
2562 seq_printf(s, "irqs %d\n", stats.irq_count);
2563#define PIS(x) \
2564 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2565
2566 PIS(FRAMEDONE);
2567 PIS(VSYNC);
2568 PIS(EVSYNC_EVEN);
2569 PIS(EVSYNC_ODD);
2570 PIS(ACBIAS_COUNT_STAT);
2571 PIS(PROG_LINE_NUM);
2572 PIS(GFX_FIFO_UNDERFLOW);
2573 PIS(GFX_END_WIN);
2574 PIS(PAL_GAMMA_MASK);
2575 PIS(OCP_ERR);
2576 PIS(VID1_FIFO_UNDERFLOW);
2577 PIS(VID1_END_WIN);
2578 PIS(VID2_FIFO_UNDERFLOW);
2579 PIS(VID2_END_WIN);
b8c095b4
AT		 2580 if (dss_feat_get_num_ovls() > 3) {
2581 PIS(VID3_FIFO_UNDERFLOW);
2582 PIS(VID3_END_WIN);
2583 }
dfc0fd8d
TV		 2584 PIS(SYNC_LOST);
2585 PIS(SYNC_LOST_DIGIT);
2586 PIS(WAKEUP);
2a205f34
SS		 2587 if (dss_has_feature(FEAT_MGR_LCD2)) {
2588 PIS(FRAMEDONE2);
2589 PIS(VSYNC2);
2590 PIS(ACBIAS_COUNT_STAT2);
2591 PIS(SYNC_LOST2);
2592 }
dfc0fd8d
TV		 2593#undef PIS
2594}
dfc0fd8d
TV		 2595#endif
2596
80c39712
TV		 2597void dispc_dump_regs(struct seq_file *s)
2598{
4dd2da15
AT		 2599 int i, j;
2600 const char *mgr_names[] = {
2601 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2602 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2603 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2604 };
2605 const char *ovl_names[] = {
2606 [OMAP_DSS_GFX] = "GFX",
2607 [OMAP_DSS_VIDEO1] = "VID1",
2608 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2609 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2610 };
2611 const char **p_names;
2612
9b372c2d 2613#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2614
4fbafaf3
TV		 2615 if (dispc_runtime_get())
2616 return;
80c39712 2617
5010be80 2618 /* DISPC common registers */
80c39712
TV		 2619 DUMPREG(DISPC_REVISION);
2620 DUMPREG(DISPC_SYSCONFIG);
2621 DUMPREG(DISPC_SYSSTATUS);
2622 DUMPREG(DISPC_IRQSTATUS);
2623 DUMPREG(DISPC_IRQENABLE);
2624 DUMPREG(DISPC_CONTROL);
2625 DUMPREG(DISPC_CONFIG);
2626 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2627 DUMPREG(DISPC_LINE_STATUS);
2628 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2629 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2630 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2631 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2632 if (dss_has_feature(FEAT_MGR_LCD2)) {
2633 DUMPREG(DISPC_CONTROL2);
2634 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2635 }
2636
2637#undef DUMPREG
2638
2639#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2640#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2641 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2642 dispc_read_reg(DISPC_REG(i, r)))
2643
4dd2da15 2644 p_names = mgr_names;
5010be80 2645
4dd2da15
AT		 2646 /* DISPC channel specific registers */
2647 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2648 DUMPREG(i, DISPC_DEFAULT_COLOR);
2649 DUMPREG(i, DISPC_TRANS_COLOR);
2650 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2651
4dd2da15
AT		 2652 if (i == OMAP_DSS_CHANNEL_DIGIT)
2653 continue;
5010be80 2654
4dd2da15
AT		 2655 DUMPREG(i, DISPC_DEFAULT_COLOR);
2656 DUMPREG(i, DISPC_TRANS_COLOR);
2657 DUMPREG(i, DISPC_TIMING_H);
2658 DUMPREG(i, DISPC_TIMING_V);
2659 DUMPREG(i, DISPC_POL_FREQ);
2660 DUMPREG(i, DISPC_DIVISORo);
2661 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2662
4dd2da15
AT		 2663 DUMPREG(i, DISPC_DATA_CYCLE1);
2664 DUMPREG(i, DISPC_DATA_CYCLE2);
2665 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2666
332e9d70 2667 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2668 DUMPREG(i, DISPC_CPR_COEF_R);
2669 DUMPREG(i, DISPC_CPR_COEF_G);
2670 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2671 }
2a205f34 2672 }
80c39712 2673
4dd2da15
AT		 2674 p_names = ovl_names;
2675
2676 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2677 DUMPREG(i, DISPC_OVL_BA0);
2678 DUMPREG(i, DISPC_OVL_BA1);
2679 DUMPREG(i, DISPC_OVL_POSITION);
2680 DUMPREG(i, DISPC_OVL_SIZE);
2681 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2682 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2683 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2684 DUMPREG(i, DISPC_OVL_ROW_INC);
2685 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2686 if (dss_has_feature(FEAT_PRELOAD))
2687 DUMPREG(i, DISPC_OVL_PRELOAD);
2688
2689 if (i == OMAP_DSS_GFX) {
2690 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2691 DUMPREG(i, DISPC_OVL_TABLE_BA);
2692 continue;
2693 }
2694
2695 DUMPREG(i, DISPC_OVL_FIR);
2696 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2697 DUMPREG(i, DISPC_OVL_ACCU0);
2698 DUMPREG(i, DISPC_OVL_ACCU1);
2699 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2700 DUMPREG(i, DISPC_OVL_BA0_UV);
2701 DUMPREG(i, DISPC_OVL_BA1_UV);
2702 DUMPREG(i, DISPC_OVL_FIR2);
2703 DUMPREG(i, DISPC_OVL_ACCU2_0);
2704 DUMPREG(i, DISPC_OVL_ACCU2_1);
2705 }
2706 if (dss_has_feature(FEAT_ATTR2))
2707 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2708 if (dss_has_feature(FEAT_PRELOAD))
2709 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2710 }
5010be80
AT		 2711
2712#undef DISPC_REG
2713#undef DUMPREG
2714
2715#define DISPC_REG(plane, name, i) name(plane, i)
2716#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2717 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2718 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2719 dispc_read_reg(DISPC_REG(plane, name, i)))
2720
4dd2da15 2721 /* Video pipeline coefficient registers */
332e9d70 2722
4dd2da15
AT		 2723 /* start from OMAP_DSS_VIDEO1 */
2724 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2725 for (j = 0; j < 8; j++)
2726 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2727
4dd2da15
AT		 2728 for (j = 0; j < 8; j++)
2729 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2730
4dd2da15
AT		 2731 for (j = 0; j < 5; j++)
2732 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2733
4dd2da15
AT		 2734 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2735 for (j = 0; j < 8; j++)
2736 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2737 }
2738
2739 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2740 for (j = 0; j < 8; j++)
2741 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2742
2743 for (j = 0; j < 8; j++)
2744 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2745
2746 for (j = 0; j < 8; j++)
2747 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2748 }
332e9d70 2749 }
80c39712 2750
4fbafaf3 2751 dispc_runtime_put();
5010be80
AT		 2752
2753#undef DISPC_REG
80c39712
TV		 2754#undef DUMPREG
2755}
2756
26d9dd0d
TV		 2757static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2758 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2759 u8 acb)
80c39712
TV		 2760{
2761 u32 l = 0;
2762
2763 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2764 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2765
2766 l |= FLD_VAL(onoff, 17, 17);
2767 l |= FLD_VAL(rf, 16, 16);
2768 l |= FLD_VAL(ieo, 15, 15);
2769 l |= FLD_VAL(ipc, 14, 14);
2770 l |= FLD_VAL(ihs, 13, 13);
2771 l |= FLD_VAL(ivs, 12, 12);
2772 l |= FLD_VAL(acbi, 11, 8);
2773 l |= FLD_VAL(acb, 7, 0);
2774
ff1b2cde 2775 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2776}
2777
26d9dd0d 2778void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 2779 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2780{
26d9dd0d 2781 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2782 (config & OMAP_DSS_LCD_RF) != 0,
2783 (config & OMAP_DSS_LCD_IEO) != 0,
2784 (config & OMAP_DSS_LCD_IPC) != 0,
2785 (config & OMAP_DSS_LCD_IHS) != 0,
2786 (config & OMAP_DSS_LCD_IVS) != 0,
2787 acbi, acb);
2788}
2789
2790/* with fck as input clock rate, find dispc dividers that produce req_pck */
2791void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2792 struct dispc_clock_info *cinfo)
2793{
9eaaf207 2794 u16 pcd_min, pcd_max;
80c39712
TV		 2795 unsigned long best_pck;
2796 u16 best_ld, cur_ld;
2797 u16 best_pd, cur_pd;
2798
9eaaf207
TV		 2799 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2800 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2801
2802 if (!is_tft)
2803 pcd_min = 3;
2804
80c39712
TV		 2805 best_pck = 0;
2806 best_ld = 0;
2807 best_pd = 0;
2808
2809 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2810 unsigned long lck = fck / cur_ld;
2811
9eaaf207 2812 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 2813 unsigned long pck = lck / cur_pd;
2814 long old_delta = abs(best_pck - req_pck);
2815 long new_delta = abs(pck - req_pck);
2816
2817 if (best_pck == 0 || new_delta < old_delta) {
2818 best_pck = pck;
2819 best_ld = cur_ld;
2820 best_pd = cur_pd;
2821
2822 if (pck == req_pck)
2823 goto found;
2824 }
2825
2826 if (pck < req_pck)
2827 break;
2828 }
2829
2830 if (lck / pcd_min < req_pck)
2831 break;
2832 }
2833
2834found:
2835 cinfo->lck_div = best_ld;
2836 cinfo->pck_div = best_pd;
2837 cinfo->lck = fck / cinfo->lck_div;
2838 cinfo->pck = cinfo->lck / cinfo->pck_div;
2839}
2840
2841/* calculate clock rates using dividers in cinfo */
2842int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2843 struct dispc_clock_info *cinfo)
2844{
2845 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2846 return -EINVAL;
9eaaf207 2847 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 2848 return -EINVAL;
2849
2850 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2851 cinfo->pck = cinfo->lck / cinfo->pck_div;
2852
2853 return 0;
2854}
2855
26d9dd0d 2856int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 2857 struct dispc_clock_info *cinfo)
80c39712
TV		 2858{
2859 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2860 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2861
26d9dd0d 2862 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2863
2864 return 0;
2865}
2866
26d9dd0d 2867int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 2868 struct dispc_clock_info *cinfo)
80c39712
TV		 2869{
2870 unsigned long fck;
2871
2872 fck = dispc_fclk_rate();
2873
ce7fa5eb
MR		 2874 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2875 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2876
2877 cinfo->lck = fck / cinfo->lck_div;
2878 cinfo->pck = cinfo->lck / cinfo->pck_div;
2879
2880 return 0;
2881}
2882
2883/* dispc.irq_lock has to be locked by the caller */
2884static void _omap_dispc_set_irqs(void)
2885{
2886 u32 mask;
2887 u32 old_mask;
2888 int i;
2889 struct omap_dispc_isr_data *isr_data;
2890
2891 mask = dispc.irq_error_mask;
2892
2893 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2894 isr_data = &dispc.registered_isr[i];
2895
2896 if (isr_data->isr == NULL)
2897 continue;
2898
2899 mask |= isr_data->mask;
2900 }
2901
80c39712
TV		 2902 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2903 /* clear the irqstatus for newly enabled irqs */
2904 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2905
2906 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 2907}
2908
2909int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2910{
2911 int i;
2912 int ret;
2913 unsigned long flags;
2914 struct omap_dispc_isr_data *isr_data;
2915
2916 if (isr == NULL)
2917 return -EINVAL;
2918
2919 spin_lock_irqsave(&dispc.irq_lock, flags);
2920
2921 /* check for duplicate entry */
2922 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2923 isr_data = &dispc.registered_isr[i];
2924 if (isr_data->isr == isr && isr_data->arg == arg &&
2925 isr_data->mask == mask) {
2926 ret = -EINVAL;
2927 goto err;
2928 }
2929 }
2930
2931 isr_data = NULL;
2932 ret = -EBUSY;
2933
2934 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2935 isr_data = &dispc.registered_isr[i];
2936
2937 if (isr_data->isr != NULL)
2938 continue;
2939
2940 isr_data->isr = isr;
2941 isr_data->arg = arg;
2942 isr_data->mask = mask;
2943 ret = 0;
2944
2945 break;
2946 }
2947
b9cb0984
TV		 2948 if (ret)
2949 goto err;
2950
80c39712
TV		 2951 _omap_dispc_set_irqs();
2952
2953 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2954
2955 return 0;
2956err:
2957 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2958
2959 return ret;
2960}
2961EXPORT_SYMBOL(omap_dispc_register_isr);
2962
2963int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2964{
2965 int i;
2966 unsigned long flags;
2967 int ret = -EINVAL;
2968 struct omap_dispc_isr_data *isr_data;
2969
2970 spin_lock_irqsave(&dispc.irq_lock, flags);
2971
2972 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2973 isr_data = &dispc.registered_isr[i];
2974 if (isr_data->isr != isr || isr_data->arg != arg ||
2975 isr_data->mask != mask)
2976 continue;
2977
2978 /* found the correct isr */
2979
2980 isr_data->isr = NULL;
2981 isr_data->arg = NULL;
2982 isr_data->mask = 0;
2983
2984 ret = 0;
2985 break;
2986 }
2987
2988 if (ret == 0)
2989 _omap_dispc_set_irqs();
2990
2991 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2992
2993 return ret;
2994}
2995EXPORT_SYMBOL(omap_dispc_unregister_isr);
2996
2997#ifdef DEBUG
2998static void print_irq_status(u32 status)
2999{
3000 if ((status & dispc.irq_error_mask) == 0)
3001 return;
3002
3003 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3004
3005#define PIS(x) \
3006 if (status & DISPC_IRQ_##x) \
3007 printk(#x " ");
3008 PIS(GFX_FIFO_UNDERFLOW);
3009 PIS(OCP_ERR);
3010 PIS(VID1_FIFO_UNDERFLOW);
3011 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3012 if (dss_feat_get_num_ovls() > 3)
3013 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3014 PIS(SYNC_LOST);
3015 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3016 if (dss_has_feature(FEAT_MGR_LCD2))
3017 PIS(SYNC_LOST2);
80c39712
TV		 3018#undef PIS
3019
3020 printk("\n");
3021}
3022#endif
3023
3024/* Called from dss.c. Note that we don't touch clocks here,
3025 * but we presume they are on because we got an IRQ. However,
3026 * an irq handler may turn the clocks off, so we may not have
3027 * clock later in the function. */
affe360d 3028static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3029{
3030 int i;
affe360d 3031 u32 irqstatus, irqenable;
80c39712
TV		 3032 u32 handledirqs = 0;
3033 u32 unhandled_errors;
3034 struct omap_dispc_isr_data *isr_data;
3035 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3036
3037 spin_lock(&dispc.irq_lock);
3038
3039 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3040 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3041
3042 /* IRQ is not for us */
3043 if (!(irqstatus & irqenable)) {
3044 spin_unlock(&dispc.irq_lock);
3045 return IRQ_NONE;
3046 }
80c39712 3047
dfc0fd8d
TV		 3048#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3049 spin_lock(&dispc.irq_stats_lock);
3050 dispc.irq_stats.irq_count++;
3051 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3052 spin_unlock(&dispc.irq_stats_lock);
3053#endif
3054
80c39712
TV		 3055#ifdef DEBUG
3056 if (dss_debug)
3057 print_irq_status(irqstatus);
3058#endif
3059 /* Ack the interrupt. Do it here before clocks are possibly turned
3060 * off */
3061 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3062 /* flush posted write */
3063 dispc_read_reg(DISPC_IRQSTATUS);
3064
3065 /* make a copy and unlock, so that isrs can unregister
3066 * themselves */
3067 memcpy(registered_isr, dispc.registered_isr,
3068 sizeof(registered_isr));
3069
3070 spin_unlock(&dispc.irq_lock);
3071
3072 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3073 isr_data = &registered_isr[i];
3074
3075 if (!isr_data->isr)
3076 continue;
3077
3078 if (isr_data->mask & irqstatus) {
3079 isr_data->isr(isr_data->arg, irqstatus);
3080 handledirqs |= isr_data->mask;
3081 }
3082 }
3083
3084 spin_lock(&dispc.irq_lock);
3085
3086 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3087
3088 if (unhandled_errors) {
3089 dispc.error_irqs |= unhandled_errors;
3090
3091 dispc.irq_error_mask &= ~unhandled_errors;
3092 _omap_dispc_set_irqs();
3093
3094 schedule_work(&dispc.error_work);
3095 }
3096
3097 spin_unlock(&dispc.irq_lock);
affe360d 3098
3099 return IRQ_HANDLED;
80c39712
TV		 3100}
3101
3102static void dispc_error_worker(struct work_struct *work)
3103{
3104 int i;
3105 u32 errors;
3106 unsigned long flags;
fe3cc9d6
TV		 3107 static const unsigned fifo_underflow_bits[] = {
3108 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3109 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3110 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3111 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3112 };
3113
3114 static const unsigned sync_lost_bits[] = {
3115 DISPC_IRQ_SYNC_LOST,
3116 DISPC_IRQ_SYNC_LOST_DIGIT,
3117 DISPC_IRQ_SYNC_LOST2,
3118 };
80c39712
TV		 3119
3120 spin_lock_irqsave(&dispc.irq_lock, flags);
3121 errors = dispc.error_irqs;
3122 dispc.error_irqs = 0;
3123 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3124
13eae1f9
DZ		 3125 dispc_runtime_get();
3126
fe3cc9d6
TV		 3127 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3128 struct omap_overlay *ovl;
3129 unsigned bit;
80c39712 3130
fe3cc9d6
TV		 3131 ovl = omap_dss_get_overlay(i);
3132 bit = fifo_underflow_bits[i];
80c39712 3133
fe3cc9d6
TV		 3134 if (bit & errors) {
3135 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3136 ovl->name);
f0e5caab 3137 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3138 dispc_mgr_go(ovl->manager->id);
80c39712 3139 mdelay(50);
80c39712
TV		 3140 }
3141 }
3142
fe3cc9d6
TV		 3143 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3144 struct omap_overlay_manager *mgr;
3145 unsigned bit;
80c39712 3146
fe3cc9d6
TV		 3147 mgr = omap_dss_get_overlay_manager(i);
3148 bit = sync_lost_bits[i];
80c39712 3149
fe3cc9d6
TV		 3150 if (bit & errors) {
3151 struct omap_dss_device *dssdev = mgr->device;
3152 bool enable;
80c39712 3153
fe3cc9d6
TV		 3154 DSSERR("SYNC_LOST on channel %s, restarting the output "
3155 "with video overlays disabled\n",
3156 mgr->name);
2a205f34 3157
fe3cc9d6
TV		 3158 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3159 dssdev->driver->disable(dssdev);
2a205f34 3160
2a205f34
SS		 3161 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3162 struct omap_overlay *ovl;
3163 ovl = omap_dss_get_overlay(i);
3164
fe3cc9d6
TV		 3165 if (ovl->id != OMAP_DSS_GFX &&
3166 ovl->manager == mgr)
f0e5caab 3167 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3168 }
3169
26d9dd0d 3170 dispc_mgr_go(mgr->id);
2a205f34 3171 mdelay(50);
fe3cc9d6 3172
2a205f34
SS		 3173 if (enable)
3174 dssdev->driver->enable(dssdev);
3175 }
3176 }
3177
80c39712
TV		 3178 if (errors & DISPC_IRQ_OCP_ERR) {
3179 DSSERR("OCP_ERR\n");
3180 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3181 struct omap_overlay_manager *mgr;
3182 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3183 if (mgr->device && mgr->device->driver)
3184 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3185 }
3186 }
3187
3188 spin_lock_irqsave(&dispc.irq_lock, flags);
3189 dispc.irq_error_mask |= errors;
3190 _omap_dispc_set_irqs();
3191 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3192
3193 dispc_runtime_put();
80c39712
TV		 3194}
3195
3196int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3197{
3198 void dispc_irq_wait_handler(void *data, u32 mask)
3199 {
3200 complete((struct completion *)data);
3201 }
3202
3203 int r;
3204 DECLARE_COMPLETION_ONSTACK(completion);
3205
3206 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3207 irqmask);
3208
3209 if (r)
3210 return r;
3211
3212 timeout = wait_for_completion_timeout(&completion, timeout);
3213
3214 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3215
3216 if (timeout == 0)
3217 return -ETIMEDOUT;
3218
3219 if (timeout == -ERESTARTSYS)
3220 return -ERESTARTSYS;
3221
3222 return 0;
3223}
3224
3225int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3226 unsigned long timeout)
3227{
3228 void dispc_irq_wait_handler(void *data, u32 mask)
3229 {
3230 complete((struct completion *)data);
3231 }
3232
3233 int r;
3234 DECLARE_COMPLETION_ONSTACK(completion);
3235
3236 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3237 irqmask);
3238
3239 if (r)
3240 return r;
3241
3242 timeout = wait_for_completion_interruptible_timeout(&completion,
3243 timeout);
3244
3245 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3246
3247 if (timeout == 0)
3248 return -ETIMEDOUT;
3249
3250 if (timeout == -ERESTARTSYS)
3251 return -ERESTARTSYS;
3252
3253 return 0;
3254}
3255
3256#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3257void dispc_fake_vsync_irq(void)
3258{
3259 u32 irqstatus = DISPC_IRQ_VSYNC;
3260 int i;
3261
ab83b14c 3262 WARN_ON(!in_interrupt());
80c39712
TV		 3263
3264 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3265 struct omap_dispc_isr_data *isr_data;
3266 isr_data = &dispc.registered_isr[i];
3267
3268 if (!isr_data->isr)
3269 continue;
3270
3271 if (isr_data->mask & irqstatus)
3272 isr_data->isr(isr_data->arg, irqstatus);
3273 }
80c39712
TV		 3274}
3275#endif
3276
3277static void _omap_dispc_initialize_irq(void)
3278{
3279 unsigned long flags;
3280
3281 spin_lock_irqsave(&dispc.irq_lock, flags);
3282
3283 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3284
3285 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3286 if (dss_has_feature(FEAT_MGR_LCD2))
3287 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3288 if (dss_feat_get_num_ovls() > 3)
3289 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3290
3291 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3292 * so clear it */
3293 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3294
3295 _omap_dispc_set_irqs();
3296
3297 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3298}
3299
3300void dispc_enable_sidle(void)
3301{
3302 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3303}
3304
3305void dispc_disable_sidle(void)
3306{
3307 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3308}
3309
3310static void _omap_dispc_initial_config(void)
3311{
3312 u32 l;
3313
0cf35df3
MR		 3314 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3315 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3316 l = dispc_read_reg(DISPC_DIVISOR);
3317 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3318 l = FLD_MOD(l, 1, 0, 0);
3319 l = FLD_MOD(l, 1, 23, 16);
3320 dispc_write_reg(DISPC_DIVISOR, l);
3321 }
3322
80c39712 3323 /* FUNCGATED */
6ced40bf
AT		 3324 if (dss_has_feature(FEAT_FUNCGATED))
3325 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3326
80c39712
TV		 3327 _dispc_setup_color_conv_coef();
3328
3329 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3330
3331 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3332
3333 dispc_configure_burst_sizes();
54128701
AT		 3334
3335 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3336}
3337
060b6d9c
SG		 3338/* DISPC HW IP initialisation */
3339static int omap_dispchw_probe(struct platform_device *pdev)
3340{
3341 u32 rev;
affe360d 3342 int r = 0;
ea9da36a 3343 struct resource *dispc_mem;
4fbafaf3 3344 struct clk *clk;
ea9da36a 3345
060b6d9c
SG		 3346 dispc.pdev = pdev;
3347
3348 spin_lock_init(&dispc.irq_lock);
3349
3350#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3351 spin_lock_init(&dispc.irq_stats_lock);
3352 dispc.irq_stats.last_reset = jiffies;
3353#endif
3354
3355 INIT_WORK(&dispc.error_work, dispc_error_worker);
3356
ea9da36a
SG		 3357 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3358 if (!dispc_mem) {
3359 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3360 return -EINVAL;
ea9da36a 3361 }
cd3b3449 3362
6e2a14d2
JL		 3363 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3364 resource_size(dispc_mem));
060b6d9c
SG		 3365 if (!dispc.base) {
3366 DSSERR("can't ioremap DISPC\n");
cd3b3449 3367 return -ENOMEM;
affe360d 3368 }
cd3b3449 3369
affe360d 3370 dispc.irq = platform_get_irq(dispc.pdev, 0);
3371 if (dispc.irq < 0) {
3372 DSSERR("platform_get_irq failed\n");
cd3b3449 3373 return -ENODEV;
affe360d 3374 }
3375
6e2a14d2
JL		 3376 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3377 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3378 if (r < 0) {
3379 DSSERR("request_irq failed\n");
cd3b3449
TV		 3380 return r;
3381 }
3382
3383 clk = clk_get(&pdev->dev, "fck");
3384 if (IS_ERR(clk)) {
3385 DSSERR("can't get fck\n");
3386 r = PTR_ERR(clk);
3387 return r;
060b6d9c
SG		 3388 }
3389
cd3b3449
TV		 3390 dispc.dss_clk = clk;
3391
4fbafaf3
TV		 3392 pm_runtime_enable(&pdev->dev);
3393
3394 r = dispc_runtime_get();
3395 if (r)
3396 goto err_runtime_get;
060b6d9c
SG		 3397
3398 _omap_dispc_initial_config();
3399
3400 _omap_dispc_initialize_irq();
3401
060b6d9c 3402 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3403 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3404 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3405
4fbafaf3 3406 dispc_runtime_put();
060b6d9c
SG		 3407
3408 return 0;
4fbafaf3
TV		 3409
3410err_runtime_get:
3411 pm_runtime_disable(&pdev->dev);
4fbafaf3 3412 clk_put(dispc.dss_clk);
affe360d 3413 return r;
060b6d9c
SG		 3414}
3415
3416static int omap_dispchw_remove(struct platform_device *pdev)
3417{
4fbafaf3
TV		 3418 pm_runtime_disable(&pdev->dev);
3419
3420 clk_put(dispc.dss_clk);
3421
060b6d9c
SG		 3422 return 0;
3423}
3424
4fbafaf3
TV		 3425static int dispc_runtime_suspend(struct device *dev)
3426{
3427 dispc_save_context();
4fbafaf3
TV		 3428 dss_runtime_put();
3429
3430 return 0;
3431}
3432
3433static int dispc_runtime_resume(struct device *dev)
3434{
3435 int r;
3436
3437 r = dss_runtime_get();
3438 if (r < 0)
3439 return r;
3440
49ea86f3 3441 dispc_restore_context();
4fbafaf3
TV		 3442
3443 return 0;
3444}
3445
3446static const struct dev_pm_ops dispc_pm_ops = {
3447 .runtime_suspend = dispc_runtime_suspend,
3448 .runtime_resume = dispc_runtime_resume,
3449};
3450
060b6d9c
SG		 3451static struct platform_driver omap_dispchw_driver = {
3452 .probe = omap_dispchw_probe,
3453 .remove = omap_dispchw_remove,
3454 .driver = {
3455 .name = "omapdss_dispc",
3456 .owner = THIS_MODULE,
4fbafaf3 3457 .pm = &dispc_pm_ops,
060b6d9c
SG		 3458 },
3459};
3460
3461int dispc_init_platform_driver(void)
3462{
3463 return platform_driver_register(&omap_dispchw_driver);
3464}
3465
3466void dispc_uninit_platform_driver(void)
3467{
3468 return platform_driver_unregister(&omap_dispchw_driver);
3469}
Linux kernel - Deliverables
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