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OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
80c39712
TV		 36
37#include <plat/sram.h>
38#include <plat/clock.h>
39
40#include <plat/display.h>
41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
80c39712
TV		 44
45/* DISPC */
8613b000 46#define DISPC_SZ_REGS SZ_4K
80c39712
TV		 47
48struct dispc_reg { u16 idx; };
49
50#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
51
8613b000
SS		 52/*
53 * DISPC common registers and
54 * DISPC channel registers , ch = 0 for LCD, ch = 1 for
55 * DIGIT, and ch = 2 for LCD2
56 */
80c39712
TV		 57#define DISPC_REVISION DISPC_REG(0x0000)
58#define DISPC_SYSCONFIG DISPC_REG(0x0010)
59#define DISPC_SYSSTATUS DISPC_REG(0x0014)
60#define DISPC_IRQSTATUS DISPC_REG(0x0018)
61#define DISPC_IRQENABLE DISPC_REG(0x001C)
62#define DISPC_CONTROL DISPC_REG(0x0040)
8613b000 63#define DISPC_CONTROL2 DISPC_REG(0x0238)
80c39712 64#define DISPC_CONFIG DISPC_REG(0x0044)
8613b000 65#define DISPC_CONFIG2 DISPC_REG(0x0620)
80c39712 66#define DISPC_CAPABLE DISPC_REG(0x0048)
8613b000
SS		 67#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
68 (ch == 1 ? 0x0050 : 0x03AC))
69#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
70 (ch == 1 ? 0x0058 : 0x03B0))
80c39712
TV		 71#define DISPC_LINE_STATUS DISPC_REG(0x005C)
72#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
8613b000
SS		 73#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
74#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
75#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
ce7fa5eb 76#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
80c39712
TV		 77#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
78#define DISPC_SIZE_DIG DISPC_REG(0x0078)
8613b000 79#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
80c39712
TV		 80
81/* DISPC GFX plane */
82#define DISPC_GFX_BA0 DISPC_REG(0x0080)
83#define DISPC_GFX_BA1 DISPC_REG(0x0084)
84#define DISPC_GFX_POSITION DISPC_REG(0x0088)
85#define DISPC_GFX_SIZE DISPC_REG(0x008C)
86#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
87#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
88#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
89#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
90#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
91#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
92#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
93
8613b000
SS		 94#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
95#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
96#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
97#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
98#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
99#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
80c39712
TV		 100
101#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
102
103/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
104#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
105
106#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
107#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
108#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
109#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
110#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
111#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
112#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
113#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
114#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
115#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
116#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
117#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
118#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
119
120/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
121#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
122/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
123#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
124/* coef index i = {0, 1, 2, 3, 4} */
125#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
126/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
127#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
128
129#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
130
ce7fa5eb 131#define DISPC_DIVISOR DISPC_REG(0x0804)
80c39712
TV		 132
133#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
134 DISPC_IRQ_OCP_ERR | \
135 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
136 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
137 DISPC_IRQ_SYNC_LOST | \
138 DISPC_IRQ_SYNC_LOST_DIGIT)
139
140#define DISPC_MAX_NR_ISRS 8
141
142struct omap_dispc_isr_data {
143 omap_dispc_isr_t isr;
144 void *arg;
145 u32 mask;
146};
147
66be8f6c
GI		 148struct dispc_h_coef {
149 s8 hc4;
150 s8 hc3;
151 u8 hc2;
152 s8 hc1;
153 s8 hc0;
154};
155
156struct dispc_v_coef {
157 s8 vc22;
158 s8 vc2;
159 u8 vc1;
160 s8 vc0;
161 s8 vc00;
162};
163
80c39712
TV		 164#define REG_GET(idx, start, end) \
165 FLD_GET(dispc_read_reg(idx), start, end)
166
167#define REG_FLD_MOD(idx, val, start, end) \
168 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
169
170static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
171 DISPC_VID_ATTRIBUTES(0),
172 DISPC_VID_ATTRIBUTES(1) };
173
dfc0fd8d
TV		 174struct dispc_irq_stats {
175 unsigned long last_reset;
176 unsigned irq_count;
177 unsigned irqs[32];
178};
179
80c39712 180static struct {
060b6d9c 181 struct platform_device *pdev;
80c39712 182 void __iomem *base;
affe360d 183 int irq;
80c39712
TV		 184
185 u32 fifo_size[3];
186
187 spinlock_t irq_lock;
188 u32 irq_error_mask;
189 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
190 u32 error_irqs;
191 struct work_struct error_work;
192
193 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 194
195#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
196 spinlock_t irq_stats_lock;
197 struct dispc_irq_stats irq_stats;
198#endif
80c39712
TV		 199} dispc;
200
201static void _omap_dispc_set_irqs(void);
202
203static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
204{
205 __raw_writel(val, dispc.base + idx.idx);
206}
207
208static inline u32 dispc_read_reg(const struct dispc_reg idx)
209{
210 return __raw_readl(dispc.base + idx.idx);
211}
212
213#define SR(reg) \
214 dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
215#define RR(reg) \
216 dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
217
218void dispc_save_context(void)
219{
220 if (cpu_is_omap24xx())
221 return;
222
223 SR(SYSCONFIG);
224 SR(IRQENABLE);
225 SR(CONTROL);
226 SR(CONFIG);
8613b000
SS		 227 SR(DEFAULT_COLOR(0));
228 SR(DEFAULT_COLOR(1));
229 SR(TRANS_COLOR(0));
230 SR(TRANS_COLOR(1));
80c39712 231 SR(LINE_NUMBER);
8613b000
SS		 232 SR(TIMING_H(0));
233 SR(TIMING_V(0));
234 SR(POL_FREQ(0));
ce7fa5eb 235 SR(DIVISORo(0));
80c39712
TV		 236 SR(GLOBAL_ALPHA);
237 SR(SIZE_DIG);
8613b000 238 SR(SIZE_LCD(0));
2a205f34
SS		 239 if (dss_has_feature(FEAT_MGR_LCD2)) {
240 SR(CONTROL2);
241 SR(DEFAULT_COLOR(2));
242 SR(TRANS_COLOR(2));
243 SR(SIZE_LCD(2));
244 SR(TIMING_H(2));
245 SR(TIMING_V(2));
246 SR(POL_FREQ(2));
ce7fa5eb 247 SR(DIVISORo(2));
2a205f34
SS		 248 SR(CONFIG2);
249 }
80c39712
TV		 250
251 SR(GFX_BA0);
252 SR(GFX_BA1);
253 SR(GFX_POSITION);
254 SR(GFX_SIZE);
255 SR(GFX_ATTRIBUTES);
256 SR(GFX_FIFO_THRESHOLD);
257 SR(GFX_ROW_INC);
258 SR(GFX_PIXEL_INC);
259 SR(GFX_WINDOW_SKIP);
260 SR(GFX_TABLE_BA);
261
8613b000
SS		 262 SR(DATA_CYCLE1(0));
263 SR(DATA_CYCLE2(0));
264 SR(DATA_CYCLE3(0));
80c39712 265
8613b000
SS		 266 SR(CPR_COEF_R(0));
267 SR(CPR_COEF_G(0));
268 SR(CPR_COEF_B(0));
2a205f34
SS		 269 if (dss_has_feature(FEAT_MGR_LCD2)) {
270 SR(CPR_COEF_B(2));
271 SR(CPR_COEF_G(2));
272 SR(CPR_COEF_R(2));
273
274 SR(DATA_CYCLE1(2));
275 SR(DATA_CYCLE2(2));
276 SR(DATA_CYCLE3(2));
277 }
80c39712
TV		 278
279 SR(GFX_PRELOAD);
280
281 /* VID1 */
282 SR(VID_BA0(0));
283 SR(VID_BA1(0));
284 SR(VID_POSITION(0));
285 SR(VID_SIZE(0));
286 SR(VID_ATTRIBUTES(0));
287 SR(VID_FIFO_THRESHOLD(0));
288 SR(VID_ROW_INC(0));
289 SR(VID_PIXEL_INC(0));
290 SR(VID_FIR(0));
291 SR(VID_PICTURE_SIZE(0));
292 SR(VID_ACCU0(0));
293 SR(VID_ACCU1(0));
294
295 SR(VID_FIR_COEF_H(0, 0));
296 SR(VID_FIR_COEF_H(0, 1));
297 SR(VID_FIR_COEF_H(0, 2));
298 SR(VID_FIR_COEF_H(0, 3));
299 SR(VID_FIR_COEF_H(0, 4));
300 SR(VID_FIR_COEF_H(0, 5));
301 SR(VID_FIR_COEF_H(0, 6));
302 SR(VID_FIR_COEF_H(0, 7));
303
304 SR(VID_FIR_COEF_HV(0, 0));
305 SR(VID_FIR_COEF_HV(0, 1));
306 SR(VID_FIR_COEF_HV(0, 2));
307 SR(VID_FIR_COEF_HV(0, 3));
308 SR(VID_FIR_COEF_HV(0, 4));
309 SR(VID_FIR_COEF_HV(0, 5));
310 SR(VID_FIR_COEF_HV(0, 6));
311 SR(VID_FIR_COEF_HV(0, 7));
312
313 SR(VID_CONV_COEF(0, 0));
314 SR(VID_CONV_COEF(0, 1));
315 SR(VID_CONV_COEF(0, 2));
316 SR(VID_CONV_COEF(0, 3));
317 SR(VID_CONV_COEF(0, 4));
318
319 SR(VID_FIR_COEF_V(0, 0));
320 SR(VID_FIR_COEF_V(0, 1));
321 SR(VID_FIR_COEF_V(0, 2));
322 SR(VID_FIR_COEF_V(0, 3));
323 SR(VID_FIR_COEF_V(0, 4));
324 SR(VID_FIR_COEF_V(0, 5));
325 SR(VID_FIR_COEF_V(0, 6));
326 SR(VID_FIR_COEF_V(0, 7));
327
328 SR(VID_PRELOAD(0));
329
330 /* VID2 */
331 SR(VID_BA0(1));
332 SR(VID_BA1(1));
333 SR(VID_POSITION(1));
334 SR(VID_SIZE(1));
335 SR(VID_ATTRIBUTES(1));
336 SR(VID_FIFO_THRESHOLD(1));
337 SR(VID_ROW_INC(1));
338 SR(VID_PIXEL_INC(1));
339 SR(VID_FIR(1));
340 SR(VID_PICTURE_SIZE(1));
341 SR(VID_ACCU0(1));
342 SR(VID_ACCU1(1));
343
344 SR(VID_FIR_COEF_H(1, 0));
345 SR(VID_FIR_COEF_H(1, 1));
346 SR(VID_FIR_COEF_H(1, 2));
347 SR(VID_FIR_COEF_H(1, 3));
348 SR(VID_FIR_COEF_H(1, 4));
349 SR(VID_FIR_COEF_H(1, 5));
350 SR(VID_FIR_COEF_H(1, 6));
351 SR(VID_FIR_COEF_H(1, 7));
352
353 SR(VID_FIR_COEF_HV(1, 0));
354 SR(VID_FIR_COEF_HV(1, 1));
355 SR(VID_FIR_COEF_HV(1, 2));
356 SR(VID_FIR_COEF_HV(1, 3));
357 SR(VID_FIR_COEF_HV(1, 4));
358 SR(VID_FIR_COEF_HV(1, 5));
359 SR(VID_FIR_COEF_HV(1, 6));
360 SR(VID_FIR_COEF_HV(1, 7));
361
362 SR(VID_CONV_COEF(1, 0));
363 SR(VID_CONV_COEF(1, 1));
364 SR(VID_CONV_COEF(1, 2));
365 SR(VID_CONV_COEF(1, 3));
366 SR(VID_CONV_COEF(1, 4));
367
368 SR(VID_FIR_COEF_V(1, 0));
369 SR(VID_FIR_COEF_V(1, 1));
370 SR(VID_FIR_COEF_V(1, 2));
371 SR(VID_FIR_COEF_V(1, 3));
372 SR(VID_FIR_COEF_V(1, 4));
373 SR(VID_FIR_COEF_V(1, 5));
374 SR(VID_FIR_COEF_V(1, 6));
375 SR(VID_FIR_COEF_V(1, 7));
376
377 SR(VID_PRELOAD(1));
378}
379
380void dispc_restore_context(void)
381{
382 RR(SYSCONFIG);
75c7d59d 383 /*RR(IRQENABLE);*/
80c39712
TV		 384 /*RR(CONTROL);*/
385 RR(CONFIG);
8613b000
SS		 386 RR(DEFAULT_COLOR(0));
387 RR(DEFAULT_COLOR(1));
388 RR(TRANS_COLOR(0));
389 RR(TRANS_COLOR(1));
80c39712 390 RR(LINE_NUMBER);
8613b000
SS		 391 RR(TIMING_H(0));
392 RR(TIMING_V(0));
393 RR(POL_FREQ(0));
ce7fa5eb 394 RR(DIVISORo(0));
80c39712
TV		 395 RR(GLOBAL_ALPHA);
396 RR(SIZE_DIG);
8613b000 397 RR(SIZE_LCD(0));
2a205f34
SS		 398 if (dss_has_feature(FEAT_MGR_LCD2)) {
399 RR(DEFAULT_COLOR(2));
400 RR(TRANS_COLOR(2));
401 RR(SIZE_LCD(2));
402 RR(TIMING_H(2));
403 RR(TIMING_V(2));
404 RR(POL_FREQ(2));
ce7fa5eb 405 RR(DIVISORo(2));
2a205f34
SS		 406 RR(CONFIG2);
407 }
80c39712
TV		 408
409 RR(GFX_BA0);
410 RR(GFX_BA1);
411 RR(GFX_POSITION);
412 RR(GFX_SIZE);
413 RR(GFX_ATTRIBUTES);
414 RR(GFX_FIFO_THRESHOLD);
415 RR(GFX_ROW_INC);
416 RR(GFX_PIXEL_INC);
417 RR(GFX_WINDOW_SKIP);
418 RR(GFX_TABLE_BA);
419
8613b000
SS		 420 RR(DATA_CYCLE1(0));
421 RR(DATA_CYCLE2(0));
422 RR(DATA_CYCLE3(0));
80c39712 423
8613b000
SS		 424 RR(CPR_COEF_R(0));
425 RR(CPR_COEF_G(0));
426 RR(CPR_COEF_B(0));
2a205f34
SS		 427 if (dss_has_feature(FEAT_MGR_LCD2)) {
428 RR(DATA_CYCLE1(2));
429 RR(DATA_CYCLE2(2));
430 RR(DATA_CYCLE3(2));
431
432 RR(CPR_COEF_B(2));
433 RR(CPR_COEF_G(2));
434 RR(CPR_COEF_R(2));
435 }
80c39712
TV		 436
437 RR(GFX_PRELOAD);
438
439 /* VID1 */
440 RR(VID_BA0(0));
441 RR(VID_BA1(0));
442 RR(VID_POSITION(0));
443 RR(VID_SIZE(0));
444 RR(VID_ATTRIBUTES(0));
445 RR(VID_FIFO_THRESHOLD(0));
446 RR(VID_ROW_INC(0));
447 RR(VID_PIXEL_INC(0));
448 RR(VID_FIR(0));
449 RR(VID_PICTURE_SIZE(0));
450 RR(VID_ACCU0(0));
451 RR(VID_ACCU1(0));
452
453 RR(VID_FIR_COEF_H(0, 0));
454 RR(VID_FIR_COEF_H(0, 1));
455 RR(VID_FIR_COEF_H(0, 2));
456 RR(VID_FIR_COEF_H(0, 3));
457 RR(VID_FIR_COEF_H(0, 4));
458 RR(VID_FIR_COEF_H(0, 5));
459 RR(VID_FIR_COEF_H(0, 6));
460 RR(VID_FIR_COEF_H(0, 7));
461
462 RR(VID_FIR_COEF_HV(0, 0));
463 RR(VID_FIR_COEF_HV(0, 1));
464 RR(VID_FIR_COEF_HV(0, 2));
465 RR(VID_FIR_COEF_HV(0, 3));
466 RR(VID_FIR_COEF_HV(0, 4));
467 RR(VID_FIR_COEF_HV(0, 5));
468 RR(VID_FIR_COEF_HV(0, 6));
469 RR(VID_FIR_COEF_HV(0, 7));
470
471 RR(VID_CONV_COEF(0, 0));
472 RR(VID_CONV_COEF(0, 1));
473 RR(VID_CONV_COEF(0, 2));
474 RR(VID_CONV_COEF(0, 3));
475 RR(VID_CONV_COEF(0, 4));
476
477 RR(VID_FIR_COEF_V(0, 0));
478 RR(VID_FIR_COEF_V(0, 1));
479 RR(VID_FIR_COEF_V(0, 2));
480 RR(VID_FIR_COEF_V(0, 3));
481 RR(VID_FIR_COEF_V(0, 4));
482 RR(VID_FIR_COEF_V(0, 5));
483 RR(VID_FIR_COEF_V(0, 6));
484 RR(VID_FIR_COEF_V(0, 7));
485
486 RR(VID_PRELOAD(0));
487
488 /* VID2 */
489 RR(VID_BA0(1));
490 RR(VID_BA1(1));
491 RR(VID_POSITION(1));
492 RR(VID_SIZE(1));
493 RR(VID_ATTRIBUTES(1));
494 RR(VID_FIFO_THRESHOLD(1));
495 RR(VID_ROW_INC(1));
496 RR(VID_PIXEL_INC(1));
497 RR(VID_FIR(1));
498 RR(VID_PICTURE_SIZE(1));
499 RR(VID_ACCU0(1));
500 RR(VID_ACCU1(1));
501
502 RR(VID_FIR_COEF_H(1, 0));
503 RR(VID_FIR_COEF_H(1, 1));
504 RR(VID_FIR_COEF_H(1, 2));
505 RR(VID_FIR_COEF_H(1, 3));
506 RR(VID_FIR_COEF_H(1, 4));
507 RR(VID_FIR_COEF_H(1, 5));
508 RR(VID_FIR_COEF_H(1, 6));
509 RR(VID_FIR_COEF_H(1, 7));
510
511 RR(VID_FIR_COEF_HV(1, 0));
512 RR(VID_FIR_COEF_HV(1, 1));
513 RR(VID_FIR_COEF_HV(1, 2));
514 RR(VID_FIR_COEF_HV(1, 3));
515 RR(VID_FIR_COEF_HV(1, 4));
516 RR(VID_FIR_COEF_HV(1, 5));
517 RR(VID_FIR_COEF_HV(1, 6));
518 RR(VID_FIR_COEF_HV(1, 7));
519
520 RR(VID_CONV_COEF(1, 0));
521 RR(VID_CONV_COEF(1, 1));
522 RR(VID_CONV_COEF(1, 2));
523 RR(VID_CONV_COEF(1, 3));
524 RR(VID_CONV_COEF(1, 4));
525
526 RR(VID_FIR_COEF_V(1, 0));
527 RR(VID_FIR_COEF_V(1, 1));
528 RR(VID_FIR_COEF_V(1, 2));
529 RR(VID_FIR_COEF_V(1, 3));
530 RR(VID_FIR_COEF_V(1, 4));
531 RR(VID_FIR_COEF_V(1, 5));
532 RR(VID_FIR_COEF_V(1, 6));
533 RR(VID_FIR_COEF_V(1, 7));
534
535 RR(VID_PRELOAD(1));
536
537 /* enable last, because LCD & DIGIT enable are here */
538 RR(CONTROL);
2a205f34
SS		 539 if (dss_has_feature(FEAT_MGR_LCD2))
540 RR(CONTROL2);
75c7d59d
VS		 541 /* clear spurious SYNC_LOST_DIGIT interrupts */
542 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
543
544 /*
545 * enable last so IRQs won't trigger before
546 * the context is fully restored
547 */
548 RR(IRQENABLE);
80c39712
TV		 549}
550
551#undef SR
552#undef RR
553
554static inline void enable_clocks(bool enable)
555{
556 if (enable)
6af9cd14 557 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712 558 else
6af9cd14 559 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 560}
561
562bool dispc_go_busy(enum omap_channel channel)
563{
564 int bit;
565
2a205f34
SS		 566 if (channel == OMAP_DSS_CHANNEL_LCD ||
567 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 568 bit = 5; /* GOLCD */
569 else
570 bit = 6; /* GODIGIT */
571
2a205f34
SS		 572 if (channel == OMAP_DSS_CHANNEL_LCD2)
573 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
574 else
575 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 576}
577
578void dispc_go(enum omap_channel channel)
579{
580 int bit;
2a205f34 581 bool enable_bit, go_bit;
80c39712
TV		 582
583 enable_clocks(1);
584
2a205f34
SS		 585 if (channel == OMAP_DSS_CHANNEL_LCD ||
586 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 587 bit = 0; /* LCDENABLE */
588 else
589 bit = 1; /* DIGITALENABLE */
590
591 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 592 if (channel == OMAP_DSS_CHANNEL_LCD2)
593 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
594 else
595 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
596
597 if (!enable_bit)
80c39712
TV		 598 goto end;
599
2a205f34
SS		 600 if (channel == OMAP_DSS_CHANNEL_LCD ||
601 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 602 bit = 5; /* GOLCD */
603 else
604 bit = 6; /* GODIGIT */
605
2a205f34
SS		 606 if (channel == OMAP_DSS_CHANNEL_LCD2)
607 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
608 else
609 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
610
611 if (go_bit) {
80c39712
TV		 612 DSSERR("GO bit not down for channel %d\n", channel);
613 goto end;
614 }
615
2a205f34
SS		 616 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
617 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 618
2a205f34
SS		 619 if (channel == OMAP_DSS_CHANNEL_LCD2)
620 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
621 else
622 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 623end:
624 enable_clocks(0);
625}
626
627static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
628{
629 BUG_ON(plane == OMAP_DSS_GFX);
630
631 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
632}
633
634static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
635{
636 BUG_ON(plane == OMAP_DSS_GFX);
637
638 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
639}
640
641static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
642{
643 BUG_ON(plane == OMAP_DSS_GFX);
644
645 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
646}
647
648static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
649 int vscaleup, int five_taps)
650{
651 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 652 static const struct dispc_h_coef coef_hup[8] = {
653 { 0, 0, 128, 0, 0 },
654 { -1, 13, 124, -8, 0 },
655 { -2, 30, 112, -11, -1 },
656 { -5, 51, 95, -11, -2 },
657 { 0, -9, 73, 73, -9 },
658 { -2, -11, 95, 51, -5 },
659 { -1, -11, 112, 30, -2 },
660 { 0, -8, 124, 13, -1 },
80c39712
TV		 661 };
662
66be8f6c
GI		 663 /* Coefficients for vertical up-sampling */
664 static const struct dispc_v_coef coef_vup_3tap[8] = {
665 { 0, 0, 128, 0, 0 },
666 { 0, 3, 123, 2, 0 },
667 { 0, 12, 111, 5, 0 },
668 { 0, 32, 89, 7, 0 },
669 { 0, 0, 64, 64, 0 },
670 { 0, 7, 89, 32, 0 },
671 { 0, 5, 111, 12, 0 },
672 { 0, 2, 123, 3, 0 },
80c39712
TV		 673 };
674
66be8f6c
GI		 675 static const struct dispc_v_coef coef_vup_5tap[8] = {
676 { 0, 0, 128, 0, 0 },
677 { -1, 13, 124, -8, 0 },
678 { -2, 30, 112, -11, -1 },
679 { -5, 51, 95, -11, -2 },
680 { 0, -9, 73, 73, -9 },
681 { -2, -11, 95, 51, -5 },
682 { -1, -11, 112, 30, -2 },
683 { 0, -8, 124, 13, -1 },
80c39712
TV		 684 };
685
66be8f6c
GI		 686 /* Coefficients for horizontal down-sampling */
687 static const struct dispc_h_coef coef_hdown[8] = {
688 { 0, 36, 56, 36, 0 },
689 { 4, 40, 55, 31, -2 },
690 { 8, 44, 54, 27, -5 },
691 { 12, 48, 53, 22, -7 },
692 { -9, 17, 52, 51, 17 },
693 { -7, 22, 53, 48, 12 },
694 { -5, 27, 54, 44, 8 },
695 { -2, 31, 55, 40, 4 },
80c39712
TV		 696 };
697
66be8f6c
GI		 698 /* Coefficients for vertical down-sampling */
699 static const struct dispc_v_coef coef_vdown_3tap[8] = {
700 { 0, 36, 56, 36, 0 },
701 { 0, 40, 57, 31, 0 },
702 { 0, 45, 56, 27, 0 },
703 { 0, 50, 55, 23, 0 },
704 { 0, 18, 55, 55, 0 },
705 { 0, 23, 55, 50, 0 },
706 { 0, 27, 56, 45, 0 },
707 { 0, 31, 57, 40, 0 },
80c39712
TV		 708 };
709
66be8f6c
GI		 710 static const struct dispc_v_coef coef_vdown_5tap[8] = {
711 { 0, 36, 56, 36, 0 },
712 { 4, 40, 55, 31, -2 },
713 { 8, 44, 54, 27, -5 },
714 { 12, 48, 53, 22, -7 },
715 { -9, 17, 52, 51, 17 },
716 { -7, 22, 53, 48, 12 },
717 { -5, 27, 54, 44, 8 },
718 { -2, 31, 55, 40, 4 },
80c39712
TV		 719 };
720
66be8f6c
GI		 721 const struct dispc_h_coef *h_coef;
722 const struct dispc_v_coef *v_coef;
80c39712
TV		 723 int i;
724
725 if (hscaleup)
726 h_coef = coef_hup;
727 else
728 h_coef = coef_hdown;
729
66be8f6c
GI		 730 if (vscaleup)
731 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
732 else
733 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 734
735 for (i = 0; i < 8; i++) {
736 u32 h, hv;
737
66be8f6c
GI		 738 h = FLD_VAL(h_coef[i].hc0, 7, 0)
739 | FLD_VAL(h_coef[i].hc1, 15, 8)
740 | FLD_VAL(h_coef[i].hc2, 23, 16)
741 | FLD_VAL(h_coef[i].hc3, 31, 24);
742 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
743 | FLD_VAL(v_coef[i].vc0, 15, 8)
744 | FLD_VAL(v_coef[i].vc1, 23, 16)
745 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712
TV		 746
747 _dispc_write_firh_reg(plane, i, h);
748 _dispc_write_firhv_reg(plane, i, hv);
749 }
750
66be8f6c
GI		 751 if (five_taps) {
752 for (i = 0; i < 8; i++) {
753 u32 v;
754 v = FLD_VAL(v_coef[i].vc00, 7, 0)
755 | FLD_VAL(v_coef[i].vc22, 15, 8);
756 _dispc_write_firv_reg(plane, i, v);
757 }
80c39712
TV		 758 }
759}
760
761static void _dispc_setup_color_conv_coef(void)
762{
763 const struct color_conv_coef {
764 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
765 int full_range;
766 } ctbl_bt601_5 = {
767 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
768 };
769
770 const struct color_conv_coef *ct;
771
772#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
773
774 ct = &ctbl_bt601_5;
775
776 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
777 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
778 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
779 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
780 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
781
782 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
783 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
784 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
785 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
786 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
787
788#undef CVAL
789
790 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
791 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
792}
793
794
795static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
796{
797 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
798 DISPC_VID_BA0(0),
799 DISPC_VID_BA0(1) };
800
801 dispc_write_reg(ba0_reg[plane], paddr);
802}
803
804static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
805{
806 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
807 DISPC_VID_BA1(0),
808 DISPC_VID_BA1(1) };
809
810 dispc_write_reg(ba1_reg[plane], paddr);
811}
812
813static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
814{
815 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
816 DISPC_VID_POSITION(0),
817 DISPC_VID_POSITION(1) };
818
819 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
820 dispc_write_reg(pos_reg[plane], val);
821}
822
823static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
824{
825 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
826 DISPC_VID_PICTURE_SIZE(0),
827 DISPC_VID_PICTURE_SIZE(1) };
828 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
829 dispc_write_reg(siz_reg[plane], val);
830}
831
832static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
833{
834 u32 val;
835 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
836 DISPC_VID_SIZE(1) };
837
838 BUG_ON(plane == OMAP_DSS_GFX);
839
840 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
841 dispc_write_reg(vsi_reg[plane-1], val);
842}
843
fd28a390
R		 844static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
845{
846 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
847 return;
848
849 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
850 plane == OMAP_DSS_VIDEO1)
851 return;
852
853 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
854}
855
80c39712
TV		 856static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
857{
a0acb557 858 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 859 return;
860
fd28a390
R		 861 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
862 plane == OMAP_DSS_VIDEO1)
863 return;
a0acb557 864
80c39712
TV		 865 if (plane == OMAP_DSS_GFX)
866 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
867 else if (plane == OMAP_DSS_VIDEO2)
868 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
869}
870
871static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
872{
873 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
874 DISPC_VID_PIXEL_INC(0),
875 DISPC_VID_PIXEL_INC(1) };
876
877 dispc_write_reg(ri_reg[plane], inc);
878}
879
880static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
881{
882 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
883 DISPC_VID_ROW_INC(0),
884 DISPC_VID_ROW_INC(1) };
885
886 dispc_write_reg(ri_reg[plane], inc);
887}
888
889static void _dispc_set_color_mode(enum omap_plane plane,
890 enum omap_color_mode color_mode)
891{
892 u32 m = 0;
893
894 switch (color_mode) {
895 case OMAP_DSS_COLOR_CLUT1:
896 m = 0x0; break;
897 case OMAP_DSS_COLOR_CLUT2:
898 m = 0x1; break;
899 case OMAP_DSS_COLOR_CLUT4:
900 m = 0x2; break;
901 case OMAP_DSS_COLOR_CLUT8:
902 m = 0x3; break;
903 case OMAP_DSS_COLOR_RGB12U:
904 m = 0x4; break;
905 case OMAP_DSS_COLOR_ARGB16:
906 m = 0x5; break;
907 case OMAP_DSS_COLOR_RGB16:
908 m = 0x6; break;
909 case OMAP_DSS_COLOR_RGB24U:
910 m = 0x8; break;
911 case OMAP_DSS_COLOR_RGB24P:
912 m = 0x9; break;
913 case OMAP_DSS_COLOR_YUV2:
914 m = 0xa; break;
915 case OMAP_DSS_COLOR_UYVY:
916 m = 0xb; break;
917 case OMAP_DSS_COLOR_ARGB32:
918 m = 0xc; break;
919 case OMAP_DSS_COLOR_RGBA32:
920 m = 0xd; break;
921 case OMAP_DSS_COLOR_RGBX32:
922 m = 0xe; break;
923 default:
924 BUG(); break;
925 }
926
927 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
928}
929
930static void _dispc_set_channel_out(enum omap_plane plane,
931 enum omap_channel channel)
932{
933 int shift;
934 u32 val;
2a205f34 935 int chan = 0, chan2 = 0;
80c39712
TV		 936
937 switch (plane) {
938 case OMAP_DSS_GFX:
939 shift = 8;
940 break;
941 case OMAP_DSS_VIDEO1:
942 case OMAP_DSS_VIDEO2:
943 shift = 16;
944 break;
945 default:
946 BUG();
947 return;
948 }
949
950 val = dispc_read_reg(dispc_reg_att[plane]);
2a205f34
SS		 951 if (dss_has_feature(FEAT_MGR_LCD2)) {
952 switch (channel) {
953 case OMAP_DSS_CHANNEL_LCD:
954 chan = 0;
955 chan2 = 0;
956 break;
957 case OMAP_DSS_CHANNEL_DIGIT:
958 chan = 1;
959 chan2 = 0;
960 break;
961 case OMAP_DSS_CHANNEL_LCD2:
962 chan = 0;
963 chan2 = 1;
964 break;
965 default:
966 BUG();
967 }
968
969 val = FLD_MOD(val, chan, shift, shift);
970 val = FLD_MOD(val, chan2, 31, 30);
971 } else {
972 val = FLD_MOD(val, channel, shift, shift);
973 }
80c39712
TV		 974 dispc_write_reg(dispc_reg_att[plane], val);
975}
976
977void dispc_set_burst_size(enum omap_plane plane,
978 enum omap_burst_size burst_size)
979{
980 int shift;
981 u32 val;
982
983 enable_clocks(1);
984
985 switch (plane) {
986 case OMAP_DSS_GFX:
987 shift = 6;
988 break;
989 case OMAP_DSS_VIDEO1:
990 case OMAP_DSS_VIDEO2:
991 shift = 14;
992 break;
993 default:
994 BUG();
995 return;
996 }
997
998 val = dispc_read_reg(dispc_reg_att[plane]);
999 val = FLD_MOD(val, burst_size, shift+1, shift);
1000 dispc_write_reg(dispc_reg_att[plane], val);
1001
1002 enable_clocks(0);
1003}
1004
1005static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1006{
1007 u32 val;
1008
1009 BUG_ON(plane == OMAP_DSS_GFX);
1010
1011 val = dispc_read_reg(dispc_reg_att[plane]);
1012 val = FLD_MOD(val, enable, 9, 9);
1013 dispc_write_reg(dispc_reg_att[plane], val);
1014}
1015
1016void dispc_enable_replication(enum omap_plane plane, bool enable)
1017{
1018 int bit;
1019
1020 if (plane == OMAP_DSS_GFX)
1021 bit = 5;
1022 else
1023 bit = 10;
1024
1025 enable_clocks(1);
1026 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
1027 enable_clocks(0);
1028}
1029
64ba4f74 1030void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1031{
1032 u32 val;
1033 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1034 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1035 enable_clocks(1);
64ba4f74 1036 dispc_write_reg(DISPC_SIZE_LCD(channel), val);
80c39712
TV		 1037 enable_clocks(0);
1038}
1039
1040void dispc_set_digit_size(u16 width, u16 height)
1041{
1042 u32 val;
1043 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1044 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1045 enable_clocks(1);
1046 dispc_write_reg(DISPC_SIZE_DIG, val);
1047 enable_clocks(0);
1048}
1049
1050static void dispc_read_plane_fifo_sizes(void)
1051{
1052 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
1053 DISPC_VID_FIFO_SIZE_STATUS(0),
1054 DISPC_VID_FIFO_SIZE_STATUS(1) };
1055 u32 size;
1056 int plane;
a0acb557 1057 u8 start, end;
80c39712
TV		 1058
1059 enable_clocks(1);
1060
a0acb557 1061 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1062
a0acb557
AT		 1063 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1064 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
80c39712
TV		 1065 dispc.fifo_size[plane] = size;
1066 }
1067
1068 enable_clocks(0);
1069}
1070
1071u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1072{
1073 return dispc.fifo_size[plane];
1074}
1075
1076void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1077{
1078 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1079 DISPC_VID_FIFO_THRESHOLD(0),
1080 DISPC_VID_FIFO_THRESHOLD(1) };
a0acb557
AT		 1081 u8 hi_start, hi_end, lo_start, lo_end;
1082
80c39712
TV		 1083 enable_clocks(1);
1084
1085 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1086 plane,
1087 REG_GET(ftrs_reg[plane], 11, 0),
1088 REG_GET(ftrs_reg[plane], 27, 16),
1089 low, high);
1090
a0acb557
AT		 1091 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1092 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1093
1094 dispc_write_reg(ftrs_reg[plane],
1095 FLD_VAL(high, hi_start, hi_end) |
1096 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1097
1098 enable_clocks(0);
1099}
1100
1101void dispc_enable_fifomerge(bool enable)
1102{
1103 enable_clocks(1);
1104
1105 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1106 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1107
1108 enable_clocks(0);
1109}
1110
1111static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1112{
1113 u32 val;
1114 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1115 DISPC_VID_FIR(1) };
a0acb557 1116 u8 hinc_start, hinc_end, vinc_start, vinc_end;
80c39712
TV		 1117
1118 BUG_ON(plane == OMAP_DSS_GFX);
1119
a0acb557
AT		 1120 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1121 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1122
1123 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1124 FLD_VAL(hinc, hinc_start, hinc_end);
1125
80c39712
TV		 1126 dispc_write_reg(fir_reg[plane-1], val);
1127}
1128
1129static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1130{
1131 u32 val;
1132 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1133 DISPC_VID_ACCU0(1) };
87a7484b 1134 u8 hor_start, hor_end, vert_start, vert_end;
80c39712
TV		 1135
1136 BUG_ON(plane == OMAP_DSS_GFX);
1137
87a7484b
AT		 1138 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1139 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1140
1141 val = FLD_VAL(vaccu, vert_start, vert_end) |
1142 FLD_VAL(haccu, hor_start, hor_end);
1143
80c39712
TV		 1144 dispc_write_reg(ac0_reg[plane-1], val);
1145}
1146
1147static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1148{
1149 u32 val;
1150 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1151 DISPC_VID_ACCU1(1) };
87a7484b 1152 u8 hor_start, hor_end, vert_start, vert_end;
80c39712
TV		 1153
1154 BUG_ON(plane == OMAP_DSS_GFX);
1155
87a7484b
AT		 1156 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1157 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1158
1159 val = FLD_VAL(vaccu, vert_start, vert_end) |
1160 FLD_VAL(haccu, hor_start, hor_end);
1161
80c39712
TV		 1162 dispc_write_reg(ac1_reg[plane-1], val);
1163}
1164
1165
1166static void _dispc_set_scaling(enum omap_plane plane,
1167 u16 orig_width, u16 orig_height,
1168 u16 out_width, u16 out_height,
1169 bool ilace, bool five_taps,
1170 bool fieldmode)
1171{
1172 int fir_hinc;
1173 int fir_vinc;
1174 int hscaleup, vscaleup;
1175 int accu0 = 0;
1176 int accu1 = 0;
1177 u32 l;
1178
1179 BUG_ON(plane == OMAP_DSS_GFX);
1180
1181 hscaleup = orig_width <= out_width;
1182 vscaleup = orig_height <= out_height;
1183
1184 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1185
1186 if (!orig_width || orig_width == out_width)
1187 fir_hinc = 0;
1188 else
1189 fir_hinc = 1024 * orig_width / out_width;
1190
1191 if (!orig_height || orig_height == out_height)
1192 fir_vinc = 0;
1193 else
1194 fir_vinc = 1024 * orig_height / out_height;
1195
1196 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1197
1198 l = dispc_read_reg(dispc_reg_att[plane]);
80c39712 1199
87a7484b
AT		 1200 /* RESIZEENABLE and VERTICALTAPS */
1201 l &= ~((0x3 << 5) | (0x1 << 21));
80c39712
TV		 1202 l |= fir_hinc ? (1 << 5) : 0;
1203 l |= fir_vinc ? (1 << 6) : 0;
87a7484b 1204 l |= five_taps ? (1 << 21) : 0;
80c39712 1205
87a7484b
AT		 1206 /* VRESIZECONF and HRESIZECONF */
1207 if (dss_has_feature(FEAT_RESIZECONF)) {
1208 l &= ~(0x3 << 7);
1209 l |= hscaleup ? 0 : (1 << 7);
1210 l |= vscaleup ? 0 : (1 << 8);
1211 }
80c39712 1212
87a7484b
AT		 1213 /* LINEBUFFERSPLIT */
1214 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1215 l &= ~(0x1 << 22);
1216 l |= five_taps ? (1 << 22) : 0;
1217 }
80c39712
TV		 1218
1219 dispc_write_reg(dispc_reg_att[plane], l);
1220
1221 /*
1222 * field 0 = even field = bottom field
1223 * field 1 = odd field = top field
1224 */
1225 if (ilace && !fieldmode) {
1226 accu1 = 0;
1227 accu0 = (fir_vinc / 2) & 0x3ff;
1228 if (accu0 >= 1024/2) {
1229 accu1 = 1024/2;
1230 accu0 -= accu1;
1231 }
1232 }
1233
1234 _dispc_set_vid_accu0(plane, 0, accu0);
1235 _dispc_set_vid_accu1(plane, 0, accu1);
1236}
1237
1238static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1239 bool mirroring, enum omap_color_mode color_mode)
1240{
87a7484b
AT		 1241 bool row_repeat = false;
1242 int vidrot = 0;
1243
80c39712
TV		 1244 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1245 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1246
1247 if (mirroring) {
1248 switch (rotation) {
1249 case OMAP_DSS_ROT_0:
1250 vidrot = 2;
1251 break;
1252 case OMAP_DSS_ROT_90:
1253 vidrot = 1;
1254 break;
1255 case OMAP_DSS_ROT_180:
1256 vidrot = 0;
1257 break;
1258 case OMAP_DSS_ROT_270:
1259 vidrot = 3;
1260 break;
1261 }
1262 } else {
1263 switch (rotation) {
1264 case OMAP_DSS_ROT_0:
1265 vidrot = 0;
1266 break;
1267 case OMAP_DSS_ROT_90:
1268 vidrot = 1;
1269 break;
1270 case OMAP_DSS_ROT_180:
1271 vidrot = 2;
1272 break;
1273 case OMAP_DSS_ROT_270:
1274 vidrot = 3;
1275 break;
1276 }
1277 }
1278
80c39712 1279 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1280 row_repeat = true;
80c39712 1281 else
87a7484b 1282 row_repeat = false;
80c39712 1283 }
87a7484b
AT		 1284
1285 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1286 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1287 REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1288}
1289
1290static int color_mode_to_bpp(enum omap_color_mode color_mode)
1291{
1292 switch (color_mode) {
1293 case OMAP_DSS_COLOR_CLUT1:
1294 return 1;
1295 case OMAP_DSS_COLOR_CLUT2:
1296 return 2;
1297 case OMAP_DSS_COLOR_CLUT4:
1298 return 4;
1299 case OMAP_DSS_COLOR_CLUT8:
1300 return 8;
1301 case OMAP_DSS_COLOR_RGB12U:
1302 case OMAP_DSS_COLOR_RGB16:
1303 case OMAP_DSS_COLOR_ARGB16:
1304 case OMAP_DSS_COLOR_YUV2:
1305 case OMAP_DSS_COLOR_UYVY:
1306 return 16;
1307 case OMAP_DSS_COLOR_RGB24P:
1308 return 24;
1309 case OMAP_DSS_COLOR_RGB24U:
1310 case OMAP_DSS_COLOR_ARGB32:
1311 case OMAP_DSS_COLOR_RGBA32:
1312 case OMAP_DSS_COLOR_RGBX32:
1313 return 32;
1314 default:
1315 BUG();
1316 }
1317}
1318
1319static s32 pixinc(int pixels, u8 ps)
1320{
1321 if (pixels == 1)
1322 return 1;
1323 else if (pixels > 1)
1324 return 1 + (pixels - 1) * ps;
1325 else if (pixels < 0)
1326 return 1 - (-pixels + 1) * ps;
1327 else
1328 BUG();
1329}
1330
1331static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1332 u16 screen_width,
1333 u16 width, u16 height,
1334 enum omap_color_mode color_mode, bool fieldmode,
1335 unsigned int field_offset,
1336 unsigned *offset0, unsigned *offset1,
1337 s32 *row_inc, s32 *pix_inc)
1338{
1339 u8 ps;
1340
1341 /* FIXME CLUT formats */
1342 switch (color_mode) {
1343 case OMAP_DSS_COLOR_CLUT1:
1344 case OMAP_DSS_COLOR_CLUT2:
1345 case OMAP_DSS_COLOR_CLUT4:
1346 case OMAP_DSS_COLOR_CLUT8:
1347 BUG();
1348 return;
1349 case OMAP_DSS_COLOR_YUV2:
1350 case OMAP_DSS_COLOR_UYVY:
1351 ps = 4;
1352 break;
1353 default:
1354 ps = color_mode_to_bpp(color_mode) / 8;
1355 break;
1356 }
1357
1358 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1359 width, height);
1360
1361 /*
1362 * field 0 = even field = bottom field
1363 * field 1 = odd field = top field
1364 */
1365 switch (rotation + mirror * 4) {
1366 case OMAP_DSS_ROT_0:
1367 case OMAP_DSS_ROT_180:
1368 /*
1369 * If the pixel format is YUV or UYVY divide the width
1370 * of the image by 2 for 0 and 180 degree rotation.
1371 */
1372 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1373 color_mode == OMAP_DSS_COLOR_UYVY)
1374 width = width >> 1;
1375 case OMAP_DSS_ROT_90:
1376 case OMAP_DSS_ROT_270:
1377 *offset1 = 0;
1378 if (field_offset)
1379 *offset0 = field_offset * screen_width * ps;
1380 else
1381 *offset0 = 0;
1382
1383 *row_inc = pixinc(1 + (screen_width - width) +
1384 (fieldmode ? screen_width : 0),
1385 ps);
1386 *pix_inc = pixinc(1, ps);
1387 break;
1388
1389 case OMAP_DSS_ROT_0 + 4:
1390 case OMAP_DSS_ROT_180 + 4:
1391 /* If the pixel format is YUV or UYVY divide the width
1392 * of the image by 2 for 0 degree and 180 degree
1393 */
1394 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1395 color_mode == OMAP_DSS_COLOR_UYVY)
1396 width = width >> 1;
1397 case OMAP_DSS_ROT_90 + 4:
1398 case OMAP_DSS_ROT_270 + 4:
1399 *offset1 = 0;
1400 if (field_offset)
1401 *offset0 = field_offset * screen_width * ps;
1402 else
1403 *offset0 = 0;
1404 *row_inc = pixinc(1 - (screen_width + width) -
1405 (fieldmode ? screen_width : 0),
1406 ps);
1407 *pix_inc = pixinc(1, ps);
1408 break;
1409
1410 default:
1411 BUG();
1412 }
1413}
1414
1415static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1416 u16 screen_width,
1417 u16 width, u16 height,
1418 enum omap_color_mode color_mode, bool fieldmode,
1419 unsigned int field_offset,
1420 unsigned *offset0, unsigned *offset1,
1421 s32 *row_inc, s32 *pix_inc)
1422{
1423 u8 ps;
1424 u16 fbw, fbh;
1425
1426 /* FIXME CLUT formats */
1427 switch (color_mode) {
1428 case OMAP_DSS_COLOR_CLUT1:
1429 case OMAP_DSS_COLOR_CLUT2:
1430 case OMAP_DSS_COLOR_CLUT4:
1431 case OMAP_DSS_COLOR_CLUT8:
1432 BUG();
1433 return;
1434 default:
1435 ps = color_mode_to_bpp(color_mode) / 8;
1436 break;
1437 }
1438
1439 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1440 width, height);
1441
1442 /* width & height are overlay sizes, convert to fb sizes */
1443
1444 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1445 fbw = width;
1446 fbh = height;
1447 } else {
1448 fbw = height;
1449 fbh = width;
1450 }
1451
1452 /*
1453 * field 0 = even field = bottom field
1454 * field 1 = odd field = top field
1455 */
1456 switch (rotation + mirror * 4) {
1457 case OMAP_DSS_ROT_0:
1458 *offset1 = 0;
1459 if (field_offset)
1460 *offset0 = *offset1 + field_offset * screen_width * ps;
1461 else
1462 *offset0 = *offset1;
1463 *row_inc = pixinc(1 + (screen_width - fbw) +
1464 (fieldmode ? screen_width : 0),
1465 ps);
1466 *pix_inc = pixinc(1, ps);
1467 break;
1468 case OMAP_DSS_ROT_90:
1469 *offset1 = screen_width * (fbh - 1) * ps;
1470 if (field_offset)
1471 *offset0 = *offset1 + field_offset * ps;
1472 else
1473 *offset0 = *offset1;
1474 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1475 (fieldmode ? 1 : 0), ps);
1476 *pix_inc = pixinc(-screen_width, ps);
1477 break;
1478 case OMAP_DSS_ROT_180:
1479 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1480 if (field_offset)
1481 *offset0 = *offset1 - field_offset * screen_width * ps;
1482 else
1483 *offset0 = *offset1;
1484 *row_inc = pixinc(-1 -
1485 (screen_width - fbw) -
1486 (fieldmode ? screen_width : 0),
1487 ps);
1488 *pix_inc = pixinc(-1, ps);
1489 break;
1490 case OMAP_DSS_ROT_270:
1491 *offset1 = (fbw - 1) * ps;
1492 if (field_offset)
1493 *offset0 = *offset1 - field_offset * ps;
1494 else
1495 *offset0 = *offset1;
1496 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1497 (fieldmode ? 1 : 0), ps);
1498 *pix_inc = pixinc(screen_width, ps);
1499 break;
1500
1501 /* mirroring */
1502 case OMAP_DSS_ROT_0 + 4:
1503 *offset1 = (fbw - 1) * ps;
1504 if (field_offset)
1505 *offset0 = *offset1 + field_offset * screen_width * ps;
1506 else
1507 *offset0 = *offset1;
1508 *row_inc = pixinc(screen_width * 2 - 1 +
1509 (fieldmode ? screen_width : 0),
1510 ps);
1511 *pix_inc = pixinc(-1, ps);
1512 break;
1513
1514 case OMAP_DSS_ROT_90 + 4:
1515 *offset1 = 0;
1516 if (field_offset)
1517 *offset0 = *offset1 + field_offset * ps;
1518 else
1519 *offset0 = *offset1;
1520 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1521 (fieldmode ? 1 : 0),
1522 ps);
1523 *pix_inc = pixinc(screen_width, ps);
1524 break;
1525
1526 case OMAP_DSS_ROT_180 + 4:
1527 *offset1 = screen_width * (fbh - 1) * ps;
1528 if (field_offset)
1529 *offset0 = *offset1 - field_offset * screen_width * ps;
1530 else
1531 *offset0 = *offset1;
1532 *row_inc = pixinc(1 - screen_width * 2 -
1533 (fieldmode ? screen_width : 0),
1534 ps);
1535 *pix_inc = pixinc(1, ps);
1536 break;
1537
1538 case OMAP_DSS_ROT_270 + 4:
1539 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1540 if (field_offset)
1541 *offset0 = *offset1 - field_offset * ps;
1542 else
1543 *offset0 = *offset1;
1544 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1545 (fieldmode ? 1 : 0),
1546 ps);
1547 *pix_inc = pixinc(-screen_width, ps);
1548 break;
1549
1550 default:
1551 BUG();
1552 }
1553}
1554
ff1b2cde
SS		 1555static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1556 u16 height, u16 out_width, u16 out_height,
1557 enum omap_color_mode color_mode)
80c39712
TV		 1558{
1559 u32 fclk = 0;
1560 /* FIXME venc pclk? */
ff1b2cde 1561 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1562
1563 if (height > out_height) {
1564 /* FIXME get real display PPL */
1565 unsigned int ppl = 800;
1566
1567 tmp = pclk * height * out_width;
1568 do_div(tmp, 2 * out_height * ppl);
1569 fclk = tmp;
1570
2d9c5597
VS		 1571 if (height > 2 * out_height) {
1572 if (ppl == out_width)
1573 return 0;
1574
80c39712
TV		 1575 tmp = pclk * (height - 2 * out_height) * out_width;
1576 do_div(tmp, 2 * out_height * (ppl - out_width));
1577 fclk = max(fclk, (u32) tmp);
1578 }
1579 }
1580
1581 if (width > out_width) {
1582 tmp = pclk * width;
1583 do_div(tmp, out_width);
1584 fclk = max(fclk, (u32) tmp);
1585
1586 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1587 fclk <<= 1;
1588 }
1589
1590 return fclk;
1591}
1592
ff1b2cde
SS		 1593static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1594 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1595{
1596 unsigned int hf, vf;
1597
1598 /*
1599 * FIXME how to determine the 'A' factor
1600 * for the no downscaling case ?
1601 */
1602
1603 if (width > 3 * out_width)
1604 hf = 4;
1605 else if (width > 2 * out_width)
1606 hf = 3;
1607 else if (width > out_width)
1608 hf = 2;
1609 else
1610 hf = 1;
1611
1612 if (height > out_height)
1613 vf = 2;
1614 else
1615 vf = 1;
1616
1617 /* FIXME venc pclk? */
ff1b2cde 1618 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1619}
1620
1621void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1622{
1623 enable_clocks(1);
1624 _dispc_set_channel_out(plane, channel_out);
1625 enable_clocks(0);
1626}
1627
1628static int _dispc_setup_plane(enum omap_plane plane,
1629 u32 paddr, u16 screen_width,
1630 u16 pos_x, u16 pos_y,
1631 u16 width, u16 height,
1632 u16 out_width, u16 out_height,
1633 enum omap_color_mode color_mode,
1634 bool ilace,
1635 enum omap_dss_rotation_type rotation_type,
1636 u8 rotation, int mirror,
18faa1b6
SS		 1637 u8 global_alpha, u8 pre_mult_alpha,
1638 enum omap_channel channel)
80c39712
TV		 1639{
1640 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1641 bool five_taps = 0;
1642 bool fieldmode = 0;
1643 int cconv = 0;
1644 unsigned offset0, offset1;
1645 s32 row_inc;
1646 s32 pix_inc;
1647 u16 frame_height = height;
1648 unsigned int field_offset = 0;
1649
1650 if (paddr == 0)
1651 return -EINVAL;
1652
1653 if (ilace && height == out_height)
1654 fieldmode = 1;
1655
1656 if (ilace) {
1657 if (fieldmode)
1658 height /= 2;
1659 pos_y /= 2;
1660 out_height /= 2;
1661
1662 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1663 "out_height %d\n",
1664 height, pos_y, out_height);
1665 }
1666
8dad2ab6
AT		 1667 if (!dss_feat_color_mode_supported(plane, color_mode))
1668 return -EINVAL;
1669
80c39712
TV		 1670 if (plane == OMAP_DSS_GFX) {
1671 if (width != out_width || height != out_height)
1672 return -EINVAL;
80c39712
TV		 1673 } else {
1674 /* video plane */
1675
1676 unsigned long fclk = 0;
1677
1678 if (out_width < width / maxdownscale ||
1679 out_width > width * 8)
1680 return -EINVAL;
1681
1682 if (out_height < height / maxdownscale ||
1683 out_height > height * 8)
1684 return -EINVAL;
1685
8dad2ab6
AT		 1686 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1687 color_mode == OMAP_DSS_COLOR_UYVY)
80c39712 1688 cconv = 1;
80c39712
TV		 1689
1690 /* Must use 5-tap filter? */
1691 five_taps = height > out_height * 2;
1692
1693 if (!five_taps) {
18faa1b6
SS		 1694 fclk = calc_fclk(channel, width, height, out_width,
1695 out_height);
80c39712
TV		 1696
1697 /* Try 5-tap filter if 3-tap fclk is too high */
1698 if (cpu_is_omap34xx() && height > out_height &&
1699 fclk > dispc_fclk_rate())
1700 five_taps = true;
1701 }
1702
1703 if (width > (2048 >> five_taps)) {
1704 DSSERR("failed to set up scaling, fclk too low\n");
1705 return -EINVAL;
1706 }
1707
1708 if (five_taps)
18faa1b6
SS		 1709 fclk = calc_fclk_five_taps(channel, width, height,
1710 out_width, out_height, color_mode);
80c39712
TV		 1711
1712 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1713 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1714
2d9c5597 1715 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1716 DSSERR("failed to set up scaling, "
1717 "required fclk rate = %lu Hz, "
1718 "current fclk rate = %lu Hz\n",
1719 fclk, dispc_fclk_rate());
1720 return -EINVAL;
1721 }
1722 }
1723
1724 if (ilace && !fieldmode) {
1725 /*
1726 * when downscaling the bottom field may have to start several
1727 * source lines below the top field. Unfortunately ACCUI
1728 * registers will only hold the fractional part of the offset
1729 * so the integer part must be added to the base address of the
1730 * bottom field.
1731 */
1732 if (!height || height == out_height)
1733 field_offset = 0;
1734 else
1735 field_offset = height / out_height / 2;
1736 }
1737
1738 /* Fields are independent but interleaved in memory. */
1739 if (fieldmode)
1740 field_offset = 1;
1741
1742 if (rotation_type == OMAP_DSS_ROT_DMA)
1743 calc_dma_rotation_offset(rotation, mirror,
1744 screen_width, width, frame_height, color_mode,
1745 fieldmode, field_offset,
1746 &offset0, &offset1, &row_inc, &pix_inc);
1747 else
1748 calc_vrfb_rotation_offset(rotation, mirror,
1749 screen_width, width, frame_height, color_mode,
1750 fieldmode, field_offset,
1751 &offset0, &offset1, &row_inc, &pix_inc);
1752
1753 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1754 offset0, offset1, row_inc, pix_inc);
1755
1756 _dispc_set_color_mode(plane, color_mode);
1757
1758 _dispc_set_plane_ba0(plane, paddr + offset0);
1759 _dispc_set_plane_ba1(plane, paddr + offset1);
1760
1761 _dispc_set_row_inc(plane, row_inc);
1762 _dispc_set_pix_inc(plane, pix_inc);
1763
1764 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1765 out_width, out_height);
1766
1767 _dispc_set_plane_pos(plane, pos_x, pos_y);
1768
1769 _dispc_set_pic_size(plane, width, height);
1770
1771 if (plane != OMAP_DSS_GFX) {
1772 _dispc_set_scaling(plane, width, height,
1773 out_width, out_height,
1774 ilace, five_taps, fieldmode);
1775 _dispc_set_vid_size(plane, out_width, out_height);
1776 _dispc_set_vid_color_conv(plane, cconv);
1777 }
1778
1779 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1780
fd28a390
R		 1781 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1782 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 1783
1784 return 0;
1785}
1786
1787static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1788{
1789 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1790}
1791
1792static void dispc_disable_isr(void *data, u32 mask)
1793{
1794 struct completion *compl = data;
1795 complete(compl);
1796}
1797
2a205f34 1798static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1799{
2a205f34
SS		 1800 if (channel == OMAP_DSS_CHANNEL_LCD2)
1801 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1802 else
1803 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1804}
1805
2a205f34 1806static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1807{
1808 struct completion frame_done_completion;
1809 bool is_on;
1810 int r;
2a205f34 1811 u32 irq;
80c39712
TV		 1812
1813 enable_clocks(1);
1814
1815 /* When we disable LCD output, we need to wait until frame is done.
1816 * Otherwise the DSS is still working, and turning off the clocks
1817 * prevents DSS from going to OFF mode */
2a205f34
SS		 1818 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1819 REG_GET(DISPC_CONTROL2, 0, 0) :
1820 REG_GET(DISPC_CONTROL, 0, 0);
1821
1822 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1823 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1824
1825 if (!enable && is_on) {
1826 init_completion(&frame_done_completion);
1827
1828 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1829 &frame_done_completion, irq);
80c39712
TV		 1830
1831 if (r)
1832 DSSERR("failed to register FRAMEDONE isr\n");
1833 }
1834
2a205f34 1835 _enable_lcd_out(channel, enable);
80c39712
TV		 1836
1837 if (!enable && is_on) {
1838 if (!wait_for_completion_timeout(&frame_done_completion,
1839 msecs_to_jiffies(100)))
1840 DSSERR("timeout waiting for FRAME DONE\n");
1841
1842 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1843 &frame_done_completion, irq);
80c39712
TV		 1844
1845 if (r)
1846 DSSERR("failed to unregister FRAMEDONE isr\n");
1847 }
1848
1849 enable_clocks(0);
1850}
1851
1852static void _enable_digit_out(bool enable)
1853{
1854 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1855}
1856
a2faee84 1857static void dispc_enable_digit_out(bool enable)
80c39712
TV		 1858{
1859 struct completion frame_done_completion;
1860 int r;
1861
1862 enable_clocks(1);
1863
1864 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1865 enable_clocks(0);
1866 return;
1867 }
1868
1869 if (enable) {
1870 unsigned long flags;
1871 /* When we enable digit output, we'll get an extra digit
1872 * sync lost interrupt, that we need to ignore */
1873 spin_lock_irqsave(&dispc.irq_lock, flags);
1874 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1875 _omap_dispc_set_irqs();
1876 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1877 }
1878
1879 /* When we disable digit output, we need to wait until fields are done.
1880 * Otherwise the DSS is still working, and turning off the clocks
1881 * prevents DSS from going to OFF mode. And when enabling, we need to
1882 * wait for the extra sync losts */
1883 init_completion(&frame_done_completion);
1884
1885 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1886 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1887 if (r)
1888 DSSERR("failed to register EVSYNC isr\n");
1889
1890 _enable_digit_out(enable);
1891
1892 /* XXX I understand from TRM that we should only wait for the
1893 * current field to complete. But it seems we have to wait
1894 * for both fields */
1895 if (!wait_for_completion_timeout(&frame_done_completion,
1896 msecs_to_jiffies(100)))
1897 DSSERR("timeout waiting for EVSYNC\n");
1898
1899 if (!wait_for_completion_timeout(&frame_done_completion,
1900 msecs_to_jiffies(100)))
1901 DSSERR("timeout waiting for EVSYNC\n");
1902
1903 r = omap_dispc_unregister_isr(dispc_disable_isr,
1904 &frame_done_completion,
1905 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1906 if (r)
1907 DSSERR("failed to unregister EVSYNC isr\n");
1908
1909 if (enable) {
1910 unsigned long flags;
1911 spin_lock_irqsave(&dispc.irq_lock, flags);
1912 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 1913 if (dss_has_feature(FEAT_MGR_LCD2))
1914 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 1915 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1916 _omap_dispc_set_irqs();
1917 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1918 }
1919
1920 enable_clocks(0);
1921}
1922
a2faee84
TV		 1923bool dispc_is_channel_enabled(enum omap_channel channel)
1924{
1925 if (channel == OMAP_DSS_CHANNEL_LCD)
1926 return !!REG_GET(DISPC_CONTROL, 0, 0);
1927 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1928 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 1929 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1930 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 1931 else
1932 BUG();
1933}
1934
1935void dispc_enable_channel(enum omap_channel channel, bool enable)
1936{
2a205f34
SS		 1937 if (channel == OMAP_DSS_CHANNEL_LCD ||
1938 channel == OMAP_DSS_CHANNEL_LCD2)
1939 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 1940 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1941 dispc_enable_digit_out(enable);
1942 else
1943 BUG();
1944}
1945
80c39712
TV		 1946void dispc_lcd_enable_signal_polarity(bool act_high)
1947{
6ced40bf
AT		 1948 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1949 return;
1950
80c39712
TV		 1951 enable_clocks(1);
1952 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1953 enable_clocks(0);
1954}
1955
1956void dispc_lcd_enable_signal(bool enable)
1957{
6ced40bf
AT		 1958 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1959 return;
1960
80c39712
TV		 1961 enable_clocks(1);
1962 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1963 enable_clocks(0);
1964}
1965
1966void dispc_pck_free_enable(bool enable)
1967{
6ced40bf
AT		 1968 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1969 return;
1970
80c39712
TV		 1971 enable_clocks(1);
1972 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1973 enable_clocks(0);
1974}
1975
64ba4f74 1976void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712
TV		 1977{
1978 enable_clocks(1);
2a205f34
SS		 1979 if (channel == OMAP_DSS_CHANNEL_LCD2)
1980 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1981 else
1982 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 1983 enable_clocks(0);
1984}
1985
1986
64ba4f74
SS		 1987void dispc_set_lcd_display_type(enum omap_channel channel,
1988 enum omap_lcd_display_type type)
80c39712
TV		 1989{
1990 int mode;
1991
1992 switch (type) {
1993 case OMAP_DSS_LCD_DISPLAY_STN:
1994 mode = 0;
1995 break;
1996
1997 case OMAP_DSS_LCD_DISPLAY_TFT:
1998 mode = 1;
1999 break;
2000
2001 default:
2002 BUG();
2003 return;
2004 }
2005
2006 enable_clocks(1);
2a205f34
SS		 2007 if (channel == OMAP_DSS_CHANNEL_LCD2)
2008 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2009 else
2010 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2011 enable_clocks(0);
2012}
2013
2014void dispc_set_loadmode(enum omap_dss_load_mode mode)
2015{
2016 enable_clocks(1);
2017 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2018 enable_clocks(0);
2019}
2020
2021
2022void dispc_set_default_color(enum omap_channel channel, u32 color)
2023{
80c39712 2024 enable_clocks(1);
8613b000 2025 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2026 enable_clocks(0);
2027}
2028
2029u32 dispc_get_default_color(enum omap_channel channel)
2030{
80c39712
TV		 2031 u32 l;
2032
2033 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2034 channel != OMAP_DSS_CHANNEL_LCD &&
2035 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712
TV		 2036
2037 enable_clocks(1);
8613b000 2038 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2039 enable_clocks(0);
2040
2041 return l;
2042}
2043
2044void dispc_set_trans_key(enum omap_channel ch,
2045 enum omap_dss_trans_key_type type,
2046 u32 trans_key)
2047{
80c39712
TV		 2048 enable_clocks(1);
2049 if (ch == OMAP_DSS_CHANNEL_LCD)
2050 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2051 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2052 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2053 else /* OMAP_DSS_CHANNEL_LCD2 */
2054 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2055
8613b000 2056 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2057 enable_clocks(0);
2058}
2059
2060void dispc_get_trans_key(enum omap_channel ch,
2061 enum omap_dss_trans_key_type *type,
2062 u32 *trans_key)
2063{
80c39712
TV		 2064 enable_clocks(1);
2065 if (type) {
2066 if (ch == OMAP_DSS_CHANNEL_LCD)
2067 *type = REG_GET(DISPC_CONFIG, 11, 11);
2068 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2069 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2070 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2071 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2072 else
2073 BUG();
2074 }
2075
2076 if (trans_key)
8613b000 2077 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2078 enable_clocks(0);
2079}
2080
2081void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2082{
2083 enable_clocks(1);
2084 if (ch == OMAP_DSS_CHANNEL_LCD)
2085 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2086 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2087 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2088 else /* OMAP_DSS_CHANNEL_LCD2 */
2089 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2090 enable_clocks(0);
2091}
2092void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2093{
a0acb557 2094 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2095 return;
2096
2097 enable_clocks(1);
2098 if (ch == OMAP_DSS_CHANNEL_LCD)
2099 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2100 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2101 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2102 else /* OMAP_DSS_CHANNEL_LCD2 */
2103 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2104 enable_clocks(0);
2105}
2106bool dispc_alpha_blending_enabled(enum omap_channel ch)
2107{
2108 bool enabled;
2109
a0acb557 2110 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2111 return false;
2112
2113 enable_clocks(1);
2114 if (ch == OMAP_DSS_CHANNEL_LCD)
2115 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2116 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2117 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2118 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2119 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2120 else
2121 BUG();
2122 enable_clocks(0);
2123
2124 return enabled;
80c39712
TV		 2125}
2126
2127
2128bool dispc_trans_key_enabled(enum omap_channel ch)
2129{
2130 bool enabled;
2131
2132 enable_clocks(1);
2133 if (ch == OMAP_DSS_CHANNEL_LCD)
2134 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2135 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2136 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2137 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2138 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2139 else
2140 BUG();
2141 enable_clocks(0);
2142
2143 return enabled;
2144}
2145
2146
64ba4f74 2147void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2148{
2149 int code;
2150
2151 switch (data_lines) {
2152 case 12:
2153 code = 0;
2154 break;
2155 case 16:
2156 code = 1;
2157 break;
2158 case 18:
2159 code = 2;
2160 break;
2161 case 24:
2162 code = 3;
2163 break;
2164 default:
2165 BUG();
2166 return;
2167 }
2168
2169 enable_clocks(1);
2a205f34
SS		 2170 if (channel == OMAP_DSS_CHANNEL_LCD2)
2171 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2172 else
2173 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2174 enable_clocks(0);
2175}
2176
64ba4f74
SS		 2177void dispc_set_parallel_interface_mode(enum omap_channel channel,
2178 enum omap_parallel_interface_mode mode)
80c39712
TV		 2179{
2180 u32 l;
2181 int stallmode;
2182 int gpout0 = 1;
2183 int gpout1;
2184
2185 switch (mode) {
2186 case OMAP_DSS_PARALLELMODE_BYPASS:
2187 stallmode = 0;
2188 gpout1 = 1;
2189 break;
2190
2191 case OMAP_DSS_PARALLELMODE_RFBI:
2192 stallmode = 1;
2193 gpout1 = 0;
2194 break;
2195
2196 case OMAP_DSS_PARALLELMODE_DSI:
2197 stallmode = 1;
2198 gpout1 = 1;
2199 break;
2200
2201 default:
2202 BUG();
2203 return;
2204 }
2205
2206 enable_clocks(1);
2207
2a205f34
SS		 2208 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2209 l = dispc_read_reg(DISPC_CONTROL2);
2210 l = FLD_MOD(l, stallmode, 11, 11);
2211 dispc_write_reg(DISPC_CONTROL2, l);
2212 } else {
2213 l = dispc_read_reg(DISPC_CONTROL);
2214 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2215 l = FLD_MOD(l, gpout0, 15, 15);
2216 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2217 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2218 }
80c39712
TV		 2219
2220 enable_clocks(0);
2221}
2222
2223static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2224 int vsw, int vfp, int vbp)
2225{
2226 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2227 if (hsw < 1 || hsw > 64 ||
2228 hfp < 1 || hfp > 256 ||
2229 hbp < 1 || hbp > 256 ||
2230 vsw < 1 || vsw > 64 ||
2231 vfp < 0 || vfp > 255 ||
2232 vbp < 0 || vbp > 255)
2233 return false;
2234 } else {
2235 if (hsw < 1 || hsw > 256 ||
2236 hfp < 1 || hfp > 4096 ||
2237 hbp < 1 || hbp > 4096 ||
2238 vsw < 1 || vsw > 256 ||
2239 vfp < 0 || vfp > 4095 ||
2240 vbp < 0 || vbp > 4095)
2241 return false;
2242 }
2243
2244 return true;
2245}
2246
2247bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2248{
2249 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2250 timings->hbp, timings->vsw,
2251 timings->vfp, timings->vbp);
2252}
2253
64ba4f74
SS		 2254static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2255 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2256{
2257 u32 timing_h, timing_v;
2258
2259 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2260 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2261 FLD_VAL(hbp-1, 27, 20);
2262
2263 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2264 FLD_VAL(vbp, 27, 20);
2265 } else {
2266 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2267 FLD_VAL(hbp-1, 31, 20);
2268
2269 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2270 FLD_VAL(vbp, 31, 20);
2271 }
2272
2273 enable_clocks(1);
64ba4f74
SS		 2274 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2275 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2276 enable_clocks(0);
2277}
2278
2279/* change name to mode? */
64ba4f74
SS		 2280void dispc_set_lcd_timings(enum omap_channel channel,
2281 struct omap_video_timings *timings)
80c39712
TV		 2282{
2283 unsigned xtot, ytot;
2284 unsigned long ht, vt;
2285
2286 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2287 timings->hbp, timings->vsw,
2288 timings->vfp, timings->vbp))
2289 BUG();
2290
64ba4f74
SS		 2291 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2292 timings->hbp, timings->vsw, timings->vfp,
2293 timings->vbp);
80c39712 2294
64ba4f74 2295 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2296
2297 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2298 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2299
2300 ht = (timings->pixel_clock * 1000) / xtot;
2301 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2302
2a205f34
SS		 2303 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2304 timings->y_res);
80c39712
TV		 2305 DSSDBG("pck %u\n", timings->pixel_clock);
2306 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2307 timings->hsw, timings->hfp, timings->hbp,
2308 timings->vsw, timings->vfp, timings->vbp);
2309
2310 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2311}
2312
ff1b2cde
SS		 2313static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2314 u16 pck_div)
80c39712
TV		 2315{
2316 BUG_ON(lck_div < 1);
2317 BUG_ON(pck_div < 2);
2318
2319 enable_clocks(1);
ce7fa5eb 2320 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712
TV		 2321 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2322 enable_clocks(0);
2323}
2324
2a205f34
SS		 2325static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2326 int *pck_div)
80c39712
TV		 2327{
2328 u32 l;
ce7fa5eb 2329 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2330 *lck_div = FLD_GET(l, 23, 16);
2331 *pck_div = FLD_GET(l, 7, 0);
2332}
2333
2334unsigned long dispc_fclk_rate(void)
2335{
2336 unsigned long r = 0;
2337
88134fa1 2338 if (dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK)
6af9cd14 2339 r = dss_clk_get_rate(DSS_CLK_FCK);
80c39712
TV		 2340 else
2341#ifdef CONFIG_OMAP2_DSS_DSI
1bb47835 2342 r = dsi_get_pll_hsdiv_dispc_rate();
80c39712
TV		 2343#else
2344 BUG();
2345#endif
2346 return r;
2347}
2348
ff1b2cde 2349unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712
TV		 2350{
2351 int lcd;
2352 unsigned long r;
2353 u32 l;
2354
ce7fa5eb 2355 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2356
2357 lcd = FLD_GET(l, 23, 16);
2358
2359 r = dispc_fclk_rate();
2360
2361 return r / lcd;
2362}
2363
ff1b2cde 2364unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712
TV		 2365{
2366 int lcd, pcd;
2367 unsigned long r;
2368 u32 l;
2369
ce7fa5eb 2370 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2371
2372 lcd = FLD_GET(l, 23, 16);
2373 pcd = FLD_GET(l, 7, 0);
2374
2375 r = dispc_fclk_rate();
2376
2377 return r / lcd / pcd;
2378}
2379
2380void dispc_dump_clocks(struct seq_file *s)
2381{
2382 int lcd, pcd;
067a57e4 2383 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712
TV		 2384
2385 enable_clocks(1);
2386
80c39712
TV		 2387 seq_printf(s, "- DISPC -\n");
2388
067a57e4
AT		 2389 seq_printf(s, "dispc fclk source = %s (%s)\n",
2390 dss_get_generic_clk_source_name(dispc_clk_src),
2391 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2392
2393 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34
SS		 2394
2395 seq_printf(s, "- LCD1 -\n");
2396
2397 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2398
ff1b2cde
SS		 2399 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2400 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2401 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2402 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2403 if (dss_has_feature(FEAT_MGR_LCD2)) {
2404 seq_printf(s, "- LCD2 -\n");
2405
2406 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2407
2a205f34
SS		 2408 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2409 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2410 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2411 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2412 }
80c39712
TV		 2413 enable_clocks(0);
2414}
2415
dfc0fd8d
TV		 2416#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2417void dispc_dump_irqs(struct seq_file *s)
2418{
2419 unsigned long flags;
2420 struct dispc_irq_stats stats;
2421
2422 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2423
2424 stats = dispc.irq_stats;
2425 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2426 dispc.irq_stats.last_reset = jiffies;
2427
2428 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2429
2430 seq_printf(s, "period %u ms\n",
2431 jiffies_to_msecs(jiffies - stats.last_reset));
2432
2433 seq_printf(s, "irqs %d\n", stats.irq_count);
2434#define PIS(x) \
2435 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2436
2437 PIS(FRAMEDONE);
2438 PIS(VSYNC);
2439 PIS(EVSYNC_EVEN);
2440 PIS(EVSYNC_ODD);
2441 PIS(ACBIAS_COUNT_STAT);
2442 PIS(PROG_LINE_NUM);
2443 PIS(GFX_FIFO_UNDERFLOW);
2444 PIS(GFX_END_WIN);
2445 PIS(PAL_GAMMA_MASK);
2446 PIS(OCP_ERR);
2447 PIS(VID1_FIFO_UNDERFLOW);
2448 PIS(VID1_END_WIN);
2449 PIS(VID2_FIFO_UNDERFLOW);
2450 PIS(VID2_END_WIN);
2451 PIS(SYNC_LOST);
2452 PIS(SYNC_LOST_DIGIT);
2453 PIS(WAKEUP);
2a205f34
SS		 2454 if (dss_has_feature(FEAT_MGR_LCD2)) {
2455 PIS(FRAMEDONE2);
2456 PIS(VSYNC2);
2457 PIS(ACBIAS_COUNT_STAT2);
2458 PIS(SYNC_LOST2);
2459 }
dfc0fd8d
TV		 2460#undef PIS
2461}
dfc0fd8d
TV		 2462#endif
2463
80c39712
TV		 2464void dispc_dump_regs(struct seq_file *s)
2465{
2466#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2467
6af9cd14 2468 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2469
2470 DUMPREG(DISPC_REVISION);
2471 DUMPREG(DISPC_SYSCONFIG);
2472 DUMPREG(DISPC_SYSSTATUS);
2473 DUMPREG(DISPC_IRQSTATUS);
2474 DUMPREG(DISPC_IRQENABLE);
2475 DUMPREG(DISPC_CONTROL);
2476 DUMPREG(DISPC_CONFIG);
2477 DUMPREG(DISPC_CAPABLE);
8613b000
SS		 2478 DUMPREG(DISPC_DEFAULT_COLOR(0));
2479 DUMPREG(DISPC_DEFAULT_COLOR(1));
2480 DUMPREG(DISPC_TRANS_COLOR(0));
2481 DUMPREG(DISPC_TRANS_COLOR(1));
80c39712
TV		 2482 DUMPREG(DISPC_LINE_STATUS);
2483 DUMPREG(DISPC_LINE_NUMBER);
8613b000
SS		 2484 DUMPREG(DISPC_TIMING_H(0));
2485 DUMPREG(DISPC_TIMING_V(0));
2486 DUMPREG(DISPC_POL_FREQ(0));
ce7fa5eb 2487 DUMPREG(DISPC_DIVISORo(0));
80c39712
TV		 2488 DUMPREG(DISPC_GLOBAL_ALPHA);
2489 DUMPREG(DISPC_SIZE_DIG);
8613b000 2490 DUMPREG(DISPC_SIZE_LCD(0));
2a205f34
SS		 2491 if (dss_has_feature(FEAT_MGR_LCD2)) {
2492 DUMPREG(DISPC_CONTROL2);
2493 DUMPREG(DISPC_CONFIG2);
2494 DUMPREG(DISPC_DEFAULT_COLOR(2));
2495 DUMPREG(DISPC_TRANS_COLOR(2));
2496 DUMPREG(DISPC_TIMING_H(2));
2497 DUMPREG(DISPC_TIMING_V(2));
2498 DUMPREG(DISPC_POL_FREQ(2));
ce7fa5eb 2499 DUMPREG(DISPC_DIVISORo(2));
2a205f34
SS		 2500 DUMPREG(DISPC_SIZE_LCD(2));
2501 }
80c39712
TV		 2502
2503 DUMPREG(DISPC_GFX_BA0);
2504 DUMPREG(DISPC_GFX_BA1);
2505 DUMPREG(DISPC_GFX_POSITION);
2506 DUMPREG(DISPC_GFX_SIZE);
2507 DUMPREG(DISPC_GFX_ATTRIBUTES);
2508 DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2509 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2510 DUMPREG(DISPC_GFX_ROW_INC);
2511 DUMPREG(DISPC_GFX_PIXEL_INC);
2512 DUMPREG(DISPC_GFX_WINDOW_SKIP);
2513 DUMPREG(DISPC_GFX_TABLE_BA);
2514
8613b000
SS		 2515 DUMPREG(DISPC_DATA_CYCLE1(0));
2516 DUMPREG(DISPC_DATA_CYCLE2(0));
2517 DUMPREG(DISPC_DATA_CYCLE3(0));
80c39712 2518
8613b000
SS		 2519 DUMPREG(DISPC_CPR_COEF_R(0));
2520 DUMPREG(DISPC_CPR_COEF_G(0));
2521 DUMPREG(DISPC_CPR_COEF_B(0));
2a205f34
SS		 2522 if (dss_has_feature(FEAT_MGR_LCD2)) {
2523 DUMPREG(DISPC_DATA_CYCLE1(2));
2524 DUMPREG(DISPC_DATA_CYCLE2(2));
2525 DUMPREG(DISPC_DATA_CYCLE3(2));
2526
2527 DUMPREG(DISPC_CPR_COEF_R(2));
2528 DUMPREG(DISPC_CPR_COEF_G(2));
2529 DUMPREG(DISPC_CPR_COEF_B(2));
2530 }
80c39712
TV		 2531
2532 DUMPREG(DISPC_GFX_PRELOAD);
2533
2534 DUMPREG(DISPC_VID_BA0(0));
2535 DUMPREG(DISPC_VID_BA1(0));
2536 DUMPREG(DISPC_VID_POSITION(0));
2537 DUMPREG(DISPC_VID_SIZE(0));
2538 DUMPREG(DISPC_VID_ATTRIBUTES(0));
2539 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2540 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2541 DUMPREG(DISPC_VID_ROW_INC(0));
2542 DUMPREG(DISPC_VID_PIXEL_INC(0));
2543 DUMPREG(DISPC_VID_FIR(0));
2544 DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2545 DUMPREG(DISPC_VID_ACCU0(0));
2546 DUMPREG(DISPC_VID_ACCU1(0));
2547
2548 DUMPREG(DISPC_VID_BA0(1));
2549 DUMPREG(DISPC_VID_BA1(1));
2550 DUMPREG(DISPC_VID_POSITION(1));
2551 DUMPREG(DISPC_VID_SIZE(1));
2552 DUMPREG(DISPC_VID_ATTRIBUTES(1));
2553 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2554 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2555 DUMPREG(DISPC_VID_ROW_INC(1));
2556 DUMPREG(DISPC_VID_PIXEL_INC(1));
2557 DUMPREG(DISPC_VID_FIR(1));
2558 DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2559 DUMPREG(DISPC_VID_ACCU0(1));
2560 DUMPREG(DISPC_VID_ACCU1(1));
2561
2562 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2563 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2564 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2565 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2566 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2567 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2568 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2569 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2570 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2571 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2572 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2573 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2574 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2575 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2576 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2577 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2578 DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2579 DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2580 DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2581 DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2582 DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2583 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2584 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2585 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2586 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2587 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2588 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2589 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2590 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2591
2592 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2593 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2594 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2595 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2596 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2597 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2598 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2599 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2600 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2601 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2602 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2603 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2604 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2605 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2606 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2607 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2608 DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2609 DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2610 DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2611 DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2612 DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2613 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2614 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2615 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2616 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2617 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2618 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2619 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2620 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2621
2622 DUMPREG(DISPC_VID_PRELOAD(0));
2623 DUMPREG(DISPC_VID_PRELOAD(1));
2624
6af9cd14 2625 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
80c39712
TV		 2626#undef DUMPREG
2627}
2628
ff1b2cde
SS		 2629static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2630 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2631{
2632 u32 l = 0;
2633
2634 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2635 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2636
2637 l |= FLD_VAL(onoff, 17, 17);
2638 l |= FLD_VAL(rf, 16, 16);
2639 l |= FLD_VAL(ieo, 15, 15);
2640 l |= FLD_VAL(ipc, 14, 14);
2641 l |= FLD_VAL(ihs, 13, 13);
2642 l |= FLD_VAL(ivs, 12, 12);
2643 l |= FLD_VAL(acbi, 11, 8);
2644 l |= FLD_VAL(acb, 7, 0);
2645
2646 enable_clocks(1);
ff1b2cde 2647 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2648 enable_clocks(0);
2649}
2650
ff1b2cde
SS		 2651void dispc_set_pol_freq(enum omap_channel channel,
2652 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2653{
ff1b2cde 2654 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2655 (config & OMAP_DSS_LCD_RF) != 0,
2656 (config & OMAP_DSS_LCD_IEO) != 0,
2657 (config & OMAP_DSS_LCD_IPC) != 0,
2658 (config & OMAP_DSS_LCD_IHS) != 0,
2659 (config & OMAP_DSS_LCD_IVS) != 0,
2660 acbi, acb);
2661}
2662
2663/* with fck as input clock rate, find dispc dividers that produce req_pck */
2664void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2665 struct dispc_clock_info *cinfo)
2666{
2667 u16 pcd_min = is_tft ? 2 : 3;
2668 unsigned long best_pck;
2669 u16 best_ld, cur_ld;
2670 u16 best_pd, cur_pd;
2671
2672 best_pck = 0;
2673 best_ld = 0;
2674 best_pd = 0;
2675
2676 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2677 unsigned long lck = fck / cur_ld;
2678
2679 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2680 unsigned long pck = lck / cur_pd;
2681 long old_delta = abs(best_pck - req_pck);
2682 long new_delta = abs(pck - req_pck);
2683
2684 if (best_pck == 0 || new_delta < old_delta) {
2685 best_pck = pck;
2686 best_ld = cur_ld;
2687 best_pd = cur_pd;
2688
2689 if (pck == req_pck)
2690 goto found;
2691 }
2692
2693 if (pck < req_pck)
2694 break;
2695 }
2696
2697 if (lck / pcd_min < req_pck)
2698 break;
2699 }
2700
2701found:
2702 cinfo->lck_div = best_ld;
2703 cinfo->pck_div = best_pd;
2704 cinfo->lck = fck / cinfo->lck_div;
2705 cinfo->pck = cinfo->lck / cinfo->pck_div;
2706}
2707
2708/* calculate clock rates using dividers in cinfo */
2709int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2710 struct dispc_clock_info *cinfo)
2711{
2712 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2713 return -EINVAL;
2714 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2715 return -EINVAL;
2716
2717 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2718 cinfo->pck = cinfo->lck / cinfo->pck_div;
2719
2720 return 0;
2721}
2722
ff1b2cde
SS		 2723int dispc_set_clock_div(enum omap_channel channel,
2724 struct dispc_clock_info *cinfo)
80c39712
TV		 2725{
2726 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2727 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2728
ff1b2cde 2729 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2730
2731 return 0;
2732}
2733
ff1b2cde
SS		 2734int dispc_get_clock_div(enum omap_channel channel,
2735 struct dispc_clock_info *cinfo)
80c39712
TV		 2736{
2737 unsigned long fck;
2738
2739 fck = dispc_fclk_rate();
2740
ce7fa5eb
MR		 2741 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2742 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2743
2744 cinfo->lck = fck / cinfo->lck_div;
2745 cinfo->pck = cinfo->lck / cinfo->pck_div;
2746
2747 return 0;
2748}
2749
2750/* dispc.irq_lock has to be locked by the caller */
2751static void _omap_dispc_set_irqs(void)
2752{
2753 u32 mask;
2754 u32 old_mask;
2755 int i;
2756 struct omap_dispc_isr_data *isr_data;
2757
2758 mask = dispc.irq_error_mask;
2759
2760 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2761 isr_data = &dispc.registered_isr[i];
2762
2763 if (isr_data->isr == NULL)
2764 continue;
2765
2766 mask |= isr_data->mask;
2767 }
2768
2769 enable_clocks(1);
2770
2771 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2772 /* clear the irqstatus for newly enabled irqs */
2773 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2774
2775 dispc_write_reg(DISPC_IRQENABLE, mask);
2776
2777 enable_clocks(0);
2778}
2779
2780int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2781{
2782 int i;
2783 int ret;
2784 unsigned long flags;
2785 struct omap_dispc_isr_data *isr_data;
2786
2787 if (isr == NULL)
2788 return -EINVAL;
2789
2790 spin_lock_irqsave(&dispc.irq_lock, flags);
2791
2792 /* check for duplicate entry */
2793 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2794 isr_data = &dispc.registered_isr[i];
2795 if (isr_data->isr == isr && isr_data->arg == arg &&
2796 isr_data->mask == mask) {
2797 ret = -EINVAL;
2798 goto err;
2799 }
2800 }
2801
2802 isr_data = NULL;
2803 ret = -EBUSY;
2804
2805 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2806 isr_data = &dispc.registered_isr[i];
2807
2808 if (isr_data->isr != NULL)
2809 continue;
2810
2811 isr_data->isr = isr;
2812 isr_data->arg = arg;
2813 isr_data->mask = mask;
2814 ret = 0;
2815
2816 break;
2817 }
2818
2819 _omap_dispc_set_irqs();
2820
2821 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2822
2823 return 0;
2824err:
2825 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2826
2827 return ret;
2828}
2829EXPORT_SYMBOL(omap_dispc_register_isr);
2830
2831int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2832{
2833 int i;
2834 unsigned long flags;
2835 int ret = -EINVAL;
2836 struct omap_dispc_isr_data *isr_data;
2837
2838 spin_lock_irqsave(&dispc.irq_lock, flags);
2839
2840 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2841 isr_data = &dispc.registered_isr[i];
2842 if (isr_data->isr != isr || isr_data->arg != arg ||
2843 isr_data->mask != mask)
2844 continue;
2845
2846 /* found the correct isr */
2847
2848 isr_data->isr = NULL;
2849 isr_data->arg = NULL;
2850 isr_data->mask = 0;
2851
2852 ret = 0;
2853 break;
2854 }
2855
2856 if (ret == 0)
2857 _omap_dispc_set_irqs();
2858
2859 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2860
2861 return ret;
2862}
2863EXPORT_SYMBOL(omap_dispc_unregister_isr);
2864
2865#ifdef DEBUG
2866static void print_irq_status(u32 status)
2867{
2868 if ((status & dispc.irq_error_mask) == 0)
2869 return;
2870
2871 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2872
2873#define PIS(x) \
2874 if (status & DISPC_IRQ_##x) \
2875 printk(#x " ");
2876 PIS(GFX_FIFO_UNDERFLOW);
2877 PIS(OCP_ERR);
2878 PIS(VID1_FIFO_UNDERFLOW);
2879 PIS(VID2_FIFO_UNDERFLOW);
2880 PIS(SYNC_LOST);
2881 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 2882 if (dss_has_feature(FEAT_MGR_LCD2))
2883 PIS(SYNC_LOST2);
80c39712
TV		 2884#undef PIS
2885
2886 printk("\n");
2887}
2888#endif
2889
2890/* Called from dss.c. Note that we don't touch clocks here,
2891 * but we presume they are on because we got an IRQ. However,
2892 * an irq handler may turn the clocks off, so we may not have
2893 * clock later in the function. */
affe360d 2894static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 2895{
2896 int i;
affe360d 2897 u32 irqstatus, irqenable;
80c39712
TV		 2898 u32 handledirqs = 0;
2899 u32 unhandled_errors;
2900 struct omap_dispc_isr_data *isr_data;
2901 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2902
2903 spin_lock(&dispc.irq_lock);
2904
2905 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 2906 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2907
2908 /* IRQ is not for us */
2909 if (!(irqstatus & irqenable)) {
2910 spin_unlock(&dispc.irq_lock);
2911 return IRQ_NONE;
2912 }
80c39712 2913
dfc0fd8d
TV		 2914#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2915 spin_lock(&dispc.irq_stats_lock);
2916 dispc.irq_stats.irq_count++;
2917 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2918 spin_unlock(&dispc.irq_stats_lock);
2919#endif
2920
80c39712
TV		 2921#ifdef DEBUG
2922 if (dss_debug)
2923 print_irq_status(irqstatus);
2924#endif
2925 /* Ack the interrupt. Do it here before clocks are possibly turned
2926 * off */
2927 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2928 /* flush posted write */
2929 dispc_read_reg(DISPC_IRQSTATUS);
2930
2931 /* make a copy and unlock, so that isrs can unregister
2932 * themselves */
2933 memcpy(registered_isr, dispc.registered_isr,
2934 sizeof(registered_isr));
2935
2936 spin_unlock(&dispc.irq_lock);
2937
2938 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2939 isr_data = &registered_isr[i];
2940
2941 if (!isr_data->isr)
2942 continue;
2943
2944 if (isr_data->mask & irqstatus) {
2945 isr_data->isr(isr_data->arg, irqstatus);
2946 handledirqs |= isr_data->mask;
2947 }
2948 }
2949
2950 spin_lock(&dispc.irq_lock);
2951
2952 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2953
2954 if (unhandled_errors) {
2955 dispc.error_irqs |= unhandled_errors;
2956
2957 dispc.irq_error_mask &= ~unhandled_errors;
2958 _omap_dispc_set_irqs();
2959
2960 schedule_work(&dispc.error_work);
2961 }
2962
2963 spin_unlock(&dispc.irq_lock);
affe360d 2964
2965 return IRQ_HANDLED;
80c39712
TV		 2966}
2967
2968static void dispc_error_worker(struct work_struct *work)
2969{
2970 int i;
2971 u32 errors;
2972 unsigned long flags;
2973
2974 spin_lock_irqsave(&dispc.irq_lock, flags);
2975 errors = dispc.error_irqs;
2976 dispc.error_irqs = 0;
2977 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2978
2979 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2980 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2981 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2982 struct omap_overlay *ovl;
2983 ovl = omap_dss_get_overlay(i);
2984
2985 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2986 continue;
2987
2988 if (ovl->id == 0) {
2989 dispc_enable_plane(ovl->id, 0);
2990 dispc_go(ovl->manager->id);
2991 mdelay(50);
2992 break;
2993 }
2994 }
2995 }
2996
2997 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2998 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2999 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3000 struct omap_overlay *ovl;
3001 ovl = omap_dss_get_overlay(i);
3002
3003 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3004 continue;
3005
3006 if (ovl->id == 1) {
3007 dispc_enable_plane(ovl->id, 0);
3008 dispc_go(ovl->manager->id);
3009 mdelay(50);
3010 break;
3011 }
3012 }
3013 }
3014
3015 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3016 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3017 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3018 struct omap_overlay *ovl;
3019 ovl = omap_dss_get_overlay(i);
3020
3021 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3022 continue;
3023
3024 if (ovl->id == 2) {
3025 dispc_enable_plane(ovl->id, 0);
3026 dispc_go(ovl->manager->id);
3027 mdelay(50);
3028 break;
3029 }
3030 }
3031 }
3032
3033 if (errors & DISPC_IRQ_SYNC_LOST) {
3034 struct omap_overlay_manager *manager = NULL;
3035 bool enable = false;
3036
3037 DSSERR("SYNC_LOST, disabling LCD\n");
3038
3039 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3040 struct omap_overlay_manager *mgr;
3041 mgr = omap_dss_get_overlay_manager(i);
3042
3043 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3044 manager = mgr;
3045 enable = mgr->device->state ==
3046 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3047 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3048 break;
3049 }
3050 }
3051
3052 if (manager) {
37ac60e4 3053 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3054 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3055 struct omap_overlay *ovl;
3056 ovl = omap_dss_get_overlay(i);
3057
3058 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3059 continue;
3060
3061 if (ovl->id != 0 && ovl->manager == manager)
3062 dispc_enable_plane(ovl->id, 0);
3063 }
3064
3065 dispc_go(manager->id);
3066 mdelay(50);
3067 if (enable)
37ac60e4 3068 dssdev->driver->enable(dssdev);
80c39712
TV		 3069 }
3070 }
3071
3072 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3073 struct omap_overlay_manager *manager = NULL;
3074 bool enable = false;
3075
3076 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3077
3078 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3079 struct omap_overlay_manager *mgr;
3080 mgr = omap_dss_get_overlay_manager(i);
3081
3082 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3083 manager = mgr;
3084 enable = mgr->device->state ==
3085 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3086 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3087 break;
3088 }
3089 }
3090
3091 if (manager) {
37ac60e4 3092 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3093 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3094 struct omap_overlay *ovl;
3095 ovl = omap_dss_get_overlay(i);
3096
3097 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3098 continue;
3099
3100 if (ovl->id != 0 && ovl->manager == manager)
3101 dispc_enable_plane(ovl->id, 0);
3102 }
3103
3104 dispc_go(manager->id);
3105 mdelay(50);
3106 if (enable)
37ac60e4 3107 dssdev->driver->enable(dssdev);
80c39712
TV		 3108 }
3109 }
3110
2a205f34
SS		 3111 if (errors & DISPC_IRQ_SYNC_LOST2) {
3112 struct omap_overlay_manager *manager = NULL;
3113 bool enable = false;
3114
3115 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3116
3117 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3118 struct omap_overlay_manager *mgr;
3119 mgr = omap_dss_get_overlay_manager(i);
3120
3121 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3122 manager = mgr;
3123 enable = mgr->device->state ==
3124 OMAP_DSS_DISPLAY_ACTIVE;
3125 mgr->device->driver->disable(mgr->device);
3126 break;
3127 }
3128 }
3129
3130 if (manager) {
3131 struct omap_dss_device *dssdev = manager->device;
3132 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3133 struct omap_overlay *ovl;
3134 ovl = omap_dss_get_overlay(i);
3135
3136 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3137 continue;
3138
3139 if (ovl->id != 0 && ovl->manager == manager)
3140 dispc_enable_plane(ovl->id, 0);
3141 }
3142
3143 dispc_go(manager->id);
3144 mdelay(50);
3145 if (enable)
3146 dssdev->driver->enable(dssdev);
3147 }
3148 }
3149
80c39712
TV		 3150 if (errors & DISPC_IRQ_OCP_ERR) {
3151 DSSERR("OCP_ERR\n");
3152 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3153 struct omap_overlay_manager *mgr;
3154 mgr = omap_dss_get_overlay_manager(i);
3155
3156 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3157 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3158 }
3159 }
3160
3161 spin_lock_irqsave(&dispc.irq_lock, flags);
3162 dispc.irq_error_mask |= errors;
3163 _omap_dispc_set_irqs();
3164 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3165}
3166
3167int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3168{
3169 void dispc_irq_wait_handler(void *data, u32 mask)
3170 {
3171 complete((struct completion *)data);
3172 }
3173
3174 int r;
3175 DECLARE_COMPLETION_ONSTACK(completion);
3176
3177 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3178 irqmask);
3179
3180 if (r)
3181 return r;
3182
3183 timeout = wait_for_completion_timeout(&completion, timeout);
3184
3185 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3186
3187 if (timeout == 0)
3188 return -ETIMEDOUT;
3189
3190 if (timeout == -ERESTARTSYS)
3191 return -ERESTARTSYS;
3192
3193 return 0;
3194}
3195
3196int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3197 unsigned long timeout)
3198{
3199 void dispc_irq_wait_handler(void *data, u32 mask)
3200 {
3201 complete((struct completion *)data);
3202 }
3203
3204 int r;
3205 DECLARE_COMPLETION_ONSTACK(completion);
3206
3207 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3208 irqmask);
3209
3210 if (r)
3211 return r;
3212
3213 timeout = wait_for_completion_interruptible_timeout(&completion,
3214 timeout);
3215
3216 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3217
3218 if (timeout == 0)
3219 return -ETIMEDOUT;
3220
3221 if (timeout == -ERESTARTSYS)
3222 return -ERESTARTSYS;
3223
3224 return 0;
3225}
3226
3227#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3228void dispc_fake_vsync_irq(void)
3229{
3230 u32 irqstatus = DISPC_IRQ_VSYNC;
3231 int i;
3232
ab83b14c 3233 WARN_ON(!in_interrupt());
80c39712
TV		 3234
3235 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3236 struct omap_dispc_isr_data *isr_data;
3237 isr_data = &dispc.registered_isr[i];
3238
3239 if (!isr_data->isr)
3240 continue;
3241
3242 if (isr_data->mask & irqstatus)
3243 isr_data->isr(isr_data->arg, irqstatus);
3244 }
80c39712
TV		 3245}
3246#endif
3247
3248static void _omap_dispc_initialize_irq(void)
3249{
3250 unsigned long flags;
3251
3252 spin_lock_irqsave(&dispc.irq_lock, flags);
3253
3254 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3255
3256 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3257 if (dss_has_feature(FEAT_MGR_LCD2))
3258 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3259
3260 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3261 * so clear it */
3262 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3263
3264 _omap_dispc_set_irqs();
3265
3266 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3267}
3268
3269void dispc_enable_sidle(void)
3270{
3271 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3272}
3273
3274void dispc_disable_sidle(void)
3275{
3276 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3277}
3278
3279static void _omap_dispc_initial_config(void)
3280{
3281 u32 l;
3282
3283 l = dispc_read_reg(DISPC_SYSCONFIG);
3284 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3285 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3286 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3287 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3288 dispc_write_reg(DISPC_SYSCONFIG, l);
3289
3290 /* FUNCGATED */
6ced40bf
AT		 3291 if (dss_has_feature(FEAT_FUNCGATED))
3292 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3293
3294 /* L3 firewall setting: enable access to OCM RAM */
3295 /* XXX this should be somewhere in plat-omap */
3296 if (cpu_is_omap24xx())
3297 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3298
3299 _dispc_setup_color_conv_coef();
3300
3301 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3302
3303 dispc_read_plane_fifo_sizes();
3304}
3305
80c39712
TV		 3306int dispc_enable_plane(enum omap_plane plane, bool enable)
3307{
3308 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3309
3310 enable_clocks(1);
3311 _dispc_enable_plane(plane, enable);
3312 enable_clocks(0);
3313
3314 return 0;
3315}
3316
3317int dispc_setup_plane(enum omap_plane plane,
3318 u32 paddr, u16 screen_width,
3319 u16 pos_x, u16 pos_y,
3320 u16 width, u16 height,
3321 u16 out_width, u16 out_height,
3322 enum omap_color_mode color_mode,
3323 bool ilace,
3324 enum omap_dss_rotation_type rotation_type,
fd28a390 3325 u8 rotation, bool mirror, u8 global_alpha,
18faa1b6 3326 u8 pre_mult_alpha, enum omap_channel channel)
80c39712
TV		 3327{
3328 int r = 0;
3329
3330 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
18faa1b6 3331 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
80c39712
TV		 3332 plane, paddr, screen_width, pos_x, pos_y,
3333 width, height,
3334 out_width, out_height,
3335 ilace, color_mode,
18faa1b6 3336 rotation, mirror, channel);
80c39712
TV		 3337
3338 enable_clocks(1);
3339
3340 r = _dispc_setup_plane(plane,
3341 paddr, screen_width,
3342 pos_x, pos_y,
3343 width, height,
3344 out_width, out_height,
3345 color_mode, ilace,
3346 rotation_type,
3347 rotation, mirror,
fd28a390 3348 global_alpha,
18faa1b6 3349 pre_mult_alpha, channel);
80c39712
TV		 3350
3351 enable_clocks(0);
3352
3353 return r;
3354}
060b6d9c
SG		 3355
3356/* DISPC HW IP initialisation */
3357static int omap_dispchw_probe(struct platform_device *pdev)
3358{
3359 u32 rev;
affe360d 3360 int r = 0;
ea9da36a
SG		 3361 struct resource *dispc_mem;
3362
060b6d9c
SG		 3363 dispc.pdev = pdev;
3364
3365 spin_lock_init(&dispc.irq_lock);
3366
3367#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3368 spin_lock_init(&dispc.irq_stats_lock);
3369 dispc.irq_stats.last_reset = jiffies;
3370#endif
3371
3372 INIT_WORK(&dispc.error_work, dispc_error_worker);
3373
ea9da36a
SG		 3374 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3375 if (!dispc_mem) {
3376 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3377 r = -EINVAL;
3378 goto fail0;
ea9da36a
SG		 3379 }
3380 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3381 if (!dispc.base) {
3382 DSSERR("can't ioremap DISPC\n");
affe360d 3383 r = -ENOMEM;
3384 goto fail0;
3385 }
3386 dispc.irq = platform_get_irq(dispc.pdev, 0);
3387 if (dispc.irq < 0) {
3388 DSSERR("platform_get_irq failed\n");
3389 r = -ENODEV;
3390 goto fail1;
3391 }
3392
3393 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3394 "OMAP DISPC", dispc.pdev);
3395 if (r < 0) {
3396 DSSERR("request_irq failed\n");
3397 goto fail1;
060b6d9c
SG		 3398 }
3399
3400 enable_clocks(1);
3401
3402 _omap_dispc_initial_config();
3403
3404 _omap_dispc_initialize_irq();
3405
3406 dispc_save_context();
3407
3408 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3409 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3410 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3411
3412 enable_clocks(0);
3413
3414 return 0;
affe360d 3415fail1:
3416 iounmap(dispc.base);
3417fail0:
3418 return r;
060b6d9c
SG		 3419}
3420
3421static int omap_dispchw_remove(struct platform_device *pdev)
3422{
affe360d 3423 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3424 iounmap(dispc.base);
3425 return 0;
3426}
3427
3428static struct platform_driver omap_dispchw_driver = {
3429 .probe = omap_dispchw_probe,
3430 .remove = omap_dispchw_remove,
3431 .driver = {
3432 .name = "omapdss_dispc",
3433 .owner = THIS_MODULE,
3434 },
3435};
3436
3437int dispc_init_platform_driver(void)
3438{
3439 return platform_driver_register(&omap_dispchw_driver);
3440}
3441
3442void dispc_uninit_platform_driver(void)
3443{
3444 return platform_driver_unregister(&omap_dispchw_driver);
3445}
Linux kernel - Deliverables
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