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OMAPDSS: DISPC: Create helper function dispc_mgr_is_lcd()
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
80c39712
TV		 38
39#include <plat/sram.h>
40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
66be8f6c
GI		 66struct dispc_h_coef {
67 s8 hc4;
68 s8 hc3;
69 u8 hc2;
70 s8 hc1;
71 s8 hc0;
72};
73
74struct dispc_v_coef {
75 s8 vc22;
76 s8 vc2;
77 u8 vc1;
78 s8 vc0;
79 s8 vc00;
80};
81
5ed8cf5b
TV		 82enum omap_burst_size {
83 BURST_SIZE_X2 = 0,
84 BURST_SIZE_X4 = 1,
85 BURST_SIZE_X8 = 2,
86};
87
80c39712
TV		 88#define REG_GET(idx, start, end) \
89 FLD_GET(dispc_read_reg(idx), start, end)
90
91#define REG_FLD_MOD(idx, val, start, end) \
92 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
93
dfc0fd8d
TV		 94struct dispc_irq_stats {
95 unsigned long last_reset;
96 unsigned irq_count;
97 unsigned irqs[32];
98};
99
80c39712 100static struct {
060b6d9c 101 struct platform_device *pdev;
80c39712 102 void __iomem *base;
4fbafaf3
TV		 103
104 int ctx_loss_cnt;
105
affe360d 106 int irq;
4fbafaf3 107 struct clk *dss_clk;
80c39712 108
e13a138b 109 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 110
111 spinlock_t irq_lock;
112 u32 irq_error_mask;
113 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
114 u32 error_irqs;
115 struct work_struct error_work;
116
49ea86f3 117 bool ctx_valid;
80c39712 118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 119
120#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
121 spinlock_t irq_stats_lock;
122 struct dispc_irq_stats irq_stats;
123#endif
80c39712
TV		 124} dispc;
125
0d66cbb5
AJ		 126enum omap_color_component {
127 /* used for all color formats for OMAP3 and earlier
128 * and for RGB and Y color component on OMAP4
129 */
130 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
131 /* used for UV component for
132 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
133 * color formats on OMAP4
134 */
135 DISPC_COLOR_COMPONENT_UV = 1 << 1,
136};
137
80c39712
TV		 138static void _omap_dispc_set_irqs(void);
139
55978cc2 140static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 141{
55978cc2 142 __raw_writel(val, dispc.base + idx);
80c39712
TV		 143}
144
55978cc2 145static inline u32 dispc_read_reg(const u16 idx)
80c39712 146{
55978cc2 147 return __raw_readl(dispc.base + idx);
80c39712
TV		 148}
149
49ea86f3
TV		 150static int dispc_get_ctx_loss_count(void)
151{
152 struct device *dev = &dispc.pdev->dev;
153 struct omap_display_platform_data *pdata = dev->platform_data;
154 struct omap_dss_board_info *board_data = pdata->board_data;
155 int cnt;
156
157 if (!board_data->get_context_loss_count)
158 return -ENOENT;
159
160 cnt = board_data->get_context_loss_count(dev);
161
162 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
163
164 return cnt;
165}
166
80c39712 167#define SR(reg) \
55978cc2 168 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 169#define RR(reg) \
55978cc2 170 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 171
4fbafaf3 172static void dispc_save_context(void)
80c39712 173{
c6104b8e 174 int i, j;
80c39712 175
4fbafaf3
TV		 176 DSSDBG("dispc_save_context\n");
177
80c39712
TV		 178 SR(IRQENABLE);
179 SR(CONTROL);
180 SR(CONFIG);
80c39712 181 SR(LINE_NUMBER);
332e9d70
TV		 182 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
183 SR(GLOBAL_ALPHA);
2a205f34
SS		 184 if (dss_has_feature(FEAT_MGR_LCD2)) {
185 SR(CONTROL2);
2a205f34
SS		 186 SR(CONFIG2);
187 }
80c39712 188
c6104b8e
AT		 189 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
190 SR(DEFAULT_COLOR(i));
191 SR(TRANS_COLOR(i));
192 SR(SIZE_MGR(i));
193 if (i == OMAP_DSS_CHANNEL_DIGIT)
194 continue;
195 SR(TIMING_H(i));
196 SR(TIMING_V(i));
197 SR(POL_FREQ(i));
198 SR(DIVISORo(i));
199
200 SR(DATA_CYCLE1(i));
201 SR(DATA_CYCLE2(i));
202 SR(DATA_CYCLE3(i));
203
332e9d70 204 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 205 SR(CPR_COEF_R(i));
206 SR(CPR_COEF_G(i));
207 SR(CPR_COEF_B(i));
332e9d70 208 }
2a205f34 209 }
80c39712 210
c6104b8e
AT		 211 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
212 SR(OVL_BA0(i));
213 SR(OVL_BA1(i));
214 SR(OVL_POSITION(i));
215 SR(OVL_SIZE(i));
216 SR(OVL_ATTRIBUTES(i));
217 SR(OVL_FIFO_THRESHOLD(i));
218 SR(OVL_ROW_INC(i));
219 SR(OVL_PIXEL_INC(i));
220 if (dss_has_feature(FEAT_PRELOAD))
221 SR(OVL_PRELOAD(i));
222 if (i == OMAP_DSS_GFX) {
223 SR(OVL_WINDOW_SKIP(i));
224 SR(OVL_TABLE_BA(i));
225 continue;
226 }
227 SR(OVL_FIR(i));
228 SR(OVL_PICTURE_SIZE(i));
229 SR(OVL_ACCU0(i));
230 SR(OVL_ACCU1(i));
9b372c2d 231
c6104b8e
AT		 232 for (j = 0; j < 8; j++)
233 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 234
c6104b8e
AT		 235 for (j = 0; j < 8; j++)
236 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 237
c6104b8e
AT		 238 for (j = 0; j < 5; j++)
239 SR(OVL_CONV_COEF(i, j));
ab5ca071 240
c6104b8e
AT		 241 if (dss_has_feature(FEAT_FIR_COEF_V)) {
242 for (j = 0; j < 8; j++)
243 SR(OVL_FIR_COEF_V(i, j));
244 }
9b372c2d 245
c6104b8e
AT		 246 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
247 SR(OVL_BA0_UV(i));
248 SR(OVL_BA1_UV(i));
249 SR(OVL_FIR2(i));
250 SR(OVL_ACCU2_0(i));
251 SR(OVL_ACCU2_1(i));
ab5ca071 252
c6104b8e
AT		 253 for (j = 0; j < 8; j++)
254 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 255
c6104b8e
AT		 256 for (j = 0; j < 8; j++)
257 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 258
c6104b8e
AT		 259 for (j = 0; j < 8; j++)
260 SR(OVL_FIR_COEF_V2(i, j));
261 }
262 if (dss_has_feature(FEAT_ATTR2))
263 SR(OVL_ATTRIBUTES2(i));
ab5ca071 264 }
0cf35df3
MR		 265
266 if (dss_has_feature(FEAT_CORE_CLK_DIV))
267 SR(DIVISOR);
49ea86f3
TV		 268
269 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
270 dispc.ctx_valid = true;
271
272 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 273}
274
4fbafaf3 275static void dispc_restore_context(void)
80c39712 276{
c6104b8e 277 int i, j, ctx;
4fbafaf3
TV		 278
279 DSSDBG("dispc_restore_context\n");
280
49ea86f3
TV		 281 if (!dispc.ctx_valid)
282 return;
283
284 ctx = dispc_get_ctx_loss_count();
285
286 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
287 return;
288
289 DSSDBG("ctx_loss_count: saved %d, current %d\n",
290 dispc.ctx_loss_cnt, ctx);
291
75c7d59d 292 /*RR(IRQENABLE);*/
80c39712
TV		 293 /*RR(CONTROL);*/
294 RR(CONFIG);
80c39712 295 RR(LINE_NUMBER);
332e9d70
TV		 296 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
297 RR(GLOBAL_ALPHA);
c6104b8e 298 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 299 RR(CONFIG2);
80c39712 300
c6104b8e
AT		 301 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
302 RR(DEFAULT_COLOR(i));
303 RR(TRANS_COLOR(i));
304 RR(SIZE_MGR(i));
305 if (i == OMAP_DSS_CHANNEL_DIGIT)
306 continue;
307 RR(TIMING_H(i));
308 RR(TIMING_V(i));
309 RR(POL_FREQ(i));
310 RR(DIVISORo(i));
311
312 RR(DATA_CYCLE1(i));
313 RR(DATA_CYCLE2(i));
314 RR(DATA_CYCLE3(i));
2a205f34 315
332e9d70 316 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 317 RR(CPR_COEF_R(i));
318 RR(CPR_COEF_G(i));
319 RR(CPR_COEF_B(i));
332e9d70 320 }
2a205f34 321 }
80c39712 322
c6104b8e
AT		 323 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
324 RR(OVL_BA0(i));
325 RR(OVL_BA1(i));
326 RR(OVL_POSITION(i));
327 RR(OVL_SIZE(i));
328 RR(OVL_ATTRIBUTES(i));
329 RR(OVL_FIFO_THRESHOLD(i));
330 RR(OVL_ROW_INC(i));
331 RR(OVL_PIXEL_INC(i));
332 if (dss_has_feature(FEAT_PRELOAD))
333 RR(OVL_PRELOAD(i));
334 if (i == OMAP_DSS_GFX) {
335 RR(OVL_WINDOW_SKIP(i));
336 RR(OVL_TABLE_BA(i));
337 continue;
338 }
339 RR(OVL_FIR(i));
340 RR(OVL_PICTURE_SIZE(i));
341 RR(OVL_ACCU0(i));
342 RR(OVL_ACCU1(i));
9b372c2d 343
c6104b8e
AT		 344 for (j = 0; j < 8; j++)
345 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 346
c6104b8e
AT		 347 for (j = 0; j < 8; j++)
348 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 349
c6104b8e
AT		 350 for (j = 0; j < 5; j++)
351 RR(OVL_CONV_COEF(i, j));
ab5ca071 352
c6104b8e
AT		 353 if (dss_has_feature(FEAT_FIR_COEF_V)) {
354 for (j = 0; j < 8; j++)
355 RR(OVL_FIR_COEF_V(i, j));
356 }
9b372c2d 357
c6104b8e
AT		 358 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
359 RR(OVL_BA0_UV(i));
360 RR(OVL_BA1_UV(i));
361 RR(OVL_FIR2(i));
362 RR(OVL_ACCU2_0(i));
363 RR(OVL_ACCU2_1(i));
ab5ca071 364
c6104b8e
AT		 365 for (j = 0; j < 8; j++)
366 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 367
c6104b8e
AT		 368 for (j = 0; j < 8; j++)
369 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 370
c6104b8e
AT		 371 for (j = 0; j < 8; j++)
372 RR(OVL_FIR_COEF_V2(i, j));
373 }
374 if (dss_has_feature(FEAT_ATTR2))
375 RR(OVL_ATTRIBUTES2(i));
ab5ca071 376 }
80c39712 377
0cf35df3
MR		 378 if (dss_has_feature(FEAT_CORE_CLK_DIV))
379 RR(DIVISOR);
380
80c39712
TV		 381 /* enable last, because LCD & DIGIT enable are here */
382 RR(CONTROL);
2a205f34
SS		 383 if (dss_has_feature(FEAT_MGR_LCD2))
384 RR(CONTROL2);
75c7d59d
VS		 385 /* clear spurious SYNC_LOST_DIGIT interrupts */
386 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
387
388 /*
389 * enable last so IRQs won't trigger before
390 * the context is fully restored
391 */
392 RR(IRQENABLE);
49ea86f3
TV		 393
394 DSSDBG("context restored\n");
80c39712
TV		 395}
396
397#undef SR
398#undef RR
399
4fbafaf3
TV		 400int dispc_runtime_get(void)
401{
402 int r;
403
404 DSSDBG("dispc_runtime_get\n");
405
406 r = pm_runtime_get_sync(&dispc.pdev->dev);
407 WARN_ON(r < 0);
408 return r < 0 ? r : 0;
409}
410
411void dispc_runtime_put(void)
412{
413 int r;
414
415 DSSDBG("dispc_runtime_put\n");
416
417 r = pm_runtime_put(&dispc.pdev->dev);
418 WARN_ON(r < 0);
80c39712
TV		 419}
420
dac57a05
AT		 421static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
422{
423 if (channel == OMAP_DSS_CHANNEL_LCD ||
424 channel == OMAP_DSS_CHANNEL_LCD2)
425 return true;
426 else
427 return false;
428}
4fbafaf3 429
26d9dd0d 430bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 431{
432 int bit;
433
dac57a05 434 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 435 bit = 5; /* GOLCD */
436 else
437 bit = 6; /* GODIGIT */
438
2a205f34
SS		 439 if (channel == OMAP_DSS_CHANNEL_LCD2)
440 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
441 else
442 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 443}
444
26d9dd0d 445void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 446{
447 int bit;
2a205f34 448 bool enable_bit, go_bit;
80c39712 449
dac57a05 450 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 451 bit = 0; /* LCDENABLE */
452 else
453 bit = 1; /* DIGITALENABLE */
454
455 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 456 if (channel == OMAP_DSS_CHANNEL_LCD2)
457 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
458 else
459 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
460
461 if (!enable_bit)
e6d80f95 462 return;
80c39712 463
dac57a05 464 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 465 bit = 5; /* GOLCD */
466 else
467 bit = 6; /* GODIGIT */
468
2a205f34
SS		 469 if (channel == OMAP_DSS_CHANNEL_LCD2)
470 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
471 else
472 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
473
474 if (go_bit) {
80c39712 475 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 476 return;
80c39712
TV		 477 }
478
2a205f34
SS		 479 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
480 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 481
2a205f34
SS		 482 if (channel == OMAP_DSS_CHANNEL_LCD2)
483 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
484 else
485 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 486}
487
f0e5caab 488static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 489{
9b372c2d 490 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 491}
492
f0e5caab 493static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 494{
9b372c2d 495 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 496}
497
f0e5caab 498static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 499{
9b372c2d 500 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 501}
502
f0e5caab 503static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 504{
505 BUG_ON(plane == OMAP_DSS_GFX);
506
507 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
508}
509
f0e5caab
TV		 510static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
511 u32 value)
ab5ca071
AJ		 512{
513 BUG_ON(plane == OMAP_DSS_GFX);
514
515 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
516}
517
f0e5caab 518static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 519{
520 BUG_ON(plane == OMAP_DSS_GFX);
521
522 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
523}
524
f0e5caab 525static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
0d66cbb5
AJ		 526 int vscaleup, int five_taps,
527 enum omap_color_component color_comp)
80c39712
TV		 528{
529 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 530 static const struct dispc_h_coef coef_hup[8] = {
531 { 0, 0, 128, 0, 0 },
532 { -1, 13, 124, -8, 0 },
533 { -2, 30, 112, -11, -1 },
534 { -5, 51, 95, -11, -2 },
535 { 0, -9, 73, 73, -9 },
536 { -2, -11, 95, 51, -5 },
537 { -1, -11, 112, 30, -2 },
538 { 0, -8, 124, 13, -1 },
80c39712
TV		 539 };
540
66be8f6c
GI		 541 /* Coefficients for vertical up-sampling */
542 static const struct dispc_v_coef coef_vup_3tap[8] = {
543 { 0, 0, 128, 0, 0 },
544 { 0, 3, 123, 2, 0 },
545 { 0, 12, 111, 5, 0 },
546 { 0, 32, 89, 7, 0 },
547 { 0, 0, 64, 64, 0 },
548 { 0, 7, 89, 32, 0 },
549 { 0, 5, 111, 12, 0 },
550 { 0, 2, 123, 3, 0 },
80c39712
TV		 551 };
552
66be8f6c
GI		 553 static const struct dispc_v_coef coef_vup_5tap[8] = {
554 { 0, 0, 128, 0, 0 },
555 { -1, 13, 124, -8, 0 },
556 { -2, 30, 112, -11, -1 },
557 { -5, 51, 95, -11, -2 },
558 { 0, -9, 73, 73, -9 },
559 { -2, -11, 95, 51, -5 },
560 { -1, -11, 112, 30, -2 },
561 { 0, -8, 124, 13, -1 },
80c39712
TV		 562 };
563
66be8f6c
GI		 564 /* Coefficients for horizontal down-sampling */
565 static const struct dispc_h_coef coef_hdown[8] = {
566 { 0, 36, 56, 36, 0 },
567 { 4, 40, 55, 31, -2 },
568 { 8, 44, 54, 27, -5 },
569 { 12, 48, 53, 22, -7 },
570 { -9, 17, 52, 51, 17 },
571 { -7, 22, 53, 48, 12 },
572 { -5, 27, 54, 44, 8 },
573 { -2, 31, 55, 40, 4 },
80c39712
TV		 574 };
575
66be8f6c
GI		 576 /* Coefficients for vertical down-sampling */
577 static const struct dispc_v_coef coef_vdown_3tap[8] = {
578 { 0, 36, 56, 36, 0 },
579 { 0, 40, 57, 31, 0 },
580 { 0, 45, 56, 27, 0 },
581 { 0, 50, 55, 23, 0 },
582 { 0, 18, 55, 55, 0 },
583 { 0, 23, 55, 50, 0 },
584 { 0, 27, 56, 45, 0 },
585 { 0, 31, 57, 40, 0 },
80c39712
TV		 586 };
587
66be8f6c
GI		 588 static const struct dispc_v_coef coef_vdown_5tap[8] = {
589 { 0, 36, 56, 36, 0 },
590 { 4, 40, 55, 31, -2 },
591 { 8, 44, 54, 27, -5 },
592 { 12, 48, 53, 22, -7 },
593 { -9, 17, 52, 51, 17 },
594 { -7, 22, 53, 48, 12 },
595 { -5, 27, 54, 44, 8 },
596 { -2, 31, 55, 40, 4 },
80c39712
TV		 597 };
598
66be8f6c
GI		 599 const struct dispc_h_coef *h_coef;
600 const struct dispc_v_coef *v_coef;
80c39712
TV		 601 int i;
602
603 if (hscaleup)
604 h_coef = coef_hup;
605 else
606 h_coef = coef_hdown;
607
66be8f6c
GI		 608 if (vscaleup)
609 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
610 else
611 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 612
613 for (i = 0; i < 8; i++) {
614 u32 h, hv;
615
66be8f6c
GI		 616 h = FLD_VAL(h_coef[i].hc0, 7, 0)
617 | FLD_VAL(h_coef[i].hc1, 15, 8)
618 | FLD_VAL(h_coef[i].hc2, 23, 16)
619 | FLD_VAL(h_coef[i].hc3, 31, 24);
620 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
621 | FLD_VAL(v_coef[i].vc0, 15, 8)
622 | FLD_VAL(v_coef[i].vc1, 23, 16)
623 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712 624
0d66cbb5 625 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 626 dispc_ovl_write_firh_reg(plane, i, h);
627 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 628 } else {
f0e5caab
TV		 629 dispc_ovl_write_firh2_reg(plane, i, h);
630 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 631 }
632
80c39712
TV		 633 }
634
66be8f6c
GI		 635 if (five_taps) {
636 for (i = 0; i < 8; i++) {
637 u32 v;
638 v = FLD_VAL(v_coef[i].vc00, 7, 0)
639 | FLD_VAL(v_coef[i].vc22, 15, 8);
0d66cbb5 640 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 641 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 642 else
f0e5caab 643 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 644 }
80c39712
TV		 645 }
646}
647
648static void _dispc_setup_color_conv_coef(void)
649{
ac01c29e 650 int i;
80c39712
TV		 651 const struct color_conv_coef {
652 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
653 int full_range;
654 } ctbl_bt601_5 = {
655 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
656 };
657
658 const struct color_conv_coef *ct;
659
660#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
661
662 ct = &ctbl_bt601_5;
663
ac01c29e
AT		 664 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
665 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
666 CVAL(ct->rcr, ct->ry));
667 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
668 CVAL(ct->gy, ct->rcb));
669 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
670 CVAL(ct->gcb, ct->gcr));
671 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
672 CVAL(ct->bcr, ct->by));
673 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
674 CVAL(0, ct->bcb));
675
676 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
677 11, 11);
678 }
80c39712
TV		 679
680#undef CVAL
80c39712
TV		 681}
682
683
f0e5caab 684static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 685{
9b372c2d 686 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 687}
688
f0e5caab 689static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 690{
9b372c2d 691 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 692}
693
f0e5caab 694static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 695{
696 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
697}
698
f0e5caab 699static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 700{
701 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
702}
703
f0e5caab 704static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 705{
80c39712 706 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 707
708 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 709}
710
f0e5caab 711static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 712{
80c39712 713 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 714
715 if (plane == OMAP_DSS_GFX)
716 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
717 else
718 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 719}
720
f0e5caab 721static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 722{
723 u32 val;
80c39712
TV		 724
725 BUG_ON(plane == OMAP_DSS_GFX);
726
727 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 728
729 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 730}
731
f0e5caab 732static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 733{
f6dc8150 734 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 735
f6dc8150 736 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 737 return;
738
9b372c2d 739 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 740}
741
f0e5caab 742static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 743{
fe3cc9d6
TV		 744 static const unsigned shifts[] = { 0, 8, 16, };
745 int shift;
f6dc8150 746 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 747
f6dc8150 748 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 749 return;
a0acb557 750
fe3cc9d6
TV		 751 shift = shifts[plane];
752 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 753}
754
f0e5caab 755static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 756{
9b372c2d 757 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 758}
759
f0e5caab 760static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 761{
9b372c2d 762 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 763}
764
f0e5caab 765static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 766 enum omap_color_mode color_mode)
767{
768 u32 m = 0;
f20e4220
AJ		 769 if (plane != OMAP_DSS_GFX) {
770 switch (color_mode) {
771 case OMAP_DSS_COLOR_NV12:
772 m = 0x0; break;
773 case OMAP_DSS_COLOR_RGB12U:
774 m = 0x1; break;
775 case OMAP_DSS_COLOR_RGBA16:
776 m = 0x2; break;
777 case OMAP_DSS_COLOR_RGBX16:
778 m = 0x4; break;
779 case OMAP_DSS_COLOR_ARGB16:
780 m = 0x5; break;
781 case OMAP_DSS_COLOR_RGB16:
782 m = 0x6; break;
783 case OMAP_DSS_COLOR_ARGB16_1555:
784 m = 0x7; break;
785 case OMAP_DSS_COLOR_RGB24U:
786 m = 0x8; break;
787 case OMAP_DSS_COLOR_RGB24P:
788 m = 0x9; break;
789 case OMAP_DSS_COLOR_YUV2:
790 m = 0xa; break;
791 case OMAP_DSS_COLOR_UYVY:
792 m = 0xb; break;
793 case OMAP_DSS_COLOR_ARGB32:
794 m = 0xc; break;
795 case OMAP_DSS_COLOR_RGBA32:
796 m = 0xd; break;
797 case OMAP_DSS_COLOR_RGBX32:
798 m = 0xe; break;
799 case OMAP_DSS_COLOR_XRGB16_1555:
800 m = 0xf; break;
801 default:
802 BUG(); break;
803 }
804 } else {
805 switch (color_mode) {
806 case OMAP_DSS_COLOR_CLUT1:
807 m = 0x0; break;
808 case OMAP_DSS_COLOR_CLUT2:
809 m = 0x1; break;
810 case OMAP_DSS_COLOR_CLUT4:
811 m = 0x2; break;
812 case OMAP_DSS_COLOR_CLUT8:
813 m = 0x3; break;
814 case OMAP_DSS_COLOR_RGB12U:
815 m = 0x4; break;
816 case OMAP_DSS_COLOR_ARGB16:
817 m = 0x5; break;
818 case OMAP_DSS_COLOR_RGB16:
819 m = 0x6; break;
820 case OMAP_DSS_COLOR_ARGB16_1555:
821 m = 0x7; break;
822 case OMAP_DSS_COLOR_RGB24U:
823 m = 0x8; break;
824 case OMAP_DSS_COLOR_RGB24P:
825 m = 0x9; break;
826 case OMAP_DSS_COLOR_YUV2:
827 m = 0xa; break;
828 case OMAP_DSS_COLOR_UYVY:
829 m = 0xb; break;
830 case OMAP_DSS_COLOR_ARGB32:
831 m = 0xc; break;
832 case OMAP_DSS_COLOR_RGBA32:
833 m = 0xd; break;
834 case OMAP_DSS_COLOR_RGBX32:
835 m = 0xe; break;
836 case OMAP_DSS_COLOR_XRGB16_1555:
837 m = 0xf; break;
838 default:
839 BUG(); break;
840 }
80c39712
TV		 841 }
842
9b372c2d 843 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 844}
845
f0e5caab 846static void dispc_ovl_set_channel_out(enum omap_plane plane,
80c39712
TV		 847 enum omap_channel channel)
848{
849 int shift;
850 u32 val;
2a205f34 851 int chan = 0, chan2 = 0;
80c39712
TV		 852
853 switch (plane) {
854 case OMAP_DSS_GFX:
855 shift = 8;
856 break;
857 case OMAP_DSS_VIDEO1:
858 case OMAP_DSS_VIDEO2:
859 shift = 16;
860 break;
861 default:
862 BUG();
863 return;
864 }
865
9b372c2d 866 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 867 if (dss_has_feature(FEAT_MGR_LCD2)) {
868 switch (channel) {
869 case OMAP_DSS_CHANNEL_LCD:
870 chan = 0;
871 chan2 = 0;
872 break;
873 case OMAP_DSS_CHANNEL_DIGIT:
874 chan = 1;
875 chan2 = 0;
876 break;
877 case OMAP_DSS_CHANNEL_LCD2:
878 chan = 0;
879 chan2 = 1;
880 break;
881 default:
882 BUG();
883 }
884
885 val = FLD_MOD(val, chan, shift, shift);
886 val = FLD_MOD(val, chan2, 31, 30);
887 } else {
888 val = FLD_MOD(val, channel, shift, shift);
889 }
9b372c2d 890 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 891}
892
f0e5caab 893static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 894 enum omap_burst_size burst_size)
895{
fe3cc9d6 896 static const unsigned shifts[] = { 6, 14, 14, };
80c39712 897 int shift;
80c39712 898
fe3cc9d6 899 shift = shifts[plane];
5ed8cf5b 900 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 901}
902
5ed8cf5b
TV		 903static void dispc_configure_burst_sizes(void)
904{
905 int i;
906 const int burst_size = BURST_SIZE_X8;
907
908 /* Configure burst size always to maximum size */
909 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 910 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 911}
912
f0e5caab 913u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 914{
915 unsigned unit = dss_feat_get_burst_size_unit();
916 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
917 return unit * 8;
918}
919
d3862610
M		 920void dispc_enable_gamma_table(bool enable)
921{
922 /*
923 * This is partially implemented to support only disabling of
924 * the gamma table.
925 */
926 if (enable) {
927 DSSWARN("Gamma table enabling for TV not yet supported");
928 return;
929 }
930
931 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
932}
933
26d9dd0d 934void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 935{
936 u16 reg;
937
938 if (channel == OMAP_DSS_CHANNEL_LCD)
939 reg = DISPC_CONFIG;
940 else if (channel == OMAP_DSS_CHANNEL_LCD2)
941 reg = DISPC_CONFIG2;
942 else
943 return;
944
945 REG_FLD_MOD(reg, enable, 15, 15);
946}
947
26d9dd0d 948void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 949 struct omap_dss_cpr_coefs *coefs)
950{
951 u32 coef_r, coef_g, coef_b;
952
dac57a05 953 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 954 return;
955
956 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
957 FLD_VAL(coefs->rb, 9, 0);
958 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
959 FLD_VAL(coefs->gb, 9, 0);
960 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
961 FLD_VAL(coefs->bb, 9, 0);
962
963 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
964 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
965 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
966}
967
f0e5caab 968static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 969{
970 u32 val;
971
972 BUG_ON(plane == OMAP_DSS_GFX);
973
9b372c2d 974 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 975 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 976 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 977}
978
c3d92529 979static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 980{
fe3cc9d6
TV		 981 static const unsigned shifts[] = { 5, 10, 10 };
982 int shift;
80c39712 983
fe3cc9d6
TV		 984 shift = shifts[plane];
985 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 986}
987
26d9dd0d 988void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 989{
990 u32 val;
991 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
992 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 993 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 994}
995
996void dispc_set_digit_size(u16 width, u16 height)
997{
998 u32 val;
999 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1000 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1001 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1002}
1003
1004static void dispc_read_plane_fifo_sizes(void)
1005{
80c39712
TV		 1006 u32 size;
1007 int plane;
a0acb557 1008 u8 start, end;
5ed8cf5b
TV		 1009 u32 unit;
1010
1011 unit = dss_feat_get_buffer_size_unit();
80c39712 1012
a0acb557 1013 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1014
e13a138b 1015 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1016 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1017 size *= unit;
80c39712
TV		 1018 dispc.fifo_size[plane] = size;
1019 }
80c39712
TV		 1020}
1021
f0e5caab 1022u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1023{
1024 return dispc.fifo_size[plane];
1025}
1026
c3d92529
AT		 1027static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1028 u32 high)
80c39712 1029{
a0acb557 1030 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1031 u32 unit;
1032
1033 unit = dss_feat_get_buffer_size_unit();
1034
1035 WARN_ON(low % unit != 0);
1036 WARN_ON(high % unit != 0);
1037
1038 low /= unit;
1039 high /= unit;
a0acb557 1040
9b372c2d
AT		 1041 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1042 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1043
80c39712
TV		 1044 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1045 plane,
9b372c2d
AT		 1046 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1047 lo_start, lo_end),
1048 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1049 hi_start, hi_end),
80c39712
TV		 1050 low, high);
1051
9b372c2d 1052 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1053 FLD_VAL(high, hi_start, hi_end) |
1054 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1055}
1056
1057void dispc_enable_fifomerge(bool enable)
1058{
80c39712
TV		 1059 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1060 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1061}
1062
f0e5caab 1063static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1064 int hinc, int vinc,
1065 enum omap_color_component color_comp)
80c39712
TV		 1066{
1067 u32 val;
80c39712 1068
0d66cbb5
AJ		 1069 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1070 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1071
0d66cbb5
AJ		 1072 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1073 &hinc_start, &hinc_end);
1074 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1075 &vinc_start, &vinc_end);
1076 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1077 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1078
0d66cbb5
AJ		 1079 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1080 } else {
1081 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1082 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1083 }
80c39712
TV		 1084}
1085
f0e5caab 1086static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1087{
1088 u32 val;
87a7484b 1089 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1090
87a7484b
AT		 1091 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1092 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1093
1094 val = FLD_VAL(vaccu, vert_start, vert_end) |
1095 FLD_VAL(haccu, hor_start, hor_end);
1096
9b372c2d 1097 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1098}
1099
f0e5caab 1100static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1101{
1102 u32 val;
87a7484b 1103 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1104
87a7484b
AT		 1105 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1106 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1107
1108 val = FLD_VAL(vaccu, vert_start, vert_end) |
1109 FLD_VAL(haccu, hor_start, hor_end);
1110
9b372c2d 1111 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1112}
1113
f0e5caab
TV		 1114static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1115 int vaccu)
ab5ca071
AJ		 1116{
1117 u32 val;
1118
1119 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1120 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1121}
1122
f0e5caab
TV		 1123static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1124 int vaccu)
ab5ca071
AJ		 1125{
1126 u32 val;
1127
1128 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1129 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1130}
80c39712 1131
f0e5caab 1132static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1133 u16 orig_width, u16 orig_height,
1134 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1135 bool five_taps, u8 rotation,
1136 enum omap_color_component color_comp)
80c39712 1137{
0d66cbb5 1138 int fir_hinc, fir_vinc;
80c39712 1139 int hscaleup, vscaleup;
80c39712
TV		 1140
1141 hscaleup = orig_width <= out_width;
1142 vscaleup = orig_height <= out_height;
1143
f0e5caab
TV		 1144 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1145 color_comp);
80c39712 1146
ed14a3ce
AJ		 1147 fir_hinc = 1024 * orig_width / out_width;
1148 fir_vinc = 1024 * orig_height / out_height;
80c39712 1149
f0e5caab 1150 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1151}
1152
f0e5caab 1153static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1154 u16 orig_width, u16 orig_height,
1155 u16 out_width, u16 out_height,
1156 bool ilace, bool five_taps,
1157 bool fieldmode, enum omap_color_mode color_mode,
1158 u8 rotation)
1159{
1160 int accu0 = 0;
1161 int accu1 = 0;
1162 u32 l;
80c39712 1163
f0e5caab 1164 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1165 out_width, out_height, five_taps,
1166 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1167 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1168
87a7484b
AT		 1169 /* RESIZEENABLE and VERTICALTAPS */
1170 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1171 l |= (orig_width != out_width) ? (1 << 5) : 0;
1172 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1173 l |= five_taps ? (1 << 21) : 0;
80c39712 1174
87a7484b
AT		 1175 /* VRESIZECONF and HRESIZECONF */
1176 if (dss_has_feature(FEAT_RESIZECONF)) {
1177 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1178 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1179 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1180 }
80c39712 1181
87a7484b
AT		 1182 /* LINEBUFFERSPLIT */
1183 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1184 l &= ~(0x1 << 22);
1185 l |= five_taps ? (1 << 22) : 0;
1186 }
80c39712 1187
9b372c2d 1188 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1189
1190 /*
1191 * field 0 = even field = bottom field
1192 * field 1 = odd field = top field
1193 */
1194 if (ilace && !fieldmode) {
1195 accu1 = 0;
0d66cbb5 1196 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1197 if (accu0 >= 1024/2) {
1198 accu1 = 1024/2;
1199 accu0 -= accu1;
1200 }
1201 }
1202
f0e5caab
TV		 1203 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1204 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1205}
1206
f0e5caab 1207static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1208 u16 orig_width, u16 orig_height,
1209 u16 out_width, u16 out_height,
1210 bool ilace, bool five_taps,
1211 bool fieldmode, enum omap_color_mode color_mode,
1212 u8 rotation)
1213{
1214 int scale_x = out_width != orig_width;
1215 int scale_y = out_height != orig_height;
1216
1217 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1218 return;
1219 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1220 color_mode != OMAP_DSS_COLOR_UYVY &&
1221 color_mode != OMAP_DSS_COLOR_NV12)) {
1222 /* reset chroma resampling for RGB formats */
1223 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1224 return;
1225 }
1226 switch (color_mode) {
1227 case OMAP_DSS_COLOR_NV12:
1228 /* UV is subsampled by 2 vertically*/
1229 orig_height >>= 1;
1230 /* UV is subsampled by 2 horz.*/
1231 orig_width >>= 1;
1232 break;
1233 case OMAP_DSS_COLOR_YUV2:
1234 case OMAP_DSS_COLOR_UYVY:
1235 /*For YUV422 with 90/270 rotation,
1236 *we don't upsample chroma
1237 */
1238 if (rotation == OMAP_DSS_ROT_0 ||
1239 rotation == OMAP_DSS_ROT_180)
1240 /* UV is subsampled by 2 hrz*/
1241 orig_width >>= 1;
1242 /* must use FIR for YUV422 if rotated */
1243 if (rotation != OMAP_DSS_ROT_0)
1244 scale_x = scale_y = true;
1245 break;
1246 default:
1247 BUG();
1248 }
1249
1250 if (out_width != orig_width)
1251 scale_x = true;
1252 if (out_height != orig_height)
1253 scale_y = true;
1254
f0e5caab 1255 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1256 out_width, out_height, five_taps,
1257 rotation, DISPC_COLOR_COMPONENT_UV);
1258
1259 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1260 (scale_x || scale_y) ? 1 : 0, 8, 8);
1261 /* set H scaling */
1262 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1263 /* set V scaling */
1264 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1265
f0e5caab
TV		 1266 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1267 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
0d66cbb5
AJ		 1268}
1269
f0e5caab 1270static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1271 u16 orig_width, u16 orig_height,
1272 u16 out_width, u16 out_height,
1273 bool ilace, bool five_taps,
1274 bool fieldmode, enum omap_color_mode color_mode,
1275 u8 rotation)
1276{
1277 BUG_ON(plane == OMAP_DSS_GFX);
1278
f0e5caab 1279 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1280 orig_width, orig_height,
1281 out_width, out_height,
1282 ilace, five_taps,
1283 fieldmode, color_mode,
1284 rotation);
1285
f0e5caab 1286 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1287 orig_width, orig_height,
1288 out_width, out_height,
1289 ilace, five_taps,
1290 fieldmode, color_mode,
1291 rotation);
1292}
1293
f0e5caab 1294static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1295 bool mirroring, enum omap_color_mode color_mode)
1296{
87a7484b
AT		 1297 bool row_repeat = false;
1298 int vidrot = 0;
1299
80c39712
TV		 1300 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1301 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1302
1303 if (mirroring) {
1304 switch (rotation) {
1305 case OMAP_DSS_ROT_0:
1306 vidrot = 2;
1307 break;
1308 case OMAP_DSS_ROT_90:
1309 vidrot = 1;
1310 break;
1311 case OMAP_DSS_ROT_180:
1312 vidrot = 0;
1313 break;
1314 case OMAP_DSS_ROT_270:
1315 vidrot = 3;
1316 break;
1317 }
1318 } else {
1319 switch (rotation) {
1320 case OMAP_DSS_ROT_0:
1321 vidrot = 0;
1322 break;
1323 case OMAP_DSS_ROT_90:
1324 vidrot = 1;
1325 break;
1326 case OMAP_DSS_ROT_180:
1327 vidrot = 2;
1328 break;
1329 case OMAP_DSS_ROT_270:
1330 vidrot = 3;
1331 break;
1332 }
1333 }
1334
80c39712 1335 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1336 row_repeat = true;
80c39712 1337 else
87a7484b 1338 row_repeat = false;
80c39712 1339 }
87a7484b 1340
9b372c2d 1341 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1342 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1343 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1344 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1345}
1346
1347static int color_mode_to_bpp(enum omap_color_mode color_mode)
1348{
1349 switch (color_mode) {
1350 case OMAP_DSS_COLOR_CLUT1:
1351 return 1;
1352 case OMAP_DSS_COLOR_CLUT2:
1353 return 2;
1354 case OMAP_DSS_COLOR_CLUT4:
1355 return 4;
1356 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1357 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1358 return 8;
1359 case OMAP_DSS_COLOR_RGB12U:
1360 case OMAP_DSS_COLOR_RGB16:
1361 case OMAP_DSS_COLOR_ARGB16:
1362 case OMAP_DSS_COLOR_YUV2:
1363 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1364 case OMAP_DSS_COLOR_RGBA16:
1365 case OMAP_DSS_COLOR_RGBX16:
1366 case OMAP_DSS_COLOR_ARGB16_1555:
1367 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1368 return 16;
1369 case OMAP_DSS_COLOR_RGB24P:
1370 return 24;
1371 case OMAP_DSS_COLOR_RGB24U:
1372 case OMAP_DSS_COLOR_ARGB32:
1373 case OMAP_DSS_COLOR_RGBA32:
1374 case OMAP_DSS_COLOR_RGBX32:
1375 return 32;
1376 default:
1377 BUG();
1378 }
1379}
1380
1381static s32 pixinc(int pixels, u8 ps)
1382{
1383 if (pixels == 1)
1384 return 1;
1385 else if (pixels > 1)
1386 return 1 + (pixels - 1) * ps;
1387 else if (pixels < 0)
1388 return 1 - (-pixels + 1) * ps;
1389 else
1390 BUG();
1391}
1392
1393static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1394 u16 screen_width,
1395 u16 width, u16 height,
1396 enum omap_color_mode color_mode, bool fieldmode,
1397 unsigned int field_offset,
1398 unsigned *offset0, unsigned *offset1,
1399 s32 *row_inc, s32 *pix_inc)
1400{
1401 u8 ps;
1402
1403 /* FIXME CLUT formats */
1404 switch (color_mode) {
1405 case OMAP_DSS_COLOR_CLUT1:
1406 case OMAP_DSS_COLOR_CLUT2:
1407 case OMAP_DSS_COLOR_CLUT4:
1408 case OMAP_DSS_COLOR_CLUT8:
1409 BUG();
1410 return;
1411 case OMAP_DSS_COLOR_YUV2:
1412 case OMAP_DSS_COLOR_UYVY:
1413 ps = 4;
1414 break;
1415 default:
1416 ps = color_mode_to_bpp(color_mode) / 8;
1417 break;
1418 }
1419
1420 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1421 width, height);
1422
1423 /*
1424 * field 0 = even field = bottom field
1425 * field 1 = odd field = top field
1426 */
1427 switch (rotation + mirror * 4) {
1428 case OMAP_DSS_ROT_0:
1429 case OMAP_DSS_ROT_180:
1430 /*
1431 * If the pixel format is YUV or UYVY divide the width
1432 * of the image by 2 for 0 and 180 degree rotation.
1433 */
1434 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1435 color_mode == OMAP_DSS_COLOR_UYVY)
1436 width = width >> 1;
1437 case OMAP_DSS_ROT_90:
1438 case OMAP_DSS_ROT_270:
1439 *offset1 = 0;
1440 if (field_offset)
1441 *offset0 = field_offset * screen_width * ps;
1442 else
1443 *offset0 = 0;
1444
1445 *row_inc = pixinc(1 + (screen_width - width) +
1446 (fieldmode ? screen_width : 0),
1447 ps);
1448 *pix_inc = pixinc(1, ps);
1449 break;
1450
1451 case OMAP_DSS_ROT_0 + 4:
1452 case OMAP_DSS_ROT_180 + 4:
1453 /* If the pixel format is YUV or UYVY divide the width
1454 * of the image by 2 for 0 degree and 180 degree
1455 */
1456 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1457 color_mode == OMAP_DSS_COLOR_UYVY)
1458 width = width >> 1;
1459 case OMAP_DSS_ROT_90 + 4:
1460 case OMAP_DSS_ROT_270 + 4:
1461 *offset1 = 0;
1462 if (field_offset)
1463 *offset0 = field_offset * screen_width * ps;
1464 else
1465 *offset0 = 0;
1466 *row_inc = pixinc(1 - (screen_width + width) -
1467 (fieldmode ? screen_width : 0),
1468 ps);
1469 *pix_inc = pixinc(1, ps);
1470 break;
1471
1472 default:
1473 BUG();
1474 }
1475}
1476
1477static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1478 u16 screen_width,
1479 u16 width, u16 height,
1480 enum omap_color_mode color_mode, bool fieldmode,
1481 unsigned int field_offset,
1482 unsigned *offset0, unsigned *offset1,
1483 s32 *row_inc, s32 *pix_inc)
1484{
1485 u8 ps;
1486 u16 fbw, fbh;
1487
1488 /* FIXME CLUT formats */
1489 switch (color_mode) {
1490 case OMAP_DSS_COLOR_CLUT1:
1491 case OMAP_DSS_COLOR_CLUT2:
1492 case OMAP_DSS_COLOR_CLUT4:
1493 case OMAP_DSS_COLOR_CLUT8:
1494 BUG();
1495 return;
1496 default:
1497 ps = color_mode_to_bpp(color_mode) / 8;
1498 break;
1499 }
1500
1501 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1502 width, height);
1503
1504 /* width & height are overlay sizes, convert to fb sizes */
1505
1506 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1507 fbw = width;
1508 fbh = height;
1509 } else {
1510 fbw = height;
1511 fbh = width;
1512 }
1513
1514 /*
1515 * field 0 = even field = bottom field
1516 * field 1 = odd field = top field
1517 */
1518 switch (rotation + mirror * 4) {
1519 case OMAP_DSS_ROT_0:
1520 *offset1 = 0;
1521 if (field_offset)
1522 *offset0 = *offset1 + field_offset * screen_width * ps;
1523 else
1524 *offset0 = *offset1;
1525 *row_inc = pixinc(1 + (screen_width - fbw) +
1526 (fieldmode ? screen_width : 0),
1527 ps);
1528 *pix_inc = pixinc(1, ps);
1529 break;
1530 case OMAP_DSS_ROT_90:
1531 *offset1 = screen_width * (fbh - 1) * ps;
1532 if (field_offset)
1533 *offset0 = *offset1 + field_offset * ps;
1534 else
1535 *offset0 = *offset1;
1536 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1537 (fieldmode ? 1 : 0), ps);
1538 *pix_inc = pixinc(-screen_width, ps);
1539 break;
1540 case OMAP_DSS_ROT_180:
1541 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1542 if (field_offset)
1543 *offset0 = *offset1 - field_offset * screen_width * ps;
1544 else
1545 *offset0 = *offset1;
1546 *row_inc = pixinc(-1 -
1547 (screen_width - fbw) -
1548 (fieldmode ? screen_width : 0),
1549 ps);
1550 *pix_inc = pixinc(-1, ps);
1551 break;
1552 case OMAP_DSS_ROT_270:
1553 *offset1 = (fbw - 1) * ps;
1554 if (field_offset)
1555 *offset0 = *offset1 - field_offset * ps;
1556 else
1557 *offset0 = *offset1;
1558 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1559 (fieldmode ? 1 : 0), ps);
1560 *pix_inc = pixinc(screen_width, ps);
1561 break;
1562
1563 /* mirroring */
1564 case OMAP_DSS_ROT_0 + 4:
1565 *offset1 = (fbw - 1) * ps;
1566 if (field_offset)
1567 *offset0 = *offset1 + field_offset * screen_width * ps;
1568 else
1569 *offset0 = *offset1;
1570 *row_inc = pixinc(screen_width * 2 - 1 +
1571 (fieldmode ? screen_width : 0),
1572 ps);
1573 *pix_inc = pixinc(-1, ps);
1574 break;
1575
1576 case OMAP_DSS_ROT_90 + 4:
1577 *offset1 = 0;
1578 if (field_offset)
1579 *offset0 = *offset1 + field_offset * ps;
1580 else
1581 *offset0 = *offset1;
1582 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1583 (fieldmode ? 1 : 0),
1584 ps);
1585 *pix_inc = pixinc(screen_width, ps);
1586 break;
1587
1588 case OMAP_DSS_ROT_180 + 4:
1589 *offset1 = screen_width * (fbh - 1) * ps;
1590 if (field_offset)
1591 *offset0 = *offset1 - field_offset * screen_width * ps;
1592 else
1593 *offset0 = *offset1;
1594 *row_inc = pixinc(1 - screen_width * 2 -
1595 (fieldmode ? screen_width : 0),
1596 ps);
1597 *pix_inc = pixinc(1, ps);
1598 break;
1599
1600 case OMAP_DSS_ROT_270 + 4:
1601 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1602 if (field_offset)
1603 *offset0 = *offset1 - field_offset * ps;
1604 else
1605 *offset0 = *offset1;
1606 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1607 (fieldmode ? 1 : 0),
1608 ps);
1609 *pix_inc = pixinc(-screen_width, ps);
1610 break;
1611
1612 default:
1613 BUG();
1614 }
1615}
1616
ff1b2cde
SS		 1617static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1618 u16 height, u16 out_width, u16 out_height,
1619 enum omap_color_mode color_mode)
80c39712
TV		 1620{
1621 u32 fclk = 0;
1622 /* FIXME venc pclk? */
26d9dd0d 1623 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1624
1625 if (height > out_height) {
1626 /* FIXME get real display PPL */
1627 unsigned int ppl = 800;
1628
1629 tmp = pclk * height * out_width;
1630 do_div(tmp, 2 * out_height * ppl);
1631 fclk = tmp;
1632
2d9c5597
VS		 1633 if (height > 2 * out_height) {
1634 if (ppl == out_width)
1635 return 0;
1636
80c39712
TV		 1637 tmp = pclk * (height - 2 * out_height) * out_width;
1638 do_div(tmp, 2 * out_height * (ppl - out_width));
1639 fclk = max(fclk, (u32) tmp);
1640 }
1641 }
1642
1643 if (width > out_width) {
1644 tmp = pclk * width;
1645 do_div(tmp, out_width);
1646 fclk = max(fclk, (u32) tmp);
1647
1648 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1649 fclk <<= 1;
1650 }
1651
1652 return fclk;
1653}
1654
ff1b2cde
SS		 1655static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1656 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1657{
1658 unsigned int hf, vf;
1659
1660 /*
1661 * FIXME how to determine the 'A' factor
1662 * for the no downscaling case ?
1663 */
1664
1665 if (width > 3 * out_width)
1666 hf = 4;
1667 else if (width > 2 * out_width)
1668 hf = 3;
1669 else if (width > out_width)
1670 hf = 2;
1671 else
1672 hf = 1;
1673
1674 if (height > out_height)
1675 vf = 2;
1676 else
1677 vf = 1;
1678
1679 /* FIXME venc pclk? */
26d9dd0d 1680 return dispc_mgr_pclk_rate(channel) * vf * hf;
80c39712
TV		 1681}
1682
a4273b7c 1683int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
c3d92529
AT		 1684 bool ilace, enum omap_channel channel, bool replication,
1685 u32 fifo_low, u32 fifo_high)
80c39712
TV		 1686{
1687 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1688 bool five_taps = 0;
1689 bool fieldmode = 0;
1690 int cconv = 0;
1691 unsigned offset0, offset1;
1692 s32 row_inc;
1693 s32 pix_inc;
a4273b7c 1694 u16 frame_height = oi->height;
80c39712
TV		 1695 unsigned int field_offset = 0;
1696
a4273b7c 1697 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
c3d92529
AT		 1698 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1699 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1700 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1701 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1702 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
e6d80f95 1703
a4273b7c 1704 if (oi->paddr == 0)
80c39712
TV		 1705 return -EINVAL;
1706
a4273b7c 1707 if (ilace && oi->height == oi->out_height)
80c39712
TV		 1708 fieldmode = 1;
1709
1710 if (ilace) {
1711 if (fieldmode)
a4273b7c
AT		 1712 oi->height /= 2;
1713 oi->pos_y /= 2;
1714 oi->out_height /= 2;
80c39712
TV		 1715
1716 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1717 "out_height %d\n",
a4273b7c 1718 oi->height, oi->pos_y, oi->out_height);
80c39712
TV		 1719 }
1720
a4273b7c 1721 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 1722 return -EINVAL;
1723
80c39712 1724 if (plane == OMAP_DSS_GFX) {
a4273b7c 1725 if (oi->width != oi->out_width || oi->height != oi->out_height)
80c39712 1726 return -EINVAL;
80c39712
TV		 1727 } else {
1728 /* video plane */
1729
1730 unsigned long fclk = 0;
1731
a4273b7c
AT		 1732 if (oi->out_width < oi->width / maxdownscale ||
1733 oi->out_width > oi->width * 8)
80c39712
TV		 1734 return -EINVAL;
1735
a4273b7c
AT		 1736 if (oi->out_height < oi->height / maxdownscale ||
1737 oi->out_height > oi->height * 8)
80c39712
TV		 1738 return -EINVAL;
1739
a4273b7c
AT		 1740 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1741 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1742 oi->color_mode == OMAP_DSS_COLOR_NV12)
80c39712 1743 cconv = 1;
80c39712
TV		 1744
1745 /* Must use 5-tap filter? */
a4273b7c 1746 five_taps = oi->height > oi->out_height * 2;
80c39712
TV		 1747
1748 if (!five_taps) {
a4273b7c
AT		 1749 fclk = calc_fclk(channel, oi->width, oi->height,
1750 oi->out_width, oi->out_height);
80c39712
TV		 1751
1752 /* Try 5-tap filter if 3-tap fclk is too high */
a4273b7c 1753 if (cpu_is_omap34xx() && oi->height > oi->out_height &&
80c39712
TV		 1754 fclk > dispc_fclk_rate())
1755 five_taps = true;
1756 }
1757
a4273b7c 1758 if (oi->width > (2048 >> five_taps)) {
80c39712
TV		 1759 DSSERR("failed to set up scaling, fclk too low\n");
1760 return -EINVAL;
1761 }
1762
1763 if (five_taps)
a4273b7c
AT		 1764 fclk = calc_fclk_five_taps(channel, oi->width,
1765 oi->height, oi->out_width,
1766 oi->out_height, oi->color_mode);
80c39712
TV		 1767
1768 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1769 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1770
2d9c5597 1771 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1772 DSSERR("failed to set up scaling, "
1773 "required fclk rate = %lu Hz, "
1774 "current fclk rate = %lu Hz\n",
1775 fclk, dispc_fclk_rate());
1776 return -EINVAL;
1777 }
1778 }
1779
1780 if (ilace && !fieldmode) {
1781 /*
1782 * when downscaling the bottom field may have to start several
1783 * source lines below the top field. Unfortunately ACCUI
1784 * registers will only hold the fractional part of the offset
1785 * so the integer part must be added to the base address of the
1786 * bottom field.
1787 */
a4273b7c 1788 if (!oi->height || oi->height == oi->out_height)
80c39712
TV		 1789 field_offset = 0;
1790 else
a4273b7c 1791 field_offset = oi->height / oi->out_height / 2;
80c39712
TV		 1792 }
1793
1794 /* Fields are independent but interleaved in memory. */
1795 if (fieldmode)
1796 field_offset = 1;
1797
a4273b7c
AT		 1798 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1799 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1800 oi->screen_width, oi->width, frame_height,
1801 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1802 &offset0, &offset1, &row_inc, &pix_inc);
1803 else
a4273b7c
AT		 1804 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1805 oi->screen_width, oi->width, frame_height,
1806 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1807 &offset0, &offset1, &row_inc, &pix_inc);
1808
1809 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1810 offset0, offset1, row_inc, pix_inc);
1811
a4273b7c 1812 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 1813
a4273b7c
AT		 1814 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1815 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 1816
a4273b7c
AT		 1817 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1818 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1819 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 1820 }
1821
1822
f0e5caab
TV		 1823 dispc_ovl_set_row_inc(plane, row_inc);
1824 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 1825
a4273b7c
AT		 1826 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1827 oi->height, oi->out_width, oi->out_height);
80c39712 1828
a4273b7c 1829 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 1830
a4273b7c 1831 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
80c39712
TV		 1832
1833 if (plane != OMAP_DSS_GFX) {
a4273b7c
AT		 1834 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1835 oi->out_width, oi->out_height,
0d66cbb5 1836 ilace, five_taps, fieldmode,
a4273b7c
AT		 1837 oi->color_mode, oi->rotation);
1838 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
f0e5caab 1839 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 1840 }
1841
a4273b7c
AT		 1842 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1843 oi->color_mode);
80c39712 1844
a4273b7c
AT		 1845 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1846 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 1847
f0e5caab 1848 dispc_ovl_set_channel_out(plane, channel);
8fa8031c 1849
c3d92529
AT		 1850 dispc_ovl_enable_replication(plane, replication);
1851 dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1852
80c39712
TV		 1853 return 0;
1854}
1855
f0e5caab 1856int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 1857{
e6d80f95
TV		 1858 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1859
9b372c2d 1860 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 1861
1862 return 0;
80c39712
TV		 1863}
1864
1865static void dispc_disable_isr(void *data, u32 mask)
1866{
1867 struct completion *compl = data;
1868 complete(compl);
1869}
1870
2a205f34 1871static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1872{
2a205f34
SS		 1873 if (channel == OMAP_DSS_CHANNEL_LCD2)
1874 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1875 else
1876 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1877}
1878
26d9dd0d 1879static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1880{
1881 struct completion frame_done_completion;
1882 bool is_on;
1883 int r;
2a205f34 1884 u32 irq;
80c39712 1885
80c39712
TV		 1886 /* When we disable LCD output, we need to wait until frame is done.
1887 * Otherwise the DSS is still working, and turning off the clocks
1888 * prevents DSS from going to OFF mode */
2a205f34
SS		 1889 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1890 REG_GET(DISPC_CONTROL2, 0, 0) :
1891 REG_GET(DISPC_CONTROL, 0, 0);
1892
1893 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1894 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1895
1896 if (!enable && is_on) {
1897 init_completion(&frame_done_completion);
1898
1899 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1900 &frame_done_completion, irq);
80c39712
TV		 1901
1902 if (r)
1903 DSSERR("failed to register FRAMEDONE isr\n");
1904 }
1905
2a205f34 1906 _enable_lcd_out(channel, enable);
80c39712
TV		 1907
1908 if (!enable && is_on) {
1909 if (!wait_for_completion_timeout(&frame_done_completion,
1910 msecs_to_jiffies(100)))
1911 DSSERR("timeout waiting for FRAME DONE\n");
1912
1913 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1914 &frame_done_completion, irq);
80c39712
TV		 1915
1916 if (r)
1917 DSSERR("failed to unregister FRAMEDONE isr\n");
1918 }
80c39712
TV		 1919}
1920
1921static void _enable_digit_out(bool enable)
1922{
1923 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1924}
1925
26d9dd0d 1926static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 1927{
1928 struct completion frame_done_completion;
e82b090b
TV		 1929 enum dss_hdmi_venc_clk_source_select src;
1930 int r, i;
1931 u32 irq_mask;
1932 int num_irqs;
80c39712 1933
e6d80f95 1934 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 1935 return;
80c39712 1936
e82b090b
TV		 1937 src = dss_get_hdmi_venc_clk_source();
1938
80c39712
TV		 1939 if (enable) {
1940 unsigned long flags;
1941 /* When we enable digit output, we'll get an extra digit
1942 * sync lost interrupt, that we need to ignore */
1943 spin_lock_irqsave(&dispc.irq_lock, flags);
1944 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1945 _omap_dispc_set_irqs();
1946 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1947 }
1948
1949 /* When we disable digit output, we need to wait until fields are done.
1950 * Otherwise the DSS is still working, and turning off the clocks
1951 * prevents DSS from going to OFF mode. And when enabling, we need to
1952 * wait for the extra sync losts */
1953 init_completion(&frame_done_completion);
1954
e82b090b
TV		 1955 if (src == DSS_HDMI_M_PCLK && enable == false) {
1956 irq_mask = DISPC_IRQ_FRAMEDONETV;
1957 num_irqs = 1;
1958 } else {
1959 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
1960 /* XXX I understand from TRM that we should only wait for the
1961 * current field to complete. But it seems we have to wait for
1962 * both fields */
1963 num_irqs = 2;
1964 }
1965
80c39712 1966 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 1967 irq_mask);
80c39712 1968 if (r)
e82b090b 1969 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 1970
1971 _enable_digit_out(enable);
1972
e82b090b
TV		 1973 for (i = 0; i < num_irqs; ++i) {
1974 if (!wait_for_completion_timeout(&frame_done_completion,
1975 msecs_to_jiffies(100)))
1976 DSSERR("timeout waiting for digit out to %s\n",
1977 enable ? "start" : "stop");
1978 }
80c39712 1979
e82b090b
TV		 1980 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
1981 irq_mask);
80c39712 1982 if (r)
e82b090b 1983 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 1984
1985 if (enable) {
1986 unsigned long flags;
1987 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 1988 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 1989 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1990 _omap_dispc_set_irqs();
1991 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1992 }
80c39712
TV		 1993}
1994
26d9dd0d 1995bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 1996{
1997 if (channel == OMAP_DSS_CHANNEL_LCD)
1998 return !!REG_GET(DISPC_CONTROL, 0, 0);
1999 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2000 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2001 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2002 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2003 else
2004 BUG();
2005}
2006
26d9dd0d 2007void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2008{
dac57a05 2009 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2010 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2011 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2012 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2013 else
2014 BUG();
2015}
2016
80c39712
TV		 2017void dispc_lcd_enable_signal_polarity(bool act_high)
2018{
6ced40bf
AT		 2019 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2020 return;
2021
80c39712 2022 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2023}
2024
2025void dispc_lcd_enable_signal(bool enable)
2026{
6ced40bf
AT		 2027 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2028 return;
2029
80c39712 2030 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2031}
2032
2033void dispc_pck_free_enable(bool enable)
2034{
6ced40bf
AT		 2035 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2036 return;
2037
80c39712 2038 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2039}
2040
26d9dd0d 2041void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2042{
2a205f34
SS		 2043 if (channel == OMAP_DSS_CHANNEL_LCD2)
2044 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2045 else
2046 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2047}
2048
2049
26d9dd0d 2050void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2051 enum omap_lcd_display_type type)
80c39712
TV		 2052{
2053 int mode;
2054
2055 switch (type) {
2056 case OMAP_DSS_LCD_DISPLAY_STN:
2057 mode = 0;
2058 break;
2059
2060 case OMAP_DSS_LCD_DISPLAY_TFT:
2061 mode = 1;
2062 break;
2063
2064 default:
2065 BUG();
2066 return;
2067 }
2068
2a205f34
SS		 2069 if (channel == OMAP_DSS_CHANNEL_LCD2)
2070 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2071 else
2072 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2073}
2074
2075void dispc_set_loadmode(enum omap_dss_load_mode mode)
2076{
80c39712 2077 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2078}
2079
2080
26d9dd0d 2081void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2082{
8613b000 2083 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2084}
2085
26d9dd0d 2086u32 dispc_mgr_get_default_color(enum omap_channel channel)
80c39712 2087{
80c39712
TV		 2088 u32 l;
2089
2090 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2091 channel != OMAP_DSS_CHANNEL_LCD &&
2092 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712 2093
8613b000 2094 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2095
2096 return l;
2097}
2098
26d9dd0d 2099void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2100 enum omap_dss_trans_key_type type,
2101 u32 trans_key)
2102{
80c39712
TV		 2103 if (ch == OMAP_DSS_CHANNEL_LCD)
2104 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2105 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2106 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2107 else /* OMAP_DSS_CHANNEL_LCD2 */
2108 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2109
8613b000 2110 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2111}
2112
26d9dd0d 2113void dispc_mgr_get_trans_key(enum omap_channel ch,
80c39712
TV		 2114 enum omap_dss_trans_key_type *type,
2115 u32 *trans_key)
2116{
80c39712
TV		 2117 if (type) {
2118 if (ch == OMAP_DSS_CHANNEL_LCD)
2119 *type = REG_GET(DISPC_CONFIG, 11, 11);
2120 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2121 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2122 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2123 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2124 else
2125 BUG();
2126 }
2127
2128 if (trans_key)
8613b000 2129 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2130}
2131
26d9dd0d 2132void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2133{
80c39712
TV		 2134 if (ch == OMAP_DSS_CHANNEL_LCD)
2135 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2136 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2137 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2138 else /* OMAP_DSS_CHANNEL_LCD2 */
2139 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2140}
26d9dd0d 2141void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable)
80c39712 2142{
a0acb557 2143 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2144 return;
2145
80c39712
TV		 2146 if (ch == OMAP_DSS_CHANNEL_LCD)
2147 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2148 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2149 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2150 else /* OMAP_DSS_CHANNEL_LCD2 */
2151 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712 2152}
26d9dd0d 2153bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch)
80c39712
TV		 2154{
2155 bool enabled;
2156
a0acb557 2157 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2158 return false;
2159
80c39712
TV		 2160 if (ch == OMAP_DSS_CHANNEL_LCD)
2161 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2162 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2163 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2164 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2165 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2166 else
2167 BUG();
80c39712
TV		 2168
2169 return enabled;
80c39712
TV		 2170}
2171
2172
26d9dd0d 2173bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
80c39712
TV		 2174{
2175 bool enabled;
2176
80c39712
TV		 2177 if (ch == OMAP_DSS_CHANNEL_LCD)
2178 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2179 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2180 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2181 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2182 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2183 else
2184 BUG();
80c39712
TV		 2185
2186 return enabled;
2187}
2188
2189
26d9dd0d 2190void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2191{
2192 int code;
2193
2194 switch (data_lines) {
2195 case 12:
2196 code = 0;
2197 break;
2198 case 16:
2199 code = 1;
2200 break;
2201 case 18:
2202 code = 2;
2203 break;
2204 case 24:
2205 code = 3;
2206 break;
2207 default:
2208 BUG();
2209 return;
2210 }
2211
2a205f34
SS		 2212 if (channel == OMAP_DSS_CHANNEL_LCD2)
2213 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2214 else
2215 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2216}
2217
569969d6 2218void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2219{
2220 u32 l;
569969d6 2221 int gpout0, gpout1;
80c39712
TV		 2222
2223 switch (mode) {
569969d6
AT		 2224 case DSS_IO_PAD_MODE_RESET:
2225 gpout0 = 0;
2226 gpout1 = 0;
80c39712 2227 break;
569969d6
AT		 2228 case DSS_IO_PAD_MODE_RFBI:
2229 gpout0 = 1;
80c39712
TV		 2230 gpout1 = 0;
2231 break;
569969d6
AT		 2232 case DSS_IO_PAD_MODE_BYPASS:
2233 gpout0 = 1;
80c39712
TV		 2234 gpout1 = 1;
2235 break;
80c39712
TV		 2236 default:
2237 BUG();
2238 return;
2239 }
2240
569969d6
AT		 2241 l = dispc_read_reg(DISPC_CONTROL);
2242 l = FLD_MOD(l, gpout0, 15, 15);
2243 l = FLD_MOD(l, gpout1, 16, 16);
2244 dispc_write_reg(DISPC_CONTROL, l);
2245}
2246
2247void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2248{
2249 if (channel == OMAP_DSS_CHANNEL_LCD2)
2250 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2251 else
2252 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2253}
2254
2255static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2256 int vsw, int vfp, int vbp)
2257{
2258 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2259 if (hsw < 1 || hsw > 64 ||
2260 hfp < 1 || hfp > 256 ||
2261 hbp < 1 || hbp > 256 ||
2262 vsw < 1 || vsw > 64 ||
2263 vfp < 0 || vfp > 255 ||
2264 vbp < 0 || vbp > 255)
2265 return false;
2266 } else {
2267 if (hsw < 1 || hsw > 256 ||
2268 hfp < 1 || hfp > 4096 ||
2269 hbp < 1 || hbp > 4096 ||
2270 vsw < 1 || vsw > 256 ||
2271 vfp < 0 || vfp > 4095 ||
2272 vbp < 0 || vbp > 4095)
2273 return false;
2274 }
2275
2276 return true;
2277}
2278
2279bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2280{
2281 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2282 timings->hbp, timings->vsw,
2283 timings->vfp, timings->vbp);
2284}
2285
26d9dd0d 2286static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2287 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2288{
2289 u32 timing_h, timing_v;
2290
2291 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2292 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2293 FLD_VAL(hbp-1, 27, 20);
2294
2295 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2296 FLD_VAL(vbp, 27, 20);
2297 } else {
2298 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2299 FLD_VAL(hbp-1, 31, 20);
2300
2301 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2302 FLD_VAL(vbp, 31, 20);
2303 }
2304
64ba4f74
SS		 2305 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2306 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2307}
2308
2309/* change name to mode? */
26d9dd0d 2310void dispc_mgr_set_lcd_timings(enum omap_channel channel,
64ba4f74 2311 struct omap_video_timings *timings)
80c39712
TV		 2312{
2313 unsigned xtot, ytot;
2314 unsigned long ht, vt;
2315
2316 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2317 timings->hbp, timings->vsw,
2318 timings->vfp, timings->vbp))
2319 BUG();
2320
26d9dd0d 2321 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
64ba4f74
SS		 2322 timings->hbp, timings->vsw, timings->vfp,
2323 timings->vbp);
80c39712 2324
26d9dd0d 2325 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2326
2327 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2328 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2329
2330 ht = (timings->pixel_clock * 1000) / xtot;
2331 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2332
2a205f34
SS		 2333 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2334 timings->y_res);
80c39712
TV		 2335 DSSDBG("pck %u\n", timings->pixel_clock);
2336 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2337 timings->hsw, timings->hfp, timings->hbp,
2338 timings->vsw, timings->vfp, timings->vbp);
2339
2340 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2341}
2342
26d9dd0d 2343static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2344 u16 pck_div)
80c39712
TV		 2345{
2346 BUG_ON(lck_div < 1);
9eaaf207 2347 BUG_ON(pck_div < 1);
80c39712 2348
ce7fa5eb 2349 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2350 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2351}
2352
26d9dd0d 2353static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2354 int *pck_div)
80c39712
TV		 2355{
2356 u32 l;
ce7fa5eb 2357 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2358 *lck_div = FLD_GET(l, 23, 16);
2359 *pck_div = FLD_GET(l, 7, 0);
2360}
2361
2362unsigned long dispc_fclk_rate(void)
2363{
a72b64b9 2364 struct platform_device *dsidev;
80c39712
TV		 2365 unsigned long r = 0;
2366
66534e8e 2367 switch (dss_get_dispc_clk_source()) {
89a35e51 2368 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2369 r = clk_get_rate(dispc.dss_clk);
66534e8e 2370 break;
89a35e51 2371 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2372 dsidev = dsi_get_dsidev_from_id(0);
2373 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2374 break;
5a8b572d
AT		 2375 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2376 dsidev = dsi_get_dsidev_from_id(1);
2377 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2378 break;
66534e8e
TA		 2379 default:
2380 BUG();
2381 }
2382
80c39712
TV		 2383 return r;
2384}
2385
26d9dd0d 2386unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2387{
a72b64b9 2388 struct platform_device *dsidev;
80c39712
TV		 2389 int lcd;
2390 unsigned long r;
2391 u32 l;
2392
ce7fa5eb 2393 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2394
2395 lcd = FLD_GET(l, 23, 16);
2396
ea75159e 2397 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2398 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2399 r = clk_get_rate(dispc.dss_clk);
ea75159e 2400 break;
89a35e51 2401 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2402 dsidev = dsi_get_dsidev_from_id(0);
2403 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2404 break;
5a8b572d
AT		 2405 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2406 dsidev = dsi_get_dsidev_from_id(1);
2407 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2408 break;
ea75159e
TA		 2409 default:
2410 BUG();
2411 }
80c39712
TV		 2412
2413 return r / lcd;
2414}
2415
26d9dd0d 2416unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2417{
ea75159e 2418 int pcd;
80c39712
TV		 2419 unsigned long r;
2420 u32 l;
2421
ce7fa5eb 2422 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2423
80c39712
TV		 2424 pcd = FLD_GET(l, 7, 0);
2425
26d9dd0d 2426 r = dispc_mgr_lclk_rate(channel);
80c39712 2427
ea75159e 2428 return r / pcd;
80c39712
TV		 2429}
2430
2431void dispc_dump_clocks(struct seq_file *s)
2432{
2433 int lcd, pcd;
0cf35df3 2434 u32 l;
89a35e51
AT		 2435 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2436 enum omap_dss_clk_source lcd_clk_src;
80c39712 2437
4fbafaf3
TV		 2438 if (dispc_runtime_get())
2439 return;
80c39712 2440
80c39712
TV		 2441 seq_printf(s, "- DISPC -\n");
2442
067a57e4
AT		 2443 seq_printf(s, "dispc fclk source = %s (%s)\n",
2444 dss_get_generic_clk_source_name(dispc_clk_src),
2445 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2446
2447 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2448
0cf35df3
MR		 2449 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2450 seq_printf(s, "- DISPC-CORE-CLK -\n");
2451 l = dispc_read_reg(DISPC_DIVISOR);
2452 lcd = FLD_GET(l, 23, 16);
2453
2454 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2455 (dispc_fclk_rate()/lcd), lcd);
2456 }
2a205f34
SS		 2457 seq_printf(s, "- LCD1 -\n");
2458
ea75159e
TA		 2459 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2460
2461 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2462 dss_get_generic_clk_source_name(lcd_clk_src),
2463 dss_feat_get_clk_source_name(lcd_clk_src));
2464
26d9dd0d 2465 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2466
ff1b2cde 2467 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2468 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2469 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2470 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2471 if (dss_has_feature(FEAT_MGR_LCD2)) {
2472 seq_printf(s, "- LCD2 -\n");
2473
ea75159e
TA		 2474 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2475
2476 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2477 dss_get_generic_clk_source_name(lcd_clk_src),
2478 dss_feat_get_clk_source_name(lcd_clk_src));
2479
26d9dd0d 2480 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2481
2a205f34 2482 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2483 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2484 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2485 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2486 }
4fbafaf3
TV		 2487
2488 dispc_runtime_put();
80c39712
TV		 2489}
2490
dfc0fd8d
TV		 2491#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2492void dispc_dump_irqs(struct seq_file *s)
2493{
2494 unsigned long flags;
2495 struct dispc_irq_stats stats;
2496
2497 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2498
2499 stats = dispc.irq_stats;
2500 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2501 dispc.irq_stats.last_reset = jiffies;
2502
2503 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2504
2505 seq_printf(s, "period %u ms\n",
2506 jiffies_to_msecs(jiffies - stats.last_reset));
2507
2508 seq_printf(s, "irqs %d\n", stats.irq_count);
2509#define PIS(x) \
2510 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2511
2512 PIS(FRAMEDONE);
2513 PIS(VSYNC);
2514 PIS(EVSYNC_EVEN);
2515 PIS(EVSYNC_ODD);
2516 PIS(ACBIAS_COUNT_STAT);
2517 PIS(PROG_LINE_NUM);
2518 PIS(GFX_FIFO_UNDERFLOW);
2519 PIS(GFX_END_WIN);
2520 PIS(PAL_GAMMA_MASK);
2521 PIS(OCP_ERR);
2522 PIS(VID1_FIFO_UNDERFLOW);
2523 PIS(VID1_END_WIN);
2524 PIS(VID2_FIFO_UNDERFLOW);
2525 PIS(VID2_END_WIN);
2526 PIS(SYNC_LOST);
2527 PIS(SYNC_LOST_DIGIT);
2528 PIS(WAKEUP);
2a205f34
SS		 2529 if (dss_has_feature(FEAT_MGR_LCD2)) {
2530 PIS(FRAMEDONE2);
2531 PIS(VSYNC2);
2532 PIS(ACBIAS_COUNT_STAT2);
2533 PIS(SYNC_LOST2);
2534 }
dfc0fd8d
TV		 2535#undef PIS
2536}
dfc0fd8d
TV		 2537#endif
2538
80c39712
TV		 2539void dispc_dump_regs(struct seq_file *s)
2540{
4dd2da15
AT		 2541 int i, j;
2542 const char *mgr_names[] = {
2543 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2544 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2545 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2546 };
2547 const char *ovl_names[] = {
2548 [OMAP_DSS_GFX] = "GFX",
2549 [OMAP_DSS_VIDEO1] = "VID1",
2550 [OMAP_DSS_VIDEO2] = "VID2",
2551 };
2552 const char **p_names;
2553
9b372c2d 2554#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2555
4fbafaf3
TV		 2556 if (dispc_runtime_get())
2557 return;
80c39712 2558
5010be80 2559 /* DISPC common registers */
80c39712
TV		 2560 DUMPREG(DISPC_REVISION);
2561 DUMPREG(DISPC_SYSCONFIG);
2562 DUMPREG(DISPC_SYSSTATUS);
2563 DUMPREG(DISPC_IRQSTATUS);
2564 DUMPREG(DISPC_IRQENABLE);
2565 DUMPREG(DISPC_CONTROL);
2566 DUMPREG(DISPC_CONFIG);
2567 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2568 DUMPREG(DISPC_LINE_STATUS);
2569 DUMPREG(DISPC_LINE_NUMBER);
332e9d70
TV		 2570 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2571 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2572 if (dss_has_feature(FEAT_MGR_LCD2)) {
2573 DUMPREG(DISPC_CONTROL2);
2574 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2575 }
2576
2577#undef DUMPREG
2578
2579#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2580#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2581 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2582 dispc_read_reg(DISPC_REG(i, r)))
2583
4dd2da15 2584 p_names = mgr_names;
5010be80 2585
4dd2da15
AT		 2586 /* DISPC channel specific registers */
2587 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2588 DUMPREG(i, DISPC_DEFAULT_COLOR);
2589 DUMPREG(i, DISPC_TRANS_COLOR);
2590 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2591
4dd2da15
AT		 2592 if (i == OMAP_DSS_CHANNEL_DIGIT)
2593 continue;
5010be80 2594
4dd2da15
AT		 2595 DUMPREG(i, DISPC_DEFAULT_COLOR);
2596 DUMPREG(i, DISPC_TRANS_COLOR);
2597 DUMPREG(i, DISPC_TIMING_H);
2598 DUMPREG(i, DISPC_TIMING_V);
2599 DUMPREG(i, DISPC_POL_FREQ);
2600 DUMPREG(i, DISPC_DIVISORo);
2601 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2602
4dd2da15
AT		 2603 DUMPREG(i, DISPC_DATA_CYCLE1);
2604 DUMPREG(i, DISPC_DATA_CYCLE2);
2605 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2606
332e9d70 2607 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2608 DUMPREG(i, DISPC_CPR_COEF_R);
2609 DUMPREG(i, DISPC_CPR_COEF_G);
2610 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2611 }
2a205f34 2612 }
80c39712 2613
4dd2da15
AT		 2614 p_names = ovl_names;
2615
2616 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2617 DUMPREG(i, DISPC_OVL_BA0);
2618 DUMPREG(i, DISPC_OVL_BA1);
2619 DUMPREG(i, DISPC_OVL_POSITION);
2620 DUMPREG(i, DISPC_OVL_SIZE);
2621 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2622 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2623 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2624 DUMPREG(i, DISPC_OVL_ROW_INC);
2625 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2626 if (dss_has_feature(FEAT_PRELOAD))
2627 DUMPREG(i, DISPC_OVL_PRELOAD);
2628
2629 if (i == OMAP_DSS_GFX) {
2630 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2631 DUMPREG(i, DISPC_OVL_TABLE_BA);
2632 continue;
2633 }
2634
2635 DUMPREG(i, DISPC_OVL_FIR);
2636 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2637 DUMPREG(i, DISPC_OVL_ACCU0);
2638 DUMPREG(i, DISPC_OVL_ACCU1);
2639 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2640 DUMPREG(i, DISPC_OVL_BA0_UV);
2641 DUMPREG(i, DISPC_OVL_BA1_UV);
2642 DUMPREG(i, DISPC_OVL_FIR2);
2643 DUMPREG(i, DISPC_OVL_ACCU2_0);
2644 DUMPREG(i, DISPC_OVL_ACCU2_1);
2645 }
2646 if (dss_has_feature(FEAT_ATTR2))
2647 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2648 if (dss_has_feature(FEAT_PRELOAD))
2649 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2650 }
5010be80
AT		 2651
2652#undef DISPC_REG
2653#undef DUMPREG
2654
2655#define DISPC_REG(plane, name, i) name(plane, i)
2656#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2657 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2658 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2659 dispc_read_reg(DISPC_REG(plane, name, i)))
2660
4dd2da15 2661 /* Video pipeline coefficient registers */
332e9d70 2662
4dd2da15
AT		 2663 /* start from OMAP_DSS_VIDEO1 */
2664 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2665 for (j = 0; j < 8; j++)
2666 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2667
4dd2da15
AT		 2668 for (j = 0; j < 8; j++)
2669 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2670
4dd2da15
AT		 2671 for (j = 0; j < 5; j++)
2672 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2673
4dd2da15
AT		 2674 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2675 for (j = 0; j < 8; j++)
2676 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2677 }
2678
2679 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2680 for (j = 0; j < 8; j++)
2681 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2682
2683 for (j = 0; j < 8; j++)
2684 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2685
2686 for (j = 0; j < 8; j++)
2687 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2688 }
332e9d70 2689 }
80c39712 2690
4fbafaf3 2691 dispc_runtime_put();
5010be80
AT		 2692
2693#undef DISPC_REG
80c39712
TV		 2694#undef DUMPREG
2695}
2696
26d9dd0d
TV		 2697static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2698 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2699 u8 acb)
80c39712
TV		 2700{
2701 u32 l = 0;
2702
2703 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2704 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2705
2706 l |= FLD_VAL(onoff, 17, 17);
2707 l |= FLD_VAL(rf, 16, 16);
2708 l |= FLD_VAL(ieo, 15, 15);
2709 l |= FLD_VAL(ipc, 14, 14);
2710 l |= FLD_VAL(ihs, 13, 13);
2711 l |= FLD_VAL(ivs, 12, 12);
2712 l |= FLD_VAL(acbi, 11, 8);
2713 l |= FLD_VAL(acb, 7, 0);
2714
ff1b2cde 2715 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2716}
2717
26d9dd0d 2718void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 2719 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2720{
26d9dd0d 2721 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2722 (config & OMAP_DSS_LCD_RF) != 0,
2723 (config & OMAP_DSS_LCD_IEO) != 0,
2724 (config & OMAP_DSS_LCD_IPC) != 0,
2725 (config & OMAP_DSS_LCD_IHS) != 0,
2726 (config & OMAP_DSS_LCD_IVS) != 0,
2727 acbi, acb);
2728}
2729
2730/* with fck as input clock rate, find dispc dividers that produce req_pck */
2731void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2732 struct dispc_clock_info *cinfo)
2733{
9eaaf207 2734 u16 pcd_min, pcd_max;
80c39712
TV		 2735 unsigned long best_pck;
2736 u16 best_ld, cur_ld;
2737 u16 best_pd, cur_pd;
2738
9eaaf207
TV		 2739 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2740 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2741
2742 if (!is_tft)
2743 pcd_min = 3;
2744
80c39712
TV		 2745 best_pck = 0;
2746 best_ld = 0;
2747 best_pd = 0;
2748
2749 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2750 unsigned long lck = fck / cur_ld;
2751
9eaaf207 2752 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 2753 unsigned long pck = lck / cur_pd;
2754 long old_delta = abs(best_pck - req_pck);
2755 long new_delta = abs(pck - req_pck);
2756
2757 if (best_pck == 0 || new_delta < old_delta) {
2758 best_pck = pck;
2759 best_ld = cur_ld;
2760 best_pd = cur_pd;
2761
2762 if (pck == req_pck)
2763 goto found;
2764 }
2765
2766 if (pck < req_pck)
2767 break;
2768 }
2769
2770 if (lck / pcd_min < req_pck)
2771 break;
2772 }
2773
2774found:
2775 cinfo->lck_div = best_ld;
2776 cinfo->pck_div = best_pd;
2777 cinfo->lck = fck / cinfo->lck_div;
2778 cinfo->pck = cinfo->lck / cinfo->pck_div;
2779}
2780
2781/* calculate clock rates using dividers in cinfo */
2782int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2783 struct dispc_clock_info *cinfo)
2784{
2785 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2786 return -EINVAL;
9eaaf207 2787 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 2788 return -EINVAL;
2789
2790 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2791 cinfo->pck = cinfo->lck / cinfo->pck_div;
2792
2793 return 0;
2794}
2795
26d9dd0d 2796int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 2797 struct dispc_clock_info *cinfo)
80c39712
TV		 2798{
2799 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2800 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2801
26d9dd0d 2802 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2803
2804 return 0;
2805}
2806
26d9dd0d 2807int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 2808 struct dispc_clock_info *cinfo)
80c39712
TV		 2809{
2810 unsigned long fck;
2811
2812 fck = dispc_fclk_rate();
2813
ce7fa5eb
MR		 2814 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2815 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2816
2817 cinfo->lck = fck / cinfo->lck_div;
2818 cinfo->pck = cinfo->lck / cinfo->pck_div;
2819
2820 return 0;
2821}
2822
2823/* dispc.irq_lock has to be locked by the caller */
2824static void _omap_dispc_set_irqs(void)
2825{
2826 u32 mask;
2827 u32 old_mask;
2828 int i;
2829 struct omap_dispc_isr_data *isr_data;
2830
2831 mask = dispc.irq_error_mask;
2832
2833 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2834 isr_data = &dispc.registered_isr[i];
2835
2836 if (isr_data->isr == NULL)
2837 continue;
2838
2839 mask |= isr_data->mask;
2840 }
2841
80c39712
TV		 2842 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2843 /* clear the irqstatus for newly enabled irqs */
2844 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2845
2846 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 2847}
2848
2849int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2850{
2851 int i;
2852 int ret;
2853 unsigned long flags;
2854 struct omap_dispc_isr_data *isr_data;
2855
2856 if (isr == NULL)
2857 return -EINVAL;
2858
2859 spin_lock_irqsave(&dispc.irq_lock, flags);
2860
2861 /* check for duplicate entry */
2862 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2863 isr_data = &dispc.registered_isr[i];
2864 if (isr_data->isr == isr && isr_data->arg == arg &&
2865 isr_data->mask == mask) {
2866 ret = -EINVAL;
2867 goto err;
2868 }
2869 }
2870
2871 isr_data = NULL;
2872 ret = -EBUSY;
2873
2874 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2875 isr_data = &dispc.registered_isr[i];
2876
2877 if (isr_data->isr != NULL)
2878 continue;
2879
2880 isr_data->isr = isr;
2881 isr_data->arg = arg;
2882 isr_data->mask = mask;
2883 ret = 0;
2884
2885 break;
2886 }
2887
b9cb0984
TV		 2888 if (ret)
2889 goto err;
2890
80c39712
TV		 2891 _omap_dispc_set_irqs();
2892
2893 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2894
2895 return 0;
2896err:
2897 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2898
2899 return ret;
2900}
2901EXPORT_SYMBOL(omap_dispc_register_isr);
2902
2903int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2904{
2905 int i;
2906 unsigned long flags;
2907 int ret = -EINVAL;
2908 struct omap_dispc_isr_data *isr_data;
2909
2910 spin_lock_irqsave(&dispc.irq_lock, flags);
2911
2912 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2913 isr_data = &dispc.registered_isr[i];
2914 if (isr_data->isr != isr || isr_data->arg != arg ||
2915 isr_data->mask != mask)
2916 continue;
2917
2918 /* found the correct isr */
2919
2920 isr_data->isr = NULL;
2921 isr_data->arg = NULL;
2922 isr_data->mask = 0;
2923
2924 ret = 0;
2925 break;
2926 }
2927
2928 if (ret == 0)
2929 _omap_dispc_set_irqs();
2930
2931 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2932
2933 return ret;
2934}
2935EXPORT_SYMBOL(omap_dispc_unregister_isr);
2936
2937#ifdef DEBUG
2938static void print_irq_status(u32 status)
2939{
2940 if ((status & dispc.irq_error_mask) == 0)
2941 return;
2942
2943 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2944
2945#define PIS(x) \
2946 if (status & DISPC_IRQ_##x) \
2947 printk(#x " ");
2948 PIS(GFX_FIFO_UNDERFLOW);
2949 PIS(OCP_ERR);
2950 PIS(VID1_FIFO_UNDERFLOW);
2951 PIS(VID2_FIFO_UNDERFLOW);
2952 PIS(SYNC_LOST);
2953 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 2954 if (dss_has_feature(FEAT_MGR_LCD2))
2955 PIS(SYNC_LOST2);
80c39712
TV		 2956#undef PIS
2957
2958 printk("\n");
2959}
2960#endif
2961
2962/* Called from dss.c. Note that we don't touch clocks here,
2963 * but we presume they are on because we got an IRQ. However,
2964 * an irq handler may turn the clocks off, so we may not have
2965 * clock later in the function. */
affe360d 2966static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 2967{
2968 int i;
affe360d 2969 u32 irqstatus, irqenable;
80c39712
TV		 2970 u32 handledirqs = 0;
2971 u32 unhandled_errors;
2972 struct omap_dispc_isr_data *isr_data;
2973 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2974
2975 spin_lock(&dispc.irq_lock);
2976
2977 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 2978 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2979
2980 /* IRQ is not for us */
2981 if (!(irqstatus & irqenable)) {
2982 spin_unlock(&dispc.irq_lock);
2983 return IRQ_NONE;
2984 }
80c39712 2985
dfc0fd8d
TV		 2986#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2987 spin_lock(&dispc.irq_stats_lock);
2988 dispc.irq_stats.irq_count++;
2989 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2990 spin_unlock(&dispc.irq_stats_lock);
2991#endif
2992
80c39712
TV		 2993#ifdef DEBUG
2994 if (dss_debug)
2995 print_irq_status(irqstatus);
2996#endif
2997 /* Ack the interrupt. Do it here before clocks are possibly turned
2998 * off */
2999 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3000 /* flush posted write */
3001 dispc_read_reg(DISPC_IRQSTATUS);
3002
3003 /* make a copy and unlock, so that isrs can unregister
3004 * themselves */
3005 memcpy(registered_isr, dispc.registered_isr,
3006 sizeof(registered_isr));
3007
3008 spin_unlock(&dispc.irq_lock);
3009
3010 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3011 isr_data = &registered_isr[i];
3012
3013 if (!isr_data->isr)
3014 continue;
3015
3016 if (isr_data->mask & irqstatus) {
3017 isr_data->isr(isr_data->arg, irqstatus);
3018 handledirqs |= isr_data->mask;
3019 }
3020 }
3021
3022 spin_lock(&dispc.irq_lock);
3023
3024 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3025
3026 if (unhandled_errors) {
3027 dispc.error_irqs |= unhandled_errors;
3028
3029 dispc.irq_error_mask &= ~unhandled_errors;
3030 _omap_dispc_set_irqs();
3031
3032 schedule_work(&dispc.error_work);
3033 }
3034
3035 spin_unlock(&dispc.irq_lock);
affe360d 3036
3037 return IRQ_HANDLED;
80c39712
TV		 3038}
3039
3040static void dispc_error_worker(struct work_struct *work)
3041{
3042 int i;
3043 u32 errors;
3044 unsigned long flags;
fe3cc9d6
TV		 3045 static const unsigned fifo_underflow_bits[] = {
3046 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3047 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3048 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3049 };
3050
3051 static const unsigned sync_lost_bits[] = {
3052 DISPC_IRQ_SYNC_LOST,
3053 DISPC_IRQ_SYNC_LOST_DIGIT,
3054 DISPC_IRQ_SYNC_LOST2,
3055 };
80c39712
TV		 3056
3057 spin_lock_irqsave(&dispc.irq_lock, flags);
3058 errors = dispc.error_irqs;
3059 dispc.error_irqs = 0;
3060 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3061
13eae1f9
DZ		 3062 dispc_runtime_get();
3063
fe3cc9d6
TV		 3064 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3065 struct omap_overlay *ovl;
3066 unsigned bit;
80c39712 3067
fe3cc9d6
TV		 3068 ovl = omap_dss_get_overlay(i);
3069 bit = fifo_underflow_bits[i];
80c39712 3070
fe3cc9d6
TV		 3071 if (bit & errors) {
3072 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3073 ovl->name);
f0e5caab 3074 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3075 dispc_mgr_go(ovl->manager->id);
80c39712 3076 mdelay(50);
80c39712
TV		 3077 }
3078 }
3079
fe3cc9d6
TV		 3080 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3081 struct omap_overlay_manager *mgr;
3082 unsigned bit;
80c39712 3083
fe3cc9d6
TV		 3084 mgr = omap_dss_get_overlay_manager(i);
3085 bit = sync_lost_bits[i];
80c39712 3086
fe3cc9d6
TV		 3087 if (bit & errors) {
3088 struct omap_dss_device *dssdev = mgr->device;
3089 bool enable;
80c39712 3090
fe3cc9d6
TV		 3091 DSSERR("SYNC_LOST on channel %s, restarting the output "
3092 "with video overlays disabled\n",
3093 mgr->name);
2a205f34 3094
fe3cc9d6
TV		 3095 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3096 dssdev->driver->disable(dssdev);
2a205f34 3097
2a205f34
SS		 3098 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3099 struct omap_overlay *ovl;
3100 ovl = omap_dss_get_overlay(i);
3101
fe3cc9d6
TV		 3102 if (ovl->id != OMAP_DSS_GFX &&
3103 ovl->manager == mgr)
f0e5caab 3104 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3105 }
3106
26d9dd0d 3107 dispc_mgr_go(mgr->id);
2a205f34 3108 mdelay(50);
fe3cc9d6 3109
2a205f34
SS		 3110 if (enable)
3111 dssdev->driver->enable(dssdev);
3112 }
3113 }
3114
80c39712
TV		 3115 if (errors & DISPC_IRQ_OCP_ERR) {
3116 DSSERR("OCP_ERR\n");
3117 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3118 struct omap_overlay_manager *mgr;
3119 mgr = omap_dss_get_overlay_manager(i);
4a9e78ab 3120 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3121 }
3122 }
3123
3124 spin_lock_irqsave(&dispc.irq_lock, flags);
3125 dispc.irq_error_mask |= errors;
3126 _omap_dispc_set_irqs();
3127 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3128
3129 dispc_runtime_put();
80c39712
TV		 3130}
3131
3132int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3133{
3134 void dispc_irq_wait_handler(void *data, u32 mask)
3135 {
3136 complete((struct completion *)data);
3137 }
3138
3139 int r;
3140 DECLARE_COMPLETION_ONSTACK(completion);
3141
3142 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3143 irqmask);
3144
3145 if (r)
3146 return r;
3147
3148 timeout = wait_for_completion_timeout(&completion, timeout);
3149
3150 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3151
3152 if (timeout == 0)
3153 return -ETIMEDOUT;
3154
3155 if (timeout == -ERESTARTSYS)
3156 return -ERESTARTSYS;
3157
3158 return 0;
3159}
3160
3161int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3162 unsigned long timeout)
3163{
3164 void dispc_irq_wait_handler(void *data, u32 mask)
3165 {
3166 complete((struct completion *)data);
3167 }
3168
3169 int r;
3170 DECLARE_COMPLETION_ONSTACK(completion);
3171
3172 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3173 irqmask);
3174
3175 if (r)
3176 return r;
3177
3178 timeout = wait_for_completion_interruptible_timeout(&completion,
3179 timeout);
3180
3181 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3182
3183 if (timeout == 0)
3184 return -ETIMEDOUT;
3185
3186 if (timeout == -ERESTARTSYS)
3187 return -ERESTARTSYS;
3188
3189 return 0;
3190}
3191
3192#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3193void dispc_fake_vsync_irq(void)
3194{
3195 u32 irqstatus = DISPC_IRQ_VSYNC;
3196 int i;
3197
ab83b14c 3198 WARN_ON(!in_interrupt());
80c39712
TV		 3199
3200 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3201 struct omap_dispc_isr_data *isr_data;
3202 isr_data = &dispc.registered_isr[i];
3203
3204 if (!isr_data->isr)
3205 continue;
3206
3207 if (isr_data->mask & irqstatus)
3208 isr_data->isr(isr_data->arg, irqstatus);
3209 }
80c39712
TV		 3210}
3211#endif
3212
3213static void _omap_dispc_initialize_irq(void)
3214{
3215 unsigned long flags;
3216
3217 spin_lock_irqsave(&dispc.irq_lock, flags);
3218
3219 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3220
3221 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3222 if (dss_has_feature(FEAT_MGR_LCD2))
3223 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3224
3225 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3226 * so clear it */
3227 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3228
3229 _omap_dispc_set_irqs();
3230
3231 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3232}
3233
3234void dispc_enable_sidle(void)
3235{
3236 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3237}
3238
3239void dispc_disable_sidle(void)
3240{
3241 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3242}
3243
3244static void _omap_dispc_initial_config(void)
3245{
3246 u32 l;
3247
0cf35df3
MR		 3248 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3249 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3250 l = dispc_read_reg(DISPC_DIVISOR);
3251 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3252 l = FLD_MOD(l, 1, 0, 0);
3253 l = FLD_MOD(l, 1, 23, 16);
3254 dispc_write_reg(DISPC_DIVISOR, l);
3255 }
3256
80c39712 3257 /* FUNCGATED */
6ced40bf
AT		 3258 if (dss_has_feature(FEAT_FUNCGATED))
3259 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3260
3261 /* L3 firewall setting: enable access to OCM RAM */
3262 /* XXX this should be somewhere in plat-omap */
3263 if (cpu_is_omap24xx())
3264 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3265
3266 _dispc_setup_color_conv_coef();
3267
3268 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3269
3270 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3271
3272 dispc_configure_burst_sizes();
80c39712
TV		 3273}
3274
060b6d9c
SG		 3275/* DISPC HW IP initialisation */
3276static int omap_dispchw_probe(struct platform_device *pdev)
3277{
3278 u32 rev;
affe360d 3279 int r = 0;
ea9da36a 3280 struct resource *dispc_mem;
4fbafaf3 3281 struct clk *clk;
ea9da36a 3282
060b6d9c
SG		 3283 dispc.pdev = pdev;
3284
4fbafaf3
TV		 3285 clk = clk_get(&pdev->dev, "fck");
3286 if (IS_ERR(clk)) {
3287 DSSERR("can't get fck\n");
3288 r = PTR_ERR(clk);
3289 goto err_get_clk;
3290 }
3291
3292 dispc.dss_clk = clk;
3293
060b6d9c
SG		 3294 spin_lock_init(&dispc.irq_lock);
3295
3296#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3297 spin_lock_init(&dispc.irq_stats_lock);
3298 dispc.irq_stats.last_reset = jiffies;
3299#endif
3300
3301 INIT_WORK(&dispc.error_work, dispc_error_worker);
3302
ea9da36a
SG		 3303 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3304 if (!dispc_mem) {
3305 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3306 r = -EINVAL;
4fbafaf3 3307 goto err_ioremap;
ea9da36a
SG		 3308 }
3309 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3310 if (!dispc.base) {
3311 DSSERR("can't ioremap DISPC\n");
affe360d 3312 r = -ENOMEM;
4fbafaf3 3313 goto err_ioremap;
affe360d 3314 }
3315 dispc.irq = platform_get_irq(dispc.pdev, 0);
3316 if (dispc.irq < 0) {
3317 DSSERR("platform_get_irq failed\n");
3318 r = -ENODEV;
4fbafaf3 3319 goto err_irq;
affe360d 3320 }
3321
3322 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3323 "OMAP DISPC", dispc.pdev);
3324 if (r < 0) {
3325 DSSERR("request_irq failed\n");
4fbafaf3 3326 goto err_irq;
060b6d9c
SG		 3327 }
3328
4fbafaf3
TV		 3329 pm_runtime_enable(&pdev->dev);
3330
3331 r = dispc_runtime_get();
3332 if (r)
3333 goto err_runtime_get;
060b6d9c
SG		 3334
3335 _omap_dispc_initial_config();
3336
3337 _omap_dispc_initialize_irq();
3338
060b6d9c 3339 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3340 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3341 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3342
4fbafaf3 3343 dispc_runtime_put();
060b6d9c
SG		 3344
3345 return 0;
4fbafaf3
TV		 3346
3347err_runtime_get:
3348 pm_runtime_disable(&pdev->dev);
3349 free_irq(dispc.irq, dispc.pdev);
3350err_irq:
affe360d 3351 iounmap(dispc.base);
4fbafaf3
TV		 3352err_ioremap:
3353 clk_put(dispc.dss_clk);
3354err_get_clk:
affe360d 3355 return r;
060b6d9c
SG		 3356}
3357
3358static int omap_dispchw_remove(struct platform_device *pdev)
3359{
4fbafaf3
TV		 3360 pm_runtime_disable(&pdev->dev);
3361
3362 clk_put(dispc.dss_clk);
3363
affe360d 3364 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3365 iounmap(dispc.base);
3366 return 0;
3367}
3368
4fbafaf3
TV		 3369static int dispc_runtime_suspend(struct device *dev)
3370{
3371 dispc_save_context();
4fbafaf3
TV		 3372 dss_runtime_put();
3373
3374 return 0;
3375}
3376
3377static int dispc_runtime_resume(struct device *dev)
3378{
3379 int r;
3380
3381 r = dss_runtime_get();
3382 if (r < 0)
3383 return r;
3384
49ea86f3 3385 dispc_restore_context();
4fbafaf3
TV		 3386
3387 return 0;
3388}
3389
3390static const struct dev_pm_ops dispc_pm_ops = {
3391 .runtime_suspend = dispc_runtime_suspend,
3392 .runtime_resume = dispc_runtime_resume,
3393};
3394
060b6d9c
SG		 3395static struct platform_driver omap_dispchw_driver = {
3396 .probe = omap_dispchw_probe,
3397 .remove = omap_dispchw_remove,
3398 .driver = {
3399 .name = "omapdss_dispc",
3400 .owner = THIS_MODULE,
4fbafaf3 3401 .pm = &dispc_pm_ops,
060b6d9c
SG		 3402 },
3403};
3404
3405int dispc_init_platform_driver(void)
3406{
3407 return platform_driver_register(&omap_dispchw_driver);
3408}
3409
3410void dispc_uninit_platform_driver(void)
3411{
3412 return platform_driver_unregister(&omap_dispchw_driver);
3413}
Linux kernel - Deliverables
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