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OMAPDSS: Remove unused get_context_loss_count support
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
80c39712 39
a0b38cc4 40#include <video/omapdss.h>
80c39712
TV		 41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
9b372c2d 44#include "dispc.h"
80c39712
TV		 45
46/* DISPC */
8613b000 47#define DISPC_SZ_REGS SZ_4K
80c39712 48
5ed8cf5b
TV		 49enum omap_burst_size {
50 BURST_SIZE_X2 = 0,
51 BURST_SIZE_X4 = 1,
52 BURST_SIZE_X8 = 2,
53};
54
80c39712
TV		 55#define REG_GET(idx, start, end) \
56 FLD_GET(dispc_read_reg(idx), start, end)
57
58#define REG_FLD_MOD(idx, val, start, end) \
59 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
60
dcbe765b
CM		 61struct dispc_features {
62 u8 sw_start;
63 u8 fp_start;
64 u8 bp_start;
65 u16 sw_max;
66 u16 vp_max;
67 u16 hp_max;
33b89928
AT		 68 u8 mgr_width_start;
69 u8 mgr_height_start;
70 u16 mgr_width_max;
71 u16 mgr_height_max;
ca5ca69c
AT		 72 unsigned long max_lcd_pclk;
73 unsigned long max_tv_pclk;
0c6921de 74 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 75 const struct omap_video_timings *mgr_timings,
76 u16 width, u16 height, u16 out_width, u16 out_height,
77 enum omap_color_mode color_mode, bool *five_taps,
78 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 79 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 80 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 81 u16 width, u16 height, u16 out_width, u16 out_height,
82 bool mem_to_mem);
42a6961c 83 u8 num_fifos;
66a0f9e4
TV		 84
85 /* swap GFX & WB fifos */
86 bool gfx_fifo_workaround:1;
cffa947d
TV		 87
88 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
89 bool no_framedone_tv:1;
d0df9a2c
AT		 90
91 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
92 bool mstandby_workaround:1;
8bc65552
AT		 93
94 bool set_max_preload:1;
dcbe765b
CM		 95};
96
42a6961c
TV		 97#define DISPC_MAX_NR_FIFOS 5
98
80c39712 99static struct {
060b6d9c 100 struct platform_device *pdev;
80c39712 101 void __iomem *base;
4fbafaf3 102
affe360d 103 int irq;
80c39712 104
7b3926b3 105 unsigned long core_clk_rate;
5391e87d 106 unsigned long tv_pclk_rate;
7b3926b3 107
42a6961c
TV		 108 u32 fifo_size[DISPC_MAX_NR_FIFOS];
109 /* maps which plane is using a fifo. fifo-id -> plane-id */
110 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 111
49ea86f3 112 bool ctx_valid;
80c39712 113 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 114
dcbe765b 115 const struct dispc_features *feat;
80c39712
TV		 116} dispc;
117
0d66cbb5
AJ		 118enum omap_color_component {
119 /* used for all color formats for OMAP3 and earlier
120 * and for RGB and Y color component on OMAP4
121 */
122 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
123 /* used for UV component for
124 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
125 * color formats on OMAP4
126 */
127 DISPC_COLOR_COMPONENT_UV = 1 << 1,
128};
129
efa70b3b
CM		 130enum mgr_reg_fields {
131 DISPC_MGR_FLD_ENABLE,
132 DISPC_MGR_FLD_STNTFT,
133 DISPC_MGR_FLD_GO,
134 DISPC_MGR_FLD_TFTDATALINES,
135 DISPC_MGR_FLD_STALLMODE,
136 DISPC_MGR_FLD_TCKENABLE,
137 DISPC_MGR_FLD_TCKSELECTION,
138 DISPC_MGR_FLD_CPR,
139 DISPC_MGR_FLD_FIFOHANDCHECK,
140 /* used to maintain a count of the above fields */
141 DISPC_MGR_FLD_NUM,
142};
143
144static const struct {
145 const char *name;
146 u32 vsync_irq;
147 u32 framedone_irq;
148 u32 sync_lost_irq;
149 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
150} mgr_desc[] = {
151 [OMAP_DSS_CHANNEL_LCD] = {
152 .name = "LCD",
153 .vsync_irq = DISPC_IRQ_VSYNC,
154 .framedone_irq = DISPC_IRQ_FRAMEDONE,
155 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
156 .reg_desc = {
157 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
158 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
159 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
160 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
161 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
162 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
163 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
164 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
165 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
166 },
167 },
168 [OMAP_DSS_CHANNEL_DIGIT] = {
169 .name = "DIGIT",
170 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 171 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
173 .reg_desc = {
174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
175 [DISPC_MGR_FLD_STNTFT] = { },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
177 [DISPC_MGR_FLD_TFTDATALINES] = { },
178 [DISPC_MGR_FLD_STALLMODE] = { },
179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
181 [DISPC_MGR_FLD_CPR] = { },
182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
183 },
184 },
185 [OMAP_DSS_CHANNEL_LCD2] = {
186 .name = "LCD2",
187 .vsync_irq = DISPC_IRQ_VSYNC2,
188 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
190 .reg_desc = {
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
192 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
194 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
195 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
198 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
200 },
201 },
e86d456a
CM		 202 [OMAP_DSS_CHANNEL_LCD3] = {
203 .name = "LCD3",
204 .vsync_irq = DISPC_IRQ_VSYNC3,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
207 .reg_desc = {
208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
217 },
218 },
efa70b3b
CM		 219};
220
6e5264b0
AT		 221struct color_conv_coef {
222 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
223 int full_range;
224};
225
3e8a6ff2
AT		 226static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
227static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 228
55978cc2 229static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 230{
55978cc2 231 __raw_writel(val, dispc.base + idx);
80c39712
TV		 232}
233
55978cc2 234static inline u32 dispc_read_reg(const u16 idx)
80c39712 235{
55978cc2 236 return __raw_readl(dispc.base + idx);
80c39712
TV		 237}
238
efa70b3b
CM		 239static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
240{
241 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
242 return REG_GET(rfld.reg, rfld.high, rfld.low);
243}
244
245static void mgr_fld_write(enum omap_channel channel,
246 enum mgr_reg_fields regfld, int val) {
247 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
248 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
249}
250
80c39712 251#define SR(reg) \
55978cc2 252 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 253#define RR(reg) \
55978cc2 254 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 255
4fbafaf3 256static void dispc_save_context(void)
80c39712 257{
c6104b8e 258 int i, j;
80c39712 259
4fbafaf3
TV		 260 DSSDBG("dispc_save_context\n");
261
80c39712
TV		 262 SR(IRQENABLE);
263 SR(CONTROL);
264 SR(CONFIG);
80c39712 265 SR(LINE_NUMBER);
11354dd5
AT		 266 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
267 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 268 SR(GLOBAL_ALPHA);
2a205f34
SS		 269 if (dss_has_feature(FEAT_MGR_LCD2)) {
270 SR(CONTROL2);
2a205f34
SS		 271 SR(CONFIG2);
272 }
e86d456a
CM		 273 if (dss_has_feature(FEAT_MGR_LCD3)) {
274 SR(CONTROL3);
275 SR(CONFIG3);
276 }
80c39712 277
c6104b8e
AT		 278 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
279 SR(DEFAULT_COLOR(i));
280 SR(TRANS_COLOR(i));
281 SR(SIZE_MGR(i));
282 if (i == OMAP_DSS_CHANNEL_DIGIT)
283 continue;
284 SR(TIMING_H(i));
285 SR(TIMING_V(i));
286 SR(POL_FREQ(i));
287 SR(DIVISORo(i));
288
289 SR(DATA_CYCLE1(i));
290 SR(DATA_CYCLE2(i));
291 SR(DATA_CYCLE3(i));
292
332e9d70 293 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 294 SR(CPR_COEF_R(i));
295 SR(CPR_COEF_G(i));
296 SR(CPR_COEF_B(i));
332e9d70 297 }
2a205f34 298 }
80c39712 299
c6104b8e
AT		 300 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
301 SR(OVL_BA0(i));
302 SR(OVL_BA1(i));
303 SR(OVL_POSITION(i));
304 SR(OVL_SIZE(i));
305 SR(OVL_ATTRIBUTES(i));
306 SR(OVL_FIFO_THRESHOLD(i));
307 SR(OVL_ROW_INC(i));
308 SR(OVL_PIXEL_INC(i));
309 if (dss_has_feature(FEAT_PRELOAD))
310 SR(OVL_PRELOAD(i));
311 if (i == OMAP_DSS_GFX) {
312 SR(OVL_WINDOW_SKIP(i));
313 SR(OVL_TABLE_BA(i));
314 continue;
315 }
316 SR(OVL_FIR(i));
317 SR(OVL_PICTURE_SIZE(i));
318 SR(OVL_ACCU0(i));
319 SR(OVL_ACCU1(i));
9b372c2d 320
c6104b8e
AT		 321 for (j = 0; j < 8; j++)
322 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 323
c6104b8e
AT		 324 for (j = 0; j < 8; j++)
325 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 326
c6104b8e
AT		 327 for (j = 0; j < 5; j++)
328 SR(OVL_CONV_COEF(i, j));
ab5ca071 329
c6104b8e
AT		 330 if (dss_has_feature(FEAT_FIR_COEF_V)) {
331 for (j = 0; j < 8; j++)
332 SR(OVL_FIR_COEF_V(i, j));
333 }
9b372c2d 334
c6104b8e
AT		 335 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
336 SR(OVL_BA0_UV(i));
337 SR(OVL_BA1_UV(i));
338 SR(OVL_FIR2(i));
339 SR(OVL_ACCU2_0(i));
340 SR(OVL_ACCU2_1(i));
ab5ca071 341
c6104b8e
AT		 342 for (j = 0; j < 8; j++)
343 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 344
c6104b8e
AT		 345 for (j = 0; j < 8; j++)
346 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 347
c6104b8e
AT		 348 for (j = 0; j < 8; j++)
349 SR(OVL_FIR_COEF_V2(i, j));
350 }
351 if (dss_has_feature(FEAT_ATTR2))
352 SR(OVL_ATTRIBUTES2(i));
ab5ca071 353 }
0cf35df3
MR		 354
355 if (dss_has_feature(FEAT_CORE_CLK_DIV))
356 SR(DIVISOR);
49ea86f3 357
49ea86f3
TV		 358 dispc.ctx_valid = true;
359
9229b516 360 DSSDBG("context saved\n");
80c39712
TV		 361}
362
4fbafaf3 363static void dispc_restore_context(void)
80c39712 364{
9229b516 365 int i, j;
4fbafaf3
TV		 366
367 DSSDBG("dispc_restore_context\n");
368
49ea86f3
TV		 369 if (!dispc.ctx_valid)
370 return;
371
75c7d59d 372 /*RR(IRQENABLE);*/
80c39712
TV		 373 /*RR(CONTROL);*/
374 RR(CONFIG);
80c39712 375 RR(LINE_NUMBER);
11354dd5
AT		 376 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
377 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 378 RR(GLOBAL_ALPHA);
c6104b8e 379 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 380 RR(CONFIG2);
e86d456a
CM		 381 if (dss_has_feature(FEAT_MGR_LCD3))
382 RR(CONFIG3);
80c39712 383
c6104b8e
AT		 384 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
385 RR(DEFAULT_COLOR(i));
386 RR(TRANS_COLOR(i));
387 RR(SIZE_MGR(i));
388 if (i == OMAP_DSS_CHANNEL_DIGIT)
389 continue;
390 RR(TIMING_H(i));
391 RR(TIMING_V(i));
392 RR(POL_FREQ(i));
393 RR(DIVISORo(i));
394
395 RR(DATA_CYCLE1(i));
396 RR(DATA_CYCLE2(i));
397 RR(DATA_CYCLE3(i));
2a205f34 398
332e9d70 399 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 400 RR(CPR_COEF_R(i));
401 RR(CPR_COEF_G(i));
402 RR(CPR_COEF_B(i));
332e9d70 403 }
2a205f34 404 }
80c39712 405
c6104b8e
AT		 406 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
407 RR(OVL_BA0(i));
408 RR(OVL_BA1(i));
409 RR(OVL_POSITION(i));
410 RR(OVL_SIZE(i));
411 RR(OVL_ATTRIBUTES(i));
412 RR(OVL_FIFO_THRESHOLD(i));
413 RR(OVL_ROW_INC(i));
414 RR(OVL_PIXEL_INC(i));
415 if (dss_has_feature(FEAT_PRELOAD))
416 RR(OVL_PRELOAD(i));
417 if (i == OMAP_DSS_GFX) {
418 RR(OVL_WINDOW_SKIP(i));
419 RR(OVL_TABLE_BA(i));
420 continue;
421 }
422 RR(OVL_FIR(i));
423 RR(OVL_PICTURE_SIZE(i));
424 RR(OVL_ACCU0(i));
425 RR(OVL_ACCU1(i));
9b372c2d 426
c6104b8e
AT		 427 for (j = 0; j < 8; j++)
428 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 429
c6104b8e
AT		 430 for (j = 0; j < 8; j++)
431 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 432
c6104b8e
AT		 433 for (j = 0; j < 5; j++)
434 RR(OVL_CONV_COEF(i, j));
ab5ca071 435
c6104b8e
AT		 436 if (dss_has_feature(FEAT_FIR_COEF_V)) {
437 for (j = 0; j < 8; j++)
438 RR(OVL_FIR_COEF_V(i, j));
439 }
9b372c2d 440
c6104b8e
AT		 441 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
442 RR(OVL_BA0_UV(i));
443 RR(OVL_BA1_UV(i));
444 RR(OVL_FIR2(i));
445 RR(OVL_ACCU2_0(i));
446 RR(OVL_ACCU2_1(i));
ab5ca071 447
c6104b8e
AT		 448 for (j = 0; j < 8; j++)
449 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 450
c6104b8e
AT		 451 for (j = 0; j < 8; j++)
452 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 453
c6104b8e
AT		 454 for (j = 0; j < 8; j++)
455 RR(OVL_FIR_COEF_V2(i, j));
456 }
457 if (dss_has_feature(FEAT_ATTR2))
458 RR(OVL_ATTRIBUTES2(i));
ab5ca071 459 }
80c39712 460
0cf35df3
MR		 461 if (dss_has_feature(FEAT_CORE_CLK_DIV))
462 RR(DIVISOR);
463
80c39712
TV		 464 /* enable last, because LCD & DIGIT enable are here */
465 RR(CONTROL);
2a205f34
SS		 466 if (dss_has_feature(FEAT_MGR_LCD2))
467 RR(CONTROL2);
e86d456a
CM		 468 if (dss_has_feature(FEAT_MGR_LCD3))
469 RR(CONTROL3);
75c7d59d 470 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 471 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 472
473 /*
474 * enable last so IRQs won't trigger before
475 * the context is fully restored
476 */
477 RR(IRQENABLE);
49ea86f3
TV		 478
479 DSSDBG("context restored\n");
80c39712
TV		 480}
481
482#undef SR
483#undef RR
484
4fbafaf3
TV		 485int dispc_runtime_get(void)
486{
487 int r;
488
489 DSSDBG("dispc_runtime_get\n");
490
491 r = pm_runtime_get_sync(&dispc.pdev->dev);
492 WARN_ON(r < 0);
493 return r < 0 ? r : 0;
494}
348be69d 495EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 496
497void dispc_runtime_put(void)
498{
499 int r;
500
501 DSSDBG("dispc_runtime_put\n");
502
0eaf9f52 503 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 504 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 505}
348be69d 506EXPORT_SYMBOL(dispc_runtime_put);
80c39712 507
3dcec4d6
TV		 508u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
509{
efa70b3b 510 return mgr_desc[channel].vsync_irq;
3dcec4d6 511}
348be69d 512EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 513
7d1365c9
TV		 514u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
515{
cffa947d
TV		 516 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
517 return 0;
518
efa70b3b 519 return mgr_desc[channel].framedone_irq;
7d1365c9 520}
348be69d 521EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 522
cb699200
TV		 523u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
524{
525 return mgr_desc[channel].sync_lost_irq;
526}
348be69d 527EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 528
0b23e5b8
AT		 529u32 dispc_wb_get_framedone_irq(void)
530{
531 return DISPC_IRQ_FRAMEDONEWB;
532}
533
26d9dd0d 534bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 535{
efa70b3b 536 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 537}
348be69d 538EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 539
26d9dd0d 540void dispc_mgr_go(enum omap_channel channel)
80c39712 541{
3c91ee8c
TV		 542 WARN_ON(dispc_mgr_is_enabled(channel) == false);
543 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 544
efa70b3b 545 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 546
efa70b3b 547 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 548}
348be69d 549EXPORT_SYMBOL(dispc_mgr_go);
80c39712 550
0b23e5b8
AT		 551bool dispc_wb_go_busy(void)
552{
553 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
554}
555
556void dispc_wb_go(void)
557{
558 enum omap_plane plane = OMAP_DSS_WB;
559 bool enable, go;
560
561 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
562
563 if (!enable)
564 return;
565
566 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
567 if (go) {
568 DSSERR("GO bit not down for WB\n");
569 return;
570 }
571
572 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
573}
574
f0e5caab 575static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 576{
9b372c2d 577 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 578}
579
f0e5caab 580static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 581{
9b372c2d 582 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 583}
584
f0e5caab 585static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 586{
9b372c2d 587 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 588}
589
f0e5caab 590static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 591{
592 BUG_ON(plane == OMAP_DSS_GFX);
593
594 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
595}
596
f0e5caab
TV		 597static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
598 u32 value)
ab5ca071
AJ		 599{
600 BUG_ON(plane == OMAP_DSS_GFX);
601
602 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
603}
604
f0e5caab 605static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 606{
607 BUG_ON(plane == OMAP_DSS_GFX);
608
609 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
610}
611
debd9074
CM		 612static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
613 int fir_vinc, int five_taps,
614 enum omap_color_component color_comp)
80c39712 615{
debd9074 616 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 617 int i;
618
debd9074
CM		 619 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
620 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 621
622 for (i = 0; i < 8; i++) {
623 u32 h, hv;
624
debd9074
CM		 625 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
626 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
627 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
628 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
629 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
630 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
631 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
632 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 633
0d66cbb5 634 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 635 dispc_ovl_write_firh_reg(plane, i, h);
636 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 637 } else {
f0e5caab
TV		 638 dispc_ovl_write_firh2_reg(plane, i, h);
639 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 640 }
641
80c39712
TV		 642 }
643
66be8f6c
GI		 644 if (five_taps) {
645 for (i = 0; i < 8; i++) {
646 u32 v;
debd9074
CM		 647 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
648 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 649 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 650 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 651 else
f0e5caab 652 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 653 }
80c39712
TV		 654 }
655}
656
80c39712 657
6e5264b0
AT		 658static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
659 const struct color_conv_coef *ct)
660{
80c39712
TV		 661#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
662
6e5264b0
AT		 663 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
664 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
665 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
667 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 668
6e5264b0 669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 670
671#undef CVAL
80c39712
TV		 672}
673
6e5264b0
AT		 674static void dispc_setup_color_conv_coef(void)
675{
676 int i;
677 int num_ovl = dss_feat_get_num_ovls();
678 int num_wb = dss_feat_get_num_wbs();
679 const struct color_conv_coef ctbl_bt601_5_ovl = {
680 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
681 };
682 const struct color_conv_coef ctbl_bt601_5_wb = {
683 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
684 };
685
686 for (i = 1; i < num_ovl; i++)
687 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
688
689 for (; i < num_wb; i++)
690 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
691}
80c39712 692
f0e5caab 693static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 694{
9b372c2d 695 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 696}
697
f0e5caab 698static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 699{
9b372c2d 700 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 701}
702
f0e5caab 703static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 704{
705 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
706}
707
f0e5caab 708static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 709{
710 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
711}
712
d79db853
AT		 713static void dispc_ovl_set_pos(enum omap_plane plane,
714 enum omap_overlay_caps caps, int x, int y)
80c39712 715{
d79db853
AT		 716 u32 val;
717
718 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
719 return;
720
721 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 722
723 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 724}
725
78b687fc
AT		 726static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
727 int height)
80c39712 728{
80c39712 729 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 730
36d87d95 731 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 732 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
733 else
734 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 735}
736
78b687fc
AT		 737static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
738 int height)
80c39712
TV		 739{
740 u32 val;
80c39712
TV		 741
742 BUG_ON(plane == OMAP_DSS_GFX);
743
744 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 745
36d87d95
AT		 746 if (plane == OMAP_DSS_WB)
747 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
748 else
749 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 750}
751
5b54ed3e
AT		 752static void dispc_ovl_set_zorder(enum omap_plane plane,
753 enum omap_overlay_caps caps, u8 zorder)
54128701 754{
5b54ed3e 755 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 756 return;
757
758 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
759}
760
761static void dispc_ovl_enable_zorder_planes(void)
762{
763 int i;
764
765 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
766 return;
767
768 for (i = 0; i < dss_feat_get_num_ovls(); i++)
769 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
770}
771
5b54ed3e
AT		 772static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
773 enum omap_overlay_caps caps, bool enable)
fd28a390 774{
5b54ed3e 775 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 776 return;
777
9b372c2d 778 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 779}
780
5b54ed3e
AT		 781static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
782 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 783{
b8c095b4 784 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 785 int shift;
786
5b54ed3e 787 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 788 return;
a0acb557 789
fe3cc9d6
TV		 790 shift = shifts[plane];
791 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 792}
793
f0e5caab 794static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 795{
9b372c2d 796 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 797}
798
f0e5caab 799static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 800{
9b372c2d 801 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 802}
803
f0e5caab 804static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 805 enum omap_color_mode color_mode)
806{
807 u32 m = 0;
f20e4220
AJ		 808 if (plane != OMAP_DSS_GFX) {
809 switch (color_mode) {
810 case OMAP_DSS_COLOR_NV12:
811 m = 0x0; break;
08f3267e 812 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 813 m = 0x1; break;
814 case OMAP_DSS_COLOR_RGBA16:
815 m = 0x2; break;
08f3267e 816 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 817 m = 0x4; break;
818 case OMAP_DSS_COLOR_ARGB16:
819 m = 0x5; break;
820 case OMAP_DSS_COLOR_RGB16:
821 m = 0x6; break;
822 case OMAP_DSS_COLOR_ARGB16_1555:
823 m = 0x7; break;
824 case OMAP_DSS_COLOR_RGB24U:
825 m = 0x8; break;
826 case OMAP_DSS_COLOR_RGB24P:
827 m = 0x9; break;
828 case OMAP_DSS_COLOR_YUV2:
829 m = 0xa; break;
830 case OMAP_DSS_COLOR_UYVY:
831 m = 0xb; break;
832 case OMAP_DSS_COLOR_ARGB32:
833 m = 0xc; break;
834 case OMAP_DSS_COLOR_RGBA32:
835 m = 0xd; break;
836 case OMAP_DSS_COLOR_RGBX32:
837 m = 0xe; break;
838 case OMAP_DSS_COLOR_XRGB16_1555:
839 m = 0xf; break;
840 default:
c6eee968 841 BUG(); return;
f20e4220
AJ		 842 }
843 } else {
844 switch (color_mode) {
845 case OMAP_DSS_COLOR_CLUT1:
846 m = 0x0; break;
847 case OMAP_DSS_COLOR_CLUT2:
848 m = 0x1; break;
849 case OMAP_DSS_COLOR_CLUT4:
850 m = 0x2; break;
851 case OMAP_DSS_COLOR_CLUT8:
852 m = 0x3; break;
853 case OMAP_DSS_COLOR_RGB12U:
854 m = 0x4; break;
855 case OMAP_DSS_COLOR_ARGB16:
856 m = 0x5; break;
857 case OMAP_DSS_COLOR_RGB16:
858 m = 0x6; break;
859 case OMAP_DSS_COLOR_ARGB16_1555:
860 m = 0x7; break;
861 case OMAP_DSS_COLOR_RGB24U:
862 m = 0x8; break;
863 case OMAP_DSS_COLOR_RGB24P:
864 m = 0x9; break;
08f3267e 865 case OMAP_DSS_COLOR_RGBX16:
f20e4220 866 m = 0xa; break;
08f3267e 867 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 868 m = 0xb; break;
869 case OMAP_DSS_COLOR_ARGB32:
870 m = 0xc; break;
871 case OMAP_DSS_COLOR_RGBA32:
872 m = 0xd; break;
873 case OMAP_DSS_COLOR_RGBX32:
874 m = 0xe; break;
875 case OMAP_DSS_COLOR_XRGB16_1555:
876 m = 0xf; break;
877 default:
c6eee968 878 BUG(); return;
f20e4220 879 }
80c39712
TV		 880 }
881
9b372c2d 882 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 883}
884
65e006ff
CM		 885static void dispc_ovl_configure_burst_type(enum omap_plane plane,
886 enum omap_dss_rotation_type rotation_type)
887{
888 if (dss_has_feature(FEAT_BURST_2D) == 0)
889 return;
890
891 if (rotation_type == OMAP_DSS_ROT_TILER)
892 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
893 else
894 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
895}
896
f427984e 897void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 898{
899 int shift;
900 u32 val;
2a205f34 901 int chan = 0, chan2 = 0;
80c39712
TV		 902
903 switch (plane) {
904 case OMAP_DSS_GFX:
905 shift = 8;
906 break;
907 case OMAP_DSS_VIDEO1:
908 case OMAP_DSS_VIDEO2:
b8c095b4 909 case OMAP_DSS_VIDEO3:
80c39712
TV		 910 shift = 16;
911 break;
912 default:
913 BUG();
914 return;
915 }
916
9b372c2d 917 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 918 if (dss_has_feature(FEAT_MGR_LCD2)) {
919 switch (channel) {
920 case OMAP_DSS_CHANNEL_LCD:
921 chan = 0;
922 chan2 = 0;
923 break;
924 case OMAP_DSS_CHANNEL_DIGIT:
925 chan = 1;
926 chan2 = 0;
927 break;
928 case OMAP_DSS_CHANNEL_LCD2:
929 chan = 0;
930 chan2 = 1;
931 break;
e86d456a
CM		 932 case OMAP_DSS_CHANNEL_LCD3:
933 if (dss_has_feature(FEAT_MGR_LCD3)) {
934 chan = 0;
935 chan2 = 2;
936 } else {
937 BUG();
938 return;
939 }
940 break;
2a205f34
SS		 941 default:
942 BUG();
c6eee968 943 return;
2a205f34
SS		 944 }
945
946 val = FLD_MOD(val, chan, shift, shift);
947 val = FLD_MOD(val, chan2, 31, 30);
948 } else {
949 val = FLD_MOD(val, channel, shift, shift);
950 }
9b372c2d 951 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 952}
348be69d 953EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 954
2cc5d1af
TV		 955static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
956{
957 int shift;
958 u32 val;
959 enum omap_channel channel;
960
961 switch (plane) {
962 case OMAP_DSS_GFX:
963 shift = 8;
964 break;
965 case OMAP_DSS_VIDEO1:
966 case OMAP_DSS_VIDEO2:
967 case OMAP_DSS_VIDEO3:
968 shift = 16;
969 break;
970 default:
971 BUG();
c6eee968 972 return 0;
2cc5d1af
TV		 973 }
974
975 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
976
e86d456a
CM		 977 if (dss_has_feature(FEAT_MGR_LCD3)) {
978 if (FLD_GET(val, 31, 30) == 0)
979 channel = FLD_GET(val, shift, shift);
980 else if (FLD_GET(val, 31, 30) == 1)
981 channel = OMAP_DSS_CHANNEL_LCD2;
982 else
983 channel = OMAP_DSS_CHANNEL_LCD3;
984 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 985 if (FLD_GET(val, 31, 30) == 0)
986 channel = FLD_GET(val, shift, shift);
987 else
988 channel = OMAP_DSS_CHANNEL_LCD2;
989 } else {
990 channel = FLD_GET(val, shift, shift);
991 }
992
993 return channel;
994}
995
d9ac773c
AT		 996void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
997{
998 enum omap_plane plane = OMAP_DSS_WB;
999
1000 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1001}
1002
f0e5caab 1003static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1004 enum omap_burst_size burst_size)
1005{
8bbe09ee 1006 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1007 int shift;
80c39712 1008
fe3cc9d6 1009 shift = shifts[plane];
5ed8cf5b 1010 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1011}
1012
5ed8cf5b
TV		 1013static void dispc_configure_burst_sizes(void)
1014{
1015 int i;
1016 const int burst_size = BURST_SIZE_X8;
1017
1018 /* Configure burst size always to maximum size */
392faa0e 1019 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1020 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1021}
1022
83fa2f2e 1023static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1024{
1025 unsigned unit = dss_feat_get_burst_size_unit();
1026 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1027 return unit * 8;
1028}
1029
d3862610
M		 1030void dispc_enable_gamma_table(bool enable)
1031{
1032 /*
1033 * This is partially implemented to support only disabling of
1034 * the gamma table.
1035 */
1036 if (enable) {
1037 DSSWARN("Gamma table enabling for TV not yet supported");
1038 return;
1039 }
1040
1041 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1042}
1043
c64dca40 1044static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1045{
efa70b3b 1046 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1047 return;
1048
efa70b3b 1049 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1050}
1051
c64dca40 1052static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1053 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1054{
1055 u32 coef_r, coef_g, coef_b;
1056
dd88b7a6 1057 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1058 return;
1059
1060 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1061 FLD_VAL(coefs->rb, 9, 0);
1062 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1063 FLD_VAL(coefs->gb, 9, 0);
1064 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1065 FLD_VAL(coefs->bb, 9, 0);
1066
1067 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1068 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1069 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1070}
1071
f0e5caab 1072static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1073{
1074 u32 val;
1075
1076 BUG_ON(plane == OMAP_DSS_GFX);
1077
9b372c2d 1078 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1079 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1080 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1081}
1082
d79db853
AT		 1083static void dispc_ovl_enable_replication(enum omap_plane plane,
1084 enum omap_overlay_caps caps, bool enable)
80c39712 1085{
b8c095b4 1086 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1087 int shift;
80c39712 1088
d79db853
AT		 1089 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1090 return;
1091
fe3cc9d6
TV		 1092 shift = shifts[plane];
1093 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1094}
1095
8f366162 1096static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1097 u16 height)
80c39712
TV		 1098{
1099 u32 val;
80c39712 1100
33b89928
AT		 1101 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1102 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1103
8f366162 1104 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1105}
1106
42a6961c 1107static void dispc_init_fifos(void)
80c39712 1108{
80c39712 1109 u32 size;
42a6961c 1110 int fifo;
a0acb557 1111 u8 start, end;
5ed8cf5b
TV		 1112 u32 unit;
1113
1114 unit = dss_feat_get_buffer_size_unit();
80c39712 1115
a0acb557 1116 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1117
42a6961c
TV		 1118 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1119 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1120 size *= unit;
42a6961c
TV		 1121 dispc.fifo_size[fifo] = size;
1122
1123 /*
1124 * By default fifos are mapped directly to overlays, fifo 0 to
1125 * ovl 0, fifo 1 to ovl 1, etc.
1126 */
1127 dispc.fifo_assignment[fifo] = fifo;
80c39712 1128 }
66a0f9e4
TV		 1129
1130 /*
1131 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1132 * causes problems with certain use cases, like using the tiler in 2D
1133 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1134 * giving GFX plane a larger fifo. WB but should work fine with a
1135 * smaller fifo.
1136 */
1137 if (dispc.feat->gfx_fifo_workaround) {
1138 u32 v;
1139
1140 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1141
1142 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1143 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1144 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1145 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1146
1147 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1148
1149 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1150 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1151 }
80c39712
TV		 1152}
1153
83fa2f2e 1154static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1155{
42a6961c
TV		 1156 int fifo;
1157 u32 size = 0;
1158
1159 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1160 if (dispc.fifo_assignment[fifo] == plane)
1161 size += dispc.fifo_size[fifo];
1162 }
1163
1164 return size;
80c39712
TV		 1165}
1166
6f04e1bf 1167void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1168{
a0acb557 1169 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1170 u32 unit;
1171
1172 unit = dss_feat_get_buffer_size_unit();
1173
1174 WARN_ON(low % unit != 0);
1175 WARN_ON(high % unit != 0);
1176
1177 low /= unit;
1178 high /= unit;
a0acb557 1179
9b372c2d
AT		 1180 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1181 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1182
3cb5d966 1183 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1184 plane,
9b372c2d 1185 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1186 lo_start, lo_end) * unit,
9b372c2d 1187 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1188 hi_start, hi_end) * unit,
1189 low * unit, high * unit);
80c39712 1190
9b372c2d 1191 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1192 FLD_VAL(high, hi_start, hi_end) |
1193 FLD_VAL(low, lo_start, lo_end));
8bc65552
AT		 1194
1195 /*
1196 * configure the preload to the pipeline's high threhold, if HT it's too
1197 * large for the preload field, set the threshold to the maximum value
1198 * that can be held by the preload register
1199 */
1200 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1201 plane != OMAP_DSS_WB)
1202 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
80c39712 1203}
8ee5c842 1204EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
80c39712
TV		 1205
1206void dispc_enable_fifomerge(bool enable)
1207{
e6b0f884
TV		 1208 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1209 WARN_ON(enable);
1210 return;
1211 }
1212
80c39712
TV		 1213 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1214 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1215}
1216
83fa2f2e 1217void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1218 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1219 bool manual_update)
83fa2f2e
TV		 1220{
1221 /*
1222 * All sizes are in bytes. Both the buffer and burst are made of
1223 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1224 */
1225
1226 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1227 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1228 int i;
83fa2f2e
TV		 1229
1230 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1231 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1232
e0e405b9
TV		 1233 if (use_fifomerge) {
1234 total_fifo_size = 0;
392faa0e 1235 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1236 total_fifo_size += dispc_ovl_get_fifo_size(i);
1237 } else {
1238 total_fifo_size = ovl_fifo_size;
1239 }
1240
1241 /*
1242 * We use the same low threshold for both fifomerge and non-fifomerge
1243 * cases, but for fifomerge we calculate the high threshold using the
1244 * combined fifo size
1245 */
1246
3568f2a4 1247 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1248 *fifo_low = ovl_fifo_size - burst_size * 2;
1249 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1250 } else if (plane == OMAP_DSS_WB) {
1251 /*
1252 * Most optimal configuration for writeback is to push out data
1253 * to the interconnect the moment writeback pushes enough pixels
1254 * in the FIFO to form a burst
1255 */
1256 *fifo_low = 0;
1257 *fifo_high = burst_size;
e0e405b9
TV		 1258 } else {
1259 *fifo_low = ovl_fifo_size - burst_size;
1260 *fifo_high = total_fifo_size - buf_unit;
1261 }
83fa2f2e 1262}
8ee5c842 1263EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
83fa2f2e 1264
f0e5caab 1265static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1266 int hinc, int vinc,
1267 enum omap_color_component color_comp)
80c39712
TV		 1268{
1269 u32 val;
80c39712 1270
0d66cbb5
AJ		 1271 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1272 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1273
0d66cbb5
AJ		 1274 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1275 &hinc_start, &hinc_end);
1276 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1277 &vinc_start, &vinc_end);
1278 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1279 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1280
0d66cbb5
AJ		 1281 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1282 } else {
1283 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1284 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1285 }
80c39712
TV		 1286}
1287
f0e5caab 1288static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1289{
1290 u32 val;
87a7484b 1291 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1292
87a7484b
AT		 1293 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1294 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1295
1296 val = FLD_VAL(vaccu, vert_start, vert_end) |
1297 FLD_VAL(haccu, hor_start, hor_end);
1298
9b372c2d 1299 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1300}
1301
f0e5caab 1302static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1303{
1304 u32 val;
87a7484b 1305 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1306
87a7484b
AT		 1307 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1308 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1309
1310 val = FLD_VAL(vaccu, vert_start, vert_end) |
1311 FLD_VAL(haccu, hor_start, hor_end);
1312
9b372c2d 1313 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1314}
1315
f0e5caab
TV		 1316static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1317 int vaccu)
ab5ca071
AJ		 1318{
1319 u32 val;
1320
1321 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1322 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1323}
1324
f0e5caab
TV		 1325static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1326 int vaccu)
ab5ca071
AJ		 1327{
1328 u32 val;
1329
1330 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1331 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1332}
80c39712 1333
f0e5caab 1334static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1335 u16 orig_width, u16 orig_height,
1336 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1337 bool five_taps, u8 rotation,
1338 enum omap_color_component color_comp)
80c39712 1339{
0d66cbb5 1340 int fir_hinc, fir_vinc;
80c39712 1341
ed14a3ce
AJ		 1342 fir_hinc = 1024 * orig_width / out_width;
1343 fir_vinc = 1024 * orig_height / out_height;
80c39712 1344
debd9074
CM		 1345 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1346 color_comp);
f0e5caab 1347 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1348}
1349
05dd0f53
CM		 1350static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1351 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1352 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1353{
1354 int h_accu2_0, h_accu2_1;
1355 int v_accu2_0, v_accu2_1;
1356 int chroma_hinc, chroma_vinc;
1357 int idx;
1358
1359 struct accu {
1360 s8 h0_m, h0_n;
1361 s8 h1_m, h1_n;
1362 s8 v0_m, v0_n;
1363 s8 v1_m, v1_n;
1364 };
1365
1366 const struct accu *accu_table;
1367 const struct accu *accu_val;
1368
1369 static const struct accu accu_nv12[4] = {
1370 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1371 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1372 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1373 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1374 };
1375
1376 static const struct accu accu_nv12_ilace[4] = {
1377 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1378 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1379 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1380 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1381 };
1382
1383 static const struct accu accu_yuv[4] = {
1384 { 0, 1, 0, 1, 0, 1, 0, 1 },
1385 { 0, 1, 0, 1, 0, 1, 0, 1 },
1386 { -1, 1, 0, 1, 0, 1, 0, 1 },
1387 { 0, 1, 0, 1, -1, 1, 0, 1 },
1388 };
1389
1390 switch (rotation) {
1391 case OMAP_DSS_ROT_0:
1392 idx = 0;
1393 break;
1394 case OMAP_DSS_ROT_90:
1395 idx = 1;
1396 break;
1397 case OMAP_DSS_ROT_180:
1398 idx = 2;
1399 break;
1400 case OMAP_DSS_ROT_270:
1401 idx = 3;
1402 break;
1403 default:
1404 BUG();
c6eee968 1405 return;
05dd0f53
CM		 1406 }
1407
1408 switch (color_mode) {
1409 case OMAP_DSS_COLOR_NV12:
1410 if (ilace)
1411 accu_table = accu_nv12_ilace;
1412 else
1413 accu_table = accu_nv12;
1414 break;
1415 case OMAP_DSS_COLOR_YUV2:
1416 case OMAP_DSS_COLOR_UYVY:
1417 accu_table = accu_yuv;
1418 break;
1419 default:
1420 BUG();
c6eee968 1421 return;
05dd0f53
CM		 1422 }
1423
1424 accu_val = &accu_table[idx];
1425
1426 chroma_hinc = 1024 * orig_width / out_width;
1427 chroma_vinc = 1024 * orig_height / out_height;
1428
1429 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1430 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1431 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1432 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1433
1434 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1435 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1436}
1437
f0e5caab 1438static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1439 u16 orig_width, u16 orig_height,
1440 u16 out_width, u16 out_height,
1441 bool ilace, bool five_taps,
1442 bool fieldmode, enum omap_color_mode color_mode,
1443 u8 rotation)
1444{
1445 int accu0 = 0;
1446 int accu1 = 0;
1447 u32 l;
80c39712 1448
f0e5caab 1449 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1450 out_width, out_height, five_taps,
1451 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1452 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1453
87a7484b
AT		 1454 /* RESIZEENABLE and VERTICALTAPS */
1455 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1456 l |= (orig_width != out_width) ? (1 << 5) : 0;
1457 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1458 l |= five_taps ? (1 << 21) : 0;
80c39712 1459
87a7484b
AT		 1460 /* VRESIZECONF and HRESIZECONF */
1461 if (dss_has_feature(FEAT_RESIZECONF)) {
1462 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1463 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1464 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1465 }
80c39712 1466
87a7484b
AT		 1467 /* LINEBUFFERSPLIT */
1468 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1469 l &= ~(0x1 << 22);
1470 l |= five_taps ? (1 << 22) : 0;
1471 }
80c39712 1472
9b372c2d 1473 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1474
1475 /*
1476 * field 0 = even field = bottom field
1477 * field 1 = odd field = top field
1478 */
1479 if (ilace && !fieldmode) {
1480 accu1 = 0;
0d66cbb5 1481 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1482 if (accu0 >= 1024/2) {
1483 accu1 = 1024/2;
1484 accu0 -= accu1;
1485 }
1486 }
1487
f0e5caab
TV		 1488 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1489 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1490}
1491
f0e5caab 1492static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1493 u16 orig_width, u16 orig_height,
1494 u16 out_width, u16 out_height,
1495 bool ilace, bool five_taps,
1496 bool fieldmode, enum omap_color_mode color_mode,
1497 u8 rotation)
1498{
1499 int scale_x = out_width != orig_width;
1500 int scale_y = out_height != orig_height;
f92afae2 1501 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1502
1503 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1504 return;
1505 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1506 color_mode != OMAP_DSS_COLOR_UYVY &&
1507 color_mode != OMAP_DSS_COLOR_NV12)) {
1508 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1509 if (plane != OMAP_DSS_WB)
1510 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1511 return;
1512 }
36377357
TV		 1513
1514 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1515 out_height, ilace, color_mode, rotation);
1516
0d66cbb5
AJ		 1517 switch (color_mode) {
1518 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1519 if (chroma_upscale) {
1520 /* UV is subsampled by 2 horizontally and vertically */
1521 orig_height >>= 1;
1522 orig_width >>= 1;
1523 } else {
1524 /* UV is downsampled by 2 horizontally and vertically */
1525 orig_height <<= 1;
1526 orig_width <<= 1;
1527 }
1528
0d66cbb5
AJ		 1529 break;
1530 case OMAP_DSS_COLOR_YUV2:
1531 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1532 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1533 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1534 rotation == OMAP_DSS_ROT_180) {
1535 if (chroma_upscale)
1536 /* UV is subsampled by 2 horizontally */
1537 orig_width >>= 1;
1538 else
1539 /* UV is downsampled by 2 horizontally */
1540 orig_width <<= 1;
1541 }
1542
0d66cbb5
AJ		 1543 /* must use FIR for YUV422 if rotated */
1544 if (rotation != OMAP_DSS_ROT_0)
1545 scale_x = scale_y = true;
20fbb50b 1546
0d66cbb5
AJ		 1547 break;
1548 default:
1549 BUG();
c6eee968 1550 return;
0d66cbb5
AJ		 1551 }
1552
1553 if (out_width != orig_width)
1554 scale_x = true;
1555 if (out_height != orig_height)
1556 scale_y = true;
1557
f0e5caab 1558 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1559 out_width, out_height, five_taps,
1560 rotation, DISPC_COLOR_COMPONENT_UV);
1561
2a5561b1
AT		 1562 if (plane != OMAP_DSS_WB)
1563 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1564 (scale_x || scale_y) ? 1 : 0, 8, 8);
1565
0d66cbb5
AJ		 1566 /* set H scaling */
1567 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1568 /* set V scaling */
1569 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1570}
1571
f0e5caab 1572static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1573 u16 orig_width, u16 orig_height,
1574 u16 out_width, u16 out_height,
1575 bool ilace, bool five_taps,
1576 bool fieldmode, enum omap_color_mode color_mode,
1577 u8 rotation)
1578{
1579 BUG_ON(plane == OMAP_DSS_GFX);
1580
f0e5caab 1581 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1582 orig_width, orig_height,
1583 out_width, out_height,
1584 ilace, five_taps,
1585 fieldmode, color_mode,
1586 rotation);
1587
f0e5caab 1588 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1589 orig_width, orig_height,
1590 out_width, out_height,
1591 ilace, five_taps,
1592 fieldmode, color_mode,
1593 rotation);
1594}
1595
f0e5caab 1596static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1597 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1598 bool mirroring, enum omap_color_mode color_mode)
1599{
87a7484b
AT		 1600 bool row_repeat = false;
1601 int vidrot = 0;
1602
80c39712
TV		 1603 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1604 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1605
1606 if (mirroring) {
1607 switch (rotation) {
1608 case OMAP_DSS_ROT_0:
1609 vidrot = 2;
1610 break;
1611 case OMAP_DSS_ROT_90:
1612 vidrot = 1;
1613 break;
1614 case OMAP_DSS_ROT_180:
1615 vidrot = 0;
1616 break;
1617 case OMAP_DSS_ROT_270:
1618 vidrot = 3;
1619 break;
1620 }
1621 } else {
1622 switch (rotation) {
1623 case OMAP_DSS_ROT_0:
1624 vidrot = 0;
1625 break;
1626 case OMAP_DSS_ROT_90:
1627 vidrot = 1;
1628 break;
1629 case OMAP_DSS_ROT_180:
1630 vidrot = 2;
1631 break;
1632 case OMAP_DSS_ROT_270:
1633 vidrot = 3;
1634 break;
1635 }
1636 }
1637
80c39712 1638 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1639 row_repeat = true;
80c39712 1640 else
87a7484b 1641 row_repeat = false;
80c39712 1642 }
87a7484b 1643
9b372c2d 1644 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1645 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1646 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1647 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1648
1649 if (color_mode == OMAP_DSS_COLOR_NV12) {
1650 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1651 (rotation == OMAP_DSS_ROT_0 ||
1652 rotation == OMAP_DSS_ROT_180);
1653 /* DOUBLESTRIDE */
1654 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1655 }
1656
80c39712
TV		 1657}
1658
1659static int color_mode_to_bpp(enum omap_color_mode color_mode)
1660{
1661 switch (color_mode) {
1662 case OMAP_DSS_COLOR_CLUT1:
1663 return 1;
1664 case OMAP_DSS_COLOR_CLUT2:
1665 return 2;
1666 case OMAP_DSS_COLOR_CLUT4:
1667 return 4;
1668 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1669 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1670 return 8;
1671 case OMAP_DSS_COLOR_RGB12U:
1672 case OMAP_DSS_COLOR_RGB16:
1673 case OMAP_DSS_COLOR_ARGB16:
1674 case OMAP_DSS_COLOR_YUV2:
1675 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1676 case OMAP_DSS_COLOR_RGBA16:
1677 case OMAP_DSS_COLOR_RGBX16:
1678 case OMAP_DSS_COLOR_ARGB16_1555:
1679 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1680 return 16;
1681 case OMAP_DSS_COLOR_RGB24P:
1682 return 24;
1683 case OMAP_DSS_COLOR_RGB24U:
1684 case OMAP_DSS_COLOR_ARGB32:
1685 case OMAP_DSS_COLOR_RGBA32:
1686 case OMAP_DSS_COLOR_RGBX32:
1687 return 32;
1688 default:
1689 BUG();
c6eee968 1690 return 0;
80c39712
TV		 1691 }
1692}
1693
1694static s32 pixinc(int pixels, u8 ps)
1695{
1696 if (pixels == 1)
1697 return 1;
1698 else if (pixels > 1)
1699 return 1 + (pixels - 1) * ps;
1700 else if (pixels < 0)
1701 return 1 - (-pixels + 1) * ps;
1702 else
1703 BUG();
c6eee968 1704 return 0;
80c39712
TV		 1705}
1706
1707static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1708 u16 screen_width,
1709 u16 width, u16 height,
1710 enum omap_color_mode color_mode, bool fieldmode,
1711 unsigned int field_offset,
1712 unsigned *offset0, unsigned *offset1,
aed74b55 1713 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1714{
1715 u8 ps;
1716
1717 /* FIXME CLUT formats */
1718 switch (color_mode) {
1719 case OMAP_DSS_COLOR_CLUT1:
1720 case OMAP_DSS_COLOR_CLUT2:
1721 case OMAP_DSS_COLOR_CLUT4:
1722 case OMAP_DSS_COLOR_CLUT8:
1723 BUG();
1724 return;
1725 case OMAP_DSS_COLOR_YUV2:
1726 case OMAP_DSS_COLOR_UYVY:
1727 ps = 4;
1728 break;
1729 default:
1730 ps = color_mode_to_bpp(color_mode) / 8;
1731 break;
1732 }
1733
1734 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1735 width, height);
1736
1737 /*
1738 * field 0 = even field = bottom field
1739 * field 1 = odd field = top field
1740 */
1741 switch (rotation + mirror * 4) {
1742 case OMAP_DSS_ROT_0:
1743 case OMAP_DSS_ROT_180:
1744 /*
1745 * If the pixel format is YUV or UYVY divide the width
1746 * of the image by 2 for 0 and 180 degree rotation.
1747 */
1748 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1749 color_mode == OMAP_DSS_COLOR_UYVY)
1750 width = width >> 1;
1751 case OMAP_DSS_ROT_90:
1752 case OMAP_DSS_ROT_270:
1753 *offset1 = 0;
1754 if (field_offset)
1755 *offset0 = field_offset * screen_width * ps;
1756 else
1757 *offset0 = 0;
1758
aed74b55
CM		 1759 *row_inc = pixinc(1 +
1760 (y_predecim * screen_width - x_predecim * width) +
1761 (fieldmode ? screen_width : 0), ps);
1762 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1763 break;
1764
1765 case OMAP_DSS_ROT_0 + 4:
1766 case OMAP_DSS_ROT_180 + 4:
1767 /* If the pixel format is YUV or UYVY divide the width
1768 * of the image by 2 for 0 degree and 180 degree
1769 */
1770 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1771 color_mode == OMAP_DSS_COLOR_UYVY)
1772 width = width >> 1;
1773 case OMAP_DSS_ROT_90 + 4:
1774 case OMAP_DSS_ROT_270 + 4:
1775 *offset1 = 0;
1776 if (field_offset)
1777 *offset0 = field_offset * screen_width * ps;
1778 else
1779 *offset0 = 0;
aed74b55
CM		 1780 *row_inc = pixinc(1 -
1781 (y_predecim * screen_width + x_predecim * width) -
1782 (fieldmode ? screen_width : 0), ps);
1783 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1784 break;
1785
1786 default:
1787 BUG();
c6eee968 1788 return;
80c39712
TV		 1789 }
1790}
1791
1792static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1793 u16 screen_width,
1794 u16 width, u16 height,
1795 enum omap_color_mode color_mode, bool fieldmode,
1796 unsigned int field_offset,
1797 unsigned *offset0, unsigned *offset1,
aed74b55 1798 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1799{
1800 u8 ps;
1801 u16 fbw, fbh;
1802
1803 /* FIXME CLUT formats */
1804 switch (color_mode) {
1805 case OMAP_DSS_COLOR_CLUT1:
1806 case OMAP_DSS_COLOR_CLUT2:
1807 case OMAP_DSS_COLOR_CLUT4:
1808 case OMAP_DSS_COLOR_CLUT8:
1809 BUG();
1810 return;
1811 default:
1812 ps = color_mode_to_bpp(color_mode) / 8;
1813 break;
1814 }
1815
1816 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1817 width, height);
1818
1819 /* width & height are overlay sizes, convert to fb sizes */
1820
1821 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1822 fbw = width;
1823 fbh = height;
1824 } else {
1825 fbw = height;
1826 fbh = width;
1827 }
1828
1829 /*
1830 * field 0 = even field = bottom field
1831 * field 1 = odd field = top field
1832 */
1833 switch (rotation + mirror * 4) {
1834 case OMAP_DSS_ROT_0:
1835 *offset1 = 0;
1836 if (field_offset)
1837 *offset0 = *offset1 + field_offset * screen_width * ps;
1838 else
1839 *offset0 = *offset1;
aed74b55
CM		 1840 *row_inc = pixinc(1 +
1841 (y_predecim * screen_width - fbw * x_predecim) +
1842 (fieldmode ? screen_width : 0), ps);
1843 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1844 color_mode == OMAP_DSS_COLOR_UYVY)
1845 *pix_inc = pixinc(x_predecim, 2 * ps);
1846 else
1847 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1848 break;
1849 case OMAP_DSS_ROT_90:
1850 *offset1 = screen_width * (fbh - 1) * ps;
1851 if (field_offset)
1852 *offset0 = *offset1 + field_offset * ps;
1853 else
1854 *offset0 = *offset1;
aed74b55
CM		 1855 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1856 y_predecim + (fieldmode ? 1 : 0), ps);
1857 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1858 break;
1859 case OMAP_DSS_ROT_180:
1860 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1861 if (field_offset)
1862 *offset0 = *offset1 - field_offset * screen_width * ps;
1863 else
1864 *offset0 = *offset1;
1865 *row_inc = pixinc(-1 -
aed74b55
CM		 1866 (y_predecim * screen_width - fbw * x_predecim) -
1867 (fieldmode ? screen_width : 0), ps);
1868 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1869 color_mode == OMAP_DSS_COLOR_UYVY)
1870 *pix_inc = pixinc(-x_predecim, 2 * ps);
1871 else
1872 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1873 break;
1874 case OMAP_DSS_ROT_270:
1875 *offset1 = (fbw - 1) * ps;
1876 if (field_offset)
1877 *offset0 = *offset1 - field_offset * ps;
1878 else
1879 *offset0 = *offset1;
aed74b55
CM		 1880 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1881 y_predecim - (fieldmode ? 1 : 0), ps);
1882 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1883 break;
1884
1885 /* mirroring */
1886 case OMAP_DSS_ROT_0 + 4:
1887 *offset1 = (fbw - 1) * ps;
1888 if (field_offset)
1889 *offset0 = *offset1 + field_offset * screen_width * ps;
1890 else
1891 *offset0 = *offset1;
aed74b55 1892 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1893 (fieldmode ? screen_width : 0),
1894 ps);
aed74b55
CM		 1895 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1896 color_mode == OMAP_DSS_COLOR_UYVY)
1897 *pix_inc = pixinc(-x_predecim, 2 * ps);
1898 else
1899 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1900 break;
1901
1902 case OMAP_DSS_ROT_90 + 4:
1903 *offset1 = 0;
1904 if (field_offset)
1905 *offset0 = *offset1 + field_offset * ps;
1906 else
1907 *offset0 = *offset1;
aed74b55
CM		 1908 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1909 y_predecim + (fieldmode ? 1 : 0),
80c39712 1910 ps);
aed74b55 1911 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1912 break;
1913
1914 case OMAP_DSS_ROT_180 + 4:
1915 *offset1 = screen_width * (fbh - 1) * ps;
1916 if (field_offset)
1917 *offset0 = *offset1 - field_offset * screen_width * ps;
1918 else
1919 *offset0 = *offset1;
aed74b55 1920 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1921 (fieldmode ? screen_width : 0),
1922 ps);
aed74b55
CM		 1923 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1924 color_mode == OMAP_DSS_COLOR_UYVY)
1925 *pix_inc = pixinc(x_predecim, 2 * ps);
1926 else
1927 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1928 break;
1929
1930 case OMAP_DSS_ROT_270 + 4:
1931 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1932 if (field_offset)
1933 *offset0 = *offset1 - field_offset * ps;
1934 else
1935 *offset0 = *offset1;
aed74b55
CM		 1936 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1937 y_predecim - (fieldmode ? 1 : 0),
80c39712 1938 ps);
aed74b55 1939 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1940 break;
1941
1942 default:
1943 BUG();
c6eee968 1944 return;
80c39712
TV		 1945 }
1946}
1947
65e006ff
CM		 1948static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1949 enum omap_color_mode color_mode, bool fieldmode,
1950 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1951 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1952{
1953 u8 ps;
1954
1955 switch (color_mode) {
1956 case OMAP_DSS_COLOR_CLUT1:
1957 case OMAP_DSS_COLOR_CLUT2:
1958 case OMAP_DSS_COLOR_CLUT4:
1959 case OMAP_DSS_COLOR_CLUT8:
1960 BUG();
1961 return;
1962 default:
1963 ps = color_mode_to_bpp(color_mode) / 8;
1964 break;
1965 }
1966
1967 DSSDBG("scrw %d, width %d\n", screen_width, width);
1968
1969 /*
1970 * field 0 = even field = bottom field
1971 * field 1 = odd field = top field
1972 */
1973 *offset1 = 0;
1974 if (field_offset)
1975 *offset0 = *offset1 + field_offset * screen_width * ps;
1976 else
1977 *offset0 = *offset1;
1978 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1979 (fieldmode ? screen_width : 0), ps);
1980 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1981 color_mode == OMAP_DSS_COLOR_UYVY)
1982 *pix_inc = pixinc(x_predecim, 2 * ps);
1983 else
1984 *pix_inc = pixinc(x_predecim, ps);
1985}
1986
7faa9233
CM		 1987/*
1988 * This function is used to avoid synclosts in OMAP3, because of some
1989 * undocumented horizontal position and timing related limitations.
1990 */
465ec13f 1991static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 1992 const struct omap_video_timings *t, u16 pos_x,
e4998634
ID		 1993 u16 width, u16 height, u16 out_width, u16 out_height,
1994 bool five_taps)
7faa9233 1995{
230edc03 1996 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 1997 unsigned long nonactive;
7faa9233
CM		 1998 static const u8 limits[3] = { 8, 10, 20 };
1999 u64 val, blank;
2000 int i;
2001
81ab95b7 2002 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2003
2004 i = 0;
2005 if (out_height < height)
2006 i++;
2007 if (out_width < width)
2008 i++;
81ab95b7 2009 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2010 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2011 if (blank <= limits[i])
2012 return -EINVAL;
2013
e4998634
ID		 2014 /* FIXME add checks for 3-tap filter once the limitations are known */
2015 if (!five_taps)
2016 return 0;
2017
7faa9233
CM		 2018 /*
2019 * Pixel data should be prepared before visible display point starts.
2020 * So, atleast DS-2 lines must have already been fetched by DISPC
2021 * during nonactive - pos_x period.
2022 */
2023 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2024 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2025 val, max(0, ds - 2) * width);
2026 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2027 return -EINVAL;
2028
2029 /*
2030 * All lines need to be refilled during the nonactive period of which
2031 * only one line can be loaded during the active period. So, atleast
2032 * DS - 1 lines should be loaded during nonactive period.
2033 */
2034 val = div_u64((u64)nonactive * lclk, pclk);
2035 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2036 val, max(0, ds - 1) * width);
2037 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2038 return -EINVAL;
2039
2040 return 0;
2041}
2042
8702ee50 2043static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2044 const struct omap_video_timings *mgr_timings, u16 width,
2045 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2046 enum omap_color_mode color_mode)
80c39712 2047{
8b53d991 2048 u32 core_clk = 0;
3e8a6ff2 2049 u64 tmp;
80c39712 2050
7282f1b7
CM		 2051 if (height <= out_height && width <= out_width)
2052 return (unsigned long) pclk;
2053
80c39712 2054 if (height > out_height) {
81ab95b7 2055 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2056
2057 tmp = pclk * height * out_width;
2058 do_div(tmp, 2 * out_height * ppl);
8b53d991 2059 core_clk = tmp;
80c39712 2060
2d9c5597
VS		 2061 if (height > 2 * out_height) {
2062 if (ppl == out_width)
2063 return 0;
2064
80c39712
TV		 2065 tmp = pclk * (height - 2 * out_height) * out_width;
2066 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2067 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2068 }
2069 }
2070
2071 if (width > out_width) {
2072 tmp = pclk * width;
2073 do_div(tmp, out_width);
8b53d991 2074 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2075
2076 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2077 core_clk <<= 1;
80c39712
TV		 2078 }
2079
8b53d991 2080 return core_clk;
80c39712
TV		 2081}
2082
8702ee50 2083static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2084 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2085{
dcbe765b
CM		 2086 if (height > out_height && width > out_width)
2087 return pclk * 4;
2088 else
2089 return pclk * 2;
2090}
2091
8702ee50 2092static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2093 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2094{
2095 unsigned int hf, vf;
2096
2097 /*
2098 * FIXME how to determine the 'A' factor
2099 * for the no downscaling case ?
2100 */
2101
2102 if (width > 3 * out_width)
2103 hf = 4;
2104 else if (width > 2 * out_width)
2105 hf = 3;
2106 else if (width > out_width)
2107 hf = 2;
2108 else
2109 hf = 1;
80c39712
TV		 2110 if (height > out_height)
2111 vf = 2;
2112 else
2113 vf = 1;
2114
dcbe765b
CM		 2115 return pclk * vf * hf;
2116}
2117
8702ee50 2118static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2119 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2120{
8ba85306
AT		 2121 /*
2122 * If the overlay/writeback is in mem to mem mode, there are no
2123 * downscaling limitations with respect to pixel clock, return 1 as
2124 * required core clock to represent that we have sufficient enough
2125 * core clock to do maximum downscaling
2126 */
2127 if (mem_to_mem)
2128 return 1;
2129
dcbe765b
CM		 2130 if (width > out_width)
2131 return DIV_ROUND_UP(pclk, out_width) * width;
2132 else
2133 return pclk;
2134}
2135
0c6921de 2136static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2137 const struct omap_video_timings *mgr_timings,
2138 u16 width, u16 height, u16 out_width, u16 out_height,
2139 enum omap_color_mode color_mode, bool *five_taps,
2140 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2141 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2142{
2143 int error;
2144 u16 in_width, in_height;
2145 int min_factor = min(*decim_x, *decim_y);
2146 const int maxsinglelinewidth =
2147 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2148
dcbe765b
CM		 2149 *five_taps = false;
2150
2151 do {
2152 in_height = DIV_ROUND_UP(height, *decim_y);
2153 in_width = DIV_ROUND_UP(width, *decim_x);
8702ee50 2154 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2155 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2156 error = (in_width > maxsinglelinewidth || !*core_clk ||
2157 *core_clk > dispc_core_clk_rate());
2158 if (error) {
2159 if (*decim_x == *decim_y) {
2160 *decim_x = min_factor;
2161 ++*decim_y;
2162 } else {
2163 swap(*decim_x, *decim_y);
2164 if (*decim_x < *decim_y)
2165 ++*decim_x;
2166 }
2167 }
2168 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2169
2170 if (in_width > maxsinglelinewidth) {
2171 DSSERR("Cannot scale max input width exceeded");
2172 return -EINVAL;
2173 }
2174 return 0;
2175}
2176
0c6921de 2177static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2178 const struct omap_video_timings *mgr_timings,
2179 u16 width, u16 height, u16 out_width, u16 out_height,
2180 enum omap_color_mode color_mode, bool *five_taps,
2181 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2182 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2183{
2184 int error;
2185 u16 in_width, in_height;
2186 int min_factor = min(*decim_x, *decim_y);
2187 const int maxsinglelinewidth =
2188 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2189
2190 do {
2191 in_height = DIV_ROUND_UP(height, *decim_y);
2192 in_width = DIV_ROUND_UP(width, *decim_x);
e4998634 2193 *five_taps = in_height > out_height;
dcbe765b
CM		 2194
2195 if (in_width > maxsinglelinewidth)
2196 if (in_height > out_height &&
2197 in_height < out_height * 2)
2198 *five_taps = false;
e4998634
ID		 2199again:
2200 if (*five_taps)
2201 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2202 in_width, in_height, out_width,
2203 out_height, color_mode);
2204 else
8702ee50 2205 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2206 in_height, out_width, out_height,
2207 mem_to_mem);
dcbe765b 2208
e4998634
ID		 2209 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2210 pos_x, in_width, in_height, out_width,
2211 out_height, *five_taps);
2212 if (error && *five_taps) {
2213 *five_taps = false;
2214 goto again;
2215 }
2216
dcbe765b
CM		 2217 error = (error || in_width > maxsinglelinewidth * 2 ||
2218 (in_width > maxsinglelinewidth && *five_taps) ||
2219 !*core_clk || *core_clk > dispc_core_clk_rate());
2220 if (error) {
2221 if (*decim_x == *decim_y) {
2222 *decim_x = min_factor;
2223 ++*decim_y;
2224 } else {
2225 swap(*decim_x, *decim_y);
2226 if (*decim_x < *decim_y)
2227 ++*decim_x;
2228 }
2229 }
2230 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2231
465ec13f 2232 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
e4998634 2233 height, out_width, out_height, *five_taps)) {
dcbe765b
CM		 2234 DSSERR("horizontal timing too tight\n");
2235 return -EINVAL;
7282f1b7 2236 }
dcbe765b
CM		 2237
2238 if (in_width > (maxsinglelinewidth * 2)) {
2239 DSSERR("Cannot setup scaling");
2240 DSSERR("width exceeds maximum width possible");
2241 return -EINVAL;
2242 }
2243
2244 if (in_width > maxsinglelinewidth && *five_taps) {
2245 DSSERR("cannot setup scaling with five taps");
2246 return -EINVAL;
2247 }
2248 return 0;
2249}
2250
0c6921de 2251static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2252 const struct omap_video_timings *mgr_timings,
2253 u16 width, u16 height, u16 out_width, u16 out_height,
2254 enum omap_color_mode color_mode, bool *five_taps,
2255 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2256 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2257{
2258 u16 in_width, in_width_max;
2259 int decim_x_min = *decim_x;
2260 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2261 const int maxsinglelinewidth =
2262 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2263 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2264
5d501085
AT		 2265 if (mem_to_mem) {
2266 in_width_max = out_width * maxdownscale;
2267 } else {
8ba85306
AT		 2268 in_width_max = dispc_core_clk_rate() /
2269 DIV_ROUND_UP(pclk, out_width);
5d501085 2270 }
dcbe765b 2271
dcbe765b
CM		 2272 *decim_x = DIV_ROUND_UP(width, in_width_max);
2273
2274 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2275 if (*decim_x > *x_predecim)
2276 return -EINVAL;
2277
2278 do {
2279 in_width = DIV_ROUND_UP(width, *decim_x);
2280 } while (*decim_x <= *x_predecim &&
2281 in_width > maxsinglelinewidth && ++*decim_x);
2282
2283 if (in_width > maxsinglelinewidth) {
2284 DSSERR("Cannot scale width exceeds max line width");
2285 return -EINVAL;
2286 }
2287
8702ee50 2288 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2289 out_width, out_height, mem_to_mem);
dcbe765b 2290 return 0;
80c39712
TV		 2291}
2292
74e16458 2293static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2294 enum omap_overlay_caps caps,
81ab95b7
AT		 2295 const struct omap_video_timings *mgr_timings,
2296 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2297 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2298 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2299 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2300{
0373cac6 2301 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2302 const int max_decim_limit = 16;
8b53d991 2303 unsigned long core_clk = 0;
dcbe765b 2304 int decim_x, decim_y, ret;
79ad75f2 2305
f95cb5eb
TV		 2306 if (width == out_width && height == out_height)
2307 return 0;
2308
5b54ed3e 2309 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2310 return -EINVAL;
79ad75f2 2311
74e16458 2312 if (mem_to_mem) {
1c031441
AT		 2313 *x_predecim = *y_predecim = 1;
2314 } else {
2315 *x_predecim = max_decim_limit;
2316 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2317 dss_has_feature(FEAT_BURST_2D)) ?
2318 2 : max_decim_limit;
2319 }
aed74b55
CM		 2320
2321 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2322 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2323 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2324 color_mode == OMAP_DSS_COLOR_CLUT8) {
2325 *x_predecim = 1;
2326 *y_predecim = 1;
2327 *five_taps = false;
2328 return 0;
2329 }
2330
2331 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2332 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2333
aed74b55 2334 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2335 return -EINVAL;
2336
aed74b55 2337 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2338 return -EINVAL;
2339
0c6921de 2340 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2341 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2342 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2343 mem_to_mem);
dcbe765b
CM		 2344 if (ret)
2345 return ret;
79ad75f2 2346
8b53d991
CM		 2347 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2348 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2349
8b53d991 2350 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2351 DSSERR("failed to set up scaling, "
8b53d991
CM		 2352 "required core clk rate = %lu Hz, "
2353 "current core clk rate = %lu Hz\n",
2354 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2355 return -EINVAL;
2356 }
2357
aed74b55
CM		 2358 *x_predecim = decim_x;
2359 *y_predecim = decim_y;
79ad75f2
AT		 2360 return 0;
2361}
2362
f9b719b6
TV		 2363int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2364 const struct omap_overlay_info *oi,
2365 const struct omap_video_timings *timings,
2366 int *x_predecim, int *y_predecim)
2367{
2368 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2369 bool five_taps = true;
62a83183 2370 bool fieldmode = false;
f9b719b6
TV		 2371 u16 in_height = oi->height;
2372 u16 in_width = oi->width;
2373 bool ilace = timings->interlace;
2374 u16 out_width, out_height;
2375 int pos_x = oi->pos_x;
2376 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2377 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2378
2379 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2380 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2381
2382 if (ilace && oi->height == out_height)
62a83183 2383 fieldmode = true;
f9b719b6
TV		 2384
2385 if (ilace) {
2386 if (fieldmode)
2387 in_height /= 2;
2388 out_height /= 2;
2389
2390 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2391 in_height, out_height);
2392 }
2393
2394 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2395 return -EINVAL;
2396
2397 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2398 in_height, out_width, out_height, oi->color_mode,
2399 &five_taps, x_predecim, y_predecim, pos_x,
2400 oi->rotation_type, false);
2401}
348be69d 2402EXPORT_SYMBOL(dispc_ovl_check);
f9b719b6 2403
84a880fd 2404static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2405 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2406 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2407 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2408 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2409 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2410 bool replication, const struct omap_video_timings *mgr_timings,
2411 bool mem_to_mem)
80c39712 2412{
7282f1b7 2413 bool five_taps = true;
62a83183 2414 bool fieldmode = false;
79ad75f2 2415 int r, cconv = 0;
80c39712
TV		 2416 unsigned offset0, offset1;
2417 s32 row_inc;
2418 s32 pix_inc;
6be0d73e 2419 u16 frame_width, frame_height;
80c39712 2420 unsigned int field_offset = 0;
84a880fd
AT		 2421 u16 in_height = height;
2422 u16 in_width = width;
aed74b55 2423 int x_predecim = 1, y_predecim = 1;
8050cbe4 2424 bool ilace = mgr_timings->interlace;
74e16458
TV		 2425 unsigned long pclk = dispc_plane_pclk_rate(plane);
2426 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2427
84a880fd 2428 if (paddr == 0)
80c39712
TV		 2429 return -EINVAL;
2430
84a880fd
AT		 2431 out_width = out_width == 0 ? width : out_width;
2432 out_height = out_height == 0 ? height : out_height;
cf073668 2433
84a880fd 2434 if (ilace && height == out_height)
62a83183 2435 fieldmode = true;
80c39712
TV		 2436
2437 if (ilace) {
2438 if (fieldmode)
aed74b55 2439 in_height /= 2;
8eeb7019 2440 pos_y /= 2;
aed74b55 2441 out_height /= 2;
80c39712
TV		 2442
2443 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2444 "out_height %d\n", in_height, pos_y,
2445 out_height);
80c39712
TV		 2446 }
2447
84a880fd 2448 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2449 return -EINVAL;
2450
74e16458 2451 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2452 in_height, out_width, out_height, color_mode,
2453 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2454 rotation_type, mem_to_mem);
79ad75f2
AT		 2455 if (r)
2456 return r;
80c39712 2457
aed74b55
CM		 2458 in_width = DIV_ROUND_UP(in_width, x_predecim);
2459 in_height = DIV_ROUND_UP(in_height, y_predecim);
2460
84a880fd
AT		 2461 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2462 color_mode == OMAP_DSS_COLOR_UYVY ||
2463 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2464 cconv = 1;
80c39712
TV		 2465
2466 if (ilace && !fieldmode) {
2467 /*
2468 * when downscaling the bottom field may have to start several
2469 * source lines below the top field. Unfortunately ACCUI
2470 * registers will only hold the fractional part of the offset
2471 * so the integer part must be added to the base address of the
2472 * bottom field.
2473 */
aed74b55 2474 if (!in_height || in_height == out_height)
80c39712
TV		 2475 field_offset = 0;
2476 else
aed74b55 2477 field_offset = in_height / out_height / 2;
80c39712
TV		 2478 }
2479
2480 /* Fields are independent but interleaved in memory. */
2481 if (fieldmode)
2482 field_offset = 1;
2483
c6eee968
TV		 2484 offset0 = 0;
2485 offset1 = 0;
2486 row_inc = 0;
2487 pix_inc = 0;
2488
6be0d73e
AT		 2489 if (plane == OMAP_DSS_WB) {
2490 frame_width = out_width;
2491 frame_height = out_height;
2492 } else {
2493 frame_width = in_width;
2494 frame_height = height;
2495 }
2496
84a880fd 2497 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2498 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2499 color_mode, fieldmode, field_offset,
65e006ff
CM		 2500 &offset0, &offset1, &row_inc, &pix_inc,
2501 x_predecim, y_predecim);
84a880fd 2502 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2503 calc_dma_rotation_offset(rotation, mirror, screen_width,
2504 frame_width, frame_height,
84a880fd 2505 color_mode, fieldmode, field_offset,
aed74b55
CM		 2506 &offset0, &offset1, &row_inc, &pix_inc,
2507 x_predecim, y_predecim);
80c39712 2508 else
84a880fd 2509 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2510 screen_width, frame_width, frame_height,
84a880fd 2511 color_mode, fieldmode, field_offset,
aed74b55
CM		 2512 &offset0, &offset1, &row_inc, &pix_inc,
2513 x_predecim, y_predecim);
80c39712
TV		 2514
2515 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2516 offset0, offset1, row_inc, pix_inc);
2517
84a880fd 2518 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2519
84a880fd 2520 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2521
84a880fd
AT		 2522 dispc_ovl_set_ba0(plane, paddr + offset0);
2523 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2524
84a880fd
AT		 2525 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2526 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2527 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2528 }
2529
f0e5caab
TV		 2530 dispc_ovl_set_row_inc(plane, row_inc);
2531 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2532
84a880fd 2533 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2534 in_height, out_width, out_height);
80c39712 2535
84a880fd 2536 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2537
78b687fc 2538 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2539
5b54ed3e 2540 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2541 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2542 out_height, ilace, five_taps, fieldmode,
84a880fd 2543 color_mode, rotation);
78b687fc 2544 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2545 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2546 }
2547
c35eeb2e
AT		 2548 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2549 color_mode);
80c39712 2550
84a880fd
AT		 2551 dispc_ovl_set_zorder(plane, caps, zorder);
2552 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2553 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2554
d79db853 2555 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2556
80c39712
TV		 2557 return 0;
2558}
2559
84a880fd 2560int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2561 bool replication, const struct omap_video_timings *mgr_timings,
2562 bool mem_to_mem)
84a880fd
AT		 2563{
2564 int r;
16bf20c7 2565 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2566 enum omap_channel channel;
2567
2568 channel = dispc_ovl_get_channel_out(plane);
2569
2570 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2571 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2572 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2573 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2574 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2575
16bf20c7 2576 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2577 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2578 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2579 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2580 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2581
2582 return r;
2583}
348be69d 2584EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2585
749feffa 2586int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2587 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2588{
2589 int r;
9e4a0fc7 2590 u32 l;
749feffa
AT		 2591 enum omap_plane plane = OMAP_DSS_WB;
2592 const int pos_x = 0, pos_y = 0;
2593 const u8 zorder = 0, global_alpha = 0;
2594 const bool replication = false;
9e4a0fc7 2595 bool truncation;
749feffa
AT		 2596 int in_width = mgr_timings->x_res;
2597 int in_height = mgr_timings->y_res;
2598 enum omap_overlay_caps caps =
2599 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2600
2601 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2602 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2603 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2604 wi->mirror);
2605
2606 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2607 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2608 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2609 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2610 replication, mgr_timings, mem_to_mem);
2611
2612 switch (wi->color_mode) {
2613 case OMAP_DSS_COLOR_RGB16:
2614 case OMAP_DSS_COLOR_RGB24P:
2615 case OMAP_DSS_COLOR_ARGB16:
2616 case OMAP_DSS_COLOR_RGBA16:
2617 case OMAP_DSS_COLOR_RGB12U:
2618 case OMAP_DSS_COLOR_ARGB16_1555:
2619 case OMAP_DSS_COLOR_XRGB16_1555:
2620 case OMAP_DSS_COLOR_RGBX16:
2621 truncation = true;
2622 break;
2623 default:
2624 truncation = false;
2625 break;
2626 }
2627
2628 /* setup extra DISPC_WB_ATTRIBUTES */
2629 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2630 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2631 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2632 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2633
2634 return r;
2635}
2636
f0e5caab 2637int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2638{
e6d80f95
TV		 2639 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2640
9b372c2d 2641 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2642
2643 return 0;
80c39712 2644}
348be69d 2645EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2646
04bd8ac1
TV		 2647bool dispc_ovl_enabled(enum omap_plane plane)
2648{
2649 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2650}
348be69d 2651EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2652
f1a813d3 2653void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2654{
efa70b3b
CM		 2655 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2656 /* flush posted write */
2657 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2658}
348be69d 2659EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2660
65398511
TV		 2661bool dispc_mgr_is_enabled(enum omap_channel channel)
2662{
2663 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2664}
348be69d 2665EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2666
0b23e5b8
AT		 2667void dispc_wb_enable(bool enable)
2668{
916188a4 2669 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2670}
2671
2672bool dispc_wb_is_enabled(void)
2673{
916188a4 2674 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2675}
2676
fb2cec1f 2677static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2678{
6ced40bf
AT		 2679 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2680 return;
2681
80c39712 2682 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2683}
2684
2685void dispc_lcd_enable_signal(bool enable)
2686{
6ced40bf
AT		 2687 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2688 return;
2689
80c39712 2690 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2691}
2692
2693void dispc_pck_free_enable(bool enable)
2694{
6ced40bf
AT		 2695 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2696 return;
2697
80c39712 2698 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2699}
2700
fb2cec1f 2701static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2702{
efa70b3b 2703 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2704}
2705
2706
fb2cec1f 2707static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2708{
d21f43bc 2709 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2710}
2711
2712void dispc_set_loadmode(enum omap_dss_load_mode mode)
2713{
80c39712 2714 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2715}
2716
2717
c64dca40 2718static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2719{
8613b000 2720 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2721}
2722
c64dca40 2723static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2724 enum omap_dss_trans_key_type type,
2725 u32 trans_key)
2726{
efa70b3b 2727 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2728
8613b000 2729 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2730}
2731
c64dca40 2732static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2733{
efa70b3b 2734 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2735}
11354dd5 2736
c64dca40
TV		 2737static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2738 bool enable)
80c39712 2739{
11354dd5 2740 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2741 return;
2742
80c39712
TV		 2743 if (ch == OMAP_DSS_CHANNEL_LCD)
2744 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2745 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2746 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2747}
11354dd5 2748
c64dca40 2749void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2750 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2751{
2752 dispc_mgr_set_default_color(channel, info->default_color);
2753 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2754 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2755 dispc_mgr_enable_alpha_fixed_zorder(channel,
2756 info->partial_alpha_enabled);
2757 if (dss_has_feature(FEAT_CPR)) {
2758 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2759 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2760 }
2761}
348be69d 2762EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 2763
fb2cec1f 2764static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2765{
2766 int code;
2767
2768 switch (data_lines) {
2769 case 12:
2770 code = 0;
2771 break;
2772 case 16:
2773 code = 1;
2774 break;
2775 case 18:
2776 code = 2;
2777 break;
2778 case 24:
2779 code = 3;
2780 break;
2781 default:
2782 BUG();
2783 return;
2784 }
2785
efa70b3b 2786 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2787}
2788
fb2cec1f 2789static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2790{
2791 u32 l;
569969d6 2792 int gpout0, gpout1;
80c39712
TV		 2793
2794 switch (mode) {
569969d6
AT		 2795 case DSS_IO_PAD_MODE_RESET:
2796 gpout0 = 0;
2797 gpout1 = 0;
80c39712 2798 break;
569969d6
AT		 2799 case DSS_IO_PAD_MODE_RFBI:
2800 gpout0 = 1;
80c39712
TV		 2801 gpout1 = 0;
2802 break;
569969d6
AT		 2803 case DSS_IO_PAD_MODE_BYPASS:
2804 gpout0 = 1;
80c39712
TV		 2805 gpout1 = 1;
2806 break;
80c39712
TV		 2807 default:
2808 BUG();
2809 return;
2810 }
2811
569969d6
AT		 2812 l = dispc_read_reg(DISPC_CONTROL);
2813 l = FLD_MOD(l, gpout0, 15, 15);
2814 l = FLD_MOD(l, gpout1, 16, 16);
2815 dispc_write_reg(DISPC_CONTROL, l);
2816}
2817
fb2cec1f 2818static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2819{
efa70b3b 2820 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2821}
2822
fb2cec1f
TV		 2823void dispc_mgr_set_lcd_config(enum omap_channel channel,
2824 const struct dss_lcd_mgr_config *config)
2825{
2826 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2827
2828 dispc_mgr_enable_stallmode(channel, config->stallmode);
2829 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2830
2831 dispc_mgr_set_clock_div(channel, &config->clock_info);
2832
2833 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2834
2835 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2836
2837 dispc_mgr_set_lcd_type_tft(channel);
2838}
348be69d 2839EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 2840
8f366162
AT		 2841static bool _dispc_mgr_size_ok(u16 width, u16 height)
2842{
33b89928
AT		 2843 return width <= dispc.feat->mgr_width_max &&
2844 height <= dispc.feat->mgr_height_max;
8f366162
AT		 2845}
2846
80c39712
TV		 2847static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2848 int vsw, int vfp, int vbp)
2849{
dcbe765b
CM		 2850 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2851 hfp < 1 || hfp > dispc.feat->hp_max ||
2852 hbp < 1 || hbp > dispc.feat->hp_max ||
2853 vsw < 1 || vsw > dispc.feat->sw_max ||
2854 vfp < 0 || vfp > dispc.feat->vp_max ||
2855 vbp < 0 || vbp > dispc.feat->vp_max)
2856 return false;
80c39712
TV		 2857 return true;
2858}
2859
ca5ca69c
AT		 2860static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2861 unsigned long pclk)
2862{
2863 if (dss_mgr_is_lcd(channel))
2864 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2865 else
2866 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2867}
2868
8f366162 2869bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2870 const struct omap_video_timings *timings)
80c39712 2871{
8f366162
AT		 2872 bool timings_ok;
2873
2874 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2875
ca5ca69c
AT		 2876 timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixel_clock * 1000);
2877
2878 if (dss_mgr_is_lcd(channel)) {
2879 timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2880 timings->hbp, timings->vsw, timings->vfp,
2881 timings->vbp);
2882 }
8f366162
AT		 2883
2884 return timings_ok;
80c39712
TV		 2885}
2886
26d9dd0d 2887static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2888 int hfp, int hbp, int vsw, int vfp, int vbp,
2889 enum omap_dss_signal_level vsync_level,
2890 enum omap_dss_signal_level hsync_level,
2891 enum omap_dss_signal_edge data_pclk_edge,
2892 enum omap_dss_signal_level de_level,
2893 enum omap_dss_signal_edge sync_pclk_edge)
2894
80c39712 2895{
655e2941
AT		 2896 u32 timing_h, timing_v, l;
2897 bool onoff, rf, ipc;
80c39712 2898
dcbe765b
CM		 2899 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2900 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2901 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2902 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2903 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2904 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 2905
64ba4f74
SS		 2906 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2907 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 2908
2909 switch (data_pclk_edge) {
2910 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2911 ipc = false;
2912 break;
2913 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2914 ipc = true;
2915 break;
2916 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2917 default:
2918 BUG();
2919 }
2920
2921 switch (sync_pclk_edge) {
2922 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2923 onoff = false;
2924 rf = false;
2925 break;
2926 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2927 onoff = true;
2928 rf = false;
2929 break;
2930 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2931 onoff = true;
2932 rf = true;
2933 break;
2934 default:
2935 BUG();
cf6ac4ce 2936 }
655e2941
AT		 2937
2938 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2939 l |= FLD_VAL(onoff, 17, 17);
2940 l |= FLD_VAL(rf, 16, 16);
2941 l |= FLD_VAL(de_level, 15, 15);
2942 l |= FLD_VAL(ipc, 14, 14);
2943 l |= FLD_VAL(hsync_level, 13, 13);
2944 l |= FLD_VAL(vsync_level, 12, 12);
2945 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2946}
2947
2948/* change name to mode? */
c51d921a 2949void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 2950 const struct omap_video_timings *timings)
80c39712
TV		 2951{
2952 unsigned xtot, ytot;
2953 unsigned long ht, vt;
2aefad49 2954 struct omap_video_timings t = *timings;
80c39712 2955
2aefad49 2956 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 2957
2aefad49 2958 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2959 BUG();
c6eee968
TV		 2960 return;
2961 }
80c39712 2962
dd88b7a6 2963 if (dss_mgr_is_lcd(channel)) {
2aefad49 2964 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 2965 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2966 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 2967
2aefad49
AT		 2968 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2969 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 2970
c51d921a
AT		 2971 ht = (timings->pixel_clock * 1000) / xtot;
2972 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2973
2974 DSSDBG("pck %u\n", timings->pixel_clock);
2975 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 2976 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 2977 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2978 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2979 t.de_level, t.sync_pclk_edge);
80c39712 2980
c51d921a 2981 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 2982 } else {
23c8f88e 2983 if (t.interlace == true)
2aefad49 2984 t.y_res /= 2;
c51d921a 2985 }
8f366162 2986
2aefad49 2987 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 2988}
348be69d 2989EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 2990
26d9dd0d 2991static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2992 u16 pck_div)
80c39712
TV		 2993{
2994 BUG_ON(lck_div < 1);
9eaaf207 2995 BUG_ON(pck_div < 1);
80c39712 2996
ce7fa5eb 2997 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2998 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3
TV		 2999
3000 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
3001 channel == OMAP_DSS_CHANNEL_LCD)
3002 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 3003}
3004
26d9dd0d 3005static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3006 int *pck_div)
80c39712
TV		 3007{
3008 u32 l;
ce7fa5eb 3009 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3010 *lck_div = FLD_GET(l, 23, 16);
3011 *pck_div = FLD_GET(l, 7, 0);
3012}
3013
3014unsigned long dispc_fclk_rate(void)
3015{
a72b64b9 3016 struct platform_device *dsidev;
80c39712
TV		 3017 unsigned long r = 0;
3018
66534e8e 3019 switch (dss_get_dispc_clk_source()) {
89a35e51 3020 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3021 r = dss_get_dispc_clk_rate();
66534e8e 3022 break;
89a35e51 3023 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3024 dsidev = dsi_get_dsidev_from_id(0);
3025 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 3026 break;
5a8b572d
AT		 3027 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3028 dsidev = dsi_get_dsidev_from_id(1);
3029 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3030 break;
66534e8e
TA		 3031 default:
3032 BUG();
c6eee968 3033 return 0;
66534e8e
TA		 3034 }
3035
80c39712
TV		 3036 return r;
3037}
3038
26d9dd0d 3039unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3040{
a72b64b9 3041 struct platform_device *dsidev;
80c39712
TV		 3042 int lcd;
3043 unsigned long r;
3044 u32 l;
3045
c31cba8a
TV		 3046 if (dss_mgr_is_lcd(channel)) {
3047 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3048
c31cba8a 3049 lcd = FLD_GET(l, 23, 16);
80c39712 3050
c31cba8a
TV		 3051 switch (dss_get_lcd_clk_source(channel)) {
3052 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3053 r = dss_get_dispc_clk_rate();
c31cba8a
TV		 3054 break;
3055 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3056 dsidev = dsi_get_dsidev_from_id(0);
3057 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3058 break;
3059 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3060 dsidev = dsi_get_dsidev_from_id(1);
3061 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3062 break;
3063 default:
3064 BUG();
3065 return 0;
3066 }
80c39712 3067
c31cba8a
TV		 3068 return r / lcd;
3069 } else {
3070 return dispc_fclk_rate();
3071 }
80c39712
TV		 3072}
3073
26d9dd0d 3074unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3075{
80c39712 3076 unsigned long r;
80c39712 3077
dd88b7a6 3078 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3079 int pcd;
3080 u32 l;
80c39712 3081
c3dc6a7a 3082 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3083
c3dc6a7a 3084 pcd = FLD_GET(l, 7, 0);
80c39712 3085
c3dc6a7a
AT		 3086 r = dispc_mgr_lclk_rate(channel);
3087
3088 return r / pcd;
3089 } else {
5391e87d 3090 return dispc.tv_pclk_rate;
c3dc6a7a 3091 }
80c39712
TV		 3092}
3093
5391e87d
TV		 3094void dispc_set_tv_pclk(unsigned long pclk)
3095{
3096 dispc.tv_pclk_rate = pclk;
3097}
3098
8b53d991
CM		 3099unsigned long dispc_core_clk_rate(void)
3100{
7b3926b3 3101 return dispc.core_clk_rate;
8b53d991
CM		 3102}
3103
3e8a6ff2
AT		 3104static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3105{
251886d8
TV		 3106 enum omap_channel channel;
3107
3108 if (plane == OMAP_DSS_WB)
3109 return 0;
3110
3111 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3112
3113 return dispc_mgr_pclk_rate(channel);
3114}
3115
3116static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3117{
251886d8
TV		 3118 enum omap_channel channel;
3119
3120 if (plane == OMAP_DSS_WB)
3121 return 0;
3122
3123 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3124
c31cba8a 3125 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3126}
c31cba8a 3127
6f1891fc 3128static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3129{
3130 int lcd, pcd;
6f1891fc
CM		 3131 enum omap_dss_clk_source lcd_clk_src;
3132
3133 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3134
3135 lcd_clk_src = dss_get_lcd_clk_source(channel);
3136
3137 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3138 dss_get_generic_clk_source_name(lcd_clk_src),
3139 dss_feat_get_clk_source_name(lcd_clk_src));
3140
3141 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3142
3143 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3144 dispc_mgr_lclk_rate(channel), lcd);
3145 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3146 dispc_mgr_pclk_rate(channel), pcd);
3147}
3148
3149void dispc_dump_clocks(struct seq_file *s)
3150{
3151 int lcd;
0cf35df3 3152 u32 l;
89a35e51 3153 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3154
4fbafaf3
TV		 3155 if (dispc_runtime_get())
3156 return;
80c39712 3157
80c39712
TV		 3158 seq_printf(s, "- DISPC -\n");
3159
067a57e4
AT		 3160 seq_printf(s, "dispc fclk source = %s (%s)\n",
3161 dss_get_generic_clk_source_name(dispc_clk_src),
3162 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3163
3164 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3165
0cf35df3
MR		 3166 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3167 seq_printf(s, "- DISPC-CORE-CLK -\n");
3168 l = dispc_read_reg(DISPC_DIVISOR);
3169 lcd = FLD_GET(l, 23, 16);
3170
3171 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3172 (dispc_fclk_rate()/lcd), lcd);
3173 }
2a205f34 3174
6f1891fc 3175 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3176
6f1891fc
CM		 3177 if (dss_has_feature(FEAT_MGR_LCD2))
3178 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3179 if (dss_has_feature(FEAT_MGR_LCD3))
3180 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3181
3182 dispc_runtime_put();
80c39712
TV		 3183}
3184
e40402cf 3185static void dispc_dump_regs(struct seq_file *s)
80c39712 3186{
4dd2da15
AT		 3187 int i, j;
3188 const char *mgr_names[] = {
3189 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3190 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3191 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3192 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3193 };
3194 const char *ovl_names[] = {
3195 [OMAP_DSS_GFX] = "GFX",
3196 [OMAP_DSS_VIDEO1] = "VID1",
3197 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3198 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3199 };
3200 const char **p_names;
3201
9b372c2d 3202#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3203
4fbafaf3
TV		 3204 if (dispc_runtime_get())
3205 return;
80c39712 3206
5010be80 3207 /* DISPC common registers */
80c39712
TV		 3208 DUMPREG(DISPC_REVISION);
3209 DUMPREG(DISPC_SYSCONFIG);
3210 DUMPREG(DISPC_SYSSTATUS);
3211 DUMPREG(DISPC_IRQSTATUS);
3212 DUMPREG(DISPC_IRQENABLE);
3213 DUMPREG(DISPC_CONTROL);
3214 DUMPREG(DISPC_CONFIG);
3215 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3216 DUMPREG(DISPC_LINE_STATUS);
3217 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3218 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3219 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3220 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3221 if (dss_has_feature(FEAT_MGR_LCD2)) {
3222 DUMPREG(DISPC_CONTROL2);
3223 DUMPREG(DISPC_CONFIG2);
5010be80 3224 }
6f1891fc
CM		 3225 if (dss_has_feature(FEAT_MGR_LCD3)) {
3226 DUMPREG(DISPC_CONTROL3);
3227 DUMPREG(DISPC_CONFIG3);
3228 }
29fceeeb
TV		 3229 if (dss_has_feature(FEAT_MFLAG))
3230 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
5010be80
AT		 3231
3232#undef DUMPREG
3233
3234#define DISPC_REG(i, name) name(i)
4dd2da15 3235#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3236 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3237 dispc_read_reg(DISPC_REG(i, r)))
3238
4dd2da15 3239 p_names = mgr_names;
5010be80 3240
4dd2da15
AT		 3241 /* DISPC channel specific registers */
3242 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3243 DUMPREG(i, DISPC_DEFAULT_COLOR);
3244 DUMPREG(i, DISPC_TRANS_COLOR);
3245 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3246
4dd2da15
AT		 3247 if (i == OMAP_DSS_CHANNEL_DIGIT)
3248 continue;
5010be80 3249
4dd2da15
AT		 3250 DUMPREG(i, DISPC_DEFAULT_COLOR);
3251 DUMPREG(i, DISPC_TRANS_COLOR);
3252 DUMPREG(i, DISPC_TIMING_H);
3253 DUMPREG(i, DISPC_TIMING_V);
3254 DUMPREG(i, DISPC_POL_FREQ);
3255 DUMPREG(i, DISPC_DIVISORo);
3256 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3257
4dd2da15
AT		 3258 DUMPREG(i, DISPC_DATA_CYCLE1);
3259 DUMPREG(i, DISPC_DATA_CYCLE2);
3260 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3261
332e9d70 3262 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3263 DUMPREG(i, DISPC_CPR_COEF_R);
3264 DUMPREG(i, DISPC_CPR_COEF_G);
3265 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3266 }
2a205f34 3267 }
80c39712 3268
4dd2da15
AT		 3269 p_names = ovl_names;
3270
3271 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3272 DUMPREG(i, DISPC_OVL_BA0);
3273 DUMPREG(i, DISPC_OVL_BA1);
3274 DUMPREG(i, DISPC_OVL_POSITION);
3275 DUMPREG(i, DISPC_OVL_SIZE);
3276 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3277 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3278 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3279 DUMPREG(i, DISPC_OVL_ROW_INC);
3280 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3281 if (dss_has_feature(FEAT_PRELOAD))
3282 DUMPREG(i, DISPC_OVL_PRELOAD);
3283
3284 if (i == OMAP_DSS_GFX) {
3285 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3286 DUMPREG(i, DISPC_OVL_TABLE_BA);
3287 continue;
3288 }
3289
3290 DUMPREG(i, DISPC_OVL_FIR);
3291 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3292 DUMPREG(i, DISPC_OVL_ACCU0);
3293 DUMPREG(i, DISPC_OVL_ACCU1);
3294 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3295 DUMPREG(i, DISPC_OVL_BA0_UV);
3296 DUMPREG(i, DISPC_OVL_BA1_UV);
3297 DUMPREG(i, DISPC_OVL_FIR2);
3298 DUMPREG(i, DISPC_OVL_ACCU2_0);
3299 DUMPREG(i, DISPC_OVL_ACCU2_1);
3300 }
3301 if (dss_has_feature(FEAT_ATTR2))
3302 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3303 if (dss_has_feature(FEAT_PRELOAD))
3304 DUMPREG(i, DISPC_OVL_PRELOAD);
29fceeeb
TV		 3305 if (dss_has_feature(FEAT_MFLAG))
3306 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
ab5ca071 3307 }
5010be80
AT		 3308
3309#undef DISPC_REG
3310#undef DUMPREG
3311
3312#define DISPC_REG(plane, name, i) name(plane, i)
3313#define DUMPREG(plane, name, i) \
4dd2da15 3314 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3315 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3316 dispc_read_reg(DISPC_REG(plane, name, i)))
3317
4dd2da15 3318 /* Video pipeline coefficient registers */
332e9d70 3319
4dd2da15
AT		 3320 /* start from OMAP_DSS_VIDEO1 */
3321 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3322 for (j = 0; j < 8; j++)
3323 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3324
4dd2da15
AT		 3325 for (j = 0; j < 8; j++)
3326 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3327
4dd2da15
AT		 3328 for (j = 0; j < 5; j++)
3329 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3330
4dd2da15
AT		 3331 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3332 for (j = 0; j < 8; j++)
3333 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3334 }
3335
3336 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3337 for (j = 0; j < 8; j++)
3338 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3339
3340 for (j = 0; j < 8; j++)
3341 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3342
3343 for (j = 0; j < 8; j++)
3344 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3345 }
332e9d70 3346 }
80c39712 3347
4fbafaf3 3348 dispc_runtime_put();
5010be80
AT		 3349
3350#undef DISPC_REG
80c39712
TV		 3351#undef DUMPREG
3352}
3353
80c39712
TV		 3354/* calculate clock rates using dividers in cinfo */
3355int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3356 struct dispc_clock_info *cinfo)
3357{
80c39712
TV		 3358 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3359 return -EINVAL;
9eaaf207 3360 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3361 return -EINVAL;
80c39712 3362
80c39712
TV		 3363 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3364 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3365
80c39712
TV		 3366 return 0;
3367}
80c39712 3368
7c284e6e
TV		 3369bool dispc_div_calc(unsigned long dispc,
3370 unsigned long pck_min, unsigned long pck_max,
3371 dispc_div_calc_func func, void *data)
3372{
3373 int lckd, lckd_start, lckd_stop;
3374 int pckd, pckd_start, pckd_stop;
3375 unsigned long pck, lck;
3376 unsigned long lck_max;
3377 unsigned long pckd_hw_min, pckd_hw_max;
3378 unsigned min_fck_per_pck;
3379 unsigned long fck;
80c39712 3380
7c284e6e
TV		 3381#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3382 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3383#else
3384 min_fck_per_pck = 0;
3385#endif
80c39712 3386
7c284e6e
TV		 3387 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3388 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3389
7c284e6e 3390 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3391
7c284e6e
TV		 3392 pck_min = pck_min ? pck_min : 1;
3393 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3394
7c284e6e
TV		 3395 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3396 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3397
7c284e6e
TV		 3398 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3399 lck = dispc / lckd;
80c39712 3400
7c284e6e
TV		 3401 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3402 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3403
7c284e6e
TV		 3404 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3405 pck = lck / pckd;
80c39712 3406
7c284e6e
TV		 3407 /*
3408 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3409 * clock, which means we're configuring DISPC fclk here
3410 * also. Thus we need to use the calculated lck. For
3411 * OMAP4+ the DISPC fclk is a separate clock.
3412 */
3413 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3414 fck = dispc_core_clk_rate();
3415 else
3416 fck = lck;
3417
3418 if (fck < pck * min_fck_per_pck)
3419 continue;
3420
3421 if (func(lckd, pckd, lck, pck, data))
3422 return true;
3423 }
3424 }
3425
3426 return false;
80c39712
TV		 3427}
3428
f0d08f89 3429void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3430 const struct dispc_clock_info *cinfo)
80c39712
TV		 3431{
3432 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3433 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3434
26d9dd0d 3435 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3436}
3437
26d9dd0d 3438int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3439 struct dispc_clock_info *cinfo)
80c39712
TV		 3440{
3441 unsigned long fck;
3442
3443 fck = dispc_fclk_rate();
3444
ce7fa5eb
MR		 3445 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3446 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3447
3448 cinfo->lck = fck / cinfo->lck_div;
3449 cinfo->pck = cinfo->lck / cinfo->pck_div;
3450
3451 return 0;
3452}
3453
4e0397cf
TV		 3454u32 dispc_read_irqstatus(void)
3455{
3456 return dispc_read_reg(DISPC_IRQSTATUS);
3457}
348be69d 3458EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3459
3460void dispc_clear_irqstatus(u32 mask)
3461{
3462 dispc_write_reg(DISPC_IRQSTATUS, mask);
3463}
348be69d 3464EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3465
3466u32 dispc_read_irqenable(void)
3467{
3468 return dispc_read_reg(DISPC_IRQENABLE);
3469}
348be69d 3470EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3471
3472void dispc_write_irqenable(u32 mask)
3473{
3474 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3475
3476 /* clear the irqstatus for newly enabled irqs */
3477 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3478
3479 dispc_write_reg(DISPC_IRQENABLE, mask);
3480}
348be69d 3481EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3482
80c39712
TV		 3483void dispc_enable_sidle(void)
3484{
3485 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3486}
3487
3488void dispc_disable_sidle(void)
3489{
3490 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3491}
3492
3493static void _omap_dispc_initial_config(void)
3494{
3495 u32 l;
3496
0cf35df3
MR		 3497 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3498 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3499 l = dispc_read_reg(DISPC_DIVISOR);
3500 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3501 l = FLD_MOD(l, 1, 0, 0);
3502 l = FLD_MOD(l, 1, 23, 16);
3503 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3504
3505 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3506 }
3507
80c39712 3508 /* FUNCGATED */
6ced40bf
AT		 3509 if (dss_has_feature(FEAT_FUNCGATED))
3510 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3511
6e5264b0 3512 dispc_setup_color_conv_coef();
80c39712
TV		 3513
3514 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3515
42a6961c 3516 dispc_init_fifos();
5ed8cf5b
TV		 3517
3518 dispc_configure_burst_sizes();
54128701
AT		 3519
3520 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3521
3522 if (dispc.feat->mstandby_workaround)
3523 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
80c39712
TV		 3524}
3525
dcbe765b
CM		 3526static const struct dispc_features omap24xx_dispc_feats __initconst = {
3527 .sw_start = 5,
3528 .fp_start = 15,
3529 .bp_start = 27,
3530 .sw_max = 64,
3531 .vp_max = 255,
3532 .hp_max = 256,
33b89928
AT		 3533 .mgr_width_start = 10,
3534 .mgr_height_start = 26,
3535 .mgr_width_max = 2048,
3536 .mgr_height_max = 2048,
ca5ca69c 3537 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3538 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3539 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3540 .num_fifos = 3,
cffa947d 3541 .no_framedone_tv = true,
8bc65552 3542 .set_max_preload = false,
dcbe765b
CM		 3543};
3544
3545static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3546 .sw_start = 5,
3547 .fp_start = 15,
3548 .bp_start = 27,
3549 .sw_max = 64,
3550 .vp_max = 255,
3551 .hp_max = 256,
33b89928
AT		 3552 .mgr_width_start = 10,
3553 .mgr_height_start = 26,
3554 .mgr_width_max = 2048,
3555 .mgr_height_max = 2048,
ca5ca69c
AT		 3556 .max_lcd_pclk = 173000000,
3557 .max_tv_pclk = 59000000,
dcbe765b
CM		 3558 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3559 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3560 .num_fifos = 3,
cffa947d 3561 .no_framedone_tv = true,
8bc65552 3562 .set_max_preload = false,
dcbe765b
CM		 3563};
3564
3565static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3566 .sw_start = 7,
3567 .fp_start = 19,
3568 .bp_start = 31,
3569 .sw_max = 256,
3570 .vp_max = 4095,
3571 .hp_max = 4096,
33b89928
AT		 3572 .mgr_width_start = 10,
3573 .mgr_height_start = 26,
3574 .mgr_width_max = 2048,
3575 .mgr_height_max = 2048,
ca5ca69c
AT		 3576 .max_lcd_pclk = 173000000,
3577 .max_tv_pclk = 59000000,
dcbe765b
CM		 3578 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3579 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3580 .num_fifos = 3,
cffa947d 3581 .no_framedone_tv = true,
8bc65552 3582 .set_max_preload = false,
dcbe765b
CM		 3583};
3584
3585static const struct dispc_features omap44xx_dispc_feats __initconst = {
3586 .sw_start = 7,
3587 .fp_start = 19,
3588 .bp_start = 31,
3589 .sw_max = 256,
3590 .vp_max = 4095,
3591 .hp_max = 4096,
33b89928
AT		 3592 .mgr_width_start = 10,
3593 .mgr_height_start = 26,
3594 .mgr_width_max = 2048,
3595 .mgr_height_max = 2048,
ca5ca69c
AT		 3596 .max_lcd_pclk = 170000000,
3597 .max_tv_pclk = 185625000,
dcbe765b
CM		 3598 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3599 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3600 .num_fifos = 5,
66a0f9e4 3601 .gfx_fifo_workaround = true,
8bc65552 3602 .set_max_preload = true,
dcbe765b
CM		 3603};
3604
264236f8
AT		 3605static const struct dispc_features omap54xx_dispc_feats __initconst = {
3606 .sw_start = 7,
3607 .fp_start = 19,
3608 .bp_start = 31,
3609 .sw_max = 256,
3610 .vp_max = 4095,
3611 .hp_max = 4096,
3612 .mgr_width_start = 11,
3613 .mgr_height_start = 27,
3614 .mgr_width_max = 4096,
3615 .mgr_height_max = 4096,
ca5ca69c
AT		 3616 .max_lcd_pclk = 170000000,
3617 .max_tv_pclk = 186000000,
264236f8
AT		 3618 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3619 .calc_core_clk = calc_core_clk_44xx,
3620 .num_fifos = 5,
3621 .gfx_fifo_workaround = true,
d0df9a2c 3622 .mstandby_workaround = true,
8bc65552 3623 .set_max_preload = true,
264236f8
AT		 3624};
3625
84b47623 3626static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3627{
3628 const struct dispc_features *src;
3629 struct dispc_features *dst;
3630
84b47623 3631 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3632 if (!dst) {
84b47623 3633 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3634 return -ENOMEM;
3635 }
3636
b2c7d54f 3637 switch (omapdss_get_version()) {
84b47623 3638 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3639 src = &omap24xx_dispc_feats;
84b47623
TV		 3640 break;
3641
3642 case OMAPDSS_VER_OMAP34xx_ES1:
3643 src = &omap34xx_rev1_0_dispc_feats;
3644 break;
3645
3646 case OMAPDSS_VER_OMAP34xx_ES3:
3647 case OMAPDSS_VER_OMAP3630:
3648 case OMAPDSS_VER_AM35xx:
3649 src = &omap34xx_rev3_0_dispc_feats;
3650 break;
3651
3652 case OMAPDSS_VER_OMAP4430_ES1:
3653 case OMAPDSS_VER_OMAP4430_ES2:
3654 case OMAPDSS_VER_OMAP4:
dcbe765b 3655 src = &omap44xx_dispc_feats;
84b47623
TV		 3656 break;
3657
3658 case OMAPDSS_VER_OMAP5:
264236f8 3659 src = &omap54xx_dispc_feats;
84b47623
TV		 3660 break;
3661
3662 default:
dcbe765b
CM		 3663 return -ENODEV;
3664 }
3665
3666 memcpy(dst, src, sizeof(*dst));
3667 dispc.feat = dst;
3668
3669 return 0;
3670}
3671
96e2e637
TV		 3672int dispc_request_irq(irq_handler_t handler, void *dev_id)
3673{
3674 return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler,
3675 IRQF_SHARED, "OMAP DISPC", dev_id);
3676}
348be69d 3677EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 3678
3679void dispc_free_irq(void *dev_id)
3680{
3681 devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id);
3682}
348be69d 3683EXPORT_SYMBOL(dispc_free_irq);
96e2e637 3684
060b6d9c 3685/* DISPC HW IP initialisation */
6e7e8f06 3686static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3687{
3688 u32 rev;
affe360d 3689 int r = 0;
ea9da36a
SG		 3690 struct resource *dispc_mem;
3691
060b6d9c
SG		 3692 dispc.pdev = pdev;
3693
84b47623 3694 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 3695 if (r)
3696 return r;
3697
ea9da36a
SG		 3698 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3699 if (!dispc_mem) {
3700 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3701 return -EINVAL;
ea9da36a 3702 }
cd3b3449 3703
6e2a14d2
JL		 3704 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3705 resource_size(dispc_mem));
060b6d9c
SG		 3706 if (!dispc.base) {
3707 DSSERR("can't ioremap DISPC\n");
cd3b3449 3708 return -ENOMEM;
affe360d 3709 }
cd3b3449 3710
affe360d 3711 dispc.irq = platform_get_irq(dispc.pdev, 0);
3712 if (dispc.irq < 0) {
3713 DSSERR("platform_get_irq failed\n");
cd3b3449 3714 return -ENODEV;
affe360d 3715 }
3716
4fbafaf3
TV		 3717 pm_runtime_enable(&pdev->dev);
3718
3719 r = dispc_runtime_get();
3720 if (r)
3721 goto err_runtime_get;
060b6d9c
SG		 3722
3723 _omap_dispc_initial_config();
3724
060b6d9c 3725 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3726 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3727 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3728
4fbafaf3 3729 dispc_runtime_put();
060b6d9c 3730
04b1fc02
TV		 3731 dss_init_overlay_managers();
3732
e40402cf
TV		 3733 dss_debugfs_create_file("dispc", dispc_dump_regs);
3734
060b6d9c 3735 return 0;
4fbafaf3
TV		 3736
3737err_runtime_get:
3738 pm_runtime_disable(&pdev->dev);
affe360d 3739 return r;
060b6d9c
SG		 3740}
3741
6e7e8f06 3742static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3743{
4fbafaf3
TV		 3744 pm_runtime_disable(&pdev->dev);
3745
04b1fc02
TV		 3746 dss_uninit_overlay_managers();
3747
060b6d9c
SG		 3748 return 0;
3749}
3750
4fbafaf3
TV		 3751static int dispc_runtime_suspend(struct device *dev)
3752{
3753 dispc_save_context();
4fbafaf3
TV		 3754
3755 return 0;
3756}
3757
3758static int dispc_runtime_resume(struct device *dev)
3759{
9229b516
TV		 3760 /*
3761 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
3762 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
3763 * _omap_dispc_initial_config(). We can thus use it to detect if
3764 * we have lost register context.
3765 */
3766 if (REG_GET(DISPC_CONFIG, 2, 1) == OMAP_DSS_LOAD_FRAME_ONLY)
3767 return 0;
3768
be07dcd7
TV		 3769 _omap_dispc_initial_config();
3770
49ea86f3 3771 dispc_restore_context();
4fbafaf3
TV		 3772
3773 return 0;
3774}
3775
3776static const struct dev_pm_ops dispc_pm_ops = {
3777 .runtime_suspend = dispc_runtime_suspend,
3778 .runtime_resume = dispc_runtime_resume,
3779};
3780
060b6d9c 3781static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3782 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3783 .driver = {
3784 .name = "omapdss_dispc",
3785 .owner = THIS_MODULE,
4fbafaf3 3786 .pm = &dispc_pm_ops,
060b6d9c
SG		 3787 },
3788};
3789
6e7e8f06 3790int __init dispc_init_platform_driver(void)
060b6d9c 3791{
11436e1d 3792 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3793}
3794
6e7e8f06 3795void __exit dispc_uninit_platform_driver(void)
060b6d9c 3796{
04c742c3 3797 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3798}
Linux kernel - Deliverables
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