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OMAPDSS: DISPC: make dispc_ovl_set_channel_out() public
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712
TV		 39
40#include <plat/sram.h>
41#include <plat/clock.h>
42
a0b38cc4 43#include <video/omapdss.h>
80c39712
TV		 44
45#include "dss.h"
a0acb557 46#include "dss_features.h"
9b372c2d 47#include "dispc.h"
80c39712
TV		 48
49/* DISPC */
8613b000 50#define DISPC_SZ_REGS SZ_4K
80c39712 51
80c39712
TV		 52#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
53 DISPC_IRQ_OCP_ERR | \
54 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
55 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
56 DISPC_IRQ_SYNC_LOST | \
57 DISPC_IRQ_SYNC_LOST_DIGIT)
58
59#define DISPC_MAX_NR_ISRS 8
60
61struct omap_dispc_isr_data {
62 omap_dispc_isr_t isr;
63 void *arg;
64 u32 mask;
65};
66
66be8f6c
GI		 67struct dispc_h_coef {
68 s8 hc4;
69 s8 hc3;
70 u8 hc2;
71 s8 hc1;
72 s8 hc0;
73};
74
75struct dispc_v_coef {
76 s8 vc22;
77 s8 vc2;
78 u8 vc1;
79 s8 vc0;
80 s8 vc00;
81};
82
5ed8cf5b
TV		 83enum omap_burst_size {
84 BURST_SIZE_X2 = 0,
85 BURST_SIZE_X4 = 1,
86 BURST_SIZE_X8 = 2,
87};
88
80c39712
TV		 89#define REG_GET(idx, start, end) \
90 FLD_GET(dispc_read_reg(idx), start, end)
91
92#define REG_FLD_MOD(idx, val, start, end) \
93 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
94
dfc0fd8d
TV		 95struct dispc_irq_stats {
96 unsigned long last_reset;
97 unsigned irq_count;
98 unsigned irqs[32];
99};
100
80c39712 101static struct {
060b6d9c 102 struct platform_device *pdev;
80c39712 103 void __iomem *base;
4fbafaf3
TV		 104
105 int ctx_loss_cnt;
106
affe360d 107 int irq;
4fbafaf3 108 struct clk *dss_clk;
80c39712 109
e13a138b 110 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 111
112 spinlock_t irq_lock;
113 u32 irq_error_mask;
114 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
115 u32 error_irqs;
116 struct work_struct error_work;
117
49ea86f3 118 bool ctx_valid;
80c39712 119 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 120
121#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
122 spinlock_t irq_stats_lock;
123 struct dispc_irq_stats irq_stats;
124#endif
80c39712
TV		 125} dispc;
126
0d66cbb5
AJ		 127enum omap_color_component {
128 /* used for all color formats for OMAP3 and earlier
129 * and for RGB and Y color component on OMAP4
130 */
131 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
132 /* used for UV component for
133 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
134 * color formats on OMAP4
135 */
136 DISPC_COLOR_COMPONENT_UV = 1 << 1,
137};
138
80c39712
TV		 139static void _omap_dispc_set_irqs(void);
140
55978cc2 141static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 142{
55978cc2 143 __raw_writel(val, dispc.base + idx);
80c39712
TV		 144}
145
55978cc2 146static inline u32 dispc_read_reg(const u16 idx)
80c39712 147{
55978cc2 148 return __raw_readl(dispc.base + idx);
80c39712
TV		 149}
150
49ea86f3
TV		 151static int dispc_get_ctx_loss_count(void)
152{
153 struct device *dev = &dispc.pdev->dev;
154 struct omap_display_platform_data *pdata = dev->platform_data;
155 struct omap_dss_board_info *board_data = pdata->board_data;
156 int cnt;
157
158 if (!board_data->get_context_loss_count)
159 return -ENOENT;
160
161 cnt = board_data->get_context_loss_count(dev);
162
163 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
164
165 return cnt;
166}
167
80c39712 168#define SR(reg) \
55978cc2 169 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 170#define RR(reg) \
55978cc2 171 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 172
4fbafaf3 173static void dispc_save_context(void)
80c39712 174{
c6104b8e 175 int i, j;
80c39712 176
4fbafaf3
TV		 177 DSSDBG("dispc_save_context\n");
178
80c39712
TV		 179 SR(IRQENABLE);
180 SR(CONTROL);
181 SR(CONFIG);
80c39712 182 SR(LINE_NUMBER);
11354dd5
AT		 183 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
184 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 185 SR(GLOBAL_ALPHA);
2a205f34
SS		 186 if (dss_has_feature(FEAT_MGR_LCD2)) {
187 SR(CONTROL2);
2a205f34
SS		 188 SR(CONFIG2);
189 }
80c39712 190
c6104b8e
AT		 191 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
192 SR(DEFAULT_COLOR(i));
193 SR(TRANS_COLOR(i));
194 SR(SIZE_MGR(i));
195 if (i == OMAP_DSS_CHANNEL_DIGIT)
196 continue;
197 SR(TIMING_H(i));
198 SR(TIMING_V(i));
199 SR(POL_FREQ(i));
200 SR(DIVISORo(i));
201
202 SR(DATA_CYCLE1(i));
203 SR(DATA_CYCLE2(i));
204 SR(DATA_CYCLE3(i));
205
332e9d70 206 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 207 SR(CPR_COEF_R(i));
208 SR(CPR_COEF_G(i));
209 SR(CPR_COEF_B(i));
332e9d70 210 }
2a205f34 211 }
80c39712 212
c6104b8e
AT		 213 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
214 SR(OVL_BA0(i));
215 SR(OVL_BA1(i));
216 SR(OVL_POSITION(i));
217 SR(OVL_SIZE(i));
218 SR(OVL_ATTRIBUTES(i));
219 SR(OVL_FIFO_THRESHOLD(i));
220 SR(OVL_ROW_INC(i));
221 SR(OVL_PIXEL_INC(i));
222 if (dss_has_feature(FEAT_PRELOAD))
223 SR(OVL_PRELOAD(i));
224 if (i == OMAP_DSS_GFX) {
225 SR(OVL_WINDOW_SKIP(i));
226 SR(OVL_TABLE_BA(i));
227 continue;
228 }
229 SR(OVL_FIR(i));
230 SR(OVL_PICTURE_SIZE(i));
231 SR(OVL_ACCU0(i));
232 SR(OVL_ACCU1(i));
9b372c2d 233
c6104b8e
AT		 234 for (j = 0; j < 8; j++)
235 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 236
c6104b8e
AT		 237 for (j = 0; j < 8; j++)
238 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 239
c6104b8e
AT		 240 for (j = 0; j < 5; j++)
241 SR(OVL_CONV_COEF(i, j));
ab5ca071 242
c6104b8e
AT		 243 if (dss_has_feature(FEAT_FIR_COEF_V)) {
244 for (j = 0; j < 8; j++)
245 SR(OVL_FIR_COEF_V(i, j));
246 }
9b372c2d 247
c6104b8e
AT		 248 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
249 SR(OVL_BA0_UV(i));
250 SR(OVL_BA1_UV(i));
251 SR(OVL_FIR2(i));
252 SR(OVL_ACCU2_0(i));
253 SR(OVL_ACCU2_1(i));
ab5ca071 254
c6104b8e
AT		 255 for (j = 0; j < 8; j++)
256 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 257
c6104b8e
AT		 258 for (j = 0; j < 8; j++)
259 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 260
c6104b8e
AT		 261 for (j = 0; j < 8; j++)
262 SR(OVL_FIR_COEF_V2(i, j));
263 }
264 if (dss_has_feature(FEAT_ATTR2))
265 SR(OVL_ATTRIBUTES2(i));
ab5ca071 266 }
0cf35df3
MR		 267
268 if (dss_has_feature(FEAT_CORE_CLK_DIV))
269 SR(DIVISOR);
49ea86f3
TV		 270
271 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
272 dispc.ctx_valid = true;
273
274 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 275}
276
4fbafaf3 277static void dispc_restore_context(void)
80c39712 278{
c6104b8e 279 int i, j, ctx;
4fbafaf3
TV		 280
281 DSSDBG("dispc_restore_context\n");
282
49ea86f3
TV		 283 if (!dispc.ctx_valid)
284 return;
285
286 ctx = dispc_get_ctx_loss_count();
287
288 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
289 return;
290
291 DSSDBG("ctx_loss_count: saved %d, current %d\n",
292 dispc.ctx_loss_cnt, ctx);
293
75c7d59d 294 /*RR(IRQENABLE);*/
80c39712
TV		 295 /*RR(CONTROL);*/
296 RR(CONFIG);
80c39712 297 RR(LINE_NUMBER);
11354dd5
AT		 298 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
299 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 300 RR(GLOBAL_ALPHA);
c6104b8e 301 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 302 RR(CONFIG2);
80c39712 303
c6104b8e
AT		 304 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
305 RR(DEFAULT_COLOR(i));
306 RR(TRANS_COLOR(i));
307 RR(SIZE_MGR(i));
308 if (i == OMAP_DSS_CHANNEL_DIGIT)
309 continue;
310 RR(TIMING_H(i));
311 RR(TIMING_V(i));
312 RR(POL_FREQ(i));
313 RR(DIVISORo(i));
314
315 RR(DATA_CYCLE1(i));
316 RR(DATA_CYCLE2(i));
317 RR(DATA_CYCLE3(i));
2a205f34 318
332e9d70 319 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 320 RR(CPR_COEF_R(i));
321 RR(CPR_COEF_G(i));
322 RR(CPR_COEF_B(i));
332e9d70 323 }
2a205f34 324 }
80c39712 325
c6104b8e
AT		 326 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
327 RR(OVL_BA0(i));
328 RR(OVL_BA1(i));
329 RR(OVL_POSITION(i));
330 RR(OVL_SIZE(i));
331 RR(OVL_ATTRIBUTES(i));
332 RR(OVL_FIFO_THRESHOLD(i));
333 RR(OVL_ROW_INC(i));
334 RR(OVL_PIXEL_INC(i));
335 if (dss_has_feature(FEAT_PRELOAD))
336 RR(OVL_PRELOAD(i));
337 if (i == OMAP_DSS_GFX) {
338 RR(OVL_WINDOW_SKIP(i));
339 RR(OVL_TABLE_BA(i));
340 continue;
341 }
342 RR(OVL_FIR(i));
343 RR(OVL_PICTURE_SIZE(i));
344 RR(OVL_ACCU0(i));
345 RR(OVL_ACCU1(i));
9b372c2d 346
c6104b8e
AT		 347 for (j = 0; j < 8; j++)
348 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 349
c6104b8e
AT		 350 for (j = 0; j < 8; j++)
351 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 352
c6104b8e
AT		 353 for (j = 0; j < 5; j++)
354 RR(OVL_CONV_COEF(i, j));
ab5ca071 355
c6104b8e
AT		 356 if (dss_has_feature(FEAT_FIR_COEF_V)) {
357 for (j = 0; j < 8; j++)
358 RR(OVL_FIR_COEF_V(i, j));
359 }
9b372c2d 360
c6104b8e
AT		 361 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
362 RR(OVL_BA0_UV(i));
363 RR(OVL_BA1_UV(i));
364 RR(OVL_FIR2(i));
365 RR(OVL_ACCU2_0(i));
366 RR(OVL_ACCU2_1(i));
ab5ca071 367
c6104b8e
AT		 368 for (j = 0; j < 8; j++)
369 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 370
c6104b8e
AT		 371 for (j = 0; j < 8; j++)
372 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 373
c6104b8e
AT		 374 for (j = 0; j < 8; j++)
375 RR(OVL_FIR_COEF_V2(i, j));
376 }
377 if (dss_has_feature(FEAT_ATTR2))
378 RR(OVL_ATTRIBUTES2(i));
ab5ca071 379 }
80c39712 380
0cf35df3
MR		 381 if (dss_has_feature(FEAT_CORE_CLK_DIV))
382 RR(DIVISOR);
383
80c39712
TV		 384 /* enable last, because LCD & DIGIT enable are here */
385 RR(CONTROL);
2a205f34
SS		 386 if (dss_has_feature(FEAT_MGR_LCD2))
387 RR(CONTROL2);
75c7d59d
VS		 388 /* clear spurious SYNC_LOST_DIGIT interrupts */
389 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
390
391 /*
392 * enable last so IRQs won't trigger before
393 * the context is fully restored
394 */
395 RR(IRQENABLE);
49ea86f3
TV		 396
397 DSSDBG("context restored\n");
80c39712
TV		 398}
399
400#undef SR
401#undef RR
402
4fbafaf3
TV		 403int dispc_runtime_get(void)
404{
405 int r;
406
407 DSSDBG("dispc_runtime_get\n");
408
409 r = pm_runtime_get_sync(&dispc.pdev->dev);
410 WARN_ON(r < 0);
411 return r < 0 ? r : 0;
412}
413
414void dispc_runtime_put(void)
415{
416 int r;
417
418 DSSDBG("dispc_runtime_put\n");
419
420 r = pm_runtime_put(&dispc.pdev->dev);
421 WARN_ON(r < 0);
80c39712
TV		 422}
423
dac57a05
AT		 424static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
425{
426 if (channel == OMAP_DSS_CHANNEL_LCD ||
427 channel == OMAP_DSS_CHANNEL_LCD2)
428 return true;
429 else
430 return false;
431}
4fbafaf3 432
c3dc6a7a
AT		 433static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
434{
435 struct omap_overlay_manager *mgr =
436 omap_dss_get_overlay_manager(channel);
437
438 return mgr ? mgr->device : NULL;
439}
440
26d9dd0d 441bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 442{
443 int bit;
444
dac57a05 445 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 446 bit = 5; /* GOLCD */
447 else
448 bit = 6; /* GODIGIT */
449
2a205f34
SS		 450 if (channel == OMAP_DSS_CHANNEL_LCD2)
451 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
452 else
453 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 454}
455
26d9dd0d 456void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 457{
458 int bit;
2a205f34 459 bool enable_bit, go_bit;
80c39712 460
dac57a05 461 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 462 bit = 0; /* LCDENABLE */
463 else
464 bit = 1; /* DIGITALENABLE */
465
466 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 467 if (channel == OMAP_DSS_CHANNEL_LCD2)
468 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
469 else
470 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
471
472 if (!enable_bit)
e6d80f95 473 return;
80c39712 474
dac57a05 475 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 476 bit = 5; /* GOLCD */
477 else
478 bit = 6; /* GODIGIT */
479
2a205f34
SS		 480 if (channel == OMAP_DSS_CHANNEL_LCD2)
481 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
482 else
483 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
484
485 if (go_bit) {
80c39712 486 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 487 return;
80c39712
TV		 488 }
489
2a205f34
SS		 490 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
491 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 492
2a205f34
SS		 493 if (channel == OMAP_DSS_CHANNEL_LCD2)
494 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
495 else
496 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 497}
498
f0e5caab 499static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 500{
9b372c2d 501 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 502}
503
f0e5caab 504static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 505{
9b372c2d 506 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 507}
508
f0e5caab 509static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 510{
9b372c2d 511 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 512}
513
f0e5caab 514static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 515{
516 BUG_ON(plane == OMAP_DSS_GFX);
517
518 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
519}
520
f0e5caab
TV		 521static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
522 u32 value)
ab5ca071
AJ		 523{
524 BUG_ON(plane == OMAP_DSS_GFX);
525
526 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
527}
528
f0e5caab 529static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 530{
531 BUG_ON(plane == OMAP_DSS_GFX);
532
533 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
534}
535
f0e5caab 536static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
0d66cbb5
AJ		 537 int vscaleup, int five_taps,
538 enum omap_color_component color_comp)
80c39712
TV		 539{
540 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 541 static const struct dispc_h_coef coef_hup[8] = {
542 { 0, 0, 128, 0, 0 },
543 { -1, 13, 124, -8, 0 },
544 { -2, 30, 112, -11, -1 },
545 { -5, 51, 95, -11, -2 },
546 { 0, -9, 73, 73, -9 },
547 { -2, -11, 95, 51, -5 },
548 { -1, -11, 112, 30, -2 },
549 { 0, -8, 124, 13, -1 },
80c39712
TV		 550 };
551
66be8f6c
GI		 552 /* Coefficients for vertical up-sampling */
553 static const struct dispc_v_coef coef_vup_3tap[8] = {
554 { 0, 0, 128, 0, 0 },
555 { 0, 3, 123, 2, 0 },
556 { 0, 12, 111, 5, 0 },
557 { 0, 32, 89, 7, 0 },
558 { 0, 0, 64, 64, 0 },
559 { 0, 7, 89, 32, 0 },
560 { 0, 5, 111, 12, 0 },
561 { 0, 2, 123, 3, 0 },
80c39712
TV		 562 };
563
66be8f6c
GI		 564 static const struct dispc_v_coef coef_vup_5tap[8] = {
565 { 0, 0, 128, 0, 0 },
566 { -1, 13, 124, -8, 0 },
567 { -2, 30, 112, -11, -1 },
568 { -5, 51, 95, -11, -2 },
569 { 0, -9, 73, 73, -9 },
570 { -2, -11, 95, 51, -5 },
571 { -1, -11, 112, 30, -2 },
572 { 0, -8, 124, 13, -1 },
80c39712
TV		 573 };
574
66be8f6c
GI		 575 /* Coefficients for horizontal down-sampling */
576 static const struct dispc_h_coef coef_hdown[8] = {
577 { 0, 36, 56, 36, 0 },
578 { 4, 40, 55, 31, -2 },
579 { 8, 44, 54, 27, -5 },
580 { 12, 48, 53, 22, -7 },
581 { -9, 17, 52, 51, 17 },
582 { -7, 22, 53, 48, 12 },
583 { -5, 27, 54, 44, 8 },
584 { -2, 31, 55, 40, 4 },
80c39712
TV		 585 };
586
66be8f6c
GI		 587 /* Coefficients for vertical down-sampling */
588 static const struct dispc_v_coef coef_vdown_3tap[8] = {
589 { 0, 36, 56, 36, 0 },
590 { 0, 40, 57, 31, 0 },
591 { 0, 45, 56, 27, 0 },
592 { 0, 50, 55, 23, 0 },
593 { 0, 18, 55, 55, 0 },
594 { 0, 23, 55, 50, 0 },
595 { 0, 27, 56, 45, 0 },
596 { 0, 31, 57, 40, 0 },
80c39712
TV		 597 };
598
66be8f6c
GI		 599 static const struct dispc_v_coef coef_vdown_5tap[8] = {
600 { 0, 36, 56, 36, 0 },
601 { 4, 40, 55, 31, -2 },
602 { 8, 44, 54, 27, -5 },
603 { 12, 48, 53, 22, -7 },
604 { -9, 17, 52, 51, 17 },
605 { -7, 22, 53, 48, 12 },
606 { -5, 27, 54, 44, 8 },
607 { -2, 31, 55, 40, 4 },
80c39712
TV		 608 };
609
66be8f6c
GI		 610 const struct dispc_h_coef *h_coef;
611 const struct dispc_v_coef *v_coef;
80c39712
TV		 612 int i;
613
614 if (hscaleup)
615 h_coef = coef_hup;
616 else
617 h_coef = coef_hdown;
618
66be8f6c
GI		 619 if (vscaleup)
620 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
621 else
622 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 623
624 for (i = 0; i < 8; i++) {
625 u32 h, hv;
626
66be8f6c
GI		 627 h = FLD_VAL(h_coef[i].hc0, 7, 0)
628 | FLD_VAL(h_coef[i].hc1, 15, 8)
629 | FLD_VAL(h_coef[i].hc2, 23, 16)
630 | FLD_VAL(h_coef[i].hc3, 31, 24);
631 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
632 | FLD_VAL(v_coef[i].vc0, 15, 8)
633 | FLD_VAL(v_coef[i].vc1, 23, 16)
634 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712 635
0d66cbb5 636 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 637 dispc_ovl_write_firh_reg(plane, i, h);
638 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 639 } else {
f0e5caab
TV		 640 dispc_ovl_write_firh2_reg(plane, i, h);
641 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 642 }
643
80c39712
TV		 644 }
645
66be8f6c
GI		 646 if (five_taps) {
647 for (i = 0; i < 8; i++) {
648 u32 v;
649 v = FLD_VAL(v_coef[i].vc00, 7, 0)
650 | FLD_VAL(v_coef[i].vc22, 15, 8);
0d66cbb5 651 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 652 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 653 else
f0e5caab 654 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 655 }
80c39712
TV		 656 }
657}
658
659static void _dispc_setup_color_conv_coef(void)
660{
ac01c29e 661 int i;
80c39712
TV		 662 const struct color_conv_coef {
663 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
664 int full_range;
665 } ctbl_bt601_5 = {
666 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
667 };
668
669 const struct color_conv_coef *ct;
670
671#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
672
673 ct = &ctbl_bt601_5;
674
ac01c29e
AT		 675 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
676 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
677 CVAL(ct->rcr, ct->ry));
678 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
679 CVAL(ct->gy, ct->rcb));
680 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
681 CVAL(ct->gcb, ct->gcr));
682 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
683 CVAL(ct->bcr, ct->by));
684 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
685 CVAL(0, ct->bcb));
686
687 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
688 11, 11);
689 }
80c39712
TV		 690
691#undef CVAL
80c39712
TV		 692}
693
694
f0e5caab 695static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 696{
9b372c2d 697 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 698}
699
f0e5caab 700static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 701{
9b372c2d 702 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 703}
704
f0e5caab 705static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 706{
707 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
708}
709
f0e5caab 710static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 711{
712 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
713}
714
f0e5caab 715static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 716{
80c39712 717 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 718
719 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 720}
721
f0e5caab 722static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 723{
80c39712 724 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 725
726 if (plane == OMAP_DSS_GFX)
727 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
728 else
729 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 730}
731
f0e5caab 732static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 733{
734 u32 val;
80c39712
TV		 735
736 BUG_ON(plane == OMAP_DSS_GFX);
737
738 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 739
740 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 741}
742
54128701
AT		 743static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
744{
745 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
746
747 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
748 return;
749
750 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
751}
752
753static void dispc_ovl_enable_zorder_planes(void)
754{
755 int i;
756
757 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
758 return;
759
760 for (i = 0; i < dss_feat_get_num_ovls(); i++)
761 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
762}
763
f0e5caab 764static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 765{
f6dc8150 766 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 767
f6dc8150 768 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 769 return;
770
9b372c2d 771 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 772}
773
f0e5caab 774static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 775{
b8c095b4 776 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 777 int shift;
f6dc8150 778 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 779
f6dc8150 780 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 781 return;
a0acb557 782
fe3cc9d6
TV		 783 shift = shifts[plane];
784 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 785}
786
f0e5caab 787static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 788{
9b372c2d 789 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 790}
791
f0e5caab 792static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 793{
9b372c2d 794 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 795}
796
f0e5caab 797static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 798 enum omap_color_mode color_mode)
799{
800 u32 m = 0;
f20e4220
AJ		 801 if (plane != OMAP_DSS_GFX) {
802 switch (color_mode) {
803 case OMAP_DSS_COLOR_NV12:
804 m = 0x0; break;
805 case OMAP_DSS_COLOR_RGB12U:
806 m = 0x1; break;
807 case OMAP_DSS_COLOR_RGBA16:
808 m = 0x2; break;
809 case OMAP_DSS_COLOR_RGBX16:
810 m = 0x4; break;
811 case OMAP_DSS_COLOR_ARGB16:
812 m = 0x5; break;
813 case OMAP_DSS_COLOR_RGB16:
814 m = 0x6; break;
815 case OMAP_DSS_COLOR_ARGB16_1555:
816 m = 0x7; break;
817 case OMAP_DSS_COLOR_RGB24U:
818 m = 0x8; break;
819 case OMAP_DSS_COLOR_RGB24P:
820 m = 0x9; break;
821 case OMAP_DSS_COLOR_YUV2:
822 m = 0xa; break;
823 case OMAP_DSS_COLOR_UYVY:
824 m = 0xb; break;
825 case OMAP_DSS_COLOR_ARGB32:
826 m = 0xc; break;
827 case OMAP_DSS_COLOR_RGBA32:
828 m = 0xd; break;
829 case OMAP_DSS_COLOR_RGBX32:
830 m = 0xe; break;
831 case OMAP_DSS_COLOR_XRGB16_1555:
832 m = 0xf; break;
833 default:
834 BUG(); break;
835 }
836 } else {
837 switch (color_mode) {
838 case OMAP_DSS_COLOR_CLUT1:
839 m = 0x0; break;
840 case OMAP_DSS_COLOR_CLUT2:
841 m = 0x1; break;
842 case OMAP_DSS_COLOR_CLUT4:
843 m = 0x2; break;
844 case OMAP_DSS_COLOR_CLUT8:
845 m = 0x3; break;
846 case OMAP_DSS_COLOR_RGB12U:
847 m = 0x4; break;
848 case OMAP_DSS_COLOR_ARGB16:
849 m = 0x5; break;
850 case OMAP_DSS_COLOR_RGB16:
851 m = 0x6; break;
852 case OMAP_DSS_COLOR_ARGB16_1555:
853 m = 0x7; break;
854 case OMAP_DSS_COLOR_RGB24U:
855 m = 0x8; break;
856 case OMAP_DSS_COLOR_RGB24P:
857 m = 0x9; break;
858 case OMAP_DSS_COLOR_YUV2:
859 m = 0xa; break;
860 case OMAP_DSS_COLOR_UYVY:
861 m = 0xb; break;
862 case OMAP_DSS_COLOR_ARGB32:
863 m = 0xc; break;
864 case OMAP_DSS_COLOR_RGBA32:
865 m = 0xd; break;
866 case OMAP_DSS_COLOR_RGBX32:
867 m = 0xe; break;
868 case OMAP_DSS_COLOR_XRGB16_1555:
869 m = 0xf; break;
870 default:
871 BUG(); break;
872 }
80c39712
TV		 873 }
874
9b372c2d 875 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 876}
877
f427984e 878void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 879{
880 int shift;
881 u32 val;
2a205f34 882 int chan = 0, chan2 = 0;
80c39712
TV		 883
884 switch (plane) {
885 case OMAP_DSS_GFX:
886 shift = 8;
887 break;
888 case OMAP_DSS_VIDEO1:
889 case OMAP_DSS_VIDEO2:
b8c095b4 890 case OMAP_DSS_VIDEO3:
80c39712
TV		 891 shift = 16;
892 break;
893 default:
894 BUG();
895 return;
896 }
897
9b372c2d 898 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 899 if (dss_has_feature(FEAT_MGR_LCD2)) {
900 switch (channel) {
901 case OMAP_DSS_CHANNEL_LCD:
902 chan = 0;
903 chan2 = 0;
904 break;
905 case OMAP_DSS_CHANNEL_DIGIT:
906 chan = 1;
907 chan2 = 0;
908 break;
909 case OMAP_DSS_CHANNEL_LCD2:
910 chan = 0;
911 chan2 = 1;
912 break;
913 default:
914 BUG();
915 }
916
917 val = FLD_MOD(val, chan, shift, shift);
918 val = FLD_MOD(val, chan2, 31, 30);
919 } else {
920 val = FLD_MOD(val, channel, shift, shift);
921 }
9b372c2d 922 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 923}
924
f0e5caab 925static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 926 enum omap_burst_size burst_size)
927{
b8c095b4 928 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 929 int shift;
80c39712 930
fe3cc9d6 931 shift = shifts[plane];
5ed8cf5b 932 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 933}
934
5ed8cf5b
TV		 935static void dispc_configure_burst_sizes(void)
936{
937 int i;
938 const int burst_size = BURST_SIZE_X8;
939
940 /* Configure burst size always to maximum size */
941 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 942 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 943}
944
f0e5caab 945u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 946{
947 unsigned unit = dss_feat_get_burst_size_unit();
948 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
949 return unit * 8;
950}
951
d3862610
M		 952void dispc_enable_gamma_table(bool enable)
953{
954 /*
955 * This is partially implemented to support only disabling of
956 * the gamma table.
957 */
958 if (enable) {
959 DSSWARN("Gamma table enabling for TV not yet supported");
960 return;
961 }
962
963 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
964}
965
26d9dd0d 966void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 967{
968 u16 reg;
969
970 if (channel == OMAP_DSS_CHANNEL_LCD)
971 reg = DISPC_CONFIG;
972 else if (channel == OMAP_DSS_CHANNEL_LCD2)
973 reg = DISPC_CONFIG2;
974 else
975 return;
976
977 REG_FLD_MOD(reg, enable, 15, 15);
978}
979
26d9dd0d 980void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 981 struct omap_dss_cpr_coefs *coefs)
982{
983 u32 coef_r, coef_g, coef_b;
984
dac57a05 985 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 986 return;
987
988 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
989 FLD_VAL(coefs->rb, 9, 0);
990 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
991 FLD_VAL(coefs->gb, 9, 0);
992 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
993 FLD_VAL(coefs->bb, 9, 0);
994
995 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
996 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
997 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
998}
999
f0e5caab 1000static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1001{
1002 u32 val;
1003
1004 BUG_ON(plane == OMAP_DSS_GFX);
1005
9b372c2d 1006 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1007 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1008 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1009}
1010
c3d92529 1011static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 1012{
b8c095b4 1013 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1014 int shift;
80c39712 1015
fe3cc9d6
TV		 1016 shift = shifts[plane];
1017 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1018}
1019
26d9dd0d 1020void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1021{
1022 u32 val;
1023 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1024 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1025 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1026}
1027
1028void dispc_set_digit_size(u16 width, u16 height)
1029{
1030 u32 val;
1031 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1032 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1033 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1034}
1035
1036static void dispc_read_plane_fifo_sizes(void)
1037{
80c39712
TV		 1038 u32 size;
1039 int plane;
a0acb557 1040 u8 start, end;
5ed8cf5b
TV		 1041 u32 unit;
1042
1043 unit = dss_feat_get_buffer_size_unit();
80c39712 1044
a0acb557 1045 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1046
e13a138b 1047 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1048 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1049 size *= unit;
80c39712
TV		 1050 dispc.fifo_size[plane] = size;
1051 }
80c39712
TV		 1052}
1053
f0e5caab 1054u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1055{
1056 return dispc.fifo_size[plane];
1057}
1058
c3d92529
AT		 1059static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1060 u32 high)
80c39712 1061{
a0acb557 1062 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1063 u32 unit;
1064
1065 unit = dss_feat_get_buffer_size_unit();
1066
1067 WARN_ON(low % unit != 0);
1068 WARN_ON(high % unit != 0);
1069
1070 low /= unit;
1071 high /= unit;
a0acb557 1072
9b372c2d
AT		 1073 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1074 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1075
80c39712
TV		 1076 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1077 plane,
9b372c2d
AT		 1078 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1079 lo_start, lo_end),
1080 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1081 hi_start, hi_end),
80c39712
TV		 1082 low, high);
1083
9b372c2d 1084 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1085 FLD_VAL(high, hi_start, hi_end) |
1086 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1087}
1088
1089void dispc_enable_fifomerge(bool enable)
1090{
80c39712
TV		 1091 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1092 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1093}
1094
f0e5caab 1095static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1096 int hinc, int vinc,
1097 enum omap_color_component color_comp)
80c39712
TV		 1098{
1099 u32 val;
80c39712 1100
0d66cbb5
AJ		 1101 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1102 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1103
0d66cbb5
AJ		 1104 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1105 &hinc_start, &hinc_end);
1106 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1107 &vinc_start, &vinc_end);
1108 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1109 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1110
0d66cbb5
AJ		 1111 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1112 } else {
1113 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1114 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1115 }
80c39712
TV		 1116}
1117
f0e5caab 1118static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1119{
1120 u32 val;
87a7484b 1121 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1122
87a7484b
AT		 1123 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1124 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1125
1126 val = FLD_VAL(vaccu, vert_start, vert_end) |
1127 FLD_VAL(haccu, hor_start, hor_end);
1128
9b372c2d 1129 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1130}
1131
f0e5caab 1132static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1133{
1134 u32 val;
87a7484b 1135 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1136
87a7484b
AT		 1137 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1138 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1139
1140 val = FLD_VAL(vaccu, vert_start, vert_end) |
1141 FLD_VAL(haccu, hor_start, hor_end);
1142
9b372c2d 1143 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1144}
1145
f0e5caab
TV		 1146static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1147 int vaccu)
ab5ca071
AJ		 1148{
1149 u32 val;
1150
1151 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1152 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1153}
1154
f0e5caab
TV		 1155static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1156 int vaccu)
ab5ca071
AJ		 1157{
1158 u32 val;
1159
1160 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1161 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1162}
80c39712 1163
f0e5caab 1164static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1165 u16 orig_width, u16 orig_height,
1166 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1167 bool five_taps, u8 rotation,
1168 enum omap_color_component color_comp)
80c39712 1169{
0d66cbb5 1170 int fir_hinc, fir_vinc;
80c39712 1171 int hscaleup, vscaleup;
80c39712
TV		 1172
1173 hscaleup = orig_width <= out_width;
1174 vscaleup = orig_height <= out_height;
1175
f0e5caab
TV		 1176 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1177 color_comp);
80c39712 1178
ed14a3ce
AJ		 1179 fir_hinc = 1024 * orig_width / out_width;
1180 fir_vinc = 1024 * orig_height / out_height;
80c39712 1181
f0e5caab 1182 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1183}
1184
f0e5caab 1185static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1186 u16 orig_width, u16 orig_height,
1187 u16 out_width, u16 out_height,
1188 bool ilace, bool five_taps,
1189 bool fieldmode, enum omap_color_mode color_mode,
1190 u8 rotation)
1191{
1192 int accu0 = 0;
1193 int accu1 = 0;
1194 u32 l;
80c39712 1195
f0e5caab 1196 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1197 out_width, out_height, five_taps,
1198 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1199 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1200
87a7484b
AT		 1201 /* RESIZEENABLE and VERTICALTAPS */
1202 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1203 l |= (orig_width != out_width) ? (1 << 5) : 0;
1204 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1205 l |= five_taps ? (1 << 21) : 0;
80c39712 1206
87a7484b
AT		 1207 /* VRESIZECONF and HRESIZECONF */
1208 if (dss_has_feature(FEAT_RESIZECONF)) {
1209 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1210 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1211 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1212 }
80c39712 1213
87a7484b
AT		 1214 /* LINEBUFFERSPLIT */
1215 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1216 l &= ~(0x1 << 22);
1217 l |= five_taps ? (1 << 22) : 0;
1218 }
80c39712 1219
9b372c2d 1220 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1221
1222 /*
1223 * field 0 = even field = bottom field
1224 * field 1 = odd field = top field
1225 */
1226 if (ilace && !fieldmode) {
1227 accu1 = 0;
0d66cbb5 1228 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1229 if (accu0 >= 1024/2) {
1230 accu1 = 1024/2;
1231 accu0 -= accu1;
1232 }
1233 }
1234
f0e5caab
TV		 1235 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1236 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1237}
1238
f0e5caab 1239static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1240 u16 orig_width, u16 orig_height,
1241 u16 out_width, u16 out_height,
1242 bool ilace, bool five_taps,
1243 bool fieldmode, enum omap_color_mode color_mode,
1244 u8 rotation)
1245{
1246 int scale_x = out_width != orig_width;
1247 int scale_y = out_height != orig_height;
1248
1249 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1250 return;
1251 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1252 color_mode != OMAP_DSS_COLOR_UYVY &&
1253 color_mode != OMAP_DSS_COLOR_NV12)) {
1254 /* reset chroma resampling for RGB formats */
1255 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1256 return;
1257 }
1258 switch (color_mode) {
1259 case OMAP_DSS_COLOR_NV12:
1260 /* UV is subsampled by 2 vertically*/
1261 orig_height >>= 1;
1262 /* UV is subsampled by 2 horz.*/
1263 orig_width >>= 1;
1264 break;
1265 case OMAP_DSS_COLOR_YUV2:
1266 case OMAP_DSS_COLOR_UYVY:
1267 /*For YUV422 with 90/270 rotation,
1268 *we don't upsample chroma
1269 */
1270 if (rotation == OMAP_DSS_ROT_0 ||
1271 rotation == OMAP_DSS_ROT_180)
1272 /* UV is subsampled by 2 hrz*/
1273 orig_width >>= 1;
1274 /* must use FIR for YUV422 if rotated */
1275 if (rotation != OMAP_DSS_ROT_0)
1276 scale_x = scale_y = true;
1277 break;
1278 default:
1279 BUG();
1280 }
1281
1282 if (out_width != orig_width)
1283 scale_x = true;
1284 if (out_height != orig_height)
1285 scale_y = true;
1286
f0e5caab 1287 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1288 out_width, out_height, five_taps,
1289 rotation, DISPC_COLOR_COMPONENT_UV);
1290
1291 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1292 (scale_x || scale_y) ? 1 : 0, 8, 8);
1293 /* set H scaling */
1294 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1295 /* set V scaling */
1296 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1297
f0e5caab
TV		 1298 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1299 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
0d66cbb5
AJ		 1300}
1301
f0e5caab 1302static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1303 u16 orig_width, u16 orig_height,
1304 u16 out_width, u16 out_height,
1305 bool ilace, bool five_taps,
1306 bool fieldmode, enum omap_color_mode color_mode,
1307 u8 rotation)
1308{
1309 BUG_ON(plane == OMAP_DSS_GFX);
1310
f0e5caab 1311 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1312 orig_width, orig_height,
1313 out_width, out_height,
1314 ilace, five_taps,
1315 fieldmode, color_mode,
1316 rotation);
1317
f0e5caab 1318 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1319 orig_width, orig_height,
1320 out_width, out_height,
1321 ilace, five_taps,
1322 fieldmode, color_mode,
1323 rotation);
1324}
1325
f0e5caab 1326static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1327 bool mirroring, enum omap_color_mode color_mode)
1328{
87a7484b
AT		 1329 bool row_repeat = false;
1330 int vidrot = 0;
1331
80c39712
TV		 1332 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1333 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1334
1335 if (mirroring) {
1336 switch (rotation) {
1337 case OMAP_DSS_ROT_0:
1338 vidrot = 2;
1339 break;
1340 case OMAP_DSS_ROT_90:
1341 vidrot = 1;
1342 break;
1343 case OMAP_DSS_ROT_180:
1344 vidrot = 0;
1345 break;
1346 case OMAP_DSS_ROT_270:
1347 vidrot = 3;
1348 break;
1349 }
1350 } else {
1351 switch (rotation) {
1352 case OMAP_DSS_ROT_0:
1353 vidrot = 0;
1354 break;
1355 case OMAP_DSS_ROT_90:
1356 vidrot = 1;
1357 break;
1358 case OMAP_DSS_ROT_180:
1359 vidrot = 2;
1360 break;
1361 case OMAP_DSS_ROT_270:
1362 vidrot = 3;
1363 break;
1364 }
1365 }
1366
80c39712 1367 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1368 row_repeat = true;
80c39712 1369 else
87a7484b 1370 row_repeat = false;
80c39712 1371 }
87a7484b 1372
9b372c2d 1373 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1374 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1375 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1376 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1377}
1378
1379static int color_mode_to_bpp(enum omap_color_mode color_mode)
1380{
1381 switch (color_mode) {
1382 case OMAP_DSS_COLOR_CLUT1:
1383 return 1;
1384 case OMAP_DSS_COLOR_CLUT2:
1385 return 2;
1386 case OMAP_DSS_COLOR_CLUT4:
1387 return 4;
1388 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1389 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1390 return 8;
1391 case OMAP_DSS_COLOR_RGB12U:
1392 case OMAP_DSS_COLOR_RGB16:
1393 case OMAP_DSS_COLOR_ARGB16:
1394 case OMAP_DSS_COLOR_YUV2:
1395 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1396 case OMAP_DSS_COLOR_RGBA16:
1397 case OMAP_DSS_COLOR_RGBX16:
1398 case OMAP_DSS_COLOR_ARGB16_1555:
1399 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1400 return 16;
1401 case OMAP_DSS_COLOR_RGB24P:
1402 return 24;
1403 case OMAP_DSS_COLOR_RGB24U:
1404 case OMAP_DSS_COLOR_ARGB32:
1405 case OMAP_DSS_COLOR_RGBA32:
1406 case OMAP_DSS_COLOR_RGBX32:
1407 return 32;
1408 default:
1409 BUG();
1410 }
1411}
1412
1413static s32 pixinc(int pixels, u8 ps)
1414{
1415 if (pixels == 1)
1416 return 1;
1417 else if (pixels > 1)
1418 return 1 + (pixels - 1) * ps;
1419 else if (pixels < 0)
1420 return 1 - (-pixels + 1) * ps;
1421 else
1422 BUG();
1423}
1424
1425static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1426 u16 screen_width,
1427 u16 width, u16 height,
1428 enum omap_color_mode color_mode, bool fieldmode,
1429 unsigned int field_offset,
1430 unsigned *offset0, unsigned *offset1,
1431 s32 *row_inc, s32 *pix_inc)
1432{
1433 u8 ps;
1434
1435 /* FIXME CLUT formats */
1436 switch (color_mode) {
1437 case OMAP_DSS_COLOR_CLUT1:
1438 case OMAP_DSS_COLOR_CLUT2:
1439 case OMAP_DSS_COLOR_CLUT4:
1440 case OMAP_DSS_COLOR_CLUT8:
1441 BUG();
1442 return;
1443 case OMAP_DSS_COLOR_YUV2:
1444 case OMAP_DSS_COLOR_UYVY:
1445 ps = 4;
1446 break;
1447 default:
1448 ps = color_mode_to_bpp(color_mode) / 8;
1449 break;
1450 }
1451
1452 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1453 width, height);
1454
1455 /*
1456 * field 0 = even field = bottom field
1457 * field 1 = odd field = top field
1458 */
1459 switch (rotation + mirror * 4) {
1460 case OMAP_DSS_ROT_0:
1461 case OMAP_DSS_ROT_180:
1462 /*
1463 * If the pixel format is YUV or UYVY divide the width
1464 * of the image by 2 for 0 and 180 degree rotation.
1465 */
1466 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1467 color_mode == OMAP_DSS_COLOR_UYVY)
1468 width = width >> 1;
1469 case OMAP_DSS_ROT_90:
1470 case OMAP_DSS_ROT_270:
1471 *offset1 = 0;
1472 if (field_offset)
1473 *offset0 = field_offset * screen_width * ps;
1474 else
1475 *offset0 = 0;
1476
1477 *row_inc = pixinc(1 + (screen_width - width) +
1478 (fieldmode ? screen_width : 0),
1479 ps);
1480 *pix_inc = pixinc(1, ps);
1481 break;
1482
1483 case OMAP_DSS_ROT_0 + 4:
1484 case OMAP_DSS_ROT_180 + 4:
1485 /* If the pixel format is YUV or UYVY divide the width
1486 * of the image by 2 for 0 degree and 180 degree
1487 */
1488 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1489 color_mode == OMAP_DSS_COLOR_UYVY)
1490 width = width >> 1;
1491 case OMAP_DSS_ROT_90 + 4:
1492 case OMAP_DSS_ROT_270 + 4:
1493 *offset1 = 0;
1494 if (field_offset)
1495 *offset0 = field_offset * screen_width * ps;
1496 else
1497 *offset0 = 0;
1498 *row_inc = pixinc(1 - (screen_width + width) -
1499 (fieldmode ? screen_width : 0),
1500 ps);
1501 *pix_inc = pixinc(1, ps);
1502 break;
1503
1504 default:
1505 BUG();
1506 }
1507}
1508
1509static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1510 u16 screen_width,
1511 u16 width, u16 height,
1512 enum omap_color_mode color_mode, bool fieldmode,
1513 unsigned int field_offset,
1514 unsigned *offset0, unsigned *offset1,
1515 s32 *row_inc, s32 *pix_inc)
1516{
1517 u8 ps;
1518 u16 fbw, fbh;
1519
1520 /* FIXME CLUT formats */
1521 switch (color_mode) {
1522 case OMAP_DSS_COLOR_CLUT1:
1523 case OMAP_DSS_COLOR_CLUT2:
1524 case OMAP_DSS_COLOR_CLUT4:
1525 case OMAP_DSS_COLOR_CLUT8:
1526 BUG();
1527 return;
1528 default:
1529 ps = color_mode_to_bpp(color_mode) / 8;
1530 break;
1531 }
1532
1533 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1534 width, height);
1535
1536 /* width & height are overlay sizes, convert to fb sizes */
1537
1538 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1539 fbw = width;
1540 fbh = height;
1541 } else {
1542 fbw = height;
1543 fbh = width;
1544 }
1545
1546 /*
1547 * field 0 = even field = bottom field
1548 * field 1 = odd field = top field
1549 */
1550 switch (rotation + mirror * 4) {
1551 case OMAP_DSS_ROT_0:
1552 *offset1 = 0;
1553 if (field_offset)
1554 *offset0 = *offset1 + field_offset * screen_width * ps;
1555 else
1556 *offset0 = *offset1;
1557 *row_inc = pixinc(1 + (screen_width - fbw) +
1558 (fieldmode ? screen_width : 0),
1559 ps);
1560 *pix_inc = pixinc(1, ps);
1561 break;
1562 case OMAP_DSS_ROT_90:
1563 *offset1 = screen_width * (fbh - 1) * ps;
1564 if (field_offset)
1565 *offset0 = *offset1 + field_offset * ps;
1566 else
1567 *offset0 = *offset1;
1568 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1569 (fieldmode ? 1 : 0), ps);
1570 *pix_inc = pixinc(-screen_width, ps);
1571 break;
1572 case OMAP_DSS_ROT_180:
1573 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1574 if (field_offset)
1575 *offset0 = *offset1 - field_offset * screen_width * ps;
1576 else
1577 *offset0 = *offset1;
1578 *row_inc = pixinc(-1 -
1579 (screen_width - fbw) -
1580 (fieldmode ? screen_width : 0),
1581 ps);
1582 *pix_inc = pixinc(-1, ps);
1583 break;
1584 case OMAP_DSS_ROT_270:
1585 *offset1 = (fbw - 1) * ps;
1586 if (field_offset)
1587 *offset0 = *offset1 - field_offset * ps;
1588 else
1589 *offset0 = *offset1;
1590 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1591 (fieldmode ? 1 : 0), ps);
1592 *pix_inc = pixinc(screen_width, ps);
1593 break;
1594
1595 /* mirroring */
1596 case OMAP_DSS_ROT_0 + 4:
1597 *offset1 = (fbw - 1) * ps;
1598 if (field_offset)
1599 *offset0 = *offset1 + field_offset * screen_width * ps;
1600 else
1601 *offset0 = *offset1;
1602 *row_inc = pixinc(screen_width * 2 - 1 +
1603 (fieldmode ? screen_width : 0),
1604 ps);
1605 *pix_inc = pixinc(-1, ps);
1606 break;
1607
1608 case OMAP_DSS_ROT_90 + 4:
1609 *offset1 = 0;
1610 if (field_offset)
1611 *offset0 = *offset1 + field_offset * ps;
1612 else
1613 *offset0 = *offset1;
1614 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1615 (fieldmode ? 1 : 0),
1616 ps);
1617 *pix_inc = pixinc(screen_width, ps);
1618 break;
1619
1620 case OMAP_DSS_ROT_180 + 4:
1621 *offset1 = screen_width * (fbh - 1) * ps;
1622 if (field_offset)
1623 *offset0 = *offset1 - field_offset * screen_width * ps;
1624 else
1625 *offset0 = *offset1;
1626 *row_inc = pixinc(1 - screen_width * 2 -
1627 (fieldmode ? screen_width : 0),
1628 ps);
1629 *pix_inc = pixinc(1, ps);
1630 break;
1631
1632 case OMAP_DSS_ROT_270 + 4:
1633 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1634 if (field_offset)
1635 *offset0 = *offset1 - field_offset * ps;
1636 else
1637 *offset0 = *offset1;
1638 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1639 (fieldmode ? 1 : 0),
1640 ps);
1641 *pix_inc = pixinc(-screen_width, ps);
1642 break;
1643
1644 default:
1645 BUG();
1646 }
1647}
1648
ff1b2cde
SS		 1649static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1650 u16 height, u16 out_width, u16 out_height,
1651 enum omap_color_mode color_mode)
80c39712
TV		 1652{
1653 u32 fclk = 0;
26d9dd0d 1654 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1655
1656 if (height > out_height) {
ebdc5249
AT		 1657 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1658 unsigned int ppl = dssdev->panel.timings.x_res;
80c39712
TV		 1659
1660 tmp = pclk * height * out_width;
1661 do_div(tmp, 2 * out_height * ppl);
1662 fclk = tmp;
1663
2d9c5597
VS		 1664 if (height > 2 * out_height) {
1665 if (ppl == out_width)
1666 return 0;
1667
80c39712
TV		 1668 tmp = pclk * (height - 2 * out_height) * out_width;
1669 do_div(tmp, 2 * out_height * (ppl - out_width));
1670 fclk = max(fclk, (u32) tmp);
1671 }
1672 }
1673
1674 if (width > out_width) {
1675 tmp = pclk * width;
1676 do_div(tmp, out_width);
1677 fclk = max(fclk, (u32) tmp);
1678
1679 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1680 fclk <<= 1;
1681 }
1682
1683 return fclk;
1684}
1685
ff1b2cde
SS		 1686static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1687 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1688{
1689 unsigned int hf, vf;
1690
1691 /*
1692 * FIXME how to determine the 'A' factor
1693 * for the no downscaling case ?
1694 */
1695
1696 if (width > 3 * out_width)
1697 hf = 4;
1698 else if (width > 2 * out_width)
1699 hf = 3;
1700 else if (width > out_width)
1701 hf = 2;
1702 else
1703 hf = 1;
1704
1705 if (height > out_height)
1706 vf = 2;
1707 else
1708 vf = 1;
1709
26d9dd0d 1710 return dispc_mgr_pclk_rate(channel) * vf * hf;
80c39712
TV		 1711}
1712
79ad75f2
AT		 1713static int dispc_ovl_calc_scaling(enum omap_plane plane,
1714 enum omap_channel channel, u16 width, u16 height,
1715 u16 out_width, u16 out_height,
1716 enum omap_color_mode color_mode, bool *five_taps)
1717{
1718 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1719 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
79ad75f2
AT		 1720 unsigned long fclk = 0;
1721
f95cb5eb
TV		 1722 if (width == out_width && height == out_height)
1723 return 0;
1724
1725 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1726 return -EINVAL;
79ad75f2
AT		 1727
1728 if (out_width < width / maxdownscale ||
1729 out_width > width * 8)
1730 return -EINVAL;
1731
1732 if (out_height < height / maxdownscale ||
1733 out_height > height * 8)
1734 return -EINVAL;
1735
1736 /* Must use 5-tap filter? */
1737 *five_taps = height > out_height * 2;
1738
1739 if (!*five_taps) {
1740 fclk = calc_fclk(channel, width, height, out_width,
1741 out_height);
1742
1743 /* Try 5-tap filter if 3-tap fclk is too high */
1744 if (cpu_is_omap34xx() && height > out_height &&
1745 fclk > dispc_fclk_rate())
1746 *five_taps = true;
1747 }
1748
1749 if (width > (2048 >> *five_taps)) {
1750 DSSERR("failed to set up scaling, fclk too low\n");
1751 return -EINVAL;
1752 }
1753
1754 if (*five_taps)
1755 fclk = calc_fclk_five_taps(channel, width, height,
1756 out_width, out_height, color_mode);
1757
1758 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1759 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1760
1761 if (!fclk || fclk > dispc_fclk_rate()) {
1762 DSSERR("failed to set up scaling, "
1763 "required fclk rate = %lu Hz, "
1764 "current fclk rate = %lu Hz\n",
1765 fclk, dispc_fclk_rate());
1766 return -EINVAL;
1767 }
1768
1769 return 0;
1770}
1771
a4273b7c 1772int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
c3d92529
AT		 1773 bool ilace, enum omap_channel channel, bool replication,
1774 u32 fifo_low, u32 fifo_high)
80c39712 1775{
79ad75f2
AT		 1776 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1777 bool five_taps = false;
80c39712 1778 bool fieldmode = 0;
79ad75f2 1779 int r, cconv = 0;
80c39712
TV		 1780 unsigned offset0, offset1;
1781 s32 row_inc;
1782 s32 pix_inc;
a4273b7c 1783 u16 frame_height = oi->height;
80c39712
TV		 1784 unsigned int field_offset = 0;
1785
a4273b7c 1786 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
c3d92529
AT		 1787 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1788 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1789 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1790 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1791 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
e6d80f95 1792
a4273b7c 1793 if (oi->paddr == 0)
80c39712
TV		 1794 return -EINVAL;
1795
a4273b7c 1796 if (ilace && oi->height == oi->out_height)
80c39712
TV		 1797 fieldmode = 1;
1798
1799 if (ilace) {
1800 if (fieldmode)
a4273b7c
AT		 1801 oi->height /= 2;
1802 oi->pos_y /= 2;
1803 oi->out_height /= 2;
80c39712
TV		 1804
1805 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1806 "out_height %d\n",
a4273b7c 1807 oi->height, oi->pos_y, oi->out_height);
80c39712
TV		 1808 }
1809
a4273b7c 1810 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 1811 return -EINVAL;
1812
79ad75f2
AT		 1813 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1814 oi->out_width, oi->out_height, oi->color_mode,
1815 &five_taps);
1816 if (r)
1817 return r;
80c39712 1818
79ad75f2
AT		 1819 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1820 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1821 oi->color_mode == OMAP_DSS_COLOR_NV12)
1822 cconv = 1;
80c39712
TV		 1823
1824 if (ilace && !fieldmode) {
1825 /*
1826 * when downscaling the bottom field may have to start several
1827 * source lines below the top field. Unfortunately ACCUI
1828 * registers will only hold the fractional part of the offset
1829 * so the integer part must be added to the base address of the
1830 * bottom field.
1831 */
a4273b7c 1832 if (!oi->height || oi->height == oi->out_height)
80c39712
TV		 1833 field_offset = 0;
1834 else
a4273b7c 1835 field_offset = oi->height / oi->out_height / 2;
80c39712
TV		 1836 }
1837
1838 /* Fields are independent but interleaved in memory. */
1839 if (fieldmode)
1840 field_offset = 1;
1841
a4273b7c
AT		 1842 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1843 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1844 oi->screen_width, oi->width, frame_height,
1845 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1846 &offset0, &offset1, &row_inc, &pix_inc);
1847 else
a4273b7c
AT		 1848 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1849 oi->screen_width, oi->width, frame_height,
1850 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1851 &offset0, &offset1, &row_inc, &pix_inc);
1852
1853 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1854 offset0, offset1, row_inc, pix_inc);
1855
a4273b7c 1856 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 1857
a4273b7c
AT		 1858 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1859 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 1860
a4273b7c
AT		 1861 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1862 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1863 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 1864 }
1865
1866
f0e5caab
TV		 1867 dispc_ovl_set_row_inc(plane, row_inc);
1868 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 1869
a4273b7c
AT		 1870 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1871 oi->height, oi->out_width, oi->out_height);
80c39712 1872
a4273b7c 1873 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 1874
a4273b7c 1875 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
80c39712 1876
79ad75f2 1877 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
a4273b7c
AT		 1878 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1879 oi->out_width, oi->out_height,
0d66cbb5 1880 ilace, five_taps, fieldmode,
a4273b7c
AT		 1881 oi->color_mode, oi->rotation);
1882 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
f0e5caab 1883 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 1884 }
1885
a4273b7c
AT		 1886 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1887 oi->color_mode);
80c39712 1888
54128701 1889 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 1890 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1891 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 1892
f0e5caab 1893 dispc_ovl_set_channel_out(plane, channel);
8fa8031c 1894
c3d92529
AT		 1895 dispc_ovl_enable_replication(plane, replication);
1896 dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1897
80c39712
TV		 1898 return 0;
1899}
1900
f0e5caab 1901int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 1902{
e6d80f95
TV		 1903 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1904
9b372c2d 1905 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 1906
1907 return 0;
80c39712
TV		 1908}
1909
1910static void dispc_disable_isr(void *data, u32 mask)
1911{
1912 struct completion *compl = data;
1913 complete(compl);
1914}
1915
2a205f34 1916static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1917{
b6a44e77 1918 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 1919 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 1920 /* flush posted write */
1921 dispc_read_reg(DISPC_CONTROL2);
1922 } else {
2a205f34 1923 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 1924 dispc_read_reg(DISPC_CONTROL);
1925 }
80c39712
TV		 1926}
1927
26d9dd0d 1928static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1929{
1930 struct completion frame_done_completion;
1931 bool is_on;
1932 int r;
2a205f34 1933 u32 irq;
80c39712 1934
80c39712
TV		 1935 /* When we disable LCD output, we need to wait until frame is done.
1936 * Otherwise the DSS is still working, and turning off the clocks
1937 * prevents DSS from going to OFF mode */
2a205f34
SS		 1938 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1939 REG_GET(DISPC_CONTROL2, 0, 0) :
1940 REG_GET(DISPC_CONTROL, 0, 0);
1941
1942 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1943 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1944
1945 if (!enable && is_on) {
1946 init_completion(&frame_done_completion);
1947
1948 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1949 &frame_done_completion, irq);
80c39712
TV		 1950
1951 if (r)
1952 DSSERR("failed to register FRAMEDONE isr\n");
1953 }
1954
2a205f34 1955 _enable_lcd_out(channel, enable);
80c39712
TV		 1956
1957 if (!enable && is_on) {
1958 if (!wait_for_completion_timeout(&frame_done_completion,
1959 msecs_to_jiffies(100)))
1960 DSSERR("timeout waiting for FRAME DONE\n");
1961
1962 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1963 &frame_done_completion, irq);
80c39712
TV		 1964
1965 if (r)
1966 DSSERR("failed to unregister FRAMEDONE isr\n");
1967 }
80c39712
TV		 1968}
1969
1970static void _enable_digit_out(bool enable)
1971{
1972 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 1973 /* flush posted write */
1974 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 1975}
1976
26d9dd0d 1977static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 1978{
1979 struct completion frame_done_completion;
e82b090b
TV		 1980 enum dss_hdmi_venc_clk_source_select src;
1981 int r, i;
1982 u32 irq_mask;
1983 int num_irqs;
80c39712 1984
e6d80f95 1985 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 1986 return;
80c39712 1987
e82b090b
TV		 1988 src = dss_get_hdmi_venc_clk_source();
1989
80c39712
TV		 1990 if (enable) {
1991 unsigned long flags;
1992 /* When we enable digit output, we'll get an extra digit
1993 * sync lost interrupt, that we need to ignore */
1994 spin_lock_irqsave(&dispc.irq_lock, flags);
1995 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1996 _omap_dispc_set_irqs();
1997 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1998 }
1999
2000 /* When we disable digit output, we need to wait until fields are done.
2001 * Otherwise the DSS is still working, and turning off the clocks
2002 * prevents DSS from going to OFF mode. And when enabling, we need to
2003 * wait for the extra sync losts */
2004 init_completion(&frame_done_completion);
2005
e82b090b
TV		 2006 if (src == DSS_HDMI_M_PCLK && enable == false) {
2007 irq_mask = DISPC_IRQ_FRAMEDONETV;
2008 num_irqs = 1;
2009 } else {
2010 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2011 /* XXX I understand from TRM that we should only wait for the
2012 * current field to complete. But it seems we have to wait for
2013 * both fields */
2014 num_irqs = 2;
2015 }
2016
80c39712 2017 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2018 irq_mask);
80c39712 2019 if (r)
e82b090b 2020 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2021
2022 _enable_digit_out(enable);
2023
e82b090b
TV		 2024 for (i = 0; i < num_irqs; ++i) {
2025 if (!wait_for_completion_timeout(&frame_done_completion,
2026 msecs_to_jiffies(100)))
2027 DSSERR("timeout waiting for digit out to %s\n",
2028 enable ? "start" : "stop");
2029 }
80c39712 2030
e82b090b
TV		 2031 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2032 irq_mask);
80c39712 2033 if (r)
e82b090b 2034 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2035
2036 if (enable) {
2037 unsigned long flags;
2038 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2039 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2040 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2041 _omap_dispc_set_irqs();
2042 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2043 }
80c39712
TV		 2044}
2045
26d9dd0d 2046bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2047{
2048 if (channel == OMAP_DSS_CHANNEL_LCD)
2049 return !!REG_GET(DISPC_CONTROL, 0, 0);
2050 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2051 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2052 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2053 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2054 else
2055 BUG();
2056}
2057
26d9dd0d 2058void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2059{
dac57a05 2060 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2061 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2062 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2063 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2064 else
2065 BUG();
2066}
2067
80c39712
TV		 2068void dispc_lcd_enable_signal_polarity(bool act_high)
2069{
6ced40bf
AT		 2070 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2071 return;
2072
80c39712 2073 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2074}
2075
2076void dispc_lcd_enable_signal(bool enable)
2077{
6ced40bf
AT		 2078 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2079 return;
2080
80c39712 2081 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2082}
2083
2084void dispc_pck_free_enable(bool enable)
2085{
6ced40bf
AT		 2086 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2087 return;
2088
80c39712 2089 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2090}
2091
26d9dd0d 2092void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2093{
2a205f34
SS		 2094 if (channel == OMAP_DSS_CHANNEL_LCD2)
2095 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2096 else
2097 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2098}
2099
2100
26d9dd0d 2101void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2102 enum omap_lcd_display_type type)
80c39712
TV		 2103{
2104 int mode;
2105
2106 switch (type) {
2107 case OMAP_DSS_LCD_DISPLAY_STN:
2108 mode = 0;
2109 break;
2110
2111 case OMAP_DSS_LCD_DISPLAY_TFT:
2112 mode = 1;
2113 break;
2114
2115 default:
2116 BUG();
2117 return;
2118 }
2119
2a205f34
SS		 2120 if (channel == OMAP_DSS_CHANNEL_LCD2)
2121 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2122 else
2123 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2124}
2125
2126void dispc_set_loadmode(enum omap_dss_load_mode mode)
2127{
80c39712 2128 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2129}
2130
2131
26d9dd0d 2132void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2133{
8613b000 2134 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2135}
2136
26d9dd0d 2137u32 dispc_mgr_get_default_color(enum omap_channel channel)
80c39712 2138{
80c39712
TV		 2139 u32 l;
2140
2141 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2142 channel != OMAP_DSS_CHANNEL_LCD &&
2143 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712 2144
8613b000 2145 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2146
2147 return l;
2148}
2149
26d9dd0d 2150void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2151 enum omap_dss_trans_key_type type,
2152 u32 trans_key)
2153{
80c39712
TV		 2154 if (ch == OMAP_DSS_CHANNEL_LCD)
2155 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2156 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2157 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2158 else /* OMAP_DSS_CHANNEL_LCD2 */
2159 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2160
8613b000 2161 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2162}
2163
26d9dd0d 2164void dispc_mgr_get_trans_key(enum omap_channel ch,
80c39712
TV		 2165 enum omap_dss_trans_key_type *type,
2166 u32 *trans_key)
2167{
80c39712
TV		 2168 if (type) {
2169 if (ch == OMAP_DSS_CHANNEL_LCD)
2170 *type = REG_GET(DISPC_CONFIG, 11, 11);
2171 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2172 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2173 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2174 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2175 else
2176 BUG();
2177 }
2178
2179 if (trans_key)
8613b000 2180 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2181}
2182
26d9dd0d 2183void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2184{
80c39712
TV		 2185 if (ch == OMAP_DSS_CHANNEL_LCD)
2186 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2187 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2188 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2189 else /* OMAP_DSS_CHANNEL_LCD2 */
2190 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2191}
11354dd5
AT		 2192
2193void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable)
80c39712 2194{
11354dd5 2195 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2196 return;
2197
80c39712
TV		 2198 if (ch == OMAP_DSS_CHANNEL_LCD)
2199 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2200 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2201 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2202}
11354dd5
AT		 2203
2204bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch)
80c39712
TV		 2205{
2206 bool enabled;
2207
11354dd5 2208 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2209 return false;
2210
80c39712
TV		 2211 if (ch == OMAP_DSS_CHANNEL_LCD)
2212 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2213 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2214 enabled = REG_GET(DISPC_CONFIG, 19, 19);
80c39712
TV		 2215 else
2216 BUG();
80c39712
TV		 2217
2218 return enabled;
80c39712
TV		 2219}
2220
26d9dd0d 2221bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
80c39712
TV		 2222{
2223 bool enabled;
2224
80c39712
TV		 2225 if (ch == OMAP_DSS_CHANNEL_LCD)
2226 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2227 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2228 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2229 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2230 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2231 else
2232 BUG();
80c39712
TV		 2233
2234 return enabled;
2235}
2236
2237
26d9dd0d 2238void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2239{
2240 int code;
2241
2242 switch (data_lines) {
2243 case 12:
2244 code = 0;
2245 break;
2246 case 16:
2247 code = 1;
2248 break;
2249 case 18:
2250 code = 2;
2251 break;
2252 case 24:
2253 code = 3;
2254 break;
2255 default:
2256 BUG();
2257 return;
2258 }
2259
2a205f34
SS		 2260 if (channel == OMAP_DSS_CHANNEL_LCD2)
2261 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2262 else
2263 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2264}
2265
569969d6 2266void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2267{
2268 u32 l;
569969d6 2269 int gpout0, gpout1;
80c39712
TV		 2270
2271 switch (mode) {
569969d6
AT		 2272 case DSS_IO_PAD_MODE_RESET:
2273 gpout0 = 0;
2274 gpout1 = 0;
80c39712 2275 break;
569969d6
AT		 2276 case DSS_IO_PAD_MODE_RFBI:
2277 gpout0 = 1;
80c39712
TV		 2278 gpout1 = 0;
2279 break;
569969d6
AT		 2280 case DSS_IO_PAD_MODE_BYPASS:
2281 gpout0 = 1;
80c39712
TV		 2282 gpout1 = 1;
2283 break;
80c39712
TV		 2284 default:
2285 BUG();
2286 return;
2287 }
2288
569969d6
AT		 2289 l = dispc_read_reg(DISPC_CONTROL);
2290 l = FLD_MOD(l, gpout0, 15, 15);
2291 l = FLD_MOD(l, gpout1, 16, 16);
2292 dispc_write_reg(DISPC_CONTROL, l);
2293}
2294
2295void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2296{
2297 if (channel == OMAP_DSS_CHANNEL_LCD2)
2298 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2299 else
2300 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2301}
2302
2303static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2304 int vsw, int vfp, int vbp)
2305{
2306 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2307 if (hsw < 1 || hsw > 64 ||
2308 hfp < 1 || hfp > 256 ||
2309 hbp < 1 || hbp > 256 ||
2310 vsw < 1 || vsw > 64 ||
2311 vfp < 0 || vfp > 255 ||
2312 vbp < 0 || vbp > 255)
2313 return false;
2314 } else {
2315 if (hsw < 1 || hsw > 256 ||
2316 hfp < 1 || hfp > 4096 ||
2317 hbp < 1 || hbp > 4096 ||
2318 vsw < 1 || vsw > 256 ||
2319 vfp < 0 || vfp > 4095 ||
2320 vbp < 0 || vbp > 4095)
2321 return false;
2322 }
2323
2324 return true;
2325}
2326
2327bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2328{
2329 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2330 timings->hbp, timings->vsw,
2331 timings->vfp, timings->vbp);
2332}
2333
26d9dd0d 2334static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2335 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2336{
2337 u32 timing_h, timing_v;
2338
2339 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2340 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2341 FLD_VAL(hbp-1, 27, 20);
2342
2343 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2344 FLD_VAL(vbp, 27, 20);
2345 } else {
2346 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2347 FLD_VAL(hbp-1, 31, 20);
2348
2349 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2350 FLD_VAL(vbp, 31, 20);
2351 }
2352
64ba4f74
SS		 2353 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2354 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2355}
2356
2357/* change name to mode? */
26d9dd0d 2358void dispc_mgr_set_lcd_timings(enum omap_channel channel,
64ba4f74 2359 struct omap_video_timings *timings)
80c39712
TV		 2360{
2361 unsigned xtot, ytot;
2362 unsigned long ht, vt;
2363
2364 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2365 timings->hbp, timings->vsw,
2366 timings->vfp, timings->vbp))
2367 BUG();
2368
26d9dd0d 2369 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
64ba4f74
SS		 2370 timings->hbp, timings->vsw, timings->vfp,
2371 timings->vbp);
80c39712 2372
26d9dd0d 2373 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2374
2375 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2376 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2377
2378 ht = (timings->pixel_clock * 1000) / xtot;
2379 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2380
2a205f34
SS		 2381 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2382 timings->y_res);
80c39712
TV		 2383 DSSDBG("pck %u\n", timings->pixel_clock);
2384 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2385 timings->hsw, timings->hfp, timings->hbp,
2386 timings->vsw, timings->vfp, timings->vbp);
2387
2388 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2389}
2390
26d9dd0d 2391static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2392 u16 pck_div)
80c39712
TV		 2393{
2394 BUG_ON(lck_div < 1);
9eaaf207 2395 BUG_ON(pck_div < 1);
80c39712 2396
ce7fa5eb 2397 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2398 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2399}
2400
26d9dd0d 2401static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2402 int *pck_div)
80c39712
TV		 2403{
2404 u32 l;
ce7fa5eb 2405 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2406 *lck_div = FLD_GET(l, 23, 16);
2407 *pck_div = FLD_GET(l, 7, 0);
2408}
2409
2410unsigned long dispc_fclk_rate(void)
2411{
a72b64b9 2412 struct platform_device *dsidev;
80c39712
TV		 2413 unsigned long r = 0;
2414
66534e8e 2415 switch (dss_get_dispc_clk_source()) {
89a35e51 2416 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2417 r = clk_get_rate(dispc.dss_clk);
66534e8e 2418 break;
89a35e51 2419 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2420 dsidev = dsi_get_dsidev_from_id(0);
2421 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2422 break;
5a8b572d
AT		 2423 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2424 dsidev = dsi_get_dsidev_from_id(1);
2425 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2426 break;
66534e8e
TA		 2427 default:
2428 BUG();
2429 }
2430
80c39712
TV		 2431 return r;
2432}
2433
26d9dd0d 2434unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2435{
a72b64b9 2436 struct platform_device *dsidev;
80c39712
TV		 2437 int lcd;
2438 unsigned long r;
2439 u32 l;
2440
ce7fa5eb 2441 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2442
2443 lcd = FLD_GET(l, 23, 16);
2444
ea75159e 2445 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2446 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2447 r = clk_get_rate(dispc.dss_clk);
ea75159e 2448 break;
89a35e51 2449 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2450 dsidev = dsi_get_dsidev_from_id(0);
2451 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2452 break;
5a8b572d
AT		 2453 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2454 dsidev = dsi_get_dsidev_from_id(1);
2455 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2456 break;
ea75159e
TA		 2457 default:
2458 BUG();
2459 }
80c39712
TV		 2460
2461 return r / lcd;
2462}
2463
26d9dd0d 2464unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2465{
80c39712 2466 unsigned long r;
80c39712 2467
c3dc6a7a
AT		 2468 if (dispc_mgr_is_lcd(channel)) {
2469 int pcd;
2470 u32 l;
80c39712 2471
c3dc6a7a 2472 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2473
c3dc6a7a 2474 pcd = FLD_GET(l, 7, 0);
80c39712 2475
c3dc6a7a
AT		 2476 r = dispc_mgr_lclk_rate(channel);
2477
2478 return r / pcd;
2479 } else {
2480 struct omap_dss_device *dssdev =
2481 dispc_mgr_get_device(channel);
2482
2483 switch (dssdev->type) {
2484 case OMAP_DISPLAY_TYPE_VENC:
2485 return venc_get_pixel_clock();
2486 case OMAP_DISPLAY_TYPE_HDMI:
2487 return hdmi_get_pixel_clock();
2488 default:
2489 BUG();
2490 }
2491 }
80c39712
TV		 2492}
2493
2494void dispc_dump_clocks(struct seq_file *s)
2495{
2496 int lcd, pcd;
0cf35df3 2497 u32 l;
89a35e51
AT		 2498 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2499 enum omap_dss_clk_source lcd_clk_src;
80c39712 2500
4fbafaf3
TV		 2501 if (dispc_runtime_get())
2502 return;
80c39712 2503
80c39712
TV		 2504 seq_printf(s, "- DISPC -\n");
2505
067a57e4
AT		 2506 seq_printf(s, "dispc fclk source = %s (%s)\n",
2507 dss_get_generic_clk_source_name(dispc_clk_src),
2508 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2509
2510 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2511
0cf35df3
MR		 2512 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2513 seq_printf(s, "- DISPC-CORE-CLK -\n");
2514 l = dispc_read_reg(DISPC_DIVISOR);
2515 lcd = FLD_GET(l, 23, 16);
2516
2517 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2518 (dispc_fclk_rate()/lcd), lcd);
2519 }
2a205f34
SS		 2520 seq_printf(s, "- LCD1 -\n");
2521
ea75159e
TA		 2522 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2523
2524 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2525 dss_get_generic_clk_source_name(lcd_clk_src),
2526 dss_feat_get_clk_source_name(lcd_clk_src));
2527
26d9dd0d 2528 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2529
ff1b2cde 2530 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2531 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2532 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2533 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2534 if (dss_has_feature(FEAT_MGR_LCD2)) {
2535 seq_printf(s, "- LCD2 -\n");
2536
ea75159e
TA		 2537 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2538
2539 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2540 dss_get_generic_clk_source_name(lcd_clk_src),
2541 dss_feat_get_clk_source_name(lcd_clk_src));
2542
26d9dd0d 2543 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2544
2a205f34 2545 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2546 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2547 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2548 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2549 }
4fbafaf3
TV		 2550
2551 dispc_runtime_put();
80c39712
TV		 2552}
2553
dfc0fd8d
TV		 2554#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2555void dispc_dump_irqs(struct seq_file *s)
2556{
2557 unsigned long flags;
2558 struct dispc_irq_stats stats;
2559
2560 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2561
2562 stats = dispc.irq_stats;
2563 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2564 dispc.irq_stats.last_reset = jiffies;
2565
2566 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2567
2568 seq_printf(s, "period %u ms\n",
2569 jiffies_to_msecs(jiffies - stats.last_reset));
2570
2571 seq_printf(s, "irqs %d\n", stats.irq_count);
2572#define PIS(x) \
2573 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2574
2575 PIS(FRAMEDONE);
2576 PIS(VSYNC);
2577 PIS(EVSYNC_EVEN);
2578 PIS(EVSYNC_ODD);
2579 PIS(ACBIAS_COUNT_STAT);
2580 PIS(PROG_LINE_NUM);
2581 PIS(GFX_FIFO_UNDERFLOW);
2582 PIS(GFX_END_WIN);
2583 PIS(PAL_GAMMA_MASK);
2584 PIS(OCP_ERR);
2585 PIS(VID1_FIFO_UNDERFLOW);
2586 PIS(VID1_END_WIN);
2587 PIS(VID2_FIFO_UNDERFLOW);
2588 PIS(VID2_END_WIN);
b8c095b4
AT		 2589 if (dss_feat_get_num_ovls() > 3) {
2590 PIS(VID3_FIFO_UNDERFLOW);
2591 PIS(VID3_END_WIN);
2592 }
dfc0fd8d
TV		 2593 PIS(SYNC_LOST);
2594 PIS(SYNC_LOST_DIGIT);
2595 PIS(WAKEUP);
2a205f34
SS		 2596 if (dss_has_feature(FEAT_MGR_LCD2)) {
2597 PIS(FRAMEDONE2);
2598 PIS(VSYNC2);
2599 PIS(ACBIAS_COUNT_STAT2);
2600 PIS(SYNC_LOST2);
2601 }
dfc0fd8d
TV		 2602#undef PIS
2603}
dfc0fd8d
TV		 2604#endif
2605
80c39712
TV		 2606void dispc_dump_regs(struct seq_file *s)
2607{
4dd2da15
AT		 2608 int i, j;
2609 const char *mgr_names[] = {
2610 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2611 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2612 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2613 };
2614 const char *ovl_names[] = {
2615 [OMAP_DSS_GFX] = "GFX",
2616 [OMAP_DSS_VIDEO1] = "VID1",
2617 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2618 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2619 };
2620 const char **p_names;
2621
9b372c2d 2622#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2623
4fbafaf3
TV		 2624 if (dispc_runtime_get())
2625 return;
80c39712 2626
5010be80 2627 /* DISPC common registers */
80c39712
TV		 2628 DUMPREG(DISPC_REVISION);
2629 DUMPREG(DISPC_SYSCONFIG);
2630 DUMPREG(DISPC_SYSSTATUS);
2631 DUMPREG(DISPC_IRQSTATUS);
2632 DUMPREG(DISPC_IRQENABLE);
2633 DUMPREG(DISPC_CONTROL);
2634 DUMPREG(DISPC_CONFIG);
2635 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2636 DUMPREG(DISPC_LINE_STATUS);
2637 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2638 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2639 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2640 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2641 if (dss_has_feature(FEAT_MGR_LCD2)) {
2642 DUMPREG(DISPC_CONTROL2);
2643 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2644 }
2645
2646#undef DUMPREG
2647
2648#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2649#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2650 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2651 dispc_read_reg(DISPC_REG(i, r)))
2652
4dd2da15 2653 p_names = mgr_names;
5010be80 2654
4dd2da15
AT		 2655 /* DISPC channel specific registers */
2656 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2657 DUMPREG(i, DISPC_DEFAULT_COLOR);
2658 DUMPREG(i, DISPC_TRANS_COLOR);
2659 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2660
4dd2da15
AT		 2661 if (i == OMAP_DSS_CHANNEL_DIGIT)
2662 continue;
5010be80 2663
4dd2da15
AT		 2664 DUMPREG(i, DISPC_DEFAULT_COLOR);
2665 DUMPREG(i, DISPC_TRANS_COLOR);
2666 DUMPREG(i, DISPC_TIMING_H);
2667 DUMPREG(i, DISPC_TIMING_V);
2668 DUMPREG(i, DISPC_POL_FREQ);
2669 DUMPREG(i, DISPC_DIVISORo);
2670 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2671
4dd2da15
AT		 2672 DUMPREG(i, DISPC_DATA_CYCLE1);
2673 DUMPREG(i, DISPC_DATA_CYCLE2);
2674 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2675
332e9d70 2676 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2677 DUMPREG(i, DISPC_CPR_COEF_R);
2678 DUMPREG(i, DISPC_CPR_COEF_G);
2679 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2680 }
2a205f34 2681 }
80c39712 2682
4dd2da15
AT		 2683 p_names = ovl_names;
2684
2685 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2686 DUMPREG(i, DISPC_OVL_BA0);
2687 DUMPREG(i, DISPC_OVL_BA1);
2688 DUMPREG(i, DISPC_OVL_POSITION);
2689 DUMPREG(i, DISPC_OVL_SIZE);
2690 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2691 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2692 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2693 DUMPREG(i, DISPC_OVL_ROW_INC);
2694 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2695 if (dss_has_feature(FEAT_PRELOAD))
2696 DUMPREG(i, DISPC_OVL_PRELOAD);
2697
2698 if (i == OMAP_DSS_GFX) {
2699 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2700 DUMPREG(i, DISPC_OVL_TABLE_BA);
2701 continue;
2702 }
2703
2704 DUMPREG(i, DISPC_OVL_FIR);
2705 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2706 DUMPREG(i, DISPC_OVL_ACCU0);
2707 DUMPREG(i, DISPC_OVL_ACCU1);
2708 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2709 DUMPREG(i, DISPC_OVL_BA0_UV);
2710 DUMPREG(i, DISPC_OVL_BA1_UV);
2711 DUMPREG(i, DISPC_OVL_FIR2);
2712 DUMPREG(i, DISPC_OVL_ACCU2_0);
2713 DUMPREG(i, DISPC_OVL_ACCU2_1);
2714 }
2715 if (dss_has_feature(FEAT_ATTR2))
2716 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2717 if (dss_has_feature(FEAT_PRELOAD))
2718 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2719 }
5010be80
AT		 2720
2721#undef DISPC_REG
2722#undef DUMPREG
2723
2724#define DISPC_REG(plane, name, i) name(plane, i)
2725#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2726 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2727 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2728 dispc_read_reg(DISPC_REG(plane, name, i)))
2729
4dd2da15 2730 /* Video pipeline coefficient registers */
332e9d70 2731
4dd2da15
AT		 2732 /* start from OMAP_DSS_VIDEO1 */
2733 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2734 for (j = 0; j < 8; j++)
2735 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2736
4dd2da15
AT		 2737 for (j = 0; j < 8; j++)
2738 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2739
4dd2da15
AT		 2740 for (j = 0; j < 5; j++)
2741 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2742
4dd2da15
AT		 2743 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2744 for (j = 0; j < 8; j++)
2745 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2746 }
2747
2748 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2749 for (j = 0; j < 8; j++)
2750 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2751
2752 for (j = 0; j < 8; j++)
2753 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2754
2755 for (j = 0; j < 8; j++)
2756 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2757 }
332e9d70 2758 }
80c39712 2759
4fbafaf3 2760 dispc_runtime_put();
5010be80
AT		 2761
2762#undef DISPC_REG
80c39712
TV		 2763#undef DUMPREG
2764}
2765
26d9dd0d
TV		 2766static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2767 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2768 u8 acb)
80c39712
TV		 2769{
2770 u32 l = 0;
2771
2772 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2773 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2774
2775 l |= FLD_VAL(onoff, 17, 17);
2776 l |= FLD_VAL(rf, 16, 16);
2777 l |= FLD_VAL(ieo, 15, 15);
2778 l |= FLD_VAL(ipc, 14, 14);
2779 l |= FLD_VAL(ihs, 13, 13);
2780 l |= FLD_VAL(ivs, 12, 12);
2781 l |= FLD_VAL(acbi, 11, 8);
2782 l |= FLD_VAL(acb, 7, 0);
2783
ff1b2cde 2784 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2785}
2786
26d9dd0d 2787void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 2788 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2789{
26d9dd0d 2790 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2791 (config & OMAP_DSS_LCD_RF) != 0,
2792 (config & OMAP_DSS_LCD_IEO) != 0,
2793 (config & OMAP_DSS_LCD_IPC) != 0,
2794 (config & OMAP_DSS_LCD_IHS) != 0,
2795 (config & OMAP_DSS_LCD_IVS) != 0,
2796 acbi, acb);
2797}
2798
2799/* with fck as input clock rate, find dispc dividers that produce req_pck */
2800void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2801 struct dispc_clock_info *cinfo)
2802{
9eaaf207 2803 u16 pcd_min, pcd_max;
80c39712
TV		 2804 unsigned long best_pck;
2805 u16 best_ld, cur_ld;
2806 u16 best_pd, cur_pd;
2807
9eaaf207
TV		 2808 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2809 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2810
2811 if (!is_tft)
2812 pcd_min = 3;
2813
80c39712
TV		 2814 best_pck = 0;
2815 best_ld = 0;
2816 best_pd = 0;
2817
2818 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2819 unsigned long lck = fck / cur_ld;
2820
9eaaf207 2821 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 2822 unsigned long pck = lck / cur_pd;
2823 long old_delta = abs(best_pck - req_pck);
2824 long new_delta = abs(pck - req_pck);
2825
2826 if (best_pck == 0 || new_delta < old_delta) {
2827 best_pck = pck;
2828 best_ld = cur_ld;
2829 best_pd = cur_pd;
2830
2831 if (pck == req_pck)
2832 goto found;
2833 }
2834
2835 if (pck < req_pck)
2836 break;
2837 }
2838
2839 if (lck / pcd_min < req_pck)
2840 break;
2841 }
2842
2843found:
2844 cinfo->lck_div = best_ld;
2845 cinfo->pck_div = best_pd;
2846 cinfo->lck = fck / cinfo->lck_div;
2847 cinfo->pck = cinfo->lck / cinfo->pck_div;
2848}
2849
2850/* calculate clock rates using dividers in cinfo */
2851int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2852 struct dispc_clock_info *cinfo)
2853{
2854 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2855 return -EINVAL;
9eaaf207 2856 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 2857 return -EINVAL;
2858
2859 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2860 cinfo->pck = cinfo->lck / cinfo->pck_div;
2861
2862 return 0;
2863}
2864
26d9dd0d 2865int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 2866 struct dispc_clock_info *cinfo)
80c39712
TV		 2867{
2868 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2869 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2870
26d9dd0d 2871 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2872
2873 return 0;
2874}
2875
26d9dd0d 2876int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 2877 struct dispc_clock_info *cinfo)
80c39712
TV		 2878{
2879 unsigned long fck;
2880
2881 fck = dispc_fclk_rate();
2882
ce7fa5eb
MR		 2883 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2884 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2885
2886 cinfo->lck = fck / cinfo->lck_div;
2887 cinfo->pck = cinfo->lck / cinfo->pck_div;
2888
2889 return 0;
2890}
2891
2892/* dispc.irq_lock has to be locked by the caller */
2893static void _omap_dispc_set_irqs(void)
2894{
2895 u32 mask;
2896 u32 old_mask;
2897 int i;
2898 struct omap_dispc_isr_data *isr_data;
2899
2900 mask = dispc.irq_error_mask;
2901
2902 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2903 isr_data = &dispc.registered_isr[i];
2904
2905 if (isr_data->isr == NULL)
2906 continue;
2907
2908 mask |= isr_data->mask;
2909 }
2910
80c39712
TV		 2911 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2912 /* clear the irqstatus for newly enabled irqs */
2913 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2914
2915 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 2916}
2917
2918int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2919{
2920 int i;
2921 int ret;
2922 unsigned long flags;
2923 struct omap_dispc_isr_data *isr_data;
2924
2925 if (isr == NULL)
2926 return -EINVAL;
2927
2928 spin_lock_irqsave(&dispc.irq_lock, flags);
2929
2930 /* check for duplicate entry */
2931 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2932 isr_data = &dispc.registered_isr[i];
2933 if (isr_data->isr == isr && isr_data->arg == arg &&
2934 isr_data->mask == mask) {
2935 ret = -EINVAL;
2936 goto err;
2937 }
2938 }
2939
2940 isr_data = NULL;
2941 ret = -EBUSY;
2942
2943 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2944 isr_data = &dispc.registered_isr[i];
2945
2946 if (isr_data->isr != NULL)
2947 continue;
2948
2949 isr_data->isr = isr;
2950 isr_data->arg = arg;
2951 isr_data->mask = mask;
2952 ret = 0;
2953
2954 break;
2955 }
2956
b9cb0984
TV		 2957 if (ret)
2958 goto err;
2959
80c39712
TV		 2960 _omap_dispc_set_irqs();
2961
2962 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2963
2964 return 0;
2965err:
2966 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2967
2968 return ret;
2969}
2970EXPORT_SYMBOL(omap_dispc_register_isr);
2971
2972int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2973{
2974 int i;
2975 unsigned long flags;
2976 int ret = -EINVAL;
2977 struct omap_dispc_isr_data *isr_data;
2978
2979 spin_lock_irqsave(&dispc.irq_lock, flags);
2980
2981 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2982 isr_data = &dispc.registered_isr[i];
2983 if (isr_data->isr != isr || isr_data->arg != arg ||
2984 isr_data->mask != mask)
2985 continue;
2986
2987 /* found the correct isr */
2988
2989 isr_data->isr = NULL;
2990 isr_data->arg = NULL;
2991 isr_data->mask = 0;
2992
2993 ret = 0;
2994 break;
2995 }
2996
2997 if (ret == 0)
2998 _omap_dispc_set_irqs();
2999
3000 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3001
3002 return ret;
3003}
3004EXPORT_SYMBOL(omap_dispc_unregister_isr);
3005
3006#ifdef DEBUG
3007static void print_irq_status(u32 status)
3008{
3009 if ((status & dispc.irq_error_mask) == 0)
3010 return;
3011
3012 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3013
3014#define PIS(x) \
3015 if (status & DISPC_IRQ_##x) \
3016 printk(#x " ");
3017 PIS(GFX_FIFO_UNDERFLOW);
3018 PIS(OCP_ERR);
3019 PIS(VID1_FIFO_UNDERFLOW);
3020 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3021 if (dss_feat_get_num_ovls() > 3)
3022 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3023 PIS(SYNC_LOST);
3024 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3025 if (dss_has_feature(FEAT_MGR_LCD2))
3026 PIS(SYNC_LOST2);
80c39712
TV		 3027#undef PIS
3028
3029 printk("\n");
3030}
3031#endif
3032
3033/* Called from dss.c. Note that we don't touch clocks here,
3034 * but we presume they are on because we got an IRQ. However,
3035 * an irq handler may turn the clocks off, so we may not have
3036 * clock later in the function. */
affe360d 3037static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3038{
3039 int i;
affe360d 3040 u32 irqstatus, irqenable;
80c39712
TV		 3041 u32 handledirqs = 0;
3042 u32 unhandled_errors;
3043 struct omap_dispc_isr_data *isr_data;
3044 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3045
3046 spin_lock(&dispc.irq_lock);
3047
3048 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3049 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3050
3051 /* IRQ is not for us */
3052 if (!(irqstatus & irqenable)) {
3053 spin_unlock(&dispc.irq_lock);
3054 return IRQ_NONE;
3055 }
80c39712 3056
dfc0fd8d
TV		 3057#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3058 spin_lock(&dispc.irq_stats_lock);
3059 dispc.irq_stats.irq_count++;
3060 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3061 spin_unlock(&dispc.irq_stats_lock);
3062#endif
3063
80c39712
TV		 3064#ifdef DEBUG
3065 if (dss_debug)
3066 print_irq_status(irqstatus);
3067#endif
3068 /* Ack the interrupt. Do it here before clocks are possibly turned
3069 * off */
3070 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3071 /* flush posted write */
3072 dispc_read_reg(DISPC_IRQSTATUS);
3073
3074 /* make a copy and unlock, so that isrs can unregister
3075 * themselves */
3076 memcpy(registered_isr, dispc.registered_isr,
3077 sizeof(registered_isr));
3078
3079 spin_unlock(&dispc.irq_lock);
3080
3081 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3082 isr_data = &registered_isr[i];
3083
3084 if (!isr_data->isr)
3085 continue;
3086
3087 if (isr_data->mask & irqstatus) {
3088 isr_data->isr(isr_data->arg, irqstatus);
3089 handledirqs |= isr_data->mask;
3090 }
3091 }
3092
3093 spin_lock(&dispc.irq_lock);
3094
3095 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3096
3097 if (unhandled_errors) {
3098 dispc.error_irqs |= unhandled_errors;
3099
3100 dispc.irq_error_mask &= ~unhandled_errors;
3101 _omap_dispc_set_irqs();
3102
3103 schedule_work(&dispc.error_work);
3104 }
3105
3106 spin_unlock(&dispc.irq_lock);
affe360d 3107
3108 return IRQ_HANDLED;
80c39712
TV		 3109}
3110
3111static void dispc_error_worker(struct work_struct *work)
3112{
3113 int i;
3114 u32 errors;
3115 unsigned long flags;
fe3cc9d6
TV		 3116 static const unsigned fifo_underflow_bits[] = {
3117 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3118 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3119 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3120 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3121 };
3122
3123 static const unsigned sync_lost_bits[] = {
3124 DISPC_IRQ_SYNC_LOST,
3125 DISPC_IRQ_SYNC_LOST_DIGIT,
3126 DISPC_IRQ_SYNC_LOST2,
3127 };
80c39712
TV		 3128
3129 spin_lock_irqsave(&dispc.irq_lock, flags);
3130 errors = dispc.error_irqs;
3131 dispc.error_irqs = 0;
3132 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3133
13eae1f9
DZ		 3134 dispc_runtime_get();
3135
fe3cc9d6
TV		 3136 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3137 struct omap_overlay *ovl;
3138 unsigned bit;
80c39712 3139
fe3cc9d6
TV		 3140 ovl = omap_dss_get_overlay(i);
3141 bit = fifo_underflow_bits[i];
80c39712 3142
fe3cc9d6
TV		 3143 if (bit & errors) {
3144 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3145 ovl->name);
f0e5caab 3146 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3147 dispc_mgr_go(ovl->manager->id);
80c39712 3148 mdelay(50);
80c39712
TV		 3149 }
3150 }
3151
fe3cc9d6
TV		 3152 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3153 struct omap_overlay_manager *mgr;
3154 unsigned bit;
80c39712 3155
fe3cc9d6
TV		 3156 mgr = omap_dss_get_overlay_manager(i);
3157 bit = sync_lost_bits[i];
80c39712 3158
fe3cc9d6
TV		 3159 if (bit & errors) {
3160 struct omap_dss_device *dssdev = mgr->device;
3161 bool enable;
80c39712 3162
fe3cc9d6
TV		 3163 DSSERR("SYNC_LOST on channel %s, restarting the output "
3164 "with video overlays disabled\n",
3165 mgr->name);
2a205f34 3166
fe3cc9d6
TV		 3167 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3168 dssdev->driver->disable(dssdev);
2a205f34 3169
2a205f34
SS		 3170 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3171 struct omap_overlay *ovl;
3172 ovl = omap_dss_get_overlay(i);
3173
fe3cc9d6
TV		 3174 if (ovl->id != OMAP_DSS_GFX &&
3175 ovl->manager == mgr)
f0e5caab 3176 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3177 }
3178
26d9dd0d 3179 dispc_mgr_go(mgr->id);
2a205f34 3180 mdelay(50);
fe3cc9d6 3181
2a205f34
SS		 3182 if (enable)
3183 dssdev->driver->enable(dssdev);
3184 }
3185 }
3186
80c39712
TV		 3187 if (errors & DISPC_IRQ_OCP_ERR) {
3188 DSSERR("OCP_ERR\n");
3189 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3190 struct omap_overlay_manager *mgr;
3191 mgr = omap_dss_get_overlay_manager(i);
4a9e78ab 3192 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3193 }
3194 }
3195
3196 spin_lock_irqsave(&dispc.irq_lock, flags);
3197 dispc.irq_error_mask |= errors;
3198 _omap_dispc_set_irqs();
3199 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3200
3201 dispc_runtime_put();
80c39712
TV		 3202}
3203
3204int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3205{
3206 void dispc_irq_wait_handler(void *data, u32 mask)
3207 {
3208 complete((struct completion *)data);
3209 }
3210
3211 int r;
3212 DECLARE_COMPLETION_ONSTACK(completion);
3213
3214 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3215 irqmask);
3216
3217 if (r)
3218 return r;
3219
3220 timeout = wait_for_completion_timeout(&completion, timeout);
3221
3222 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3223
3224 if (timeout == 0)
3225 return -ETIMEDOUT;
3226
3227 if (timeout == -ERESTARTSYS)
3228 return -ERESTARTSYS;
3229
3230 return 0;
3231}
3232
3233int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3234 unsigned long timeout)
3235{
3236 void dispc_irq_wait_handler(void *data, u32 mask)
3237 {
3238 complete((struct completion *)data);
3239 }
3240
3241 int r;
3242 DECLARE_COMPLETION_ONSTACK(completion);
3243
3244 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3245 irqmask);
3246
3247 if (r)
3248 return r;
3249
3250 timeout = wait_for_completion_interruptible_timeout(&completion,
3251 timeout);
3252
3253 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3254
3255 if (timeout == 0)
3256 return -ETIMEDOUT;
3257
3258 if (timeout == -ERESTARTSYS)
3259 return -ERESTARTSYS;
3260
3261 return 0;
3262}
3263
3264#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3265void dispc_fake_vsync_irq(void)
3266{
3267 u32 irqstatus = DISPC_IRQ_VSYNC;
3268 int i;
3269
ab83b14c 3270 WARN_ON(!in_interrupt());
80c39712
TV		 3271
3272 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3273 struct omap_dispc_isr_data *isr_data;
3274 isr_data = &dispc.registered_isr[i];
3275
3276 if (!isr_data->isr)
3277 continue;
3278
3279 if (isr_data->mask & irqstatus)
3280 isr_data->isr(isr_data->arg, irqstatus);
3281 }
80c39712
TV		 3282}
3283#endif
3284
3285static void _omap_dispc_initialize_irq(void)
3286{
3287 unsigned long flags;
3288
3289 spin_lock_irqsave(&dispc.irq_lock, flags);
3290
3291 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3292
3293 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3294 if (dss_has_feature(FEAT_MGR_LCD2))
3295 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3296 if (dss_feat_get_num_ovls() > 3)
3297 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3298
3299 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3300 * so clear it */
3301 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3302
3303 _omap_dispc_set_irqs();
3304
3305 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3306}
3307
3308void dispc_enable_sidle(void)
3309{
3310 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3311}
3312
3313void dispc_disable_sidle(void)
3314{
3315 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3316}
3317
3318static void _omap_dispc_initial_config(void)
3319{
3320 u32 l;
3321
0cf35df3
MR		 3322 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3323 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3324 l = dispc_read_reg(DISPC_DIVISOR);
3325 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3326 l = FLD_MOD(l, 1, 0, 0);
3327 l = FLD_MOD(l, 1, 23, 16);
3328 dispc_write_reg(DISPC_DIVISOR, l);
3329 }
3330
80c39712 3331 /* FUNCGATED */
6ced40bf
AT		 3332 if (dss_has_feature(FEAT_FUNCGATED))
3333 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3334
3335 /* L3 firewall setting: enable access to OCM RAM */
3336 /* XXX this should be somewhere in plat-omap */
3337 if (cpu_is_omap24xx())
3338 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3339
3340 _dispc_setup_color_conv_coef();
3341
3342 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3343
3344 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3345
3346 dispc_configure_burst_sizes();
54128701
AT		 3347
3348 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3349}
3350
060b6d9c
SG		 3351/* DISPC HW IP initialisation */
3352static int omap_dispchw_probe(struct platform_device *pdev)
3353{
3354 u32 rev;
affe360d 3355 int r = 0;
ea9da36a 3356 struct resource *dispc_mem;
4fbafaf3 3357 struct clk *clk;
ea9da36a 3358
060b6d9c
SG		 3359 dispc.pdev = pdev;
3360
4fbafaf3
TV		 3361 clk = clk_get(&pdev->dev, "fck");
3362 if (IS_ERR(clk)) {
3363 DSSERR("can't get fck\n");
3364 r = PTR_ERR(clk);
3365 goto err_get_clk;
3366 }
3367
3368 dispc.dss_clk = clk;
3369
060b6d9c
SG		 3370 spin_lock_init(&dispc.irq_lock);
3371
3372#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3373 spin_lock_init(&dispc.irq_stats_lock);
3374 dispc.irq_stats.last_reset = jiffies;
3375#endif
3376
3377 INIT_WORK(&dispc.error_work, dispc_error_worker);
3378
ea9da36a
SG		 3379 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3380 if (!dispc_mem) {
3381 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3382 r = -EINVAL;
4fbafaf3 3383 goto err_ioremap;
ea9da36a
SG		 3384 }
3385 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3386 if (!dispc.base) {
3387 DSSERR("can't ioremap DISPC\n");
affe360d 3388 r = -ENOMEM;
4fbafaf3 3389 goto err_ioremap;
affe360d 3390 }
3391 dispc.irq = platform_get_irq(dispc.pdev, 0);
3392 if (dispc.irq < 0) {
3393 DSSERR("platform_get_irq failed\n");
3394 r = -ENODEV;
4fbafaf3 3395 goto err_irq;
affe360d 3396 }
3397
3398 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3399 "OMAP DISPC", dispc.pdev);
3400 if (r < 0) {
3401 DSSERR("request_irq failed\n");
4fbafaf3 3402 goto err_irq;
060b6d9c
SG		 3403 }
3404
4fbafaf3
TV		 3405 pm_runtime_enable(&pdev->dev);
3406
3407 r = dispc_runtime_get();
3408 if (r)
3409 goto err_runtime_get;
060b6d9c
SG		 3410
3411 _omap_dispc_initial_config();
3412
3413 _omap_dispc_initialize_irq();
3414
060b6d9c 3415 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3416 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3417 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3418
4fbafaf3 3419 dispc_runtime_put();
060b6d9c
SG		 3420
3421 return 0;
4fbafaf3
TV		 3422
3423err_runtime_get:
3424 pm_runtime_disable(&pdev->dev);
3425 free_irq(dispc.irq, dispc.pdev);
3426err_irq:
affe360d 3427 iounmap(dispc.base);
4fbafaf3
TV		 3428err_ioremap:
3429 clk_put(dispc.dss_clk);
3430err_get_clk:
affe360d 3431 return r;
060b6d9c
SG		 3432}
3433
3434static int omap_dispchw_remove(struct platform_device *pdev)
3435{
4fbafaf3
TV		 3436 pm_runtime_disable(&pdev->dev);
3437
3438 clk_put(dispc.dss_clk);
3439
affe360d 3440 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3441 iounmap(dispc.base);
3442 return 0;
3443}
3444
4fbafaf3
TV		 3445static int dispc_runtime_suspend(struct device *dev)
3446{
3447 dispc_save_context();
4fbafaf3
TV		 3448 dss_runtime_put();
3449
3450 return 0;
3451}
3452
3453static int dispc_runtime_resume(struct device *dev)
3454{
3455 int r;
3456
3457 r = dss_runtime_get();
3458 if (r < 0)
3459 return r;
3460
49ea86f3 3461 dispc_restore_context();
4fbafaf3
TV		 3462
3463 return 0;
3464}
3465
3466static const struct dev_pm_ops dispc_pm_ops = {
3467 .runtime_suspend = dispc_runtime_suspend,
3468 .runtime_resume = dispc_runtime_resume,
3469};
3470
060b6d9c
SG		 3471static struct platform_driver omap_dispchw_driver = {
3472 .probe = omap_dispchw_probe,
3473 .remove = omap_dispchw_remove,
3474 .driver = {
3475 .name = "omapdss_dispc",
3476 .owner = THIS_MODULE,
4fbafaf3 3477 .pm = &dispc_pm_ops,
060b6d9c
SG		 3478 },
3479};
3480
3481int dispc_init_platform_driver(void)
3482{
3483 return platform_driver_register(&omap_dispchw_driver);
3484}
3485
3486void dispc_uninit_platform_driver(void)
3487{
3488 return platform_driver_unregister(&omap_dispchw_driver);
3489}
Linux kernel - Deliverables
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