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OMAPDSS: Add support for LCD3 channel
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
efa70b3b
CM		 122enum mgr_reg_fields {
123 DISPC_MGR_FLD_ENABLE,
124 DISPC_MGR_FLD_STNTFT,
125 DISPC_MGR_FLD_GO,
126 DISPC_MGR_FLD_TFTDATALINES,
127 DISPC_MGR_FLD_STALLMODE,
128 DISPC_MGR_FLD_TCKENABLE,
129 DISPC_MGR_FLD_TCKSELECTION,
130 DISPC_MGR_FLD_CPR,
131 DISPC_MGR_FLD_FIFOHANDCHECK,
132 /* used to maintain a count of the above fields */
133 DISPC_MGR_FLD_NUM,
134};
135
136static const struct {
137 const char *name;
138 u32 vsync_irq;
139 u32 framedone_irq;
140 u32 sync_lost_irq;
141 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
142} mgr_desc[] = {
143 [OMAP_DSS_CHANNEL_LCD] = {
144 .name = "LCD",
145 .vsync_irq = DISPC_IRQ_VSYNC,
146 .framedone_irq = DISPC_IRQ_FRAMEDONE,
147 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
148 .reg_desc = {
149 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
150 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
151 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
152 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
153 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
154 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
155 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
156 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
157 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
158 },
159 },
160 [OMAP_DSS_CHANNEL_DIGIT] = {
161 .name = "DIGIT",
162 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
163 .framedone_irq = 0,
164 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
165 .reg_desc = {
166 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
167 [DISPC_MGR_FLD_STNTFT] = { },
168 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
169 [DISPC_MGR_FLD_TFTDATALINES] = { },
170 [DISPC_MGR_FLD_STALLMODE] = { },
171 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
172 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
173 [DISPC_MGR_FLD_CPR] = { },
174 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
175 },
176 },
177 [OMAP_DSS_CHANNEL_LCD2] = {
178 .name = "LCD2",
179 .vsync_irq = DISPC_IRQ_VSYNC2,
180 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
181 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
182 .reg_desc = {
183 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
184 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
185 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
186 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
187 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
188 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
189 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
190 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
191 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
192 },
193 },
194};
195
80c39712
TV		 196static void _omap_dispc_set_irqs(void);
197
55978cc2 198static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 199{
55978cc2 200 __raw_writel(val, dispc.base + idx);
80c39712
TV		 201}
202
55978cc2 203static inline u32 dispc_read_reg(const u16 idx)
80c39712 204{
55978cc2 205 return __raw_readl(dispc.base + idx);
80c39712
TV		 206}
207
efa70b3b
CM		 208static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
209{
210 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
211 return REG_GET(rfld.reg, rfld.high, rfld.low);
212}
213
214static void mgr_fld_write(enum omap_channel channel,
215 enum mgr_reg_fields regfld, int val) {
216 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
217 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
218}
219
80c39712 220#define SR(reg) \
55978cc2 221 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 222#define RR(reg) \
55978cc2 223 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 224
4fbafaf3 225static void dispc_save_context(void)
80c39712 226{
c6104b8e 227 int i, j;
80c39712 228
4fbafaf3
TV		 229 DSSDBG("dispc_save_context\n");
230
80c39712
TV		 231 SR(IRQENABLE);
232 SR(CONTROL);
233 SR(CONFIG);
80c39712 234 SR(LINE_NUMBER);
11354dd5
AT		 235 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
236 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 237 SR(GLOBAL_ALPHA);
2a205f34
SS		 238 if (dss_has_feature(FEAT_MGR_LCD2)) {
239 SR(CONTROL2);
2a205f34
SS		 240 SR(CONFIG2);
241 }
80c39712 242
c6104b8e
AT		 243 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
244 SR(DEFAULT_COLOR(i));
245 SR(TRANS_COLOR(i));
246 SR(SIZE_MGR(i));
247 if (i == OMAP_DSS_CHANNEL_DIGIT)
248 continue;
249 SR(TIMING_H(i));
250 SR(TIMING_V(i));
251 SR(POL_FREQ(i));
252 SR(DIVISORo(i));
253
254 SR(DATA_CYCLE1(i));
255 SR(DATA_CYCLE2(i));
256 SR(DATA_CYCLE3(i));
257
332e9d70 258 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 259 SR(CPR_COEF_R(i));
260 SR(CPR_COEF_G(i));
261 SR(CPR_COEF_B(i));
332e9d70 262 }
2a205f34 263 }
80c39712 264
c6104b8e
AT		 265 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
266 SR(OVL_BA0(i));
267 SR(OVL_BA1(i));
268 SR(OVL_POSITION(i));
269 SR(OVL_SIZE(i));
270 SR(OVL_ATTRIBUTES(i));
271 SR(OVL_FIFO_THRESHOLD(i));
272 SR(OVL_ROW_INC(i));
273 SR(OVL_PIXEL_INC(i));
274 if (dss_has_feature(FEAT_PRELOAD))
275 SR(OVL_PRELOAD(i));
276 if (i == OMAP_DSS_GFX) {
277 SR(OVL_WINDOW_SKIP(i));
278 SR(OVL_TABLE_BA(i));
279 continue;
280 }
281 SR(OVL_FIR(i));
282 SR(OVL_PICTURE_SIZE(i));
283 SR(OVL_ACCU0(i));
284 SR(OVL_ACCU1(i));
9b372c2d 285
c6104b8e
AT		 286 for (j = 0; j < 8; j++)
287 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 288
c6104b8e
AT		 289 for (j = 0; j < 8; j++)
290 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 291
c6104b8e
AT		 292 for (j = 0; j < 5; j++)
293 SR(OVL_CONV_COEF(i, j));
ab5ca071 294
c6104b8e
AT		 295 if (dss_has_feature(FEAT_FIR_COEF_V)) {
296 for (j = 0; j < 8; j++)
297 SR(OVL_FIR_COEF_V(i, j));
298 }
9b372c2d 299
c6104b8e
AT		 300 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
301 SR(OVL_BA0_UV(i));
302 SR(OVL_BA1_UV(i));
303 SR(OVL_FIR2(i));
304 SR(OVL_ACCU2_0(i));
305 SR(OVL_ACCU2_1(i));
ab5ca071 306
c6104b8e
AT		 307 for (j = 0; j < 8; j++)
308 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 309
c6104b8e
AT		 310 for (j = 0; j < 8; j++)
311 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 312
c6104b8e
AT		 313 for (j = 0; j < 8; j++)
314 SR(OVL_FIR_COEF_V2(i, j));
315 }
316 if (dss_has_feature(FEAT_ATTR2))
317 SR(OVL_ATTRIBUTES2(i));
ab5ca071 318 }
0cf35df3
MR		 319
320 if (dss_has_feature(FEAT_CORE_CLK_DIV))
321 SR(DIVISOR);
49ea86f3 322
00928eaf 323 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 324 dispc.ctx_valid = true;
325
326 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 327}
328
4fbafaf3 329static void dispc_restore_context(void)
80c39712 330{
c6104b8e 331 int i, j, ctx;
4fbafaf3
TV		 332
333 DSSDBG("dispc_restore_context\n");
334
49ea86f3
TV		 335 if (!dispc.ctx_valid)
336 return;
337
00928eaf 338 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 339
340 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
341 return;
342
343 DSSDBG("ctx_loss_count: saved %d, current %d\n",
344 dispc.ctx_loss_cnt, ctx);
345
75c7d59d 346 /*RR(IRQENABLE);*/
80c39712
TV		 347 /*RR(CONTROL);*/
348 RR(CONFIG);
80c39712 349 RR(LINE_NUMBER);
11354dd5
AT		 350 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
351 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 352 RR(GLOBAL_ALPHA);
c6104b8e 353 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 354 RR(CONFIG2);
80c39712 355
c6104b8e
AT		 356 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
357 RR(DEFAULT_COLOR(i));
358 RR(TRANS_COLOR(i));
359 RR(SIZE_MGR(i));
360 if (i == OMAP_DSS_CHANNEL_DIGIT)
361 continue;
362 RR(TIMING_H(i));
363 RR(TIMING_V(i));
364 RR(POL_FREQ(i));
365 RR(DIVISORo(i));
366
367 RR(DATA_CYCLE1(i));
368 RR(DATA_CYCLE2(i));
369 RR(DATA_CYCLE3(i));
2a205f34 370
332e9d70 371 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 372 RR(CPR_COEF_R(i));
373 RR(CPR_COEF_G(i));
374 RR(CPR_COEF_B(i));
332e9d70 375 }
2a205f34 376 }
80c39712 377
c6104b8e
AT		 378 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
379 RR(OVL_BA0(i));
380 RR(OVL_BA1(i));
381 RR(OVL_POSITION(i));
382 RR(OVL_SIZE(i));
383 RR(OVL_ATTRIBUTES(i));
384 RR(OVL_FIFO_THRESHOLD(i));
385 RR(OVL_ROW_INC(i));
386 RR(OVL_PIXEL_INC(i));
387 if (dss_has_feature(FEAT_PRELOAD))
388 RR(OVL_PRELOAD(i));
389 if (i == OMAP_DSS_GFX) {
390 RR(OVL_WINDOW_SKIP(i));
391 RR(OVL_TABLE_BA(i));
392 continue;
393 }
394 RR(OVL_FIR(i));
395 RR(OVL_PICTURE_SIZE(i));
396 RR(OVL_ACCU0(i));
397 RR(OVL_ACCU1(i));
9b372c2d 398
c6104b8e
AT		 399 for (j = 0; j < 8; j++)
400 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 401
c6104b8e
AT		 402 for (j = 0; j < 8; j++)
403 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 404
c6104b8e
AT		 405 for (j = 0; j < 5; j++)
406 RR(OVL_CONV_COEF(i, j));
ab5ca071 407
c6104b8e
AT		 408 if (dss_has_feature(FEAT_FIR_COEF_V)) {
409 for (j = 0; j < 8; j++)
410 RR(OVL_FIR_COEF_V(i, j));
411 }
9b372c2d 412
c6104b8e
AT		 413 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
414 RR(OVL_BA0_UV(i));
415 RR(OVL_BA1_UV(i));
416 RR(OVL_FIR2(i));
417 RR(OVL_ACCU2_0(i));
418 RR(OVL_ACCU2_1(i));
ab5ca071 419
c6104b8e
AT		 420 for (j = 0; j < 8; j++)
421 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 422
c6104b8e
AT		 423 for (j = 0; j < 8; j++)
424 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 425
c6104b8e
AT		 426 for (j = 0; j < 8; j++)
427 RR(OVL_FIR_COEF_V2(i, j));
428 }
429 if (dss_has_feature(FEAT_ATTR2))
430 RR(OVL_ATTRIBUTES2(i));
ab5ca071 431 }
80c39712 432
0cf35df3
MR		 433 if (dss_has_feature(FEAT_CORE_CLK_DIV))
434 RR(DIVISOR);
435
80c39712
TV		 436 /* enable last, because LCD & DIGIT enable are here */
437 RR(CONTROL);
2a205f34
SS		 438 if (dss_has_feature(FEAT_MGR_LCD2))
439 RR(CONTROL2);
75c7d59d
VS		 440 /* clear spurious SYNC_LOST_DIGIT interrupts */
441 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
442
443 /*
444 * enable last so IRQs won't trigger before
445 * the context is fully restored
446 */
447 RR(IRQENABLE);
49ea86f3
TV		 448
449 DSSDBG("context restored\n");
80c39712
TV		 450}
451
452#undef SR
453#undef RR
454
4fbafaf3
TV		 455int dispc_runtime_get(void)
456{
457 int r;
458
459 DSSDBG("dispc_runtime_get\n");
460
461 r = pm_runtime_get_sync(&dispc.pdev->dev);
462 WARN_ON(r < 0);
463 return r < 0 ? r : 0;
464}
465
466void dispc_runtime_put(void)
467{
468 int r;
469
470 DSSDBG("dispc_runtime_put\n");
471
0eaf9f52 472 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 473 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 474}
475
dac57a05
AT		 476static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
477{
478 if (channel == OMAP_DSS_CHANNEL_LCD ||
479 channel == OMAP_DSS_CHANNEL_LCD2)
480 return true;
481 else
482 return false;
483}
4fbafaf3 484
3dcec4d6
TV		 485u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
486{
efa70b3b 487 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 488}
489
7d1365c9
TV		 490u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
491{
efa70b3b 492 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 493}
494
26d9dd0d 495bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 496{
efa70b3b 497 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 498}
499
26d9dd0d 500void dispc_mgr_go(enum omap_channel channel)
80c39712 501{
2a205f34 502 bool enable_bit, go_bit;
80c39712 503
80c39712 504 /* if the channel is not enabled, we don't need GO */
efa70b3b 505 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
2a205f34
SS		 506
507 if (!enable_bit)
e6d80f95 508 return;
80c39712 509
efa70b3b 510 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
2a205f34
SS		 511
512 if (go_bit) {
80c39712 513 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 514 return;
80c39712
TV		 515 }
516
efa70b3b 517 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 518
efa70b3b 519 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 520}
521
f0e5caab 522static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 523{
9b372c2d 524 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 525}
526
f0e5caab 527static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 528{
9b372c2d 529 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 530}
531
f0e5caab 532static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 533{
9b372c2d 534 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 535}
536
f0e5caab 537static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 538{
539 BUG_ON(plane == OMAP_DSS_GFX);
540
541 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
542}
543
f0e5caab
TV		 544static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
545 u32 value)
ab5ca071
AJ		 546{
547 BUG_ON(plane == OMAP_DSS_GFX);
548
549 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
550}
551
f0e5caab 552static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 553{
554 BUG_ON(plane == OMAP_DSS_GFX);
555
556 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
557}
558
debd9074
CM		 559static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
560 int fir_vinc, int five_taps,
561 enum omap_color_component color_comp)
80c39712 562{
debd9074 563 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 564 int i;
565
debd9074
CM		 566 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
567 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 568
569 for (i = 0; i < 8; i++) {
570 u32 h, hv;
571
debd9074
CM		 572 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
573 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
574 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
575 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
576 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
577 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
578 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
579 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 580
0d66cbb5 581 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 582 dispc_ovl_write_firh_reg(plane, i, h);
583 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 584 } else {
f0e5caab
TV		 585 dispc_ovl_write_firh2_reg(plane, i, h);
586 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 587 }
588
80c39712
TV		 589 }
590
66be8f6c
GI		 591 if (five_taps) {
592 for (i = 0; i < 8; i++) {
593 u32 v;
debd9074
CM		 594 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
595 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 596 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 597 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 598 else
f0e5caab 599 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 600 }
80c39712
TV		 601 }
602}
603
604static void _dispc_setup_color_conv_coef(void)
605{
ac01c29e 606 int i;
80c39712
TV		 607 const struct color_conv_coef {
608 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
609 int full_range;
610 } ctbl_bt601_5 = {
611 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
612 };
613
614 const struct color_conv_coef *ct;
615
616#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
617
618 ct = &ctbl_bt601_5;
619
ac01c29e
AT		 620 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
621 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
622 CVAL(ct->rcr, ct->ry));
623 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
624 CVAL(ct->gy, ct->rcb));
625 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
626 CVAL(ct->gcb, ct->gcr));
627 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
628 CVAL(ct->bcr, ct->by));
629 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
630 CVAL(0, ct->bcb));
631
632 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
633 11, 11);
634 }
80c39712
TV		 635
636#undef CVAL
80c39712
TV		 637}
638
639
f0e5caab 640static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 641{
9b372c2d 642 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 643}
644
f0e5caab 645static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 646{
9b372c2d 647 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 648}
649
f0e5caab 650static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 651{
652 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
653}
654
f0e5caab 655static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 656{
657 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
658}
659
f0e5caab 660static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 661{
80c39712 662 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 663
664 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 665}
666
f0e5caab 667static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 668{
80c39712 669 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 670
671 if (plane == OMAP_DSS_GFX)
672 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
673 else
674 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 675}
676
f0e5caab 677static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 678{
679 u32 val;
80c39712
TV		 680
681 BUG_ON(plane == OMAP_DSS_GFX);
682
683 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 684
685 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 686}
687
54128701
AT		 688static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
689{
690 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
691
692 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
693 return;
694
695 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
696}
697
698static void dispc_ovl_enable_zorder_planes(void)
699{
700 int i;
701
702 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
703 return;
704
705 for (i = 0; i < dss_feat_get_num_ovls(); i++)
706 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
707}
708
f0e5caab 709static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 710{
f6dc8150 711 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 712
f6dc8150 713 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 714 return;
715
9b372c2d 716 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 717}
718
f0e5caab 719static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 720{
b8c095b4 721 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 722 int shift;
f6dc8150 723 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 724
f6dc8150 725 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 726 return;
a0acb557 727
fe3cc9d6
TV		 728 shift = shifts[plane];
729 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 730}
731
f0e5caab 732static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 733{
9b372c2d 734 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 735}
736
f0e5caab 737static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 738{
9b372c2d 739 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 740}
741
f0e5caab 742static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 743 enum omap_color_mode color_mode)
744{
745 u32 m = 0;
f20e4220
AJ		 746 if (plane != OMAP_DSS_GFX) {
747 switch (color_mode) {
748 case OMAP_DSS_COLOR_NV12:
749 m = 0x0; break;
08f3267e 750 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 751 m = 0x1; break;
752 case OMAP_DSS_COLOR_RGBA16:
753 m = 0x2; break;
08f3267e 754 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 755 m = 0x4; break;
756 case OMAP_DSS_COLOR_ARGB16:
757 m = 0x5; break;
758 case OMAP_DSS_COLOR_RGB16:
759 m = 0x6; break;
760 case OMAP_DSS_COLOR_ARGB16_1555:
761 m = 0x7; break;
762 case OMAP_DSS_COLOR_RGB24U:
763 m = 0x8; break;
764 case OMAP_DSS_COLOR_RGB24P:
765 m = 0x9; break;
766 case OMAP_DSS_COLOR_YUV2:
767 m = 0xa; break;
768 case OMAP_DSS_COLOR_UYVY:
769 m = 0xb; break;
770 case OMAP_DSS_COLOR_ARGB32:
771 m = 0xc; break;
772 case OMAP_DSS_COLOR_RGBA32:
773 m = 0xd; break;
774 case OMAP_DSS_COLOR_RGBX32:
775 m = 0xe; break;
776 case OMAP_DSS_COLOR_XRGB16_1555:
777 m = 0xf; break;
778 default:
c6eee968 779 BUG(); return;
f20e4220
AJ		 780 }
781 } else {
782 switch (color_mode) {
783 case OMAP_DSS_COLOR_CLUT1:
784 m = 0x0; break;
785 case OMAP_DSS_COLOR_CLUT2:
786 m = 0x1; break;
787 case OMAP_DSS_COLOR_CLUT4:
788 m = 0x2; break;
789 case OMAP_DSS_COLOR_CLUT8:
790 m = 0x3; break;
791 case OMAP_DSS_COLOR_RGB12U:
792 m = 0x4; break;
793 case OMAP_DSS_COLOR_ARGB16:
794 m = 0x5; break;
795 case OMAP_DSS_COLOR_RGB16:
796 m = 0x6; break;
797 case OMAP_DSS_COLOR_ARGB16_1555:
798 m = 0x7; break;
799 case OMAP_DSS_COLOR_RGB24U:
800 m = 0x8; break;
801 case OMAP_DSS_COLOR_RGB24P:
802 m = 0x9; break;
08f3267e 803 case OMAP_DSS_COLOR_RGBX16:
f20e4220 804 m = 0xa; break;
08f3267e 805 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 806 m = 0xb; break;
807 case OMAP_DSS_COLOR_ARGB32:
808 m = 0xc; break;
809 case OMAP_DSS_COLOR_RGBA32:
810 m = 0xd; break;
811 case OMAP_DSS_COLOR_RGBX32:
812 m = 0xe; break;
813 case OMAP_DSS_COLOR_XRGB16_1555:
814 m = 0xf; break;
815 default:
c6eee968 816 BUG(); return;
f20e4220 817 }
80c39712
TV		 818 }
819
9b372c2d 820 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 821}
822
65e006ff
CM		 823static void dispc_ovl_configure_burst_type(enum omap_plane plane,
824 enum omap_dss_rotation_type rotation_type)
825{
826 if (dss_has_feature(FEAT_BURST_2D) == 0)
827 return;
828
829 if (rotation_type == OMAP_DSS_ROT_TILER)
830 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
831 else
832 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
833}
834
f427984e 835void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 836{
837 int shift;
838 u32 val;
2a205f34 839 int chan = 0, chan2 = 0;
80c39712
TV		 840
841 switch (plane) {
842 case OMAP_DSS_GFX:
843 shift = 8;
844 break;
845 case OMAP_DSS_VIDEO1:
846 case OMAP_DSS_VIDEO2:
b8c095b4 847 case OMAP_DSS_VIDEO3:
80c39712
TV		 848 shift = 16;
849 break;
850 default:
851 BUG();
852 return;
853 }
854
9b372c2d 855 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 856 if (dss_has_feature(FEAT_MGR_LCD2)) {
857 switch (channel) {
858 case OMAP_DSS_CHANNEL_LCD:
859 chan = 0;
860 chan2 = 0;
861 break;
862 case OMAP_DSS_CHANNEL_DIGIT:
863 chan = 1;
864 chan2 = 0;
865 break;
866 case OMAP_DSS_CHANNEL_LCD2:
867 chan = 0;
868 chan2 = 1;
869 break;
870 default:
871 BUG();
c6eee968 872 return;
2a205f34
SS		 873 }
874
875 val = FLD_MOD(val, chan, shift, shift);
876 val = FLD_MOD(val, chan2, 31, 30);
877 } else {
878 val = FLD_MOD(val, channel, shift, shift);
879 }
9b372c2d 880 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 881}
882
2cc5d1af
TV		 883static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
884{
885 int shift;
886 u32 val;
887 enum omap_channel channel;
888
889 switch (plane) {
890 case OMAP_DSS_GFX:
891 shift = 8;
892 break;
893 case OMAP_DSS_VIDEO1:
894 case OMAP_DSS_VIDEO2:
895 case OMAP_DSS_VIDEO3:
896 shift = 16;
897 break;
898 default:
899 BUG();
c6eee968 900 return 0;
2cc5d1af
TV		 901 }
902
903 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
904
905 if (dss_has_feature(FEAT_MGR_LCD2)) {
906 if (FLD_GET(val, 31, 30) == 0)
907 channel = FLD_GET(val, shift, shift);
908 else
909 channel = OMAP_DSS_CHANNEL_LCD2;
910 } else {
911 channel = FLD_GET(val, shift, shift);
912 }
913
914 return channel;
915}
916
f0e5caab 917static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 918 enum omap_burst_size burst_size)
919{
b8c095b4 920 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 921 int shift;
80c39712 922
fe3cc9d6 923 shift = shifts[plane];
5ed8cf5b 924 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 925}
926
5ed8cf5b
TV		 927static void dispc_configure_burst_sizes(void)
928{
929 int i;
930 const int burst_size = BURST_SIZE_X8;
931
932 /* Configure burst size always to maximum size */
933 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 934 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 935}
936
83fa2f2e 937static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 938{
939 unsigned unit = dss_feat_get_burst_size_unit();
940 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
941 return unit * 8;
942}
943
d3862610
M		 944void dispc_enable_gamma_table(bool enable)
945{
946 /*
947 * This is partially implemented to support only disabling of
948 * the gamma table.
949 */
950 if (enable) {
951 DSSWARN("Gamma table enabling for TV not yet supported");
952 return;
953 }
954
955 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
956}
957
c64dca40 958static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 959{
efa70b3b 960 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 961 return;
962
efa70b3b 963 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 964}
965
c64dca40 966static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 967 struct omap_dss_cpr_coefs *coefs)
968{
969 u32 coef_r, coef_g, coef_b;
970
dac57a05 971 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 972 return;
973
974 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
975 FLD_VAL(coefs->rb, 9, 0);
976 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
977 FLD_VAL(coefs->gb, 9, 0);
978 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
979 FLD_VAL(coefs->bb, 9, 0);
980
981 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
982 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
983 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
984}
985
f0e5caab 986static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 987{
988 u32 val;
989
990 BUG_ON(plane == OMAP_DSS_GFX);
991
9b372c2d 992 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 993 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 994 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 995}
996
c3d92529 997static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 998{
b8c095b4 999 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1000 int shift;
80c39712 1001
fe3cc9d6
TV		 1002 shift = shifts[plane];
1003 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1004}
1005
8f366162 1006static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1007 u16 height)
80c39712
TV		 1008{
1009 u32 val;
80c39712 1010
80c39712 1011 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 1012 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1013}
1014
1015static void dispc_read_plane_fifo_sizes(void)
1016{
80c39712
TV		 1017 u32 size;
1018 int plane;
a0acb557 1019 u8 start, end;
5ed8cf5b
TV		 1020 u32 unit;
1021
1022 unit = dss_feat_get_buffer_size_unit();
80c39712 1023
a0acb557 1024 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1025
e13a138b 1026 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1027 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1028 size *= unit;
80c39712
TV		 1029 dispc.fifo_size[plane] = size;
1030 }
80c39712
TV		 1031}
1032
83fa2f2e 1033static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1034{
1035 return dispc.fifo_size[plane];
1036}
1037
6f04e1bf 1038void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1039{
a0acb557 1040 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1041 u32 unit;
1042
1043 unit = dss_feat_get_buffer_size_unit();
1044
1045 WARN_ON(low % unit != 0);
1046 WARN_ON(high % unit != 0);
1047
1048 low /= unit;
1049 high /= unit;
a0acb557 1050
9b372c2d
AT		 1051 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1052 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1053
3cb5d966 1054 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1055 plane,
9b372c2d 1056 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1057 lo_start, lo_end) * unit,
9b372c2d 1058 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1059 hi_start, hi_end) * unit,
1060 low * unit, high * unit);
80c39712 1061
9b372c2d 1062 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1063 FLD_VAL(high, hi_start, hi_end) |
1064 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1065}
1066
1067void dispc_enable_fifomerge(bool enable)
1068{
e6b0f884
TV		 1069 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1070 WARN_ON(enable);
1071 return;
1072 }
1073
80c39712
TV		 1074 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1075 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1076}
1077
83fa2f2e 1078void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1079 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1080 bool manual_update)
83fa2f2e
TV		 1081{
1082 /*
1083 * All sizes are in bytes. Both the buffer and burst are made of
1084 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1085 */
1086
1087 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1088 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1089 int i;
83fa2f2e
TV		 1090
1091 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1092 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1093
e0e405b9
TV		 1094 if (use_fifomerge) {
1095 total_fifo_size = 0;
1096 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1097 total_fifo_size += dispc_ovl_get_fifo_size(i);
1098 } else {
1099 total_fifo_size = ovl_fifo_size;
1100 }
1101
1102 /*
1103 * We use the same low threshold for both fifomerge and non-fifomerge
1104 * cases, but for fifomerge we calculate the high threshold using the
1105 * combined fifo size
1106 */
1107
3568f2a4 1108 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1109 *fifo_low = ovl_fifo_size - burst_size * 2;
1110 *fifo_high = total_fifo_size - burst_size;
1111 } else {
1112 *fifo_low = ovl_fifo_size - burst_size;
1113 *fifo_high = total_fifo_size - buf_unit;
1114 }
83fa2f2e
TV		 1115}
1116
f0e5caab 1117static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1118 int hinc, int vinc,
1119 enum omap_color_component color_comp)
80c39712
TV		 1120{
1121 u32 val;
80c39712 1122
0d66cbb5
AJ		 1123 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1124 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1125
0d66cbb5
AJ		 1126 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1127 &hinc_start, &hinc_end);
1128 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1129 &vinc_start, &vinc_end);
1130 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1131 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1132
0d66cbb5
AJ		 1133 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1134 } else {
1135 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1136 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1137 }
80c39712
TV		 1138}
1139
f0e5caab 1140static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1141{
1142 u32 val;
87a7484b 1143 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1144
87a7484b
AT		 1145 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1146 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1147
1148 val = FLD_VAL(vaccu, vert_start, vert_end) |
1149 FLD_VAL(haccu, hor_start, hor_end);
1150
9b372c2d 1151 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1152}
1153
f0e5caab 1154static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1155{
1156 u32 val;
87a7484b 1157 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1158
87a7484b
AT		 1159 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1160 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1161
1162 val = FLD_VAL(vaccu, vert_start, vert_end) |
1163 FLD_VAL(haccu, hor_start, hor_end);
1164
9b372c2d 1165 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1166}
1167
f0e5caab
TV		 1168static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1169 int vaccu)
ab5ca071
AJ		 1170{
1171 u32 val;
1172
1173 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1174 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1175}
1176
f0e5caab
TV		 1177static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1178 int vaccu)
ab5ca071
AJ		 1179{
1180 u32 val;
1181
1182 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1183 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1184}
80c39712 1185
f0e5caab 1186static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1187 u16 orig_width, u16 orig_height,
1188 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1189 bool five_taps, u8 rotation,
1190 enum omap_color_component color_comp)
80c39712 1191{
0d66cbb5 1192 int fir_hinc, fir_vinc;
80c39712 1193
ed14a3ce
AJ		 1194 fir_hinc = 1024 * orig_width / out_width;
1195 fir_vinc = 1024 * orig_height / out_height;
80c39712 1196
debd9074
CM		 1197 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1198 color_comp);
f0e5caab 1199 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1200}
1201
05dd0f53
CM		 1202static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1203 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1204 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1205{
1206 int h_accu2_0, h_accu2_1;
1207 int v_accu2_0, v_accu2_1;
1208 int chroma_hinc, chroma_vinc;
1209 int idx;
1210
1211 struct accu {
1212 s8 h0_m, h0_n;
1213 s8 h1_m, h1_n;
1214 s8 v0_m, v0_n;
1215 s8 v1_m, v1_n;
1216 };
1217
1218 const struct accu *accu_table;
1219 const struct accu *accu_val;
1220
1221 static const struct accu accu_nv12[4] = {
1222 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1223 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1224 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1225 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1226 };
1227
1228 static const struct accu accu_nv12_ilace[4] = {
1229 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1230 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1231 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1232 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1233 };
1234
1235 static const struct accu accu_yuv[4] = {
1236 { 0, 1, 0, 1, 0, 1, 0, 1 },
1237 { 0, 1, 0, 1, 0, 1, 0, 1 },
1238 { -1, 1, 0, 1, 0, 1, 0, 1 },
1239 { 0, 1, 0, 1, -1, 1, 0, 1 },
1240 };
1241
1242 switch (rotation) {
1243 case OMAP_DSS_ROT_0:
1244 idx = 0;
1245 break;
1246 case OMAP_DSS_ROT_90:
1247 idx = 1;
1248 break;
1249 case OMAP_DSS_ROT_180:
1250 idx = 2;
1251 break;
1252 case OMAP_DSS_ROT_270:
1253 idx = 3;
1254 break;
1255 default:
1256 BUG();
c6eee968 1257 return;
05dd0f53
CM		 1258 }
1259
1260 switch (color_mode) {
1261 case OMAP_DSS_COLOR_NV12:
1262 if (ilace)
1263 accu_table = accu_nv12_ilace;
1264 else
1265 accu_table = accu_nv12;
1266 break;
1267 case OMAP_DSS_COLOR_YUV2:
1268 case OMAP_DSS_COLOR_UYVY:
1269 accu_table = accu_yuv;
1270 break;
1271 default:
1272 BUG();
c6eee968 1273 return;
05dd0f53
CM		 1274 }
1275
1276 accu_val = &accu_table[idx];
1277
1278 chroma_hinc = 1024 * orig_width / out_width;
1279 chroma_vinc = 1024 * orig_height / out_height;
1280
1281 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1282 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1283 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1284 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1285
1286 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1287 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1288}
1289
f0e5caab 1290static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1291 u16 orig_width, u16 orig_height,
1292 u16 out_width, u16 out_height,
1293 bool ilace, bool five_taps,
1294 bool fieldmode, enum omap_color_mode color_mode,
1295 u8 rotation)
1296{
1297 int accu0 = 0;
1298 int accu1 = 0;
1299 u32 l;
80c39712 1300
f0e5caab 1301 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1302 out_width, out_height, five_taps,
1303 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1304 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1305
87a7484b
AT		 1306 /* RESIZEENABLE and VERTICALTAPS */
1307 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1308 l |= (orig_width != out_width) ? (1 << 5) : 0;
1309 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1310 l |= five_taps ? (1 << 21) : 0;
80c39712 1311
87a7484b
AT		 1312 /* VRESIZECONF and HRESIZECONF */
1313 if (dss_has_feature(FEAT_RESIZECONF)) {
1314 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1315 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1316 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1317 }
80c39712 1318
87a7484b
AT		 1319 /* LINEBUFFERSPLIT */
1320 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1321 l &= ~(0x1 << 22);
1322 l |= five_taps ? (1 << 22) : 0;
1323 }
80c39712 1324
9b372c2d 1325 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1326
1327 /*
1328 * field 0 = even field = bottom field
1329 * field 1 = odd field = top field
1330 */
1331 if (ilace && !fieldmode) {
1332 accu1 = 0;
0d66cbb5 1333 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1334 if (accu0 >= 1024/2) {
1335 accu1 = 1024/2;
1336 accu0 -= accu1;
1337 }
1338 }
1339
f0e5caab
TV		 1340 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1341 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1342}
1343
f0e5caab 1344static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1345 u16 orig_width, u16 orig_height,
1346 u16 out_width, u16 out_height,
1347 bool ilace, bool five_taps,
1348 bool fieldmode, enum omap_color_mode color_mode,
1349 u8 rotation)
1350{
1351 int scale_x = out_width != orig_width;
1352 int scale_y = out_height != orig_height;
1353
1354 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1355 return;
1356 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1357 color_mode != OMAP_DSS_COLOR_UYVY &&
1358 color_mode != OMAP_DSS_COLOR_NV12)) {
1359 /* reset chroma resampling for RGB formats */
1360 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1361 return;
1362 }
36377357
TV		 1363
1364 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1365 out_height, ilace, color_mode, rotation);
1366
0d66cbb5
AJ		 1367 switch (color_mode) {
1368 case OMAP_DSS_COLOR_NV12:
1369 /* UV is subsampled by 2 vertically*/
1370 orig_height >>= 1;
1371 /* UV is subsampled by 2 horz.*/
1372 orig_width >>= 1;
1373 break;
1374 case OMAP_DSS_COLOR_YUV2:
1375 case OMAP_DSS_COLOR_UYVY:
1376 /*For YUV422 with 90/270 rotation,
1377 *we don't upsample chroma
1378 */
1379 if (rotation == OMAP_DSS_ROT_0 ||
1380 rotation == OMAP_DSS_ROT_180)
1381 /* UV is subsampled by 2 hrz*/
1382 orig_width >>= 1;
1383 /* must use FIR for YUV422 if rotated */
1384 if (rotation != OMAP_DSS_ROT_0)
1385 scale_x = scale_y = true;
1386 break;
1387 default:
1388 BUG();
c6eee968 1389 return;
0d66cbb5
AJ		 1390 }
1391
1392 if (out_width != orig_width)
1393 scale_x = true;
1394 if (out_height != orig_height)
1395 scale_y = true;
1396
f0e5caab 1397 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1398 out_width, out_height, five_taps,
1399 rotation, DISPC_COLOR_COMPONENT_UV);
1400
1401 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1402 (scale_x || scale_y) ? 1 : 0, 8, 8);
1403 /* set H scaling */
1404 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1405 /* set V scaling */
1406 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1407}
1408
f0e5caab 1409static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1410 u16 orig_width, u16 orig_height,
1411 u16 out_width, u16 out_height,
1412 bool ilace, bool five_taps,
1413 bool fieldmode, enum omap_color_mode color_mode,
1414 u8 rotation)
1415{
1416 BUG_ON(plane == OMAP_DSS_GFX);
1417
f0e5caab 1418 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1419 orig_width, orig_height,
1420 out_width, out_height,
1421 ilace, five_taps,
1422 fieldmode, color_mode,
1423 rotation);
1424
f0e5caab 1425 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1426 orig_width, orig_height,
1427 out_width, out_height,
1428 ilace, five_taps,
1429 fieldmode, color_mode,
1430 rotation);
1431}
1432
f0e5caab 1433static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1434 bool mirroring, enum omap_color_mode color_mode)
1435{
87a7484b
AT		 1436 bool row_repeat = false;
1437 int vidrot = 0;
1438
80c39712
TV		 1439 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1440 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1441
1442 if (mirroring) {
1443 switch (rotation) {
1444 case OMAP_DSS_ROT_0:
1445 vidrot = 2;
1446 break;
1447 case OMAP_DSS_ROT_90:
1448 vidrot = 1;
1449 break;
1450 case OMAP_DSS_ROT_180:
1451 vidrot = 0;
1452 break;
1453 case OMAP_DSS_ROT_270:
1454 vidrot = 3;
1455 break;
1456 }
1457 } else {
1458 switch (rotation) {
1459 case OMAP_DSS_ROT_0:
1460 vidrot = 0;
1461 break;
1462 case OMAP_DSS_ROT_90:
1463 vidrot = 1;
1464 break;
1465 case OMAP_DSS_ROT_180:
1466 vidrot = 2;
1467 break;
1468 case OMAP_DSS_ROT_270:
1469 vidrot = 3;
1470 break;
1471 }
1472 }
1473
80c39712 1474 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1475 row_repeat = true;
80c39712 1476 else
87a7484b 1477 row_repeat = false;
80c39712 1478 }
87a7484b 1479
9b372c2d 1480 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1481 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1482 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1483 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1484}
1485
1486static int color_mode_to_bpp(enum omap_color_mode color_mode)
1487{
1488 switch (color_mode) {
1489 case OMAP_DSS_COLOR_CLUT1:
1490 return 1;
1491 case OMAP_DSS_COLOR_CLUT2:
1492 return 2;
1493 case OMAP_DSS_COLOR_CLUT4:
1494 return 4;
1495 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1496 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1497 return 8;
1498 case OMAP_DSS_COLOR_RGB12U:
1499 case OMAP_DSS_COLOR_RGB16:
1500 case OMAP_DSS_COLOR_ARGB16:
1501 case OMAP_DSS_COLOR_YUV2:
1502 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1503 case OMAP_DSS_COLOR_RGBA16:
1504 case OMAP_DSS_COLOR_RGBX16:
1505 case OMAP_DSS_COLOR_ARGB16_1555:
1506 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1507 return 16;
1508 case OMAP_DSS_COLOR_RGB24P:
1509 return 24;
1510 case OMAP_DSS_COLOR_RGB24U:
1511 case OMAP_DSS_COLOR_ARGB32:
1512 case OMAP_DSS_COLOR_RGBA32:
1513 case OMAP_DSS_COLOR_RGBX32:
1514 return 32;
1515 default:
1516 BUG();
c6eee968 1517 return 0;
80c39712
TV		 1518 }
1519}
1520
1521static s32 pixinc(int pixels, u8 ps)
1522{
1523 if (pixels == 1)
1524 return 1;
1525 else if (pixels > 1)
1526 return 1 + (pixels - 1) * ps;
1527 else if (pixels < 0)
1528 return 1 - (-pixels + 1) * ps;
1529 else
1530 BUG();
c6eee968 1531 return 0;
80c39712
TV		 1532}
1533
1534static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1535 u16 screen_width,
1536 u16 width, u16 height,
1537 enum omap_color_mode color_mode, bool fieldmode,
1538 unsigned int field_offset,
1539 unsigned *offset0, unsigned *offset1,
aed74b55 1540 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1541{
1542 u8 ps;
1543
1544 /* FIXME CLUT formats */
1545 switch (color_mode) {
1546 case OMAP_DSS_COLOR_CLUT1:
1547 case OMAP_DSS_COLOR_CLUT2:
1548 case OMAP_DSS_COLOR_CLUT4:
1549 case OMAP_DSS_COLOR_CLUT8:
1550 BUG();
1551 return;
1552 case OMAP_DSS_COLOR_YUV2:
1553 case OMAP_DSS_COLOR_UYVY:
1554 ps = 4;
1555 break;
1556 default:
1557 ps = color_mode_to_bpp(color_mode) / 8;
1558 break;
1559 }
1560
1561 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1562 width, height);
1563
1564 /*
1565 * field 0 = even field = bottom field
1566 * field 1 = odd field = top field
1567 */
1568 switch (rotation + mirror * 4) {
1569 case OMAP_DSS_ROT_0:
1570 case OMAP_DSS_ROT_180:
1571 /*
1572 * If the pixel format is YUV or UYVY divide the width
1573 * of the image by 2 for 0 and 180 degree rotation.
1574 */
1575 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1576 color_mode == OMAP_DSS_COLOR_UYVY)
1577 width = width >> 1;
1578 case OMAP_DSS_ROT_90:
1579 case OMAP_DSS_ROT_270:
1580 *offset1 = 0;
1581 if (field_offset)
1582 *offset0 = field_offset * screen_width * ps;
1583 else
1584 *offset0 = 0;
1585
aed74b55
CM		 1586 *row_inc = pixinc(1 +
1587 (y_predecim * screen_width - x_predecim * width) +
1588 (fieldmode ? screen_width : 0), ps);
1589 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1590 break;
1591
1592 case OMAP_DSS_ROT_0 + 4:
1593 case OMAP_DSS_ROT_180 + 4:
1594 /* If the pixel format is YUV or UYVY divide the width
1595 * of the image by 2 for 0 degree and 180 degree
1596 */
1597 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1598 color_mode == OMAP_DSS_COLOR_UYVY)
1599 width = width >> 1;
1600 case OMAP_DSS_ROT_90 + 4:
1601 case OMAP_DSS_ROT_270 + 4:
1602 *offset1 = 0;
1603 if (field_offset)
1604 *offset0 = field_offset * screen_width * ps;
1605 else
1606 *offset0 = 0;
aed74b55
CM		 1607 *row_inc = pixinc(1 -
1608 (y_predecim * screen_width + x_predecim * width) -
1609 (fieldmode ? screen_width : 0), ps);
1610 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1611 break;
1612
1613 default:
1614 BUG();
c6eee968 1615 return;
80c39712
TV		 1616 }
1617}
1618
1619static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1620 u16 screen_width,
1621 u16 width, u16 height,
1622 enum omap_color_mode color_mode, bool fieldmode,
1623 unsigned int field_offset,
1624 unsigned *offset0, unsigned *offset1,
aed74b55 1625 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1626{
1627 u8 ps;
1628 u16 fbw, fbh;
1629
1630 /* FIXME CLUT formats */
1631 switch (color_mode) {
1632 case OMAP_DSS_COLOR_CLUT1:
1633 case OMAP_DSS_COLOR_CLUT2:
1634 case OMAP_DSS_COLOR_CLUT4:
1635 case OMAP_DSS_COLOR_CLUT8:
1636 BUG();
1637 return;
1638 default:
1639 ps = color_mode_to_bpp(color_mode) / 8;
1640 break;
1641 }
1642
1643 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1644 width, height);
1645
1646 /* width & height are overlay sizes, convert to fb sizes */
1647
1648 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1649 fbw = width;
1650 fbh = height;
1651 } else {
1652 fbw = height;
1653 fbh = width;
1654 }
1655
1656 /*
1657 * field 0 = even field = bottom field
1658 * field 1 = odd field = top field
1659 */
1660 switch (rotation + mirror * 4) {
1661 case OMAP_DSS_ROT_0:
1662 *offset1 = 0;
1663 if (field_offset)
1664 *offset0 = *offset1 + field_offset * screen_width * ps;
1665 else
1666 *offset0 = *offset1;
aed74b55
CM		 1667 *row_inc = pixinc(1 +
1668 (y_predecim * screen_width - fbw * x_predecim) +
1669 (fieldmode ? screen_width : 0), ps);
1670 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1671 color_mode == OMAP_DSS_COLOR_UYVY)
1672 *pix_inc = pixinc(x_predecim, 2 * ps);
1673 else
1674 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1675 break;
1676 case OMAP_DSS_ROT_90:
1677 *offset1 = screen_width * (fbh - 1) * ps;
1678 if (field_offset)
1679 *offset0 = *offset1 + field_offset * ps;
1680 else
1681 *offset0 = *offset1;
aed74b55
CM		 1682 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1683 y_predecim + (fieldmode ? 1 : 0), ps);
1684 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1685 break;
1686 case OMAP_DSS_ROT_180:
1687 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1688 if (field_offset)
1689 *offset0 = *offset1 - field_offset * screen_width * ps;
1690 else
1691 *offset0 = *offset1;
1692 *row_inc = pixinc(-1 -
aed74b55
CM		 1693 (y_predecim * screen_width - fbw * x_predecim) -
1694 (fieldmode ? screen_width : 0), ps);
1695 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1696 color_mode == OMAP_DSS_COLOR_UYVY)
1697 *pix_inc = pixinc(-x_predecim, 2 * ps);
1698 else
1699 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1700 break;
1701 case OMAP_DSS_ROT_270:
1702 *offset1 = (fbw - 1) * ps;
1703 if (field_offset)
1704 *offset0 = *offset1 - field_offset * ps;
1705 else
1706 *offset0 = *offset1;
aed74b55
CM		 1707 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1708 y_predecim - (fieldmode ? 1 : 0), ps);
1709 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1710 break;
1711
1712 /* mirroring */
1713 case OMAP_DSS_ROT_0 + 4:
1714 *offset1 = (fbw - 1) * ps;
1715 if (field_offset)
1716 *offset0 = *offset1 + field_offset * screen_width * ps;
1717 else
1718 *offset0 = *offset1;
aed74b55 1719 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1720 (fieldmode ? screen_width : 0),
1721 ps);
aed74b55
CM		 1722 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1723 color_mode == OMAP_DSS_COLOR_UYVY)
1724 *pix_inc = pixinc(-x_predecim, 2 * ps);
1725 else
1726 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1727 break;
1728
1729 case OMAP_DSS_ROT_90 + 4:
1730 *offset1 = 0;
1731 if (field_offset)
1732 *offset0 = *offset1 + field_offset * ps;
1733 else
1734 *offset0 = *offset1;
aed74b55
CM		 1735 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1736 y_predecim + (fieldmode ? 1 : 0),
80c39712 1737 ps);
aed74b55 1738 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1739 break;
1740
1741 case OMAP_DSS_ROT_180 + 4:
1742 *offset1 = screen_width * (fbh - 1) * ps;
1743 if (field_offset)
1744 *offset0 = *offset1 - field_offset * screen_width * ps;
1745 else
1746 *offset0 = *offset1;
aed74b55 1747 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1748 (fieldmode ? screen_width : 0),
1749 ps);
aed74b55
CM		 1750 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1751 color_mode == OMAP_DSS_COLOR_UYVY)
1752 *pix_inc = pixinc(x_predecim, 2 * ps);
1753 else
1754 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1755 break;
1756
1757 case OMAP_DSS_ROT_270 + 4:
1758 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1759 if (field_offset)
1760 *offset0 = *offset1 - field_offset * ps;
1761 else
1762 *offset0 = *offset1;
aed74b55
CM		 1763 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1764 y_predecim - (fieldmode ? 1 : 0),
80c39712 1765 ps);
aed74b55 1766 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1767 break;
1768
1769 default:
1770 BUG();
c6eee968 1771 return;
80c39712
TV		 1772 }
1773}
1774
65e006ff
CM		 1775static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1776 enum omap_color_mode color_mode, bool fieldmode,
1777 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1778 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1779{
1780 u8 ps;
1781
1782 switch (color_mode) {
1783 case OMAP_DSS_COLOR_CLUT1:
1784 case OMAP_DSS_COLOR_CLUT2:
1785 case OMAP_DSS_COLOR_CLUT4:
1786 case OMAP_DSS_COLOR_CLUT8:
1787 BUG();
1788 return;
1789 default:
1790 ps = color_mode_to_bpp(color_mode) / 8;
1791 break;
1792 }
1793
1794 DSSDBG("scrw %d, width %d\n", screen_width, width);
1795
1796 /*
1797 * field 0 = even field = bottom field
1798 * field 1 = odd field = top field
1799 */
1800 *offset1 = 0;
1801 if (field_offset)
1802 *offset0 = *offset1 + field_offset * screen_width * ps;
1803 else
1804 *offset0 = *offset1;
1805 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1806 (fieldmode ? screen_width : 0), ps);
1807 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1808 color_mode == OMAP_DSS_COLOR_UYVY)
1809 *pix_inc = pixinc(x_predecim, 2 * ps);
1810 else
1811 *pix_inc = pixinc(x_predecim, ps);
1812}
1813
7faa9233
CM		 1814/*
1815 * This function is used to avoid synclosts in OMAP3, because of some
1816 * undocumented horizontal position and timing related limitations.
1817 */
81ab95b7
AT		 1818static int check_horiz_timing_omap3(enum omap_channel channel,
1819 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1820 u16 width, u16 height, u16 out_width, u16 out_height)
1821{
1822 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1823 unsigned long nonactive, lclk, pclk;
1824 static const u8 limits[3] = { 8, 10, 20 };
1825 u64 val, blank;
1826 int i;
1827
81ab95b7 1828 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 1829 pclk = dispc_mgr_pclk_rate(channel);
1830 if (dispc_mgr_is_lcd(channel))
1831 lclk = dispc_mgr_lclk_rate(channel);
1832 else
1833 lclk = dispc_fclk_rate();
1834
1835 i = 0;
1836 if (out_height < height)
1837 i++;
1838 if (out_width < width)
1839 i++;
81ab95b7 1840 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1841 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1842 if (blank <= limits[i])
1843 return -EINVAL;
1844
1845 /*
1846 * Pixel data should be prepared before visible display point starts.
1847 * So, atleast DS-2 lines must have already been fetched by DISPC
1848 * during nonactive - pos_x period.
1849 */
1850 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1851 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1852 val, max(0, DS - 2) * width);
1853 if (val < max(0, DS - 2) * width)
1854 return -EINVAL;
1855
1856 /*
1857 * All lines need to be refilled during the nonactive period of which
1858 * only one line can be loaded during the active period. So, atleast
1859 * DS - 1 lines should be loaded during nonactive period.
1860 */
1861 val = div_u64((u64)nonactive * lclk, pclk);
1862 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1863 val, max(0, DS - 1) * width);
1864 if (val < max(0, DS - 1) * width)
1865 return -EINVAL;
1866
1867 return 0;
1868}
1869
8b53d991 1870static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1871 const struct omap_video_timings *mgr_timings, u16 width,
1872 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1873 enum omap_color_mode color_mode)
80c39712 1874{
8b53d991 1875 u32 core_clk = 0;
26d9dd0d 1876 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1877
7282f1b7
CM		 1878 if (height <= out_height && width <= out_width)
1879 return (unsigned long) pclk;
1880
80c39712 1881 if (height > out_height) {
81ab95b7 1882 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1883
1884 tmp = pclk * height * out_width;
1885 do_div(tmp, 2 * out_height * ppl);
8b53d991 1886 core_clk = tmp;
80c39712 1887
2d9c5597
VS		 1888 if (height > 2 * out_height) {
1889 if (ppl == out_width)
1890 return 0;
1891
80c39712
TV		 1892 tmp = pclk * (height - 2 * out_height) * out_width;
1893 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1894 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1895 }
1896 }
1897
1898 if (width > out_width) {
1899 tmp = pclk * width;
1900 do_div(tmp, out_width);
8b53d991 1901 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1902
1903 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1904 core_clk <<= 1;
80c39712
TV		 1905 }
1906
8b53d991 1907 return core_clk;
80c39712
TV		 1908}
1909
8b53d991 1910static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
ff1b2cde 1911 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1912{
1913 unsigned int hf, vf;
79ee89cd 1914 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1915
1916 /*
1917 * FIXME how to determine the 'A' factor
1918 * for the no downscaling case ?
1919 */
1920
1921 if (width > 3 * out_width)
1922 hf = 4;
1923 else if (width > 2 * out_width)
1924 hf = 3;
1925 else if (width > out_width)
1926 hf = 2;
1927 else
1928 hf = 1;
1929
1930 if (height > out_height)
1931 vf = 2;
1932 else
1933 vf = 1;
1934
7282f1b7
CM		 1935 if (cpu_is_omap24xx()) {
1936 if (vf > 1 && hf > 1)
79ee89cd 1937 return pclk * 4;
7282f1b7 1938 else
79ee89cd 1939 return pclk * 2;
7282f1b7 1940 } else if (cpu_is_omap34xx()) {
79ee89cd 1941 return pclk * vf * hf;
7282f1b7 1942 } else {
79ee89cd
AT		 1943 if (hf > 1)
1944 return DIV_ROUND_UP(pclk, out_width) * width;
1945 else
1946 return pclk;
7282f1b7 1947 }
80c39712
TV		 1948}
1949
79ad75f2 1950static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 1951 enum omap_channel channel,
1952 const struct omap_video_timings *mgr_timings,
1953 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 1954 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 1955 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 1956{
1957 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1958 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1959 const int maxsinglelinewidth =
1960 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
aed74b55 1961 const int max_decim_limit = 16;
8b53d991 1962 unsigned long core_clk = 0;
aed74b55
CM		 1963 int decim_x, decim_y, error, min_factor;
1964 u16 in_width, in_height, in_width_max = 0;
79ad75f2 1965
f95cb5eb
TV		 1966 if (width == out_width && height == out_height)
1967 return 0;
1968
1969 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1970 return -EINVAL;
79ad75f2 1971
aed74b55
CM		 1972 *x_predecim = max_decim_limit;
1973 *y_predecim = max_decim_limit;
1974
1975 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
1976 color_mode == OMAP_DSS_COLOR_CLUT2 ||
1977 color_mode == OMAP_DSS_COLOR_CLUT4 ||
1978 color_mode == OMAP_DSS_COLOR_CLUT8) {
1979 *x_predecim = 1;
1980 *y_predecim = 1;
1981 *five_taps = false;
1982 return 0;
1983 }
1984
1985 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
1986 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
1987
1988 min_factor = min(decim_x, decim_y);
1989
1990 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 1991 return -EINVAL;
1992
aed74b55 1993 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 1994 return -EINVAL;
1995
7282f1b7 1996 if (cpu_is_omap24xx()) {
7282f1b7 1997 *five_taps = false;
aed74b55
CM		 1998
1999 do {
2000 in_height = DIV_ROUND_UP(height, decim_y);
2001 in_width = DIV_ROUND_UP(width, decim_x);
8b53d991 2002 core_clk = calc_core_clk(channel, in_width, in_height,
aed74b55 2003 out_width, out_height);
8b53d991
CM		 2004 error = (in_width > maxsinglelinewidth || !core_clk ||
2005 core_clk > dispc_core_clk_rate());
aed74b55
CM		 2006 if (error) {
2007 if (decim_x == decim_y) {
2008 decim_x = min_factor;
2009 decim_y++;
2010 } else {
2011 swap(decim_x, decim_y);
2012 if (decim_x < decim_y)
2013 decim_x++;
2014 }
2015 }
2016 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
2017 error);
2018
2019 if (in_width > maxsinglelinewidth) {
2020 DSSERR("Cannot scale max input width exceeded");
2021 return -EINVAL;
2022 }
7282f1b7 2023 } else if (cpu_is_omap34xx()) {
aed74b55
CM		 2024
2025 do {
2026 in_height = DIV_ROUND_UP(height, decim_y);
2027 in_width = DIV_ROUND_UP(width, decim_x);
81ab95b7
AT		 2028 core_clk = calc_core_clk_five_taps(channel, mgr_timings,
2029 in_width, in_height, out_width, out_height,
2030 color_mode);
aed74b55 2031
81ab95b7
AT		 2032 error = check_horiz_timing_omap3(channel, mgr_timings,
2033 pos_x, in_width, in_height, out_width,
2034 out_height);
7faa9233 2035
aed74b55
CM		 2036 if (in_width > maxsinglelinewidth)
2037 if (in_height > out_height &&
2038 in_height < out_height * 2)
2039 *five_taps = false;
2040 if (!*five_taps)
8b53d991
CM		 2041 core_clk = calc_core_clk(channel, in_width,
2042 in_height, out_width, out_height);
7faa9233 2043 error = (error || in_width > maxsinglelinewidth * 2 ||
aed74b55 2044 (in_width > maxsinglelinewidth && *five_taps) ||
8b53d991 2045 !core_clk || core_clk > dispc_core_clk_rate());
aed74b55
CM		 2046 if (error) {
2047 if (decim_x == decim_y) {
2048 decim_x = min_factor;
2049 decim_y++;
2050 } else {
2051 swap(decim_x, decim_y);
2052 if (decim_x < decim_y)
2053 decim_x++;
2054 }
2055 }
2056 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
2057 && error);
2058
81ab95b7
AT		 2059 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
2060 height, out_width, out_height)){
7faa9233
CM		 2061 DSSERR("horizontal timing too tight\n");
2062 return -EINVAL;
2063 }
2064
aed74b55 2065 if (in_width > (maxsinglelinewidth * 2)) {
7282f1b7
CM		 2066 DSSERR("Cannot setup scaling");
2067 DSSERR("width exceeds maximum width possible");
2068 return -EINVAL;
2069 }
aed74b55
CM		 2070
2071 if (in_width > maxsinglelinewidth && *five_taps) {
2072 DSSERR("cannot setup scaling with five taps");
2073 return -EINVAL;
7282f1b7 2074 }
7282f1b7 2075 } else {
aed74b55
CM		 2076 int decim_x_min = decim_x;
2077 in_height = DIV_ROUND_UP(height, decim_y);
8b53d991 2078 in_width_max = dispc_core_clk_rate() /
aed74b55
CM		 2079 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
2080 out_width);
2081 decim_x = DIV_ROUND_UP(width, in_width_max);
2082
2083 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
2084 if (decim_x > *x_predecim)
2085 return -EINVAL;
2086
2087 do {
2088 in_width = DIV_ROUND_UP(width, decim_x);
2089 } while (decim_x <= *x_predecim &&
2090 in_width > maxsinglelinewidth && decim_x++);
2091
2092 if (in_width > maxsinglelinewidth) {
7282f1b7
CM		 2093 DSSERR("Cannot scale width exceeds max line width");
2094 return -EINVAL;
2095 }
aed74b55 2096
8b53d991
CM		 2097 core_clk = calc_core_clk(channel, in_width, in_height,
2098 out_width, out_height);
79ad75f2
AT		 2099 }
2100
8b53d991
CM		 2101 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2102 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2103
8b53d991 2104 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2105 DSSERR("failed to set up scaling, "
8b53d991
CM		 2106 "required core clk rate = %lu Hz, "
2107 "current core clk rate = %lu Hz\n",
2108 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2109 return -EINVAL;
2110 }
2111
aed74b55
CM		 2112 *x_predecim = decim_x;
2113 *y_predecim = decim_y;
79ad75f2
AT		 2114 return 0;
2115}
2116
a4273b7c 2117int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
81ab95b7
AT		 2118 bool ilace, bool replication,
2119 const struct omap_video_timings *mgr_timings)
80c39712 2120{
79ad75f2 2121 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 2122 bool five_taps = true;
80c39712 2123 bool fieldmode = 0;
79ad75f2 2124 int r, cconv = 0;
80c39712
TV		 2125 unsigned offset0, offset1;
2126 s32 row_inc;
2127 s32 pix_inc;
a4273b7c 2128 u16 frame_height = oi->height;
80c39712 2129 unsigned int field_offset = 0;
aed74b55
CM		 2130 u16 in_height = oi->height;
2131 u16 in_width = oi->width;
2132 u16 out_width, out_height;
2cc5d1af 2133 enum omap_channel channel;
aed74b55 2134 int x_predecim = 1, y_predecim = 1;
2cc5d1af
TV		 2135
2136 channel = dispc_ovl_get_channel_out(plane);
80c39712 2137
a4273b7c 2138 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 2139 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2140 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 2141 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2142 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 2143 oi->mirror, ilace, channel, replication);
e6d80f95 2144
a4273b7c 2145 if (oi->paddr == 0)
80c39712
TV		 2146 return -EINVAL;
2147
aed74b55
CM		 2148 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2149 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 2150
aed74b55 2151 if (ilace && oi->height == out_height)
80c39712
TV		 2152 fieldmode = 1;
2153
2154 if (ilace) {
2155 if (fieldmode)
aed74b55 2156 in_height /= 2;
a4273b7c 2157 oi->pos_y /= 2;
aed74b55 2158 out_height /= 2;
80c39712
TV		 2159
2160 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2161 "out_height %d\n",
aed74b55 2162 in_height, oi->pos_y, out_height);
80c39712
TV		 2163 }
2164
a4273b7c 2165 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2166 return -EINVAL;
2167
81ab95b7
AT		 2168 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2169 in_height, out_width, out_height, oi->color_mode,
2170 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 2171 if (r)
2172 return r;
80c39712 2173
aed74b55
CM		 2174 in_width = DIV_ROUND_UP(in_width, x_predecim);
2175 in_height = DIV_ROUND_UP(in_height, y_predecim);
2176
79ad75f2
AT		 2177 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2178 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2179 oi->color_mode == OMAP_DSS_COLOR_NV12)
2180 cconv = 1;
80c39712
TV		 2181
2182 if (ilace && !fieldmode) {
2183 /*
2184 * when downscaling the bottom field may have to start several
2185 * source lines below the top field. Unfortunately ACCUI
2186 * registers will only hold the fractional part of the offset
2187 * so the integer part must be added to the base address of the
2188 * bottom field.
2189 */
aed74b55 2190 if (!in_height || in_height == out_height)
80c39712
TV		 2191 field_offset = 0;
2192 else
aed74b55 2193 field_offset = in_height / out_height / 2;
80c39712
TV		 2194 }
2195
2196 /* Fields are independent but interleaved in memory. */
2197 if (fieldmode)
2198 field_offset = 1;
2199
c6eee968
TV		 2200 offset0 = 0;
2201 offset1 = 0;
2202 row_inc = 0;
2203 pix_inc = 0;
2204
65e006ff
CM		 2205 if (oi->rotation_type == OMAP_DSS_ROT_TILER)
2206 calc_tiler_rotation_offset(oi->screen_width, in_width,
2207 oi->color_mode, fieldmode, field_offset,
2208 &offset0, &offset1, &row_inc, &pix_inc,
2209 x_predecim, y_predecim);
2210 else if (oi->rotation_type == OMAP_DSS_ROT_DMA)
a4273b7c 2211 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2212 oi->screen_width, in_width, frame_height,
a4273b7c 2213 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2214 &offset0, &offset1, &row_inc, &pix_inc,
2215 x_predecim, y_predecim);
80c39712 2216 else
a4273b7c 2217 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2218 oi->screen_width, in_width, frame_height,
a4273b7c 2219 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2220 &offset0, &offset1, &row_inc, &pix_inc,
2221 x_predecim, y_predecim);
80c39712
TV		 2222
2223 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2224 offset0, offset1, row_inc, pix_inc);
2225
a4273b7c 2226 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2227
65e006ff
CM		 2228 dispc_ovl_configure_burst_type(plane, oi->rotation_type);
2229
a4273b7c
AT		 2230 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2231 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2232
a4273b7c
AT		 2233 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2234 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2235 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2236 }
2237
2238
f0e5caab
TV		 2239 dispc_ovl_set_row_inc(plane, row_inc);
2240 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2241
aed74b55
CM		 2242 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2243 in_height, out_width, out_height);
80c39712 2244
a4273b7c 2245 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2246
aed74b55 2247 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2248
79ad75f2 2249 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2250 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2251 out_height, ilace, five_taps, fieldmode,
a4273b7c 2252 oi->color_mode, oi->rotation);
aed74b55 2253 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2254 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2255 }
2256
a4273b7c
AT		 2257 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2258 oi->color_mode);
80c39712 2259
54128701 2260 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2261 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2262 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2263
c3d92529 2264 dispc_ovl_enable_replication(plane, replication);
c3d92529 2265
80c39712
TV		 2266 return 0;
2267}
2268
f0e5caab 2269int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2270{
e6d80f95
TV		 2271 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2272
9b372c2d 2273 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2274
2275 return 0;
80c39712
TV		 2276}
2277
2278static void dispc_disable_isr(void *data, u32 mask)
2279{
2280 struct completion *compl = data;
2281 complete(compl);
2282}
2283
2a205f34 2284static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2285{
efa70b3b
CM		 2286 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2287 /* flush posted write */
2288 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2289}
2290
26d9dd0d 2291static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2292{
2293 struct completion frame_done_completion;
2294 bool is_on;
2295 int r;
2a205f34 2296 u32 irq;
80c39712 2297
80c39712
TV		 2298 /* When we disable LCD output, we need to wait until frame is done.
2299 * Otherwise the DSS is still working, and turning off the clocks
2300 * prevents DSS from going to OFF mode */
efa70b3b 2301 is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2a205f34 2302
efa70b3b 2303 irq = mgr_desc[channel].framedone_irq;
80c39712
TV		 2304
2305 if (!enable && is_on) {
2306 init_completion(&frame_done_completion);
2307
2308 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2309 &frame_done_completion, irq);
80c39712
TV		 2310
2311 if (r)
2312 DSSERR("failed to register FRAMEDONE isr\n");
2313 }
2314
2a205f34 2315 _enable_lcd_out(channel, enable);
80c39712
TV		 2316
2317 if (!enable && is_on) {
2318 if (!wait_for_completion_timeout(&frame_done_completion,
2319 msecs_to_jiffies(100)))
2320 DSSERR("timeout waiting for FRAME DONE\n");
2321
2322 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2323 &frame_done_completion, irq);
80c39712
TV		 2324
2325 if (r)
2326 DSSERR("failed to unregister FRAMEDONE isr\n");
2327 }
80c39712
TV		 2328}
2329
2330static void _enable_digit_out(bool enable)
2331{
2332 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2333 /* flush posted write */
2334 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2335}
2336
26d9dd0d 2337static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2338{
2339 struct completion frame_done_completion;
e82b090b
TV		 2340 enum dss_hdmi_venc_clk_source_select src;
2341 int r, i;
2342 u32 irq_mask;
2343 int num_irqs;
80c39712 2344
e6d80f95 2345 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2346 return;
80c39712 2347
e82b090b
TV		 2348 src = dss_get_hdmi_venc_clk_source();
2349
80c39712
TV		 2350 if (enable) {
2351 unsigned long flags;
2352 /* When we enable digit output, we'll get an extra digit
2353 * sync lost interrupt, that we need to ignore */
2354 spin_lock_irqsave(&dispc.irq_lock, flags);
2355 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2356 _omap_dispc_set_irqs();
2357 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2358 }
2359
2360 /* When we disable digit output, we need to wait until fields are done.
2361 * Otherwise the DSS is still working, and turning off the clocks
2362 * prevents DSS from going to OFF mode. And when enabling, we need to
2363 * wait for the extra sync losts */
2364 init_completion(&frame_done_completion);
2365
e82b090b
TV		 2366 if (src == DSS_HDMI_M_PCLK && enable == false) {
2367 irq_mask = DISPC_IRQ_FRAMEDONETV;
2368 num_irqs = 1;
2369 } else {
2370 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2371 /* XXX I understand from TRM that we should only wait for the
2372 * current field to complete. But it seems we have to wait for
2373 * both fields */
2374 num_irqs = 2;
2375 }
2376
80c39712 2377 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2378 irq_mask);
80c39712 2379 if (r)
e82b090b 2380 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2381
2382 _enable_digit_out(enable);
2383
e82b090b
TV		 2384 for (i = 0; i < num_irqs; ++i) {
2385 if (!wait_for_completion_timeout(&frame_done_completion,
2386 msecs_to_jiffies(100)))
2387 DSSERR("timeout waiting for digit out to %s\n",
2388 enable ? "start" : "stop");
2389 }
80c39712 2390
e82b090b
TV		 2391 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2392 irq_mask);
80c39712 2393 if (r)
e82b090b 2394 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2395
2396 if (enable) {
2397 unsigned long flags;
2398 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2399 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2400 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2401 _omap_dispc_set_irqs();
2402 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2403 }
80c39712
TV		 2404}
2405
26d9dd0d 2406bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84 2407{
efa70b3b 2408 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
a2faee84
TV		 2409}
2410
26d9dd0d 2411void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2412{
dac57a05 2413 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2414 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2415 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2416 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2417 else
2418 BUG();
2419}
2420
80c39712
TV		 2421void dispc_lcd_enable_signal_polarity(bool act_high)
2422{
6ced40bf
AT		 2423 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2424 return;
2425
80c39712 2426 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2427}
2428
2429void dispc_lcd_enable_signal(bool enable)
2430{
6ced40bf
AT		 2431 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2432 return;
2433
80c39712 2434 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2435}
2436
2437void dispc_pck_free_enable(bool enable)
2438{
6ced40bf
AT		 2439 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2440 return;
2441
80c39712 2442 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2443}
2444
26d9dd0d 2445void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2446{
efa70b3b 2447 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2448}
2449
2450
26d9dd0d 2451void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2452 enum omap_lcd_display_type type)
80c39712
TV		 2453{
2454 int mode;
2455
2456 switch (type) {
2457 case OMAP_DSS_LCD_DISPLAY_STN:
2458 mode = 0;
2459 break;
2460
2461 case OMAP_DSS_LCD_DISPLAY_TFT:
2462 mode = 1;
2463 break;
2464
2465 default:
2466 BUG();
2467 return;
2468 }
2469
efa70b3b 2470 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, mode);
80c39712
TV		 2471}
2472
2473void dispc_set_loadmode(enum omap_dss_load_mode mode)
2474{
80c39712 2475 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2476}
2477
2478
c64dca40 2479static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2480{
8613b000 2481 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2482}
2483
c64dca40 2484static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2485 enum omap_dss_trans_key_type type,
2486 u32 trans_key)
2487{
efa70b3b 2488 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2489
8613b000 2490 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2491}
2492
c64dca40 2493static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2494{
efa70b3b 2495 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2496}
11354dd5 2497
c64dca40
TV		 2498static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2499 bool enable)
80c39712 2500{
11354dd5 2501 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2502 return;
2503
80c39712
TV		 2504 if (ch == OMAP_DSS_CHANNEL_LCD)
2505 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2506 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2507 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2508}
11354dd5 2509
c64dca40
TV		 2510void dispc_mgr_setup(enum omap_channel channel,
2511 struct omap_overlay_manager_info *info)
2512{
2513 dispc_mgr_set_default_color(channel, info->default_color);
2514 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2515 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2516 dispc_mgr_enable_alpha_fixed_zorder(channel,
2517 info->partial_alpha_enabled);
2518 if (dss_has_feature(FEAT_CPR)) {
2519 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2520 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2521 }
2522}
80c39712 2523
26d9dd0d 2524void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2525{
2526 int code;
2527
2528 switch (data_lines) {
2529 case 12:
2530 code = 0;
2531 break;
2532 case 16:
2533 code = 1;
2534 break;
2535 case 18:
2536 code = 2;
2537 break;
2538 case 24:
2539 code = 3;
2540 break;
2541 default:
2542 BUG();
2543 return;
2544 }
2545
efa70b3b 2546 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2547}
2548
569969d6 2549void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2550{
2551 u32 l;
569969d6 2552 int gpout0, gpout1;
80c39712
TV		 2553
2554 switch (mode) {
569969d6
AT		 2555 case DSS_IO_PAD_MODE_RESET:
2556 gpout0 = 0;
2557 gpout1 = 0;
80c39712 2558 break;
569969d6
AT		 2559 case DSS_IO_PAD_MODE_RFBI:
2560 gpout0 = 1;
80c39712
TV		 2561 gpout1 = 0;
2562 break;
569969d6
AT		 2563 case DSS_IO_PAD_MODE_BYPASS:
2564 gpout0 = 1;
80c39712
TV		 2565 gpout1 = 1;
2566 break;
80c39712
TV		 2567 default:
2568 BUG();
2569 return;
2570 }
2571
569969d6
AT		 2572 l = dispc_read_reg(DISPC_CONTROL);
2573 l = FLD_MOD(l, gpout0, 15, 15);
2574 l = FLD_MOD(l, gpout1, 16, 16);
2575 dispc_write_reg(DISPC_CONTROL, l);
2576}
2577
2578void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2579{
efa70b3b 2580 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2581}
2582
8f366162
AT		 2583static bool _dispc_mgr_size_ok(u16 width, u16 height)
2584{
2585 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2586 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2587}
2588
80c39712
TV		 2589static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2590 int vsw, int vfp, int vbp)
2591{
2592 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2593 if (hsw < 1 || hsw > 64 ||
2594 hfp < 1 || hfp > 256 ||
2595 hbp < 1 || hbp > 256 ||
2596 vsw < 1 || vsw > 64 ||
2597 vfp < 0 || vfp > 255 ||
2598 vbp < 0 || vbp > 255)
2599 return false;
2600 } else {
2601 if (hsw < 1 || hsw > 256 ||
2602 hfp < 1 || hfp > 4096 ||
2603 hbp < 1 || hbp > 4096 ||
2604 vsw < 1 || vsw > 256 ||
2605 vfp < 0 || vfp > 4095 ||
2606 vbp < 0 || vbp > 4095)
2607 return false;
2608 }
2609
2610 return true;
2611}
2612
8f366162 2613bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2614 const struct omap_video_timings *timings)
80c39712 2615{
8f366162
AT		 2616 bool timings_ok;
2617
2618 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2619
2620 if (dispc_mgr_is_lcd(channel))
2621 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2622 timings->hfp, timings->hbp,
2623 timings->vsw, timings->vfp,
2624 timings->vbp);
2625
2626 return timings_ok;
80c39712
TV		 2627}
2628
26d9dd0d 2629static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2630 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2631{
2632 u32 timing_h, timing_v;
2633
2634 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2635 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2636 FLD_VAL(hbp-1, 27, 20);
2637
2638 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2639 FLD_VAL(vbp, 27, 20);
2640 } else {
2641 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2642 FLD_VAL(hbp-1, 31, 20);
2643
2644 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2645 FLD_VAL(vbp, 31, 20);
2646 }
2647
64ba4f74
SS		 2648 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2649 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2650}
2651
2652/* change name to mode? */
c51d921a 2653void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2654 struct omap_video_timings *timings)
80c39712
TV		 2655{
2656 unsigned xtot, ytot;
2657 unsigned long ht, vt;
2aefad49 2658 struct omap_video_timings t = *timings;
80c39712 2659
2aefad49 2660 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 2661
2aefad49 2662 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2663 BUG();
c6eee968
TV		 2664 return;
2665 }
80c39712 2666
8f366162 2667 if (dispc_mgr_is_lcd(channel)) {
2aefad49
AT		 2668 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2669 t.vfp, t.vbp);
80c39712 2670
2aefad49
AT		 2671 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2672 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 2673
c51d921a
AT		 2674 ht = (timings->pixel_clock * 1000) / xtot;
2675 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2676
2677 DSSDBG("pck %u\n", timings->pixel_clock);
2678 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 2679 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
80c39712 2680
c51d921a 2681 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49
AT		 2682 } else {
2683 enum dss_hdmi_venc_clk_source_select source;
2684
2685 source = dss_get_hdmi_venc_clk_source();
2686
2687 if (source == DSS_VENC_TV_CLK)
2688 t.y_res /= 2;
c51d921a 2689 }
8f366162 2690
2aefad49 2691 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 2692}
2693
26d9dd0d 2694static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2695 u16 pck_div)
80c39712
TV		 2696{
2697 BUG_ON(lck_div < 1);
9eaaf207 2698 BUG_ON(pck_div < 1);
80c39712 2699
ce7fa5eb 2700 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2701 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2702}
2703
26d9dd0d 2704static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2705 int *pck_div)
80c39712
TV		 2706{
2707 u32 l;
ce7fa5eb 2708 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2709 *lck_div = FLD_GET(l, 23, 16);
2710 *pck_div = FLD_GET(l, 7, 0);
2711}
2712
2713unsigned long dispc_fclk_rate(void)
2714{
a72b64b9 2715 struct platform_device *dsidev;
80c39712
TV		 2716 unsigned long r = 0;
2717
66534e8e 2718 switch (dss_get_dispc_clk_source()) {
89a35e51 2719 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2720 r = clk_get_rate(dispc.dss_clk);
66534e8e 2721 break;
89a35e51 2722 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2723 dsidev = dsi_get_dsidev_from_id(0);
2724 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2725 break;
5a8b572d
AT		 2726 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2727 dsidev = dsi_get_dsidev_from_id(1);
2728 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2729 break;
66534e8e
TA		 2730 default:
2731 BUG();
c6eee968 2732 return 0;
66534e8e
TA		 2733 }
2734
80c39712
TV		 2735 return r;
2736}
2737
26d9dd0d 2738unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2739{
a72b64b9 2740 struct platform_device *dsidev;
80c39712
TV		 2741 int lcd;
2742 unsigned long r;
2743 u32 l;
2744
ce7fa5eb 2745 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2746
2747 lcd = FLD_GET(l, 23, 16);
2748
ea75159e 2749 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2750 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2751 r = clk_get_rate(dispc.dss_clk);
ea75159e 2752 break;
89a35e51 2753 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2754 dsidev = dsi_get_dsidev_from_id(0);
2755 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2756 break;
5a8b572d
AT		 2757 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2758 dsidev = dsi_get_dsidev_from_id(1);
2759 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2760 break;
ea75159e
TA		 2761 default:
2762 BUG();
c6eee968 2763 return 0;
ea75159e 2764 }
80c39712
TV		 2765
2766 return r / lcd;
2767}
2768
26d9dd0d 2769unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2770{
80c39712 2771 unsigned long r;
80c39712 2772
c3dc6a7a
AT		 2773 if (dispc_mgr_is_lcd(channel)) {
2774 int pcd;
2775 u32 l;
80c39712 2776
c3dc6a7a 2777 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2778
c3dc6a7a 2779 pcd = FLD_GET(l, 7, 0);
80c39712 2780
c3dc6a7a
AT		 2781 r = dispc_mgr_lclk_rate(channel);
2782
2783 return r / pcd;
2784 } else {
3fa03ba8 2785 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2786
3fa03ba8
AT		 2787 source = dss_get_hdmi_venc_clk_source();
2788
2789 switch (source) {
2790 case DSS_VENC_TV_CLK:
c3dc6a7a 2791 return venc_get_pixel_clock();
3fa03ba8 2792 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2793 return hdmi_get_pixel_clock();
2794 default:
2795 BUG();
c6eee968 2796 return 0;
c3dc6a7a
AT		 2797 }
2798 }
80c39712
TV		 2799}
2800
8b53d991
CM		 2801unsigned long dispc_core_clk_rate(void)
2802{
2803 int lcd;
2804 unsigned long fclk = dispc_fclk_rate();
2805
2806 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2807 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2808 else
2809 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2810
2811 return fclk / lcd;
2812}
2813
80c39712
TV		 2814void dispc_dump_clocks(struct seq_file *s)
2815{
2816 int lcd, pcd;
0cf35df3 2817 u32 l;
89a35e51
AT		 2818 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2819 enum omap_dss_clk_source lcd_clk_src;
80c39712 2820
4fbafaf3
TV		 2821 if (dispc_runtime_get())
2822 return;
80c39712 2823
80c39712
TV		 2824 seq_printf(s, "- DISPC -\n");
2825
067a57e4
AT		 2826 seq_printf(s, "dispc fclk source = %s (%s)\n",
2827 dss_get_generic_clk_source_name(dispc_clk_src),
2828 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2829
2830 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2831
0cf35df3
MR		 2832 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2833 seq_printf(s, "- DISPC-CORE-CLK -\n");
2834 l = dispc_read_reg(DISPC_DIVISOR);
2835 lcd = FLD_GET(l, 23, 16);
2836
2837 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2838 (dispc_fclk_rate()/lcd), lcd);
2839 }
2a205f34
SS		 2840 seq_printf(s, "- LCD1 -\n");
2841
ea75159e
TA		 2842 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2843
2844 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2845 dss_get_generic_clk_source_name(lcd_clk_src),
2846 dss_feat_get_clk_source_name(lcd_clk_src));
2847
26d9dd0d 2848 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2849
ff1b2cde 2850 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2851 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2852 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2853 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2854 if (dss_has_feature(FEAT_MGR_LCD2)) {
2855 seq_printf(s, "- LCD2 -\n");
2856
ea75159e
TA		 2857 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2858
2859 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2860 dss_get_generic_clk_source_name(lcd_clk_src),
2861 dss_feat_get_clk_source_name(lcd_clk_src));
2862
26d9dd0d 2863 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2864
2a205f34 2865 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2866 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2867 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2868 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2869 }
4fbafaf3
TV		 2870
2871 dispc_runtime_put();
80c39712
TV		 2872}
2873
dfc0fd8d
TV		 2874#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2875void dispc_dump_irqs(struct seq_file *s)
2876{
2877 unsigned long flags;
2878 struct dispc_irq_stats stats;
2879
2880 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2881
2882 stats = dispc.irq_stats;
2883 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2884 dispc.irq_stats.last_reset = jiffies;
2885
2886 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2887
2888 seq_printf(s, "period %u ms\n",
2889 jiffies_to_msecs(jiffies - stats.last_reset));
2890
2891 seq_printf(s, "irqs %d\n", stats.irq_count);
2892#define PIS(x) \
2893 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2894
2895 PIS(FRAMEDONE);
2896 PIS(VSYNC);
2897 PIS(EVSYNC_EVEN);
2898 PIS(EVSYNC_ODD);
2899 PIS(ACBIAS_COUNT_STAT);
2900 PIS(PROG_LINE_NUM);
2901 PIS(GFX_FIFO_UNDERFLOW);
2902 PIS(GFX_END_WIN);
2903 PIS(PAL_GAMMA_MASK);
2904 PIS(OCP_ERR);
2905 PIS(VID1_FIFO_UNDERFLOW);
2906 PIS(VID1_END_WIN);
2907 PIS(VID2_FIFO_UNDERFLOW);
2908 PIS(VID2_END_WIN);
b8c095b4
AT		 2909 if (dss_feat_get_num_ovls() > 3) {
2910 PIS(VID3_FIFO_UNDERFLOW);
2911 PIS(VID3_END_WIN);
2912 }
dfc0fd8d
TV		 2913 PIS(SYNC_LOST);
2914 PIS(SYNC_LOST_DIGIT);
2915 PIS(WAKEUP);
2a205f34
SS		 2916 if (dss_has_feature(FEAT_MGR_LCD2)) {
2917 PIS(FRAMEDONE2);
2918 PIS(VSYNC2);
2919 PIS(ACBIAS_COUNT_STAT2);
2920 PIS(SYNC_LOST2);
2921 }
dfc0fd8d
TV		 2922#undef PIS
2923}
dfc0fd8d
TV		 2924#endif
2925
e40402cf 2926static void dispc_dump_regs(struct seq_file *s)
80c39712 2927{
4dd2da15
AT		 2928 int i, j;
2929 const char *mgr_names[] = {
2930 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2931 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2932 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2933 };
2934 const char *ovl_names[] = {
2935 [OMAP_DSS_GFX] = "GFX",
2936 [OMAP_DSS_VIDEO1] = "VID1",
2937 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2938 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2939 };
2940 const char **p_names;
2941
9b372c2d 2942#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2943
4fbafaf3
TV		 2944 if (dispc_runtime_get())
2945 return;
80c39712 2946
5010be80 2947 /* DISPC common registers */
80c39712
TV		 2948 DUMPREG(DISPC_REVISION);
2949 DUMPREG(DISPC_SYSCONFIG);
2950 DUMPREG(DISPC_SYSSTATUS);
2951 DUMPREG(DISPC_IRQSTATUS);
2952 DUMPREG(DISPC_IRQENABLE);
2953 DUMPREG(DISPC_CONTROL);
2954 DUMPREG(DISPC_CONFIG);
2955 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2956 DUMPREG(DISPC_LINE_STATUS);
2957 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2958 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2959 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2960 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2961 if (dss_has_feature(FEAT_MGR_LCD2)) {
2962 DUMPREG(DISPC_CONTROL2);
2963 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2964 }
2965
2966#undef DUMPREG
2967
2968#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2969#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2970 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2971 dispc_read_reg(DISPC_REG(i, r)))
2972
4dd2da15 2973 p_names = mgr_names;
5010be80 2974
4dd2da15
AT		 2975 /* DISPC channel specific registers */
2976 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2977 DUMPREG(i, DISPC_DEFAULT_COLOR);
2978 DUMPREG(i, DISPC_TRANS_COLOR);
2979 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2980
4dd2da15
AT		 2981 if (i == OMAP_DSS_CHANNEL_DIGIT)
2982 continue;
5010be80 2983
4dd2da15
AT		 2984 DUMPREG(i, DISPC_DEFAULT_COLOR);
2985 DUMPREG(i, DISPC_TRANS_COLOR);
2986 DUMPREG(i, DISPC_TIMING_H);
2987 DUMPREG(i, DISPC_TIMING_V);
2988 DUMPREG(i, DISPC_POL_FREQ);
2989 DUMPREG(i, DISPC_DIVISORo);
2990 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2991
4dd2da15
AT		 2992 DUMPREG(i, DISPC_DATA_CYCLE1);
2993 DUMPREG(i, DISPC_DATA_CYCLE2);
2994 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2995
332e9d70 2996 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2997 DUMPREG(i, DISPC_CPR_COEF_R);
2998 DUMPREG(i, DISPC_CPR_COEF_G);
2999 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3000 }
2a205f34 3001 }
80c39712 3002
4dd2da15
AT		 3003 p_names = ovl_names;
3004
3005 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3006 DUMPREG(i, DISPC_OVL_BA0);
3007 DUMPREG(i, DISPC_OVL_BA1);
3008 DUMPREG(i, DISPC_OVL_POSITION);
3009 DUMPREG(i, DISPC_OVL_SIZE);
3010 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3011 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3012 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3013 DUMPREG(i, DISPC_OVL_ROW_INC);
3014 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3015 if (dss_has_feature(FEAT_PRELOAD))
3016 DUMPREG(i, DISPC_OVL_PRELOAD);
3017
3018 if (i == OMAP_DSS_GFX) {
3019 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3020 DUMPREG(i, DISPC_OVL_TABLE_BA);
3021 continue;
3022 }
3023
3024 DUMPREG(i, DISPC_OVL_FIR);
3025 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3026 DUMPREG(i, DISPC_OVL_ACCU0);
3027 DUMPREG(i, DISPC_OVL_ACCU1);
3028 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3029 DUMPREG(i, DISPC_OVL_BA0_UV);
3030 DUMPREG(i, DISPC_OVL_BA1_UV);
3031 DUMPREG(i, DISPC_OVL_FIR2);
3032 DUMPREG(i, DISPC_OVL_ACCU2_0);
3033 DUMPREG(i, DISPC_OVL_ACCU2_1);
3034 }
3035 if (dss_has_feature(FEAT_ATTR2))
3036 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3037 if (dss_has_feature(FEAT_PRELOAD))
3038 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3039 }
5010be80
AT		 3040
3041#undef DISPC_REG
3042#undef DUMPREG
3043
3044#define DISPC_REG(plane, name, i) name(plane, i)
3045#define DUMPREG(plane, name, i) \
4dd2da15
AT		 3046 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3047 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 3048 dispc_read_reg(DISPC_REG(plane, name, i)))
3049
4dd2da15 3050 /* Video pipeline coefficient registers */
332e9d70 3051
4dd2da15
AT		 3052 /* start from OMAP_DSS_VIDEO1 */
3053 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3054 for (j = 0; j < 8; j++)
3055 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3056
4dd2da15
AT		 3057 for (j = 0; j < 8; j++)
3058 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3059
4dd2da15
AT		 3060 for (j = 0; j < 5; j++)
3061 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3062
4dd2da15
AT		 3063 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3064 for (j = 0; j < 8; j++)
3065 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3066 }
3067
3068 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3069 for (j = 0; j < 8; j++)
3070 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3071
3072 for (j = 0; j < 8; j++)
3073 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3074
3075 for (j = 0; j < 8; j++)
3076 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3077 }
332e9d70 3078 }
80c39712 3079
4fbafaf3 3080 dispc_runtime_put();
5010be80
AT		 3081
3082#undef DISPC_REG
80c39712
TV		 3083#undef DUMPREG
3084}
3085
26d9dd0d
TV		 3086static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
3087 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
3088 u8 acb)
80c39712
TV		 3089{
3090 u32 l = 0;
3091
3092 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
3093 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
3094
3095 l |= FLD_VAL(onoff, 17, 17);
3096 l |= FLD_VAL(rf, 16, 16);
3097 l |= FLD_VAL(ieo, 15, 15);
3098 l |= FLD_VAL(ipc, 14, 14);
3099 l |= FLD_VAL(ihs, 13, 13);
3100 l |= FLD_VAL(ivs, 12, 12);
3101 l |= FLD_VAL(acbi, 11, 8);
3102 l |= FLD_VAL(acb, 7, 0);
3103
ff1b2cde 3104 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3105}
3106
26d9dd0d 3107void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 3108 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 3109{
26d9dd0d 3110 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 3111 (config & OMAP_DSS_LCD_RF) != 0,
3112 (config & OMAP_DSS_LCD_IEO) != 0,
3113 (config & OMAP_DSS_LCD_IPC) != 0,
3114 (config & OMAP_DSS_LCD_IHS) != 0,
3115 (config & OMAP_DSS_LCD_IVS) != 0,
3116 acbi, acb);
3117}
3118
3119/* with fck as input clock rate, find dispc dividers that produce req_pck */
3120void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3121 struct dispc_clock_info *cinfo)
3122{
9eaaf207 3123 u16 pcd_min, pcd_max;
80c39712
TV		 3124 unsigned long best_pck;
3125 u16 best_ld, cur_ld;
3126 u16 best_pd, cur_pd;
3127
9eaaf207
TV		 3128 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3129 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3130
3131 if (!is_tft)
3132 pcd_min = 3;
3133
80c39712
TV		 3134 best_pck = 0;
3135 best_ld = 0;
3136 best_pd = 0;
3137
3138 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3139 unsigned long lck = fck / cur_ld;
3140
9eaaf207 3141 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3142 unsigned long pck = lck / cur_pd;
3143 long old_delta = abs(best_pck - req_pck);
3144 long new_delta = abs(pck - req_pck);
3145
3146 if (best_pck == 0 || new_delta < old_delta) {
3147 best_pck = pck;
3148 best_ld = cur_ld;
3149 best_pd = cur_pd;
3150
3151 if (pck == req_pck)
3152 goto found;
3153 }
3154
3155 if (pck < req_pck)
3156 break;
3157 }
3158
3159 if (lck / pcd_min < req_pck)
3160 break;
3161 }
3162
3163found:
3164 cinfo->lck_div = best_ld;
3165 cinfo->pck_div = best_pd;
3166 cinfo->lck = fck / cinfo->lck_div;
3167 cinfo->pck = cinfo->lck / cinfo->pck_div;
3168}
3169
3170/* calculate clock rates using dividers in cinfo */
3171int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3172 struct dispc_clock_info *cinfo)
3173{
3174 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3175 return -EINVAL;
9eaaf207 3176 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3177 return -EINVAL;
3178
3179 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3180 cinfo->pck = cinfo->lck / cinfo->pck_div;
3181
3182 return 0;
3183}
3184
26d9dd0d 3185int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3186 struct dispc_clock_info *cinfo)
80c39712
TV		 3187{
3188 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3189 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3190
26d9dd0d 3191 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3192
3193 return 0;
3194}
3195
26d9dd0d 3196int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3197 struct dispc_clock_info *cinfo)
80c39712
TV		 3198{
3199 unsigned long fck;
3200
3201 fck = dispc_fclk_rate();
3202
ce7fa5eb
MR		 3203 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3204 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3205
3206 cinfo->lck = fck / cinfo->lck_div;
3207 cinfo->pck = cinfo->lck / cinfo->pck_div;
3208
3209 return 0;
3210}
3211
3212/* dispc.irq_lock has to be locked by the caller */
3213static void _omap_dispc_set_irqs(void)
3214{
3215 u32 mask;
3216 u32 old_mask;
3217 int i;
3218 struct omap_dispc_isr_data *isr_data;
3219
3220 mask = dispc.irq_error_mask;
3221
3222 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3223 isr_data = &dispc.registered_isr[i];
3224
3225 if (isr_data->isr == NULL)
3226 continue;
3227
3228 mask |= isr_data->mask;
3229 }
3230
80c39712
TV		 3231 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3232 /* clear the irqstatus for newly enabled irqs */
3233 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3234
3235 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3236}
3237
3238int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3239{
3240 int i;
3241 int ret;
3242 unsigned long flags;
3243 struct omap_dispc_isr_data *isr_data;
3244
3245 if (isr == NULL)
3246 return -EINVAL;
3247
3248 spin_lock_irqsave(&dispc.irq_lock, flags);
3249
3250 /* check for duplicate entry */
3251 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3252 isr_data = &dispc.registered_isr[i];
3253 if (isr_data->isr == isr && isr_data->arg == arg &&
3254 isr_data->mask == mask) {
3255 ret = -EINVAL;
3256 goto err;
3257 }
3258 }
3259
3260 isr_data = NULL;
3261 ret = -EBUSY;
3262
3263 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3264 isr_data = &dispc.registered_isr[i];
3265
3266 if (isr_data->isr != NULL)
3267 continue;
3268
3269 isr_data->isr = isr;
3270 isr_data->arg = arg;
3271 isr_data->mask = mask;
3272 ret = 0;
3273
3274 break;
3275 }
3276
b9cb0984
TV		 3277 if (ret)
3278 goto err;
3279
80c39712
TV		 3280 _omap_dispc_set_irqs();
3281
3282 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3283
3284 return 0;
3285err:
3286 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3287
3288 return ret;
3289}
3290EXPORT_SYMBOL(omap_dispc_register_isr);
3291
3292int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3293{
3294 int i;
3295 unsigned long flags;
3296 int ret = -EINVAL;
3297 struct omap_dispc_isr_data *isr_data;
3298
3299 spin_lock_irqsave(&dispc.irq_lock, flags);
3300
3301 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3302 isr_data = &dispc.registered_isr[i];
3303 if (isr_data->isr != isr || isr_data->arg != arg ||
3304 isr_data->mask != mask)
3305 continue;
3306
3307 /* found the correct isr */
3308
3309 isr_data->isr = NULL;
3310 isr_data->arg = NULL;
3311 isr_data->mask = 0;
3312
3313 ret = 0;
3314 break;
3315 }
3316
3317 if (ret == 0)
3318 _omap_dispc_set_irqs();
3319
3320 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3321
3322 return ret;
3323}
3324EXPORT_SYMBOL(omap_dispc_unregister_isr);
3325
3326#ifdef DEBUG
3327static void print_irq_status(u32 status)
3328{
3329 if ((status & dispc.irq_error_mask) == 0)
3330 return;
3331
3332 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3333
3334#define PIS(x) \
3335 if (status & DISPC_IRQ_##x) \
3336 printk(#x " ");
3337 PIS(GFX_FIFO_UNDERFLOW);
3338 PIS(OCP_ERR);
3339 PIS(VID1_FIFO_UNDERFLOW);
3340 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3341 if (dss_feat_get_num_ovls() > 3)
3342 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3343 PIS(SYNC_LOST);
3344 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3345 if (dss_has_feature(FEAT_MGR_LCD2))
3346 PIS(SYNC_LOST2);
80c39712
TV		 3347#undef PIS
3348
3349 printk("\n");
3350}
3351#endif
3352
3353/* Called from dss.c. Note that we don't touch clocks here,
3354 * but we presume they are on because we got an IRQ. However,
3355 * an irq handler may turn the clocks off, so we may not have
3356 * clock later in the function. */
affe360d 3357static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3358{
3359 int i;
affe360d 3360 u32 irqstatus, irqenable;
80c39712
TV		 3361 u32 handledirqs = 0;
3362 u32 unhandled_errors;
3363 struct omap_dispc_isr_data *isr_data;
3364 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3365
3366 spin_lock(&dispc.irq_lock);
3367
3368 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3369 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3370
3371 /* IRQ is not for us */
3372 if (!(irqstatus & irqenable)) {
3373 spin_unlock(&dispc.irq_lock);
3374 return IRQ_NONE;
3375 }
80c39712 3376
dfc0fd8d
TV		 3377#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3378 spin_lock(&dispc.irq_stats_lock);
3379 dispc.irq_stats.irq_count++;
3380 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3381 spin_unlock(&dispc.irq_stats_lock);
3382#endif
3383
80c39712
TV		 3384#ifdef DEBUG
3385 if (dss_debug)
3386 print_irq_status(irqstatus);
3387#endif
3388 /* Ack the interrupt. Do it here before clocks are possibly turned
3389 * off */
3390 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3391 /* flush posted write */
3392 dispc_read_reg(DISPC_IRQSTATUS);
3393
3394 /* make a copy and unlock, so that isrs can unregister
3395 * themselves */
3396 memcpy(registered_isr, dispc.registered_isr,
3397 sizeof(registered_isr));
3398
3399 spin_unlock(&dispc.irq_lock);
3400
3401 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3402 isr_data = &registered_isr[i];
3403
3404 if (!isr_data->isr)
3405 continue;
3406
3407 if (isr_data->mask & irqstatus) {
3408 isr_data->isr(isr_data->arg, irqstatus);
3409 handledirqs |= isr_data->mask;
3410 }
3411 }
3412
3413 spin_lock(&dispc.irq_lock);
3414
3415 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3416
3417 if (unhandled_errors) {
3418 dispc.error_irqs |= unhandled_errors;
3419
3420 dispc.irq_error_mask &= ~unhandled_errors;
3421 _omap_dispc_set_irqs();
3422
3423 schedule_work(&dispc.error_work);
3424 }
3425
3426 spin_unlock(&dispc.irq_lock);
affe360d 3427
3428 return IRQ_HANDLED;
80c39712
TV		 3429}
3430
3431static void dispc_error_worker(struct work_struct *work)
3432{
3433 int i;
3434 u32 errors;
3435 unsigned long flags;
fe3cc9d6
TV		 3436 static const unsigned fifo_underflow_bits[] = {
3437 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3438 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3439 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3440 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3441 };
3442
80c39712
TV		 3443 spin_lock_irqsave(&dispc.irq_lock, flags);
3444 errors = dispc.error_irqs;
3445 dispc.error_irqs = 0;
3446 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3447
13eae1f9
DZ		 3448 dispc_runtime_get();
3449
fe3cc9d6
TV		 3450 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3451 struct omap_overlay *ovl;
3452 unsigned bit;
80c39712 3453
fe3cc9d6
TV		 3454 ovl = omap_dss_get_overlay(i);
3455 bit = fifo_underflow_bits[i];
80c39712 3456
fe3cc9d6
TV		 3457 if (bit & errors) {
3458 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3459 ovl->name);
f0e5caab 3460 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3461 dispc_mgr_go(ovl->manager->id);
80c39712 3462 mdelay(50);
80c39712
TV		 3463 }
3464 }
3465
fe3cc9d6
TV		 3466 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3467 struct omap_overlay_manager *mgr;
3468 unsigned bit;
80c39712 3469
fe3cc9d6 3470 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3471 bit = mgr_desc[i].sync_lost_irq;
80c39712 3472
fe3cc9d6
TV		 3473 if (bit & errors) {
3474 struct omap_dss_device *dssdev = mgr->device;
3475 bool enable;
80c39712 3476
fe3cc9d6
TV		 3477 DSSERR("SYNC_LOST on channel %s, restarting the output "
3478 "with video overlays disabled\n",
3479 mgr->name);
2a205f34 3480
fe3cc9d6
TV		 3481 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3482 dssdev->driver->disable(dssdev);
2a205f34 3483
2a205f34
SS		 3484 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3485 struct omap_overlay *ovl;
3486 ovl = omap_dss_get_overlay(i);
3487
fe3cc9d6
TV		 3488 if (ovl->id != OMAP_DSS_GFX &&
3489 ovl->manager == mgr)
f0e5caab 3490 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3491 }
3492
26d9dd0d 3493 dispc_mgr_go(mgr->id);
2a205f34 3494 mdelay(50);
fe3cc9d6 3495
2a205f34
SS		 3496 if (enable)
3497 dssdev->driver->enable(dssdev);
3498 }
3499 }
3500
80c39712
TV		 3501 if (errors & DISPC_IRQ_OCP_ERR) {
3502 DSSERR("OCP_ERR\n");
3503 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3504 struct omap_overlay_manager *mgr;
3505 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3506 if (mgr->device && mgr->device->driver)
3507 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3508 }
3509 }
3510
3511 spin_lock_irqsave(&dispc.irq_lock, flags);
3512 dispc.irq_error_mask |= errors;
3513 _omap_dispc_set_irqs();
3514 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3515
3516 dispc_runtime_put();
80c39712
TV		 3517}
3518
3519int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3520{
3521 void dispc_irq_wait_handler(void *data, u32 mask)
3522 {
3523 complete((struct completion *)data);
3524 }
3525
3526 int r;
3527 DECLARE_COMPLETION_ONSTACK(completion);
3528
3529 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3530 irqmask);
3531
3532 if (r)
3533 return r;
3534
3535 timeout = wait_for_completion_timeout(&completion, timeout);
3536
3537 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3538
3539 if (timeout == 0)
3540 return -ETIMEDOUT;
3541
3542 if (timeout == -ERESTARTSYS)
3543 return -ERESTARTSYS;
3544
3545 return 0;
3546}
3547
3548int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3549 unsigned long timeout)
3550{
3551 void dispc_irq_wait_handler(void *data, u32 mask)
3552 {
3553 complete((struct completion *)data);
3554 }
3555
3556 int r;
3557 DECLARE_COMPLETION_ONSTACK(completion);
3558
3559 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3560 irqmask);
3561
3562 if (r)
3563 return r;
3564
3565 timeout = wait_for_completion_interruptible_timeout(&completion,
3566 timeout);
3567
3568 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3569
3570 if (timeout == 0)
3571 return -ETIMEDOUT;
3572
3573 if (timeout == -ERESTARTSYS)
3574 return -ERESTARTSYS;
3575
3576 return 0;
3577}
3578
80c39712
TV		 3579static void _omap_dispc_initialize_irq(void)
3580{
3581 unsigned long flags;
3582
3583 spin_lock_irqsave(&dispc.irq_lock, flags);
3584
3585 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3586
3587 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3588 if (dss_has_feature(FEAT_MGR_LCD2))
3589 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3590 if (dss_feat_get_num_ovls() > 3)
3591 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3592
3593 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3594 * so clear it */
3595 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3596
3597 _omap_dispc_set_irqs();
3598
3599 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3600}
3601
3602void dispc_enable_sidle(void)
3603{
3604 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3605}
3606
3607void dispc_disable_sidle(void)
3608{
3609 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3610}
3611
3612static void _omap_dispc_initial_config(void)
3613{
3614 u32 l;
3615
0cf35df3
MR		 3616 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3617 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3618 l = dispc_read_reg(DISPC_DIVISOR);
3619 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3620 l = FLD_MOD(l, 1, 0, 0);
3621 l = FLD_MOD(l, 1, 23, 16);
3622 dispc_write_reg(DISPC_DIVISOR, l);
3623 }
3624
80c39712 3625 /* FUNCGATED */
6ced40bf
AT		 3626 if (dss_has_feature(FEAT_FUNCGATED))
3627 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3628
80c39712
TV		 3629 _dispc_setup_color_conv_coef();
3630
3631 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3632
3633 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3634
3635 dispc_configure_burst_sizes();
54128701
AT		 3636
3637 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3638}
3639
060b6d9c 3640/* DISPC HW IP initialisation */
6e7e8f06 3641static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3642{
3643 u32 rev;
affe360d 3644 int r = 0;
ea9da36a 3645 struct resource *dispc_mem;
4fbafaf3 3646 struct clk *clk;
ea9da36a 3647
060b6d9c
SG		 3648 dispc.pdev = pdev;
3649
3650 spin_lock_init(&dispc.irq_lock);
3651
3652#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3653 spin_lock_init(&dispc.irq_stats_lock);
3654 dispc.irq_stats.last_reset = jiffies;
3655#endif
3656
3657 INIT_WORK(&dispc.error_work, dispc_error_worker);
3658
ea9da36a
SG		 3659 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3660 if (!dispc_mem) {
3661 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3662 return -EINVAL;
ea9da36a 3663 }
cd3b3449 3664
6e2a14d2
JL		 3665 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3666 resource_size(dispc_mem));
060b6d9c
SG		 3667 if (!dispc.base) {
3668 DSSERR("can't ioremap DISPC\n");
cd3b3449 3669 return -ENOMEM;
affe360d 3670 }
cd3b3449 3671
affe360d 3672 dispc.irq = platform_get_irq(dispc.pdev, 0);
3673 if (dispc.irq < 0) {
3674 DSSERR("platform_get_irq failed\n");
cd3b3449 3675 return -ENODEV;
affe360d 3676 }
3677
6e2a14d2
JL		 3678 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3679 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3680 if (r < 0) {
3681 DSSERR("request_irq failed\n");
cd3b3449
TV		 3682 return r;
3683 }
3684
3685 clk = clk_get(&pdev->dev, "fck");
3686 if (IS_ERR(clk)) {
3687 DSSERR("can't get fck\n");
3688 r = PTR_ERR(clk);
3689 return r;
060b6d9c
SG		 3690 }
3691
cd3b3449
TV		 3692 dispc.dss_clk = clk;
3693
4fbafaf3
TV		 3694 pm_runtime_enable(&pdev->dev);
3695
3696 r = dispc_runtime_get();
3697 if (r)
3698 goto err_runtime_get;
060b6d9c
SG		 3699
3700 _omap_dispc_initial_config();
3701
3702 _omap_dispc_initialize_irq();
3703
060b6d9c 3704 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3705 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3706 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3707
4fbafaf3 3708 dispc_runtime_put();
060b6d9c 3709
e40402cf
TV		 3710 dss_debugfs_create_file("dispc", dispc_dump_regs);
3711
3712#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3713 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3714#endif
060b6d9c 3715 return 0;
4fbafaf3
TV		 3716
3717err_runtime_get:
3718 pm_runtime_disable(&pdev->dev);
4fbafaf3 3719 clk_put(dispc.dss_clk);
affe360d 3720 return r;
060b6d9c
SG		 3721}
3722
6e7e8f06 3723static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3724{
4fbafaf3
TV		 3725 pm_runtime_disable(&pdev->dev);
3726
3727 clk_put(dispc.dss_clk);
3728
060b6d9c
SG		 3729 return 0;
3730}
3731
4fbafaf3
TV		 3732static int dispc_runtime_suspend(struct device *dev)
3733{
3734 dispc_save_context();
4fbafaf3
TV		 3735
3736 return 0;
3737}
3738
3739static int dispc_runtime_resume(struct device *dev)
3740{
49ea86f3 3741 dispc_restore_context();
4fbafaf3
TV		 3742
3743 return 0;
3744}
3745
3746static const struct dev_pm_ops dispc_pm_ops = {
3747 .runtime_suspend = dispc_runtime_suspend,
3748 .runtime_resume = dispc_runtime_resume,
3749};
3750
060b6d9c 3751static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3752 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3753 .driver = {
3754 .name = "omapdss_dispc",
3755 .owner = THIS_MODULE,
4fbafaf3 3756 .pm = &dispc_pm_ops,
060b6d9c
SG		 3757 },
3758};
3759
6e7e8f06 3760int __init dispc_init_platform_driver(void)
060b6d9c 3761{
11436e1d 3762 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3763}
3764
6e7e8f06 3765void __exit dispc_uninit_platform_driver(void)
060b6d9c 3766{
04c742c3 3767 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3768}
Linux kernel - Deliverables
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