[deliverable/linux.git] / drivers / video / omap2 / dss / dpi.c

/*
 * linux/drivers/video/omap2/dss/dpi.c
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "DPI"

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#include <video/omapdss.h>
#include <plat/cpu.h>

#include "dss.h"

static struct {
	struct regulator *vdds_dsi_reg;
	struct platform_device *dsidev;
} dpi;

static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
{
	int dsi_module;

	dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;

	return dsi_get_dsidev_from_id(dsi_module);
}

static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
{
	if (dssdev->clocks.dispc.dispc_fclk_src ==
			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
			dssdev->clocks.dispc.dispc_fclk_src ==
			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
			dssdev->clocks.dispc.channel.lcd_clk_src ==
			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
			dssdev->clocks.dispc.channel.lcd_clk_src ==
			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
		return true;
	else
		return false;
}

static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
		unsigned long pck_req, unsigned long *fck, int *lck_div,
		int *pck_div)
{
	struct dsi_clock_info dsi_cinfo;
	struct dispc_clock_info dispc_cinfo;
	int r;

	r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
			&dsi_cinfo, &dispc_cinfo);
	if (r)
		return r;

	r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
	if (r)
		return r;

	dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);

	r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
	if (r)
		return r;

	*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
	*lck_div = dispc_cinfo.lck_div;
	*pck_div = dispc_cinfo.pck_div;

	return 0;
}

static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
		unsigned long pck_req, unsigned long *fck, int *lck_div,
		int *pck_div)
{
	struct dss_clock_info dss_cinfo;
	struct dispc_clock_info dispc_cinfo;
	int r;

	r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
	if (r)
		return r;

	r = dss_set_clock_div(&dss_cinfo);
	if (r)
		return r;

	r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
	if (r)
		return r;

	*fck = dss_cinfo.fck;
	*lck_div = dispc_cinfo.lck_div;
	*pck_div = dispc_cinfo.pck_div;

	return 0;
}

static int dpi_set_mode(struct omap_dss_device *dssdev)
{
	struct omap_video_timings *t = &dssdev->panel.timings;
	int lck_div = 0, pck_div = 0;
	unsigned long fck = 0;
	unsigned long pck;
	bool is_tft;
	int r = 0;

	dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
			dssdev->panel.acbi, dssdev->panel.acb);

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

	if (dpi_use_dsi_pll(dssdev))
		r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
				&fck, &lck_div, &pck_div);
	else
		r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
				&fck, &lck_div, &pck_div);
	if (r)
		return r;

	pck = fck / lck_div / pck_div / 1000;

	if (pck != t->pixel_clock) {
		DSSWARN("Could not find exact pixel clock. "
				"Requested %d kHz, got %lu kHz\n",
				t->pixel_clock, pck);

		t->pixel_clock = pck;
	}

	dispc_set_lcd_timings(dssdev->manager->id, t);

	return 0;
}

static void dpi_basic_init(struct omap_dss_device *dssdev)
{
	bool is_tft;

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

	dispc_set_parallel_interface_mode(dssdev->manager->id,
			OMAP_DSS_PARALLELMODE_BYPASS);
	dispc_set_lcd_display_type(dssdev->manager->id, is_tft ?
			OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
	dispc_set_tft_data_lines(dssdev->manager->id,
			dssdev->phy.dpi.data_lines);
}

int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
{
	int r;

	if (dssdev->manager == NULL) {
		DSSERR("failed to enable display: no manager\n");
		return -ENODEV;
	}

	r = omap_dss_start_device(dssdev);
	if (r) {
		DSSERR("failed to start device\n");
		goto err_start_dev;
	}

	if (cpu_is_omap34xx()) {
		r = regulator_enable(dpi.vdds_dsi_reg);
		if (r)
			goto err_reg_enable;
	}

	r = dss_runtime_get();
	if (r)
		goto err_get_dss;

	r = dispc_runtime_get();
	if (r)
		goto err_get_dispc;

	dpi_basic_init(dssdev);

	if (dpi_use_dsi_pll(dssdev)) {
		r = dsi_runtime_get(dpi.dsidev);
		if (r)
			goto err_get_dsi;

		r = dsi_pll_init(dpi.dsidev, 0, 1);
		if (r)
			goto err_dsi_pll_init;
	}

	r = dpi_set_mode(dssdev);
	if (r)
		goto err_set_mode;

	mdelay(2);

	dssdev->manager->enable(dssdev->manager);

	return 0;

err_set_mode:
	if (dpi_use_dsi_pll(dssdev))
		dsi_pll_uninit(dpi.dsidev, true);
err_dsi_pll_init:
	if (dpi_use_dsi_pll(dssdev))
		dsi_runtime_put(dpi.dsidev);
err_get_dsi:
	dispc_runtime_put();
err_get_dispc:
	dss_runtime_put();
err_get_dss:
	if (cpu_is_omap34xx())
		regulator_disable(dpi.vdds_dsi_reg);
err_reg_enable:
	omap_dss_stop_device(dssdev);
err_start_dev:
	return r;
}
EXPORT_SYMBOL(omapdss_dpi_display_enable);

void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
{
	dssdev->manager->disable(dssdev->manager);

	if (dpi_use_dsi_pll(dssdev)) {
		dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
		dsi_pll_uninit(dpi.dsidev, true);
		dsi_runtime_put(dpi.dsidev);
	}

	dispc_runtime_put();
	dss_runtime_put();

	if (cpu_is_omap34xx())
		regulator_disable(dpi.vdds_dsi_reg);

	omap_dss_stop_device(dssdev);
}
EXPORT_SYMBOL(omapdss_dpi_display_disable);

void dpi_set_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings)
{
	int r;

	DSSDBG("dpi_set_timings\n");
	dssdev->panel.timings = *timings;
	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
		r = dss_runtime_get();
		if (r)
			return;

		r = dispc_runtime_get();
		if (r) {
			dss_runtime_put();
			return;
		}

		dpi_set_mode(dssdev);
		dispc_go(dssdev->manager->id);

		dispc_runtime_put();
		dss_runtime_put();
	}
}
EXPORT_SYMBOL(dpi_set_timings);

int dpi_check_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings)
{
	bool is_tft;
	int r;
	int lck_div, pck_div;
	unsigned long fck;
	unsigned long pck;
	struct dispc_clock_info dispc_cinfo;

	if (!dispc_lcd_timings_ok(timings))
		return -EINVAL;

	if (timings->pixel_clock == 0)
		return -EINVAL;

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

	if (dpi_use_dsi_pll(dssdev)) {
		struct dsi_clock_info dsi_cinfo;
		r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
				timings->pixel_clock * 1000,
				&dsi_cinfo, &dispc_cinfo);

		if (r)
			return r;

		fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
	} else {
		struct dss_clock_info dss_cinfo;
		r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
				&dss_cinfo, &dispc_cinfo);

		if (r)
			return r;

		fck = dss_cinfo.fck;
	}

	lck_div = dispc_cinfo.lck_div;
	pck_div = dispc_cinfo.pck_div;

	pck = fck / lck_div / pck_div / 1000;

	timings->pixel_clock = pck;

	return 0;
}
EXPORT_SYMBOL(dpi_check_timings);

int dpi_init_display(struct omap_dss_device *dssdev)
{
	DSSDBG("init_display\n");

	if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
		struct regulator *vdds_dsi;

		vdds_dsi = dss_get_vdds_dsi();

		if (IS_ERR(vdds_dsi)) {
			DSSERR("can't get VDDS_DSI regulator\n");
			return PTR_ERR(vdds_dsi);
		}

		dpi.vdds_dsi_reg = vdds_dsi;
	}

	if (dpi_use_dsi_pll(dssdev)) {
		enum omap_dss_clk_source dispc_fclk_src =
			dssdev->clocks.dispc.dispc_fclk_src;
		dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
	}

	return 0;
}

int dpi_init(void)
{
	return 0;
}

void dpi_exit(void)
{
}
Commit	Line	Data
553c48cf TV	1	/*
	2	* linux/drivers/video/omap2/dss/dpi.c
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	6	*
	7	* Some code and ideas taken from drivers/video/omap/ driver
	8	* by Imre Deak.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along with
	20	* this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#define DSS_SUBSYS_NAME "DPI"
	24
	25	#include <linux/kernel.h>
553c48cf	26	#include <linux/delay.h>
8a2cfea8	27	#include <linux/err.h>
553c48cf	28	#include <linux/errno.h>
8a2cfea8 TV	29	#include <linux/platform_device.h>
8a2cfea8 TV	30	#include <linux/regulator/consumer.h>
553c48cf	31
a0b38cc4	32	#include <video/omapdss.h>
553c48cf TV	33	#include <plat/cpu.h>
	34
	35	#include "dss.h"
	36
	37	static struct {
8a2cfea8	38	struct regulator *vdds_dsi_reg;
a72b64b9	39	struct platform_device *dsidev;
553c48cf TV	40	} dpi;
553c48cf TV	41
a72b64b9 AT	42	static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
	43	{
	44	int dsi_module;
	45
	46	dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
	47
	48	return dsi_get_dsidev_from_id(dsi_module);
	49	}
	50
7636b3b4 AT	51	static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
	52	{
	53	if (dssdev->clocks.dispc.dispc_fclk_src ==
	54	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC \|\|
5a8b572d AT	55	dssdev->clocks.dispc.dispc_fclk_src ==
5a8b572d AT	56	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC \|\|
7636b3b4	57	dssdev->clocks.dispc.channel.lcd_clk_src ==
5a8b572d AT	58	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC \|\|
	59	dssdev->clocks.dispc.channel.lcd_clk_src ==
	60	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
7636b3b4 AT	61	return true;
	62	else
	63	return false;
	64	}
	65
ff1b2cde SS	66	static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
	67	unsigned long pck_req, unsigned long fck, int lck_div,
	68	int *pck_div)
553c48cf TV	69	{
	70	struct dsi_clock_info dsi_cinfo;
	71	struct dispc_clock_info dispc_cinfo;
	72	int r;
	73
a72b64b9 AT	74	r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
a72b64b9 AT	75	&dsi_cinfo, &dispc_cinfo);
553c48cf TV	76	if (r)
	77	return r;
	78
a72b64b9	79	r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
553c48cf TV	80	if (r)
	81	return r;
	82
e8881662	83	dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
553c48cf	84
ff1b2cde	85	r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
553c48cf TV	86	if (r)
	87	return r;
	88
1bb47835	89	*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
553c48cf TV	90	*lck_div = dispc_cinfo.lck_div;
	91	*pck_div = dispc_cinfo.pck_div;
	92
	93	return 0;
	94	}
7636b3b4	95
ff1b2cde SS	96	static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
	97	unsigned long pck_req, unsigned long fck, int lck_div,
	98	int *pck_div)
553c48cf TV	99	{
	100	struct dss_clock_info dss_cinfo;
	101	struct dispc_clock_info dispc_cinfo;
	102	int r;
	103
	104	r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
	105	if (r)
	106	return r;
	107
	108	r = dss_set_clock_div(&dss_cinfo);
	109	if (r)
	110	return r;
	111
ff1b2cde	112	r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
553c48cf TV	113	if (r)
	114	return r;
	115
	116	*fck = dss_cinfo.fck;
	117	*lck_div = dispc_cinfo.lck_div;
	118	*pck_div = dispc_cinfo.pck_div;
	119
	120	return 0;
	121	}
553c48cf TV	122
	123	static int dpi_set_mode(struct omap_dss_device *dssdev)
	124	{
	125	struct omap_video_timings *t = &dssdev->panel.timings;
7636b3b4 AT	126	int lck_div = 0, pck_div = 0;
7636b3b4 AT	127	unsigned long fck = 0;
553c48cf TV	128	unsigned long pck;
	129	bool is_tft;
	130	int r = 0;
	131
ff1b2cde SS	132	dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
ff1b2cde SS	133	dssdev->panel.acbi, dssdev->panel.acb);
553c48cf TV	134
	135	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
	136
7636b3b4 AT	137	if (dpi_use_dsi_pll(dssdev))
	138	r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
	139	&fck, &lck_div, &pck_div);
	140	else
	141	r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
	142	&fck, &lck_div, &pck_div);
553c48cf	143	if (r)
4fbafaf3	144	return r;
553c48cf TV	145
	146	pck = fck / lck_div / pck_div / 1000;
	147
	148	if (pck != t->pixel_clock) {
	149	DSSWARN("Could not find exact pixel clock. "
	150	"Requested %d kHz, got %lu kHz\n",
	151	t->pixel_clock, pck);
	152
	153	t->pixel_clock = pck;
	154	}
	155
64ba4f74	156	dispc_set_lcd_timings(dssdev->manager->id, t);
553c48cf	157
4fbafaf3	158	return 0;
553c48cf TV	159	}
553c48cf TV	160
4fbafaf3	161	static void dpi_basic_init(struct omap_dss_device *dssdev)
553c48cf TV	162	{
	163	bool is_tft;
	164
	165	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
	166
64ba4f74 SS	167	dispc_set_parallel_interface_mode(dssdev->manager->id,
	168	OMAP_DSS_PARALLELMODE_BYPASS);
	169	dispc_set_lcd_display_type(dssdev->manager->id, is_tft ?
	170	OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
	171	dispc_set_tft_data_lines(dssdev->manager->id,
	172	dssdev->phy.dpi.data_lines);
553c48cf TV	173	}
553c48cf TV	174
37ac60e4	175	int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
553c48cf TV	176	{
	177	int r;
	178
05e1d606 TV	179	if (dssdev->manager == NULL) {
	180	DSSERR("failed to enable display: no manager\n");
	181	return -ENODEV;
	182	}
	183
553c48cf TV	184	r = omap_dss_start_device(dssdev);
	185	if (r) {
	186	DSSERR("failed to start device\n");
4fbafaf3	187	goto err_start_dev;
553c48cf TV	188	}
553c48cf TV	189
8a2cfea8 TV	190	if (cpu_is_omap34xx()) {
	191	r = regulator_enable(dpi.vdds_dsi_reg);
	192	if (r)
4fbafaf3	193	goto err_reg_enable;
8a2cfea8 TV	194	}
8a2cfea8 TV	195
4fbafaf3 TV	196	r = dss_runtime_get();
	197	if (r)
	198	goto err_get_dss;
553c48cf	199
4fbafaf3	200	r = dispc_runtime_get();
553c48cf	201	if (r)
4fbafaf3 TV	202	goto err_get_dispc;
	203
	204	dpi_basic_init(dssdev);
553c48cf	205
7636b3b4	206	if (dpi_use_dsi_pll(dssdev)) {
4fbafaf3 TV	207	r = dsi_runtime_get(dpi.dsidev);
	208	if (r)
	209	goto err_get_dsi;
	210
a72b64b9	211	r = dsi_pll_init(dpi.dsidev, 0, 1);
7636b3b4	212	if (r)
4fbafaf3	213	goto err_dsi_pll_init;
7636b3b4 AT	214	}
7636b3b4 AT	215
553c48cf TV	216	r = dpi_set_mode(dssdev);
553c48cf TV	217	if (r)
4fbafaf3	218	goto err_set_mode;
553c48cf TV	219
	220	mdelay(2);
	221
a2faee84	222	dssdev->manager->enable(dssdev->manager);
553c48cf	223
553c48cf TV	224	return 0;
553c48cf TV	225
4fbafaf3	226	err_set_mode:
7636b3b4	227	if (dpi_use_dsi_pll(dssdev))
19077a73	228	dsi_pll_uninit(dpi.dsidev, true);
4fbafaf3 TV	229	err_dsi_pll_init:
	230	if (dpi_use_dsi_pll(dssdev))
	231	dsi_runtime_put(dpi.dsidev);
	232	err_get_dsi:
	233	dispc_runtime_put();
	234	err_get_dispc:
	235	dss_runtime_put();
	236	err_get_dss:
8a2cfea8 TV	237	if (cpu_is_omap34xx())
8a2cfea8 TV	238	regulator_disable(dpi.vdds_dsi_reg);
4fbafaf3	239	err_reg_enable:
553c48cf	240	omap_dss_stop_device(dssdev);
4fbafaf3	241	err_start_dev:
553c48cf TV	242	return r;
553c48cf TV	243	}
37ac60e4	244	EXPORT_SYMBOL(omapdss_dpi_display_enable);
553c48cf	245
37ac60e4	246	void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
553c48cf	247	{
a2faee84	248	dssdev->manager->disable(dssdev->manager);
553c48cf	249
7636b3b4 AT	250	if (dpi_use_dsi_pll(dssdev)) {
7636b3b4 AT	251	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
a72b64b9	252	dsi_pll_uninit(dpi.dsidev, true);
4fbafaf3	253	dsi_runtime_put(dpi.dsidev);
7636b3b4	254	}
553c48cf	255
4fbafaf3 TV	256	dispc_runtime_put();
4fbafaf3 TV	257	dss_runtime_put();
553c48cf	258
8a2cfea8 TV	259	if (cpu_is_omap34xx())
	260	regulator_disable(dpi.vdds_dsi_reg);
	261
553c48cf TV	262	omap_dss_stop_device(dssdev);
553c48cf TV	263	}
37ac60e4	264	EXPORT_SYMBOL(omapdss_dpi_display_disable);
553c48cf	265
69b2048f	266	void dpi_set_timings(struct omap_dss_device *dssdev,
553c48cf TV	267	struct omap_video_timings *timings)
553c48cf TV	268	{
4fbafaf3 TV	269	int r;
4fbafaf3 TV	270
553c48cf TV	271	DSSDBG("dpi_set_timings\n");
	272	dssdev->panel.timings = *timings;
	273	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
4fbafaf3 TV	274	r = dss_runtime_get();
	275	if (r)
	276	return;
	277
	278	r = dispc_runtime_get();
	279	if (r) {
	280	dss_runtime_put();
	281	return;
	282	}
	283
553c48cf	284	dpi_set_mode(dssdev);
2a205f34	285	dispc_go(dssdev->manager->id);
4fbafaf3 TV	286
	287	dispc_runtime_put();
	288	dss_runtime_put();
553c48cf TV	289	}
553c48cf TV	290	}
69b2048f	291	EXPORT_SYMBOL(dpi_set_timings);
553c48cf	292
69b2048f	293	int dpi_check_timings(struct omap_dss_device *dssdev,
553c48cf TV	294	struct omap_video_timings *timings)
	295	{
	296	bool is_tft;
	297	int r;
	298	int lck_div, pck_div;
	299	unsigned long fck;
	300	unsigned long pck;
7636b3b4	301	struct dispc_clock_info dispc_cinfo;
553c48cf TV	302
	303	if (!dispc_lcd_timings_ok(timings))
	304	return -EINVAL;
	305
	306	if (timings->pixel_clock == 0)
	307	return -EINVAL;
	308
	309	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
	310
7636b3b4	311	if (dpi_use_dsi_pll(dssdev)) {
553c48cf	312	struct dsi_clock_info dsi_cinfo;
a72b64b9	313	r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
553c48cf TV	314	timings->pixel_clock * 1000,
	315	&dsi_cinfo, &dispc_cinfo);
	316
	317	if (r)
	318	return r;
	319
1bb47835	320	fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
7636b3b4	321	} else {
553c48cf	322	struct dss_clock_info dss_cinfo;
553c48cf TV	323	r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
	324	&dss_cinfo, &dispc_cinfo);
	325
	326	if (r)
	327	return r;
	328
	329	fck = dss_cinfo.fck;
553c48cf	330	}
7636b3b4 AT	331
	332	lck_div = dispc_cinfo.lck_div;
	333	pck_div = dispc_cinfo.pck_div;
553c48cf TV	334
	335	pck = fck / lck_div / pck_div / 1000;
	336
	337	timings->pixel_clock = pck;
	338
	339	return 0;
	340	}
69b2048f	341	EXPORT_SYMBOL(dpi_check_timings);
553c48cf	342
553c48cf TV	343	int dpi_init_display(struct omap_dss_device *dssdev)
	344	{
	345	DSSDBG("init_display\n");
	346
5f42f2ce TV	347	if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
5f42f2ce TV	348	struct regulator *vdds_dsi;
553c48cf	349
5f42f2ce TV	350	vdds_dsi = dss_get_vdds_dsi();
	351
	352	if (IS_ERR(vdds_dsi)) {
8a2cfea8	353	DSSERR("can't get VDDS_DSI regulator\n");
5f42f2ce	354	return PTR_ERR(vdds_dsi);
8a2cfea8	355	}
5f42f2ce TV	356
5f42f2ce TV	357	dpi.vdds_dsi_reg = vdds_dsi;
8a2cfea8 TV	358	}
8a2cfea8 TV	359
a72b64b9 AT	360	if (dpi_use_dsi_pll(dssdev)) {
	361	enum omap_dss_clk_source dispc_fclk_src =
	362	dssdev->clocks.dispc.dispc_fclk_src;
	363	dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
	364	}
	365
553c48cf TV	366	return 0;
	367	}
	368
277b2881	369	int dpi_init(void)
5f42f2ce TV	370	{
	371	return 0;
	372	}
	373
553c48cf TV	374	void dpi_exit(void)
	375	{
	376	}
	377