OMAPDSS: APPLY: Constify timings argument in dss_mgr_set_timings
[deliverable/linux.git] / drivers / video / omap2 / dss / dpi.c
CommitLineData
553c48cf
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1/*
2 * linux/drivers/video/omap2/dss/dpi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DPI"
24
25#include <linux/kernel.h>
553c48cf 26#include <linux/delay.h>
a8a35931 27#include <linux/export.h>
8a2cfea8 28#include <linux/err.h>
553c48cf 29#include <linux/errno.h>
8a2cfea8
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30#include <linux/platform_device.h>
31#include <linux/regulator/consumer.h>
553c48cf 32
a0b38cc4 33#include <video/omapdss.h>
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34#include <plat/cpu.h>
35
36#include "dss.h"
37
38static struct {
8a2cfea8 39 struct regulator *vdds_dsi_reg;
a72b64b9 40 struct platform_device *dsidev;
5cf9a264
AT
41
42 struct dss_lcd_mgr_config mgr_config;
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43} dpi;
44
a72b64b9
AT
45static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
46{
47 int dsi_module;
48
49 dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
50
51 return dsi_get_dsidev_from_id(dsi_module);
52}
53
7636b3b4
AT
54static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
55{
56 if (dssdev->clocks.dispc.dispc_fclk_src ==
57 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
5a8b572d
AT
58 dssdev->clocks.dispc.dispc_fclk_src ==
59 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
7636b3b4 60 dssdev->clocks.dispc.channel.lcd_clk_src ==
5a8b572d
AT
61 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
62 dssdev->clocks.dispc.channel.lcd_clk_src ==
63 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
7636b3b4
AT
64 return true;
65 else
66 return false;
67}
68
6d523e7b 69static int dpi_set_dsi_clk(struct omap_dss_device *dssdev,
ff1b2cde
SS
70 unsigned long pck_req, unsigned long *fck, int *lck_div,
71 int *pck_div)
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72{
73 struct dsi_clock_info dsi_cinfo;
74 struct dispc_clock_info dispc_cinfo;
75 int r;
76
6d523e7b
AT
77 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, pck_req, &dsi_cinfo,
78 &dispc_cinfo);
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79 if (r)
80 return r;
81
a72b64b9 82 r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
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83 if (r)
84 return r;
85
e8881662 86 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
553c48cf 87
5cf9a264 88 dpi.mgr_config.clock_info = dispc_cinfo;
553c48cf 89
1bb47835 90 *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
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91 *lck_div = dispc_cinfo.lck_div;
92 *pck_div = dispc_cinfo.pck_div;
93
94 return 0;
95}
7636b3b4 96
6d523e7b 97static int dpi_set_dispc_clk(struct omap_dss_device *dssdev,
ff1b2cde
SS
98 unsigned long pck_req, unsigned long *fck, int *lck_div,
99 int *pck_div)
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100{
101 struct dss_clock_info dss_cinfo;
102 struct dispc_clock_info dispc_cinfo;
103 int r;
104
6d523e7b 105 r = dss_calc_clock_div(pck_req, &dss_cinfo, &dispc_cinfo);
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106 if (r)
107 return r;
108
109 r = dss_set_clock_div(&dss_cinfo);
110 if (r)
111 return r;
112
5cf9a264 113 dpi.mgr_config.clock_info = dispc_cinfo;
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114
115 *fck = dss_cinfo.fck;
116 *lck_div = dispc_cinfo.lck_div;
117 *pck_div = dispc_cinfo.pck_div;
118
119 return 0;
120}
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121
122static int dpi_set_mode(struct omap_dss_device *dssdev)
123{
124 struct omap_video_timings *t = &dssdev->panel.timings;
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125 int lck_div = 0, pck_div = 0;
126 unsigned long fck = 0;
553c48cf 127 unsigned long pck;
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128 int r = 0;
129
7636b3b4 130 if (dpi_use_dsi_pll(dssdev))
6d523e7b
AT
131 r = dpi_set_dsi_clk(dssdev, t->pixel_clock * 1000, &fck,
132 &lck_div, &pck_div);
7636b3b4 133 else
6d523e7b
AT
134 r = dpi_set_dispc_clk(dssdev, t->pixel_clock * 1000, &fck,
135 &lck_div, &pck_div);
553c48cf 136 if (r)
4fbafaf3 137 return r;
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138
139 pck = fck / lck_div / pck_div / 1000;
140
141 if (pck != t->pixel_clock) {
142 DSSWARN("Could not find exact pixel clock. "
143 "Requested %d kHz, got %lu kHz\n",
144 t->pixel_clock, pck);
145
146 t->pixel_clock = pck;
147 }
148
41721163 149 dss_mgr_set_timings(dssdev->manager, t);
553c48cf 150
4fbafaf3 151 return 0;
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152}
153
5cf9a264 154static void dpi_config_lcd_manager(struct omap_dss_device *dssdev)
553c48cf 155{
5cf9a264 156 dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
569969d6 157
5cf9a264
AT
158 dpi.mgr_config.stallmode = false;
159 dpi.mgr_config.fifohandcheck = false;
160
161 dpi.mgr_config.video_port_width = dssdev->phy.dpi.data_lines;
162
163 dpi.mgr_config.lcden_sig_polarity = 0;
164
f476ae9d 165 dss_mgr_set_lcd_config(dssdev->manager, &dpi.mgr_config);
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166}
167
37ac60e4 168int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
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169{
170 int r;
171
40410715
RK
172 if (cpu_is_omap34xx() && !dpi.vdds_dsi_reg) {
173 DSSERR("no VDSS_DSI regulator\n");
174 return -ENODEV;
175 }
176
05e1d606
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177 if (dssdev->manager == NULL) {
178 DSSERR("failed to enable display: no manager\n");
179 return -ENODEV;
180 }
181
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182 r = omap_dss_start_device(dssdev);
183 if (r) {
184 DSSERR("failed to start device\n");
4fbafaf3 185 goto err_start_dev;
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186 }
187
8a2cfea8
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188 if (cpu_is_omap34xx()) {
189 r = regulator_enable(dpi.vdds_dsi_reg);
190 if (r)
4fbafaf3 191 goto err_reg_enable;
8a2cfea8
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192 }
193
4fbafaf3 194 r = dispc_runtime_get();
553c48cf 195 if (r)
4fbafaf3
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196 goto err_get_dispc;
197
7636b3b4 198 if (dpi_use_dsi_pll(dssdev)) {
4fbafaf3
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199 r = dsi_runtime_get(dpi.dsidev);
200 if (r)
201 goto err_get_dsi;
202
a72b64b9 203 r = dsi_pll_init(dpi.dsidev, 0, 1);
7636b3b4 204 if (r)
4fbafaf3 205 goto err_dsi_pll_init;
7636b3b4
AT
206 }
207
553c48cf
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208 r = dpi_set_mode(dssdev);
209 if (r)
4fbafaf3 210 goto err_set_mode;
553c48cf 211
5cf9a264
AT
212 dpi_config_lcd_manager(dssdev);
213
553c48cf
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214 mdelay(2);
215
33ca237f
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216 r = dss_mgr_enable(dssdev->manager);
217 if (r)
218 goto err_mgr_enable;
553c48cf 219
553c48cf
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220 return 0;
221
33ca237f 222err_mgr_enable:
4fbafaf3 223err_set_mode:
7636b3b4 224 if (dpi_use_dsi_pll(dssdev))
19077a73 225 dsi_pll_uninit(dpi.dsidev, true);
4fbafaf3
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226err_dsi_pll_init:
227 if (dpi_use_dsi_pll(dssdev))
228 dsi_runtime_put(dpi.dsidev);
229err_get_dsi:
230 dispc_runtime_put();
231err_get_dispc:
8a2cfea8
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232 if (cpu_is_omap34xx())
233 regulator_disable(dpi.vdds_dsi_reg);
4fbafaf3 234err_reg_enable:
553c48cf 235 omap_dss_stop_device(dssdev);
4fbafaf3 236err_start_dev:
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237 return r;
238}
37ac60e4 239EXPORT_SYMBOL(omapdss_dpi_display_enable);
553c48cf 240
37ac60e4 241void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
553c48cf 242{
7797c6da 243 dss_mgr_disable(dssdev->manager);
553c48cf 244
7636b3b4
AT
245 if (dpi_use_dsi_pll(dssdev)) {
246 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
a72b64b9 247 dsi_pll_uninit(dpi.dsidev, true);
4fbafaf3 248 dsi_runtime_put(dpi.dsidev);
7636b3b4 249 }
553c48cf 250
4fbafaf3 251 dispc_runtime_put();
553c48cf 252
8a2cfea8
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253 if (cpu_is_omap34xx())
254 regulator_disable(dpi.vdds_dsi_reg);
255
553c48cf
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256 omap_dss_stop_device(dssdev);
257}
37ac60e4 258EXPORT_SYMBOL(omapdss_dpi_display_disable);
553c48cf 259
69b2048f 260void dpi_set_timings(struct omap_dss_device *dssdev,
553c48cf
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261 struct omap_video_timings *timings)
262{
4fbafaf3
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263 int r;
264
553c48cf
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265 DSSDBG("dpi_set_timings\n");
266 dssdev->panel.timings = *timings;
267 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
4fbafaf3 268 r = dispc_runtime_get();
852f0838 269 if (r)
4fbafaf3 270 return;
4fbafaf3 271
553c48cf 272 dpi_set_mode(dssdev);
4fbafaf3
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273
274 dispc_runtime_put();
fcc36619
AT
275 } else {
276 dss_mgr_set_timings(dssdev->manager, timings);
553c48cf
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277 }
278}
69b2048f 279EXPORT_SYMBOL(dpi_set_timings);
553c48cf 280
69b2048f 281int dpi_check_timings(struct omap_dss_device *dssdev,
553c48cf
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282 struct omap_video_timings *timings)
283{
553c48cf
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284 int r;
285 int lck_div, pck_div;
286 unsigned long fck;
287 unsigned long pck;
7636b3b4 288 struct dispc_clock_info dispc_cinfo;
553c48cf 289
b917fa39 290 if (dss_mgr_check_timings(dssdev->manager, timings))
553c48cf
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291 return -EINVAL;
292
293 if (timings->pixel_clock == 0)
294 return -EINVAL;
295
7636b3b4 296 if (dpi_use_dsi_pll(dssdev)) {
553c48cf 297 struct dsi_clock_info dsi_cinfo;
6d523e7b 298 r = dsi_pll_calc_clock_div_pck(dpi.dsidev,
553c48cf
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299 timings->pixel_clock * 1000,
300 &dsi_cinfo, &dispc_cinfo);
301
302 if (r)
303 return r;
304
1bb47835 305 fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
7636b3b4 306 } else {
553c48cf 307 struct dss_clock_info dss_cinfo;
6d523e7b 308 r = dss_calc_clock_div(timings->pixel_clock * 1000,
553c48cf
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309 &dss_cinfo, &dispc_cinfo);
310
311 if (r)
312 return r;
313
314 fck = dss_cinfo.fck;
553c48cf 315 }
7636b3b4
AT
316
317 lck_div = dispc_cinfo.lck_div;
318 pck_div = dispc_cinfo.pck_div;
553c48cf
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319
320 pck = fck / lck_div / pck_div / 1000;
321
322 timings->pixel_clock = pck;
323
324 return 0;
325}
69b2048f 326EXPORT_SYMBOL(dpi_check_timings);
553c48cf 327
9d8232a7 328static int __init dpi_init_display(struct omap_dss_device *dssdev)
553c48cf
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329{
330 DSSDBG("init_display\n");
331
5f42f2ce
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332 if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
333 struct regulator *vdds_dsi;
553c48cf 334
5f42f2ce
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335 vdds_dsi = dss_get_vdds_dsi();
336
337 if (IS_ERR(vdds_dsi)) {
8a2cfea8 338 DSSERR("can't get VDDS_DSI regulator\n");
5f42f2ce 339 return PTR_ERR(vdds_dsi);
8a2cfea8 340 }
5f42f2ce
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341
342 dpi.vdds_dsi_reg = vdds_dsi;
8a2cfea8
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343 }
344
a72b64b9
AT
345 if (dpi_use_dsi_pll(dssdev)) {
346 enum omap_dss_clk_source dispc_fclk_src =
347 dssdev->clocks.dispc.dispc_fclk_src;
348 dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
349 }
350
553c48cf
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351 return 0;
352}
353
38f3daf6 354static void __init dpi_probe_pdata(struct platform_device *pdev)
5f42f2ce 355{
35deca3d
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356 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
357 int i, r;
358
359 for (i = 0; i < pdata->num_devices; ++i) {
360 struct omap_dss_device *dssdev = pdata->devices[i];
361
362 if (dssdev->type != OMAP_DISPLAY_TYPE_DPI)
363 continue;
364
9d8232a7
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365 r = dpi_init_display(dssdev);
366 if (r) {
367 DSSERR("device %s init failed: %d\n", dssdev->name, r);
368 continue;
369 }
370
35deca3d
TV
371 r = omap_dss_register_device(dssdev, &pdev->dev, i);
372 if (r)
373 DSSERR("device %s register failed: %d\n",
374 dssdev->name, r);
375 }
38f3daf6
TV
376}
377
378static int __init omap_dpi_probe(struct platform_device *pdev)
379{
380 dpi_probe_pdata(pdev);
35deca3d 381
5f42f2ce
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382 return 0;
383}
384
6e7e8f06 385static int __exit omap_dpi_remove(struct platform_device *pdev)
553c48cf 386{
35deca3d
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387 omap_dss_unregister_child_devices(&pdev->dev);
388
a57dd4fe 389 return 0;
553c48cf
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390}
391
a57dd4fe 392static struct platform_driver omap_dpi_driver = {
6e7e8f06 393 .remove = __exit_p(omap_dpi_remove),
a57dd4fe
TV
394 .driver = {
395 .name = "omapdss_dpi",
396 .owner = THIS_MODULE,
397 },
398};
399
6e7e8f06 400int __init dpi_init_platform_driver(void)
a57dd4fe 401{
61055d4b 402 return platform_driver_probe(&omap_dpi_driver, omap_dpi_probe);
a57dd4fe
TV
403}
404
6e7e8f06 405void __exit dpi_uninit_platform_driver(void)
a57dd4fe
TV
406{
407 platform_driver_unregister(&omap_dpi_driver);
408}
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