[deliverable/linux.git] / drivers / video / omap2 / dss / dpi.c

/*
 * linux/drivers/video/omap2/dss/dpi.c
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "DPI"

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#include <plat/display.h>
#include <plat/cpu.h>

#include "dss.h"

static struct {
	struct regulator *vdds_dsi_reg;
} dpi;

#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
		unsigned long *fck, int *lck_div, int *pck_div)
{
	struct dsi_clock_info dsi_cinfo;
	struct dispc_clock_info dispc_cinfo;
	int r;

	r = dsi_pll_calc_clock_div_pck(is_tft, pck_req, &dsi_cinfo,
			&dispc_cinfo);
	if (r)
		return r;

	r = dsi_pll_set_clock_div(&dsi_cinfo);
	if (r)
		return r;

	dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);

	r = dispc_set_clock_div(&dispc_cinfo);
	if (r)
		return r;

	*fck = dsi_cinfo.dsi1_pll_fclk;
	*lck_div = dispc_cinfo.lck_div;
	*pck_div = dispc_cinfo.pck_div;

	return 0;
}
#else
static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
		unsigned long *fck, int *lck_div, int *pck_div)
{
	struct dss_clock_info dss_cinfo;
	struct dispc_clock_info dispc_cinfo;
	int r;

	r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
	if (r)
		return r;

	r = dss_set_clock_div(&dss_cinfo);
	if (r)
		return r;

	r = dispc_set_clock_div(&dispc_cinfo);
	if (r)
		return r;

	*fck = dss_cinfo.fck;
	*lck_div = dispc_cinfo.lck_div;
	*pck_div = dispc_cinfo.pck_div;

	return 0;
}
#endif

static int dpi_set_mode(struct omap_dss_device *dssdev)
{
	struct omap_video_timings *t = &dssdev->panel.timings;
	int lck_div, pck_div;
	unsigned long fck;
	unsigned long pck;
	bool is_tft;
	int r = 0;

	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);

	dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
			dssdev->panel.acb);

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	r = dpi_set_dsi_clk(is_tft, t->pixel_clock * 1000,
			&fck, &lck_div, &pck_div);
#else
	r = dpi_set_dispc_clk(is_tft, t->pixel_clock * 1000,
			&fck, &lck_div, &pck_div);
#endif
	if (r)
		goto err0;

	pck = fck / lck_div / pck_div / 1000;

	if (pck != t->pixel_clock) {
		DSSWARN("Could not find exact pixel clock. "
				"Requested %d kHz, got %lu kHz\n",
				t->pixel_clock, pck);

		t->pixel_clock = pck;
	}

	dispc_set_lcd_timings(t);

err0:
	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
	return r;
}

static int dpi_basic_init(struct omap_dss_device *dssdev)
{
	bool is_tft;

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
	dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
			OMAP_DSS_LCD_DISPLAY_STN);
	dispc_set_tft_data_lines(dssdev->phy.dpi.data_lines);

	return 0;
}

int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
{
	int r;

	r = omap_dss_start_device(dssdev);
	if (r) {
		DSSERR("failed to start device\n");
		goto err0;
	}

	if (cpu_is_omap34xx()) {
		r = regulator_enable(dpi.vdds_dsi_reg);
		if (r)
			goto err1;
	}

	dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);

	r = dpi_basic_init(dssdev);
	if (r)
		goto err2;

#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	dss_clk_enable(DSS_CLK_FCK2);
	r = dsi_pll_init(dssdev, 0, 1);
	if (r)
		goto err3;
#endif
	r = dpi_set_mode(dssdev);
	if (r)
		goto err4;

	mdelay(2);

	dssdev->manager->enable(dssdev->manager);

	return 0;

err4:
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	dsi_pll_uninit();
err3:
	dss_clk_disable(DSS_CLK_FCK2);
#endif
err2:
	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
	if (cpu_is_omap34xx())
		regulator_disable(dpi.vdds_dsi_reg);
err1:
	omap_dss_stop_device(dssdev);
err0:
	return r;
}
EXPORT_SYMBOL(omapdss_dpi_display_enable);

void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
{
	dssdev->manager->disable(dssdev->manager);

#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
	dsi_pll_uninit();
	dss_clk_disable(DSS_CLK_FCK2);
#endif

	dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);

	if (cpu_is_omap34xx())
		regulator_disable(dpi.vdds_dsi_reg);

	omap_dss_stop_device(dssdev);
}
EXPORT_SYMBOL(omapdss_dpi_display_disable);

static void dpi_set_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings)
{
	DSSDBG("dpi_set_timings\n");
	dssdev->panel.timings = *timings;
	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
		dpi_set_mode(dssdev);
		dispc_go(OMAP_DSS_CHANNEL_LCD);
	}
}

static int dpi_check_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings)
{
	bool is_tft;
	int r;
	int lck_div, pck_div;
	unsigned long fck;
	unsigned long pck;

	if (!dispc_lcd_timings_ok(timings))
		return -EINVAL;

	if (timings->pixel_clock == 0)
		return -EINVAL;

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	{
		struct dsi_clock_info dsi_cinfo;
		struct dispc_clock_info dispc_cinfo;
		r = dsi_pll_calc_clock_div_pck(is_tft,
				timings->pixel_clock * 1000,
				&dsi_cinfo, &dispc_cinfo);

		if (r)
			return r;

		fck = dsi_cinfo.dsi1_pll_fclk;
		lck_div = dispc_cinfo.lck_div;
		pck_div = dispc_cinfo.pck_div;
	}
#else
	{
		struct dss_clock_info dss_cinfo;
		struct dispc_clock_info dispc_cinfo;
		r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
				&dss_cinfo, &dispc_cinfo);

		if (r)
			return r;

		fck = dss_cinfo.fck;
		lck_div = dispc_cinfo.lck_div;
		pck_div = dispc_cinfo.pck_div;
	}
#endif

	pck = fck / lck_div / pck_div / 1000;

	timings->pixel_clock = pck;

	return 0;
}

static void dpi_get_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings)
{
	*timings = dssdev->panel.timings;
}

int dpi_init_display(struct omap_dss_device *dssdev)
{
	DSSDBG("init_display\n");

	dssdev->set_timings = dpi_set_timings;
	dssdev->check_timings = dpi_check_timings;
	dssdev->get_timings = dpi_get_timings;

	return 0;
}

int dpi_init(struct platform_device *pdev)
{
	if (cpu_is_omap34xx()) {
		dpi.vdds_dsi_reg = dss_get_vdds_dsi();
		if (IS_ERR(dpi.vdds_dsi_reg)) {
			DSSERR("can't get VDDS_DSI regulator\n");
			return PTR_ERR(dpi.vdds_dsi_reg);
		}
	}

	return 0;
}

void dpi_exit(void)
{
}
Commit	Line	Data
553c48cf TV	1	/*
	2	* linux/drivers/video/omap2/dss/dpi.c
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	6	*
	7	* Some code and ideas taken from drivers/video/omap/ driver
	8	* by Imre Deak.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along with
	20	* this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#define DSS_SUBSYS_NAME "DPI"
	24
	25	#include <linux/kernel.h>
	26	#include <linux/clk.h>
	27	#include <linux/delay.h>
8a2cfea8	28	#include <linux/err.h>
553c48cf	29	#include <linux/errno.h>
8a2cfea8 TV	30	#include <linux/platform_device.h>
8a2cfea8 TV	31	#include <linux/regulator/consumer.h>
553c48cf TV	32
	33	#include <plat/display.h>
	34	#include <plat/cpu.h>
	35
	36	#include "dss.h"
	37
	38	static struct {
8a2cfea8	39	struct regulator *vdds_dsi_reg;
553c48cf TV	40	} dpi;
	41
	42	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	43	static int dpi_set_dsi_clk(bool is_tft, unsigned long pck_req,
	44	unsigned long fck, int lck_div, int *pck_div)
	45	{
	46	struct dsi_clock_info dsi_cinfo;
	47	struct dispc_clock_info dispc_cinfo;
	48	int r;
	49
	50	r = dsi_pll_calc_clock_div_pck(is_tft, pck_req, &dsi_cinfo,
	51	&dispc_cinfo);
	52	if (r)
	53	return r;
	54
	55	r = dsi_pll_set_clock_div(&dsi_cinfo);
	56	if (r)
	57	return r;
	58
2f18c4d8	59	dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
553c48cf TV	60
	61	r = dispc_set_clock_div(&dispc_cinfo);
	62	if (r)
	63	return r;
	64
	65	*fck = dsi_cinfo.dsi1_pll_fclk;
	66	*lck_div = dispc_cinfo.lck_div;
	67	*pck_div = dispc_cinfo.pck_div;
	68
	69	return 0;
	70	}
	71	#else
	72	static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
	73	unsigned long fck, int lck_div, int *pck_div)
	74	{
	75	struct dss_clock_info dss_cinfo;
	76	struct dispc_clock_info dispc_cinfo;
	77	int r;
	78
	79	r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
	80	if (r)
	81	return r;
	82
	83	r = dss_set_clock_div(&dss_cinfo);
	84	if (r)
	85	return r;
	86
	87	r = dispc_set_clock_div(&dispc_cinfo);
	88	if (r)
	89	return r;
	90
	91	*fck = dss_cinfo.fck;
	92	*lck_div = dispc_cinfo.lck_div;
	93	*pck_div = dispc_cinfo.pck_div;
	94
	95	return 0;
	96	}
	97	#endif
	98
	99	static int dpi_set_mode(struct omap_dss_device *dssdev)
	100	{
	101	struct omap_video_timings *t = &dssdev->panel.timings;
	102	int lck_div, pck_div;
	103	unsigned long fck;
	104	unsigned long pck;
	105	bool is_tft;
	106	int r = 0;
	107
	108	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);
	109
	110	dispc_set_pol_freq(dssdev->panel.config, dssdev->panel.acbi,
	111	dssdev->panel.acb);
	112
	113	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
	114
	115	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	116	r = dpi_set_dsi_clk(is_tft, t->pixel_clock * 1000,
	117	&fck, &lck_div, &pck_div);
	118	#else
	119	r = dpi_set_dispc_clk(is_tft, t->pixel_clock * 1000,
	120	&fck, &lck_div, &pck_div);
	121	#endif
	122	if (r)
	123	goto err0;
124
125	pck = fck / lck_div / pck_div / 1000;
126
127	if (pck != t->pixel_clock) {
128	DSSWARN("Could not find exact pixel clock. "
129	"Requested %d kHz, got %lu kHz\n",
130	t->pixel_clock, pck);
131
132	t->pixel_clock = pck;
133	}
134
135	dispc_set_lcd_timings(t);
136
137	err0:
138	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);
139	return r;
140	}
141
142	static int dpi_basic_init(struct omap_dss_device *dssdev)
143	{
144	bool is_tft;
145
146	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
147
148	dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_BYPASS);
149	dispc_set_lcd_display_type(is_tft ? OMAP_DSS_LCD_DISPLAY_TFT :
150	OMAP_DSS_LCD_DISPLAY_STN);
151	dispc_set_tft_data_lines(dssdev->phy.dpi.data_lines);
152
153	return 0;
154	}
155
37ac60e4	156	int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
553c48cf TV	157	{
	158	int r;
	159
	160	r = omap_dss_start_device(dssdev);
	161	if (r) {
	162	DSSERR("failed to start device\n");
	163	goto err0;
	164	}
	165
8a2cfea8 TV	166	if (cpu_is_omap34xx()) {
	167	r = regulator_enable(dpi.vdds_dsi_reg);
	168	if (r)
37ac60e4	169	goto err1;
8a2cfea8 TV	170	}
8a2cfea8 TV	171
553c48cf TV	172	dss_clk_enable(DSS_CLK_ICK \| DSS_CLK_FCK1);
	173
	174	r = dpi_basic_init(dssdev);
	175	if (r)
37ac60e4	176	goto err2;
553c48cf TV	177
	178	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	179	dss_clk_enable(DSS_CLK_FCK2);
	180	r = dsi_pll_init(dssdev, 0, 1);
	181	if (r)
37ac60e4	182	goto err3;
553c48cf TV	183	#endif
	184	r = dpi_set_mode(dssdev);
	185	if (r)
37ac60e4	186	goto err4;
553c48cf TV	187
	188	mdelay(2);
	189
a2faee84	190	dssdev->manager->enable(dssdev->manager);
553c48cf	191
553c48cf TV	192	return 0;
553c48cf TV	193
37ac60e4	194	err4:
553c48cf TV	195	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
553c48cf TV	196	dsi_pll_uninit();
37ac60e4	197	err3:
553c48cf TV	198	dss_clk_disable(DSS_CLK_FCK2);
553c48cf TV	199	#endif
8a2cfea8	200	err2:
37ac60e4	201	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);
8a2cfea8 TV	202	if (cpu_is_omap34xx())
8a2cfea8 TV	203	regulator_disable(dpi.vdds_dsi_reg);
553c48cf TV	204	err1:
	205	omap_dss_stop_device(dssdev);
	206	err0:
	207	return r;
	208	}
37ac60e4	209	EXPORT_SYMBOL(omapdss_dpi_display_enable);
553c48cf	210
37ac60e4	211	void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
553c48cf	212	{
a2faee84	213	dssdev->manager->disable(dssdev->manager);
553c48cf TV	214
553c48cf TV	215	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
2f18c4d8	216	dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
553c48cf TV	217	dsi_pll_uninit();
	218	dss_clk_disable(DSS_CLK_FCK2);
	219	#endif
	220
	221	dss_clk_disable(DSS_CLK_ICK \| DSS_CLK_FCK1);
	222
8a2cfea8 TV	223	if (cpu_is_omap34xx())
	224	regulator_disable(dpi.vdds_dsi_reg);
	225
553c48cf TV	226	omap_dss_stop_device(dssdev);
553c48cf TV	227	}
37ac60e4	228	EXPORT_SYMBOL(omapdss_dpi_display_disable);
553c48cf TV	229
	230	static void dpi_set_timings(struct omap_dss_device *dssdev,
	231	struct omap_video_timings *timings)
	232	{
	233	DSSDBG("dpi_set_timings\n");
	234	dssdev->panel.timings = *timings;
	235	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
	236	dpi_set_mode(dssdev);
	237	dispc_go(OMAP_DSS_CHANNEL_LCD);
	238	}
	239	}
	240
	241	static int dpi_check_timings(struct omap_dss_device *dssdev,
	242	struct omap_video_timings *timings)
	243	{
	244	bool is_tft;
	245	int r;
	246	int lck_div, pck_div;
	247	unsigned long fck;
	248	unsigned long pck;
	249
	250	if (!dispc_lcd_timings_ok(timings))
	251	return -EINVAL;
	252
	253	if (timings->pixel_clock == 0)
	254	return -EINVAL;
	255
	256	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
	257
	258	#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
	259	{
	260	struct dsi_clock_info dsi_cinfo;
	261	struct dispc_clock_info dispc_cinfo;
	262	r = dsi_pll_calc_clock_div_pck(is_tft,
	263	timings->pixel_clock * 1000,
	264	&dsi_cinfo, &dispc_cinfo);
	265
	266	if (r)
	267	return r;
	268
	269	fck = dsi_cinfo.dsi1_pll_fclk;
	270	lck_div = dispc_cinfo.lck_div;
	271	pck_div = dispc_cinfo.pck_div;
	272	}
	273	#else
	274	{
	275	struct dss_clock_info dss_cinfo;
	276	struct dispc_clock_info dispc_cinfo;
	277	r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
	278	&dss_cinfo, &dispc_cinfo);
	279
	280	if (r)
	281	return r;
	282
	283	fck = dss_cinfo.fck;
	284	lck_div = dispc_cinfo.lck_div;
	285	pck_div = dispc_cinfo.pck_div;
	286	}
	287	#endif
	288
	289	pck = fck / lck_div / pck_div / 1000;
	290
	291	timings->pixel_clock = pck;
	292
293	return 0;
294	}
295
296	static void dpi_get_timings(struct omap_dss_device *dssdev,
297	struct omap_video_timings *timings)
298	{
299	*timings = dssdev->panel.timings;
300	}
301
553c48cf TV	302	int dpi_init_display(struct omap_dss_device *dssdev)
	303	{
	304	DSSDBG("init_display\n");
	305
553c48cf TV	306	dssdev->set_timings = dpi_set_timings;
	307	dssdev->check_timings = dpi_check_timings;
	308	dssdev->get_timings = dpi_get_timings;
553c48cf TV	309
	310	return 0;
	311	}
	312
8a2cfea8	313	int dpi_init(struct platform_device *pdev)
553c48cf	314	{
8a2cfea8 TV	315	if (cpu_is_omap34xx()) {
	316	dpi.vdds_dsi_reg = dss_get_vdds_dsi();
	317	if (IS_ERR(dpi.vdds_dsi_reg)) {
	318	DSSERR("can't get VDDS_DSI regulator\n");
	319	return PTR_ERR(dpi.vdds_dsi_reg);
	320	}
	321	}
	322
553c48cf TV	323	return 0;
	324	}
	325
	326	void dpi_exit(void)
	327	{
	328	}
	329