Commit | Line | Data |
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553c48cf TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dpi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DPI" | |
24 | ||
25 | #include <linux/kernel.h> | |
553c48cf | 26 | #include <linux/delay.h> |
a8a35931 | 27 | #include <linux/export.h> |
8a2cfea8 | 28 | #include <linux/err.h> |
553c48cf | 29 | #include <linux/errno.h> |
8a2cfea8 TV |
30 | #include <linux/platform_device.h> |
31 | #include <linux/regulator/consumer.h> | |
13b1ba7d | 32 | #include <linux/string.h> |
553c48cf | 33 | |
a0b38cc4 | 34 | #include <video/omapdss.h> |
553c48cf TV |
35 | |
36 | #include "dss.h" | |
195e672a | 37 | #include "dss_features.h" |
553c48cf TV |
38 | |
39 | static struct { | |
00df43b8 TV |
40 | struct platform_device *pdev; |
41 | ||
8a2cfea8 | 42 | struct regulator *vdds_dsi_reg; |
a72b64b9 | 43 | struct platform_device *dsidev; |
5cf9a264 | 44 | |
c8a5e4e8 AT |
45 | struct mutex lock; |
46 | ||
c499144c | 47 | struct omap_video_timings timings; |
5cf9a264 | 48 | struct dss_lcd_mgr_config mgr_config; |
c6b393d4 | 49 | int data_lines; |
81b87f51 | 50 | |
1f68d9c4 | 51 | struct omap_dss_device output; |
553c48cf TV |
52 | } dpi; |
53 | ||
0e8276ef | 54 | static struct platform_device *dpi_get_dsidev(enum omap_channel channel) |
a72b64b9 | 55 | { |
bd0f5cc3 TV |
56 | /* |
57 | * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL | |
58 | * would also be used for DISPC fclk. Meaning, when the DPI output is | |
59 | * disabled, DISPC clock will be disabled, and TV out will stop. | |
60 | */ | |
61 | switch (omapdss_get_version()) { | |
62 | case OMAPDSS_VER_OMAP24xx: | |
63 | case OMAPDSS_VER_OMAP34xx_ES1: | |
64 | case OMAPDSS_VER_OMAP34xx_ES3: | |
65 | case OMAPDSS_VER_OMAP3630: | |
66 | case OMAPDSS_VER_AM35xx: | |
67 | return NULL; | |
bd0f5cc3 | 68 | |
f8ad984c TV |
69 | case OMAPDSS_VER_OMAP4430_ES1: |
70 | case OMAPDSS_VER_OMAP4430_ES2: | |
71 | case OMAPDSS_VER_OMAP4: | |
72 | switch (channel) { | |
73 | case OMAP_DSS_CHANNEL_LCD: | |
74 | return dsi_get_dsidev_from_id(0); | |
75 | case OMAP_DSS_CHANNEL_LCD2: | |
76 | return dsi_get_dsidev_from_id(1); | |
77 | default: | |
78 | return NULL; | |
79 | } | |
80 | ||
81 | case OMAPDSS_VER_OMAP5: | |
82 | switch (channel) { | |
83 | case OMAP_DSS_CHANNEL_LCD: | |
84 | return dsi_get_dsidev_from_id(0); | |
85 | case OMAP_DSS_CHANNEL_LCD3: | |
86 | return dsi_get_dsidev_from_id(1); | |
87 | default: | |
88 | return NULL; | |
89 | } | |
90 | ||
0e8276ef TV |
91 | default: |
92 | return NULL; | |
93 | } | |
a72b64b9 AT |
94 | } |
95 | ||
0e8276ef | 96 | static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel) |
7636b3b4 | 97 | { |
0e8276ef TV |
98 | switch (channel) { |
99 | case OMAP_DSS_CHANNEL_LCD: | |
100 | return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC; | |
101 | case OMAP_DSS_CHANNEL_LCD2: | |
102 | return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC; | |
103 | default: | |
104 | /* this shouldn't happen */ | |
105 | WARN_ON(1); | |
106 | return OMAP_DSS_CLK_SRC_FCK; | |
107 | } | |
7636b3b4 AT |
108 | } |
109 | ||
100c8262 TV |
110 | struct dpi_clk_calc_ctx { |
111 | struct platform_device *dsidev; | |
112 | ||
113 | /* inputs */ | |
114 | ||
115 | unsigned long pck_min, pck_max; | |
116 | ||
117 | /* outputs */ | |
118 | ||
119 | struct dsi_clock_info dsi_cinfo; | |
120 | struct dss_clock_info dss_cinfo; | |
121 | struct dispc_clock_info dispc_cinfo; | |
122 | }; | |
123 | ||
124 | static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
125 | unsigned long pck, void *data) | |
126 | { | |
127 | struct dpi_clk_calc_ctx *ctx = data; | |
128 | ||
129 | /* | |
130 | * Odd dividers give us uneven duty cycle, causing problem when level | |
131 | * shifted. So skip all odd dividers when the pixel clock is on the | |
132 | * higher side. | |
133 | */ | |
72e5512a | 134 | if (ctx->pck_min >= 100000000) { |
100c8262 TV |
135 | if (lckd > 1 && lckd % 2 != 0) |
136 | return false; | |
137 | ||
138 | if (pckd > 1 && pckd % 2 != 0) | |
139 | return false; | |
140 | } | |
141 | ||
142 | ctx->dispc_cinfo.lck_div = lckd; | |
143 | ctx->dispc_cinfo.pck_div = pckd; | |
144 | ctx->dispc_cinfo.lck = lck; | |
145 | ctx->dispc_cinfo.pck = pck; | |
146 | ||
147 | return true; | |
148 | } | |
149 | ||
150 | ||
151 | static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc, | |
152 | void *data) | |
153 | { | |
154 | struct dpi_clk_calc_ctx *ctx = data; | |
155 | ||
156 | /* | |
157 | * Odd dividers give us uneven duty cycle, causing problem when level | |
158 | * shifted. So skip all odd dividers when the pixel clock is on the | |
159 | * higher side. | |
160 | */ | |
72e5512a | 161 | if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000) |
100c8262 TV |
162 | return false; |
163 | ||
164 | ctx->dsi_cinfo.regm_dispc = regm_dispc; | |
165 | ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc; | |
166 | ||
167 | return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max, | |
168 | dpi_calc_dispc_cb, ctx); | |
169 | } | |
170 | ||
171 | ||
172 | static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint, | |
173 | unsigned long pll, | |
174 | void *data) | |
175 | { | |
176 | struct dpi_clk_calc_ctx *ctx = data; | |
177 | ||
178 | ctx->dsi_cinfo.regn = regn; | |
179 | ctx->dsi_cinfo.regm = regm; | |
180 | ctx->dsi_cinfo.fint = fint; | |
181 | ctx->dsi_cinfo.clkin4ddr = pll; | |
182 | ||
183 | return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min, | |
184 | dpi_calc_hsdiv_cb, ctx); | |
185 | } | |
186 | ||
187 | static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data) | |
188 | { | |
189 | struct dpi_clk_calc_ctx *ctx = data; | |
190 | ||
191 | ctx->dss_cinfo.fck = fck; | |
192 | ctx->dss_cinfo.fck_div = fckd; | |
193 | ||
194 | return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, | |
195 | dpi_calc_dispc_cb, ctx); | |
196 | } | |
197 | ||
198 | static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx) | |
199 | { | |
200 | unsigned long clkin; | |
201 | unsigned long pll_min, pll_max; | |
202 | ||
203 | clkin = dsi_get_pll_clkin(dpi.dsidev); | |
204 | ||
205 | memset(ctx, 0, sizeof(*ctx)); | |
206 | ctx->dsidev = dpi.dsidev; | |
207 | ctx->pck_min = pck - 1000; | |
208 | ctx->pck_max = pck + 1000; | |
209 | ctx->dsi_cinfo.clkin = clkin; | |
210 | ||
211 | pll_min = 0; | |
212 | pll_max = 0; | |
213 | ||
214 | return dsi_pll_calc(dpi.dsidev, clkin, | |
215 | pll_min, pll_max, | |
216 | dpi_calc_pll_cb, ctx); | |
217 | } | |
218 | ||
219 | static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx) | |
220 | { | |
221 | int i; | |
222 | ||
223 | /* | |
224 | * DSS fck gives us very few possibilities, so finding a good pixel | |
225 | * clock may not be possible. We try multiple times to find the clock, | |
226 | * each time widening the pixel clock range we look for, up to | |
2c6360fb | 227 | * +/- ~15MHz. |
100c8262 TV |
228 | */ |
229 | ||
2c6360fb | 230 | for (i = 0; i < 25; ++i) { |
100c8262 TV |
231 | bool ok; |
232 | ||
233 | memset(ctx, 0, sizeof(*ctx)); | |
234 | if (pck > 1000 * i * i * i) | |
235 | ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); | |
236 | else | |
237 | ctx->pck_min = 0; | |
238 | ctx->pck_max = pck + 1000 * i * i * i; | |
239 | ||
240 | ok = dss_div_calc(ctx->pck_min, dpi_calc_dss_cb, ctx); | |
241 | if (ok) | |
242 | return ok; | |
243 | } | |
244 | ||
245 | return false; | |
246 | } | |
247 | ||
248 | ||
249 | ||
03a0d1e8 | 250 | static int dpi_set_dsi_clk(enum omap_channel channel, |
ff1b2cde SS |
251 | unsigned long pck_req, unsigned long *fck, int *lck_div, |
252 | int *pck_div) | |
553c48cf | 253 | { |
100c8262 | 254 | struct dpi_clk_calc_ctx ctx; |
553c48cf | 255 | int r; |
100c8262 | 256 | bool ok; |
553c48cf | 257 | |
100c8262 TV |
258 | ok = dpi_dsi_clk_calc(pck_req, &ctx); |
259 | if (!ok) | |
260 | return -EINVAL; | |
553c48cf | 261 | |
100c8262 | 262 | r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo); |
553c48cf TV |
263 | if (r) |
264 | return r; | |
265 | ||
03a0d1e8 TV |
266 | dss_select_lcd_clk_source(channel, |
267 | dpi_get_alt_clk_src(channel)); | |
553c48cf | 268 | |
100c8262 | 269 | dpi.mgr_config.clock_info = ctx.dispc_cinfo; |
553c48cf | 270 | |
100c8262 TV |
271 | *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk; |
272 | *lck_div = ctx.dispc_cinfo.lck_div; | |
273 | *pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf TV |
274 | |
275 | return 0; | |
276 | } | |
7636b3b4 | 277 | |
03a0d1e8 TV |
278 | static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck, |
279 | int *lck_div, int *pck_div) | |
553c48cf | 280 | { |
100c8262 | 281 | struct dpi_clk_calc_ctx ctx; |
553c48cf | 282 | int r; |
100c8262 | 283 | bool ok; |
553c48cf | 284 | |
100c8262 TV |
285 | ok = dpi_dss_clk_calc(pck_req, &ctx); |
286 | if (!ok) | |
287 | return -EINVAL; | |
553c48cf | 288 | |
100c8262 | 289 | r = dss_set_clock_div(&ctx.dss_cinfo); |
553c48cf TV |
290 | if (r) |
291 | return r; | |
292 | ||
100c8262 | 293 | dpi.mgr_config.clock_info = ctx.dispc_cinfo; |
553c48cf | 294 | |
100c8262 TV |
295 | *fck = ctx.dss_cinfo.fck; |
296 | *lck_div = ctx.dispc_cinfo.lck_div; | |
297 | *pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf TV |
298 | |
299 | return 0; | |
300 | } | |
553c48cf | 301 | |
03a0d1e8 | 302 | static int dpi_set_mode(struct omap_overlay_manager *mgr) |
553c48cf | 303 | { |
c499144c | 304 | struct omap_video_timings *t = &dpi.timings; |
7636b3b4 AT |
305 | int lck_div = 0, pck_div = 0; |
306 | unsigned long fck = 0; | |
553c48cf | 307 | unsigned long pck; |
553c48cf TV |
308 | int r = 0; |
309 | ||
8a3db406 | 310 | if (dpi.dsidev) |
03a0d1e8 | 311 | r = dpi_set_dsi_clk(mgr->id, t->pixel_clock * 1000, &fck, |
6d523e7b | 312 | &lck_div, &pck_div); |
7636b3b4 | 313 | else |
03a0d1e8 | 314 | r = dpi_set_dispc_clk(t->pixel_clock * 1000, &fck, |
6d523e7b | 315 | &lck_div, &pck_div); |
553c48cf | 316 | if (r) |
4fbafaf3 | 317 | return r; |
553c48cf TV |
318 | |
319 | pck = fck / lck_div / pck_div / 1000; | |
320 | ||
321 | if (pck != t->pixel_clock) { | |
322 | DSSWARN("Could not find exact pixel clock. " | |
323 | "Requested %d kHz, got %lu kHz\n", | |
324 | t->pixel_clock, pck); | |
325 | ||
326 | t->pixel_clock = pck; | |
327 | } | |
328 | ||
5d512fcd | 329 | dss_mgr_set_timings(mgr, t); |
553c48cf | 330 | |
4fbafaf3 | 331 | return 0; |
553c48cf TV |
332 | } |
333 | ||
03a0d1e8 | 334 | static void dpi_config_lcd_manager(struct omap_overlay_manager *mgr) |
553c48cf | 335 | { |
5cf9a264 | 336 | dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; |
569969d6 | 337 | |
5cf9a264 AT |
338 | dpi.mgr_config.stallmode = false; |
339 | dpi.mgr_config.fifohandcheck = false; | |
340 | ||
c6b393d4 | 341 | dpi.mgr_config.video_port_width = dpi.data_lines; |
5cf9a264 AT |
342 | |
343 | dpi.mgr_config.lcden_sig_polarity = 0; | |
344 | ||
5d512fcd | 345 | dss_mgr_set_lcd_config(mgr, &dpi.mgr_config); |
553c48cf TV |
346 | } |
347 | ||
86a3efe1 | 348 | static int dpi_display_enable(struct omap_dss_device *dssdev) |
553c48cf | 349 | { |
1f68d9c4 | 350 | struct omap_dss_device *out = &dpi.output; |
553c48cf TV |
351 | int r; |
352 | ||
c8a5e4e8 AT |
353 | mutex_lock(&dpi.lock); |
354 | ||
195e672a | 355 | if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi.vdds_dsi_reg) { |
40410715 | 356 | DSSERR("no VDSS_DSI regulator\n"); |
c8a5e4e8 AT |
357 | r = -ENODEV; |
358 | goto err_no_reg; | |
40410715 RK |
359 | } |
360 | ||
5d512fcd AT |
361 | if (out == NULL || out->manager == NULL) { |
362 | DSSERR("failed to enable display: no output/manager\n"); | |
c8a5e4e8 | 363 | r = -ENODEV; |
5d512fcd | 364 | goto err_no_out_mgr; |
05e1d606 TV |
365 | } |
366 | ||
195e672a | 367 | if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) { |
8a2cfea8 TV |
368 | r = regulator_enable(dpi.vdds_dsi_reg); |
369 | if (r) | |
4fbafaf3 | 370 | goto err_reg_enable; |
8a2cfea8 TV |
371 | } |
372 | ||
4fbafaf3 | 373 | r = dispc_runtime_get(); |
553c48cf | 374 | if (r) |
4fbafaf3 TV |
375 | goto err_get_dispc; |
376 | ||
03a0d1e8 | 377 | r = dss_dpi_select_source(out->manager->id); |
de09e455 TV |
378 | if (r) |
379 | goto err_src_sel; | |
380 | ||
8a3db406 | 381 | if (dpi.dsidev) { |
4fbafaf3 TV |
382 | r = dsi_runtime_get(dpi.dsidev); |
383 | if (r) | |
384 | goto err_get_dsi; | |
385 | ||
a72b64b9 | 386 | r = dsi_pll_init(dpi.dsidev, 0, 1); |
7636b3b4 | 387 | if (r) |
4fbafaf3 | 388 | goto err_dsi_pll_init; |
7636b3b4 AT |
389 | } |
390 | ||
03a0d1e8 | 391 | r = dpi_set_mode(out->manager); |
553c48cf | 392 | if (r) |
4fbafaf3 | 393 | goto err_set_mode; |
553c48cf | 394 | |
03a0d1e8 | 395 | dpi_config_lcd_manager(out->manager); |
5cf9a264 | 396 | |
553c48cf TV |
397 | mdelay(2); |
398 | ||
5d512fcd | 399 | r = dss_mgr_enable(out->manager); |
33ca237f TV |
400 | if (r) |
401 | goto err_mgr_enable; | |
553c48cf | 402 | |
c8a5e4e8 AT |
403 | mutex_unlock(&dpi.lock); |
404 | ||
553c48cf TV |
405 | return 0; |
406 | ||
33ca237f | 407 | err_mgr_enable: |
4fbafaf3 | 408 | err_set_mode: |
8a3db406 | 409 | if (dpi.dsidev) |
19077a73 | 410 | dsi_pll_uninit(dpi.dsidev, true); |
4fbafaf3 | 411 | err_dsi_pll_init: |
8a3db406 | 412 | if (dpi.dsidev) |
4fbafaf3 TV |
413 | dsi_runtime_put(dpi.dsidev); |
414 | err_get_dsi: | |
de09e455 | 415 | err_src_sel: |
4fbafaf3 TV |
416 | dispc_runtime_put(); |
417 | err_get_dispc: | |
195e672a | 418 | if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) |
8a2cfea8 | 419 | regulator_disable(dpi.vdds_dsi_reg); |
4fbafaf3 | 420 | err_reg_enable: |
5d512fcd | 421 | err_no_out_mgr: |
c8a5e4e8 AT |
422 | err_no_reg: |
423 | mutex_unlock(&dpi.lock); | |
553c48cf TV |
424 | return r; |
425 | } | |
426 | ||
86a3efe1 | 427 | static void dpi_display_disable(struct omap_dss_device *dssdev) |
553c48cf | 428 | { |
03a0d1e8 | 429 | struct omap_overlay_manager *mgr = dpi.output.manager; |
5d512fcd | 430 | |
c8a5e4e8 AT |
431 | mutex_lock(&dpi.lock); |
432 | ||
5d512fcd | 433 | dss_mgr_disable(mgr); |
553c48cf | 434 | |
8a3db406 | 435 | if (dpi.dsidev) { |
a5b8399f | 436 | dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); |
a72b64b9 | 437 | dsi_pll_uninit(dpi.dsidev, true); |
4fbafaf3 | 438 | dsi_runtime_put(dpi.dsidev); |
7636b3b4 | 439 | } |
553c48cf | 440 | |
4fbafaf3 | 441 | dispc_runtime_put(); |
553c48cf | 442 | |
195e672a | 443 | if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) |
8a2cfea8 TV |
444 | regulator_disable(dpi.vdds_dsi_reg); |
445 | ||
c8a5e4e8 | 446 | mutex_unlock(&dpi.lock); |
553c48cf | 447 | } |
553c48cf | 448 | |
86a3efe1 | 449 | static void dpi_set_timings(struct omap_dss_device *dssdev, |
c499144c | 450 | struct omap_video_timings *timings) |
553c48cf TV |
451 | { |
452 | DSSDBG("dpi_set_timings\n"); | |
c8a5e4e8 AT |
453 | |
454 | mutex_lock(&dpi.lock); | |
455 | ||
c499144c | 456 | dpi.timings = *timings; |
c499144c | 457 | |
c8a5e4e8 | 458 | mutex_unlock(&dpi.lock); |
553c48cf TV |
459 | } |
460 | ||
0b24edb1 TV |
461 | static void dpi_get_timings(struct omap_dss_device *dssdev, |
462 | struct omap_video_timings *timings) | |
463 | { | |
464 | mutex_lock(&dpi.lock); | |
465 | ||
466 | *timings = dpi.timings; | |
467 | ||
468 | mutex_unlock(&dpi.lock); | |
469 | } | |
470 | ||
86a3efe1 | 471 | static int dpi_check_timings(struct omap_dss_device *dssdev, |
553c48cf TV |
472 | struct omap_video_timings *timings) |
473 | { | |
03a0d1e8 | 474 | struct omap_overlay_manager *mgr = dpi.output.manager; |
553c48cf TV |
475 | int lck_div, pck_div; |
476 | unsigned long fck; | |
477 | unsigned long pck; | |
100c8262 TV |
478 | struct dpi_clk_calc_ctx ctx; |
479 | bool ok; | |
553c48cf | 480 | |
8b095513 | 481 | if (mgr && !dispc_mgr_timings_ok(mgr->id, timings)) |
553c48cf TV |
482 | return -EINVAL; |
483 | ||
484 | if (timings->pixel_clock == 0) | |
485 | return -EINVAL; | |
486 | ||
8a3db406 | 487 | if (dpi.dsidev) { |
100c8262 TV |
488 | ok = dpi_dsi_clk_calc(timings->pixel_clock * 1000, &ctx); |
489 | if (!ok) | |
490 | return -EINVAL; | |
553c48cf | 491 | |
100c8262 | 492 | fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk; |
7636b3b4 | 493 | } else { |
100c8262 TV |
494 | ok = dpi_dss_clk_calc(timings->pixel_clock * 1000, &ctx); |
495 | if (!ok) | |
496 | return -EINVAL; | |
553c48cf | 497 | |
100c8262 | 498 | fck = ctx.dss_cinfo.fck; |
553c48cf | 499 | } |
7636b3b4 | 500 | |
100c8262 TV |
501 | lck_div = ctx.dispc_cinfo.lck_div; |
502 | pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf TV |
503 | |
504 | pck = fck / lck_div / pck_div / 1000; | |
505 | ||
506 | timings->pixel_clock = pck; | |
507 | ||
508 | return 0; | |
509 | } | |
553c48cf | 510 | |
86a3efe1 | 511 | static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines) |
c6b393d4 AT |
512 | { |
513 | mutex_lock(&dpi.lock); | |
514 | ||
515 | dpi.data_lines = data_lines; | |
516 | ||
517 | mutex_unlock(&dpi.lock); | |
518 | } | |
c6b393d4 | 519 | |
94cf394b | 520 | static int dpi_verify_dsi_pll(struct platform_device *dsidev) |
6061675b TV |
521 | { |
522 | int r; | |
523 | ||
524 | /* do initial setup with the PLL to see if it is operational */ | |
525 | ||
526 | r = dsi_runtime_get(dsidev); | |
527 | if (r) | |
528 | return r; | |
529 | ||
530 | r = dsi_pll_init(dsidev, 0, 1); | |
531 | if (r) { | |
532 | dsi_runtime_put(dsidev); | |
533 | return r; | |
534 | } | |
535 | ||
536 | dsi_pll_uninit(dsidev, true); | |
537 | dsi_runtime_put(dsidev); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
2795f646 TV |
542 | static int dpi_init_regulator(void) |
543 | { | |
544 | struct regulator *vdds_dsi; | |
545 | ||
546 | if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) | |
547 | return 0; | |
548 | ||
549 | if (dpi.vdds_dsi_reg) | |
550 | return 0; | |
551 | ||
4123de21 | 552 | vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi"); |
2795f646 | 553 | if (IS_ERR(vdds_dsi)) { |
40359a9b TV |
554 | if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) |
555 | DSSERR("can't get VDDS_DSI regulator\n"); | |
4123de21 | 556 | return PTR_ERR(vdds_dsi); |
2795f646 TV |
557 | } |
558 | ||
559 | dpi.vdds_dsi_reg = vdds_dsi; | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | static void dpi_init_pll(void) | |
565 | { | |
566 | struct platform_device *dsidev; | |
567 | ||
568 | if (dpi.dsidev) | |
569 | return; | |
570 | ||
571 | dsidev = dpi_get_dsidev(dpi.output.dispc_channel); | |
572 | if (!dsidev) | |
573 | return; | |
574 | ||
575 | if (dpi_verify_dsi_pll(dsidev)) { | |
576 | DSSWARN("DSI PLL not operational\n"); | |
577 | return; | |
578 | } | |
579 | ||
580 | dpi.dsidev = dsidev; | |
581 | } | |
582 | ||
2eea5ae6 TV |
583 | /* |
584 | * Return a hardcoded channel for the DPI output. This should work for | |
585 | * current use cases, but this can be later expanded to either resolve | |
586 | * the channel in some more dynamic manner, or get the channel as a user | |
587 | * parameter. | |
588 | */ | |
589 | static enum omap_channel dpi_get_channel(void) | |
590 | { | |
591 | switch (omapdss_get_version()) { | |
592 | case OMAPDSS_VER_OMAP24xx: | |
593 | case OMAPDSS_VER_OMAP34xx_ES1: | |
594 | case OMAPDSS_VER_OMAP34xx_ES3: | |
595 | case OMAPDSS_VER_OMAP3630: | |
596 | case OMAPDSS_VER_AM35xx: | |
597 | return OMAP_DSS_CHANNEL_LCD; | |
598 | ||
599 | case OMAPDSS_VER_OMAP4430_ES1: | |
600 | case OMAPDSS_VER_OMAP4430_ES2: | |
601 | case OMAPDSS_VER_OMAP4: | |
602 | return OMAP_DSS_CHANNEL_LCD2; | |
603 | ||
604 | case OMAPDSS_VER_OMAP5: | |
605 | return OMAP_DSS_CHANNEL_LCD3; | |
606 | ||
607 | default: | |
608 | DSSWARN("unsupported DSS version\n"); | |
609 | return OMAP_DSS_CHANNEL_LCD; | |
610 | } | |
611 | } | |
612 | ||
0b24edb1 TV |
613 | static int dpi_connect(struct omap_dss_device *dssdev, |
614 | struct omap_dss_device *dst) | |
615 | { | |
616 | struct omap_overlay_manager *mgr; | |
617 | int r; | |
618 | ||
619 | r = dpi_init_regulator(); | |
620 | if (r) | |
621 | return r; | |
622 | ||
623 | dpi_init_pll(); | |
624 | ||
625 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | |
626 | if (!mgr) | |
627 | return -ENODEV; | |
628 | ||
629 | r = dss_mgr_connect(mgr, dssdev); | |
630 | if (r) | |
631 | return r; | |
632 | ||
633 | r = omapdss_output_set_device(dssdev, dst); | |
634 | if (r) { | |
635 | DSSERR("failed to connect output to new device: %s\n", | |
636 | dst->name); | |
637 | dss_mgr_disconnect(mgr, dssdev); | |
638 | return r; | |
639 | } | |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
644 | static void dpi_disconnect(struct omap_dss_device *dssdev, | |
645 | struct omap_dss_device *dst) | |
646 | { | |
9560dc10 | 647 | WARN_ON(dst != dssdev->dst); |
0b24edb1 | 648 | |
9560dc10 | 649 | if (dst != dssdev->dst) |
0b24edb1 TV |
650 | return; |
651 | ||
652 | omapdss_output_unset_device(dssdev); | |
653 | ||
654 | if (dssdev->manager) | |
655 | dss_mgr_disconnect(dssdev->manager, dssdev); | |
656 | } | |
657 | ||
658 | static const struct omapdss_dpi_ops dpi_ops = { | |
659 | .connect = dpi_connect, | |
660 | .disconnect = dpi_disconnect, | |
661 | ||
86a3efe1 TV |
662 | .enable = dpi_display_enable, |
663 | .disable = dpi_display_disable, | |
0b24edb1 TV |
664 | |
665 | .check_timings = dpi_check_timings, | |
86a3efe1 | 666 | .set_timings = dpi_set_timings, |
0b24edb1 TV |
667 | .get_timings = dpi_get_timings, |
668 | ||
86a3efe1 | 669 | .set_data_lines = dpi_set_data_lines, |
0b24edb1 TV |
670 | }; |
671 | ||
94cf394b | 672 | static void dpi_init_output(struct platform_device *pdev) |
81b87f51 | 673 | { |
1f68d9c4 | 674 | struct omap_dss_device *out = &dpi.output; |
81b87f51 | 675 | |
1f68d9c4 | 676 | out->dev = &pdev->dev; |
81b87f51 | 677 | out->id = OMAP_DSS_OUTPUT_DPI; |
1f68d9c4 | 678 | out->output_type = OMAP_DISPLAY_TYPE_DPI; |
7286a08f | 679 | out->name = "dpi.0"; |
2eea5ae6 | 680 | out->dispc_channel = dpi_get_channel(); |
0b24edb1 | 681 | out->ops.dpi = &dpi_ops; |
b7328e14 | 682 | out->owner = THIS_MODULE; |
81b87f51 | 683 | |
5d47dbc8 | 684 | omapdss_register_output(out); |
81b87f51 AT |
685 | } |
686 | ||
687 | static void __exit dpi_uninit_output(struct platform_device *pdev) | |
688 | { | |
1f68d9c4 | 689 | struct omap_dss_device *out = &dpi.output; |
81b87f51 | 690 | |
5d47dbc8 | 691 | omapdss_unregister_output(out); |
81b87f51 AT |
692 | } |
693 | ||
94cf394b | 694 | static int omap_dpi_probe(struct platform_device *pdev) |
38f3daf6 | 695 | { |
00df43b8 TV |
696 | dpi.pdev = pdev; |
697 | ||
c8a5e4e8 AT |
698 | mutex_init(&dpi.lock); |
699 | ||
81b87f51 AT |
700 | dpi_init_output(pdev); |
701 | ||
5f42f2ce TV |
702 | return 0; |
703 | } | |
704 | ||
6e7e8f06 | 705 | static int __exit omap_dpi_remove(struct platform_device *pdev) |
553c48cf | 706 | { |
81b87f51 AT |
707 | dpi_uninit_output(pdev); |
708 | ||
a57dd4fe | 709 | return 0; |
553c48cf TV |
710 | } |
711 | ||
a57dd4fe | 712 | static struct platform_driver omap_dpi_driver = { |
94cf394b | 713 | .probe = omap_dpi_probe, |
6e7e8f06 | 714 | .remove = __exit_p(omap_dpi_remove), |
a57dd4fe TV |
715 | .driver = { |
716 | .name = "omapdss_dpi", | |
717 | .owner = THIS_MODULE, | |
718 | }, | |
719 | }; | |
720 | ||
6e7e8f06 | 721 | int __init dpi_init_platform_driver(void) |
a57dd4fe | 722 | { |
94cf394b | 723 | return platform_driver_register(&omap_dpi_driver); |
a57dd4fe TV |
724 | } |
725 | ||
6e7e8f06 | 726 | void __exit dpi_uninit_platform_driver(void) |
a57dd4fe TV |
727 | { |
728 | platform_driver_unregister(&omap_dpi_driver); | |
729 | } |