[deliverable/linux.git] / drivers / video / omap2 / dss / dpi.c

/*
 * linux/drivers/video/omap2/dss/dpi.c
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "DPI"

#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#include <video/omapdss.h>
#include <plat/cpu.h>

#include "dss.h"

static struct {
	struct regulator *vdds_dsi_reg;
	struct platform_device *dsidev;
} dpi;

static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
{
	int dsi_module;

	dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;

	return dsi_get_dsidev_from_id(dsi_module);
}

static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
{
	if (dssdev->clocks.dispc.dispc_fclk_src ==
			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
			dssdev->clocks.dispc.dispc_fclk_src ==
			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
			dssdev->clocks.dispc.channel.lcd_clk_src ==
			OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
			dssdev->clocks.dispc.channel.lcd_clk_src ==
			OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
		return true;
	else
		return false;
}

static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
		unsigned long pck_req, unsigned long *fck, int *lck_div,
		int *pck_div)
{
	struct dsi_clock_info dsi_cinfo;
	struct dispc_clock_info dispc_cinfo;
	int r;

	r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
			&dsi_cinfo, &dispc_cinfo);
	if (r)
		return r;

	r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
	if (r)
		return r;

	dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);

	r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
	if (r) {
		dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
		return r;
	}

	*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
	*lck_div = dispc_cinfo.lck_div;
	*pck_div = dispc_cinfo.pck_div;

	return 0;
}

static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
		unsigned long pck_req, unsigned long *fck, int *lck_div,
		int *pck_div)
{
	struct dss_clock_info dss_cinfo;
	struct dispc_clock_info dispc_cinfo;
	int r;

	r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
	if (r)
		return r;

	r = dss_set_clock_div(&dss_cinfo);
	if (r)
		return r;

	r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
	if (r)
		return r;

	*fck = dss_cinfo.fck;
	*lck_div = dispc_cinfo.lck_div;
	*pck_div = dispc_cinfo.pck_div;

	return 0;
}

static int dpi_set_mode(struct omap_dss_device *dssdev)
{
	struct omap_video_timings *t = &dssdev->panel.timings;
	int lck_div = 0, pck_div = 0;
	unsigned long fck = 0;
	unsigned long pck;
	bool is_tft;
	int r = 0;

	dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
			dssdev->panel.acbi, dssdev->panel.acb);

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

	if (dpi_use_dsi_pll(dssdev))
		r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
				&fck, &lck_div, &pck_div);
	else
		r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
				&fck, &lck_div, &pck_div);
	if (r)
		return r;

	pck = fck / lck_div / pck_div / 1000;

	if (pck != t->pixel_clock) {
		DSSWARN("Could not find exact pixel clock. "
				"Requested %d kHz, got %lu kHz\n",
				t->pixel_clock, pck);

		t->pixel_clock = pck;
	}

	dispc_mgr_set_lcd_timings(dssdev->manager->id, t);

	return 0;
}

static void dpi_basic_init(struct omap_dss_device *dssdev)
{
	bool is_tft;

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

	dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
	dispc_mgr_enable_stallmode(dssdev->manager->id, false);

	dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ?
			OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
	dispc_mgr_set_tft_data_lines(dssdev->manager->id,
			dssdev->phy.dpi.data_lines);
}

int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
{
	int r;

	if (dssdev->manager == NULL) {
		DSSERR("failed to enable display: no manager\n");
		return -ENODEV;
	}

	r = omap_dss_start_device(dssdev);
	if (r) {
		DSSERR("failed to start device\n");
		goto err_start_dev;
	}

	if (cpu_is_omap34xx()) {
		r = regulator_enable(dpi.vdds_dsi_reg);
		if (r)
			goto err_reg_enable;
	}

	r = dss_runtime_get();
	if (r)
		goto err_get_dss;

	r = dispc_runtime_get();
	if (r)
		goto err_get_dispc;

	dpi_basic_init(dssdev);

	if (dpi_use_dsi_pll(dssdev)) {
		r = dsi_runtime_get(dpi.dsidev);
		if (r)
			goto err_get_dsi;

		r = dsi_pll_init(dpi.dsidev, 0, 1);
		if (r)
			goto err_dsi_pll_init;
	}

	r = dpi_set_mode(dssdev);
	if (r)
		goto err_set_mode;

	mdelay(2);

	dss_mgr_enable(dssdev->manager);

	return 0;

err_set_mode:
	if (dpi_use_dsi_pll(dssdev))
		dsi_pll_uninit(dpi.dsidev, true);
err_dsi_pll_init:
	if (dpi_use_dsi_pll(dssdev))
		dsi_runtime_put(dpi.dsidev);
err_get_dsi:
	dispc_runtime_put();
err_get_dispc:
	dss_runtime_put();
err_get_dss:
	if (cpu_is_omap34xx())
		regulator_disable(dpi.vdds_dsi_reg);
err_reg_enable:
	omap_dss_stop_device(dssdev);
err_start_dev:
	return r;
}
EXPORT_SYMBOL(omapdss_dpi_display_enable);

void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
{
	dss_mgr_disable(dssdev->manager);

	if (dpi_use_dsi_pll(dssdev)) {
		dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
		dsi_pll_uninit(dpi.dsidev, true);
		dsi_runtime_put(dpi.dsidev);
	}

	dispc_runtime_put();
	dss_runtime_put();

	if (cpu_is_omap34xx())
		regulator_disable(dpi.vdds_dsi_reg);

	omap_dss_stop_device(dssdev);
}
EXPORT_SYMBOL(omapdss_dpi_display_disable);

void dpi_set_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings)
{
	int r;

	DSSDBG("dpi_set_timings\n");
	dssdev->panel.timings = *timings;
	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
		r = dss_runtime_get();
		if (r)
			return;

		r = dispc_runtime_get();
		if (r) {
			dss_runtime_put();
			return;
		}

		dpi_set_mode(dssdev);
		dispc_mgr_go(dssdev->manager->id);

		dispc_runtime_put();
		dss_runtime_put();
	}
}
EXPORT_SYMBOL(dpi_set_timings);

int dpi_check_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings)
{
	bool is_tft;
	int r;
	int lck_div, pck_div;
	unsigned long fck;
	unsigned long pck;
	struct dispc_clock_info dispc_cinfo;

	if (!dispc_lcd_timings_ok(timings))
		return -EINVAL;

	if (timings->pixel_clock == 0)
		return -EINVAL;

	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;

	if (dpi_use_dsi_pll(dssdev)) {
		struct dsi_clock_info dsi_cinfo;
		r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
				timings->pixel_clock * 1000,
				&dsi_cinfo, &dispc_cinfo);

		if (r)
			return r;

		fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
	} else {
		struct dss_clock_info dss_cinfo;
		r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
				&dss_cinfo, &dispc_cinfo);

		if (r)
			return r;

		fck = dss_cinfo.fck;
	}

	lck_div = dispc_cinfo.lck_div;
	pck_div = dispc_cinfo.pck_div;

	pck = fck / lck_div / pck_div / 1000;

	timings->pixel_clock = pck;

	return 0;
}
EXPORT_SYMBOL(dpi_check_timings);

int dpi_init_display(struct omap_dss_device *dssdev)
{
	DSSDBG("init_display\n");

	if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
		struct regulator *vdds_dsi;

		vdds_dsi = dss_get_vdds_dsi();

		if (IS_ERR(vdds_dsi)) {
			DSSERR("can't get VDDS_DSI regulator\n");
			return PTR_ERR(vdds_dsi);
		}

		dpi.vdds_dsi_reg = vdds_dsi;
	}

	if (dpi_use_dsi_pll(dssdev)) {
		enum omap_dss_clk_source dispc_fclk_src =
			dssdev->clocks.dispc.dispc_fclk_src;
		dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
	}

	return 0;
}

int dpi_init(void)
{
	return 0;
}

void dpi_exit(void)
{
}
Commit	Line	Data
553c48cf TV	1	/*
	2	* linux/drivers/video/omap2/dss/dpi.c
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	6	*
	7	* Some code and ideas taken from drivers/video/omap/ driver
	8	* by Imre Deak.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along with
	20	* this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#define DSS_SUBSYS_NAME "DPI"
	24
	25	#include <linux/kernel.h>
553c48cf	26	#include <linux/delay.h>
a8a35931	27	#include <linux/export.h>
8a2cfea8	28	#include <linux/err.h>
553c48cf	29	#include <linux/errno.h>
8a2cfea8 TV	30	#include <linux/platform_device.h>
8a2cfea8 TV	31	#include <linux/regulator/consumer.h>
553c48cf	32
a0b38cc4	33	#include <video/omapdss.h>
553c48cf TV	34	#include <plat/cpu.h>
	35
	36	#include "dss.h"
	37
	38	static struct {
8a2cfea8	39	struct regulator *vdds_dsi_reg;
a72b64b9	40	struct platform_device *dsidev;
553c48cf TV	41	} dpi;
553c48cf TV	42
a72b64b9 AT	43	static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
	44	{
	45	int dsi_module;
	46
	47	dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
	48
	49	return dsi_get_dsidev_from_id(dsi_module);
	50	}
	51
7636b3b4 AT	52	static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
	53	{
	54	if (dssdev->clocks.dispc.dispc_fclk_src ==
	55	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC \|\|
5a8b572d AT	56	dssdev->clocks.dispc.dispc_fclk_src ==
5a8b572d AT	57	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC \|\|
7636b3b4	58	dssdev->clocks.dispc.channel.lcd_clk_src ==
5a8b572d AT	59	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC \|\|
	60	dssdev->clocks.dispc.channel.lcd_clk_src ==
	61	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
7636b3b4 AT	62	return true;
	63	else
	64	return false;
	65	}
	66
ff1b2cde SS	67	static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
	68	unsigned long pck_req, unsigned long fck, int lck_div,
	69	int *pck_div)
553c48cf TV	70	{
	71	struct dsi_clock_info dsi_cinfo;
	72	struct dispc_clock_info dispc_cinfo;
	73	int r;
	74
a72b64b9 AT	75	r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
a72b64b9 AT	76	&dsi_cinfo, &dispc_cinfo);
553c48cf TV	77	if (r)
	78	return r;
	79
a72b64b9	80	r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
553c48cf TV	81	if (r)
	82	return r;
	83
e8881662	84	dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
553c48cf	85
26d9dd0d	86	r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
5e785091 TV	87	if (r) {
5e785091 TV	88	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
553c48cf	89	return r;
5e785091	90	}
553c48cf	91
1bb47835	92	*fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
553c48cf TV	93	*lck_div = dispc_cinfo.lck_div;
	94	*pck_div = dispc_cinfo.pck_div;
	95
	96	return 0;
	97	}
7636b3b4	98
ff1b2cde SS	99	static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
	100	unsigned long pck_req, unsigned long fck, int lck_div,
	101	int *pck_div)
553c48cf TV	102	{
	103	struct dss_clock_info dss_cinfo;
	104	struct dispc_clock_info dispc_cinfo;
	105	int r;
	106
	107	r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
	108	if (r)
	109	return r;
	110
	111	r = dss_set_clock_div(&dss_cinfo);
	112	if (r)
	113	return r;
	114
26d9dd0d	115	r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
553c48cf TV	116	if (r)
	117	return r;
	118
	119	*fck = dss_cinfo.fck;
	120	*lck_div = dispc_cinfo.lck_div;
	121	*pck_div = dispc_cinfo.pck_div;
	122
	123	return 0;
	124	}
553c48cf TV	125
	126	static int dpi_set_mode(struct omap_dss_device *dssdev)
	127	{
	128	struct omap_video_timings *t = &dssdev->panel.timings;
7636b3b4 AT	129	int lck_div = 0, pck_div = 0;
7636b3b4 AT	130	unsigned long fck = 0;
553c48cf TV	131	unsigned long pck;
	132	bool is_tft;
	133	int r = 0;
	134
26d9dd0d	135	dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
ff1b2cde	136	dssdev->panel.acbi, dssdev->panel.acb);
553c48cf TV	137
	138	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
	139
7636b3b4 AT	140	if (dpi_use_dsi_pll(dssdev))
	141	r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
	142	&fck, &lck_div, &pck_div);
	143	else
	144	r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
	145	&fck, &lck_div, &pck_div);
553c48cf	146	if (r)
4fbafaf3	147	return r;
553c48cf TV	148
	149	pck = fck / lck_div / pck_div / 1000;
	150
	151	if (pck != t->pixel_clock) {
	152	DSSWARN("Could not find exact pixel clock. "
	153	"Requested %d kHz, got %lu kHz\n",
	154	t->pixel_clock, pck);
	155
	156	t->pixel_clock = pck;
	157	}
	158
26d9dd0d	159	dispc_mgr_set_lcd_timings(dssdev->manager->id, t);
553c48cf	160
4fbafaf3	161	return 0;
553c48cf TV	162	}
553c48cf TV	163
4fbafaf3	164	static void dpi_basic_init(struct omap_dss_device *dssdev)
553c48cf TV	165	{
	166	bool is_tft;
	167
	168	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
	169
569969d6 AT	170	dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
	171	dispc_mgr_enable_stallmode(dssdev->manager->id, false);
	172
26d9dd0d	173	dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ?
64ba4f74	174	OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
26d9dd0d	175	dispc_mgr_set_tft_data_lines(dssdev->manager->id,
64ba4f74	176	dssdev->phy.dpi.data_lines);
553c48cf TV	177	}
553c48cf TV	178
37ac60e4	179	int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
553c48cf TV	180	{
	181	int r;
	182
05e1d606 TV	183	if (dssdev->manager == NULL) {
	184	DSSERR("failed to enable display: no manager\n");
	185	return -ENODEV;
	186	}
	187
553c48cf TV	188	r = omap_dss_start_device(dssdev);
	189	if (r) {
	190	DSSERR("failed to start device\n");
4fbafaf3	191	goto err_start_dev;
553c48cf TV	192	}
553c48cf TV	193
8a2cfea8 TV	194	if (cpu_is_omap34xx()) {
	195	r = regulator_enable(dpi.vdds_dsi_reg);
	196	if (r)
4fbafaf3	197	goto err_reg_enable;
8a2cfea8 TV	198	}
8a2cfea8 TV	199
4fbafaf3 TV	200	r = dss_runtime_get();
	201	if (r)
	202	goto err_get_dss;
553c48cf	203
4fbafaf3	204	r = dispc_runtime_get();
553c48cf	205	if (r)
4fbafaf3 TV	206	goto err_get_dispc;
	207
	208	dpi_basic_init(dssdev);
553c48cf	209
7636b3b4	210	if (dpi_use_dsi_pll(dssdev)) {
4fbafaf3 TV	211	r = dsi_runtime_get(dpi.dsidev);
	212	if (r)
	213	goto err_get_dsi;
	214
a72b64b9	215	r = dsi_pll_init(dpi.dsidev, 0, 1);
7636b3b4	216	if (r)
4fbafaf3	217	goto err_dsi_pll_init;
7636b3b4 AT	218	}
7636b3b4 AT	219
553c48cf TV	220	r = dpi_set_mode(dssdev);
553c48cf TV	221	if (r)
4fbafaf3	222	goto err_set_mode;
553c48cf TV	223
	224	mdelay(2);
	225
7797c6da	226	dss_mgr_enable(dssdev->manager);
553c48cf	227
553c48cf TV	228	return 0;
553c48cf TV	229
4fbafaf3	230	err_set_mode:
7636b3b4	231	if (dpi_use_dsi_pll(dssdev))
19077a73	232	dsi_pll_uninit(dpi.dsidev, true);
4fbafaf3 TV	233	err_dsi_pll_init:
	234	if (dpi_use_dsi_pll(dssdev))
	235	dsi_runtime_put(dpi.dsidev);
	236	err_get_dsi:
	237	dispc_runtime_put();
	238	err_get_dispc:
	239	dss_runtime_put();
	240	err_get_dss:
8a2cfea8 TV	241	if (cpu_is_omap34xx())
8a2cfea8 TV	242	regulator_disable(dpi.vdds_dsi_reg);
4fbafaf3	243	err_reg_enable:
553c48cf	244	omap_dss_stop_device(dssdev);
4fbafaf3	245	err_start_dev:
553c48cf TV	246	return r;
553c48cf TV	247	}
37ac60e4	248	EXPORT_SYMBOL(omapdss_dpi_display_enable);
553c48cf	249
37ac60e4	250	void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
553c48cf	251	{
7797c6da	252	dss_mgr_disable(dssdev->manager);
553c48cf	253
7636b3b4 AT	254	if (dpi_use_dsi_pll(dssdev)) {
7636b3b4 AT	255	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
a72b64b9	256	dsi_pll_uninit(dpi.dsidev, true);
4fbafaf3	257	dsi_runtime_put(dpi.dsidev);
7636b3b4	258	}
553c48cf	259
4fbafaf3 TV	260	dispc_runtime_put();
4fbafaf3 TV	261	dss_runtime_put();
553c48cf	262
8a2cfea8 TV	263	if (cpu_is_omap34xx())
	264	regulator_disable(dpi.vdds_dsi_reg);
	265
553c48cf TV	266	omap_dss_stop_device(dssdev);
553c48cf TV	267	}
37ac60e4	268	EXPORT_SYMBOL(omapdss_dpi_display_disable);
553c48cf	269
69b2048f	270	void dpi_set_timings(struct omap_dss_device *dssdev,
553c48cf TV	271	struct omap_video_timings *timings)
553c48cf TV	272	{
4fbafaf3 TV	273	int r;
4fbafaf3 TV	274
553c48cf TV	275	DSSDBG("dpi_set_timings\n");
	276	dssdev->panel.timings = *timings;
	277	if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
4fbafaf3 TV	278	r = dss_runtime_get();
	279	if (r)
	280	return;
	281
	282	r = dispc_runtime_get();
	283	if (r) {
	284	dss_runtime_put();
	285	return;
	286	}
	287
553c48cf	288	dpi_set_mode(dssdev);
26d9dd0d	289	dispc_mgr_go(dssdev->manager->id);
4fbafaf3 TV	290
	291	dispc_runtime_put();
	292	dss_runtime_put();
553c48cf TV	293	}
553c48cf TV	294	}
69b2048f	295	EXPORT_SYMBOL(dpi_set_timings);
553c48cf	296
69b2048f	297	int dpi_check_timings(struct omap_dss_device *dssdev,
553c48cf TV	298	struct omap_video_timings *timings)
	299	{
	300	bool is_tft;
	301	int r;
	302	int lck_div, pck_div;
	303	unsigned long fck;
	304	unsigned long pck;
7636b3b4	305	struct dispc_clock_info dispc_cinfo;
553c48cf TV	306
	307	if (!dispc_lcd_timings_ok(timings))
	308	return -EINVAL;
	309
	310	if (timings->pixel_clock == 0)
	311	return -EINVAL;
	312
	313	is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
	314
7636b3b4	315	if (dpi_use_dsi_pll(dssdev)) {
553c48cf	316	struct dsi_clock_info dsi_cinfo;
a72b64b9	317	r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
553c48cf TV	318	timings->pixel_clock * 1000,
	319	&dsi_cinfo, &dispc_cinfo);
	320
	321	if (r)
	322	return r;
	323
1bb47835	324	fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
7636b3b4	325	} else {
553c48cf	326	struct dss_clock_info dss_cinfo;
553c48cf TV	327	r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
	328	&dss_cinfo, &dispc_cinfo);
	329
	330	if (r)
	331	return r;
	332
	333	fck = dss_cinfo.fck;
553c48cf	334	}
7636b3b4 AT	335
	336	lck_div = dispc_cinfo.lck_div;
	337	pck_div = dispc_cinfo.pck_div;
553c48cf TV	338
	339	pck = fck / lck_div / pck_div / 1000;
	340
	341	timings->pixel_clock = pck;
	342
	343	return 0;
	344	}
69b2048f	345	EXPORT_SYMBOL(dpi_check_timings);
553c48cf	346
553c48cf TV	347	int dpi_init_display(struct omap_dss_device *dssdev)
	348	{
	349	DSSDBG("init_display\n");
	350
5f42f2ce TV	351	if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
5f42f2ce TV	352	struct regulator *vdds_dsi;
553c48cf	353
5f42f2ce TV	354	vdds_dsi = dss_get_vdds_dsi();
	355
	356	if (IS_ERR(vdds_dsi)) {
8a2cfea8	357	DSSERR("can't get VDDS_DSI regulator\n");
5f42f2ce	358	return PTR_ERR(vdds_dsi);
8a2cfea8	359	}
5f42f2ce TV	360
5f42f2ce TV	361	dpi.vdds_dsi_reg = vdds_dsi;
8a2cfea8 TV	362	}
8a2cfea8 TV	363
a72b64b9 AT	364	if (dpi_use_dsi_pll(dssdev)) {
	365	enum omap_dss_clk_source dispc_fclk_src =
	366	dssdev->clocks.dispc.dispc_fclk_src;
	367	dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
	368	}
	369
553c48cf TV	370	return 0;
	371	}
	372
277b2881	373	int dpi_init(void)
5f42f2ce TV	374	{
	375	return 0;
	376	}
	377
553c48cf TV	378	void dpi_exit(void)
	379	{
	380	}
	381