Commit | Line | Data |
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553c48cf TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dpi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DPI" | |
24 | ||
25 | #include <linux/kernel.h> | |
553c48cf | 26 | #include <linux/delay.h> |
a8a35931 | 27 | #include <linux/export.h> |
8a2cfea8 | 28 | #include <linux/err.h> |
553c48cf | 29 | #include <linux/errno.h> |
8a2cfea8 TV |
30 | #include <linux/platform_device.h> |
31 | #include <linux/regulator/consumer.h> | |
13b1ba7d | 32 | #include <linux/string.h> |
2ecef246 | 33 | #include <linux/of.h> |
553c48cf | 34 | |
a0b38cc4 | 35 | #include <video/omapdss.h> |
553c48cf TV |
36 | |
37 | #include "dss.h" | |
195e672a | 38 | #include "dss_features.h" |
553c48cf TV |
39 | |
40 | static struct { | |
00df43b8 TV |
41 | struct platform_device *pdev; |
42 | ||
8a2cfea8 | 43 | struct regulator *vdds_dsi_reg; |
a72b64b9 | 44 | struct platform_device *dsidev; |
5cf9a264 | 45 | |
c8a5e4e8 AT |
46 | struct mutex lock; |
47 | ||
c499144c | 48 | struct omap_video_timings timings; |
5cf9a264 | 49 | struct dss_lcd_mgr_config mgr_config; |
c6b393d4 | 50 | int data_lines; |
81b87f51 | 51 | |
1f68d9c4 | 52 | struct omap_dss_device output; |
2ecef246 TV |
53 | |
54 | bool port_initialized; | |
553c48cf TV |
55 | } dpi; |
56 | ||
0e8276ef | 57 | static struct platform_device *dpi_get_dsidev(enum omap_channel channel) |
a72b64b9 | 58 | { |
bd0f5cc3 TV |
59 | /* |
60 | * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL | |
61 | * would also be used for DISPC fclk. Meaning, when the DPI output is | |
62 | * disabled, DISPC clock will be disabled, and TV out will stop. | |
63 | */ | |
64 | switch (omapdss_get_version()) { | |
65 | case OMAPDSS_VER_OMAP24xx: | |
66 | case OMAPDSS_VER_OMAP34xx_ES1: | |
67 | case OMAPDSS_VER_OMAP34xx_ES3: | |
68 | case OMAPDSS_VER_OMAP3630: | |
69 | case OMAPDSS_VER_AM35xx: | |
70 | return NULL; | |
bd0f5cc3 | 71 | |
f8ad984c TV |
72 | case OMAPDSS_VER_OMAP4430_ES1: |
73 | case OMAPDSS_VER_OMAP4430_ES2: | |
74 | case OMAPDSS_VER_OMAP4: | |
75 | switch (channel) { | |
76 | case OMAP_DSS_CHANNEL_LCD: | |
77 | return dsi_get_dsidev_from_id(0); | |
78 | case OMAP_DSS_CHANNEL_LCD2: | |
79 | return dsi_get_dsidev_from_id(1); | |
80 | default: | |
81 | return NULL; | |
82 | } | |
83 | ||
84 | case OMAPDSS_VER_OMAP5: | |
85 | switch (channel) { | |
86 | case OMAP_DSS_CHANNEL_LCD: | |
87 | return dsi_get_dsidev_from_id(0); | |
88 | case OMAP_DSS_CHANNEL_LCD3: | |
89 | return dsi_get_dsidev_from_id(1); | |
90 | default: | |
91 | return NULL; | |
92 | } | |
93 | ||
0e8276ef TV |
94 | default: |
95 | return NULL; | |
96 | } | |
a72b64b9 AT |
97 | } |
98 | ||
0e8276ef | 99 | static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel) |
7636b3b4 | 100 | { |
0e8276ef TV |
101 | switch (channel) { |
102 | case OMAP_DSS_CHANNEL_LCD: | |
103 | return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC; | |
104 | case OMAP_DSS_CHANNEL_LCD2: | |
105 | return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC; | |
106 | default: | |
107 | /* this shouldn't happen */ | |
108 | WARN_ON(1); | |
109 | return OMAP_DSS_CLK_SRC_FCK; | |
110 | } | |
7636b3b4 AT |
111 | } |
112 | ||
100c8262 TV |
113 | struct dpi_clk_calc_ctx { |
114 | struct platform_device *dsidev; | |
115 | ||
116 | /* inputs */ | |
117 | ||
118 | unsigned long pck_min, pck_max; | |
119 | ||
120 | /* outputs */ | |
121 | ||
122 | struct dsi_clock_info dsi_cinfo; | |
c56812fc | 123 | unsigned long fck; |
100c8262 TV |
124 | struct dispc_clock_info dispc_cinfo; |
125 | }; | |
126 | ||
127 | static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
128 | unsigned long pck, void *data) | |
129 | { | |
130 | struct dpi_clk_calc_ctx *ctx = data; | |
131 | ||
132 | /* | |
133 | * Odd dividers give us uneven duty cycle, causing problem when level | |
134 | * shifted. So skip all odd dividers when the pixel clock is on the | |
135 | * higher side. | |
136 | */ | |
72e5512a | 137 | if (ctx->pck_min >= 100000000) { |
100c8262 TV |
138 | if (lckd > 1 && lckd % 2 != 0) |
139 | return false; | |
140 | ||
141 | if (pckd > 1 && pckd % 2 != 0) | |
142 | return false; | |
143 | } | |
144 | ||
145 | ctx->dispc_cinfo.lck_div = lckd; | |
146 | ctx->dispc_cinfo.pck_div = pckd; | |
147 | ctx->dispc_cinfo.lck = lck; | |
148 | ctx->dispc_cinfo.pck = pck; | |
149 | ||
150 | return true; | |
151 | } | |
152 | ||
153 | ||
154 | static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc, | |
155 | void *data) | |
156 | { | |
157 | struct dpi_clk_calc_ctx *ctx = data; | |
158 | ||
159 | /* | |
160 | * Odd dividers give us uneven duty cycle, causing problem when level | |
161 | * shifted. So skip all odd dividers when the pixel clock is on the | |
162 | * higher side. | |
163 | */ | |
72e5512a | 164 | if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000) |
100c8262 TV |
165 | return false; |
166 | ||
167 | ctx->dsi_cinfo.regm_dispc = regm_dispc; | |
168 | ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc; | |
169 | ||
170 | return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max, | |
171 | dpi_calc_dispc_cb, ctx); | |
172 | } | |
173 | ||
174 | ||
175 | static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint, | |
176 | unsigned long pll, | |
177 | void *data) | |
178 | { | |
179 | struct dpi_clk_calc_ctx *ctx = data; | |
180 | ||
181 | ctx->dsi_cinfo.regn = regn; | |
182 | ctx->dsi_cinfo.regm = regm; | |
183 | ctx->dsi_cinfo.fint = fint; | |
184 | ctx->dsi_cinfo.clkin4ddr = pll; | |
185 | ||
186 | return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min, | |
187 | dpi_calc_hsdiv_cb, ctx); | |
188 | } | |
189 | ||
d0f58bd3 | 190 | static bool dpi_calc_dss_cb(unsigned long fck, void *data) |
100c8262 TV |
191 | { |
192 | struct dpi_clk_calc_ctx *ctx = data; | |
193 | ||
d0f58bd3 | 194 | ctx->fck = fck; |
100c8262 TV |
195 | |
196 | return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, | |
197 | dpi_calc_dispc_cb, ctx); | |
198 | } | |
199 | ||
200 | static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx) | |
201 | { | |
202 | unsigned long clkin; | |
203 | unsigned long pll_min, pll_max; | |
204 | ||
205 | clkin = dsi_get_pll_clkin(dpi.dsidev); | |
206 | ||
207 | memset(ctx, 0, sizeof(*ctx)); | |
208 | ctx->dsidev = dpi.dsidev; | |
209 | ctx->pck_min = pck - 1000; | |
210 | ctx->pck_max = pck + 1000; | |
211 | ctx->dsi_cinfo.clkin = clkin; | |
212 | ||
213 | pll_min = 0; | |
214 | pll_max = 0; | |
215 | ||
216 | return dsi_pll_calc(dpi.dsidev, clkin, | |
217 | pll_min, pll_max, | |
218 | dpi_calc_pll_cb, ctx); | |
219 | } | |
220 | ||
221 | static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx) | |
222 | { | |
223 | int i; | |
224 | ||
225 | /* | |
226 | * DSS fck gives us very few possibilities, so finding a good pixel | |
227 | * clock may not be possible. We try multiple times to find the clock, | |
228 | * each time widening the pixel clock range we look for, up to | |
2c6360fb | 229 | * +/- ~15MHz. |
100c8262 TV |
230 | */ |
231 | ||
2c6360fb | 232 | for (i = 0; i < 25; ++i) { |
100c8262 TV |
233 | bool ok; |
234 | ||
235 | memset(ctx, 0, sizeof(*ctx)); | |
236 | if (pck > 1000 * i * i * i) | |
237 | ctx->pck_min = max(pck - 1000 * i * i * i, 0lu); | |
238 | else | |
239 | ctx->pck_min = 0; | |
240 | ctx->pck_max = pck + 1000 * i * i * i; | |
241 | ||
688af02d | 242 | ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx); |
100c8262 TV |
243 | if (ok) |
244 | return ok; | |
245 | } | |
246 | ||
247 | return false; | |
248 | } | |
249 | ||
250 | ||
251 | ||
03a0d1e8 | 252 | static int dpi_set_dsi_clk(enum omap_channel channel, |
ff1b2cde SS |
253 | unsigned long pck_req, unsigned long *fck, int *lck_div, |
254 | int *pck_div) | |
553c48cf | 255 | { |
100c8262 | 256 | struct dpi_clk_calc_ctx ctx; |
553c48cf | 257 | int r; |
100c8262 | 258 | bool ok; |
553c48cf | 259 | |
100c8262 TV |
260 | ok = dpi_dsi_clk_calc(pck_req, &ctx); |
261 | if (!ok) | |
262 | return -EINVAL; | |
553c48cf | 263 | |
100c8262 | 264 | r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo); |
553c48cf TV |
265 | if (r) |
266 | return r; | |
267 | ||
03a0d1e8 TV |
268 | dss_select_lcd_clk_source(channel, |
269 | dpi_get_alt_clk_src(channel)); | |
553c48cf | 270 | |
100c8262 | 271 | dpi.mgr_config.clock_info = ctx.dispc_cinfo; |
553c48cf | 272 | |
100c8262 TV |
273 | *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk; |
274 | *lck_div = ctx.dispc_cinfo.lck_div; | |
275 | *pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf TV |
276 | |
277 | return 0; | |
278 | } | |
7636b3b4 | 279 | |
03a0d1e8 TV |
280 | static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck, |
281 | int *lck_div, int *pck_div) | |
553c48cf | 282 | { |
100c8262 | 283 | struct dpi_clk_calc_ctx ctx; |
553c48cf | 284 | int r; |
100c8262 | 285 | bool ok; |
553c48cf | 286 | |
100c8262 TV |
287 | ok = dpi_dss_clk_calc(pck_req, &ctx); |
288 | if (!ok) | |
289 | return -EINVAL; | |
553c48cf | 290 | |
d0f58bd3 | 291 | r = dss_set_fck_rate(ctx.fck); |
553c48cf TV |
292 | if (r) |
293 | return r; | |
294 | ||
100c8262 | 295 | dpi.mgr_config.clock_info = ctx.dispc_cinfo; |
553c48cf | 296 | |
d0f58bd3 | 297 | *fck = ctx.fck; |
100c8262 TV |
298 | *lck_div = ctx.dispc_cinfo.lck_div; |
299 | *pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf TV |
300 | |
301 | return 0; | |
302 | } | |
553c48cf | 303 | |
03a0d1e8 | 304 | static int dpi_set_mode(struct omap_overlay_manager *mgr) |
553c48cf | 305 | { |
c499144c | 306 | struct omap_video_timings *t = &dpi.timings; |
7636b3b4 AT |
307 | int lck_div = 0, pck_div = 0; |
308 | unsigned long fck = 0; | |
553c48cf | 309 | unsigned long pck; |
553c48cf TV |
310 | int r = 0; |
311 | ||
8a3db406 | 312 | if (dpi.dsidev) |
d8d78941 | 313 | r = dpi_set_dsi_clk(mgr->id, t->pixelclock, &fck, |
6d523e7b | 314 | &lck_div, &pck_div); |
7636b3b4 | 315 | else |
d8d78941 | 316 | r = dpi_set_dispc_clk(t->pixelclock, &fck, |
6d523e7b | 317 | &lck_div, &pck_div); |
553c48cf | 318 | if (r) |
4fbafaf3 | 319 | return r; |
553c48cf | 320 | |
d8d78941 | 321 | pck = fck / lck_div / pck_div; |
553c48cf | 322 | |
d8d78941 TV |
323 | if (pck != t->pixelclock) { |
324 | DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n", | |
325 | t->pixelclock, pck); | |
553c48cf | 326 | |
d8d78941 | 327 | t->pixelclock = pck; |
553c48cf TV |
328 | } |
329 | ||
5d512fcd | 330 | dss_mgr_set_timings(mgr, t); |
553c48cf | 331 | |
4fbafaf3 | 332 | return 0; |
553c48cf TV |
333 | } |
334 | ||
03a0d1e8 | 335 | static void dpi_config_lcd_manager(struct omap_overlay_manager *mgr) |
553c48cf | 336 | { |
5cf9a264 | 337 | dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; |
569969d6 | 338 | |
5cf9a264 AT |
339 | dpi.mgr_config.stallmode = false; |
340 | dpi.mgr_config.fifohandcheck = false; | |
341 | ||
c6b393d4 | 342 | dpi.mgr_config.video_port_width = dpi.data_lines; |
5cf9a264 AT |
343 | |
344 | dpi.mgr_config.lcden_sig_polarity = 0; | |
345 | ||
5d512fcd | 346 | dss_mgr_set_lcd_config(mgr, &dpi.mgr_config); |
553c48cf TV |
347 | } |
348 | ||
86a3efe1 | 349 | static int dpi_display_enable(struct omap_dss_device *dssdev) |
553c48cf | 350 | { |
1f68d9c4 | 351 | struct omap_dss_device *out = &dpi.output; |
553c48cf TV |
352 | int r; |
353 | ||
c8a5e4e8 AT |
354 | mutex_lock(&dpi.lock); |
355 | ||
195e672a | 356 | if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi.vdds_dsi_reg) { |
40410715 | 357 | DSSERR("no VDSS_DSI regulator\n"); |
c8a5e4e8 AT |
358 | r = -ENODEV; |
359 | goto err_no_reg; | |
40410715 RK |
360 | } |
361 | ||
5d512fcd AT |
362 | if (out == NULL || out->manager == NULL) { |
363 | DSSERR("failed to enable display: no output/manager\n"); | |
c8a5e4e8 | 364 | r = -ENODEV; |
5d512fcd | 365 | goto err_no_out_mgr; |
05e1d606 TV |
366 | } |
367 | ||
195e672a | 368 | if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) { |
8a2cfea8 TV |
369 | r = regulator_enable(dpi.vdds_dsi_reg); |
370 | if (r) | |
4fbafaf3 | 371 | goto err_reg_enable; |
8a2cfea8 TV |
372 | } |
373 | ||
4fbafaf3 | 374 | r = dispc_runtime_get(); |
553c48cf | 375 | if (r) |
4fbafaf3 TV |
376 | goto err_get_dispc; |
377 | ||
03a0d1e8 | 378 | r = dss_dpi_select_source(out->manager->id); |
de09e455 TV |
379 | if (r) |
380 | goto err_src_sel; | |
381 | ||
8a3db406 | 382 | if (dpi.dsidev) { |
4fbafaf3 TV |
383 | r = dsi_runtime_get(dpi.dsidev); |
384 | if (r) | |
385 | goto err_get_dsi; | |
386 | ||
a72b64b9 | 387 | r = dsi_pll_init(dpi.dsidev, 0, 1); |
7636b3b4 | 388 | if (r) |
4fbafaf3 | 389 | goto err_dsi_pll_init; |
7636b3b4 AT |
390 | } |
391 | ||
03a0d1e8 | 392 | r = dpi_set_mode(out->manager); |
553c48cf | 393 | if (r) |
4fbafaf3 | 394 | goto err_set_mode; |
553c48cf | 395 | |
03a0d1e8 | 396 | dpi_config_lcd_manager(out->manager); |
5cf9a264 | 397 | |
553c48cf TV |
398 | mdelay(2); |
399 | ||
5d512fcd | 400 | r = dss_mgr_enable(out->manager); |
33ca237f TV |
401 | if (r) |
402 | goto err_mgr_enable; | |
553c48cf | 403 | |
c8a5e4e8 AT |
404 | mutex_unlock(&dpi.lock); |
405 | ||
553c48cf TV |
406 | return 0; |
407 | ||
33ca237f | 408 | err_mgr_enable: |
4fbafaf3 | 409 | err_set_mode: |
8a3db406 | 410 | if (dpi.dsidev) |
19077a73 | 411 | dsi_pll_uninit(dpi.dsidev, true); |
4fbafaf3 | 412 | err_dsi_pll_init: |
8a3db406 | 413 | if (dpi.dsidev) |
4fbafaf3 TV |
414 | dsi_runtime_put(dpi.dsidev); |
415 | err_get_dsi: | |
de09e455 | 416 | err_src_sel: |
4fbafaf3 TV |
417 | dispc_runtime_put(); |
418 | err_get_dispc: | |
195e672a | 419 | if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) |
8a2cfea8 | 420 | regulator_disable(dpi.vdds_dsi_reg); |
4fbafaf3 | 421 | err_reg_enable: |
5d512fcd | 422 | err_no_out_mgr: |
c8a5e4e8 AT |
423 | err_no_reg: |
424 | mutex_unlock(&dpi.lock); | |
553c48cf TV |
425 | return r; |
426 | } | |
427 | ||
86a3efe1 | 428 | static void dpi_display_disable(struct omap_dss_device *dssdev) |
553c48cf | 429 | { |
03a0d1e8 | 430 | struct omap_overlay_manager *mgr = dpi.output.manager; |
5d512fcd | 431 | |
c8a5e4e8 AT |
432 | mutex_lock(&dpi.lock); |
433 | ||
5d512fcd | 434 | dss_mgr_disable(mgr); |
553c48cf | 435 | |
8a3db406 | 436 | if (dpi.dsidev) { |
a5b8399f | 437 | dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); |
a72b64b9 | 438 | dsi_pll_uninit(dpi.dsidev, true); |
4fbafaf3 | 439 | dsi_runtime_put(dpi.dsidev); |
7636b3b4 | 440 | } |
553c48cf | 441 | |
4fbafaf3 | 442 | dispc_runtime_put(); |
553c48cf | 443 | |
195e672a | 444 | if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) |
8a2cfea8 TV |
445 | regulator_disable(dpi.vdds_dsi_reg); |
446 | ||
c8a5e4e8 | 447 | mutex_unlock(&dpi.lock); |
553c48cf | 448 | } |
553c48cf | 449 | |
86a3efe1 | 450 | static void dpi_set_timings(struct omap_dss_device *dssdev, |
c499144c | 451 | struct omap_video_timings *timings) |
553c48cf TV |
452 | { |
453 | DSSDBG("dpi_set_timings\n"); | |
c8a5e4e8 AT |
454 | |
455 | mutex_lock(&dpi.lock); | |
456 | ||
c499144c | 457 | dpi.timings = *timings; |
c499144c | 458 | |
c8a5e4e8 | 459 | mutex_unlock(&dpi.lock); |
553c48cf TV |
460 | } |
461 | ||
0b24edb1 TV |
462 | static void dpi_get_timings(struct omap_dss_device *dssdev, |
463 | struct omap_video_timings *timings) | |
464 | { | |
465 | mutex_lock(&dpi.lock); | |
466 | ||
467 | *timings = dpi.timings; | |
468 | ||
469 | mutex_unlock(&dpi.lock); | |
470 | } | |
471 | ||
86a3efe1 | 472 | static int dpi_check_timings(struct omap_dss_device *dssdev, |
553c48cf TV |
473 | struct omap_video_timings *timings) |
474 | { | |
03a0d1e8 | 475 | struct omap_overlay_manager *mgr = dpi.output.manager; |
553c48cf TV |
476 | int lck_div, pck_div; |
477 | unsigned long fck; | |
478 | unsigned long pck; | |
100c8262 TV |
479 | struct dpi_clk_calc_ctx ctx; |
480 | bool ok; | |
553c48cf | 481 | |
8b095513 | 482 | if (mgr && !dispc_mgr_timings_ok(mgr->id, timings)) |
553c48cf TV |
483 | return -EINVAL; |
484 | ||
d8d78941 | 485 | if (timings->pixelclock == 0) |
553c48cf TV |
486 | return -EINVAL; |
487 | ||
8a3db406 | 488 | if (dpi.dsidev) { |
d8d78941 | 489 | ok = dpi_dsi_clk_calc(timings->pixelclock, &ctx); |
100c8262 TV |
490 | if (!ok) |
491 | return -EINVAL; | |
553c48cf | 492 | |
100c8262 | 493 | fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk; |
7636b3b4 | 494 | } else { |
d8d78941 | 495 | ok = dpi_dss_clk_calc(timings->pixelclock, &ctx); |
100c8262 TV |
496 | if (!ok) |
497 | return -EINVAL; | |
553c48cf | 498 | |
d0f58bd3 | 499 | fck = ctx.fck; |
553c48cf | 500 | } |
7636b3b4 | 501 | |
100c8262 TV |
502 | lck_div = ctx.dispc_cinfo.lck_div; |
503 | pck_div = ctx.dispc_cinfo.pck_div; | |
553c48cf | 504 | |
d8d78941 | 505 | pck = fck / lck_div / pck_div; |
553c48cf | 506 | |
d8d78941 | 507 | timings->pixelclock = pck; |
553c48cf TV |
508 | |
509 | return 0; | |
510 | } | |
553c48cf | 511 | |
86a3efe1 | 512 | static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines) |
c6b393d4 AT |
513 | { |
514 | mutex_lock(&dpi.lock); | |
515 | ||
516 | dpi.data_lines = data_lines; | |
517 | ||
518 | mutex_unlock(&dpi.lock); | |
519 | } | |
c6b393d4 | 520 | |
94cf394b | 521 | static int dpi_verify_dsi_pll(struct platform_device *dsidev) |
6061675b TV |
522 | { |
523 | int r; | |
524 | ||
525 | /* do initial setup with the PLL to see if it is operational */ | |
526 | ||
527 | r = dsi_runtime_get(dsidev); | |
528 | if (r) | |
529 | return r; | |
530 | ||
531 | r = dsi_pll_init(dsidev, 0, 1); | |
532 | if (r) { | |
533 | dsi_runtime_put(dsidev); | |
534 | return r; | |
535 | } | |
536 | ||
537 | dsi_pll_uninit(dsidev, true); | |
538 | dsi_runtime_put(dsidev); | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
2795f646 TV |
543 | static int dpi_init_regulator(void) |
544 | { | |
545 | struct regulator *vdds_dsi; | |
546 | ||
547 | if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) | |
548 | return 0; | |
549 | ||
550 | if (dpi.vdds_dsi_reg) | |
551 | return 0; | |
552 | ||
4123de21 | 553 | vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi"); |
2795f646 | 554 | if (IS_ERR(vdds_dsi)) { |
40359a9b TV |
555 | if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) |
556 | DSSERR("can't get VDDS_DSI regulator\n"); | |
4123de21 | 557 | return PTR_ERR(vdds_dsi); |
2795f646 TV |
558 | } |
559 | ||
560 | dpi.vdds_dsi_reg = vdds_dsi; | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
565 | static void dpi_init_pll(void) | |
566 | { | |
567 | struct platform_device *dsidev; | |
568 | ||
569 | if (dpi.dsidev) | |
570 | return; | |
571 | ||
572 | dsidev = dpi_get_dsidev(dpi.output.dispc_channel); | |
573 | if (!dsidev) | |
574 | return; | |
575 | ||
576 | if (dpi_verify_dsi_pll(dsidev)) { | |
577 | DSSWARN("DSI PLL not operational\n"); | |
578 | return; | |
579 | } | |
580 | ||
581 | dpi.dsidev = dsidev; | |
582 | } | |
583 | ||
2eea5ae6 TV |
584 | /* |
585 | * Return a hardcoded channel for the DPI output. This should work for | |
586 | * current use cases, but this can be later expanded to either resolve | |
587 | * the channel in some more dynamic manner, or get the channel as a user | |
588 | * parameter. | |
589 | */ | |
590 | static enum omap_channel dpi_get_channel(void) | |
591 | { | |
592 | switch (omapdss_get_version()) { | |
593 | case OMAPDSS_VER_OMAP24xx: | |
594 | case OMAPDSS_VER_OMAP34xx_ES1: | |
595 | case OMAPDSS_VER_OMAP34xx_ES3: | |
596 | case OMAPDSS_VER_OMAP3630: | |
597 | case OMAPDSS_VER_AM35xx: | |
598 | return OMAP_DSS_CHANNEL_LCD; | |
599 | ||
600 | case OMAPDSS_VER_OMAP4430_ES1: | |
601 | case OMAPDSS_VER_OMAP4430_ES2: | |
602 | case OMAPDSS_VER_OMAP4: | |
603 | return OMAP_DSS_CHANNEL_LCD2; | |
604 | ||
605 | case OMAPDSS_VER_OMAP5: | |
606 | return OMAP_DSS_CHANNEL_LCD3; | |
607 | ||
608 | default: | |
609 | DSSWARN("unsupported DSS version\n"); | |
610 | return OMAP_DSS_CHANNEL_LCD; | |
611 | } | |
612 | } | |
613 | ||
0b24edb1 TV |
614 | static int dpi_connect(struct omap_dss_device *dssdev, |
615 | struct omap_dss_device *dst) | |
616 | { | |
617 | struct omap_overlay_manager *mgr; | |
618 | int r; | |
619 | ||
620 | r = dpi_init_regulator(); | |
621 | if (r) | |
622 | return r; | |
623 | ||
624 | dpi_init_pll(); | |
625 | ||
626 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | |
627 | if (!mgr) | |
628 | return -ENODEV; | |
629 | ||
630 | r = dss_mgr_connect(mgr, dssdev); | |
631 | if (r) | |
632 | return r; | |
633 | ||
634 | r = omapdss_output_set_device(dssdev, dst); | |
635 | if (r) { | |
636 | DSSERR("failed to connect output to new device: %s\n", | |
637 | dst->name); | |
638 | dss_mgr_disconnect(mgr, dssdev); | |
639 | return r; | |
640 | } | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
645 | static void dpi_disconnect(struct omap_dss_device *dssdev, | |
646 | struct omap_dss_device *dst) | |
647 | { | |
9560dc10 | 648 | WARN_ON(dst != dssdev->dst); |
0b24edb1 | 649 | |
9560dc10 | 650 | if (dst != dssdev->dst) |
0b24edb1 TV |
651 | return; |
652 | ||
653 | omapdss_output_unset_device(dssdev); | |
654 | ||
655 | if (dssdev->manager) | |
656 | dss_mgr_disconnect(dssdev->manager, dssdev); | |
657 | } | |
658 | ||
659 | static const struct omapdss_dpi_ops dpi_ops = { | |
660 | .connect = dpi_connect, | |
661 | .disconnect = dpi_disconnect, | |
662 | ||
86a3efe1 TV |
663 | .enable = dpi_display_enable, |
664 | .disable = dpi_display_disable, | |
0b24edb1 TV |
665 | |
666 | .check_timings = dpi_check_timings, | |
86a3efe1 | 667 | .set_timings = dpi_set_timings, |
0b24edb1 TV |
668 | .get_timings = dpi_get_timings, |
669 | ||
86a3efe1 | 670 | .set_data_lines = dpi_set_data_lines, |
0b24edb1 TV |
671 | }; |
672 | ||
94cf394b | 673 | static void dpi_init_output(struct platform_device *pdev) |
81b87f51 | 674 | { |
1f68d9c4 | 675 | struct omap_dss_device *out = &dpi.output; |
81b87f51 | 676 | |
1f68d9c4 | 677 | out->dev = &pdev->dev; |
81b87f51 | 678 | out->id = OMAP_DSS_OUTPUT_DPI; |
1f68d9c4 | 679 | out->output_type = OMAP_DISPLAY_TYPE_DPI; |
7286a08f | 680 | out->name = "dpi.0"; |
2eea5ae6 | 681 | out->dispc_channel = dpi_get_channel(); |
0b24edb1 | 682 | out->ops.dpi = &dpi_ops; |
b7328e14 | 683 | out->owner = THIS_MODULE; |
81b87f51 | 684 | |
5d47dbc8 | 685 | omapdss_register_output(out); |
81b87f51 AT |
686 | } |
687 | ||
688 | static void __exit dpi_uninit_output(struct platform_device *pdev) | |
689 | { | |
1f68d9c4 | 690 | struct omap_dss_device *out = &dpi.output; |
81b87f51 | 691 | |
5d47dbc8 | 692 | omapdss_unregister_output(out); |
81b87f51 AT |
693 | } |
694 | ||
94cf394b | 695 | static int omap_dpi_probe(struct platform_device *pdev) |
38f3daf6 | 696 | { |
00df43b8 TV |
697 | dpi.pdev = pdev; |
698 | ||
c8a5e4e8 AT |
699 | mutex_init(&dpi.lock); |
700 | ||
81b87f51 AT |
701 | dpi_init_output(pdev); |
702 | ||
5f42f2ce TV |
703 | return 0; |
704 | } | |
705 | ||
6e7e8f06 | 706 | static int __exit omap_dpi_remove(struct platform_device *pdev) |
553c48cf | 707 | { |
81b87f51 AT |
708 | dpi_uninit_output(pdev); |
709 | ||
a57dd4fe | 710 | return 0; |
553c48cf TV |
711 | } |
712 | ||
a57dd4fe | 713 | static struct platform_driver omap_dpi_driver = { |
94cf394b | 714 | .probe = omap_dpi_probe, |
6e7e8f06 | 715 | .remove = __exit_p(omap_dpi_remove), |
a57dd4fe TV |
716 | .driver = { |
717 | .name = "omapdss_dpi", | |
718 | .owner = THIS_MODULE, | |
719 | }, | |
720 | }; | |
721 | ||
6e7e8f06 | 722 | int __init dpi_init_platform_driver(void) |
a57dd4fe | 723 | { |
94cf394b | 724 | return platform_driver_register(&omap_dpi_driver); |
a57dd4fe TV |
725 | } |
726 | ||
6e7e8f06 | 727 | void __exit dpi_uninit_platform_driver(void) |
a57dd4fe TV |
728 | { |
729 | platform_driver_unregister(&omap_dpi_driver); | |
730 | } | |
2ecef246 TV |
731 | |
732 | int __init dpi_init_port(struct platform_device *pdev, struct device_node *port) | |
733 | { | |
734 | struct device_node *ep; | |
735 | u32 datalines; | |
736 | int r; | |
737 | ||
738 | ep = omapdss_of_get_next_endpoint(port, NULL); | |
739 | if (!ep) | |
740 | return 0; | |
741 | ||
742 | r = of_property_read_u32(ep, "data-lines", &datalines); | |
743 | if (r) { | |
744 | DSSERR("failed to parse datalines\n"); | |
745 | goto err_datalines; | |
746 | } | |
747 | ||
748 | dpi.data_lines = datalines; | |
749 | ||
750 | of_node_put(ep); | |
751 | ||
752 | dpi.pdev = pdev; | |
753 | ||
754 | mutex_init(&dpi.lock); | |
755 | ||
756 | dpi_init_output(pdev); | |
757 | ||
758 | dpi.port_initialized = true; | |
759 | ||
760 | return 0; | |
761 | ||
762 | err_datalines: | |
763 | of_node_put(ep); | |
764 | ||
765 | return r; | |
766 | } | |
767 | ||
768 | void __exit dpi_uninit_port(void) | |
769 | { | |
770 | if (!dpi.port_initialized) | |
771 | return; | |
772 | ||
773 | dpi_uninit_output(dpi.pdev); | |
774 | } |