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OMAP: DSS2: Clean up for dpll4_m4_ck handling
[deliverable/linux.git] / drivers / video / omap2 / dss / dss.c
CommitLineData
559d6701
TV		 1/*
2 * linux/drivers/video/omap2/dss/dss.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DSS"
24
25#include <linux/kernel.h>
26#include <linux/io.h>
27#include <linux/err.h>
28#include <linux/delay.h>
559d6701
TV		 29#include <linux/seq_file.h>
30#include <linux/clk.h>
31
32#include <plat/display.h>
8b9cb3a8 33#include <plat/clock.h>
559d6701 34#include "dss.h"
6ec549e5 35#include "dss_features.h"
559d6701 36
559d6701
TV		 37#define DSS_SZ_REGS SZ_512
38
39struct dss_reg {
40 u16 idx;
41};
42
43#define DSS_REG(idx) ((const struct dss_reg) { idx })
44
45#define DSS_REVISION DSS_REG(0x0000)
46#define DSS_SYSCONFIG DSS_REG(0x0010)
47#define DSS_SYSSTATUS DSS_REG(0x0014)
48#define DSS_IRQSTATUS DSS_REG(0x0018)
49#define DSS_CONTROL DSS_REG(0x0040)
50#define DSS_SDI_CONTROL DSS_REG(0x0044)
51#define DSS_PLL_CONTROL DSS_REG(0x0048)
52#define DSS_SDI_STATUS DSS_REG(0x005C)
53
54#define REG_GET(idx, start, end) \
55 FLD_GET(dss_read_reg(idx), start, end)
56
57#define REG_FLD_MOD(idx, val, start, end) \
58 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
59
60static struct {
96c401bc 61 struct platform_device *pdev;
559d6701 62 void __iomem *base;
8b9cb3a8 63 int ctx_id;
559d6701
TV		 64
65 struct clk *dpll4_m4_ck;
8b9cb3a8 66 struct clk *dss_ick;
c7642f67
AT		 67 struct clk *dss_fck;
68 struct clk *dss_sys_clk;
69 struct clk *dss_tv_fck;
70 struct clk *dss_video_fck;
8b9cb3a8 71 unsigned num_clks_enabled;
559d6701
TV		 72
73 unsigned long cache_req_pck;
74 unsigned long cache_prate;
75 struct dss_clock_info cache_dss_cinfo;
76 struct dispc_clock_info cache_dispc_cinfo;
77
2f18c4d8
TV		 78 enum dss_clk_source dsi_clk_source;
79 enum dss_clk_source dispc_clk_source;
ea75159e 80 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
2f18c4d8 81
559d6701
TV		 82 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
83} dss;
84
235e7dba
TA		 85static const char * const dss_generic_clk_source_names[] = {
86 [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC",
87 [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI",
88 [DSS_CLK_SRC_FCK] = "DSS_FCK",
067a57e4
AT		 89};
90
8b9cb3a8
SG		 91static void dss_clk_enable_all_no_ctx(void);
92static void dss_clk_disable_all_no_ctx(void);
93static void dss_clk_enable_no_ctx(enum dss_clock clks);
94static void dss_clk_disable_no_ctx(enum dss_clock clks);
95
559d6701
TV		 96static int _omap_dss_wait_reset(void);
97
98static inline void dss_write_reg(const struct dss_reg idx, u32 val)
99{
100 __raw_writel(val, dss.base + idx.idx);
101}
102
103static inline u32 dss_read_reg(const struct dss_reg idx)
104{
105 return __raw_readl(dss.base + idx.idx);
106}
107
108#define SR(reg) \
109 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
110#define RR(reg) \
111 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
112
113void dss_save_context(void)
114{
115 if (cpu_is_omap24xx())
116 return;
117
118 SR(SYSCONFIG);
119 SR(CONTROL);
120
6ec549e5
TV		 121 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
122 OMAP_DISPLAY_TYPE_SDI) {
123 SR(SDI_CONTROL);
124 SR(PLL_CONTROL);
125 }
559d6701
TV		 126}
127
128void dss_restore_context(void)
129{
130 if (_omap_dss_wait_reset())
131 DSSERR("DSS not coming out of reset after sleep\n");
132
133 RR(SYSCONFIG);
134 RR(CONTROL);
135
6ec549e5
TV		 136 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
137 OMAP_DISPLAY_TYPE_SDI) {
138 RR(SDI_CONTROL);
139 RR(PLL_CONTROL);
140 }
559d6701
TV		 141}
142
143#undef SR
144#undef RR
145
146void dss_sdi_init(u8 datapairs)
147{
148 u32 l;
149
150 BUG_ON(datapairs > 3 || datapairs < 1);
151
152 l = dss_read_reg(DSS_SDI_CONTROL);
153 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
154 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
155 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
156 dss_write_reg(DSS_SDI_CONTROL, l);
157
158 l = dss_read_reg(DSS_PLL_CONTROL);
159 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
160 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
161 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
162 dss_write_reg(DSS_PLL_CONTROL, l);
163}
164
165int dss_sdi_enable(void)
166{
167 unsigned long timeout;
168
169 dispc_pck_free_enable(1);
170
171 /* Reset SDI PLL */
172 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
173 udelay(1); /* wait 2x PCLK */
174
175 /* Lock SDI PLL */
176 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
177
178 /* Waiting for PLL lock request to complete */
179 timeout = jiffies + msecs_to_jiffies(500);
180 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
181 if (time_after_eq(jiffies, timeout)) {
182 DSSERR("PLL lock request timed out\n");
183 goto err1;
184 }
185 }
186
187 /* Clearing PLL_GO bit */
188 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
189
190 /* Waiting for PLL to lock */
191 timeout = jiffies + msecs_to_jiffies(500);
192 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
193 if (time_after_eq(jiffies, timeout)) {
194 DSSERR("PLL lock timed out\n");
195 goto err1;
196 }
197 }
198
199 dispc_lcd_enable_signal(1);
200
201 /* Waiting for SDI reset to complete */
202 timeout = jiffies + msecs_to_jiffies(500);
203 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
204 if (time_after_eq(jiffies, timeout)) {
205 DSSERR("SDI reset timed out\n");
206 goto err2;
207 }
208 }
209
210 return 0;
211
212 err2:
213 dispc_lcd_enable_signal(0);
214 err1:
215 /* Reset SDI PLL */
216 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
217
218 dispc_pck_free_enable(0);
219
220 return -ETIMEDOUT;
221}
222
223void dss_sdi_disable(void)
224{
225 dispc_lcd_enable_signal(0);
226
227 dispc_pck_free_enable(0);
228
229 /* Reset SDI PLL */
230 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
231}
232
067a57e4
AT		 233const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
234{
235e7dba 235 return dss_generic_clk_source_names[clk_src];
067a57e4
AT		 236}
237
559d6701
TV		 238void dss_dump_clocks(struct seq_file *s)
239{
240 unsigned long dpll4_ck_rate;
241 unsigned long dpll4_m4_ck_rate;
0acf659f
TV		 242 const char *fclk_name, *fclk_real_name;
243 unsigned long fclk_rate;
559d6701 244
6af9cd14 245 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
559d6701 246
559d6701
TV		 247 seq_printf(s, "- DSS -\n");
248
0acf659f
TV		 249 fclk_name = dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK);
250 fclk_real_name = dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK);
251 fclk_rate = dss_clk_get_rate(DSS_CLK_FCK);
559d6701 252
0acf659f
TV		 253 if (dss.dpll4_m4_ck) {
254 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
255 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
256
257 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
258
259 if (cpu_is_omap3630())
260 seq_printf(s, "%s (%s) = %lu / %lu = %lu\n",
261 fclk_name, fclk_real_name,
262 dpll4_ck_rate,
263 dpll4_ck_rate / dpll4_m4_ck_rate,
264 fclk_rate);
265 else
266 seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
267 fclk_name, fclk_real_name,
268 dpll4_ck_rate,
269 dpll4_ck_rate / dpll4_m4_ck_rate,
270 fclk_rate);
271 } else {
272 seq_printf(s, "%s (%s) = %lu\n",
273 fclk_name, fclk_real_name,
274 fclk_rate);
275 }
559d6701 276
6af9cd14 277 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
559d6701
TV		 278}
279
280void dss_dump_regs(struct seq_file *s)
281{
282#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
283
6af9cd14 284 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
559d6701
TV		 285
286 DUMPREG(DSS_REVISION);
287 DUMPREG(DSS_SYSCONFIG);
288 DUMPREG(DSS_SYSSTATUS);
289 DUMPREG(DSS_IRQSTATUS);
290 DUMPREG(DSS_CONTROL);
6ec549e5
TV		 291
292 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
293 OMAP_DISPLAY_TYPE_SDI) {
294 DUMPREG(DSS_SDI_CONTROL);
295 DUMPREG(DSS_PLL_CONTROL);
296 DUMPREG(DSS_SDI_STATUS);
297 }
559d6701 298
6af9cd14 299 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
559d6701
TV		 300#undef DUMPREG
301}
302
2f18c4d8
TV		 303void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
304{
305 int b;
ea75159e 306 u8 start, end;
2f18c4d8 307
66534e8e
TA		 308 switch (clk_src) {
309 case DSS_CLK_SRC_FCK:
310 b = 0;
311 break;
312 case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
313 b = 1;
1bb47835 314 dsi_wait_pll_hsdiv_dispc_active();
66534e8e
TA		 315 break;
316 default:
317 BUG();
318 }
e406f907 319
ea75159e
TA		 320 dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
321
322 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
2f18c4d8
TV		 323
324 dss.dispc_clk_source = clk_src;
325}
326
327void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
559d6701 328{
2f18c4d8
TV		 329 int b;
330
66534e8e
TA		 331 switch (clk_src) {
332 case DSS_CLK_SRC_FCK:
333 b = 0;
334 break;
335 case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
336 b = 1;
1bb47835 337 dsi_wait_pll_hsdiv_dsi_active();
66534e8e
TA		 338 break;
339 default:
340 BUG();
341 }
e406f907 342
2f18c4d8
TV		 343 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
344
345 dss.dsi_clk_source = clk_src;
559d6701
TV		 346}
347
ea75159e
TA		 348void dss_select_lcd_clk_source(enum omap_channel channel,
349 enum dss_clk_source clk_src)
350{
351 int b, ix, pos;
352
353 if (!dss_has_feature(FEAT_LCD_CLK_SRC))
354 return;
355
356 switch (clk_src) {
357 case DSS_CLK_SRC_FCK:
358 b = 0;
359 break;
360 case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
361 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
362 b = 1;
363 dsi_wait_pll_hsdiv_dispc_active();
364 break;
365 default:
366 BUG();
367 }
368
369 pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
370 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
371
372 ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
373 dss.lcd_clk_source[ix] = clk_src;
374}
375
2f18c4d8 376enum dss_clk_source dss_get_dispc_clk_source(void)
559d6701 377{
2f18c4d8 378 return dss.dispc_clk_source;
559d6701
TV		 379}
380
2f18c4d8 381enum dss_clk_source dss_get_dsi_clk_source(void)
559d6701 382{
2f18c4d8 383 return dss.dsi_clk_source;
559d6701
TV		 384}
385
ea75159e
TA		 386enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
387{
388 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
389 return dss.lcd_clk_source[ix];
390}
391
559d6701
TV		 392/* calculate clock rates using dividers in cinfo */
393int dss_calc_clock_rates(struct dss_clock_info *cinfo)
394{
0acf659f
TV		 395 if (dss.dpll4_m4_ck) {
396 unsigned long prate;
559d6701 397
0acf659f
TV		 398 if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
399 cinfo->fck_div == 0)
400 return -EINVAL;
559d6701 401
0acf659f 402 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
559d6701 403
0acf659f
TV		 404 cinfo->fck = prate / cinfo->fck_div;
405 } else {
406 if (cinfo->fck_div != 0)
407 return -EINVAL;
408 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
409 }
559d6701
TV		 410
411 return 0;
412}
413
414int dss_set_clock_div(struct dss_clock_info *cinfo)
415{
0acf659f
TV		 416 if (dss.dpll4_m4_ck) {
417 unsigned long prate;
418 int r;
559d6701 419
559d6701
TV		 420 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
421 DSSDBG("dpll4_m4 = %ld\n", prate);
422
423 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
424 if (r)
425 return r;
0acf659f
TV		 426 } else {
427 if (cinfo->fck_div != 0)
428 return -EINVAL;
559d6701
TV		 429 }
430
431 DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
432
433 return 0;
434}
435
436int dss_get_clock_div(struct dss_clock_info *cinfo)
437{
6af9cd14 438 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
559d6701 439
0acf659f 440 if (dss.dpll4_m4_ck) {
559d6701 441 unsigned long prate;
0acf659f 442
559d6701 443 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
0acf659f 444
ac01bb7e
K		 445 if (cpu_is_omap3630())
446 cinfo->fck_div = prate / (cinfo->fck);
447 else
448 cinfo->fck_div = prate / (cinfo->fck / 2);
559d6701
TV		 449 } else {
450 cinfo->fck_div = 0;
451 }
452
453 return 0;
454}
455
456unsigned long dss_get_dpll4_rate(void)
457{
0acf659f 458 if (dss.dpll4_m4_ck)
559d6701
TV		 459 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
460 else
461 return 0;
462}
463
464int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
465 struct dss_clock_info *dss_cinfo,
466 struct dispc_clock_info *dispc_cinfo)
467{
468 unsigned long prate;
469 struct dss_clock_info best_dss;
470 struct dispc_clock_info best_dispc;
471
819d807c 472 unsigned long fck, max_dss_fck;
559d6701
TV		 473
474 u16 fck_div;
475
476 int match = 0;
477 int min_fck_per_pck;
478
479 prate = dss_get_dpll4_rate();
480
31ef8237 481 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
819d807c 482
6af9cd14 483 fck = dss_clk_get_rate(DSS_CLK_FCK);
559d6701
TV		 484 if (req_pck == dss.cache_req_pck &&
485 ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
486 dss.cache_dss_cinfo.fck == fck)) {
487 DSSDBG("dispc clock info found from cache.\n");
488 *dss_cinfo = dss.cache_dss_cinfo;
489 *dispc_cinfo = dss.cache_dispc_cinfo;
490 return 0;
491 }
492
493 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
494
495 if (min_fck_per_pck &&
819d807c 496 req_pck * min_fck_per_pck > max_dss_fck) {
559d6701
TV		 497 DSSERR("Requested pixel clock not possible with the current "
498 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
499 "the constraint off.\n");
500 min_fck_per_pck = 0;
501 }
502
503retry:
504 memset(&best_dss, 0, sizeof(best_dss));
505 memset(&best_dispc, 0, sizeof(best_dispc));
506
507 if (cpu_is_omap24xx()) {
508 struct dispc_clock_info cur_dispc;
509 /* XXX can we change the clock on omap2? */
6af9cd14 510 fck = dss_clk_get_rate(DSS_CLK_FCK);
559d6701
TV		 511 fck_div = 1;
512
513 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
514 match = 1;
515
516 best_dss.fck = fck;
517 best_dss.fck_div = fck_div;
518
519 best_dispc = cur_dispc;
520
521 goto found;
522 } else if (cpu_is_omap34xx()) {
ac01bb7e
K		 523 for (fck_div = (cpu_is_omap3630() ? 32 : 16);
524 fck_div > 0; --fck_div) {
559d6701
TV		 525 struct dispc_clock_info cur_dispc;
526
ac01bb7e
K		 527 if (cpu_is_omap3630())
528 fck = prate / fck_div;
529 else
530 fck = prate / fck_div * 2;
559d6701 531
819d807c 532 if (fck > max_dss_fck)
559d6701
TV		 533 continue;
534
535 if (min_fck_per_pck &&
536 fck < req_pck * min_fck_per_pck)
537 continue;
538
539 match = 1;
540
541 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
542
543 if (abs(cur_dispc.pck - req_pck) <
544 abs(best_dispc.pck - req_pck)) {
545
546 best_dss.fck = fck;
547 best_dss.fck_div = fck_div;
548
549 best_dispc = cur_dispc;
550
551 if (cur_dispc.pck == req_pck)
552 goto found;
553 }
554 }
555 } else {
556 BUG();
557 }
558
559found:
560 if (!match) {
561 if (min_fck_per_pck) {
562 DSSERR("Could not find suitable clock settings.\n"
563 "Turning FCK/PCK constraint off and"
564 "trying again.\n");
565 min_fck_per_pck = 0;
566 goto retry;
567 }
568
569 DSSERR("Could not find suitable clock settings.\n");
570
571 return -EINVAL;
572 }
573
574 if (dss_cinfo)
575 *dss_cinfo = best_dss;
576 if (dispc_cinfo)
577 *dispc_cinfo = best_dispc;
578
579 dss.cache_req_pck = req_pck;
580 dss.cache_prate = prate;
581 dss.cache_dss_cinfo = best_dss;
582 dss.cache_dispc_cinfo = best_dispc;
583
584 return 0;
585}
586
559d6701
TV		 587static int _omap_dss_wait_reset(void)
588{
24be78b3 589 int t = 0;
559d6701
TV		 590
591 while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
24be78b3 592 if (++t > 1000) {
559d6701
TV		 593 DSSERR("soft reset failed\n");
594 return -ENODEV;
595 }
24be78b3 596 udelay(1);
559d6701
TV		 597 }
598
599 return 0;
600}
601
602static int _omap_dss_reset(void)
603{
604 /* Soft reset */
605 REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
606 return _omap_dss_wait_reset();
607}
608
609void dss_set_venc_output(enum omap_dss_venc_type type)
610{
611 int l = 0;
612
613 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
614 l = 0;
615 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
616 l = 1;
617 else
618 BUG();
619
620 /* venc out selection. 0 = comp, 1 = svideo */
621 REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
622}
623
624void dss_set_dac_pwrdn_bgz(bool enable)
625{
626 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
627}
628
7ed024aa
M		 629void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
630{
631 REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
632}
633
42c9dee8 634static int dss_init(void)
559d6701
TV		 635{
636 int r;
637 u32 rev;
ea9da36a 638 struct resource *dss_mem;
0acf659f 639 struct clk *dpll4_m4_ck;
559d6701 640
ea9da36a
SG		 641 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
642 if (!dss_mem) {
643 DSSERR("can't get IORESOURCE_MEM DSS\n");
644 r = -EINVAL;
645 goto fail0;
646 }
647 dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
559d6701
TV		 648 if (!dss.base) {
649 DSSERR("can't ioremap DSS\n");
650 r = -ENOMEM;
651 goto fail0;
652 }
653
42c9dee8
TV		 654 /* disable LCD and DIGIT output. This seems to fix the synclost
655 * problem that we get, if the bootloader starts the DSS and
656 * the kernel resets it */
657 omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
658
659 /* We need to wait here a bit, otherwise we sometimes start to
660 * get synclost errors, and after that only power cycle will
661 * restore DSS functionality. I have no idea why this happens.
662 * And we have to wait _before_ resetting the DSS, but after
663 * enabling clocks.
664 */
665 msleep(50);
666
667 _omap_dss_reset();
559d6701
TV		 668
669 /* autoidle */
670 REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
671
672 /* Select DPLL */
673 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
674
675#ifdef CONFIG_OMAP2_DSS_VENC
676 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
677 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
678 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
679#endif
559d6701 680 if (cpu_is_omap34xx()) {
0acf659f
TV		 681 dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
682 if (IS_ERR(dpll4_m4_ck)) {
559d6701 683 DSSERR("Failed to get dpll4_m4_ck\n");
0acf659f 684 r = PTR_ERR(dpll4_m4_ck);
affe360d 685 goto fail1;
559d6701 686 }
0acf659f
TV		 687 } else { /* omap24xx */
688 dpll4_m4_ck = NULL;
559d6701
TV		 689 }
690
0acf659f
TV		 691 dss.dpll4_m4_ck = dpll4_m4_ck;
692
88134fa1
AT		 693 dss.dsi_clk_source = DSS_CLK_SRC_FCK;
694 dss.dispc_clk_source = DSS_CLK_SRC_FCK;
ea75159e
TA		 695 dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
696 dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
ce619e1f 697
559d6701
TV		 698 dss_save_context();
699
700 rev = dss_read_reg(DSS_REVISION);
701 printk(KERN_INFO "OMAP DSS rev %d.%d\n",
702 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
703
704 return 0;
705
559d6701
TV		 706fail1:
707 iounmap(dss.base);
708fail0:
709 return r;
710}
711
96c401bc 712static void dss_exit(void)
559d6701 713{
0acf659f 714 if (dss.dpll4_m4_ck)
559d6701
TV		 715 clk_put(dss.dpll4_m4_ck);
716
559d6701
TV		 717 iounmap(dss.base);
718}
719
8b9cb3a8
SG		 720/* CONTEXT */
721static int dss_get_ctx_id(void)
722{
723 struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
724 int r;
725
726 if (!pdata->board_data->get_last_off_on_transaction_id)
727 return 0;
728 r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
729 if (r < 0) {
730 dev_err(&dss.pdev->dev, "getting transaction ID failed, "
731 "will force context restore\n");
732 r = -1;
733 }
734 return r;
735}
736
737int dss_need_ctx_restore(void)
738{
739 int id = dss_get_ctx_id();
740
741 if (id < 0 || id != dss.ctx_id) {
742 DSSDBG("ctx id %d -> id %d\n",
743 dss.ctx_id, id);
744 dss.ctx_id = id;
745 return 1;
746 } else {
747 return 0;
748 }
749}
750
751static void save_all_ctx(void)
752{
753 DSSDBG("save context\n");
754
6af9cd14 755 dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
8b9cb3a8
SG		 756
757 dss_save_context();
758 dispc_save_context();
759#ifdef CONFIG_OMAP2_DSS_DSI
760 dsi_save_context();
761#endif
762
6af9cd14 763 dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
8b9cb3a8
SG		 764}
765
766static void restore_all_ctx(void)
767{
768 DSSDBG("restore context\n");
769
770 dss_clk_enable_all_no_ctx();
771
772 dss_restore_context();
773 dispc_restore_context();
774#ifdef CONFIG_OMAP2_DSS_DSI
775 dsi_restore_context();
776#endif
777
778 dss_clk_disable_all_no_ctx();
779}
780
781static int dss_get_clock(struct clk **clock, const char *clk_name)
782{
783 struct clk *clk;
784
785 clk = clk_get(&dss.pdev->dev, clk_name);
786
787 if (IS_ERR(clk)) {
788 DSSERR("can't get clock %s", clk_name);
789 return PTR_ERR(clk);
790 }
791
792 *clock = clk;
793
794 DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
795
796 return 0;
797}
798
799static int dss_get_clocks(void)
800{
801 int r;
a1a0dcca 802 struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
8b9cb3a8
SG		 803
804 dss.dss_ick = NULL;
c7642f67
AT		 805 dss.dss_fck = NULL;
806 dss.dss_sys_clk = NULL;
807 dss.dss_tv_fck = NULL;
808 dss.dss_video_fck = NULL;
8b9cb3a8
SG		 809
810 r = dss_get_clock(&dss.dss_ick, "ick");
811 if (r)
812 goto err;
813
c7642f67 814 r = dss_get_clock(&dss.dss_fck, "fck");
8b9cb3a8
SG		 815 if (r)
816 goto err;
817
a1a0dcca
SS		 818 if (!pdata->opt_clock_available) {
819 r = -ENODEV;
8b9cb3a8 820 goto err;
a1a0dcca 821 }
8b9cb3a8 822
a1a0dcca
SS		 823 if (pdata->opt_clock_available("sys_clk")) {
824 r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
825 if (r)
826 goto err;
827 }
8b9cb3a8 828
a1a0dcca
SS		 829 if (pdata->opt_clock_available("tv_clk")) {
830 r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
831 if (r)
832 goto err;
833 }
834
835 if (pdata->opt_clock_available("video_clk")) {
836 r = dss_get_clock(&dss.dss_video_fck, "video_clk");
837 if (r)
838 goto err;
839 }
8b9cb3a8
SG		 840
841 return 0;
842
843err:
844 if (dss.dss_ick)
845 clk_put(dss.dss_ick);
c7642f67
AT		 846 if (dss.dss_fck)
847 clk_put(dss.dss_fck);
848 if (dss.dss_sys_clk)
849 clk_put(dss.dss_sys_clk);
850 if (dss.dss_tv_fck)
851 clk_put(dss.dss_tv_fck);
852 if (dss.dss_video_fck)
853 clk_put(dss.dss_video_fck);
8b9cb3a8
SG		 854
855 return r;
856}
857
858static void dss_put_clocks(void)
859{
c7642f67
AT		 860 if (dss.dss_video_fck)
861 clk_put(dss.dss_video_fck);
a1a0dcca
SS		 862 if (dss.dss_tv_fck)
863 clk_put(dss.dss_tv_fck);
864 if (dss.dss_sys_clk)
865 clk_put(dss.dss_sys_clk);
c7642f67 866 clk_put(dss.dss_fck);
8b9cb3a8
SG		 867 clk_put(dss.dss_ick);
868}
869
870unsigned long dss_clk_get_rate(enum dss_clock clk)
871{
872 switch (clk) {
873 case DSS_CLK_ICK:
874 return clk_get_rate(dss.dss_ick);
6af9cd14 875 case DSS_CLK_FCK:
c7642f67 876 return clk_get_rate(dss.dss_fck);
6af9cd14 877 case DSS_CLK_SYSCK:
c7642f67 878 return clk_get_rate(dss.dss_sys_clk);
6af9cd14 879 case DSS_CLK_TVFCK:
c7642f67 880 return clk_get_rate(dss.dss_tv_fck);
6af9cd14 881 case DSS_CLK_VIDFCK:
c7642f67 882 return clk_get_rate(dss.dss_video_fck);
8b9cb3a8
SG		 883 }
884
885 BUG();
886 return 0;
887}
888
889static unsigned count_clk_bits(enum dss_clock clks)
890{
891 unsigned num_clks = 0;
892
893 if (clks & DSS_CLK_ICK)
894 ++num_clks;
6af9cd14 895 if (clks & DSS_CLK_FCK)
8b9cb3a8 896 ++num_clks;
6af9cd14 897 if (clks & DSS_CLK_SYSCK)
8b9cb3a8 898 ++num_clks;
6af9cd14 899 if (clks & DSS_CLK_TVFCK)
8b9cb3a8 900 ++num_clks;
6af9cd14 901 if (clks & DSS_CLK_VIDFCK)
8b9cb3a8
SG		 902 ++num_clks;
903
904 return num_clks;
905}
906
907static void dss_clk_enable_no_ctx(enum dss_clock clks)
908{
909 unsigned num_clks = count_clk_bits(clks);
910
911 if (clks & DSS_CLK_ICK)
912 clk_enable(dss.dss_ick);
6af9cd14 913 if (clks & DSS_CLK_FCK)
c7642f67 914 clk_enable(dss.dss_fck);
a1a0dcca 915 if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
c7642f67 916 clk_enable(dss.dss_sys_clk);
a1a0dcca 917 if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
c7642f67 918 clk_enable(dss.dss_tv_fck);
a1a0dcca 919 if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
c7642f67 920 clk_enable(dss.dss_video_fck);
8b9cb3a8
SG		 921
922 dss.num_clks_enabled += num_clks;
923}
924
925void dss_clk_enable(enum dss_clock clks)
926{
927 bool check_ctx = dss.num_clks_enabled == 0;
928
929 dss_clk_enable_no_ctx(clks);
930
85604b0a
TV		 931 /*
932 * HACK: On omap4 the registers may not be accessible right after
933 * enabling the clocks. At some point this will be handled by
934 * pm_runtime, but for the time begin this should make things work.
935 */
936 if (cpu_is_omap44xx() && check_ctx)
937 udelay(10);
938
8b9cb3a8
SG		 939 if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
940 restore_all_ctx();
941}
942
943static void dss_clk_disable_no_ctx(enum dss_clock clks)
944{
945 unsigned num_clks = count_clk_bits(clks);
946
947 if (clks & DSS_CLK_ICK)
948 clk_disable(dss.dss_ick);
6af9cd14 949 if (clks & DSS_CLK_FCK)
c7642f67 950 clk_disable(dss.dss_fck);
a1a0dcca 951 if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
c7642f67 952 clk_disable(dss.dss_sys_clk);
a1a0dcca 953 if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
c7642f67 954 clk_disable(dss.dss_tv_fck);
a1a0dcca 955 if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
c7642f67 956 clk_disable(dss.dss_video_fck);
8b9cb3a8
SG		 957
958 dss.num_clks_enabled -= num_clks;
959}
960
961void dss_clk_disable(enum dss_clock clks)
962{
963 if (cpu_is_omap34xx()) {
964 unsigned num_clks = count_clk_bits(clks);
965
966 BUG_ON(dss.num_clks_enabled < num_clks);
967
968 if (dss.num_clks_enabled == num_clks)
969 save_all_ctx();
970 }
971
972 dss_clk_disable_no_ctx(clks);
973}
974
975static void dss_clk_enable_all_no_ctx(void)
976{
977 enum dss_clock clks;
978
6af9cd14 979 clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
8b9cb3a8 980 if (cpu_is_omap34xx())
6af9cd14 981 clks |= DSS_CLK_VIDFCK;
8b9cb3a8
SG		 982 dss_clk_enable_no_ctx(clks);
983}
984
985static void dss_clk_disable_all_no_ctx(void)
986{
987 enum dss_clock clks;
988
6af9cd14 989 clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
8b9cb3a8 990 if (cpu_is_omap34xx())
6af9cd14 991 clks |= DSS_CLK_VIDFCK;
8b9cb3a8
SG		 992 dss_clk_disable_no_ctx(clks);
993}
994
995#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
996/* CLOCKS */
997static void core_dump_clocks(struct seq_file *s)
998{
999 int i;
1000 struct clk *clocks[5] = {
1001 dss.dss_ick,
c7642f67
AT		 1002 dss.dss_fck,
1003 dss.dss_sys_clk,
1004 dss.dss_tv_fck,
1005 dss.dss_video_fck
8b9cb3a8
SG		 1006 };
1007
1008 seq_printf(s, "- CORE -\n");
1009
1010 seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
1011
1012 for (i = 0; i < 5; i++) {
1013 if (!clocks[i])
1014 continue;
1015 seq_printf(s, "%-15s\t%lu\t%d\n",
1016 clocks[i]->name,
1017 clk_get_rate(clocks[i]),
1018 clocks[i]->usecount);
1019 }
1020}
1021#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
1022
1023/* DEBUGFS */
1024#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
1025void dss_debug_dump_clocks(struct seq_file *s)
1026{
1027 core_dump_clocks(s);
1028 dss_dump_clocks(s);
1029 dispc_dump_clocks(s);
1030#ifdef CONFIG_OMAP2_DSS_DSI
1031 dsi_dump_clocks(s);
1032#endif
1033}
1034#endif
1035
1036
96c401bc
SG		 1037/* DSS HW IP initialisation */
1038static int omap_dsshw_probe(struct platform_device *pdev)
1039{
1040 int r;
96c401bc
SG		 1041
1042 dss.pdev = pdev;
1043
8b9cb3a8
SG		 1044 r = dss_get_clocks();
1045 if (r)
1046 goto err_clocks;
1047
1048 dss_clk_enable_all_no_ctx();
1049
1050 dss.ctx_id = dss_get_ctx_id();
1051 DSSDBG("initial ctx id %u\n", dss.ctx_id);
1052
42c9dee8 1053 r = dss_init();
96c401bc
SG		 1054 if (r) {
1055 DSSERR("Failed to initialize DSS\n");
1056 goto err_dss;
1057 }
1058
587b5e82
TV		 1059 r = dpi_init();
1060 if (r) {
1061 DSSERR("Failed to initialize DPI\n");
1062 goto err_dpi;
1063 }
1064
1065 r = sdi_init();
1066 if (r) {
1067 DSSERR("Failed to initialize SDI\n");
1068 goto err_sdi;
1069 }
1070
8b9cb3a8
SG		 1071 dss_clk_disable_all_no_ctx();
1072 return 0;
587b5e82
TV		 1073err_sdi:
1074 dpi_exit();
1075err_dpi:
1076 dss_exit();
8b9cb3a8
SG		 1077err_dss:
1078 dss_clk_disable_all_no_ctx();
1079 dss_put_clocks();
1080err_clocks:
96c401bc
SG		 1081 return r;
1082}
1083
1084static int omap_dsshw_remove(struct platform_device *pdev)
1085{
8b9cb3a8 1086
96c401bc
SG		 1087 dss_exit();
1088
8b9cb3a8
SG		 1089 /*
1090 * As part of hwmod changes, DSS is not the only controller of dss
1091 * clocks; hwmod framework itself will also enable clocks during hwmod
1092 * init for dss, and autoidle is set in h/w for DSS. Hence, there's no
1093 * need to disable clocks if their usecounts > 1.
1094 */
1095 WARN_ON(dss.num_clks_enabled > 0);
1096
1097 dss_put_clocks();
96c401bc
SG		 1098 return 0;
1099}
1100
1101static struct platform_driver omap_dsshw_driver = {
1102 .probe = omap_dsshw_probe,
1103 .remove = omap_dsshw_remove,
1104 .driver = {
1105 .name = "omapdss_dss",
1106 .owner = THIS_MODULE,
1107 },
1108};
1109
1110int dss_init_platform_driver(void)
1111{
1112 return platform_driver_register(&omap_dsshw_driver);
1113}
1114
1115void dss_uninit_platform_driver(void)
1116{
1117 return platform_driver_unregister(&omap_dsshw_driver);
1118}
Linux kernel - Deliverables
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