Commit | Line | Data |
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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dss.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DSS" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/delay.h> | |
559d6701 TV |
29 | #include <linux/seq_file.h> |
30 | #include <linux/clk.h> | |
31 | ||
a0b38cc4 | 32 | #include <video/omapdss.h> |
8b9cb3a8 | 33 | #include <plat/clock.h> |
559d6701 | 34 | #include "dss.h" |
6ec549e5 | 35 | #include "dss_features.h" |
559d6701 | 36 | |
559d6701 TV |
37 | #define DSS_SZ_REGS SZ_512 |
38 | ||
39 | struct dss_reg { | |
40 | u16 idx; | |
41 | }; | |
42 | ||
43 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) | |
44 | ||
45 | #define DSS_REVISION DSS_REG(0x0000) | |
46 | #define DSS_SYSCONFIG DSS_REG(0x0010) | |
47 | #define DSS_SYSSTATUS DSS_REG(0x0014) | |
559d6701 TV |
48 | #define DSS_CONTROL DSS_REG(0x0040) |
49 | #define DSS_SDI_CONTROL DSS_REG(0x0044) | |
50 | #define DSS_PLL_CONTROL DSS_REG(0x0048) | |
51 | #define DSS_SDI_STATUS DSS_REG(0x005C) | |
52 | ||
53 | #define REG_GET(idx, start, end) \ | |
54 | FLD_GET(dss_read_reg(idx), start, end) | |
55 | ||
56 | #define REG_FLD_MOD(idx, val, start, end) \ | |
57 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) | |
58 | ||
59 | static struct { | |
96c401bc | 60 | struct platform_device *pdev; |
559d6701 | 61 | void __iomem *base; |
8b9cb3a8 | 62 | int ctx_id; |
559d6701 TV |
63 | |
64 | struct clk *dpll4_m4_ck; | |
8b9cb3a8 | 65 | struct clk *dss_ick; |
c7642f67 AT |
66 | struct clk *dss_fck; |
67 | struct clk *dss_sys_clk; | |
68 | struct clk *dss_tv_fck; | |
69 | struct clk *dss_video_fck; | |
8b9cb3a8 | 70 | unsigned num_clks_enabled; |
559d6701 TV |
71 | |
72 | unsigned long cache_req_pck; | |
73 | unsigned long cache_prate; | |
74 | struct dss_clock_info cache_dss_cinfo; | |
75 | struct dispc_clock_info cache_dispc_cinfo; | |
76 | ||
89a35e51 AT |
77 | enum omap_dss_clk_source dsi_clk_source; |
78 | enum omap_dss_clk_source dispc_clk_source; | |
79 | enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; | |
2f18c4d8 | 80 | |
559d6701 TV |
81 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
82 | } dss; | |
83 | ||
235e7dba | 84 | static const char * const dss_generic_clk_source_names[] = { |
89a35e51 AT |
85 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", |
86 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", | |
87 | [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", | |
067a57e4 AT |
88 | }; |
89 | ||
8b9cb3a8 SG |
90 | static void dss_clk_enable_all_no_ctx(void); |
91 | static void dss_clk_disable_all_no_ctx(void); | |
92 | static void dss_clk_enable_no_ctx(enum dss_clock clks); | |
93 | static void dss_clk_disable_no_ctx(enum dss_clock clks); | |
94 | ||
559d6701 TV |
95 | static int _omap_dss_wait_reset(void); |
96 | ||
97 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) | |
98 | { | |
99 | __raw_writel(val, dss.base + idx.idx); | |
100 | } | |
101 | ||
102 | static inline u32 dss_read_reg(const struct dss_reg idx) | |
103 | { | |
104 | return __raw_readl(dss.base + idx.idx); | |
105 | } | |
106 | ||
107 | #define SR(reg) \ | |
108 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) | |
109 | #define RR(reg) \ | |
110 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) | |
111 | ||
112 | void dss_save_context(void) | |
113 | { | |
114 | if (cpu_is_omap24xx()) | |
115 | return; | |
116 | ||
117 | SR(SYSCONFIG); | |
118 | SR(CONTROL); | |
119 | ||
6ec549e5 TV |
120 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
121 | OMAP_DISPLAY_TYPE_SDI) { | |
122 | SR(SDI_CONTROL); | |
123 | SR(PLL_CONTROL); | |
124 | } | |
559d6701 TV |
125 | } |
126 | ||
127 | void dss_restore_context(void) | |
128 | { | |
129 | if (_omap_dss_wait_reset()) | |
130 | DSSERR("DSS not coming out of reset after sleep\n"); | |
131 | ||
132 | RR(SYSCONFIG); | |
133 | RR(CONTROL); | |
134 | ||
6ec549e5 TV |
135 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
136 | OMAP_DISPLAY_TYPE_SDI) { | |
137 | RR(SDI_CONTROL); | |
138 | RR(PLL_CONTROL); | |
139 | } | |
559d6701 TV |
140 | } |
141 | ||
142 | #undef SR | |
143 | #undef RR | |
144 | ||
145 | void dss_sdi_init(u8 datapairs) | |
146 | { | |
147 | u32 l; | |
148 | ||
149 | BUG_ON(datapairs > 3 || datapairs < 1); | |
150 | ||
151 | l = dss_read_reg(DSS_SDI_CONTROL); | |
152 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ | |
153 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ | |
154 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ | |
155 | dss_write_reg(DSS_SDI_CONTROL, l); | |
156 | ||
157 | l = dss_read_reg(DSS_PLL_CONTROL); | |
158 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ | |
159 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ | |
160 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ | |
161 | dss_write_reg(DSS_PLL_CONTROL, l); | |
162 | } | |
163 | ||
164 | int dss_sdi_enable(void) | |
165 | { | |
166 | unsigned long timeout; | |
167 | ||
168 | dispc_pck_free_enable(1); | |
169 | ||
170 | /* Reset SDI PLL */ | |
171 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ | |
172 | udelay(1); /* wait 2x PCLK */ | |
173 | ||
174 | /* Lock SDI PLL */ | |
175 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ | |
176 | ||
177 | /* Waiting for PLL lock request to complete */ | |
178 | timeout = jiffies + msecs_to_jiffies(500); | |
179 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { | |
180 | if (time_after_eq(jiffies, timeout)) { | |
181 | DSSERR("PLL lock request timed out\n"); | |
182 | goto err1; | |
183 | } | |
184 | } | |
185 | ||
186 | /* Clearing PLL_GO bit */ | |
187 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); | |
188 | ||
189 | /* Waiting for PLL to lock */ | |
190 | timeout = jiffies + msecs_to_jiffies(500); | |
191 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { | |
192 | if (time_after_eq(jiffies, timeout)) { | |
193 | DSSERR("PLL lock timed out\n"); | |
194 | goto err1; | |
195 | } | |
196 | } | |
197 | ||
198 | dispc_lcd_enable_signal(1); | |
199 | ||
200 | /* Waiting for SDI reset to complete */ | |
201 | timeout = jiffies + msecs_to_jiffies(500); | |
202 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { | |
203 | if (time_after_eq(jiffies, timeout)) { | |
204 | DSSERR("SDI reset timed out\n"); | |
205 | goto err2; | |
206 | } | |
207 | } | |
208 | ||
209 | return 0; | |
210 | ||
211 | err2: | |
212 | dispc_lcd_enable_signal(0); | |
213 | err1: | |
214 | /* Reset SDI PLL */ | |
215 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
216 | ||
217 | dispc_pck_free_enable(0); | |
218 | ||
219 | return -ETIMEDOUT; | |
220 | } | |
221 | ||
222 | void dss_sdi_disable(void) | |
223 | { | |
224 | dispc_lcd_enable_signal(0); | |
225 | ||
226 | dispc_pck_free_enable(0); | |
227 | ||
228 | /* Reset SDI PLL */ | |
229 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
230 | } | |
231 | ||
89a35e51 | 232 | const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) |
067a57e4 | 233 | { |
235e7dba | 234 | return dss_generic_clk_source_names[clk_src]; |
067a57e4 AT |
235 | } |
236 | ||
559d6701 TV |
237 | void dss_dump_clocks(struct seq_file *s) |
238 | { | |
239 | unsigned long dpll4_ck_rate; | |
240 | unsigned long dpll4_m4_ck_rate; | |
0acf659f TV |
241 | const char *fclk_name, *fclk_real_name; |
242 | unsigned long fclk_rate; | |
559d6701 | 243 | |
6af9cd14 | 244 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 | 245 | |
559d6701 TV |
246 | seq_printf(s, "- DSS -\n"); |
247 | ||
89a35e51 AT |
248 | fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
249 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); | |
0acf659f | 250 | fclk_rate = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 | 251 | |
0acf659f TV |
252 | if (dss.dpll4_m4_ck) { |
253 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | |
254 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); | |
255 | ||
256 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); | |
257 | ||
2de11086 | 258 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
0acf659f TV |
259 | seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", |
260 | fclk_name, fclk_real_name, | |
261 | dpll4_ck_rate, | |
262 | dpll4_ck_rate / dpll4_m4_ck_rate, | |
263 | fclk_rate); | |
264 | else | |
265 | seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", | |
266 | fclk_name, fclk_real_name, | |
267 | dpll4_ck_rate, | |
268 | dpll4_ck_rate / dpll4_m4_ck_rate, | |
269 | fclk_rate); | |
270 | } else { | |
271 | seq_printf(s, "%s (%s) = %lu\n", | |
272 | fclk_name, fclk_real_name, | |
273 | fclk_rate); | |
274 | } | |
559d6701 | 275 | |
6af9cd14 | 276 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
277 | } |
278 | ||
279 | void dss_dump_regs(struct seq_file *s) | |
280 | { | |
281 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) | |
282 | ||
6af9cd14 | 283 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
284 | |
285 | DUMPREG(DSS_REVISION); | |
286 | DUMPREG(DSS_SYSCONFIG); | |
287 | DUMPREG(DSS_SYSSTATUS); | |
559d6701 | 288 | DUMPREG(DSS_CONTROL); |
6ec549e5 TV |
289 | |
290 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & | |
291 | OMAP_DISPLAY_TYPE_SDI) { | |
292 | DUMPREG(DSS_SDI_CONTROL); | |
293 | DUMPREG(DSS_PLL_CONTROL); | |
294 | DUMPREG(DSS_SDI_STATUS); | |
295 | } | |
559d6701 | 296 | |
6af9cd14 | 297 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
298 | #undef DUMPREG |
299 | } | |
300 | ||
89a35e51 | 301 | void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src) |
2f18c4d8 TV |
302 | { |
303 | int b; | |
ea75159e | 304 | u8 start, end; |
2f18c4d8 | 305 | |
66534e8e | 306 | switch (clk_src) { |
89a35e51 | 307 | case OMAP_DSS_CLK_SRC_FCK: |
66534e8e TA |
308 | b = 0; |
309 | break; | |
89a35e51 | 310 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
66534e8e | 311 | b = 1; |
1bb47835 | 312 | dsi_wait_pll_hsdiv_dispc_active(); |
66534e8e TA |
313 | break; |
314 | default: | |
315 | BUG(); | |
316 | } | |
e406f907 | 317 | |
ea75159e TA |
318 | dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); |
319 | ||
320 | REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ | |
2f18c4d8 TV |
321 | |
322 | dss.dispc_clk_source = clk_src; | |
323 | } | |
324 | ||
89a35e51 | 325 | void dss_select_dsi_clk_source(enum omap_dss_clk_source clk_src) |
559d6701 | 326 | { |
2f18c4d8 TV |
327 | int b; |
328 | ||
66534e8e | 329 | switch (clk_src) { |
89a35e51 | 330 | case OMAP_DSS_CLK_SRC_FCK: |
66534e8e TA |
331 | b = 0; |
332 | break; | |
89a35e51 | 333 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: |
66534e8e | 334 | b = 1; |
1bb47835 | 335 | dsi_wait_pll_hsdiv_dsi_active(); |
66534e8e TA |
336 | break; |
337 | default: | |
338 | BUG(); | |
339 | } | |
e406f907 | 340 | |
2f18c4d8 TV |
341 | REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ |
342 | ||
343 | dss.dsi_clk_source = clk_src; | |
559d6701 TV |
344 | } |
345 | ||
ea75159e | 346 | void dss_select_lcd_clk_source(enum omap_channel channel, |
89a35e51 | 347 | enum omap_dss_clk_source clk_src) |
ea75159e TA |
348 | { |
349 | int b, ix, pos; | |
350 | ||
351 | if (!dss_has_feature(FEAT_LCD_CLK_SRC)) | |
352 | return; | |
353 | ||
354 | switch (clk_src) { | |
89a35e51 | 355 | case OMAP_DSS_CLK_SRC_FCK: |
ea75159e TA |
356 | b = 0; |
357 | break; | |
89a35e51 | 358 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
ea75159e TA |
359 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); |
360 | b = 1; | |
361 | dsi_wait_pll_hsdiv_dispc_active(); | |
362 | break; | |
363 | default: | |
364 | BUG(); | |
365 | } | |
366 | ||
367 | pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12; | |
368 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ | |
369 | ||
370 | ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; | |
371 | dss.lcd_clk_source[ix] = clk_src; | |
372 | } | |
373 | ||
89a35e51 | 374 | enum omap_dss_clk_source dss_get_dispc_clk_source(void) |
559d6701 | 375 | { |
2f18c4d8 | 376 | return dss.dispc_clk_source; |
559d6701 TV |
377 | } |
378 | ||
89a35e51 | 379 | enum omap_dss_clk_source dss_get_dsi_clk_source(void) |
559d6701 | 380 | { |
2f18c4d8 | 381 | return dss.dsi_clk_source; |
559d6701 TV |
382 | } |
383 | ||
89a35e51 | 384 | enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) |
ea75159e | 385 | { |
89976f29 AT |
386 | if (dss_has_feature(FEAT_LCD_CLK_SRC)) { |
387 | int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; | |
388 | return dss.lcd_clk_source[ix]; | |
389 | } else { | |
390 | /* LCD_CLK source is the same as DISPC_FCLK source for | |
391 | * OMAP2 and OMAP3 */ | |
392 | return dss.dispc_clk_source; | |
393 | } | |
ea75159e TA |
394 | } |
395 | ||
559d6701 TV |
396 | /* calculate clock rates using dividers in cinfo */ |
397 | int dss_calc_clock_rates(struct dss_clock_info *cinfo) | |
398 | { | |
0acf659f TV |
399 | if (dss.dpll4_m4_ck) { |
400 | unsigned long prate; | |
2de11086 | 401 | u16 fck_div_max = 16; |
559d6701 | 402 | |
2de11086 MR |
403 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
404 | fck_div_max = 32; | |
405 | ||
406 | if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0) | |
0acf659f | 407 | return -EINVAL; |
559d6701 | 408 | |
0acf659f | 409 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
559d6701 | 410 | |
0acf659f TV |
411 | cinfo->fck = prate / cinfo->fck_div; |
412 | } else { | |
413 | if (cinfo->fck_div != 0) | |
414 | return -EINVAL; | |
415 | cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); | |
416 | } | |
559d6701 TV |
417 | |
418 | return 0; | |
419 | } | |
420 | ||
421 | int dss_set_clock_div(struct dss_clock_info *cinfo) | |
422 | { | |
0acf659f TV |
423 | if (dss.dpll4_m4_ck) { |
424 | unsigned long prate; | |
425 | int r; | |
559d6701 | 426 | |
559d6701 TV |
427 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
428 | DSSDBG("dpll4_m4 = %ld\n", prate); | |
429 | ||
430 | r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); | |
431 | if (r) | |
432 | return r; | |
0acf659f TV |
433 | } else { |
434 | if (cinfo->fck_div != 0) | |
435 | return -EINVAL; | |
559d6701 TV |
436 | } |
437 | ||
438 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
443 | int dss_get_clock_div(struct dss_clock_info *cinfo) | |
444 | { | |
6af9cd14 | 445 | cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 | 446 | |
0acf659f | 447 | if (dss.dpll4_m4_ck) { |
559d6701 | 448 | unsigned long prate; |
0acf659f | 449 | |
559d6701 | 450 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
0acf659f | 451 | |
2de11086 | 452 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
ac01bb7e K |
453 | cinfo->fck_div = prate / (cinfo->fck); |
454 | else | |
455 | cinfo->fck_div = prate / (cinfo->fck / 2); | |
559d6701 TV |
456 | } else { |
457 | cinfo->fck_div = 0; | |
458 | } | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | unsigned long dss_get_dpll4_rate(void) | |
464 | { | |
0acf659f | 465 | if (dss.dpll4_m4_ck) |
559d6701 TV |
466 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
467 | else | |
468 | return 0; | |
469 | } | |
470 | ||
471 | int dss_calc_clock_div(bool is_tft, unsigned long req_pck, | |
472 | struct dss_clock_info *dss_cinfo, | |
473 | struct dispc_clock_info *dispc_cinfo) | |
474 | { | |
475 | unsigned long prate; | |
476 | struct dss_clock_info best_dss; | |
477 | struct dispc_clock_info best_dispc; | |
478 | ||
819d807c | 479 | unsigned long fck, max_dss_fck; |
559d6701 | 480 | |
2de11086 | 481 | u16 fck_div, fck_div_max = 16; |
559d6701 TV |
482 | |
483 | int match = 0; | |
484 | int min_fck_per_pck; | |
485 | ||
486 | prate = dss_get_dpll4_rate(); | |
487 | ||
31ef8237 | 488 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
819d807c | 489 | |
6af9cd14 | 490 | fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 TV |
491 | if (req_pck == dss.cache_req_pck && |
492 | ((cpu_is_omap34xx() && prate == dss.cache_prate) || | |
493 | dss.cache_dss_cinfo.fck == fck)) { | |
494 | DSSDBG("dispc clock info found from cache.\n"); | |
495 | *dss_cinfo = dss.cache_dss_cinfo; | |
496 | *dispc_cinfo = dss.cache_dispc_cinfo; | |
497 | return 0; | |
498 | } | |
499 | ||
500 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
501 | ||
502 | if (min_fck_per_pck && | |
819d807c | 503 | req_pck * min_fck_per_pck > max_dss_fck) { |
559d6701 TV |
504 | DSSERR("Requested pixel clock not possible with the current " |
505 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " | |
506 | "the constraint off.\n"); | |
507 | min_fck_per_pck = 0; | |
508 | } | |
509 | ||
510 | retry: | |
511 | memset(&best_dss, 0, sizeof(best_dss)); | |
512 | memset(&best_dispc, 0, sizeof(best_dispc)); | |
513 | ||
2de11086 | 514 | if (dss.dpll4_m4_ck == NULL) { |
559d6701 TV |
515 | struct dispc_clock_info cur_dispc; |
516 | /* XXX can we change the clock on omap2? */ | |
6af9cd14 | 517 | fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 TV |
518 | fck_div = 1; |
519 | ||
520 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); | |
521 | match = 1; | |
522 | ||
523 | best_dss.fck = fck; | |
524 | best_dss.fck_div = fck_div; | |
525 | ||
526 | best_dispc = cur_dispc; | |
527 | ||
528 | goto found; | |
2de11086 MR |
529 | } else { |
530 | if (cpu_is_omap3630() || cpu_is_omap44xx()) | |
531 | fck_div_max = 32; | |
532 | ||
533 | for (fck_div = fck_div_max; fck_div > 0; --fck_div) { | |
559d6701 TV |
534 | struct dispc_clock_info cur_dispc; |
535 | ||
2de11086 | 536 | if (fck_div_max == 32) |
ac01bb7e K |
537 | fck = prate / fck_div; |
538 | else | |
539 | fck = prate / fck_div * 2; | |
559d6701 | 540 | |
819d807c | 541 | if (fck > max_dss_fck) |
559d6701 TV |
542 | continue; |
543 | ||
544 | if (min_fck_per_pck && | |
545 | fck < req_pck * min_fck_per_pck) | |
546 | continue; | |
547 | ||
548 | match = 1; | |
549 | ||
550 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); | |
551 | ||
552 | if (abs(cur_dispc.pck - req_pck) < | |
553 | abs(best_dispc.pck - req_pck)) { | |
554 | ||
555 | best_dss.fck = fck; | |
556 | best_dss.fck_div = fck_div; | |
557 | ||
558 | best_dispc = cur_dispc; | |
559 | ||
560 | if (cur_dispc.pck == req_pck) | |
561 | goto found; | |
562 | } | |
563 | } | |
559d6701 TV |
564 | } |
565 | ||
566 | found: | |
567 | if (!match) { | |
568 | if (min_fck_per_pck) { | |
569 | DSSERR("Could not find suitable clock settings.\n" | |
570 | "Turning FCK/PCK constraint off and" | |
571 | "trying again.\n"); | |
572 | min_fck_per_pck = 0; | |
573 | goto retry; | |
574 | } | |
575 | ||
576 | DSSERR("Could not find suitable clock settings.\n"); | |
577 | ||
578 | return -EINVAL; | |
579 | } | |
580 | ||
581 | if (dss_cinfo) | |
582 | *dss_cinfo = best_dss; | |
583 | if (dispc_cinfo) | |
584 | *dispc_cinfo = best_dispc; | |
585 | ||
586 | dss.cache_req_pck = req_pck; | |
587 | dss.cache_prate = prate; | |
588 | dss.cache_dss_cinfo = best_dss; | |
589 | dss.cache_dispc_cinfo = best_dispc; | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
559d6701 TV |
594 | static int _omap_dss_wait_reset(void) |
595 | { | |
24be78b3 | 596 | int t = 0; |
559d6701 TV |
597 | |
598 | while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) { | |
24be78b3 | 599 | if (++t > 1000) { |
559d6701 TV |
600 | DSSERR("soft reset failed\n"); |
601 | return -ENODEV; | |
602 | } | |
24be78b3 | 603 | udelay(1); |
559d6701 TV |
604 | } |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
609 | static int _omap_dss_reset(void) | |
610 | { | |
611 | /* Soft reset */ | |
612 | REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); | |
613 | return _omap_dss_wait_reset(); | |
614 | } | |
615 | ||
616 | void dss_set_venc_output(enum omap_dss_venc_type type) | |
617 | { | |
618 | int l = 0; | |
619 | ||
620 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) | |
621 | l = 0; | |
622 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) | |
623 | l = 1; | |
624 | else | |
625 | BUG(); | |
626 | ||
627 | /* venc out selection. 0 = comp, 1 = svideo */ | |
628 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); | |
629 | } | |
630 | ||
631 | void dss_set_dac_pwrdn_bgz(bool enable) | |
632 | { | |
633 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ | |
634 | } | |
635 | ||
7ed024aa M |
636 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) |
637 | { | |
638 | REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ | |
639 | } | |
640 | ||
42c9dee8 | 641 | static int dss_init(void) |
559d6701 TV |
642 | { |
643 | int r; | |
644 | u32 rev; | |
ea9da36a | 645 | struct resource *dss_mem; |
0acf659f | 646 | struct clk *dpll4_m4_ck; |
559d6701 | 647 | |
ea9da36a SG |
648 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
649 | if (!dss_mem) { | |
650 | DSSERR("can't get IORESOURCE_MEM DSS\n"); | |
651 | r = -EINVAL; | |
652 | goto fail0; | |
653 | } | |
654 | dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); | |
559d6701 TV |
655 | if (!dss.base) { |
656 | DSSERR("can't ioremap DSS\n"); | |
657 | r = -ENOMEM; | |
658 | goto fail0; | |
659 | } | |
660 | ||
42c9dee8 TV |
661 | /* disable LCD and DIGIT output. This seems to fix the synclost |
662 | * problem that we get, if the bootloader starts the DSS and | |
663 | * the kernel resets it */ | |
664 | omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); | |
665 | ||
f1aafdcd | 666 | #ifdef CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET |
42c9dee8 TV |
667 | /* We need to wait here a bit, otherwise we sometimes start to |
668 | * get synclost errors, and after that only power cycle will | |
669 | * restore DSS functionality. I have no idea why this happens. | |
670 | * And we have to wait _before_ resetting the DSS, but after | |
671 | * enabling clocks. | |
f1aafdcd TV |
672 | * |
673 | * This bug was at least present on OMAP3430. It's unknown | |
674 | * if it happens on OMAP2 or OMAP3630. | |
42c9dee8 TV |
675 | */ |
676 | msleep(50); | |
f1aafdcd | 677 | #endif |
42c9dee8 TV |
678 | |
679 | _omap_dss_reset(); | |
559d6701 TV |
680 | |
681 | /* autoidle */ | |
682 | REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); | |
683 | ||
684 | /* Select DPLL */ | |
685 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); | |
686 | ||
687 | #ifdef CONFIG_OMAP2_DSS_VENC | |
688 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ | |
689 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ | |
690 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ | |
691 | #endif | |
559d6701 | 692 | if (cpu_is_omap34xx()) { |
0acf659f TV |
693 | dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); |
694 | if (IS_ERR(dpll4_m4_ck)) { | |
559d6701 | 695 | DSSERR("Failed to get dpll4_m4_ck\n"); |
0acf659f | 696 | r = PTR_ERR(dpll4_m4_ck); |
affe360d | 697 | goto fail1; |
559d6701 | 698 | } |
2de11086 MR |
699 | } else if (cpu_is_omap44xx()) { |
700 | dpll4_m4_ck = clk_get(NULL, "dpll_per_m5x2_ck"); | |
701 | if (IS_ERR(dpll4_m4_ck)) { | |
702 | DSSERR("Failed to get dpll4_m4_ck\n"); | |
703 | r = PTR_ERR(dpll4_m4_ck); | |
704 | goto fail1; | |
705 | } | |
0acf659f TV |
706 | } else { /* omap24xx */ |
707 | dpll4_m4_ck = NULL; | |
559d6701 TV |
708 | } |
709 | ||
0acf659f TV |
710 | dss.dpll4_m4_ck = dpll4_m4_ck; |
711 | ||
89a35e51 AT |
712 | dss.dsi_clk_source = OMAP_DSS_CLK_SRC_FCK; |
713 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; | |
714 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | |
715 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | |
ce619e1f | 716 | |
559d6701 TV |
717 | dss_save_context(); |
718 | ||
719 | rev = dss_read_reg(DSS_REVISION); | |
720 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", | |
721 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
722 | ||
723 | return 0; | |
724 | ||
559d6701 TV |
725 | fail1: |
726 | iounmap(dss.base); | |
727 | fail0: | |
728 | return r; | |
729 | } | |
730 | ||
96c401bc | 731 | static void dss_exit(void) |
559d6701 | 732 | { |
0acf659f | 733 | if (dss.dpll4_m4_ck) |
559d6701 TV |
734 | clk_put(dss.dpll4_m4_ck); |
735 | ||
559d6701 TV |
736 | iounmap(dss.base); |
737 | } | |
738 | ||
8b9cb3a8 SG |
739 | /* CONTEXT */ |
740 | static int dss_get_ctx_id(void) | |
741 | { | |
742 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; | |
743 | int r; | |
744 | ||
745 | if (!pdata->board_data->get_last_off_on_transaction_id) | |
746 | return 0; | |
747 | r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev); | |
748 | if (r < 0) { | |
749 | dev_err(&dss.pdev->dev, "getting transaction ID failed, " | |
750 | "will force context restore\n"); | |
751 | r = -1; | |
752 | } | |
753 | return r; | |
754 | } | |
755 | ||
756 | int dss_need_ctx_restore(void) | |
757 | { | |
758 | int id = dss_get_ctx_id(); | |
759 | ||
760 | if (id < 0 || id != dss.ctx_id) { | |
761 | DSSDBG("ctx id %d -> id %d\n", | |
762 | dss.ctx_id, id); | |
763 | dss.ctx_id = id; | |
764 | return 1; | |
765 | } else { | |
766 | return 0; | |
767 | } | |
768 | } | |
769 | ||
770 | static void save_all_ctx(void) | |
771 | { | |
772 | DSSDBG("save context\n"); | |
773 | ||
6af9cd14 | 774 | dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); |
8b9cb3a8 SG |
775 | |
776 | dss_save_context(); | |
777 | dispc_save_context(); | |
778 | #ifdef CONFIG_OMAP2_DSS_DSI | |
779 | dsi_save_context(); | |
780 | #endif | |
781 | ||
6af9cd14 | 782 | dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); |
8b9cb3a8 SG |
783 | } |
784 | ||
785 | static void restore_all_ctx(void) | |
786 | { | |
787 | DSSDBG("restore context\n"); | |
788 | ||
789 | dss_clk_enable_all_no_ctx(); | |
790 | ||
791 | dss_restore_context(); | |
792 | dispc_restore_context(); | |
793 | #ifdef CONFIG_OMAP2_DSS_DSI | |
794 | dsi_restore_context(); | |
795 | #endif | |
796 | ||
797 | dss_clk_disable_all_no_ctx(); | |
798 | } | |
799 | ||
800 | static int dss_get_clock(struct clk **clock, const char *clk_name) | |
801 | { | |
802 | struct clk *clk; | |
803 | ||
804 | clk = clk_get(&dss.pdev->dev, clk_name); | |
805 | ||
806 | if (IS_ERR(clk)) { | |
807 | DSSERR("can't get clock %s", clk_name); | |
808 | return PTR_ERR(clk); | |
809 | } | |
810 | ||
811 | *clock = clk; | |
812 | ||
813 | DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); | |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
818 | static int dss_get_clocks(void) | |
819 | { | |
820 | int r; | |
a1a0dcca | 821 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; |
8b9cb3a8 SG |
822 | |
823 | dss.dss_ick = NULL; | |
c7642f67 AT |
824 | dss.dss_fck = NULL; |
825 | dss.dss_sys_clk = NULL; | |
826 | dss.dss_tv_fck = NULL; | |
827 | dss.dss_video_fck = NULL; | |
8b9cb3a8 SG |
828 | |
829 | r = dss_get_clock(&dss.dss_ick, "ick"); | |
830 | if (r) | |
831 | goto err; | |
832 | ||
c7642f67 | 833 | r = dss_get_clock(&dss.dss_fck, "fck"); |
8b9cb3a8 SG |
834 | if (r) |
835 | goto err; | |
836 | ||
a1a0dcca SS |
837 | if (!pdata->opt_clock_available) { |
838 | r = -ENODEV; | |
8b9cb3a8 | 839 | goto err; |
a1a0dcca | 840 | } |
8b9cb3a8 | 841 | |
a1a0dcca SS |
842 | if (pdata->opt_clock_available("sys_clk")) { |
843 | r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); | |
844 | if (r) | |
845 | goto err; | |
846 | } | |
8b9cb3a8 | 847 | |
a1a0dcca SS |
848 | if (pdata->opt_clock_available("tv_clk")) { |
849 | r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); | |
850 | if (r) | |
851 | goto err; | |
852 | } | |
853 | ||
854 | if (pdata->opt_clock_available("video_clk")) { | |
855 | r = dss_get_clock(&dss.dss_video_fck, "video_clk"); | |
856 | if (r) | |
857 | goto err; | |
858 | } | |
8b9cb3a8 SG |
859 | |
860 | return 0; | |
861 | ||
862 | err: | |
863 | if (dss.dss_ick) | |
864 | clk_put(dss.dss_ick); | |
c7642f67 AT |
865 | if (dss.dss_fck) |
866 | clk_put(dss.dss_fck); | |
867 | if (dss.dss_sys_clk) | |
868 | clk_put(dss.dss_sys_clk); | |
869 | if (dss.dss_tv_fck) | |
870 | clk_put(dss.dss_tv_fck); | |
871 | if (dss.dss_video_fck) | |
872 | clk_put(dss.dss_video_fck); | |
8b9cb3a8 SG |
873 | |
874 | return r; | |
875 | } | |
876 | ||
877 | static void dss_put_clocks(void) | |
878 | { | |
c7642f67 AT |
879 | if (dss.dss_video_fck) |
880 | clk_put(dss.dss_video_fck); | |
a1a0dcca SS |
881 | if (dss.dss_tv_fck) |
882 | clk_put(dss.dss_tv_fck); | |
883 | if (dss.dss_sys_clk) | |
884 | clk_put(dss.dss_sys_clk); | |
c7642f67 | 885 | clk_put(dss.dss_fck); |
8b9cb3a8 SG |
886 | clk_put(dss.dss_ick); |
887 | } | |
888 | ||
889 | unsigned long dss_clk_get_rate(enum dss_clock clk) | |
890 | { | |
891 | switch (clk) { | |
892 | case DSS_CLK_ICK: | |
893 | return clk_get_rate(dss.dss_ick); | |
6af9cd14 | 894 | case DSS_CLK_FCK: |
c7642f67 | 895 | return clk_get_rate(dss.dss_fck); |
6af9cd14 | 896 | case DSS_CLK_SYSCK: |
c7642f67 | 897 | return clk_get_rate(dss.dss_sys_clk); |
6af9cd14 | 898 | case DSS_CLK_TVFCK: |
c7642f67 | 899 | return clk_get_rate(dss.dss_tv_fck); |
6af9cd14 | 900 | case DSS_CLK_VIDFCK: |
c7642f67 | 901 | return clk_get_rate(dss.dss_video_fck); |
8b9cb3a8 SG |
902 | } |
903 | ||
904 | BUG(); | |
905 | return 0; | |
906 | } | |
907 | ||
908 | static unsigned count_clk_bits(enum dss_clock clks) | |
909 | { | |
910 | unsigned num_clks = 0; | |
911 | ||
912 | if (clks & DSS_CLK_ICK) | |
913 | ++num_clks; | |
6af9cd14 | 914 | if (clks & DSS_CLK_FCK) |
8b9cb3a8 | 915 | ++num_clks; |
6af9cd14 | 916 | if (clks & DSS_CLK_SYSCK) |
8b9cb3a8 | 917 | ++num_clks; |
6af9cd14 | 918 | if (clks & DSS_CLK_TVFCK) |
8b9cb3a8 | 919 | ++num_clks; |
6af9cd14 | 920 | if (clks & DSS_CLK_VIDFCK) |
8b9cb3a8 SG |
921 | ++num_clks; |
922 | ||
923 | return num_clks; | |
924 | } | |
925 | ||
926 | static void dss_clk_enable_no_ctx(enum dss_clock clks) | |
927 | { | |
928 | unsigned num_clks = count_clk_bits(clks); | |
929 | ||
930 | if (clks & DSS_CLK_ICK) | |
931 | clk_enable(dss.dss_ick); | |
6af9cd14 | 932 | if (clks & DSS_CLK_FCK) |
c7642f67 | 933 | clk_enable(dss.dss_fck); |
a1a0dcca | 934 | if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) |
c7642f67 | 935 | clk_enable(dss.dss_sys_clk); |
a1a0dcca | 936 | if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) |
c7642f67 | 937 | clk_enable(dss.dss_tv_fck); |
a1a0dcca | 938 | if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) |
c7642f67 | 939 | clk_enable(dss.dss_video_fck); |
8b9cb3a8 SG |
940 | |
941 | dss.num_clks_enabled += num_clks; | |
942 | } | |
943 | ||
944 | void dss_clk_enable(enum dss_clock clks) | |
945 | { | |
946 | bool check_ctx = dss.num_clks_enabled == 0; | |
947 | ||
948 | dss_clk_enable_no_ctx(clks); | |
949 | ||
85604b0a TV |
950 | /* |
951 | * HACK: On omap4 the registers may not be accessible right after | |
952 | * enabling the clocks. At some point this will be handled by | |
953 | * pm_runtime, but for the time begin this should make things work. | |
954 | */ | |
955 | if (cpu_is_omap44xx() && check_ctx) | |
956 | udelay(10); | |
957 | ||
8b9cb3a8 SG |
958 | if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) |
959 | restore_all_ctx(); | |
960 | } | |
961 | ||
962 | static void dss_clk_disable_no_ctx(enum dss_clock clks) | |
963 | { | |
964 | unsigned num_clks = count_clk_bits(clks); | |
965 | ||
966 | if (clks & DSS_CLK_ICK) | |
967 | clk_disable(dss.dss_ick); | |
6af9cd14 | 968 | if (clks & DSS_CLK_FCK) |
c7642f67 | 969 | clk_disable(dss.dss_fck); |
a1a0dcca | 970 | if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) |
c7642f67 | 971 | clk_disable(dss.dss_sys_clk); |
a1a0dcca | 972 | if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) |
c7642f67 | 973 | clk_disable(dss.dss_tv_fck); |
a1a0dcca | 974 | if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) |
c7642f67 | 975 | clk_disable(dss.dss_video_fck); |
8b9cb3a8 SG |
976 | |
977 | dss.num_clks_enabled -= num_clks; | |
978 | } | |
979 | ||
980 | void dss_clk_disable(enum dss_clock clks) | |
981 | { | |
982 | if (cpu_is_omap34xx()) { | |
983 | unsigned num_clks = count_clk_bits(clks); | |
984 | ||
985 | BUG_ON(dss.num_clks_enabled < num_clks); | |
986 | ||
987 | if (dss.num_clks_enabled == num_clks) | |
988 | save_all_ctx(); | |
989 | } | |
990 | ||
991 | dss_clk_disable_no_ctx(clks); | |
992 | } | |
993 | ||
994 | static void dss_clk_enable_all_no_ctx(void) | |
995 | { | |
996 | enum dss_clock clks; | |
997 | ||
6af9cd14 | 998 | clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; |
8b9cb3a8 | 999 | if (cpu_is_omap34xx()) |
6af9cd14 | 1000 | clks |= DSS_CLK_VIDFCK; |
8b9cb3a8 SG |
1001 | dss_clk_enable_no_ctx(clks); |
1002 | } | |
1003 | ||
1004 | static void dss_clk_disable_all_no_ctx(void) | |
1005 | { | |
1006 | enum dss_clock clks; | |
1007 | ||
6af9cd14 | 1008 | clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; |
8b9cb3a8 | 1009 | if (cpu_is_omap34xx()) |
6af9cd14 | 1010 | clks |= DSS_CLK_VIDFCK; |
8b9cb3a8 SG |
1011 | dss_clk_disable_no_ctx(clks); |
1012 | } | |
1013 | ||
1014 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
1015 | /* CLOCKS */ | |
1016 | static void core_dump_clocks(struct seq_file *s) | |
1017 | { | |
1018 | int i; | |
1019 | struct clk *clocks[5] = { | |
1020 | dss.dss_ick, | |
c7642f67 AT |
1021 | dss.dss_fck, |
1022 | dss.dss_sys_clk, | |
1023 | dss.dss_tv_fck, | |
1024 | dss.dss_video_fck | |
8b9cb3a8 SG |
1025 | }; |
1026 | ||
ab46d8b2 TV |
1027 | const char *names[5] = { |
1028 | "ick", | |
1029 | "fck", | |
1030 | "sys_clk", | |
1031 | "tv_fck", | |
1032 | "video_fck" | |
1033 | }; | |
1034 | ||
8b9cb3a8 SG |
1035 | seq_printf(s, "- CORE -\n"); |
1036 | ||
1037 | seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled); | |
1038 | ||
1039 | for (i = 0; i < 5; i++) { | |
1040 | if (!clocks[i]) | |
1041 | continue; | |
ab46d8b2 TV |
1042 | seq_printf(s, "%s (%s)%*s\t%lu\t%d\n", |
1043 | names[i], | |
8b9cb3a8 | 1044 | clocks[i]->name, |
ab46d8b2 TV |
1045 | 24 - strlen(names[i]) - strlen(clocks[i]->name), |
1046 | "", | |
8b9cb3a8 SG |
1047 | clk_get_rate(clocks[i]), |
1048 | clocks[i]->usecount); | |
1049 | } | |
1050 | } | |
1051 | #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ | |
1052 | ||
1053 | /* DEBUGFS */ | |
1054 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
1055 | void dss_debug_dump_clocks(struct seq_file *s) | |
1056 | { | |
1057 | core_dump_clocks(s); | |
1058 | dss_dump_clocks(s); | |
1059 | dispc_dump_clocks(s); | |
1060 | #ifdef CONFIG_OMAP2_DSS_DSI | |
1061 | dsi_dump_clocks(s); | |
1062 | #endif | |
1063 | } | |
1064 | #endif | |
1065 | ||
1066 | ||
96c401bc SG |
1067 | /* DSS HW IP initialisation */ |
1068 | static int omap_dsshw_probe(struct platform_device *pdev) | |
1069 | { | |
1070 | int r; | |
96c401bc SG |
1071 | |
1072 | dss.pdev = pdev; | |
1073 | ||
8b9cb3a8 SG |
1074 | r = dss_get_clocks(); |
1075 | if (r) | |
1076 | goto err_clocks; | |
1077 | ||
1078 | dss_clk_enable_all_no_ctx(); | |
1079 | ||
1080 | dss.ctx_id = dss_get_ctx_id(); | |
1081 | DSSDBG("initial ctx id %u\n", dss.ctx_id); | |
1082 | ||
42c9dee8 | 1083 | r = dss_init(); |
96c401bc SG |
1084 | if (r) { |
1085 | DSSERR("Failed to initialize DSS\n"); | |
1086 | goto err_dss; | |
1087 | } | |
1088 | ||
587b5e82 TV |
1089 | r = dpi_init(); |
1090 | if (r) { | |
1091 | DSSERR("Failed to initialize DPI\n"); | |
1092 | goto err_dpi; | |
1093 | } | |
1094 | ||
1095 | r = sdi_init(); | |
1096 | if (r) { | |
1097 | DSSERR("Failed to initialize SDI\n"); | |
1098 | goto err_sdi; | |
1099 | } | |
1100 | ||
8b9cb3a8 SG |
1101 | dss_clk_disable_all_no_ctx(); |
1102 | return 0; | |
587b5e82 TV |
1103 | err_sdi: |
1104 | dpi_exit(); | |
1105 | err_dpi: | |
1106 | dss_exit(); | |
8b9cb3a8 SG |
1107 | err_dss: |
1108 | dss_clk_disable_all_no_ctx(); | |
1109 | dss_put_clocks(); | |
1110 | err_clocks: | |
96c401bc SG |
1111 | return r; |
1112 | } | |
1113 | ||
1114 | static int omap_dsshw_remove(struct platform_device *pdev) | |
1115 | { | |
8b9cb3a8 | 1116 | |
96c401bc SG |
1117 | dss_exit(); |
1118 | ||
8b9cb3a8 SG |
1119 | /* |
1120 | * As part of hwmod changes, DSS is not the only controller of dss | |
1121 | * clocks; hwmod framework itself will also enable clocks during hwmod | |
1122 | * init for dss, and autoidle is set in h/w for DSS. Hence, there's no | |
1123 | * need to disable clocks if their usecounts > 1. | |
1124 | */ | |
1125 | WARN_ON(dss.num_clks_enabled > 0); | |
1126 | ||
1127 | dss_put_clocks(); | |
96c401bc SG |
1128 | return 0; |
1129 | } | |
1130 | ||
1131 | static struct platform_driver omap_dsshw_driver = { | |
1132 | .probe = omap_dsshw_probe, | |
1133 | .remove = omap_dsshw_remove, | |
1134 | .driver = { | |
1135 | .name = "omapdss_dss", | |
1136 | .owner = THIS_MODULE, | |
1137 | }, | |
1138 | }; | |
1139 | ||
1140 | int dss_init_platform_driver(void) | |
1141 | { | |
1142 | return platform_driver_register(&omap_dsshw_driver); | |
1143 | } | |
1144 | ||
1145 | void dss_uninit_platform_driver(void) | |
1146 | { | |
1147 | return platform_driver_unregister(&omap_dsshw_driver); | |
1148 | } |