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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dss.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DSS" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/delay.h> | |
559d6701 TV |
29 | #include <linux/seq_file.h> |
30 | #include <linux/clk.h> | |
24e6289c | 31 | #include <linux/platform_device.h> |
559d6701 | 32 | |
a0b38cc4 | 33 | #include <video/omapdss.h> |
8b9cb3a8 | 34 | #include <plat/clock.h> |
559d6701 | 35 | #include "dss.h" |
6ec549e5 | 36 | #include "dss_features.h" |
559d6701 | 37 | |
559d6701 TV |
38 | #define DSS_SZ_REGS SZ_512 |
39 | ||
40 | struct dss_reg { | |
41 | u16 idx; | |
42 | }; | |
43 | ||
44 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) | |
45 | ||
46 | #define DSS_REVISION DSS_REG(0x0000) | |
47 | #define DSS_SYSCONFIG DSS_REG(0x0010) | |
48 | #define DSS_SYSSTATUS DSS_REG(0x0014) | |
559d6701 TV |
49 | #define DSS_CONTROL DSS_REG(0x0040) |
50 | #define DSS_SDI_CONTROL DSS_REG(0x0044) | |
51 | #define DSS_PLL_CONTROL DSS_REG(0x0048) | |
52 | #define DSS_SDI_STATUS DSS_REG(0x005C) | |
53 | ||
54 | #define REG_GET(idx, start, end) \ | |
55 | FLD_GET(dss_read_reg(idx), start, end) | |
56 | ||
57 | #define REG_FLD_MOD(idx, val, start, end) \ | |
58 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) | |
59 | ||
60 | static struct { | |
96c401bc | 61 | struct platform_device *pdev; |
559d6701 | 62 | void __iomem *base; |
8b9cb3a8 | 63 | int ctx_id; |
559d6701 TV |
64 | |
65 | struct clk *dpll4_m4_ck; | |
8b9cb3a8 | 66 | struct clk *dss_ick; |
c7642f67 AT |
67 | struct clk *dss_fck; |
68 | struct clk *dss_sys_clk; | |
69 | struct clk *dss_tv_fck; | |
70 | struct clk *dss_video_fck; | |
8b9cb3a8 | 71 | unsigned num_clks_enabled; |
559d6701 TV |
72 | |
73 | unsigned long cache_req_pck; | |
74 | unsigned long cache_prate; | |
75 | struct dss_clock_info cache_dss_cinfo; | |
76 | struct dispc_clock_info cache_dispc_cinfo; | |
77 | ||
5a8b572d | 78 | enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; |
89a35e51 AT |
79 | enum omap_dss_clk_source dispc_clk_source; |
80 | enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; | |
2f18c4d8 | 81 | |
559d6701 TV |
82 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
83 | } dss; | |
84 | ||
235e7dba | 85 | static const char * const dss_generic_clk_source_names[] = { |
89a35e51 AT |
86 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", |
87 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", | |
88 | [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", | |
067a57e4 AT |
89 | }; |
90 | ||
8b9cb3a8 SG |
91 | static void dss_clk_enable_all_no_ctx(void); |
92 | static void dss_clk_disable_all_no_ctx(void); | |
93 | static void dss_clk_enable_no_ctx(enum dss_clock clks); | |
94 | static void dss_clk_disable_no_ctx(enum dss_clock clks); | |
95 | ||
559d6701 TV |
96 | static int _omap_dss_wait_reset(void); |
97 | ||
98 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) | |
99 | { | |
100 | __raw_writel(val, dss.base + idx.idx); | |
101 | } | |
102 | ||
103 | static inline u32 dss_read_reg(const struct dss_reg idx) | |
104 | { | |
105 | return __raw_readl(dss.base + idx.idx); | |
106 | } | |
107 | ||
108 | #define SR(reg) \ | |
109 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) | |
110 | #define RR(reg) \ | |
111 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) | |
112 | ||
113 | void dss_save_context(void) | |
114 | { | |
115 | if (cpu_is_omap24xx()) | |
116 | return; | |
117 | ||
118 | SR(SYSCONFIG); | |
119 | SR(CONTROL); | |
120 | ||
6ec549e5 TV |
121 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
122 | OMAP_DISPLAY_TYPE_SDI) { | |
123 | SR(SDI_CONTROL); | |
124 | SR(PLL_CONTROL); | |
125 | } | |
559d6701 TV |
126 | } |
127 | ||
128 | void dss_restore_context(void) | |
129 | { | |
130 | if (_omap_dss_wait_reset()) | |
131 | DSSERR("DSS not coming out of reset after sleep\n"); | |
132 | ||
133 | RR(SYSCONFIG); | |
134 | RR(CONTROL); | |
135 | ||
6ec549e5 TV |
136 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
137 | OMAP_DISPLAY_TYPE_SDI) { | |
138 | RR(SDI_CONTROL); | |
139 | RR(PLL_CONTROL); | |
140 | } | |
559d6701 TV |
141 | } |
142 | ||
143 | #undef SR | |
144 | #undef RR | |
145 | ||
146 | void dss_sdi_init(u8 datapairs) | |
147 | { | |
148 | u32 l; | |
149 | ||
150 | BUG_ON(datapairs > 3 || datapairs < 1); | |
151 | ||
152 | l = dss_read_reg(DSS_SDI_CONTROL); | |
153 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ | |
154 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ | |
155 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ | |
156 | dss_write_reg(DSS_SDI_CONTROL, l); | |
157 | ||
158 | l = dss_read_reg(DSS_PLL_CONTROL); | |
159 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ | |
160 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ | |
161 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ | |
162 | dss_write_reg(DSS_PLL_CONTROL, l); | |
163 | } | |
164 | ||
165 | int dss_sdi_enable(void) | |
166 | { | |
167 | unsigned long timeout; | |
168 | ||
169 | dispc_pck_free_enable(1); | |
170 | ||
171 | /* Reset SDI PLL */ | |
172 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ | |
173 | udelay(1); /* wait 2x PCLK */ | |
174 | ||
175 | /* Lock SDI PLL */ | |
176 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ | |
177 | ||
178 | /* Waiting for PLL lock request to complete */ | |
179 | timeout = jiffies + msecs_to_jiffies(500); | |
180 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { | |
181 | if (time_after_eq(jiffies, timeout)) { | |
182 | DSSERR("PLL lock request timed out\n"); | |
183 | goto err1; | |
184 | } | |
185 | } | |
186 | ||
187 | /* Clearing PLL_GO bit */ | |
188 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); | |
189 | ||
190 | /* Waiting for PLL to lock */ | |
191 | timeout = jiffies + msecs_to_jiffies(500); | |
192 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { | |
193 | if (time_after_eq(jiffies, timeout)) { | |
194 | DSSERR("PLL lock timed out\n"); | |
195 | goto err1; | |
196 | } | |
197 | } | |
198 | ||
199 | dispc_lcd_enable_signal(1); | |
200 | ||
201 | /* Waiting for SDI reset to complete */ | |
202 | timeout = jiffies + msecs_to_jiffies(500); | |
203 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { | |
204 | if (time_after_eq(jiffies, timeout)) { | |
205 | DSSERR("SDI reset timed out\n"); | |
206 | goto err2; | |
207 | } | |
208 | } | |
209 | ||
210 | return 0; | |
211 | ||
212 | err2: | |
213 | dispc_lcd_enable_signal(0); | |
214 | err1: | |
215 | /* Reset SDI PLL */ | |
216 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
217 | ||
218 | dispc_pck_free_enable(0); | |
219 | ||
220 | return -ETIMEDOUT; | |
221 | } | |
222 | ||
223 | void dss_sdi_disable(void) | |
224 | { | |
225 | dispc_lcd_enable_signal(0); | |
226 | ||
227 | dispc_pck_free_enable(0); | |
228 | ||
229 | /* Reset SDI PLL */ | |
230 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
231 | } | |
232 | ||
89a35e51 | 233 | const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) |
067a57e4 | 234 | { |
235e7dba | 235 | return dss_generic_clk_source_names[clk_src]; |
067a57e4 AT |
236 | } |
237 | ||
559d6701 TV |
238 | void dss_dump_clocks(struct seq_file *s) |
239 | { | |
240 | unsigned long dpll4_ck_rate; | |
241 | unsigned long dpll4_m4_ck_rate; | |
0acf659f TV |
242 | const char *fclk_name, *fclk_real_name; |
243 | unsigned long fclk_rate; | |
559d6701 | 244 | |
6af9cd14 | 245 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 | 246 | |
559d6701 TV |
247 | seq_printf(s, "- DSS -\n"); |
248 | ||
89a35e51 AT |
249 | fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK); |
250 | fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); | |
0acf659f | 251 | fclk_rate = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 | 252 | |
0acf659f TV |
253 | if (dss.dpll4_m4_ck) { |
254 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | |
255 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); | |
256 | ||
257 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); | |
258 | ||
2de11086 | 259 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
0acf659f TV |
260 | seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", |
261 | fclk_name, fclk_real_name, | |
262 | dpll4_ck_rate, | |
263 | dpll4_ck_rate / dpll4_m4_ck_rate, | |
264 | fclk_rate); | |
265 | else | |
266 | seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", | |
267 | fclk_name, fclk_real_name, | |
268 | dpll4_ck_rate, | |
269 | dpll4_ck_rate / dpll4_m4_ck_rate, | |
270 | fclk_rate); | |
271 | } else { | |
272 | seq_printf(s, "%s (%s) = %lu\n", | |
273 | fclk_name, fclk_real_name, | |
274 | fclk_rate); | |
275 | } | |
559d6701 | 276 | |
6af9cd14 | 277 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
278 | } |
279 | ||
280 | void dss_dump_regs(struct seq_file *s) | |
281 | { | |
282 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) | |
283 | ||
6af9cd14 | 284 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
285 | |
286 | DUMPREG(DSS_REVISION); | |
287 | DUMPREG(DSS_SYSCONFIG); | |
288 | DUMPREG(DSS_SYSSTATUS); | |
559d6701 | 289 | DUMPREG(DSS_CONTROL); |
6ec549e5 TV |
290 | |
291 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & | |
292 | OMAP_DISPLAY_TYPE_SDI) { | |
293 | DUMPREG(DSS_SDI_CONTROL); | |
294 | DUMPREG(DSS_PLL_CONTROL); | |
295 | DUMPREG(DSS_SDI_STATUS); | |
296 | } | |
559d6701 | 297 | |
6af9cd14 | 298 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
299 | #undef DUMPREG |
300 | } | |
301 | ||
89a35e51 | 302 | void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src) |
2f18c4d8 | 303 | { |
a72b64b9 | 304 | struct platform_device *dsidev; |
2f18c4d8 | 305 | int b; |
ea75159e | 306 | u8 start, end; |
2f18c4d8 | 307 | |
66534e8e | 308 | switch (clk_src) { |
89a35e51 | 309 | case OMAP_DSS_CLK_SRC_FCK: |
66534e8e TA |
310 | b = 0; |
311 | break; | |
89a35e51 | 312 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
66534e8e | 313 | b = 1; |
a72b64b9 AT |
314 | dsidev = dsi_get_dsidev_from_id(0); |
315 | dsi_wait_pll_hsdiv_dispc_active(dsidev); | |
66534e8e | 316 | break; |
5a8b572d AT |
317 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
318 | b = 2; | |
319 | dsidev = dsi_get_dsidev_from_id(1); | |
320 | dsi_wait_pll_hsdiv_dispc_active(dsidev); | |
321 | break; | |
66534e8e TA |
322 | default: |
323 | BUG(); | |
324 | } | |
e406f907 | 325 | |
ea75159e TA |
326 | dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); |
327 | ||
328 | REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ | |
2f18c4d8 TV |
329 | |
330 | dss.dispc_clk_source = clk_src; | |
331 | } | |
332 | ||
5a8b572d AT |
333 | void dss_select_dsi_clk_source(int dsi_module, |
334 | enum omap_dss_clk_source clk_src) | |
559d6701 | 335 | { |
a72b64b9 | 336 | struct platform_device *dsidev; |
2f18c4d8 TV |
337 | int b; |
338 | ||
66534e8e | 339 | switch (clk_src) { |
89a35e51 | 340 | case OMAP_DSS_CLK_SRC_FCK: |
66534e8e TA |
341 | b = 0; |
342 | break; | |
89a35e51 | 343 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: |
5a8b572d | 344 | BUG_ON(dsi_module != 0); |
66534e8e | 345 | b = 1; |
a72b64b9 AT |
346 | dsidev = dsi_get_dsidev_from_id(0); |
347 | dsi_wait_pll_hsdiv_dsi_active(dsidev); | |
66534e8e | 348 | break; |
5a8b572d AT |
349 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI: |
350 | BUG_ON(dsi_module != 1); | |
351 | b = 1; | |
352 | dsidev = dsi_get_dsidev_from_id(1); | |
353 | dsi_wait_pll_hsdiv_dsi_active(dsidev); | |
354 | break; | |
66534e8e TA |
355 | default: |
356 | BUG(); | |
357 | } | |
e406f907 | 358 | |
2f18c4d8 TV |
359 | REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ |
360 | ||
5a8b572d | 361 | dss.dsi_clk_source[dsi_module] = clk_src; |
559d6701 TV |
362 | } |
363 | ||
ea75159e | 364 | void dss_select_lcd_clk_source(enum omap_channel channel, |
89a35e51 | 365 | enum omap_dss_clk_source clk_src) |
ea75159e | 366 | { |
a72b64b9 | 367 | struct platform_device *dsidev; |
ea75159e TA |
368 | int b, ix, pos; |
369 | ||
370 | if (!dss_has_feature(FEAT_LCD_CLK_SRC)) | |
371 | return; | |
372 | ||
373 | switch (clk_src) { | |
89a35e51 | 374 | case OMAP_DSS_CLK_SRC_FCK: |
ea75159e TA |
375 | b = 0; |
376 | break; | |
89a35e51 | 377 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
ea75159e TA |
378 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); |
379 | b = 1; | |
a72b64b9 AT |
380 | dsidev = dsi_get_dsidev_from_id(0); |
381 | dsi_wait_pll_hsdiv_dispc_active(dsidev); | |
ea75159e | 382 | break; |
5a8b572d AT |
383 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
384 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2); | |
385 | b = 1; | |
386 | dsidev = dsi_get_dsidev_from_id(1); | |
387 | dsi_wait_pll_hsdiv_dispc_active(dsidev); | |
388 | break; | |
ea75159e TA |
389 | default: |
390 | BUG(); | |
391 | } | |
392 | ||
393 | pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12; | |
394 | REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ | |
395 | ||
396 | ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; | |
397 | dss.lcd_clk_source[ix] = clk_src; | |
398 | } | |
399 | ||
89a35e51 | 400 | enum omap_dss_clk_source dss_get_dispc_clk_source(void) |
559d6701 | 401 | { |
2f18c4d8 | 402 | return dss.dispc_clk_source; |
559d6701 TV |
403 | } |
404 | ||
5a8b572d | 405 | enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module) |
559d6701 | 406 | { |
5a8b572d | 407 | return dss.dsi_clk_source[dsi_module]; |
559d6701 TV |
408 | } |
409 | ||
89a35e51 | 410 | enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) |
ea75159e | 411 | { |
89976f29 AT |
412 | if (dss_has_feature(FEAT_LCD_CLK_SRC)) { |
413 | int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; | |
414 | return dss.lcd_clk_source[ix]; | |
415 | } else { | |
416 | /* LCD_CLK source is the same as DISPC_FCLK source for | |
417 | * OMAP2 and OMAP3 */ | |
418 | return dss.dispc_clk_source; | |
419 | } | |
ea75159e TA |
420 | } |
421 | ||
559d6701 TV |
422 | /* calculate clock rates using dividers in cinfo */ |
423 | int dss_calc_clock_rates(struct dss_clock_info *cinfo) | |
424 | { | |
0acf659f TV |
425 | if (dss.dpll4_m4_ck) { |
426 | unsigned long prate; | |
2de11086 | 427 | u16 fck_div_max = 16; |
559d6701 | 428 | |
2de11086 MR |
429 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
430 | fck_div_max = 32; | |
431 | ||
432 | if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0) | |
0acf659f | 433 | return -EINVAL; |
559d6701 | 434 | |
0acf659f | 435 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
559d6701 | 436 | |
0acf659f TV |
437 | cinfo->fck = prate / cinfo->fck_div; |
438 | } else { | |
439 | if (cinfo->fck_div != 0) | |
440 | return -EINVAL; | |
441 | cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); | |
442 | } | |
559d6701 TV |
443 | |
444 | return 0; | |
445 | } | |
446 | ||
447 | int dss_set_clock_div(struct dss_clock_info *cinfo) | |
448 | { | |
0acf659f TV |
449 | if (dss.dpll4_m4_ck) { |
450 | unsigned long prate; | |
451 | int r; | |
559d6701 | 452 | |
559d6701 TV |
453 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
454 | DSSDBG("dpll4_m4 = %ld\n", prate); | |
455 | ||
456 | r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); | |
457 | if (r) | |
458 | return r; | |
0acf659f TV |
459 | } else { |
460 | if (cinfo->fck_div != 0) | |
461 | return -EINVAL; | |
559d6701 TV |
462 | } |
463 | ||
464 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | int dss_get_clock_div(struct dss_clock_info *cinfo) | |
470 | { | |
6af9cd14 | 471 | cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 | 472 | |
0acf659f | 473 | if (dss.dpll4_m4_ck) { |
559d6701 | 474 | unsigned long prate; |
0acf659f | 475 | |
559d6701 | 476 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
0acf659f | 477 | |
2de11086 | 478 | if (cpu_is_omap3630() || cpu_is_omap44xx()) |
ac01bb7e K |
479 | cinfo->fck_div = prate / (cinfo->fck); |
480 | else | |
481 | cinfo->fck_div = prate / (cinfo->fck / 2); | |
559d6701 TV |
482 | } else { |
483 | cinfo->fck_div = 0; | |
484 | } | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | unsigned long dss_get_dpll4_rate(void) | |
490 | { | |
0acf659f | 491 | if (dss.dpll4_m4_ck) |
559d6701 TV |
492 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); |
493 | else | |
494 | return 0; | |
495 | } | |
496 | ||
497 | int dss_calc_clock_div(bool is_tft, unsigned long req_pck, | |
498 | struct dss_clock_info *dss_cinfo, | |
499 | struct dispc_clock_info *dispc_cinfo) | |
500 | { | |
501 | unsigned long prate; | |
502 | struct dss_clock_info best_dss; | |
503 | struct dispc_clock_info best_dispc; | |
504 | ||
819d807c | 505 | unsigned long fck, max_dss_fck; |
559d6701 | 506 | |
2de11086 | 507 | u16 fck_div, fck_div_max = 16; |
559d6701 TV |
508 | |
509 | int match = 0; | |
510 | int min_fck_per_pck; | |
511 | ||
512 | prate = dss_get_dpll4_rate(); | |
513 | ||
31ef8237 | 514 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
819d807c | 515 | |
6af9cd14 | 516 | fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 TV |
517 | if (req_pck == dss.cache_req_pck && |
518 | ((cpu_is_omap34xx() && prate == dss.cache_prate) || | |
519 | dss.cache_dss_cinfo.fck == fck)) { | |
520 | DSSDBG("dispc clock info found from cache.\n"); | |
521 | *dss_cinfo = dss.cache_dss_cinfo; | |
522 | *dispc_cinfo = dss.cache_dispc_cinfo; | |
523 | return 0; | |
524 | } | |
525 | ||
526 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
527 | ||
528 | if (min_fck_per_pck && | |
819d807c | 529 | req_pck * min_fck_per_pck > max_dss_fck) { |
559d6701 TV |
530 | DSSERR("Requested pixel clock not possible with the current " |
531 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " | |
532 | "the constraint off.\n"); | |
533 | min_fck_per_pck = 0; | |
534 | } | |
535 | ||
536 | retry: | |
537 | memset(&best_dss, 0, sizeof(best_dss)); | |
538 | memset(&best_dispc, 0, sizeof(best_dispc)); | |
539 | ||
2de11086 | 540 | if (dss.dpll4_m4_ck == NULL) { |
559d6701 TV |
541 | struct dispc_clock_info cur_dispc; |
542 | /* XXX can we change the clock on omap2? */ | |
6af9cd14 | 543 | fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 TV |
544 | fck_div = 1; |
545 | ||
546 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); | |
547 | match = 1; | |
548 | ||
549 | best_dss.fck = fck; | |
550 | best_dss.fck_div = fck_div; | |
551 | ||
552 | best_dispc = cur_dispc; | |
553 | ||
554 | goto found; | |
2de11086 MR |
555 | } else { |
556 | if (cpu_is_omap3630() || cpu_is_omap44xx()) | |
557 | fck_div_max = 32; | |
558 | ||
559 | for (fck_div = fck_div_max; fck_div > 0; --fck_div) { | |
559d6701 TV |
560 | struct dispc_clock_info cur_dispc; |
561 | ||
2de11086 | 562 | if (fck_div_max == 32) |
ac01bb7e K |
563 | fck = prate / fck_div; |
564 | else | |
565 | fck = prate / fck_div * 2; | |
559d6701 | 566 | |
819d807c | 567 | if (fck > max_dss_fck) |
559d6701 TV |
568 | continue; |
569 | ||
570 | if (min_fck_per_pck && | |
571 | fck < req_pck * min_fck_per_pck) | |
572 | continue; | |
573 | ||
574 | match = 1; | |
575 | ||
576 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); | |
577 | ||
578 | if (abs(cur_dispc.pck - req_pck) < | |
579 | abs(best_dispc.pck - req_pck)) { | |
580 | ||
581 | best_dss.fck = fck; | |
582 | best_dss.fck_div = fck_div; | |
583 | ||
584 | best_dispc = cur_dispc; | |
585 | ||
586 | if (cur_dispc.pck == req_pck) | |
587 | goto found; | |
588 | } | |
589 | } | |
559d6701 TV |
590 | } |
591 | ||
592 | found: | |
593 | if (!match) { | |
594 | if (min_fck_per_pck) { | |
595 | DSSERR("Could not find suitable clock settings.\n" | |
596 | "Turning FCK/PCK constraint off and" | |
597 | "trying again.\n"); | |
598 | min_fck_per_pck = 0; | |
599 | goto retry; | |
600 | } | |
601 | ||
602 | DSSERR("Could not find suitable clock settings.\n"); | |
603 | ||
604 | return -EINVAL; | |
605 | } | |
606 | ||
607 | if (dss_cinfo) | |
608 | *dss_cinfo = best_dss; | |
609 | if (dispc_cinfo) | |
610 | *dispc_cinfo = best_dispc; | |
611 | ||
612 | dss.cache_req_pck = req_pck; | |
613 | dss.cache_prate = prate; | |
614 | dss.cache_dss_cinfo = best_dss; | |
615 | dss.cache_dispc_cinfo = best_dispc; | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
559d6701 TV |
620 | static int _omap_dss_wait_reset(void) |
621 | { | |
24be78b3 | 622 | int t = 0; |
559d6701 TV |
623 | |
624 | while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) { | |
24be78b3 | 625 | if (++t > 1000) { |
559d6701 TV |
626 | DSSERR("soft reset failed\n"); |
627 | return -ENODEV; | |
628 | } | |
24be78b3 | 629 | udelay(1); |
559d6701 TV |
630 | } |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | static int _omap_dss_reset(void) | |
636 | { | |
637 | /* Soft reset */ | |
638 | REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); | |
639 | return _omap_dss_wait_reset(); | |
640 | } | |
641 | ||
642 | void dss_set_venc_output(enum omap_dss_venc_type type) | |
643 | { | |
644 | int l = 0; | |
645 | ||
646 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) | |
647 | l = 0; | |
648 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) | |
649 | l = 1; | |
650 | else | |
651 | BUG(); | |
652 | ||
653 | /* venc out selection. 0 = comp, 1 = svideo */ | |
654 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); | |
655 | } | |
656 | ||
657 | void dss_set_dac_pwrdn_bgz(bool enable) | |
658 | { | |
659 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ | |
660 | } | |
661 | ||
7ed024aa M |
662 | void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) |
663 | { | |
664 | REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ | |
665 | } | |
666 | ||
42c9dee8 | 667 | static int dss_init(void) |
559d6701 TV |
668 | { |
669 | int r; | |
670 | u32 rev; | |
ea9da36a | 671 | struct resource *dss_mem; |
0acf659f | 672 | struct clk *dpll4_m4_ck; |
559d6701 | 673 | |
ea9da36a SG |
674 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
675 | if (!dss_mem) { | |
676 | DSSERR("can't get IORESOURCE_MEM DSS\n"); | |
677 | r = -EINVAL; | |
678 | goto fail0; | |
679 | } | |
680 | dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); | |
559d6701 TV |
681 | if (!dss.base) { |
682 | DSSERR("can't ioremap DSS\n"); | |
683 | r = -ENOMEM; | |
684 | goto fail0; | |
685 | } | |
686 | ||
42c9dee8 TV |
687 | /* disable LCD and DIGIT output. This seems to fix the synclost |
688 | * problem that we get, if the bootloader starts the DSS and | |
689 | * the kernel resets it */ | |
690 | omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); | |
691 | ||
f1aafdcd | 692 | #ifdef CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET |
42c9dee8 TV |
693 | /* We need to wait here a bit, otherwise we sometimes start to |
694 | * get synclost errors, and after that only power cycle will | |
695 | * restore DSS functionality. I have no idea why this happens. | |
696 | * And we have to wait _before_ resetting the DSS, but after | |
697 | * enabling clocks. | |
f1aafdcd TV |
698 | * |
699 | * This bug was at least present on OMAP3430. It's unknown | |
700 | * if it happens on OMAP2 or OMAP3630. | |
42c9dee8 TV |
701 | */ |
702 | msleep(50); | |
f1aafdcd | 703 | #endif |
42c9dee8 TV |
704 | |
705 | _omap_dss_reset(); | |
559d6701 TV |
706 | |
707 | /* autoidle */ | |
708 | REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); | |
709 | ||
710 | /* Select DPLL */ | |
711 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); | |
712 | ||
713 | #ifdef CONFIG_OMAP2_DSS_VENC | |
714 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ | |
715 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ | |
716 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ | |
717 | #endif | |
559d6701 | 718 | if (cpu_is_omap34xx()) { |
0acf659f TV |
719 | dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); |
720 | if (IS_ERR(dpll4_m4_ck)) { | |
559d6701 | 721 | DSSERR("Failed to get dpll4_m4_ck\n"); |
0acf659f | 722 | r = PTR_ERR(dpll4_m4_ck); |
affe360d | 723 | goto fail1; |
559d6701 | 724 | } |
2de11086 MR |
725 | } else if (cpu_is_omap44xx()) { |
726 | dpll4_m4_ck = clk_get(NULL, "dpll_per_m5x2_ck"); | |
727 | if (IS_ERR(dpll4_m4_ck)) { | |
728 | DSSERR("Failed to get dpll4_m4_ck\n"); | |
729 | r = PTR_ERR(dpll4_m4_ck); | |
730 | goto fail1; | |
731 | } | |
0acf659f TV |
732 | } else { /* omap24xx */ |
733 | dpll4_m4_ck = NULL; | |
559d6701 TV |
734 | } |
735 | ||
0acf659f TV |
736 | dss.dpll4_m4_ck = dpll4_m4_ck; |
737 | ||
5a8b572d AT |
738 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; |
739 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | |
89a35e51 AT |
740 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; |
741 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | |
742 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | |
ce619e1f | 743 | |
559d6701 TV |
744 | dss_save_context(); |
745 | ||
746 | rev = dss_read_reg(DSS_REVISION); | |
747 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", | |
748 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
749 | ||
750 | return 0; | |
751 | ||
559d6701 TV |
752 | fail1: |
753 | iounmap(dss.base); | |
754 | fail0: | |
755 | return r; | |
756 | } | |
757 | ||
96c401bc | 758 | static void dss_exit(void) |
559d6701 | 759 | { |
0acf659f | 760 | if (dss.dpll4_m4_ck) |
559d6701 TV |
761 | clk_put(dss.dpll4_m4_ck); |
762 | ||
559d6701 TV |
763 | iounmap(dss.base); |
764 | } | |
765 | ||
8b9cb3a8 SG |
766 | /* CONTEXT */ |
767 | static int dss_get_ctx_id(void) | |
768 | { | |
769 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; | |
770 | int r; | |
771 | ||
772 | if (!pdata->board_data->get_last_off_on_transaction_id) | |
773 | return 0; | |
774 | r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev); | |
775 | if (r < 0) { | |
776 | dev_err(&dss.pdev->dev, "getting transaction ID failed, " | |
777 | "will force context restore\n"); | |
778 | r = -1; | |
779 | } | |
780 | return r; | |
781 | } | |
782 | ||
783 | int dss_need_ctx_restore(void) | |
784 | { | |
785 | int id = dss_get_ctx_id(); | |
786 | ||
787 | if (id < 0 || id != dss.ctx_id) { | |
788 | DSSDBG("ctx id %d -> id %d\n", | |
789 | dss.ctx_id, id); | |
790 | dss.ctx_id = id; | |
791 | return 1; | |
792 | } else { | |
793 | return 0; | |
794 | } | |
795 | } | |
796 | ||
797 | static void save_all_ctx(void) | |
798 | { | |
799 | DSSDBG("save context\n"); | |
800 | ||
6af9cd14 | 801 | dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); |
8b9cb3a8 SG |
802 | |
803 | dss_save_context(); | |
804 | dispc_save_context(); | |
805 | #ifdef CONFIG_OMAP2_DSS_DSI | |
806 | dsi_save_context(); | |
807 | #endif | |
808 | ||
6af9cd14 | 809 | dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); |
8b9cb3a8 SG |
810 | } |
811 | ||
812 | static void restore_all_ctx(void) | |
813 | { | |
814 | DSSDBG("restore context\n"); | |
815 | ||
816 | dss_clk_enable_all_no_ctx(); | |
817 | ||
818 | dss_restore_context(); | |
819 | dispc_restore_context(); | |
820 | #ifdef CONFIG_OMAP2_DSS_DSI | |
821 | dsi_restore_context(); | |
822 | #endif | |
823 | ||
824 | dss_clk_disable_all_no_ctx(); | |
825 | } | |
826 | ||
827 | static int dss_get_clock(struct clk **clock, const char *clk_name) | |
828 | { | |
829 | struct clk *clk; | |
830 | ||
831 | clk = clk_get(&dss.pdev->dev, clk_name); | |
832 | ||
833 | if (IS_ERR(clk)) { | |
834 | DSSERR("can't get clock %s", clk_name); | |
835 | return PTR_ERR(clk); | |
836 | } | |
837 | ||
838 | *clock = clk; | |
839 | ||
840 | DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
845 | static int dss_get_clocks(void) | |
846 | { | |
847 | int r; | |
a1a0dcca | 848 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; |
8b9cb3a8 SG |
849 | |
850 | dss.dss_ick = NULL; | |
c7642f67 AT |
851 | dss.dss_fck = NULL; |
852 | dss.dss_sys_clk = NULL; | |
853 | dss.dss_tv_fck = NULL; | |
854 | dss.dss_video_fck = NULL; | |
8b9cb3a8 SG |
855 | |
856 | r = dss_get_clock(&dss.dss_ick, "ick"); | |
857 | if (r) | |
858 | goto err; | |
859 | ||
c7642f67 | 860 | r = dss_get_clock(&dss.dss_fck, "fck"); |
8b9cb3a8 SG |
861 | if (r) |
862 | goto err; | |
863 | ||
a1a0dcca SS |
864 | if (!pdata->opt_clock_available) { |
865 | r = -ENODEV; | |
8b9cb3a8 | 866 | goto err; |
a1a0dcca | 867 | } |
8b9cb3a8 | 868 | |
a1a0dcca SS |
869 | if (pdata->opt_clock_available("sys_clk")) { |
870 | r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); | |
871 | if (r) | |
872 | goto err; | |
873 | } | |
8b9cb3a8 | 874 | |
a1a0dcca SS |
875 | if (pdata->opt_clock_available("tv_clk")) { |
876 | r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); | |
877 | if (r) | |
878 | goto err; | |
879 | } | |
880 | ||
881 | if (pdata->opt_clock_available("video_clk")) { | |
882 | r = dss_get_clock(&dss.dss_video_fck, "video_clk"); | |
883 | if (r) | |
884 | goto err; | |
885 | } | |
8b9cb3a8 SG |
886 | |
887 | return 0; | |
888 | ||
889 | err: | |
890 | if (dss.dss_ick) | |
891 | clk_put(dss.dss_ick); | |
c7642f67 AT |
892 | if (dss.dss_fck) |
893 | clk_put(dss.dss_fck); | |
894 | if (dss.dss_sys_clk) | |
895 | clk_put(dss.dss_sys_clk); | |
896 | if (dss.dss_tv_fck) | |
897 | clk_put(dss.dss_tv_fck); | |
898 | if (dss.dss_video_fck) | |
899 | clk_put(dss.dss_video_fck); | |
8b9cb3a8 SG |
900 | |
901 | return r; | |
902 | } | |
903 | ||
904 | static void dss_put_clocks(void) | |
905 | { | |
c7642f67 AT |
906 | if (dss.dss_video_fck) |
907 | clk_put(dss.dss_video_fck); | |
a1a0dcca SS |
908 | if (dss.dss_tv_fck) |
909 | clk_put(dss.dss_tv_fck); | |
910 | if (dss.dss_sys_clk) | |
911 | clk_put(dss.dss_sys_clk); | |
c7642f67 | 912 | clk_put(dss.dss_fck); |
8b9cb3a8 SG |
913 | clk_put(dss.dss_ick); |
914 | } | |
915 | ||
916 | unsigned long dss_clk_get_rate(enum dss_clock clk) | |
917 | { | |
918 | switch (clk) { | |
919 | case DSS_CLK_ICK: | |
920 | return clk_get_rate(dss.dss_ick); | |
6af9cd14 | 921 | case DSS_CLK_FCK: |
c7642f67 | 922 | return clk_get_rate(dss.dss_fck); |
6af9cd14 | 923 | case DSS_CLK_SYSCK: |
c7642f67 | 924 | return clk_get_rate(dss.dss_sys_clk); |
6af9cd14 | 925 | case DSS_CLK_TVFCK: |
c7642f67 | 926 | return clk_get_rate(dss.dss_tv_fck); |
6af9cd14 | 927 | case DSS_CLK_VIDFCK: |
c7642f67 | 928 | return clk_get_rate(dss.dss_video_fck); |
8b9cb3a8 SG |
929 | } |
930 | ||
931 | BUG(); | |
932 | return 0; | |
933 | } | |
934 | ||
935 | static unsigned count_clk_bits(enum dss_clock clks) | |
936 | { | |
937 | unsigned num_clks = 0; | |
938 | ||
939 | if (clks & DSS_CLK_ICK) | |
940 | ++num_clks; | |
6af9cd14 | 941 | if (clks & DSS_CLK_FCK) |
8b9cb3a8 | 942 | ++num_clks; |
6af9cd14 | 943 | if (clks & DSS_CLK_SYSCK) |
8b9cb3a8 | 944 | ++num_clks; |
6af9cd14 | 945 | if (clks & DSS_CLK_TVFCK) |
8b9cb3a8 | 946 | ++num_clks; |
6af9cd14 | 947 | if (clks & DSS_CLK_VIDFCK) |
8b9cb3a8 SG |
948 | ++num_clks; |
949 | ||
950 | return num_clks; | |
951 | } | |
952 | ||
953 | static void dss_clk_enable_no_ctx(enum dss_clock clks) | |
954 | { | |
955 | unsigned num_clks = count_clk_bits(clks); | |
956 | ||
957 | if (clks & DSS_CLK_ICK) | |
958 | clk_enable(dss.dss_ick); | |
6af9cd14 | 959 | if (clks & DSS_CLK_FCK) |
c7642f67 | 960 | clk_enable(dss.dss_fck); |
a1a0dcca | 961 | if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) |
c7642f67 | 962 | clk_enable(dss.dss_sys_clk); |
a1a0dcca | 963 | if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) |
c7642f67 | 964 | clk_enable(dss.dss_tv_fck); |
a1a0dcca | 965 | if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) |
c7642f67 | 966 | clk_enable(dss.dss_video_fck); |
8b9cb3a8 SG |
967 | |
968 | dss.num_clks_enabled += num_clks; | |
969 | } | |
970 | ||
971 | void dss_clk_enable(enum dss_clock clks) | |
972 | { | |
973 | bool check_ctx = dss.num_clks_enabled == 0; | |
974 | ||
975 | dss_clk_enable_no_ctx(clks); | |
976 | ||
85604b0a TV |
977 | /* |
978 | * HACK: On omap4 the registers may not be accessible right after | |
979 | * enabling the clocks. At some point this will be handled by | |
980 | * pm_runtime, but for the time begin this should make things work. | |
981 | */ | |
982 | if (cpu_is_omap44xx() && check_ctx) | |
983 | udelay(10); | |
984 | ||
8b9cb3a8 SG |
985 | if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) |
986 | restore_all_ctx(); | |
987 | } | |
988 | ||
989 | static void dss_clk_disable_no_ctx(enum dss_clock clks) | |
990 | { | |
991 | unsigned num_clks = count_clk_bits(clks); | |
992 | ||
993 | if (clks & DSS_CLK_ICK) | |
994 | clk_disable(dss.dss_ick); | |
6af9cd14 | 995 | if (clks & DSS_CLK_FCK) |
c7642f67 | 996 | clk_disable(dss.dss_fck); |
a1a0dcca | 997 | if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) |
c7642f67 | 998 | clk_disable(dss.dss_sys_clk); |
a1a0dcca | 999 | if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) |
c7642f67 | 1000 | clk_disable(dss.dss_tv_fck); |
a1a0dcca | 1001 | if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) |
c7642f67 | 1002 | clk_disable(dss.dss_video_fck); |
8b9cb3a8 SG |
1003 | |
1004 | dss.num_clks_enabled -= num_clks; | |
1005 | } | |
1006 | ||
1007 | void dss_clk_disable(enum dss_clock clks) | |
1008 | { | |
1009 | if (cpu_is_omap34xx()) { | |
1010 | unsigned num_clks = count_clk_bits(clks); | |
1011 | ||
1012 | BUG_ON(dss.num_clks_enabled < num_clks); | |
1013 | ||
1014 | if (dss.num_clks_enabled == num_clks) | |
1015 | save_all_ctx(); | |
1016 | } | |
1017 | ||
1018 | dss_clk_disable_no_ctx(clks); | |
1019 | } | |
1020 | ||
1021 | static void dss_clk_enable_all_no_ctx(void) | |
1022 | { | |
1023 | enum dss_clock clks; | |
1024 | ||
6af9cd14 | 1025 | clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; |
8b9cb3a8 | 1026 | if (cpu_is_omap34xx()) |
6af9cd14 | 1027 | clks |= DSS_CLK_VIDFCK; |
8b9cb3a8 SG |
1028 | dss_clk_enable_no_ctx(clks); |
1029 | } | |
1030 | ||
1031 | static void dss_clk_disable_all_no_ctx(void) | |
1032 | { | |
1033 | enum dss_clock clks; | |
1034 | ||
6af9cd14 | 1035 | clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; |
8b9cb3a8 | 1036 | if (cpu_is_omap34xx()) |
6af9cd14 | 1037 | clks |= DSS_CLK_VIDFCK; |
8b9cb3a8 SG |
1038 | dss_clk_disable_no_ctx(clks); |
1039 | } | |
1040 | ||
1041 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
1042 | /* CLOCKS */ | |
1043 | static void core_dump_clocks(struct seq_file *s) | |
1044 | { | |
1045 | int i; | |
1046 | struct clk *clocks[5] = { | |
1047 | dss.dss_ick, | |
c7642f67 AT |
1048 | dss.dss_fck, |
1049 | dss.dss_sys_clk, | |
1050 | dss.dss_tv_fck, | |
1051 | dss.dss_video_fck | |
8b9cb3a8 SG |
1052 | }; |
1053 | ||
ab46d8b2 TV |
1054 | const char *names[5] = { |
1055 | "ick", | |
1056 | "fck", | |
1057 | "sys_clk", | |
1058 | "tv_fck", | |
1059 | "video_fck" | |
1060 | }; | |
1061 | ||
8b9cb3a8 SG |
1062 | seq_printf(s, "- CORE -\n"); |
1063 | ||
1064 | seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled); | |
1065 | ||
1066 | for (i = 0; i < 5; i++) { | |
1067 | if (!clocks[i]) | |
1068 | continue; | |
ab46d8b2 TV |
1069 | seq_printf(s, "%s (%s)%*s\t%lu\t%d\n", |
1070 | names[i], | |
8b9cb3a8 | 1071 | clocks[i]->name, |
ab46d8b2 TV |
1072 | 24 - strlen(names[i]) - strlen(clocks[i]->name), |
1073 | "", | |
8b9cb3a8 SG |
1074 | clk_get_rate(clocks[i]), |
1075 | clocks[i]->usecount); | |
1076 | } | |
1077 | } | |
1078 | #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ | |
1079 | ||
1080 | /* DEBUGFS */ | |
1081 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
1082 | void dss_debug_dump_clocks(struct seq_file *s) | |
1083 | { | |
1084 | core_dump_clocks(s); | |
1085 | dss_dump_clocks(s); | |
1086 | dispc_dump_clocks(s); | |
1087 | #ifdef CONFIG_OMAP2_DSS_DSI | |
1088 | dsi_dump_clocks(s); | |
1089 | #endif | |
1090 | } | |
1091 | #endif | |
1092 | ||
1093 | ||
96c401bc SG |
1094 | /* DSS HW IP initialisation */ |
1095 | static int omap_dsshw_probe(struct platform_device *pdev) | |
1096 | { | |
1097 | int r; | |
96c401bc SG |
1098 | |
1099 | dss.pdev = pdev; | |
1100 | ||
8b9cb3a8 SG |
1101 | r = dss_get_clocks(); |
1102 | if (r) | |
1103 | goto err_clocks; | |
1104 | ||
1105 | dss_clk_enable_all_no_ctx(); | |
1106 | ||
1107 | dss.ctx_id = dss_get_ctx_id(); | |
1108 | DSSDBG("initial ctx id %u\n", dss.ctx_id); | |
1109 | ||
42c9dee8 | 1110 | r = dss_init(); |
96c401bc SG |
1111 | if (r) { |
1112 | DSSERR("Failed to initialize DSS\n"); | |
1113 | goto err_dss; | |
1114 | } | |
1115 | ||
587b5e82 TV |
1116 | r = dpi_init(); |
1117 | if (r) { | |
1118 | DSSERR("Failed to initialize DPI\n"); | |
1119 | goto err_dpi; | |
1120 | } | |
1121 | ||
1122 | r = sdi_init(); | |
1123 | if (r) { | |
1124 | DSSERR("Failed to initialize SDI\n"); | |
1125 | goto err_sdi; | |
1126 | } | |
1127 | ||
8b9cb3a8 SG |
1128 | dss_clk_disable_all_no_ctx(); |
1129 | return 0; | |
587b5e82 TV |
1130 | err_sdi: |
1131 | dpi_exit(); | |
1132 | err_dpi: | |
1133 | dss_exit(); | |
8b9cb3a8 SG |
1134 | err_dss: |
1135 | dss_clk_disable_all_no_ctx(); | |
1136 | dss_put_clocks(); | |
1137 | err_clocks: | |
96c401bc SG |
1138 | return r; |
1139 | } | |
1140 | ||
1141 | static int omap_dsshw_remove(struct platform_device *pdev) | |
1142 | { | |
8b9cb3a8 | 1143 | |
96c401bc SG |
1144 | dss_exit(); |
1145 | ||
8b9cb3a8 SG |
1146 | /* |
1147 | * As part of hwmod changes, DSS is not the only controller of dss | |
1148 | * clocks; hwmod framework itself will also enable clocks during hwmod | |
1149 | * init for dss, and autoidle is set in h/w for DSS. Hence, there's no | |
1150 | * need to disable clocks if their usecounts > 1. | |
1151 | */ | |
1152 | WARN_ON(dss.num_clks_enabled > 0); | |
1153 | ||
1154 | dss_put_clocks(); | |
96c401bc SG |
1155 | return 0; |
1156 | } | |
1157 | ||
1158 | static struct platform_driver omap_dsshw_driver = { | |
1159 | .probe = omap_dsshw_probe, | |
1160 | .remove = omap_dsshw_remove, | |
1161 | .driver = { | |
1162 | .name = "omapdss_dss", | |
1163 | .owner = THIS_MODULE, | |
1164 | }, | |
1165 | }; | |
1166 | ||
1167 | int dss_init_platform_driver(void) | |
1168 | { | |
1169 | return platform_driver_register(&omap_dsshw_driver); | |
1170 | } | |
1171 | ||
1172 | void dss_uninit_platform_driver(void) | |
1173 | { | |
1174 | return platform_driver_unregister(&omap_dsshw_driver); | |
1175 | } |