Commit | Line | Data |
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559d6701 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dss.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DSS" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/io.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/delay.h> | |
559d6701 TV |
29 | #include <linux/seq_file.h> |
30 | #include <linux/clk.h> | |
31 | ||
32 | #include <plat/display.h> | |
8b9cb3a8 | 33 | #include <plat/clock.h> |
559d6701 | 34 | #include "dss.h" |
6ec549e5 | 35 | #include "dss_features.h" |
559d6701 | 36 | |
559d6701 TV |
37 | #define DSS_SZ_REGS SZ_512 |
38 | ||
39 | struct dss_reg { | |
40 | u16 idx; | |
41 | }; | |
42 | ||
43 | #define DSS_REG(idx) ((const struct dss_reg) { idx }) | |
44 | ||
45 | #define DSS_REVISION DSS_REG(0x0000) | |
46 | #define DSS_SYSCONFIG DSS_REG(0x0010) | |
47 | #define DSS_SYSSTATUS DSS_REG(0x0014) | |
48 | #define DSS_IRQSTATUS DSS_REG(0x0018) | |
49 | #define DSS_CONTROL DSS_REG(0x0040) | |
50 | #define DSS_SDI_CONTROL DSS_REG(0x0044) | |
51 | #define DSS_PLL_CONTROL DSS_REG(0x0048) | |
52 | #define DSS_SDI_STATUS DSS_REG(0x005C) | |
53 | ||
54 | #define REG_GET(idx, start, end) \ | |
55 | FLD_GET(dss_read_reg(idx), start, end) | |
56 | ||
57 | #define REG_FLD_MOD(idx, val, start, end) \ | |
58 | dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) | |
59 | ||
60 | static struct { | |
96c401bc | 61 | struct platform_device *pdev; |
559d6701 | 62 | void __iomem *base; |
8b9cb3a8 | 63 | int ctx_id; |
559d6701 TV |
64 | |
65 | struct clk *dpll4_m4_ck; | |
8b9cb3a8 | 66 | struct clk *dss_ick; |
c7642f67 AT |
67 | struct clk *dss_fck; |
68 | struct clk *dss_sys_clk; | |
69 | struct clk *dss_tv_fck; | |
70 | struct clk *dss_video_fck; | |
8b9cb3a8 | 71 | unsigned num_clks_enabled; |
559d6701 TV |
72 | |
73 | unsigned long cache_req_pck; | |
74 | unsigned long cache_prate; | |
75 | struct dss_clock_info cache_dss_cinfo; | |
76 | struct dispc_clock_info cache_dispc_cinfo; | |
77 | ||
2f18c4d8 TV |
78 | enum dss_clk_source dsi_clk_source; |
79 | enum dss_clk_source dispc_clk_source; | |
80 | ||
559d6701 TV |
81 | u32 ctx[DSS_SZ_REGS / sizeof(u32)]; |
82 | } dss; | |
83 | ||
067a57e4 AT |
84 | static const struct dss_clk_source_name dss_generic_clk_source_names[] = { |
85 | { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" }, | |
86 | { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" }, | |
87 | { DSS_CLK_SRC_FCK, "DSS_FCK" }, | |
88 | }; | |
89 | ||
8b9cb3a8 SG |
90 | static void dss_clk_enable_all_no_ctx(void); |
91 | static void dss_clk_disable_all_no_ctx(void); | |
92 | static void dss_clk_enable_no_ctx(enum dss_clock clks); | |
93 | static void dss_clk_disable_no_ctx(enum dss_clock clks); | |
94 | ||
559d6701 TV |
95 | static int _omap_dss_wait_reset(void); |
96 | ||
97 | static inline void dss_write_reg(const struct dss_reg idx, u32 val) | |
98 | { | |
99 | __raw_writel(val, dss.base + idx.idx); | |
100 | } | |
101 | ||
102 | static inline u32 dss_read_reg(const struct dss_reg idx) | |
103 | { | |
104 | return __raw_readl(dss.base + idx.idx); | |
105 | } | |
106 | ||
107 | #define SR(reg) \ | |
108 | dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) | |
109 | #define RR(reg) \ | |
110 | dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) | |
111 | ||
112 | void dss_save_context(void) | |
113 | { | |
114 | if (cpu_is_omap24xx()) | |
115 | return; | |
116 | ||
117 | SR(SYSCONFIG); | |
118 | SR(CONTROL); | |
119 | ||
6ec549e5 TV |
120 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
121 | OMAP_DISPLAY_TYPE_SDI) { | |
122 | SR(SDI_CONTROL); | |
123 | SR(PLL_CONTROL); | |
124 | } | |
559d6701 TV |
125 | } |
126 | ||
127 | void dss_restore_context(void) | |
128 | { | |
129 | if (_omap_dss_wait_reset()) | |
130 | DSSERR("DSS not coming out of reset after sleep\n"); | |
131 | ||
132 | RR(SYSCONFIG); | |
133 | RR(CONTROL); | |
134 | ||
6ec549e5 TV |
135 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & |
136 | OMAP_DISPLAY_TYPE_SDI) { | |
137 | RR(SDI_CONTROL); | |
138 | RR(PLL_CONTROL); | |
139 | } | |
559d6701 TV |
140 | } |
141 | ||
142 | #undef SR | |
143 | #undef RR | |
144 | ||
145 | void dss_sdi_init(u8 datapairs) | |
146 | { | |
147 | u32 l; | |
148 | ||
149 | BUG_ON(datapairs > 3 || datapairs < 1); | |
150 | ||
151 | l = dss_read_reg(DSS_SDI_CONTROL); | |
152 | l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ | |
153 | l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ | |
154 | l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ | |
155 | dss_write_reg(DSS_SDI_CONTROL, l); | |
156 | ||
157 | l = dss_read_reg(DSS_PLL_CONTROL); | |
158 | l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ | |
159 | l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ | |
160 | l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ | |
161 | dss_write_reg(DSS_PLL_CONTROL, l); | |
162 | } | |
163 | ||
164 | int dss_sdi_enable(void) | |
165 | { | |
166 | unsigned long timeout; | |
167 | ||
168 | dispc_pck_free_enable(1); | |
169 | ||
170 | /* Reset SDI PLL */ | |
171 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ | |
172 | udelay(1); /* wait 2x PCLK */ | |
173 | ||
174 | /* Lock SDI PLL */ | |
175 | REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ | |
176 | ||
177 | /* Waiting for PLL lock request to complete */ | |
178 | timeout = jiffies + msecs_to_jiffies(500); | |
179 | while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { | |
180 | if (time_after_eq(jiffies, timeout)) { | |
181 | DSSERR("PLL lock request timed out\n"); | |
182 | goto err1; | |
183 | } | |
184 | } | |
185 | ||
186 | /* Clearing PLL_GO bit */ | |
187 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); | |
188 | ||
189 | /* Waiting for PLL to lock */ | |
190 | timeout = jiffies + msecs_to_jiffies(500); | |
191 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { | |
192 | if (time_after_eq(jiffies, timeout)) { | |
193 | DSSERR("PLL lock timed out\n"); | |
194 | goto err1; | |
195 | } | |
196 | } | |
197 | ||
198 | dispc_lcd_enable_signal(1); | |
199 | ||
200 | /* Waiting for SDI reset to complete */ | |
201 | timeout = jiffies + msecs_to_jiffies(500); | |
202 | while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { | |
203 | if (time_after_eq(jiffies, timeout)) { | |
204 | DSSERR("SDI reset timed out\n"); | |
205 | goto err2; | |
206 | } | |
207 | } | |
208 | ||
209 | return 0; | |
210 | ||
211 | err2: | |
212 | dispc_lcd_enable_signal(0); | |
213 | err1: | |
214 | /* Reset SDI PLL */ | |
215 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
216 | ||
217 | dispc_pck_free_enable(0); | |
218 | ||
219 | return -ETIMEDOUT; | |
220 | } | |
221 | ||
222 | void dss_sdi_disable(void) | |
223 | { | |
224 | dispc_lcd_enable_signal(0); | |
225 | ||
226 | dispc_pck_free_enable(0); | |
227 | ||
228 | /* Reset SDI PLL */ | |
229 | REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ | |
230 | } | |
231 | ||
067a57e4 AT |
232 | const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src) |
233 | { | |
234 | return dss_generic_clk_source_names[clk_src].clksrc_name; | |
235 | } | |
236 | ||
559d6701 TV |
237 | void dss_dump_clocks(struct seq_file *s) |
238 | { | |
239 | unsigned long dpll4_ck_rate; | |
240 | unsigned long dpll4_m4_ck_rate; | |
241 | ||
6af9cd14 | 242 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
243 | |
244 | dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | |
245 | dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); | |
246 | ||
247 | seq_printf(s, "- DSS -\n"); | |
248 | ||
249 | seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); | |
250 | ||
ac01bb7e | 251 | if (cpu_is_omap3630()) |
067a57e4 AT |
252 | seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", |
253 | dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), | |
254 | dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), | |
ac01bb7e K |
255 | dpll4_ck_rate, |
256 | dpll4_ck_rate / dpll4_m4_ck_rate, | |
6af9cd14 | 257 | dss_clk_get_rate(DSS_CLK_FCK)); |
ac01bb7e | 258 | else |
067a57e4 AT |
259 | seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", |
260 | dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), | |
261 | dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), | |
559d6701 TV |
262 | dpll4_ck_rate, |
263 | dpll4_ck_rate / dpll4_m4_ck_rate, | |
6af9cd14 | 264 | dss_clk_get_rate(DSS_CLK_FCK)); |
559d6701 | 265 | |
6af9cd14 | 266 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
267 | } |
268 | ||
269 | void dss_dump_regs(struct seq_file *s) | |
270 | { | |
271 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) | |
272 | ||
6af9cd14 | 273 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
274 | |
275 | DUMPREG(DSS_REVISION); | |
276 | DUMPREG(DSS_SYSCONFIG); | |
277 | DUMPREG(DSS_SYSSTATUS); | |
278 | DUMPREG(DSS_IRQSTATUS); | |
279 | DUMPREG(DSS_CONTROL); | |
6ec549e5 TV |
280 | |
281 | if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & | |
282 | OMAP_DISPLAY_TYPE_SDI) { | |
283 | DUMPREG(DSS_SDI_CONTROL); | |
284 | DUMPREG(DSS_PLL_CONTROL); | |
285 | DUMPREG(DSS_SDI_STATUS); | |
286 | } | |
559d6701 | 287 | |
6af9cd14 | 288 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
559d6701 TV |
289 | #undef DUMPREG |
290 | } | |
291 | ||
2f18c4d8 TV |
292 | void dss_select_dispc_clk_source(enum dss_clk_source clk_src) |
293 | { | |
294 | int b; | |
295 | ||
88134fa1 AT |
296 | BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC && |
297 | clk_src != DSS_CLK_SRC_FCK); | |
2f18c4d8 | 298 | |
88134fa1 | 299 | b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; |
2f18c4d8 | 300 | |
88134fa1 | 301 | if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC) |
1bb47835 | 302 | dsi_wait_pll_hsdiv_dispc_active(); |
e406f907 | 303 | |
2f18c4d8 TV |
304 | REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ |
305 | ||
306 | dss.dispc_clk_source = clk_src; | |
307 | } | |
308 | ||
309 | void dss_select_dsi_clk_source(enum dss_clk_source clk_src) | |
559d6701 | 310 | { |
2f18c4d8 TV |
311 | int b; |
312 | ||
88134fa1 AT |
313 | BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI && |
314 | clk_src != DSS_CLK_SRC_FCK); | |
2f18c4d8 | 315 | |
88134fa1 | 316 | b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1; |
2f18c4d8 | 317 | |
88134fa1 | 318 | if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI) |
1bb47835 | 319 | dsi_wait_pll_hsdiv_dsi_active(); |
e406f907 | 320 | |
2f18c4d8 TV |
321 | REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ |
322 | ||
323 | dss.dsi_clk_source = clk_src; | |
559d6701 TV |
324 | } |
325 | ||
2f18c4d8 | 326 | enum dss_clk_source dss_get_dispc_clk_source(void) |
559d6701 | 327 | { |
2f18c4d8 | 328 | return dss.dispc_clk_source; |
559d6701 TV |
329 | } |
330 | ||
2f18c4d8 | 331 | enum dss_clk_source dss_get_dsi_clk_source(void) |
559d6701 | 332 | { |
2f18c4d8 | 333 | return dss.dsi_clk_source; |
559d6701 TV |
334 | } |
335 | ||
336 | /* calculate clock rates using dividers in cinfo */ | |
337 | int dss_calc_clock_rates(struct dss_clock_info *cinfo) | |
338 | { | |
339 | unsigned long prate; | |
340 | ||
ac01bb7e K |
341 | if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) || |
342 | cinfo->fck_div == 0) | |
559d6701 TV |
343 | return -EINVAL; |
344 | ||
345 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | |
346 | ||
347 | cinfo->fck = prate / cinfo->fck_div; | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
352 | int dss_set_clock_div(struct dss_clock_info *cinfo) | |
353 | { | |
354 | unsigned long prate; | |
355 | int r; | |
356 | ||
357 | if (cpu_is_omap34xx()) { | |
358 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | |
359 | DSSDBG("dpll4_m4 = %ld\n", prate); | |
360 | ||
361 | r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div); | |
362 | if (r) | |
363 | return r; | |
364 | } | |
365 | ||
366 | DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); | |
367 | ||
368 | return 0; | |
369 | } | |
370 | ||
371 | int dss_get_clock_div(struct dss_clock_info *cinfo) | |
372 | { | |
6af9cd14 | 373 | cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 TV |
374 | |
375 | if (cpu_is_omap34xx()) { | |
376 | unsigned long prate; | |
377 | prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | |
ac01bb7e K |
378 | if (cpu_is_omap3630()) |
379 | cinfo->fck_div = prate / (cinfo->fck); | |
380 | else | |
381 | cinfo->fck_div = prate / (cinfo->fck / 2); | |
559d6701 TV |
382 | } else { |
383 | cinfo->fck_div = 0; | |
384 | } | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
389 | unsigned long dss_get_dpll4_rate(void) | |
390 | { | |
391 | if (cpu_is_omap34xx()) | |
392 | return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); | |
393 | else | |
394 | return 0; | |
395 | } | |
396 | ||
397 | int dss_calc_clock_div(bool is_tft, unsigned long req_pck, | |
398 | struct dss_clock_info *dss_cinfo, | |
399 | struct dispc_clock_info *dispc_cinfo) | |
400 | { | |
401 | unsigned long prate; | |
402 | struct dss_clock_info best_dss; | |
403 | struct dispc_clock_info best_dispc; | |
404 | ||
819d807c | 405 | unsigned long fck, max_dss_fck; |
559d6701 TV |
406 | |
407 | u16 fck_div; | |
408 | ||
409 | int match = 0; | |
410 | int min_fck_per_pck; | |
411 | ||
412 | prate = dss_get_dpll4_rate(); | |
413 | ||
819d807c AT |
414 | max_dss_fck = dss_feat_get_max_dss_fck(); |
415 | ||
6af9cd14 | 416 | fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 TV |
417 | if (req_pck == dss.cache_req_pck && |
418 | ((cpu_is_omap34xx() && prate == dss.cache_prate) || | |
419 | dss.cache_dss_cinfo.fck == fck)) { | |
420 | DSSDBG("dispc clock info found from cache.\n"); | |
421 | *dss_cinfo = dss.cache_dss_cinfo; | |
422 | *dispc_cinfo = dss.cache_dispc_cinfo; | |
423 | return 0; | |
424 | } | |
425 | ||
426 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
427 | ||
428 | if (min_fck_per_pck && | |
819d807c | 429 | req_pck * min_fck_per_pck > max_dss_fck) { |
559d6701 TV |
430 | DSSERR("Requested pixel clock not possible with the current " |
431 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " | |
432 | "the constraint off.\n"); | |
433 | min_fck_per_pck = 0; | |
434 | } | |
435 | ||
436 | retry: | |
437 | memset(&best_dss, 0, sizeof(best_dss)); | |
438 | memset(&best_dispc, 0, sizeof(best_dispc)); | |
439 | ||
440 | if (cpu_is_omap24xx()) { | |
441 | struct dispc_clock_info cur_dispc; | |
442 | /* XXX can we change the clock on omap2? */ | |
6af9cd14 | 443 | fck = dss_clk_get_rate(DSS_CLK_FCK); |
559d6701 TV |
444 | fck_div = 1; |
445 | ||
446 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); | |
447 | match = 1; | |
448 | ||
449 | best_dss.fck = fck; | |
450 | best_dss.fck_div = fck_div; | |
451 | ||
452 | best_dispc = cur_dispc; | |
453 | ||
454 | goto found; | |
455 | } else if (cpu_is_omap34xx()) { | |
ac01bb7e K |
456 | for (fck_div = (cpu_is_omap3630() ? 32 : 16); |
457 | fck_div > 0; --fck_div) { | |
559d6701 TV |
458 | struct dispc_clock_info cur_dispc; |
459 | ||
ac01bb7e K |
460 | if (cpu_is_omap3630()) |
461 | fck = prate / fck_div; | |
462 | else | |
463 | fck = prate / fck_div * 2; | |
559d6701 | 464 | |
819d807c | 465 | if (fck > max_dss_fck) |
559d6701 TV |
466 | continue; |
467 | ||
468 | if (min_fck_per_pck && | |
469 | fck < req_pck * min_fck_per_pck) | |
470 | continue; | |
471 | ||
472 | match = 1; | |
473 | ||
474 | dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); | |
475 | ||
476 | if (abs(cur_dispc.pck - req_pck) < | |
477 | abs(best_dispc.pck - req_pck)) { | |
478 | ||
479 | best_dss.fck = fck; | |
480 | best_dss.fck_div = fck_div; | |
481 | ||
482 | best_dispc = cur_dispc; | |
483 | ||
484 | if (cur_dispc.pck == req_pck) | |
485 | goto found; | |
486 | } | |
487 | } | |
488 | } else { | |
489 | BUG(); | |
490 | } | |
491 | ||
492 | found: | |
493 | if (!match) { | |
494 | if (min_fck_per_pck) { | |
495 | DSSERR("Could not find suitable clock settings.\n" | |
496 | "Turning FCK/PCK constraint off and" | |
497 | "trying again.\n"); | |
498 | min_fck_per_pck = 0; | |
499 | goto retry; | |
500 | } | |
501 | ||
502 | DSSERR("Could not find suitable clock settings.\n"); | |
503 | ||
504 | return -EINVAL; | |
505 | } | |
506 | ||
507 | if (dss_cinfo) | |
508 | *dss_cinfo = best_dss; | |
509 | if (dispc_cinfo) | |
510 | *dispc_cinfo = best_dispc; | |
511 | ||
512 | dss.cache_req_pck = req_pck; | |
513 | dss.cache_prate = prate; | |
514 | dss.cache_dss_cinfo = best_dss; | |
515 | dss.cache_dispc_cinfo = best_dispc; | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
559d6701 TV |
520 | static int _omap_dss_wait_reset(void) |
521 | { | |
24be78b3 | 522 | int t = 0; |
559d6701 TV |
523 | |
524 | while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) { | |
24be78b3 | 525 | if (++t > 1000) { |
559d6701 TV |
526 | DSSERR("soft reset failed\n"); |
527 | return -ENODEV; | |
528 | } | |
24be78b3 | 529 | udelay(1); |
559d6701 TV |
530 | } |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static int _omap_dss_reset(void) | |
536 | { | |
537 | /* Soft reset */ | |
538 | REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1); | |
539 | return _omap_dss_wait_reset(); | |
540 | } | |
541 | ||
542 | void dss_set_venc_output(enum omap_dss_venc_type type) | |
543 | { | |
544 | int l = 0; | |
545 | ||
546 | if (type == OMAP_DSS_VENC_TYPE_COMPOSITE) | |
547 | l = 0; | |
548 | else if (type == OMAP_DSS_VENC_TYPE_SVIDEO) | |
549 | l = 1; | |
550 | else | |
551 | BUG(); | |
552 | ||
553 | /* venc out selection. 0 = comp, 1 = svideo */ | |
554 | REG_FLD_MOD(DSS_CONTROL, l, 6, 6); | |
555 | } | |
556 | ||
557 | void dss_set_dac_pwrdn_bgz(bool enable) | |
558 | { | |
559 | REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ | |
560 | } | |
561 | ||
42c9dee8 | 562 | static int dss_init(void) |
559d6701 TV |
563 | { |
564 | int r; | |
565 | u32 rev; | |
ea9da36a | 566 | struct resource *dss_mem; |
559d6701 | 567 | |
ea9da36a SG |
568 | dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); |
569 | if (!dss_mem) { | |
570 | DSSERR("can't get IORESOURCE_MEM DSS\n"); | |
571 | r = -EINVAL; | |
572 | goto fail0; | |
573 | } | |
574 | dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); | |
559d6701 TV |
575 | if (!dss.base) { |
576 | DSSERR("can't ioremap DSS\n"); | |
577 | r = -ENOMEM; | |
578 | goto fail0; | |
579 | } | |
580 | ||
42c9dee8 TV |
581 | /* disable LCD and DIGIT output. This seems to fix the synclost |
582 | * problem that we get, if the bootloader starts the DSS and | |
583 | * the kernel resets it */ | |
584 | omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); | |
585 | ||
586 | /* We need to wait here a bit, otherwise we sometimes start to | |
587 | * get synclost errors, and after that only power cycle will | |
588 | * restore DSS functionality. I have no idea why this happens. | |
589 | * And we have to wait _before_ resetting the DSS, but after | |
590 | * enabling clocks. | |
591 | */ | |
592 | msleep(50); | |
593 | ||
594 | _omap_dss_reset(); | |
559d6701 TV |
595 | |
596 | /* autoidle */ | |
597 | REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); | |
598 | ||
599 | /* Select DPLL */ | |
600 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); | |
601 | ||
602 | #ifdef CONFIG_OMAP2_DSS_VENC | |
603 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ | |
604 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ | |
605 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ | |
606 | #endif | |
607 | ||
559d6701 TV |
608 | if (cpu_is_omap34xx()) { |
609 | dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); | |
610 | if (IS_ERR(dss.dpll4_m4_ck)) { | |
611 | DSSERR("Failed to get dpll4_m4_ck\n"); | |
612 | r = PTR_ERR(dss.dpll4_m4_ck); | |
affe360d | 613 | goto fail1; |
559d6701 TV |
614 | } |
615 | } | |
616 | ||
88134fa1 AT |
617 | dss.dsi_clk_source = DSS_CLK_SRC_FCK; |
618 | dss.dispc_clk_source = DSS_CLK_SRC_FCK; | |
ce619e1f | 619 | |
559d6701 TV |
620 | dss_save_context(); |
621 | ||
622 | rev = dss_read_reg(DSS_REVISION); | |
623 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", | |
624 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
625 | ||
626 | return 0; | |
627 | ||
559d6701 TV |
628 | fail1: |
629 | iounmap(dss.base); | |
630 | fail0: | |
631 | return r; | |
632 | } | |
633 | ||
96c401bc | 634 | static void dss_exit(void) |
559d6701 TV |
635 | { |
636 | if (cpu_is_omap34xx()) | |
637 | clk_put(dss.dpll4_m4_ck); | |
638 | ||
559d6701 TV |
639 | iounmap(dss.base); |
640 | } | |
641 | ||
8b9cb3a8 SG |
642 | /* CONTEXT */ |
643 | static int dss_get_ctx_id(void) | |
644 | { | |
645 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; | |
646 | int r; | |
647 | ||
648 | if (!pdata->board_data->get_last_off_on_transaction_id) | |
649 | return 0; | |
650 | r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev); | |
651 | if (r < 0) { | |
652 | dev_err(&dss.pdev->dev, "getting transaction ID failed, " | |
653 | "will force context restore\n"); | |
654 | r = -1; | |
655 | } | |
656 | return r; | |
657 | } | |
658 | ||
659 | int dss_need_ctx_restore(void) | |
660 | { | |
661 | int id = dss_get_ctx_id(); | |
662 | ||
663 | if (id < 0 || id != dss.ctx_id) { | |
664 | DSSDBG("ctx id %d -> id %d\n", | |
665 | dss.ctx_id, id); | |
666 | dss.ctx_id = id; | |
667 | return 1; | |
668 | } else { | |
669 | return 0; | |
670 | } | |
671 | } | |
672 | ||
673 | static void save_all_ctx(void) | |
674 | { | |
675 | DSSDBG("save context\n"); | |
676 | ||
6af9cd14 | 677 | dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); |
8b9cb3a8 SG |
678 | |
679 | dss_save_context(); | |
680 | dispc_save_context(); | |
681 | #ifdef CONFIG_OMAP2_DSS_DSI | |
682 | dsi_save_context(); | |
683 | #endif | |
684 | ||
6af9cd14 | 685 | dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); |
8b9cb3a8 SG |
686 | } |
687 | ||
688 | static void restore_all_ctx(void) | |
689 | { | |
690 | DSSDBG("restore context\n"); | |
691 | ||
692 | dss_clk_enable_all_no_ctx(); | |
693 | ||
694 | dss_restore_context(); | |
695 | dispc_restore_context(); | |
696 | #ifdef CONFIG_OMAP2_DSS_DSI | |
697 | dsi_restore_context(); | |
698 | #endif | |
699 | ||
700 | dss_clk_disable_all_no_ctx(); | |
701 | } | |
702 | ||
703 | static int dss_get_clock(struct clk **clock, const char *clk_name) | |
704 | { | |
705 | struct clk *clk; | |
706 | ||
707 | clk = clk_get(&dss.pdev->dev, clk_name); | |
708 | ||
709 | if (IS_ERR(clk)) { | |
710 | DSSERR("can't get clock %s", clk_name); | |
711 | return PTR_ERR(clk); | |
712 | } | |
713 | ||
714 | *clock = clk; | |
715 | ||
716 | DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
721 | static int dss_get_clocks(void) | |
722 | { | |
723 | int r; | |
a1a0dcca | 724 | struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; |
8b9cb3a8 SG |
725 | |
726 | dss.dss_ick = NULL; | |
c7642f67 AT |
727 | dss.dss_fck = NULL; |
728 | dss.dss_sys_clk = NULL; | |
729 | dss.dss_tv_fck = NULL; | |
730 | dss.dss_video_fck = NULL; | |
8b9cb3a8 SG |
731 | |
732 | r = dss_get_clock(&dss.dss_ick, "ick"); | |
733 | if (r) | |
734 | goto err; | |
735 | ||
c7642f67 | 736 | r = dss_get_clock(&dss.dss_fck, "fck"); |
8b9cb3a8 SG |
737 | if (r) |
738 | goto err; | |
739 | ||
a1a0dcca SS |
740 | if (!pdata->opt_clock_available) { |
741 | r = -ENODEV; | |
8b9cb3a8 | 742 | goto err; |
a1a0dcca | 743 | } |
8b9cb3a8 | 744 | |
a1a0dcca SS |
745 | if (pdata->opt_clock_available("sys_clk")) { |
746 | r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); | |
747 | if (r) | |
748 | goto err; | |
749 | } | |
8b9cb3a8 | 750 | |
a1a0dcca SS |
751 | if (pdata->opt_clock_available("tv_clk")) { |
752 | r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); | |
753 | if (r) | |
754 | goto err; | |
755 | } | |
756 | ||
757 | if (pdata->opt_clock_available("video_clk")) { | |
758 | r = dss_get_clock(&dss.dss_video_fck, "video_clk"); | |
759 | if (r) | |
760 | goto err; | |
761 | } | |
8b9cb3a8 SG |
762 | |
763 | return 0; | |
764 | ||
765 | err: | |
766 | if (dss.dss_ick) | |
767 | clk_put(dss.dss_ick); | |
c7642f67 AT |
768 | if (dss.dss_fck) |
769 | clk_put(dss.dss_fck); | |
770 | if (dss.dss_sys_clk) | |
771 | clk_put(dss.dss_sys_clk); | |
772 | if (dss.dss_tv_fck) | |
773 | clk_put(dss.dss_tv_fck); | |
774 | if (dss.dss_video_fck) | |
775 | clk_put(dss.dss_video_fck); | |
8b9cb3a8 SG |
776 | |
777 | return r; | |
778 | } | |
779 | ||
780 | static void dss_put_clocks(void) | |
781 | { | |
c7642f67 AT |
782 | if (dss.dss_video_fck) |
783 | clk_put(dss.dss_video_fck); | |
a1a0dcca SS |
784 | if (dss.dss_tv_fck) |
785 | clk_put(dss.dss_tv_fck); | |
786 | if (dss.dss_sys_clk) | |
787 | clk_put(dss.dss_sys_clk); | |
c7642f67 | 788 | clk_put(dss.dss_fck); |
8b9cb3a8 SG |
789 | clk_put(dss.dss_ick); |
790 | } | |
791 | ||
792 | unsigned long dss_clk_get_rate(enum dss_clock clk) | |
793 | { | |
794 | switch (clk) { | |
795 | case DSS_CLK_ICK: | |
796 | return clk_get_rate(dss.dss_ick); | |
6af9cd14 | 797 | case DSS_CLK_FCK: |
c7642f67 | 798 | return clk_get_rate(dss.dss_fck); |
6af9cd14 | 799 | case DSS_CLK_SYSCK: |
c7642f67 | 800 | return clk_get_rate(dss.dss_sys_clk); |
6af9cd14 | 801 | case DSS_CLK_TVFCK: |
c7642f67 | 802 | return clk_get_rate(dss.dss_tv_fck); |
6af9cd14 | 803 | case DSS_CLK_VIDFCK: |
c7642f67 | 804 | return clk_get_rate(dss.dss_video_fck); |
8b9cb3a8 SG |
805 | } |
806 | ||
807 | BUG(); | |
808 | return 0; | |
809 | } | |
810 | ||
811 | static unsigned count_clk_bits(enum dss_clock clks) | |
812 | { | |
813 | unsigned num_clks = 0; | |
814 | ||
815 | if (clks & DSS_CLK_ICK) | |
816 | ++num_clks; | |
6af9cd14 | 817 | if (clks & DSS_CLK_FCK) |
8b9cb3a8 | 818 | ++num_clks; |
6af9cd14 | 819 | if (clks & DSS_CLK_SYSCK) |
8b9cb3a8 | 820 | ++num_clks; |
6af9cd14 | 821 | if (clks & DSS_CLK_TVFCK) |
8b9cb3a8 | 822 | ++num_clks; |
6af9cd14 | 823 | if (clks & DSS_CLK_VIDFCK) |
8b9cb3a8 SG |
824 | ++num_clks; |
825 | ||
826 | return num_clks; | |
827 | } | |
828 | ||
829 | static void dss_clk_enable_no_ctx(enum dss_clock clks) | |
830 | { | |
831 | unsigned num_clks = count_clk_bits(clks); | |
832 | ||
833 | if (clks & DSS_CLK_ICK) | |
834 | clk_enable(dss.dss_ick); | |
6af9cd14 | 835 | if (clks & DSS_CLK_FCK) |
c7642f67 | 836 | clk_enable(dss.dss_fck); |
a1a0dcca | 837 | if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) |
c7642f67 | 838 | clk_enable(dss.dss_sys_clk); |
a1a0dcca | 839 | if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) |
c7642f67 | 840 | clk_enable(dss.dss_tv_fck); |
a1a0dcca | 841 | if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) |
c7642f67 | 842 | clk_enable(dss.dss_video_fck); |
8b9cb3a8 SG |
843 | |
844 | dss.num_clks_enabled += num_clks; | |
845 | } | |
846 | ||
847 | void dss_clk_enable(enum dss_clock clks) | |
848 | { | |
849 | bool check_ctx = dss.num_clks_enabled == 0; | |
850 | ||
851 | dss_clk_enable_no_ctx(clks); | |
852 | ||
85604b0a TV |
853 | /* |
854 | * HACK: On omap4 the registers may not be accessible right after | |
855 | * enabling the clocks. At some point this will be handled by | |
856 | * pm_runtime, but for the time begin this should make things work. | |
857 | */ | |
858 | if (cpu_is_omap44xx() && check_ctx) | |
859 | udelay(10); | |
860 | ||
8b9cb3a8 SG |
861 | if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) |
862 | restore_all_ctx(); | |
863 | } | |
864 | ||
865 | static void dss_clk_disable_no_ctx(enum dss_clock clks) | |
866 | { | |
867 | unsigned num_clks = count_clk_bits(clks); | |
868 | ||
869 | if (clks & DSS_CLK_ICK) | |
870 | clk_disable(dss.dss_ick); | |
6af9cd14 | 871 | if (clks & DSS_CLK_FCK) |
c7642f67 | 872 | clk_disable(dss.dss_fck); |
a1a0dcca | 873 | if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) |
c7642f67 | 874 | clk_disable(dss.dss_sys_clk); |
a1a0dcca | 875 | if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) |
c7642f67 | 876 | clk_disable(dss.dss_tv_fck); |
a1a0dcca | 877 | if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) |
c7642f67 | 878 | clk_disable(dss.dss_video_fck); |
8b9cb3a8 SG |
879 | |
880 | dss.num_clks_enabled -= num_clks; | |
881 | } | |
882 | ||
883 | void dss_clk_disable(enum dss_clock clks) | |
884 | { | |
885 | if (cpu_is_omap34xx()) { | |
886 | unsigned num_clks = count_clk_bits(clks); | |
887 | ||
888 | BUG_ON(dss.num_clks_enabled < num_clks); | |
889 | ||
890 | if (dss.num_clks_enabled == num_clks) | |
891 | save_all_ctx(); | |
892 | } | |
893 | ||
894 | dss_clk_disable_no_ctx(clks); | |
895 | } | |
896 | ||
897 | static void dss_clk_enable_all_no_ctx(void) | |
898 | { | |
899 | enum dss_clock clks; | |
900 | ||
6af9cd14 | 901 | clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; |
8b9cb3a8 | 902 | if (cpu_is_omap34xx()) |
6af9cd14 | 903 | clks |= DSS_CLK_VIDFCK; |
8b9cb3a8 SG |
904 | dss_clk_enable_no_ctx(clks); |
905 | } | |
906 | ||
907 | static void dss_clk_disable_all_no_ctx(void) | |
908 | { | |
909 | enum dss_clock clks; | |
910 | ||
6af9cd14 | 911 | clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; |
8b9cb3a8 | 912 | if (cpu_is_omap34xx()) |
6af9cd14 | 913 | clks |= DSS_CLK_VIDFCK; |
8b9cb3a8 SG |
914 | dss_clk_disable_no_ctx(clks); |
915 | } | |
916 | ||
917 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
918 | /* CLOCKS */ | |
919 | static void core_dump_clocks(struct seq_file *s) | |
920 | { | |
921 | int i; | |
922 | struct clk *clocks[5] = { | |
923 | dss.dss_ick, | |
c7642f67 AT |
924 | dss.dss_fck, |
925 | dss.dss_sys_clk, | |
926 | dss.dss_tv_fck, | |
927 | dss.dss_video_fck | |
8b9cb3a8 SG |
928 | }; |
929 | ||
930 | seq_printf(s, "- CORE -\n"); | |
931 | ||
932 | seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled); | |
933 | ||
934 | for (i = 0; i < 5; i++) { | |
935 | if (!clocks[i]) | |
936 | continue; | |
937 | seq_printf(s, "%-15s\t%lu\t%d\n", | |
938 | clocks[i]->name, | |
939 | clk_get_rate(clocks[i]), | |
940 | clocks[i]->usecount); | |
941 | } | |
942 | } | |
943 | #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ | |
944 | ||
945 | /* DEBUGFS */ | |
946 | #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) | |
947 | void dss_debug_dump_clocks(struct seq_file *s) | |
948 | { | |
949 | core_dump_clocks(s); | |
950 | dss_dump_clocks(s); | |
951 | dispc_dump_clocks(s); | |
952 | #ifdef CONFIG_OMAP2_DSS_DSI | |
953 | dsi_dump_clocks(s); | |
954 | #endif | |
955 | } | |
956 | #endif | |
957 | ||
958 | ||
96c401bc SG |
959 | /* DSS HW IP initialisation */ |
960 | static int omap_dsshw_probe(struct platform_device *pdev) | |
961 | { | |
962 | int r; | |
96c401bc SG |
963 | |
964 | dss.pdev = pdev; | |
965 | ||
8b9cb3a8 SG |
966 | r = dss_get_clocks(); |
967 | if (r) | |
968 | goto err_clocks; | |
969 | ||
970 | dss_clk_enable_all_no_ctx(); | |
971 | ||
972 | dss.ctx_id = dss_get_ctx_id(); | |
973 | DSSDBG("initial ctx id %u\n", dss.ctx_id); | |
974 | ||
42c9dee8 | 975 | r = dss_init(); |
96c401bc SG |
976 | if (r) { |
977 | DSSERR("Failed to initialize DSS\n"); | |
978 | goto err_dss; | |
979 | } | |
980 | ||
587b5e82 TV |
981 | r = dpi_init(); |
982 | if (r) { | |
983 | DSSERR("Failed to initialize DPI\n"); | |
984 | goto err_dpi; | |
985 | } | |
986 | ||
987 | r = sdi_init(); | |
988 | if (r) { | |
989 | DSSERR("Failed to initialize SDI\n"); | |
990 | goto err_sdi; | |
991 | } | |
992 | ||
8b9cb3a8 SG |
993 | dss_clk_disable_all_no_ctx(); |
994 | return 0; | |
587b5e82 TV |
995 | err_sdi: |
996 | dpi_exit(); | |
997 | err_dpi: | |
998 | dss_exit(); | |
8b9cb3a8 SG |
999 | err_dss: |
1000 | dss_clk_disable_all_no_ctx(); | |
1001 | dss_put_clocks(); | |
1002 | err_clocks: | |
96c401bc SG |
1003 | return r; |
1004 | } | |
1005 | ||
1006 | static int omap_dsshw_remove(struct platform_device *pdev) | |
1007 | { | |
8b9cb3a8 | 1008 | |
96c401bc SG |
1009 | dss_exit(); |
1010 | ||
8b9cb3a8 SG |
1011 | /* |
1012 | * As part of hwmod changes, DSS is not the only controller of dss | |
1013 | * clocks; hwmod framework itself will also enable clocks during hwmod | |
1014 | * init for dss, and autoidle is set in h/w for DSS. Hence, there's no | |
1015 | * need to disable clocks if their usecounts > 1. | |
1016 | */ | |
1017 | WARN_ON(dss.num_clks_enabled > 0); | |
1018 | ||
1019 | dss_put_clocks(); | |
96c401bc SG |
1020 | return 0; |
1021 | } | |
1022 | ||
1023 | static struct platform_driver omap_dsshw_driver = { | |
1024 | .probe = omap_dsshw_probe, | |
1025 | .remove = omap_dsshw_remove, | |
1026 | .driver = { | |
1027 | .name = "omapdss_dss", | |
1028 | .owner = THIS_MODULE, | |
1029 | }, | |
1030 | }; | |
1031 | ||
1032 | int dss_init_platform_driver(void) | |
1033 | { | |
1034 | return platform_driver_register(&omap_dsshw_driver); | |
1035 | } | |
1036 | ||
1037 | void dss_uninit_platform_driver(void) | |
1038 | { | |
1039 | return platform_driver_unregister(&omap_dsshw_driver); | |
1040 | } |